1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 clkstat: CLKSTAT,
5 clkset: CLKSET,
6 clkclr: CLKCLR,
7 sysclkcr: SYSCLKCR,
8 cpuclkcr: CPUCLKCR,
9 pbclkcr: PBCLKCR,
10 usbclkcr: USBCLKCR,
11 _reserved7: [u8; 0x04],
12 ccuclkcr: CCUCLKCR,
13 wdtclkcr: WDTCLKCR,
14 extclkcr: EXTCLKCR,
15 mlinkclkcr: MLINKCLKCR,
16 sleepcr: SLEEPCR,
17 dsleepcr: DSLEEPCR,
18 _reserved13: [u8; 0x08],
19 cgatstat0: CGATSTAT0,
20 cgatset0: CGATSET0,
21 cgatclr0: CGATCLR0,
22 cgatstat1: CGATSTAT1,
23 cgatset1: CGATSET1,
24 cgatclr1: CGATCLR1,
25 cgatstat2: CGATSTAT2,
26 cgatset2: CGATSET2,
27 cgatclr2: CGATCLR2,
28}
29impl RegisterBlock {
30 #[doc = "0x00 - Clock Status Register"]
31 #[inline(always)]
32 pub const fn clkstat(&self) -> &CLKSTAT {
33 &self.clkstat
34 }
35 #[doc = "0x04 - CLK Set Register"]
36 #[inline(always)]
37 pub const fn clkset(&self) -> &CLKSET {
38 &self.clkset
39 }
40 #[doc = "0x08 - CLK Clear Register"]
41 #[inline(always)]
42 pub const fn clkclr(&self) -> &CLKCLR {
43 &self.clkclr
44 }
45 #[doc = "0x0c - System Clock Control Register"]
46 #[inline(always)]
47 pub const fn sysclkcr(&self) -> &SYSCLKCR {
48 &self.sysclkcr
49 }
50 #[doc = "0x10 - CPU Clock Control Register"]
51 #[inline(always)]
52 pub const fn cpuclkcr(&self) -> &CPUCLKCR {
53 &self.cpuclkcr
54 }
55 #[doc = "0x14 - Peripheral Bus Clock Control Register"]
56 #[inline(always)]
57 pub const fn pbclkcr(&self) -> &PBCLKCR {
58 &self.pbclkcr
59 }
60 #[doc = "0x18 - USB Clock Control Register"]
61 #[inline(always)]
62 pub const fn usbclkcr(&self) -> &USBCLKCR {
63 &self.usbclkcr
64 }
65 #[doc = "0x20 - CCU Clock Control Register"]
66 #[inline(always)]
67 pub const fn ccuclkcr(&self) -> &CCUCLKCR {
68 &self.ccuclkcr
69 }
70 #[doc = "0x24 - WDT Clock Control Register"]
71 #[inline(always)]
72 pub const fn wdtclkcr(&self) -> &WDTCLKCR {
73 &self.wdtclkcr
74 }
75 #[doc = "0x28 - External Clock Control"]
76 #[inline(always)]
77 pub const fn extclkcr(&self) -> &EXTCLKCR {
78 &self.extclkcr
79 }
80 #[doc = "0x2c - Multi-Link Clock Control"]
81 #[inline(always)]
82 pub const fn mlinkclkcr(&self) -> &MLINKCLKCR {
83 &self.mlinkclkcr
84 }
85 #[doc = "0x30 - Sleep Control Register"]
86 #[inline(always)]
87 pub const fn sleepcr(&self) -> &SLEEPCR {
88 &self.sleepcr
89 }
90 #[doc = "0x34 - Deep Sleep Control Register"]
91 #[inline(always)]
92 pub const fn dsleepcr(&self) -> &DSLEEPCR {
93 &self.dsleepcr
94 }
95 #[doc = "0x40 - Peripheral 0 Clock Gating Status"]
96 #[inline(always)]
97 pub const fn cgatstat0(&self) -> &CGATSTAT0 {
98 &self.cgatstat0
99 }
100 #[doc = "0x44 - Peripheral 0 Clock Gating Set"]
101 #[inline(always)]
102 pub const fn cgatset0(&self) -> &CGATSET0 {
103 &self.cgatset0
104 }
105 #[doc = "0x48 - Peripheral 0 Clock Gating Clear"]
106 #[inline(always)]
107 pub const fn cgatclr0(&self) -> &CGATCLR0 {
108 &self.cgatclr0
109 }
110 #[doc = "0x4c - Peripheral 1 Clock Gating Status"]
111 #[inline(always)]
112 pub const fn cgatstat1(&self) -> &CGATSTAT1 {
113 &self.cgatstat1
114 }
115 #[doc = "0x50 - Peripheral 1 Clock Gating Set"]
116 #[inline(always)]
117 pub const fn cgatset1(&self) -> &CGATSET1 {
118 &self.cgatset1
119 }
120 #[doc = "0x54 - Peripheral 1 Clock Gating Clear"]
121 #[inline(always)]
122 pub const fn cgatclr1(&self) -> &CGATCLR1 {
123 &self.cgatclr1
124 }
125 #[doc = "0x58 - Peripheral 2 Clock Gating Status"]
126 #[inline(always)]
127 pub const fn cgatstat2(&self) -> &CGATSTAT2 {
128 &self.cgatstat2
129 }
130 #[doc = "0x5c - Peripheral 2 Clock Gating Set"]
131 #[inline(always)]
132 pub const fn cgatset2(&self) -> &CGATSET2 {
133 &self.cgatset2
134 }
135 #[doc = "0x60 - Peripheral 2 Clock Gating Clear"]
136 #[inline(always)]
137 pub const fn cgatclr2(&self) -> &CGATCLR2 {
138 &self.cgatclr2
139 }
140}
141#[doc = "CLKSTAT (r) register accessor: Clock Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkstat`]
142module"]
143pub type CLKSTAT = crate::Reg<clkstat::CLKSTAT_SPEC>;
144#[doc = "Clock Status Register"]
145pub mod clkstat;
146#[doc = "CLKSET (w) register accessor: CLK Set Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkset`]
147module"]
148pub type CLKSET = crate::Reg<clkset::CLKSET_SPEC>;
149#[doc = "CLK Set Register"]
150pub mod clkset;
151#[doc = "CLKCLR (w) register accessor: CLK Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkclr`]
152module"]
153pub type CLKCLR = crate::Reg<clkclr::CLKCLR_SPEC>;
154#[doc = "CLK Clear Register"]
155pub mod clkclr;
156#[doc = "SYSCLKCR (rw) register accessor: System Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sysclkcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysclkcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysclkcr`]
157module"]
158pub type SYSCLKCR = crate::Reg<sysclkcr::SYSCLKCR_SPEC>;
159#[doc = "System Clock Control Register"]
160pub mod sysclkcr;
161#[doc = "CPUCLKCR (rw) register accessor: CPU Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cpuclkcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpuclkcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpuclkcr`]
162module"]
163pub type CPUCLKCR = crate::Reg<cpuclkcr::CPUCLKCR_SPEC>;
164#[doc = "CPU Clock Control Register"]
165pub mod cpuclkcr;
166#[doc = "PBCLKCR (rw) register accessor: Peripheral Bus Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pbclkcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbclkcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbclkcr`]
167module"]
168pub type PBCLKCR = crate::Reg<pbclkcr::PBCLKCR_SPEC>;
169#[doc = "Peripheral Bus Clock Control Register"]
170pub mod pbclkcr;
171#[doc = "USBCLKCR (rw) register accessor: USB Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`usbclkcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbclkcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbclkcr`]
172module"]
173pub type USBCLKCR = crate::Reg<usbclkcr::USBCLKCR_SPEC>;
174#[doc = "USB Clock Control Register"]
175pub mod usbclkcr;
176#[doc = "CCUCLKCR (rw) register accessor: CCU Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccuclkcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccuclkcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccuclkcr`]
177module"]
178pub type CCUCLKCR = crate::Reg<ccuclkcr::CCUCLKCR_SPEC>;
179#[doc = "CCU Clock Control Register"]
180pub mod ccuclkcr;
181#[doc = "WDTCLKCR (rw) register accessor: WDT Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtclkcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtclkcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtclkcr`]
182module"]
183pub type WDTCLKCR = crate::Reg<wdtclkcr::WDTCLKCR_SPEC>;
184#[doc = "WDT Clock Control Register"]
185pub mod wdtclkcr;
186#[doc = "EXTCLKCR (rw) register accessor: External Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`extclkcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extclkcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extclkcr`]
187module"]
188pub type EXTCLKCR = crate::Reg<extclkcr::EXTCLKCR_SPEC>;
189#[doc = "External Clock Control"]
190pub mod extclkcr;
191#[doc = "MLINKCLKCR (rw) register accessor: Multi-Link Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mlinkclkcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mlinkclkcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mlinkclkcr`]
192module"]
193pub type MLINKCLKCR = crate::Reg<mlinkclkcr::MLINKCLKCR_SPEC>;
194#[doc = "Multi-Link Clock Control"]
195pub mod mlinkclkcr;
196#[doc = "SLEEPCR (rw) register accessor: Sleep Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sleepcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleepcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleepcr`]
197module"]
198pub type SLEEPCR = crate::Reg<sleepcr::SLEEPCR_SPEC>;
199#[doc = "Sleep Control Register"]
200pub mod sleepcr;
201#[doc = "DSLEEPCR (rw) register accessor: Deep Sleep Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dsleepcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dsleepcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsleepcr`]
202module"]
203pub type DSLEEPCR = crate::Reg<dsleepcr::DSLEEPCR_SPEC>;
204#[doc = "Deep Sleep Control Register"]
205pub mod dsleepcr;
206#[doc = "CGATSTAT0 (r) register accessor: Peripheral 0 Clock Gating Status\n\nYou can [`read`](crate::Reg::read) this register and get [`cgatstat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgatstat0`]
207module"]
208pub type CGATSTAT0 = crate::Reg<cgatstat0::CGATSTAT0_SPEC>;
209#[doc = "Peripheral 0 Clock Gating Status"]
210pub mod cgatstat0;
211#[doc = "CGATSET0 (w) register accessor: Peripheral 0 Clock Gating Set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cgatset0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgatset0`]
212module"]
213pub type CGATSET0 = crate::Reg<cgatset0::CGATSET0_SPEC>;
214#[doc = "Peripheral 0 Clock Gating Set"]
215pub mod cgatset0;
216#[doc = "CGATCLR0 (w) register accessor: Peripheral 0 Clock Gating Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cgatclr0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgatclr0`]
217module"]
218pub type CGATCLR0 = crate::Reg<cgatclr0::CGATCLR0_SPEC>;
219#[doc = "Peripheral 0 Clock Gating Clear"]
220pub mod cgatclr0;
221#[doc = "CGATSTAT1 (r) register accessor: Peripheral 1 Clock Gating Status\n\nYou can [`read`](crate::Reg::read) this register and get [`cgatstat1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgatstat1`]
222module"]
223pub type CGATSTAT1 = crate::Reg<cgatstat1::CGATSTAT1_SPEC>;
224#[doc = "Peripheral 1 Clock Gating Status"]
225pub mod cgatstat1;
226#[doc = "CGATSET1 (w) register accessor: Peripheral 1 Clock Gating Set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cgatset1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgatset1`]
227module"]
228pub type CGATSET1 = crate::Reg<cgatset1::CGATSET1_SPEC>;
229#[doc = "Peripheral 1 Clock Gating Set"]
230pub mod cgatset1;
231#[doc = "CGATCLR1 (w) register accessor: Peripheral 1 Clock Gating Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cgatclr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgatclr1`]
232module"]
233pub type CGATCLR1 = crate::Reg<cgatclr1::CGATCLR1_SPEC>;
234#[doc = "Peripheral 1 Clock Gating Clear"]
235pub mod cgatclr1;
236#[doc = "CGATSTAT2 (r) register accessor: Peripheral 2 Clock Gating Status\n\nYou can [`read`](crate::Reg::read) this register and get [`cgatstat2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgatstat2`]
237module"]
238pub type CGATSTAT2 = crate::Reg<cgatstat2::CGATSTAT2_SPEC>;
239#[doc = "Peripheral 2 Clock Gating Status"]
240pub mod cgatstat2;
241#[doc = "CGATSET2 (w) register accessor: Peripheral 2 Clock Gating Set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cgatset2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgatset2`]
242module"]
243pub type CGATSET2 = crate::Reg<cgatset2::CGATSET2_SPEC>;
244#[doc = "Peripheral 2 Clock Gating Set"]
245pub mod cgatset2;
246#[doc = "CGATCLR2 (w) register accessor: Peripheral 2 Clock Gating Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cgatclr2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgatclr2`]
247module"]
248pub type CGATCLR2 = crate::Reg<cgatclr2::CGATCLR2_SPEC>;
249#[doc = "Peripheral 2 Clock Gating Clear"]
250pub mod cgatclr2;