xmc4200/ccu80_cc80/
psl.rs

1#[doc = "Register `PSL` reader"]
2pub type R = crate::R<PSL_SPEC>;
3#[doc = "Register `PSL` writer"]
4pub type W = crate::W<PSL_SPEC>;
5#[doc = "Output Passive Level for CCU8x.OUTy0\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum PSL11_A {
8    #[doc = "0: Passive Level is LOW"]
9    VALUE1 = 0,
10    #[doc = "1: Passive Level is HIGH"]
11    VALUE2 = 1,
12}
13impl From<PSL11_A> for bool {
14    #[inline(always)]
15    fn from(variant: PSL11_A) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `PSL11` reader - Output Passive Level for CCU8x.OUTy0"]
20pub type PSL11_R = crate::BitReader<PSL11_A>;
21impl PSL11_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> PSL11_A {
25        match self.bits {
26            false => PSL11_A::VALUE1,
27            true => PSL11_A::VALUE2,
28        }
29    }
30    #[doc = "Passive Level is LOW"]
31    #[inline(always)]
32    pub fn is_value1(&self) -> bool {
33        *self == PSL11_A::VALUE1
34    }
35    #[doc = "Passive Level is HIGH"]
36    #[inline(always)]
37    pub fn is_value2(&self) -> bool {
38        *self == PSL11_A::VALUE2
39    }
40}
41#[doc = "Field `PSL11` writer - Output Passive Level for CCU8x.OUTy0"]
42pub type PSL11_W<'a, REG> = crate::BitWriter<'a, REG, PSL11_A>;
43impl<'a, REG> PSL11_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Passive Level is LOW"]
48    #[inline(always)]
49    pub fn value1(self) -> &'a mut crate::W<REG> {
50        self.variant(PSL11_A::VALUE1)
51    }
52    #[doc = "Passive Level is HIGH"]
53    #[inline(always)]
54    pub fn value2(self) -> &'a mut crate::W<REG> {
55        self.variant(PSL11_A::VALUE2)
56    }
57}
58#[doc = "Output Passive Level for CCU8x.OUTy1\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum PSL12_A {
61    #[doc = "0: Passive Level is LOW"]
62    VALUE1 = 0,
63    #[doc = "1: Passive Level is HIGH"]
64    VALUE2 = 1,
65}
66impl From<PSL12_A> for bool {
67    #[inline(always)]
68    fn from(variant: PSL12_A) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `PSL12` reader - Output Passive Level for CCU8x.OUTy1"]
73pub type PSL12_R = crate::BitReader<PSL12_A>;
74impl PSL12_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> PSL12_A {
78        match self.bits {
79            false => PSL12_A::VALUE1,
80            true => PSL12_A::VALUE2,
81        }
82    }
83    #[doc = "Passive Level is LOW"]
84    #[inline(always)]
85    pub fn is_value1(&self) -> bool {
86        *self == PSL12_A::VALUE1
87    }
88    #[doc = "Passive Level is HIGH"]
89    #[inline(always)]
90    pub fn is_value2(&self) -> bool {
91        *self == PSL12_A::VALUE2
92    }
93}
94#[doc = "Field `PSL12` writer - Output Passive Level for CCU8x.OUTy1"]
95pub type PSL12_W<'a, REG> = crate::BitWriter<'a, REG, PSL12_A>;
96impl<'a, REG> PSL12_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Passive Level is LOW"]
101    #[inline(always)]
102    pub fn value1(self) -> &'a mut crate::W<REG> {
103        self.variant(PSL12_A::VALUE1)
104    }
105    #[doc = "Passive Level is HIGH"]
106    #[inline(always)]
107    pub fn value2(self) -> &'a mut crate::W<REG> {
108        self.variant(PSL12_A::VALUE2)
109    }
110}
111#[doc = "Output Passive Level for CCU8x.OUTy2\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum PSL21_A {
114    #[doc = "0: Passive Level is LOW"]
115    VALUE1 = 0,
116    #[doc = "1: Passive Level is HIGH"]
117    VALUE2 = 1,
118}
119impl From<PSL21_A> for bool {
120    #[inline(always)]
121    fn from(variant: PSL21_A) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `PSL21` reader - Output Passive Level for CCU8x.OUTy2"]
126pub type PSL21_R = crate::BitReader<PSL21_A>;
127impl PSL21_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> PSL21_A {
131        match self.bits {
132            false => PSL21_A::VALUE1,
133            true => PSL21_A::VALUE2,
134        }
135    }
136    #[doc = "Passive Level is LOW"]
137    #[inline(always)]
138    pub fn is_value1(&self) -> bool {
139        *self == PSL21_A::VALUE1
140    }
141    #[doc = "Passive Level is HIGH"]
142    #[inline(always)]
143    pub fn is_value2(&self) -> bool {
144        *self == PSL21_A::VALUE2
145    }
146}
147#[doc = "Field `PSL21` writer - Output Passive Level for CCU8x.OUTy2"]
148pub type PSL21_W<'a, REG> = crate::BitWriter<'a, REG, PSL21_A>;
149impl<'a, REG> PSL21_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Passive Level is LOW"]
154    #[inline(always)]
155    pub fn value1(self) -> &'a mut crate::W<REG> {
156        self.variant(PSL21_A::VALUE1)
157    }
158    #[doc = "Passive Level is HIGH"]
159    #[inline(always)]
160    pub fn value2(self) -> &'a mut crate::W<REG> {
161        self.variant(PSL21_A::VALUE2)
162    }
163}
164#[doc = "Output Passive Level for CCU8x.OUTy3\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum PSL22_A {
167    #[doc = "0: Passive Level is LOW"]
168    VALUE1 = 0,
169    #[doc = "1: Passive Level is HIGH"]
170    VALUE2 = 1,
171}
172impl From<PSL22_A> for bool {
173    #[inline(always)]
174    fn from(variant: PSL22_A) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `PSL22` reader - Output Passive Level for CCU8x.OUTy3"]
179pub type PSL22_R = crate::BitReader<PSL22_A>;
180impl PSL22_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> PSL22_A {
184        match self.bits {
185            false => PSL22_A::VALUE1,
186            true => PSL22_A::VALUE2,
187        }
188    }
189    #[doc = "Passive Level is LOW"]
190    #[inline(always)]
191    pub fn is_value1(&self) -> bool {
192        *self == PSL22_A::VALUE1
193    }
194    #[doc = "Passive Level is HIGH"]
195    #[inline(always)]
196    pub fn is_value2(&self) -> bool {
197        *self == PSL22_A::VALUE2
198    }
199}
200#[doc = "Field `PSL22` writer - Output Passive Level for CCU8x.OUTy3"]
201pub type PSL22_W<'a, REG> = crate::BitWriter<'a, REG, PSL22_A>;
202impl<'a, REG> PSL22_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Passive Level is LOW"]
207    #[inline(always)]
208    pub fn value1(self) -> &'a mut crate::W<REG> {
209        self.variant(PSL22_A::VALUE1)
210    }
211    #[doc = "Passive Level is HIGH"]
212    #[inline(always)]
213    pub fn value2(self) -> &'a mut crate::W<REG> {
214        self.variant(PSL22_A::VALUE2)
215    }
216}
217impl R {
218    #[doc = "Bit 0 - Output Passive Level for CCU8x.OUTy0"]
219    #[inline(always)]
220    pub fn psl11(&self) -> PSL11_R {
221        PSL11_R::new((self.bits & 1) != 0)
222    }
223    #[doc = "Bit 1 - Output Passive Level for CCU8x.OUTy1"]
224    #[inline(always)]
225    pub fn psl12(&self) -> PSL12_R {
226        PSL12_R::new(((self.bits >> 1) & 1) != 0)
227    }
228    #[doc = "Bit 2 - Output Passive Level for CCU8x.OUTy2"]
229    #[inline(always)]
230    pub fn psl21(&self) -> PSL21_R {
231        PSL21_R::new(((self.bits >> 2) & 1) != 0)
232    }
233    #[doc = "Bit 3 - Output Passive Level for CCU8x.OUTy3"]
234    #[inline(always)]
235    pub fn psl22(&self) -> PSL22_R {
236        PSL22_R::new(((self.bits >> 3) & 1) != 0)
237    }
238}
239impl W {
240    #[doc = "Bit 0 - Output Passive Level for CCU8x.OUTy0"]
241    #[inline(always)]
242    pub fn psl11(&mut self) -> PSL11_W<PSL_SPEC> {
243        PSL11_W::new(self, 0)
244    }
245    #[doc = "Bit 1 - Output Passive Level for CCU8x.OUTy1"]
246    #[inline(always)]
247    pub fn psl12(&mut self) -> PSL12_W<PSL_SPEC> {
248        PSL12_W::new(self, 1)
249    }
250    #[doc = "Bit 2 - Output Passive Level for CCU8x.OUTy2"]
251    #[inline(always)]
252    pub fn psl21(&mut self) -> PSL21_W<PSL_SPEC> {
253        PSL21_W::new(self, 2)
254    }
255    #[doc = "Bit 3 - Output Passive Level for CCU8x.OUTy3"]
256    #[inline(always)]
257    pub fn psl22(&mut self) -> PSL22_W<PSL_SPEC> {
258        PSL22_W::new(self, 3)
259    }
260}
261#[doc = "Passive Level Config\n\nYou can [`read`](crate::Reg::read) this register and get [`psl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
262pub struct PSL_SPEC;
263impl crate::RegisterSpec for PSL_SPEC {
264    type Ux = u32;
265}
266#[doc = "`read()` method returns [`psl::R`](R) reader structure"]
267impl crate::Readable for PSL_SPEC {}
268#[doc = "`write(|w| ..)` method takes [`psl::W`](W) writer structure"]
269impl crate::Writable for PSL_SPEC {
270    type Safety = crate::Unsafe;
271    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
272    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
273}
274#[doc = "`reset()` method sets PSL to value 0"]
275impl crate::Resettable for PSL_SPEC {
276    const RESET_VALUE: u32 = 0;
277}
xmc4200/ccu80_cc80/psl.rs

xmc4200/ccu80_cc80/
psl.rs
