1#[doc = "Register `CCR` reader"]
2pub type R = crate::R<CCR_SPEC>;
3#[doc = "Register `CCR` writer"]
4pub type W = crate::W<CCR_SPEC>;
5#[doc = "Non Base Thread Mode Enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum NONBASETHRDENA_A {
8 #[doc = "0: processor can enter Thread mode only when no exception is active."]
9 VALUE1 = 0,
10 #[doc = "1: processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception returnException return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:an LDM or POP instruction that loads the PCan LDR instruction with PC as the destinationa BX instruction using any register.EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits\\[31:5\\]
11set to one. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence.Exception return behaviorEXC_RETURN\\[31:0\\]Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. ."]
12 VALUE2 = 1,
13}
14impl From<NONBASETHRDENA_A> for bool {
15 #[inline(always)]
16 fn from(variant: NONBASETHRDENA_A) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `NONBASETHRDENA` reader - Non Base Thread Mode Enable"]
21pub type NONBASETHRDENA_R = crate::BitReader<NONBASETHRDENA_A>;
22impl NONBASETHRDENA_R {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> NONBASETHRDENA_A {
26 match self.bits {
27 false => NONBASETHRDENA_A::VALUE1,
28 true => NONBASETHRDENA_A::VALUE2,
29 }
30 }
31 #[doc = "processor can enter Thread mode only when no exception is active."]
32 #[inline(always)]
33 pub fn is_value1(&self) -> bool {
34 *self == NONBASETHRDENA_A::VALUE1
35 }
36 #[doc = "processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception returnException return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:an LDM or POP instruction that loads the PCan LDR instruction with PC as the destinationa BX instruction using any register.EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits\\[31:5\\]
37set to one. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence.Exception return behaviorEXC_RETURN\\[31:0\\]Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. ."]
38 #[inline(always)]
39 pub fn is_value2(&self) -> bool {
40 *self == NONBASETHRDENA_A::VALUE2
41 }
42}
43#[doc = "Field `NONBASETHRDENA` writer - Non Base Thread Mode Enable"]
44pub type NONBASETHRDENA_W<'a, REG> = crate::BitWriter<'a, REG, NONBASETHRDENA_A>;
45impl<'a, REG> NONBASETHRDENA_W<'a, REG>
46where
47 REG: crate::Writable + crate::RegisterSpec,
48{
49 #[doc = "processor can enter Thread mode only when no exception is active."]
50 #[inline(always)]
51 pub fn value1(self) -> &'a mut crate::W<REG> {
52 self.variant(NONBASETHRDENA_A::VALUE1)
53 }
54 #[doc = "processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception returnException return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:an LDM or POP instruction that loads the PCan LDR instruction with PC as the destinationa BX instruction using any register.EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits\\[31:5\\]
55set to one. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence.Exception return behaviorEXC_RETURN\\[31:0\\]Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. ."]
56 #[inline(always)]
57 pub fn value2(self) -> &'a mut crate::W<REG> {
58 self.variant(NONBASETHRDENA_A::VALUE2)
59 }
60}
61#[doc = "User Set Pending Enable\n\nValue on reset: 0"]
62#[derive(Clone, Copy, Debug, PartialEq, Eq)]
63pub enum USERSETMPEND_A {
64 #[doc = "0: disable"]
65 VALUE1 = 0,
66 #[doc = "1: enable"]
67 VALUE2 = 1,
68}
69impl From<USERSETMPEND_A> for bool {
70 #[inline(always)]
71 fn from(variant: USERSETMPEND_A) -> Self {
72 variant as u8 != 0
73 }
74}
75#[doc = "Field `USERSETMPEND` reader - User Set Pending Enable"]
76pub type USERSETMPEND_R = crate::BitReader<USERSETMPEND_A>;
77impl USERSETMPEND_R {
78 #[doc = "Get enumerated values variant"]
79 #[inline(always)]
80 pub const fn variant(&self) -> USERSETMPEND_A {
81 match self.bits {
82 false => USERSETMPEND_A::VALUE1,
83 true => USERSETMPEND_A::VALUE2,
84 }
85 }
86 #[doc = "disable"]
87 #[inline(always)]
88 pub fn is_value1(&self) -> bool {
89 *self == USERSETMPEND_A::VALUE1
90 }
91 #[doc = "enable"]
92 #[inline(always)]
93 pub fn is_value2(&self) -> bool {
94 *self == USERSETMPEND_A::VALUE2
95 }
96}
97#[doc = "Field `USERSETMPEND` writer - User Set Pending Enable"]
98pub type USERSETMPEND_W<'a, REG> = crate::BitWriter<'a, REG, USERSETMPEND_A>;
99impl<'a, REG> USERSETMPEND_W<'a, REG>
100where
101 REG: crate::Writable + crate::RegisterSpec,
102{
103 #[doc = "disable"]
104 #[inline(always)]
105 pub fn value1(self) -> &'a mut crate::W<REG> {
106 self.variant(USERSETMPEND_A::VALUE1)
107 }
108 #[doc = "enable"]
109 #[inline(always)]
110 pub fn value2(self) -> &'a mut crate::W<REG> {
111 self.variant(USERSETMPEND_A::VALUE2)
112 }
113}
114#[doc = "Unaligned Access Trap Enable\n\nValue on reset: 0"]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum UNALIGN_TRP_A {
117 #[doc = "0: do not trap unaligned halfword and word accesses"]
118 VALUE1 = 0,
119 #[doc = "1: trap unaligned halfword and word accesses."]
120 VALUE2 = 1,
121}
122impl From<UNALIGN_TRP_A> for bool {
123 #[inline(always)]
124 fn from(variant: UNALIGN_TRP_A) -> Self {
125 variant as u8 != 0
126 }
127}
128#[doc = "Field `UNALIGN_TRP` reader - Unaligned Access Trap Enable"]
129pub type UNALIGN_TRP_R = crate::BitReader<UNALIGN_TRP_A>;
130impl UNALIGN_TRP_R {
131 #[doc = "Get enumerated values variant"]
132 #[inline(always)]
133 pub const fn variant(&self) -> UNALIGN_TRP_A {
134 match self.bits {
135 false => UNALIGN_TRP_A::VALUE1,
136 true => UNALIGN_TRP_A::VALUE2,
137 }
138 }
139 #[doc = "do not trap unaligned halfword and word accesses"]
140 #[inline(always)]
141 pub fn is_value1(&self) -> bool {
142 *self == UNALIGN_TRP_A::VALUE1
143 }
144 #[doc = "trap unaligned halfword and word accesses."]
145 #[inline(always)]
146 pub fn is_value2(&self) -> bool {
147 *self == UNALIGN_TRP_A::VALUE2
148 }
149}
150#[doc = "Field `UNALIGN_TRP` writer - Unaligned Access Trap Enable"]
151pub type UNALIGN_TRP_W<'a, REG> = crate::BitWriter<'a, REG, UNALIGN_TRP_A>;
152impl<'a, REG> UNALIGN_TRP_W<'a, REG>
153where
154 REG: crate::Writable + crate::RegisterSpec,
155{
156 #[doc = "do not trap unaligned halfword and word accesses"]
157 #[inline(always)]
158 pub fn value1(self) -> &'a mut crate::W<REG> {
159 self.variant(UNALIGN_TRP_A::VALUE1)
160 }
161 #[doc = "trap unaligned halfword and word accesses."]
162 #[inline(always)]
163 pub fn value2(self) -> &'a mut crate::W<REG> {
164 self.variant(UNALIGN_TRP_A::VALUE2)
165 }
166}
167#[doc = "Divide by Zero Trap Enable\n\nValue on reset: 0"]
168#[derive(Clone, Copy, Debug, PartialEq, Eq)]
169pub enum DIV_0_TRP_A {
170 #[doc = "0: do not trap divide by 0"]
171 VALUE1 = 0,
172 #[doc = "1: trap divide by 0."]
173 VALUE2 = 1,
174}
175impl From<DIV_0_TRP_A> for bool {
176 #[inline(always)]
177 fn from(variant: DIV_0_TRP_A) -> Self {
178 variant as u8 != 0
179 }
180}
181#[doc = "Field `DIV_0_TRP` reader - Divide by Zero Trap Enable"]
182pub type DIV_0_TRP_R = crate::BitReader<DIV_0_TRP_A>;
183impl DIV_0_TRP_R {
184 #[doc = "Get enumerated values variant"]
185 #[inline(always)]
186 pub const fn variant(&self) -> DIV_0_TRP_A {
187 match self.bits {
188 false => DIV_0_TRP_A::VALUE1,
189 true => DIV_0_TRP_A::VALUE2,
190 }
191 }
192 #[doc = "do not trap divide by 0"]
193 #[inline(always)]
194 pub fn is_value1(&self) -> bool {
195 *self == DIV_0_TRP_A::VALUE1
196 }
197 #[doc = "trap divide by 0."]
198 #[inline(always)]
199 pub fn is_value2(&self) -> bool {
200 *self == DIV_0_TRP_A::VALUE2
201 }
202}
203#[doc = "Field `DIV_0_TRP` writer - Divide by Zero Trap Enable"]
204pub type DIV_0_TRP_W<'a, REG> = crate::BitWriter<'a, REG, DIV_0_TRP_A>;
205impl<'a, REG> DIV_0_TRP_W<'a, REG>
206where
207 REG: crate::Writable + crate::RegisterSpec,
208{
209 #[doc = "do not trap divide by 0"]
210 #[inline(always)]
211 pub fn value1(self) -> &'a mut crate::W<REG> {
212 self.variant(DIV_0_TRP_A::VALUE1)
213 }
214 #[doc = "trap divide by 0."]
215 #[inline(always)]
216 pub fn value2(self) -> &'a mut crate::W<REG> {
217 self.variant(DIV_0_TRP_A::VALUE2)
218 }
219}
220#[doc = "Bus Fault Hard Fault and NMI Ignore\n\nValue on reset: 0"]
221#[derive(Clone, Copy, Debug, PartialEq, Eq)]
222pub enum BFHFNMIGN_A {
223 #[doc = "0: data bus faults caused by load and store instructions cause a lock-up"]
224 VALUE1 = 0,
225 #[doc = "1: handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions."]
226 VALUE2 = 1,
227}
228impl From<BFHFNMIGN_A> for bool {
229 #[inline(always)]
230 fn from(variant: BFHFNMIGN_A) -> Self {
231 variant as u8 != 0
232 }
233}
234#[doc = "Field `BFHFNMIGN` reader - Bus Fault Hard Fault and NMI Ignore"]
235pub type BFHFNMIGN_R = crate::BitReader<BFHFNMIGN_A>;
236impl BFHFNMIGN_R {
237 #[doc = "Get enumerated values variant"]
238 #[inline(always)]
239 pub const fn variant(&self) -> BFHFNMIGN_A {
240 match self.bits {
241 false => BFHFNMIGN_A::VALUE1,
242 true => BFHFNMIGN_A::VALUE2,
243 }
244 }
245 #[doc = "data bus faults caused by load and store instructions cause a lock-up"]
246 #[inline(always)]
247 pub fn is_value1(&self) -> bool {
248 *self == BFHFNMIGN_A::VALUE1
249 }
250 #[doc = "handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions."]
251 #[inline(always)]
252 pub fn is_value2(&self) -> bool {
253 *self == BFHFNMIGN_A::VALUE2
254 }
255}
256#[doc = "Field `BFHFNMIGN` writer - Bus Fault Hard Fault and NMI Ignore"]
257pub type BFHFNMIGN_W<'a, REG> = crate::BitWriter<'a, REG, BFHFNMIGN_A>;
258impl<'a, REG> BFHFNMIGN_W<'a, REG>
259where
260 REG: crate::Writable + crate::RegisterSpec,
261{
262 #[doc = "data bus faults caused by load and store instructions cause a lock-up"]
263 #[inline(always)]
264 pub fn value1(self) -> &'a mut crate::W<REG> {
265 self.variant(BFHFNMIGN_A::VALUE1)
266 }
267 #[doc = "handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions."]
268 #[inline(always)]
269 pub fn value2(self) -> &'a mut crate::W<REG> {
270 self.variant(BFHFNMIGN_A::VALUE2)
271 }
272}
273#[doc = "Stack Alignment\n\nValue on reset: 1"]
274#[derive(Clone, Copy, Debug, PartialEq, Eq)]
275pub enum STKALIGN_A {
276 #[doc = "0: 4-byte aligned"]
277 VALUE1 = 0,
278 #[doc = "1: 8-byte aligned."]
279 VALUE2 = 1,
280}
281impl From<STKALIGN_A> for bool {
282 #[inline(always)]
283 fn from(variant: STKALIGN_A) -> Self {
284 variant as u8 != 0
285 }
286}
287#[doc = "Field `STKALIGN` reader - Stack Alignment"]
288pub type STKALIGN_R = crate::BitReader<STKALIGN_A>;
289impl STKALIGN_R {
290 #[doc = "Get enumerated values variant"]
291 #[inline(always)]
292 pub const fn variant(&self) -> STKALIGN_A {
293 match self.bits {
294 false => STKALIGN_A::VALUE1,
295 true => STKALIGN_A::VALUE2,
296 }
297 }
298 #[doc = "4-byte aligned"]
299 #[inline(always)]
300 pub fn is_value1(&self) -> bool {
301 *self == STKALIGN_A::VALUE1
302 }
303 #[doc = "8-byte aligned."]
304 #[inline(always)]
305 pub fn is_value2(&self) -> bool {
306 *self == STKALIGN_A::VALUE2
307 }
308}
309#[doc = "Field `STKALIGN` writer - Stack Alignment"]
310pub type STKALIGN_W<'a, REG> = crate::BitWriter<'a, REG, STKALIGN_A>;
311impl<'a, REG> STKALIGN_W<'a, REG>
312where
313 REG: crate::Writable + crate::RegisterSpec,
314{
315 #[doc = "4-byte aligned"]
316 #[inline(always)]
317 pub fn value1(self) -> &'a mut crate::W<REG> {
318 self.variant(STKALIGN_A::VALUE1)
319 }
320 #[doc = "8-byte aligned."]
321 #[inline(always)]
322 pub fn value2(self) -> &'a mut crate::W<REG> {
323 self.variant(STKALIGN_A::VALUE2)
324 }
325}
326impl R {
327 #[doc = "Bit 0 - Non Base Thread Mode Enable"]
328 #[inline(always)]
329 pub fn nonbasethrdena(&self) -> NONBASETHRDENA_R {
330 NONBASETHRDENA_R::new((self.bits & 1) != 0)
331 }
332 #[doc = "Bit 1 - User Set Pending Enable"]
333 #[inline(always)]
334 pub fn usersetmpend(&self) -> USERSETMPEND_R {
335 USERSETMPEND_R::new(((self.bits >> 1) & 1) != 0)
336 }
337 #[doc = "Bit 3 - Unaligned Access Trap Enable"]
338 #[inline(always)]
339 pub fn unalign_trp(&self) -> UNALIGN_TRP_R {
340 UNALIGN_TRP_R::new(((self.bits >> 3) & 1) != 0)
341 }
342 #[doc = "Bit 4 - Divide by Zero Trap Enable"]
343 #[inline(always)]
344 pub fn div_0_trp(&self) -> DIV_0_TRP_R {
345 DIV_0_TRP_R::new(((self.bits >> 4) & 1) != 0)
346 }
347 #[doc = "Bit 8 - Bus Fault Hard Fault and NMI Ignore"]
348 #[inline(always)]
349 pub fn bfhfnmign(&self) -> BFHFNMIGN_R {
350 BFHFNMIGN_R::new(((self.bits >> 8) & 1) != 0)
351 }
352 #[doc = "Bit 9 - Stack Alignment"]
353 #[inline(always)]
354 pub fn stkalign(&self) -> STKALIGN_R {
355 STKALIGN_R::new(((self.bits >> 9) & 1) != 0)
356 }
357}
358impl W {
359 #[doc = "Bit 0 - Non Base Thread Mode Enable"]
360 #[inline(always)]
361 pub fn nonbasethrdena(&mut self) -> NONBASETHRDENA_W<CCR_SPEC> {
362 NONBASETHRDENA_W::new(self, 0)
363 }
364 #[doc = "Bit 1 - User Set Pending Enable"]
365 #[inline(always)]
366 pub fn usersetmpend(&mut self) -> USERSETMPEND_W<CCR_SPEC> {
367 USERSETMPEND_W::new(self, 1)
368 }
369 #[doc = "Bit 3 - Unaligned Access Trap Enable"]
370 #[inline(always)]
371 pub fn unalign_trp(&mut self) -> UNALIGN_TRP_W<CCR_SPEC> {
372 UNALIGN_TRP_W::new(self, 3)
373 }
374 #[doc = "Bit 4 - Divide by Zero Trap Enable"]
375 #[inline(always)]
376 pub fn div_0_trp(&mut self) -> DIV_0_TRP_W<CCR_SPEC> {
377 DIV_0_TRP_W::new(self, 4)
378 }
379 #[doc = "Bit 8 - Bus Fault Hard Fault and NMI Ignore"]
380 #[inline(always)]
381 pub fn bfhfnmign(&mut self) -> BFHFNMIGN_W<CCR_SPEC> {
382 BFHFNMIGN_W::new(self, 8)
383 }
384 #[doc = "Bit 9 - Stack Alignment"]
385 #[inline(always)]
386 pub fn stkalign(&mut self) -> STKALIGN_W<CCR_SPEC> {
387 STKALIGN_W::new(self, 9)
388 }
389}
390#[doc = "Configuration and Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
391pub struct CCR_SPEC;
392impl crate::RegisterSpec for CCR_SPEC {
393 type Ux = u32;
394}
395#[doc = "`read()` method returns [`ccr::R`](R) reader structure"]
396impl crate::Readable for CCR_SPEC {}
397#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"]
398impl crate::Writable for CCR_SPEC {
399 type Safety = crate::Unsafe;
400 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
401 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
402}
403#[doc = "`reset()` method sets CCR to value 0x0200"]
404impl crate::Resettable for CCR_SPEC {
405 const RESET_VALUE: u32 = 0x0200;
406}