xmc4100/gpdma0/
chenreg.rs

1#[doc = "Register `CHENREG` reader"]
2pub type R = crate::R<CHENREG_SPEC>;
3#[doc = "Register `CHENREG` writer"]
4pub type W = crate::W<CHENREG_SPEC>;
5#[doc = "Enables/Disables the channel\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum CH_A {
9    #[doc = "0: Disable the Channel"]
10    VALUE1 = 0,
11    #[doc = "1: Enable the Channel"]
12    VALUE2 = 1,
13}
14impl From<CH_A> for u8 {
15    #[inline(always)]
16    fn from(variant: CH_A) -> Self {
17        variant as _
18    }
19}
20impl crate::FieldSpec for CH_A {
21    type Ux = u8;
22}
23impl crate::IsEnum for CH_A {}
24#[doc = "Field `CH` reader - Enables/Disables the channel"]
25pub type CH_R = crate::FieldReader<CH_A>;
26impl CH_R {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> Option<CH_A> {
30        match self.bits {
31            0 => Some(CH_A::VALUE1),
32            1 => Some(CH_A::VALUE2),
33            _ => None,
34        }
35    }
36    #[doc = "Disable the Channel"]
37    #[inline(always)]
38    pub fn is_value1(&self) -> bool {
39        *self == CH_A::VALUE1
40    }
41    #[doc = "Enable the Channel"]
42    #[inline(always)]
43    pub fn is_value2(&self) -> bool {
44        *self == CH_A::VALUE2
45    }
46}
47#[doc = "Field `CH` writer - Enables/Disables the channel"]
48pub type CH_W<'a, REG> = crate::FieldWriter<'a, REG, 8, CH_A>;
49impl<'a, REG> CH_W<'a, REG>
50where
51    REG: crate::Writable + crate::RegisterSpec,
52    REG::Ux: From<u8>,
53{
54    #[doc = "Disable the Channel"]
55    #[inline(always)]
56    pub fn value1(self) -> &'a mut crate::W<REG> {
57        self.variant(CH_A::VALUE1)
58    }
59    #[doc = "Enable the Channel"]
60    #[inline(always)]
61    pub fn value2(self) -> &'a mut crate::W<REG> {
62        self.variant(CH_A::VALUE2)
63    }
64}
65#[doc = "Field `WE_CH` writer - Channel enable write enable"]
66pub type WE_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
67impl R {
68    #[doc = "Bits 0:7 - Enables/Disables the channel"]
69    #[inline(always)]
70    pub fn ch(&self) -> CH_R {
71        CH_R::new((self.bits & 0xff) as u8)
72    }
73}
74impl W {
75    #[doc = "Bits 0:7 - Enables/Disables the channel"]
76    #[inline(always)]
77    pub fn ch(&mut self) -> CH_W<CHENREG_SPEC> {
78        CH_W::new(self, 0)
79    }
80    #[doc = "Bits 8:15 - Channel enable write enable"]
81    #[inline(always)]
82    pub fn we_ch(&mut self) -> WE_CH_W<CHENREG_SPEC> {
83        WE_CH_W::new(self, 8)
84    }
85}
86#[doc = "GPDMA Channel Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`chenreg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chenreg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
87pub struct CHENREG_SPEC;
88impl crate::RegisterSpec for CHENREG_SPEC {
89    type Ux = u32;
90}
91#[doc = "`read()` method returns [`chenreg::R`](R) reader structure"]
92impl crate::Readable for CHENREG_SPEC {}
93#[doc = "`write(|w| ..)` method takes [`chenreg::W`](W) writer structure"]
94impl crate::Writable for CHENREG_SPEC {
95    type Safety = crate::Unsafe;
96    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
97    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
98}
99#[doc = "`reset()` method sets CHENREG to value 0"]
100impl crate::Resettable for CHENREG_SPEC {
101    const RESET_VALUE: u32 = 0;
102}
xmc4100/gpdma0/chenreg.rs

xmc4100/gpdma0/
chenreg.rs
