1#[doc = "Register `BRSMR` reader"]
2pub type R = crate::R<BRSMR_SPEC>;
3#[doc = "Register `BRSMR` writer"]
4pub type W = crate::W<BRSMR_SPEC>;
5#[doc = "Enable Gate\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum ENGT_A {
9 #[doc = "0: No conversion requests are issued"]
10 VALUE1 = 0,
11 #[doc = "1: Conversion requests are issued if at least one pending bit is set"]
12 VALUE2 = 1,
13 #[doc = "2: Conversion requests are issued if at least one pending bit is set and REQGTx = 1."]
14 VALUE3 = 2,
15 #[doc = "3: Conversion requests are issued if at least one pending bit is set and REQGTx = 0."]
16 VALUE4 = 3,
17}
18impl From<ENGT_A> for u8 {
19 #[inline(always)]
20 fn from(variant: ENGT_A) -> Self {
21 variant as _
22 }
23}
24impl crate::FieldSpec for ENGT_A {
25 type Ux = u8;
26}
27impl crate::IsEnum for ENGT_A {}
28#[doc = "Field `ENGT` reader - Enable Gate"]
29pub type ENGT_R = crate::FieldReader<ENGT_A>;
30impl ENGT_R {
31 #[doc = "Get enumerated values variant"]
32 #[inline(always)]
33 pub const fn variant(&self) -> ENGT_A {
34 match self.bits {
35 0 => ENGT_A::VALUE1,
36 1 => ENGT_A::VALUE2,
37 2 => ENGT_A::VALUE3,
38 3 => ENGT_A::VALUE4,
39 _ => unreachable!(),
40 }
41 }
42 #[doc = "No conversion requests are issued"]
43 #[inline(always)]
44 pub fn is_value1(&self) -> bool {
45 *self == ENGT_A::VALUE1
46 }
47 #[doc = "Conversion requests are issued if at least one pending bit is set"]
48 #[inline(always)]
49 pub fn is_value2(&self) -> bool {
50 *self == ENGT_A::VALUE2
51 }
52 #[doc = "Conversion requests are issued if at least one pending bit is set and REQGTx = 1."]
53 #[inline(always)]
54 pub fn is_value3(&self) -> bool {
55 *self == ENGT_A::VALUE3
56 }
57 #[doc = "Conversion requests are issued if at least one pending bit is set and REQGTx = 0."]
58 #[inline(always)]
59 pub fn is_value4(&self) -> bool {
60 *self == ENGT_A::VALUE4
61 }
62}
63#[doc = "Field `ENGT` writer - Enable Gate"]
64pub type ENGT_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ENGT_A, crate::Safe>;
65impl<'a, REG> ENGT_W<'a, REG>
66where
67 REG: crate::Writable + crate::RegisterSpec,
68 REG::Ux: From<u8>,
69{
70 #[doc = "No conversion requests are issued"]
71 #[inline(always)]
72 pub fn value1(self) -> &'a mut crate::W<REG> {
73 self.variant(ENGT_A::VALUE1)
74 }
75 #[doc = "Conversion requests are issued if at least one pending bit is set"]
76 #[inline(always)]
77 pub fn value2(self) -> &'a mut crate::W<REG> {
78 self.variant(ENGT_A::VALUE2)
79 }
80 #[doc = "Conversion requests are issued if at least one pending bit is set and REQGTx = 1."]
81 #[inline(always)]
82 pub fn value3(self) -> &'a mut crate::W<REG> {
83 self.variant(ENGT_A::VALUE3)
84 }
85 #[doc = "Conversion requests are issued if at least one pending bit is set and REQGTx = 0."]
86 #[inline(always)]
87 pub fn value4(self) -> &'a mut crate::W<REG> {
88 self.variant(ENGT_A::VALUE4)
89 }
90}
91#[doc = "Enable External Trigger\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq, Eq)]
93pub enum ENTR_A {
94 #[doc = "0: External trigger disabled"]
95 VALUE1 = 0,
96 #[doc = "1: The selected edge at the selected trigger input signal REQTR generates the load event"]
97 VALUE2 = 1,
98}
99impl From<ENTR_A> for bool {
100 #[inline(always)]
101 fn from(variant: ENTR_A) -> Self {
102 variant as u8 != 0
103 }
104}
105#[doc = "Field `ENTR` reader - Enable External Trigger"]
106pub type ENTR_R = crate::BitReader<ENTR_A>;
107impl ENTR_R {
108 #[doc = "Get enumerated values variant"]
109 #[inline(always)]
110 pub const fn variant(&self) -> ENTR_A {
111 match self.bits {
112 false => ENTR_A::VALUE1,
113 true => ENTR_A::VALUE2,
114 }
115 }
116 #[doc = "External trigger disabled"]
117 #[inline(always)]
118 pub fn is_value1(&self) -> bool {
119 *self == ENTR_A::VALUE1
120 }
121 #[doc = "The selected edge at the selected trigger input signal REQTR generates the load event"]
122 #[inline(always)]
123 pub fn is_value2(&self) -> bool {
124 *self == ENTR_A::VALUE2
125 }
126}
127#[doc = "Field `ENTR` writer - Enable External Trigger"]
128pub type ENTR_W<'a, REG> = crate::BitWriter<'a, REG, ENTR_A>;
129impl<'a, REG> ENTR_W<'a, REG>
130where
131 REG: crate::Writable + crate::RegisterSpec,
132{
133 #[doc = "External trigger disabled"]
134 #[inline(always)]
135 pub fn value1(self) -> &'a mut crate::W<REG> {
136 self.variant(ENTR_A::VALUE1)
137 }
138 #[doc = "The selected edge at the selected trigger input signal REQTR generates the load event"]
139 #[inline(always)]
140 pub fn value2(self) -> &'a mut crate::W<REG> {
141 self.variant(ENTR_A::VALUE2)
142 }
143}
144#[doc = "Enable Source Interrupt\n\nValue on reset: 0"]
145#[derive(Clone, Copy, Debug, PartialEq, Eq)]
146pub enum ENSI_A {
147 #[doc = "0: No request source interrupt"]
148 VALUE1 = 0,
149 #[doc = "1: A request source interrupt is generated upon a request source event (last pending conversion is finished)"]
150 VALUE2 = 1,
151}
152impl From<ENSI_A> for bool {
153 #[inline(always)]
154 fn from(variant: ENSI_A) -> Self {
155 variant as u8 != 0
156 }
157}
158#[doc = "Field `ENSI` reader - Enable Source Interrupt"]
159pub type ENSI_R = crate::BitReader<ENSI_A>;
160impl ENSI_R {
161 #[doc = "Get enumerated values variant"]
162 #[inline(always)]
163 pub const fn variant(&self) -> ENSI_A {
164 match self.bits {
165 false => ENSI_A::VALUE1,
166 true => ENSI_A::VALUE2,
167 }
168 }
169 #[doc = "No request source interrupt"]
170 #[inline(always)]
171 pub fn is_value1(&self) -> bool {
172 *self == ENSI_A::VALUE1
173 }
174 #[doc = "A request source interrupt is generated upon a request source event (last pending conversion is finished)"]
175 #[inline(always)]
176 pub fn is_value2(&self) -> bool {
177 *self == ENSI_A::VALUE2
178 }
179}
180#[doc = "Field `ENSI` writer - Enable Source Interrupt"]
181pub type ENSI_W<'a, REG> = crate::BitWriter<'a, REG, ENSI_A>;
182impl<'a, REG> ENSI_W<'a, REG>
183where
184 REG: crate::Writable + crate::RegisterSpec,
185{
186 #[doc = "No request source interrupt"]
187 #[inline(always)]
188 pub fn value1(self) -> &'a mut crate::W<REG> {
189 self.variant(ENSI_A::VALUE1)
190 }
191 #[doc = "A request source interrupt is generated upon a request source event (last pending conversion is finished)"]
192 #[inline(always)]
193 pub fn value2(self) -> &'a mut crate::W<REG> {
194 self.variant(ENSI_A::VALUE2)
195 }
196}
197#[doc = "Autoscan Enable\n\nValue on reset: 0"]
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199pub enum SCAN_A {
200 #[doc = "0: No autoscan"]
201 VALUE1 = 0,
202 #[doc = "1: Autoscan functionality enabled: a request source event automatically generates a load event"]
203 VALUE2 = 1,
204}
205impl From<SCAN_A> for bool {
206 #[inline(always)]
207 fn from(variant: SCAN_A) -> Self {
208 variant as u8 != 0
209 }
210}
211#[doc = "Field `SCAN` reader - Autoscan Enable"]
212pub type SCAN_R = crate::BitReader<SCAN_A>;
213impl SCAN_R {
214 #[doc = "Get enumerated values variant"]
215 #[inline(always)]
216 pub const fn variant(&self) -> SCAN_A {
217 match self.bits {
218 false => SCAN_A::VALUE1,
219 true => SCAN_A::VALUE2,
220 }
221 }
222 #[doc = "No autoscan"]
223 #[inline(always)]
224 pub fn is_value1(&self) -> bool {
225 *self == SCAN_A::VALUE1
226 }
227 #[doc = "Autoscan functionality enabled: a request source event automatically generates a load event"]
228 #[inline(always)]
229 pub fn is_value2(&self) -> bool {
230 *self == SCAN_A::VALUE2
231 }
232}
233#[doc = "Field `SCAN` writer - Autoscan Enable"]
234pub type SCAN_W<'a, REG> = crate::BitWriter<'a, REG, SCAN_A>;
235impl<'a, REG> SCAN_W<'a, REG>
236where
237 REG: crate::Writable + crate::RegisterSpec,
238{
239 #[doc = "No autoscan"]
240 #[inline(always)]
241 pub fn value1(self) -> &'a mut crate::W<REG> {
242 self.variant(SCAN_A::VALUE1)
243 }
244 #[doc = "Autoscan functionality enabled: a request source event automatically generates a load event"]
245 #[inline(always)]
246 pub fn value2(self) -> &'a mut crate::W<REG> {
247 self.variant(SCAN_A::VALUE2)
248 }
249}
250#[doc = "Autoscan Source Load Event Mode\n\nValue on reset: 0"]
251#[derive(Clone, Copy, Debug, PartialEq, Eq)]
252pub enum LDM_A {
253 #[doc = "0: Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event"]
254 VALUE1 = 0,
255 #[doc = "1: Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR)"]
256 VALUE2 = 1,
257}
258impl From<LDM_A> for bool {
259 #[inline(always)]
260 fn from(variant: LDM_A) -> Self {
261 variant as u8 != 0
262 }
263}
264#[doc = "Field `LDM` reader - Autoscan Source Load Event Mode"]
265pub type LDM_R = crate::BitReader<LDM_A>;
266impl LDM_R {
267 #[doc = "Get enumerated values variant"]
268 #[inline(always)]
269 pub const fn variant(&self) -> LDM_A {
270 match self.bits {
271 false => LDM_A::VALUE1,
272 true => LDM_A::VALUE2,
273 }
274 }
275 #[doc = "Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event"]
276 #[inline(always)]
277 pub fn is_value1(&self) -> bool {
278 *self == LDM_A::VALUE1
279 }
280 #[doc = "Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR)"]
281 #[inline(always)]
282 pub fn is_value2(&self) -> bool {
283 *self == LDM_A::VALUE2
284 }
285}
286#[doc = "Field `LDM` writer - Autoscan Source Load Event Mode"]
287pub type LDM_W<'a, REG> = crate::BitWriter<'a, REG, LDM_A>;
288impl<'a, REG> LDM_W<'a, REG>
289where
290 REG: crate::Writable + crate::RegisterSpec,
291{
292 #[doc = "Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event"]
293 #[inline(always)]
294 pub fn value1(self) -> &'a mut crate::W<REG> {
295 self.variant(LDM_A::VALUE1)
296 }
297 #[doc = "Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR)"]
298 #[inline(always)]
299 pub fn value2(self) -> &'a mut crate::W<REG> {
300 self.variant(LDM_A::VALUE2)
301 }
302}
303#[doc = "Request Gate Level\n\nValue on reset: 0"]
304#[derive(Clone, Copy, Debug, PartialEq, Eq)]
305pub enum REQGT_A {
306 #[doc = "0: The gate input is low"]
307 VALUE1 = 0,
308 #[doc = "1: The gate input is high"]
309 VALUE2 = 1,
310}
311impl From<REQGT_A> for bool {
312 #[inline(always)]
313 fn from(variant: REQGT_A) -> Self {
314 variant as u8 != 0
315 }
316}
317#[doc = "Field `REQGT` reader - Request Gate Level"]
318pub type REQGT_R = crate::BitReader<REQGT_A>;
319impl REQGT_R {
320 #[doc = "Get enumerated values variant"]
321 #[inline(always)]
322 pub const fn variant(&self) -> REQGT_A {
323 match self.bits {
324 false => REQGT_A::VALUE1,
325 true => REQGT_A::VALUE2,
326 }
327 }
328 #[doc = "The gate input is low"]
329 #[inline(always)]
330 pub fn is_value1(&self) -> bool {
331 *self == REQGT_A::VALUE1
332 }
333 #[doc = "The gate input is high"]
334 #[inline(always)]
335 pub fn is_value2(&self) -> bool {
336 *self == REQGT_A::VALUE2
337 }
338}
339#[doc = "Clear Pending Bits\n\nValue on reset: 0"]
340#[derive(Clone, Copy, Debug, PartialEq, Eq)]
341pub enum CLRPND_A {
342 #[doc = "0: No action"]
343 VALUE1 = 0,
344 #[doc = "1: The bits in registers BRSPNDx are cleared"]
345 VALUE2 = 1,
346}
347impl From<CLRPND_A> for bool {
348 #[inline(always)]
349 fn from(variant: CLRPND_A) -> Self {
350 variant as u8 != 0
351 }
352}
353#[doc = "Field `CLRPND` writer - Clear Pending Bits"]
354pub type CLRPND_W<'a, REG> = crate::BitWriter<'a, REG, CLRPND_A>;
355impl<'a, REG> CLRPND_W<'a, REG>
356where
357 REG: crate::Writable + crate::RegisterSpec,
358{
359 #[doc = "No action"]
360 #[inline(always)]
361 pub fn value1(self) -> &'a mut crate::W<REG> {
362 self.variant(CLRPND_A::VALUE1)
363 }
364 #[doc = "The bits in registers BRSPNDx are cleared"]
365 #[inline(always)]
366 pub fn value2(self) -> &'a mut crate::W<REG> {
367 self.variant(CLRPND_A::VALUE2)
368 }
369}
370#[doc = "Generate Load Event\n\nValue on reset: 0"]
371#[derive(Clone, Copy, Debug, PartialEq, Eq)]
372pub enum LDEV_A {
373 #[doc = "0: No action"]
374 VALUE1 = 0,
375 #[doc = "1: A load event is generated"]
376 VALUE2 = 1,
377}
378impl From<LDEV_A> for bool {
379 #[inline(always)]
380 fn from(variant: LDEV_A) -> Self {
381 variant as u8 != 0
382 }
383}
384#[doc = "Field `LDEV` writer - Generate Load Event"]
385pub type LDEV_W<'a, REG> = crate::BitWriter<'a, REG, LDEV_A>;
386impl<'a, REG> LDEV_W<'a, REG>
387where
388 REG: crate::Writable + crate::RegisterSpec,
389{
390 #[doc = "No action"]
391 #[inline(always)]
392 pub fn value1(self) -> &'a mut crate::W<REG> {
393 self.variant(LDEV_A::VALUE1)
394 }
395 #[doc = "A load event is generated"]
396 #[inline(always)]
397 pub fn value2(self) -> &'a mut crate::W<REG> {
398 self.variant(LDEV_A::VALUE2)
399 }
400}
401#[doc = "Repeat Disable\n\nValue on reset: 0"]
402#[derive(Clone, Copy, Debug, PartialEq, Eq)]
403pub enum RPTDIS_A {
404 #[doc = "0: A cancelled conversion is repeated"]
405 VALUE1 = 0,
406 #[doc = "1: A cancelled conversion is discarded"]
407 VALUE2 = 1,
408}
409impl From<RPTDIS_A> for bool {
410 #[inline(always)]
411 fn from(variant: RPTDIS_A) -> Self {
412 variant as u8 != 0
413 }
414}
415#[doc = "Field `RPTDIS` reader - Repeat Disable"]
416pub type RPTDIS_R = crate::BitReader<RPTDIS_A>;
417impl RPTDIS_R {
418 #[doc = "Get enumerated values variant"]
419 #[inline(always)]
420 pub const fn variant(&self) -> RPTDIS_A {
421 match self.bits {
422 false => RPTDIS_A::VALUE1,
423 true => RPTDIS_A::VALUE2,
424 }
425 }
426 #[doc = "A cancelled conversion is repeated"]
427 #[inline(always)]
428 pub fn is_value1(&self) -> bool {
429 *self == RPTDIS_A::VALUE1
430 }
431 #[doc = "A cancelled conversion is discarded"]
432 #[inline(always)]
433 pub fn is_value2(&self) -> bool {
434 *self == RPTDIS_A::VALUE2
435 }
436}
437#[doc = "Field `RPTDIS` writer - Repeat Disable"]
438pub type RPTDIS_W<'a, REG> = crate::BitWriter<'a, REG, RPTDIS_A>;
439impl<'a, REG> RPTDIS_W<'a, REG>
440where
441 REG: crate::Writable + crate::RegisterSpec,
442{
443 #[doc = "A cancelled conversion is repeated"]
444 #[inline(always)]
445 pub fn value1(self) -> &'a mut crate::W<REG> {
446 self.variant(RPTDIS_A::VALUE1)
447 }
448 #[doc = "A cancelled conversion is discarded"]
449 #[inline(always)]
450 pub fn value2(self) -> &'a mut crate::W<REG> {
451 self.variant(RPTDIS_A::VALUE2)
452 }
453}
454impl R {
455 #[doc = "Bits 0:1 - Enable Gate"]
456 #[inline(always)]
457 pub fn engt(&self) -> ENGT_R {
458 ENGT_R::new((self.bits & 3) as u8)
459 }
460 #[doc = "Bit 2 - Enable External Trigger"]
461 #[inline(always)]
462 pub fn entr(&self) -> ENTR_R {
463 ENTR_R::new(((self.bits >> 2) & 1) != 0)
464 }
465 #[doc = "Bit 3 - Enable Source Interrupt"]
466 #[inline(always)]
467 pub fn ensi(&self) -> ENSI_R {
468 ENSI_R::new(((self.bits >> 3) & 1) != 0)
469 }
470 #[doc = "Bit 4 - Autoscan Enable"]
471 #[inline(always)]
472 pub fn scan(&self) -> SCAN_R {
473 SCAN_R::new(((self.bits >> 4) & 1) != 0)
474 }
475 #[doc = "Bit 5 - Autoscan Source Load Event Mode"]
476 #[inline(always)]
477 pub fn ldm(&self) -> LDM_R {
478 LDM_R::new(((self.bits >> 5) & 1) != 0)
479 }
480 #[doc = "Bit 7 - Request Gate Level"]
481 #[inline(always)]
482 pub fn reqgt(&self) -> REQGT_R {
483 REQGT_R::new(((self.bits >> 7) & 1) != 0)
484 }
485 #[doc = "Bit 16 - Repeat Disable"]
486 #[inline(always)]
487 pub fn rptdis(&self) -> RPTDIS_R {
488 RPTDIS_R::new(((self.bits >> 16) & 1) != 0)
489 }
490}
491impl W {
492 #[doc = "Bits 0:1 - Enable Gate"]
493 #[inline(always)]
494 pub fn engt(&mut self) -> ENGT_W<BRSMR_SPEC> {
495 ENGT_W::new(self, 0)
496 }
497 #[doc = "Bit 2 - Enable External Trigger"]
498 #[inline(always)]
499 pub fn entr(&mut self) -> ENTR_W<BRSMR_SPEC> {
500 ENTR_W::new(self, 2)
501 }
502 #[doc = "Bit 3 - Enable Source Interrupt"]
503 #[inline(always)]
504 pub fn ensi(&mut self) -> ENSI_W<BRSMR_SPEC> {
505 ENSI_W::new(self, 3)
506 }
507 #[doc = "Bit 4 - Autoscan Enable"]
508 #[inline(always)]
509 pub fn scan(&mut self) -> SCAN_W<BRSMR_SPEC> {
510 SCAN_W::new(self, 4)
511 }
512 #[doc = "Bit 5 - Autoscan Source Load Event Mode"]
513 #[inline(always)]
514 pub fn ldm(&mut self) -> LDM_W<BRSMR_SPEC> {
515 LDM_W::new(self, 5)
516 }
517 #[doc = "Bit 8 - Clear Pending Bits"]
518 #[inline(always)]
519 pub fn clrpnd(&mut self) -> CLRPND_W<BRSMR_SPEC> {
520 CLRPND_W::new(self, 8)
521 }
522 #[doc = "Bit 9 - Generate Load Event"]
523 #[inline(always)]
524 pub fn ldev(&mut self) -> LDEV_W<BRSMR_SPEC> {
525 LDEV_W::new(self, 9)
526 }
527 #[doc = "Bit 16 - Repeat Disable"]
528 #[inline(always)]
529 pub fn rptdis(&mut self) -> RPTDIS_W<BRSMR_SPEC> {
530 RPTDIS_W::new(self, 16)
531 }
532}
533#[doc = "Background Request Source Mode Register\n\nYou can [`read`](crate::Reg::read) this register and get [`brsmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`brsmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
534pub struct BRSMR_SPEC;
535impl crate::RegisterSpec for BRSMR_SPEC {
536 type Ux = u32;
537}
538#[doc = "`read()` method returns [`brsmr::R`](R) reader structure"]
539impl crate::Readable for BRSMR_SPEC {}
540#[doc = "`write(|w| ..)` method takes [`brsmr::W`](W) writer structure"]
541impl crate::Writable for BRSMR_SPEC {
542 type Safety = crate::Unsafe;
543 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
544 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
545}
546#[doc = "`reset()` method sets BRSMR to value 0"]
547impl crate::Resettable for BRSMR_SPEC {
548 const RESET_VALUE: u32 = 0;
549}