xmc4100/gpdma0_ch2/
cfgl.rs

1#[doc = "Register `CFGL` reader"]
2pub type R = crate::R<CFGL_SPEC>;
3#[doc = "Register `CFGL` writer"]
4pub type W = crate::W<CFGL_SPEC>;
5#[doc = "Field `CH_PRIOR` reader - Channel priority"]
6pub type CH_PRIOR_R = crate::FieldReader;
7#[doc = "Field `CH_PRIOR` writer - Channel priority"]
8pub type CH_PRIOR_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Channel Suspend\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum CH_SUSP_A {
12    #[doc = "0: Not suspended."]
13    VALUE1 = 0,
14    #[doc = "1: Suspend DMA transfer from the source."]
15    VALUE2 = 1,
16}
17impl From<CH_SUSP_A> for bool {
18    #[inline(always)]
19    fn from(variant: CH_SUSP_A) -> Self {
20        variant as u8 != 0
21    }
22}
23#[doc = "Field `CH_SUSP` reader - Channel Suspend"]
24pub type CH_SUSP_R = crate::BitReader<CH_SUSP_A>;
25impl CH_SUSP_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> CH_SUSP_A {
29        match self.bits {
30            false => CH_SUSP_A::VALUE1,
31            true => CH_SUSP_A::VALUE2,
32        }
33    }
34    #[doc = "Not suspended."]
35    #[inline(always)]
36    pub fn is_value1(&self) -> bool {
37        *self == CH_SUSP_A::VALUE1
38    }
39    #[doc = "Suspend DMA transfer from the source."]
40    #[inline(always)]
41    pub fn is_value2(&self) -> bool {
42        *self == CH_SUSP_A::VALUE2
43    }
44}
45#[doc = "Field `CH_SUSP` writer - Channel Suspend"]
46pub type CH_SUSP_W<'a, REG> = crate::BitWriter<'a, REG, CH_SUSP_A>;
47impl<'a, REG> CH_SUSP_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Not suspended."]
52    #[inline(always)]
53    pub fn value1(self) -> &'a mut crate::W<REG> {
54        self.variant(CH_SUSP_A::VALUE1)
55    }
56    #[doc = "Suspend DMA transfer from the source."]
57    #[inline(always)]
58    pub fn value2(self) -> &'a mut crate::W<REG> {
59        self.variant(CH_SUSP_A::VALUE2)
60    }
61}
62#[doc = "Indicates if there is data left in the channel FIFO\n\nValue on reset: 1"]
63#[derive(Clone, Copy, Debug, PartialEq, Eq)]
64pub enum FIFO_EMPTY_A {
65    #[doc = "1: Channel FIFO empty"]
66    VALUE1 = 1,
67    #[doc = "0: Channel FIFO not empty"]
68    VALUE2 = 0,
69}
70impl From<FIFO_EMPTY_A> for bool {
71    #[inline(always)]
72    fn from(variant: FIFO_EMPTY_A) -> Self {
73        variant as u8 != 0
74    }
75}
76#[doc = "Field `FIFO_EMPTY` reader - Indicates if there is data left in the channel FIFO"]
77pub type FIFO_EMPTY_R = crate::BitReader<FIFO_EMPTY_A>;
78impl FIFO_EMPTY_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> FIFO_EMPTY_A {
82        match self.bits {
83            true => FIFO_EMPTY_A::VALUE1,
84            false => FIFO_EMPTY_A::VALUE2,
85        }
86    }
87    #[doc = "Channel FIFO empty"]
88    #[inline(always)]
89    pub fn is_value1(&self) -> bool {
90        *self == FIFO_EMPTY_A::VALUE1
91    }
92    #[doc = "Channel FIFO not empty"]
93    #[inline(always)]
94    pub fn is_value2(&self) -> bool {
95        *self == FIFO_EMPTY_A::VALUE2
96    }
97}
98#[doc = "Destination Software or Hardware Handshaking Select\n\nValue on reset: 1"]
99#[derive(Clone, Copy, Debug, PartialEq, Eq)]
100pub enum HS_SEL_DST_A {
101    #[doc = "0: Hardware handshaking interface. Software-initiated transaction requests are ignored."]
102    VALUE1 = 0,
103    #[doc = "1: Software handshaking interface. Hardware- initiated transaction requests are ignored."]
104    VALUE2 = 1,
105}
106impl From<HS_SEL_DST_A> for bool {
107    #[inline(always)]
108    fn from(variant: HS_SEL_DST_A) -> Self {
109        variant as u8 != 0
110    }
111}
112#[doc = "Field `HS_SEL_DST` reader - Destination Software or Hardware Handshaking Select"]
113pub type HS_SEL_DST_R = crate::BitReader<HS_SEL_DST_A>;
114impl HS_SEL_DST_R {
115    #[doc = "Get enumerated values variant"]
116    #[inline(always)]
117    pub const fn variant(&self) -> HS_SEL_DST_A {
118        match self.bits {
119            false => HS_SEL_DST_A::VALUE1,
120            true => HS_SEL_DST_A::VALUE2,
121        }
122    }
123    #[doc = "Hardware handshaking interface. Software-initiated transaction requests are ignored."]
124    #[inline(always)]
125    pub fn is_value1(&self) -> bool {
126        *self == HS_SEL_DST_A::VALUE1
127    }
128    #[doc = "Software handshaking interface. Hardware- initiated transaction requests are ignored."]
129    #[inline(always)]
130    pub fn is_value2(&self) -> bool {
131        *self == HS_SEL_DST_A::VALUE2
132    }
133}
134#[doc = "Field `HS_SEL_DST` writer - Destination Software or Hardware Handshaking Select"]
135pub type HS_SEL_DST_W<'a, REG> = crate::BitWriter<'a, REG, HS_SEL_DST_A>;
136impl<'a, REG> HS_SEL_DST_W<'a, REG>
137where
138    REG: crate::Writable + crate::RegisterSpec,
139{
140    #[doc = "Hardware handshaking interface. Software-initiated transaction requests are ignored."]
141    #[inline(always)]
142    pub fn value1(self) -> &'a mut crate::W<REG> {
143        self.variant(HS_SEL_DST_A::VALUE1)
144    }
145    #[doc = "Software handshaking interface. Hardware- initiated transaction requests are ignored."]
146    #[inline(always)]
147    pub fn value2(self) -> &'a mut crate::W<REG> {
148        self.variant(HS_SEL_DST_A::VALUE2)
149    }
150}
151#[doc = "Source Software or Hardware Handshaking Select\n\nValue on reset: 1"]
152#[derive(Clone, Copy, Debug, PartialEq, Eq)]
153pub enum HS_SEL_SRC_A {
154    #[doc = "0: Hardware handshaking interface. Software-initiated transaction requests are ignored."]
155    VALUE1 = 0,
156    #[doc = "1: Software handshaking interface. Hardware-initiated transaction requests are ignored."]
157    VALUE2 = 1,
158}
159impl From<HS_SEL_SRC_A> for bool {
160    #[inline(always)]
161    fn from(variant: HS_SEL_SRC_A) -> Self {
162        variant as u8 != 0
163    }
164}
165#[doc = "Field `HS_SEL_SRC` reader - Source Software or Hardware Handshaking Select"]
166pub type HS_SEL_SRC_R = crate::BitReader<HS_SEL_SRC_A>;
167impl HS_SEL_SRC_R {
168    #[doc = "Get enumerated values variant"]
169    #[inline(always)]
170    pub const fn variant(&self) -> HS_SEL_SRC_A {
171        match self.bits {
172            false => HS_SEL_SRC_A::VALUE1,
173            true => HS_SEL_SRC_A::VALUE2,
174        }
175    }
176    #[doc = "Hardware handshaking interface. Software-initiated transaction requests are ignored."]
177    #[inline(always)]
178    pub fn is_value1(&self) -> bool {
179        *self == HS_SEL_SRC_A::VALUE1
180    }
181    #[doc = "Software handshaking interface. Hardware-initiated transaction requests are ignored."]
182    #[inline(always)]
183    pub fn is_value2(&self) -> bool {
184        *self == HS_SEL_SRC_A::VALUE2
185    }
186}
187#[doc = "Field `HS_SEL_SRC` writer - Source Software or Hardware Handshaking Select"]
188pub type HS_SEL_SRC_W<'a, REG> = crate::BitWriter<'a, REG, HS_SEL_SRC_A>;
189impl<'a, REG> HS_SEL_SRC_W<'a, REG>
190where
191    REG: crate::Writable + crate::RegisterSpec,
192{
193    #[doc = "Hardware handshaking interface. Software-initiated transaction requests are ignored."]
194    #[inline(always)]
195    pub fn value1(self) -> &'a mut crate::W<REG> {
196        self.variant(HS_SEL_SRC_A::VALUE1)
197    }
198    #[doc = "Software handshaking interface. Hardware-initiated transaction requests are ignored."]
199    #[inline(always)]
200    pub fn value2(self) -> &'a mut crate::W<REG> {
201        self.variant(HS_SEL_SRC_A::VALUE2)
202    }
203}
204#[doc = "Channel Lock Level\n\nValue on reset: 0"]
205#[derive(Clone, Copy, Debug, PartialEq, Eq)]
206#[repr(u8)]
207pub enum LOCK_CH_L_A {
208    #[doc = "0: Over complete DMA transfer"]
209    VALUE1 = 0,
210    #[doc = "1: Over complete DMA block transfer"]
211    VALUE2 = 1,
212    #[doc = "2: Over complete DMA transaction"]
213    VALUE3 = 2,
214}
215impl From<LOCK_CH_L_A> for u8 {
216    #[inline(always)]
217    fn from(variant: LOCK_CH_L_A) -> Self {
218        variant as _
219    }
220}
221impl crate::FieldSpec for LOCK_CH_L_A {
222    type Ux = u8;
223}
224impl crate::IsEnum for LOCK_CH_L_A {}
225#[doc = "Field `LOCK_CH_L` reader - Channel Lock Level"]
226pub type LOCK_CH_L_R = crate::FieldReader<LOCK_CH_L_A>;
227impl LOCK_CH_L_R {
228    #[doc = "Get enumerated values variant"]
229    #[inline(always)]
230    pub const fn variant(&self) -> Option<LOCK_CH_L_A> {
231        match self.bits {
232            0 => Some(LOCK_CH_L_A::VALUE1),
233            1 => Some(LOCK_CH_L_A::VALUE2),
234            2 => Some(LOCK_CH_L_A::VALUE3),
235            _ => None,
236        }
237    }
238    #[doc = "Over complete DMA transfer"]
239    #[inline(always)]
240    pub fn is_value1(&self) -> bool {
241        *self == LOCK_CH_L_A::VALUE1
242    }
243    #[doc = "Over complete DMA block transfer"]
244    #[inline(always)]
245    pub fn is_value2(&self) -> bool {
246        *self == LOCK_CH_L_A::VALUE2
247    }
248    #[doc = "Over complete DMA transaction"]
249    #[inline(always)]
250    pub fn is_value3(&self) -> bool {
251        *self == LOCK_CH_L_A::VALUE3
252    }
253}
254#[doc = "Field `LOCK_CH_L` writer - Channel Lock Level"]
255pub type LOCK_CH_L_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LOCK_CH_L_A>;
256impl<'a, REG> LOCK_CH_L_W<'a, REG>
257where
258    REG: crate::Writable + crate::RegisterSpec,
259    REG::Ux: From<u8>,
260{
261    #[doc = "Over complete DMA transfer"]
262    #[inline(always)]
263    pub fn value1(self) -> &'a mut crate::W<REG> {
264        self.variant(LOCK_CH_L_A::VALUE1)
265    }
266    #[doc = "Over complete DMA block transfer"]
267    #[inline(always)]
268    pub fn value2(self) -> &'a mut crate::W<REG> {
269        self.variant(LOCK_CH_L_A::VALUE2)
270    }
271    #[doc = "Over complete DMA transaction"]
272    #[inline(always)]
273    pub fn value3(self) -> &'a mut crate::W<REG> {
274        self.variant(LOCK_CH_L_A::VALUE3)
275    }
276}
277#[doc = "Bus Lock Level\n\nValue on reset: 0"]
278#[derive(Clone, Copy, Debug, PartialEq, Eq)]
279#[repr(u8)]
280pub enum LOCK_B_L_A {
281    #[doc = "0: Over complete DMA transfer"]
282    VALUE1 = 0,
283    #[doc = "1: Over complete DMA block transfer"]
284    VALUE2 = 1,
285    #[doc = "2: Over complete DMA transaction"]
286    VALUE3 = 2,
287}
288impl From<LOCK_B_L_A> for u8 {
289    #[inline(always)]
290    fn from(variant: LOCK_B_L_A) -> Self {
291        variant as _
292    }
293}
294impl crate::FieldSpec for LOCK_B_L_A {
295    type Ux = u8;
296}
297impl crate::IsEnum for LOCK_B_L_A {}
298#[doc = "Field `LOCK_B_L` reader - Bus Lock Level"]
299pub type LOCK_B_L_R = crate::FieldReader<LOCK_B_L_A>;
300impl LOCK_B_L_R {
301    #[doc = "Get enumerated values variant"]
302    #[inline(always)]
303    pub const fn variant(&self) -> Option<LOCK_B_L_A> {
304        match self.bits {
305            0 => Some(LOCK_B_L_A::VALUE1),
306            1 => Some(LOCK_B_L_A::VALUE2),
307            2 => Some(LOCK_B_L_A::VALUE3),
308            _ => None,
309        }
310    }
311    #[doc = "Over complete DMA transfer"]
312    #[inline(always)]
313    pub fn is_value1(&self) -> bool {
314        *self == LOCK_B_L_A::VALUE1
315    }
316    #[doc = "Over complete DMA block transfer"]
317    #[inline(always)]
318    pub fn is_value2(&self) -> bool {
319        *self == LOCK_B_L_A::VALUE2
320    }
321    #[doc = "Over complete DMA transaction"]
322    #[inline(always)]
323    pub fn is_value3(&self) -> bool {
324        *self == LOCK_B_L_A::VALUE3
325    }
326}
327#[doc = "Field `LOCK_B_L` writer - Bus Lock Level"]
328pub type LOCK_B_L_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LOCK_B_L_A>;
329impl<'a, REG> LOCK_B_L_W<'a, REG>
330where
331    REG: crate::Writable + crate::RegisterSpec,
332    REG::Ux: From<u8>,
333{
334    #[doc = "Over complete DMA transfer"]
335    #[inline(always)]
336    pub fn value1(self) -> &'a mut crate::W<REG> {
337        self.variant(LOCK_B_L_A::VALUE1)
338    }
339    #[doc = "Over complete DMA block transfer"]
340    #[inline(always)]
341    pub fn value2(self) -> &'a mut crate::W<REG> {
342        self.variant(LOCK_B_L_A::VALUE2)
343    }
344    #[doc = "Over complete DMA transaction"]
345    #[inline(always)]
346    pub fn value3(self) -> &'a mut crate::W<REG> {
347        self.variant(LOCK_B_L_A::VALUE3)
348    }
349}
350#[doc = "Field `LOCK_CH` reader - Channel Lock Bit"]
351pub type LOCK_CH_R = crate::BitReader;
352#[doc = "Field `LOCK_CH` writer - Channel Lock Bit"]
353pub type LOCK_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
354#[doc = "Field `LOCK_B` reader - Bus Lock Bit"]
355pub type LOCK_B_R = crate::BitReader;
356#[doc = "Field `LOCK_B` writer - Bus Lock Bit"]
357pub type LOCK_B_W<'a, REG> = crate::BitWriter<'a, REG>;
358#[doc = "Destination Handshaking Interface Polarity\n\nValue on reset: 0"]
359#[derive(Clone, Copy, Debug, PartialEq, Eq)]
360pub enum DST_HS_POL_A {
361    #[doc = "0: Active high"]
362    VALUE1 = 0,
363    #[doc = "1: Active low"]
364    VALUE2 = 1,
365}
366impl From<DST_HS_POL_A> for bool {
367    #[inline(always)]
368    fn from(variant: DST_HS_POL_A) -> Self {
369        variant as u8 != 0
370    }
371}
372#[doc = "Field `DST_HS_POL` reader - Destination Handshaking Interface Polarity"]
373pub type DST_HS_POL_R = crate::BitReader<DST_HS_POL_A>;
374impl DST_HS_POL_R {
375    #[doc = "Get enumerated values variant"]
376    #[inline(always)]
377    pub const fn variant(&self) -> DST_HS_POL_A {
378        match self.bits {
379            false => DST_HS_POL_A::VALUE1,
380            true => DST_HS_POL_A::VALUE2,
381        }
382    }
383    #[doc = "Active high"]
384    #[inline(always)]
385    pub fn is_value1(&self) -> bool {
386        *self == DST_HS_POL_A::VALUE1
387    }
388    #[doc = "Active low"]
389    #[inline(always)]
390    pub fn is_value2(&self) -> bool {
391        *self == DST_HS_POL_A::VALUE2
392    }
393}
394#[doc = "Field `DST_HS_POL` writer - Destination Handshaking Interface Polarity"]
395pub type DST_HS_POL_W<'a, REG> = crate::BitWriter<'a, REG, DST_HS_POL_A>;
396impl<'a, REG> DST_HS_POL_W<'a, REG>
397where
398    REG: crate::Writable + crate::RegisterSpec,
399{
400    #[doc = "Active high"]
401    #[inline(always)]
402    pub fn value1(self) -> &'a mut crate::W<REG> {
403        self.variant(DST_HS_POL_A::VALUE1)
404    }
405    #[doc = "Active low"]
406    #[inline(always)]
407    pub fn value2(self) -> &'a mut crate::W<REG> {
408        self.variant(DST_HS_POL_A::VALUE2)
409    }
410}
411#[doc = "Source Handshaking Interface Polarity\n\nValue on reset: 0"]
412#[derive(Clone, Copy, Debug, PartialEq, Eq)]
413pub enum SRC_HS_POL_A {
414    #[doc = "0: Active high"]
415    VALUE1 = 0,
416    #[doc = "1: Active low"]
417    VALUE2 = 1,
418}
419impl From<SRC_HS_POL_A> for bool {
420    #[inline(always)]
421    fn from(variant: SRC_HS_POL_A) -> Self {
422        variant as u8 != 0
423    }
424}
425#[doc = "Field `SRC_HS_POL` reader - Source Handshaking Interface Polarity"]
426pub type SRC_HS_POL_R = crate::BitReader<SRC_HS_POL_A>;
427impl SRC_HS_POL_R {
428    #[doc = "Get enumerated values variant"]
429    #[inline(always)]
430    pub const fn variant(&self) -> SRC_HS_POL_A {
431        match self.bits {
432            false => SRC_HS_POL_A::VALUE1,
433            true => SRC_HS_POL_A::VALUE2,
434        }
435    }
436    #[doc = "Active high"]
437    #[inline(always)]
438    pub fn is_value1(&self) -> bool {
439        *self == SRC_HS_POL_A::VALUE1
440    }
441    #[doc = "Active low"]
442    #[inline(always)]
443    pub fn is_value2(&self) -> bool {
444        *self == SRC_HS_POL_A::VALUE2
445    }
446}
447#[doc = "Field `SRC_HS_POL` writer - Source Handshaking Interface Polarity"]
448pub type SRC_HS_POL_W<'a, REG> = crate::BitWriter<'a, REG, SRC_HS_POL_A>;
449impl<'a, REG> SRC_HS_POL_W<'a, REG>
450where
451    REG: crate::Writable + crate::RegisterSpec,
452{
453    #[doc = "Active high"]
454    #[inline(always)]
455    pub fn value1(self) -> &'a mut crate::W<REG> {
456        self.variant(SRC_HS_POL_A::VALUE1)
457    }
458    #[doc = "Active low"]
459    #[inline(always)]
460    pub fn value2(self) -> &'a mut crate::W<REG> {
461        self.variant(SRC_HS_POL_A::VALUE2)
462    }
463}
464#[doc = "Field `MAX_ABRST` reader - Maximum AMBA Burst Length"]
465pub type MAX_ABRST_R = crate::FieldReader<u16>;
466#[doc = "Field `MAX_ABRST` writer - Maximum AMBA Burst Length"]
467pub type MAX_ABRST_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
468impl R {
469    #[doc = "Bits 5:7 - Channel priority"]
470    #[inline(always)]
471    pub fn ch_prior(&self) -> CH_PRIOR_R {
472        CH_PRIOR_R::new(((self.bits >> 5) & 7) as u8)
473    }
474    #[doc = "Bit 8 - Channel Suspend"]
475    #[inline(always)]
476    pub fn ch_susp(&self) -> CH_SUSP_R {
477        CH_SUSP_R::new(((self.bits >> 8) & 1) != 0)
478    }
479    #[doc = "Bit 9 - Indicates if there is data left in the channel FIFO"]
480    #[inline(always)]
481    pub fn fifo_empty(&self) -> FIFO_EMPTY_R {
482        FIFO_EMPTY_R::new(((self.bits >> 9) & 1) != 0)
483    }
484    #[doc = "Bit 10 - Destination Software or Hardware Handshaking Select"]
485    #[inline(always)]
486    pub fn hs_sel_dst(&self) -> HS_SEL_DST_R {
487        HS_SEL_DST_R::new(((self.bits >> 10) & 1) != 0)
488    }
489    #[doc = "Bit 11 - Source Software or Hardware Handshaking Select"]
490    #[inline(always)]
491    pub fn hs_sel_src(&self) -> HS_SEL_SRC_R {
492        HS_SEL_SRC_R::new(((self.bits >> 11) & 1) != 0)
493    }
494    #[doc = "Bits 12:13 - Channel Lock Level"]
495    #[inline(always)]
496    pub fn lock_ch_l(&self) -> LOCK_CH_L_R {
497        LOCK_CH_L_R::new(((self.bits >> 12) & 3) as u8)
498    }
499    #[doc = "Bits 14:15 - Bus Lock Level"]
500    #[inline(always)]
501    pub fn lock_b_l(&self) -> LOCK_B_L_R {
502        LOCK_B_L_R::new(((self.bits >> 14) & 3) as u8)
503    }
504    #[doc = "Bit 16 - Channel Lock Bit"]
505    #[inline(always)]
506    pub fn lock_ch(&self) -> LOCK_CH_R {
507        LOCK_CH_R::new(((self.bits >> 16) & 1) != 0)
508    }
509    #[doc = "Bit 17 - Bus Lock Bit"]
510    #[inline(always)]
511    pub fn lock_b(&self) -> LOCK_B_R {
512        LOCK_B_R::new(((self.bits >> 17) & 1) != 0)
513    }
514    #[doc = "Bit 18 - Destination Handshaking Interface Polarity"]
515    #[inline(always)]
516    pub fn dst_hs_pol(&self) -> DST_HS_POL_R {
517        DST_HS_POL_R::new(((self.bits >> 18) & 1) != 0)
518    }
519    #[doc = "Bit 19 - Source Handshaking Interface Polarity"]
520    #[inline(always)]
521    pub fn src_hs_pol(&self) -> SRC_HS_POL_R {
522        SRC_HS_POL_R::new(((self.bits >> 19) & 1) != 0)
523    }
524    #[doc = "Bits 20:29 - Maximum AMBA Burst Length"]
525    #[inline(always)]
526    pub fn max_abrst(&self) -> MAX_ABRST_R {
527        MAX_ABRST_R::new(((self.bits >> 20) & 0x03ff) as u16)
528    }
529}
530impl W {
531    #[doc = "Bits 5:7 - Channel priority"]
532    #[inline(always)]
533    pub fn ch_prior(&mut self) -> CH_PRIOR_W<CFGL_SPEC> {
534        CH_PRIOR_W::new(self, 5)
535    }
536    #[doc = "Bit 8 - Channel Suspend"]
537    #[inline(always)]
538    pub fn ch_susp(&mut self) -> CH_SUSP_W<CFGL_SPEC> {
539        CH_SUSP_W::new(self, 8)
540    }
541    #[doc = "Bit 10 - Destination Software or Hardware Handshaking Select"]
542    #[inline(always)]
543    pub fn hs_sel_dst(&mut self) -> HS_SEL_DST_W<CFGL_SPEC> {
544        HS_SEL_DST_W::new(self, 10)
545    }
546    #[doc = "Bit 11 - Source Software or Hardware Handshaking Select"]
547    #[inline(always)]
548    pub fn hs_sel_src(&mut self) -> HS_SEL_SRC_W<CFGL_SPEC> {
549        HS_SEL_SRC_W::new(self, 11)
550    }
551    #[doc = "Bits 12:13 - Channel Lock Level"]
552    #[inline(always)]
553    pub fn lock_ch_l(&mut self) -> LOCK_CH_L_W<CFGL_SPEC> {
554        LOCK_CH_L_W::new(self, 12)
555    }
556    #[doc = "Bits 14:15 - Bus Lock Level"]
557    #[inline(always)]
558    pub fn lock_b_l(&mut self) -> LOCK_B_L_W<CFGL_SPEC> {
559        LOCK_B_L_W::new(self, 14)
560    }
561    #[doc = "Bit 16 - Channel Lock Bit"]
562    #[inline(always)]
563    pub fn lock_ch(&mut self) -> LOCK_CH_W<CFGL_SPEC> {
564        LOCK_CH_W::new(self, 16)
565    }
566    #[doc = "Bit 17 - Bus Lock Bit"]
567    #[inline(always)]
568    pub fn lock_b(&mut self) -> LOCK_B_W<CFGL_SPEC> {
569        LOCK_B_W::new(self, 17)
570    }
571    #[doc = "Bit 18 - Destination Handshaking Interface Polarity"]
572    #[inline(always)]
573    pub fn dst_hs_pol(&mut self) -> DST_HS_POL_W<CFGL_SPEC> {
574        DST_HS_POL_W::new(self, 18)
575    }
576    #[doc = "Bit 19 - Source Handshaking Interface Polarity"]
577    #[inline(always)]
578    pub fn src_hs_pol(&mut self) -> SRC_HS_POL_W<CFGL_SPEC> {
579        SRC_HS_POL_W::new(self, 19)
580    }
581    #[doc = "Bits 20:29 - Maximum AMBA Burst Length"]
582    #[inline(always)]
583    pub fn max_abrst(&mut self) -> MAX_ABRST_W<CFGL_SPEC> {
584        MAX_ABRST_W::new(self, 20)
585    }
586}
587#[doc = "Configuration Register Low\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
588pub struct CFGL_SPEC;
589impl crate::RegisterSpec for CFGL_SPEC {
590    type Ux = u32;
591}
592#[doc = "`read()` method returns [`cfgl::R`](R) reader structure"]
593impl crate::Readable for CFGL_SPEC {}
594#[doc = "`write(|w| ..)` method takes [`cfgl::W`](W) writer structure"]
595impl crate::Writable for CFGL_SPEC {
596    type Safety = crate::Unsafe;
597    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
598    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
599}
600#[doc = "`reset()` method sets CFGL to value 0x0e00"]
601impl crate::Resettable for CFGL_SPEC {
602    const RESET_VALUE: u32 = 0x0e00;
603}
xmc4100/gpdma0_ch2/cfgl.rs

xmc4100/gpdma0_ch2/
cfgl.rs
