xmc4100/scu_reset/
prclr2.rs

1#[doc = "Register `PRCLR2` writer"]
2pub type W = crate::W<PRCLR2_SPEC>;
3#[doc = "WDT Reset Clear\n\nValue on reset: 0"]
4#[derive(Clone, Copy, Debug, PartialEq, Eq)]
5pub enum WDTRS_A {
6    #[doc = "0: No effect"]
7    VALUE1 = 0,
8    #[doc = "1: De-assert reset"]
9    VALUE2 = 1,
10}
11impl From<WDTRS_A> for bool {
12    #[inline(always)]
13    fn from(variant: WDTRS_A) -> Self {
14        variant as u8 != 0
15    }
16}
17#[doc = "Field `WDTRS` writer - WDT Reset Clear"]
18pub type WDTRS_W<'a, REG> = crate::BitWriter<'a, REG, WDTRS_A>;
19impl<'a, REG> WDTRS_W<'a, REG>
20where
21    REG: crate::Writable + crate::RegisterSpec,
22{
23    #[doc = "No effect"]
24    #[inline(always)]
25    pub fn value1(self) -> &'a mut crate::W<REG> {
26        self.variant(WDTRS_A::VALUE1)
27    }
28    #[doc = "De-assert reset"]
29    #[inline(always)]
30    pub fn value2(self) -> &'a mut crate::W<REG> {
31        self.variant(WDTRS_A::VALUE2)
32    }
33}
34#[doc = "DMA0 Reset Clear\n\nValue on reset: 0"]
35#[derive(Clone, Copy, Debug, PartialEq, Eq)]
36pub enum DMA0RS_A {
37    #[doc = "0: No effect"]
38    VALUE1 = 0,
39    #[doc = "1: De-assert reset"]
40    VALUE2 = 1,
41}
42impl From<DMA0RS_A> for bool {
43    #[inline(always)]
44    fn from(variant: DMA0RS_A) -> Self {
45        variant as u8 != 0
46    }
47}
48#[doc = "Field `DMA0RS` writer - DMA0 Reset Clear"]
49pub type DMA0RS_W<'a, REG> = crate::BitWriter<'a, REG, DMA0RS_A>;
50impl<'a, REG> DMA0RS_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    #[doc = "No effect"]
55    #[inline(always)]
56    pub fn value1(self) -> &'a mut crate::W<REG> {
57        self.variant(DMA0RS_A::VALUE1)
58    }
59    #[doc = "De-assert reset"]
60    #[inline(always)]
61    pub fn value2(self) -> &'a mut crate::W<REG> {
62        self.variant(DMA0RS_A::VALUE2)
63    }
64}
65#[doc = "FCE Reset Clear\n\nValue on reset: 0"]
66#[derive(Clone, Copy, Debug, PartialEq, Eq)]
67pub enum FCERS_A {
68    #[doc = "0: No effect"]
69    VALUE1 = 0,
70    #[doc = "1: De-assert reset"]
71    VALUE2 = 1,
72}
73impl From<FCERS_A> for bool {
74    #[inline(always)]
75    fn from(variant: FCERS_A) -> Self {
76        variant as u8 != 0
77    }
78}
79#[doc = "Field `FCERS` writer - FCE Reset Clear"]
80pub type FCERS_W<'a, REG> = crate::BitWriter<'a, REG, FCERS_A>;
81impl<'a, REG> FCERS_W<'a, REG>
82where
83    REG: crate::Writable + crate::RegisterSpec,
84{
85    #[doc = "No effect"]
86    #[inline(always)]
87    pub fn value1(self) -> &'a mut crate::W<REG> {
88        self.variant(FCERS_A::VALUE1)
89    }
90    #[doc = "De-assert reset"]
91    #[inline(always)]
92    pub fn value2(self) -> &'a mut crate::W<REG> {
93        self.variant(FCERS_A::VALUE2)
94    }
95}
96#[doc = "USB Reset Clear\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98pub enum USBRS_A {
99    #[doc = "0: No effect"]
100    VALUE1 = 0,
101    #[doc = "1: De-assert reset"]
102    VALUE2 = 1,
103}
104impl From<USBRS_A> for bool {
105    #[inline(always)]
106    fn from(variant: USBRS_A) -> Self {
107        variant as u8 != 0
108    }
109}
110#[doc = "Field `USBRS` writer - USB Reset Clear"]
111pub type USBRS_W<'a, REG> = crate::BitWriter<'a, REG, USBRS_A>;
112impl<'a, REG> USBRS_W<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115{
116    #[doc = "No effect"]
117    #[inline(always)]
118    pub fn value1(self) -> &'a mut crate::W<REG> {
119        self.variant(USBRS_A::VALUE1)
120    }
121    #[doc = "De-assert reset"]
122    #[inline(always)]
123    pub fn value2(self) -> &'a mut crate::W<REG> {
124        self.variant(USBRS_A::VALUE2)
125    }
126}
127impl W {
128    #[doc = "Bit 1 - WDT Reset Clear"]
129    #[inline(always)]
130    pub fn wdtrs(&mut self) -> WDTRS_W<PRCLR2_SPEC> {
131        WDTRS_W::new(self, 1)
132    }
133    #[doc = "Bit 4 - DMA0 Reset Clear"]
134    #[inline(always)]
135    pub fn dma0rs(&mut self) -> DMA0RS_W<PRCLR2_SPEC> {
136        DMA0RS_W::new(self, 4)
137    }
138    #[doc = "Bit 6 - FCE Reset Clear"]
139    #[inline(always)]
140    pub fn fcers(&mut self) -> FCERS_W<PRCLR2_SPEC> {
141        FCERS_W::new(self, 6)
142    }
143    #[doc = "Bit 7 - USB Reset Clear"]
144    #[inline(always)]
145    pub fn usbrs(&mut self) -> USBRS_W<PRCLR2_SPEC> {
146        USBRS_W::new(self, 7)
147    }
148}
149#[doc = "RCU Peripheral 2 Reset Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prclr2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
150pub struct PRCLR2_SPEC;
151impl crate::RegisterSpec for PRCLR2_SPEC {
152    type Ux = u32;
153}
154#[doc = "`write(|w| ..)` method takes [`prclr2::W`](W) writer structure"]
155impl crate::Writable for PRCLR2_SPEC {
156    type Safety = crate::Unsafe;
157    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
158    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
159}
160#[doc = "`reset()` method sets PRCLR2 to value 0"]
161impl crate::Resettable for PRCLR2_SPEC {
162    const RESET_VALUE: u32 = 0;
163}
xmc4100/scu_reset/prclr2.rs

xmc4100/scu_reset/
prclr2.rs
