x86_pic/
regs.rs

1//! Defines PIC's internal ISR and IRR registers.
2//!
3//! The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register (IRR) and the 
4//! In-Service (ISR). The IRR is used to store all the interrupt levels which are requesting service; and the ISR is used to 
5//! store all the interrupt levels which are being serviced.
6//!
7//! OS shall read those registers when deciding on sending the end of interrupt (EOI command). This way spurious IRQs can be 
8//! prevented and properly handled. 
9
10bitflags::bitflags! {
11    /// Read the Interrupt Request Register (IRR).
12    ///
13    /// Holds an IR1 bit vector with all interrupt events which are
14    /// awaiting to be services. Highest level interrupt is reset when
15    /// the CPU acknowledges it.
16    ///
17    /// The interrupt request register shows the requested interrupts that have been raised
18    /// but are not being acknowledged yet. The highest priority value will be flushed after 
19    /// CPU enters the interrupt handler.
20    #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
21    pub struct IRR: u8 {
22        const IRQ0 = 1;
23        const IRQ1 = 1 << 1;
24        const IRQ2 = 1 << 2;
25        const IRQ3 = 1 << 3;
26        const IRQ4 = 1 << 4;
27        const IRQ5 = 1 << 5;
28        const IRQ6 = 1 << 6;
29        const IRQ7 = 1 << 7;
30    }
31        
32    /// Read the Interrupt Service Register (ISR).    
33    ///
34    /// Tracks IRQ line currently being services. Updated by EOI command. The interrupt status register 
35    /// inside the PIC chip, shows the info about which interrupts are being serviced at that moment. 
36    /// The highest priority value will be flushed after the end_of_interrupt method.
37    #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
38    pub struct ISR: u8 {
39        const IRQ0 = 1;
40        const IRQ1 = 1 << 1;
41        const IRQ2 = 1 << 2;
42        const IRQ3 = 1 << 3;
43        const IRQ4 = 1 << 4;
44        const IRQ5 = 1 << 5;
45        const IRQ6 = 1 << 6;
46        const IRQ7 = 1 << 7;
47    }
48}