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ws63_pac/
lib.rs

1#![doc = "Peripheral access API for WS63 microcontrollers (generated using svd2rust v0.37.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
2#![allow(non_camel_case_types)]
3#![allow(non_snake_case)]
4#![no_std]
5#![cfg_attr(docsrs, feature(doc_cfg))]
6#[doc = r"Number available in the NVIC for configuring priority"]
7pub const NVIC_PRIO_BITS: u8 = 3;
8#[allow(unused_imports)]
9use generic::*;
10#[doc = r"Common register and bit access and modify traits"]
11pub mod generic {
12    use core::marker;
13    #[doc = " Generic peripheral accessor"]
14    pub struct Periph<RB, const A: usize> {
15        _marker: marker::PhantomData<RB>,
16    }
17    unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
18    impl<RB, const A: usize> Periph<RB, A> {
19        #[doc = "Pointer to the register block"]
20        pub const PTR: *const RB = A as *const _;
21        #[doc = "Return the pointer to the register block"]
22        #[inline(always)]
23        pub const fn ptr() -> *const RB {
24            Self::PTR
25        }
26        #[doc = " Steal an instance of this peripheral"]
27        #[doc = ""]
28        #[doc = " # Safety"]
29        #[doc = ""]
30        #[doc = " Ensure that the new instance of the peripheral cannot be used in a way"]
31        #[doc = " that may race with any existing instances, for example by only"]
32        #[doc = " accessing read-only or write-only registers, or by consuming the"]
33        #[doc = " original peripheral and using critical sections to coordinate"]
34        #[doc = " access between multiple new instances."]
35        #[doc = ""]
36        #[doc = " Additionally, other software such as HALs may rely on only one"]
37        #[doc = " peripheral instance existing to ensure memory safety; ensure"]
38        #[doc = " no stolen instances are passed to such software."]
39        pub unsafe fn steal() -> Self {
40            Self {
41                _marker: marker::PhantomData,
42            }
43        }
44    }
45    impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
46        type Target = RB;
47        #[inline(always)]
48        fn deref(&self) -> &Self::Target {
49            unsafe { &*Self::PTR }
50        }
51    }
52    #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
53    pub trait RawReg:
54        Copy
55        + From<bool>
56        + core::ops::BitOr<Output = Self>
57        + core::ops::BitAnd<Output = Self>
58        + core::ops::BitOrAssign
59        + core::ops::BitAndAssign
60        + core::ops::Not<Output = Self>
61        + core::ops::Shl<u8, Output = Self>
62    {
63        #[doc = " Mask for bits of width `WI`"]
64        fn mask<const WI: u8>() -> Self;
65        #[doc = " `0`"]
66        const ZERO: Self;
67        #[doc = " `1`"]
68        const ONE: Self;
69    }
70    macro_rules! raw_reg {
71        ($ U : ty , $ size : literal , $ mask : ident) => {
72            impl RawReg for $U {
73                #[inline(always)]
74                fn mask<const WI: u8>() -> Self {
75                    $mask::<WI>()
76                }
77                const ZERO: Self = 0;
78                const ONE: Self = 1;
79            }
80            const fn $mask<const WI: u8>() -> $U {
81                <$U>::MAX >> ($size - WI)
82            }
83            impl FieldSpec for $U {
84                type Ux = $U;
85            }
86        };
87    }
88    raw_reg!(u8, 8, mask_u8);
89    raw_reg!(u16, 16, mask_u16);
90    raw_reg!(u32, 32, mask_u32);
91    raw_reg!(u64, 64, mask_u64);
92    #[doc = " Raw register type"]
93    pub trait RegisterSpec {
94        #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
95        type Ux: RawReg;
96    }
97    #[doc = " Raw field type"]
98    pub trait FieldSpec: Sized {
99        #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
100        type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
101    }
102    #[doc = " Marker for fields with fixed values"]
103    pub trait IsEnum: FieldSpec {}
104    #[doc = " Trait implemented by readable registers to enable the `read` method."]
105    #[doc = ""]
106    #[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
107    pub trait Readable: RegisterSpec {}
108    #[doc = " Trait implemented by writeable registers."]
109    #[doc = ""]
110    #[doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
111    #[doc = ""]
112    #[doc = " Registers marked with `Readable` can be also be `modify`'ed."]
113    pub trait Writable: RegisterSpec {
114        #[doc = " Is it safe to write any bits to register"]
115        type Safety;
116        #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
117        const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
118        #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
119        const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
120    }
121    #[doc = " Reset value of the register."]
122    #[doc = ""]
123    #[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
124    #[doc = " register by using the `reset` method."]
125    pub trait Resettable: RegisterSpec {
126        #[doc = " Reset value of the register."]
127        const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
128        #[doc = " Reset value of the register."]
129        #[inline(always)]
130        fn reset_value() -> Self::Ux {
131            Self::RESET_VALUE
132        }
133    }
134    #[doc(hidden)]
135    pub mod raw {
136        use super::{BitM, FieldSpec, RegisterSpec, Unsafe, Writable, marker};
137        pub struct R<REG: RegisterSpec> {
138            pub(crate) bits: REG::Ux,
139            pub(super) _reg: marker::PhantomData<REG>,
140        }
141        pub struct W<REG: RegisterSpec> {
142            #[doc = "Writable bits"]
143            pub(crate) bits: REG::Ux,
144            pub(super) _reg: marker::PhantomData<REG>,
145        }
146        pub struct FieldReader<FI = u8>
147        where
148            FI: FieldSpec,
149        {
150            pub(crate) bits: FI::Ux,
151            _reg: marker::PhantomData<FI>,
152        }
153        impl<FI: FieldSpec> FieldReader<FI> {
154            #[doc = " Creates a new instance of the reader."]
155            #[allow(unused)]
156            #[inline(always)]
157            pub(crate) const fn new(bits: FI::Ux) -> Self {
158                Self {
159                    bits,
160                    _reg: marker::PhantomData,
161                }
162            }
163        }
164        pub struct BitReader<FI = bool> {
165            pub(crate) bits: bool,
166            _reg: marker::PhantomData<FI>,
167        }
168        impl<FI> BitReader<FI> {
169            #[doc = " Creates a new instance of the reader."]
170            #[allow(unused)]
171            #[inline(always)]
172            pub(crate) const fn new(bits: bool) -> Self {
173                Self {
174                    bits,
175                    _reg: marker::PhantomData,
176                }
177            }
178        }
179        #[must_use = "after creating `FieldWriter` you need to call field value setting method"]
180        pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
181        where
182            REG: Writable + RegisterSpec,
183            FI: FieldSpec,
184        {
185            pub(crate) w: &'a mut W<REG>,
186            pub(crate) o: u8,
187            _field: marker::PhantomData<(FI, Safety)>,
188        }
189        impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
190        where
191            REG: Writable + RegisterSpec,
192            FI: FieldSpec,
193        {
194            #[doc = " Creates a new instance of the writer"]
195            #[allow(unused)]
196            #[inline(always)]
197            pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
198                Self {
199                    w,
200                    o,
201                    _field: marker::PhantomData,
202                }
203            }
204        }
205        #[must_use = "after creating `BitWriter` you need to call bit setting method"]
206        pub struct BitWriter<'a, REG, FI = bool, M = BitM>
207        where
208            REG: Writable + RegisterSpec,
209            bool: From<FI>,
210        {
211            pub(crate) w: &'a mut W<REG>,
212            pub(crate) o: u8,
213            _field: marker::PhantomData<(FI, M)>,
214        }
215        impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M>
216        where
217            REG: Writable + RegisterSpec,
218            bool: From<FI>,
219        {
220            #[doc = " Creates a new instance of the writer"]
221            #[allow(unused)]
222            #[inline(always)]
223            pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
224                Self {
225                    w,
226                    o,
227                    _field: marker::PhantomData,
228                }
229            }
230        }
231    }
232    #[doc = " Register reader."]
233    #[doc = ""]
234    #[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
235    #[doc = " method."]
236    pub type R<REG> = raw::R<REG>;
237    impl<REG: RegisterSpec> R<REG> {
238        #[doc = " Reads raw bits from register."]
239        #[inline(always)]
240        pub const fn bits(&self) -> REG::Ux {
241            self.bits
242        }
243    }
244    impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
245    where
246        REG::Ux: PartialEq,
247        FI: Copy,
248        REG::Ux: From<FI>,
249    {
250        #[inline(always)]
251        fn eq(&self, other: &FI) -> bool {
252            self.bits.eq(&REG::Ux::from(*other))
253        }
254    }
255    #[doc = " Register writer."]
256    #[doc = ""]
257    #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
258    pub type W<REG> = raw::W<REG>;
259    impl<REG: Writable> W<REG> {
260        #[doc = " Writes raw bits to the register."]
261        #[doc = ""]
262        #[doc = " # Safety"]
263        #[doc = ""]
264        #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
265        #[inline(always)]
266        pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
267            self.bits = bits;
268            self
269        }
270    }
271    impl<REG> W<REG>
272    where
273        REG: Writable<Safety = Safe>,
274    {
275        #[doc = " Writes raw bits to the register."]
276        #[inline(always)]
277        pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
278            self.bits = bits;
279            self
280        }
281    }
282    #[doc = " Field reader."]
283    #[doc = ""]
284    #[doc = " Result of the `read` methods of fields."]
285    pub type FieldReader<FI = u8> = raw::FieldReader<FI>;
286    #[doc = " Bit-wise field reader"]
287    pub type BitReader<FI = bool> = raw::BitReader<FI>;
288    impl<FI: FieldSpec> FieldReader<FI> {
289        #[doc = " Reads raw bits from field."]
290        #[inline(always)]
291        pub const fn bits(&self) -> FI::Ux {
292            self.bits
293        }
294    }
295    impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
296        fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
297            core::fmt::Debug::fmt(&self.bits, f)
298        }
299    }
300    impl<FI> PartialEq<FI> for FieldReader<FI>
301    where
302        FI: FieldSpec + Copy,
303    {
304        #[inline(always)]
305        fn eq(&self, other: &FI) -> bool {
306            self.bits.eq(&FI::Ux::from(*other))
307        }
308    }
309    impl<FI> PartialEq<FI> for BitReader<FI>
310    where
311        FI: Copy,
312        bool: From<FI>,
313    {
314        #[inline(always)]
315        fn eq(&self, other: &FI) -> bool {
316            self.bits.eq(&bool::from(*other))
317        }
318    }
319    impl<FI> BitReader<FI> {
320        #[doc = " Value of the field as raw bits."]
321        #[inline(always)]
322        pub const fn bit(&self) -> bool {
323            self.bits
324        }
325        #[doc = " Returns `true` if the bit is clear (0)."]
326        #[inline(always)]
327        pub const fn bit_is_clear(&self) -> bool {
328            !self.bit()
329        }
330        #[doc = " Returns `true` if the bit is set (1)."]
331        #[inline(always)]
332        pub const fn bit_is_set(&self) -> bool {
333            self.bit()
334        }
335    }
336    impl<FI> core::fmt::Debug for BitReader<FI> {
337        fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
338            core::fmt::Debug::fmt(&self.bits, f)
339        }
340    }
341    #[doc = " Marker for register/field writers which can take any value of specified width"]
342    pub struct Safe;
343    #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
344    pub struct Unsafe;
345    #[doc = " Marker for field writers are safe to write in specified inclusive range"]
346    pub struct Range<const MIN: u64, const MAX: u64>;
347    #[doc = " Marker for field writers are safe to write in specified inclusive range"]
348    pub struct RangeFrom<const MIN: u64>;
349    #[doc = " Marker for field writers are safe to write in specified inclusive range"]
350    pub struct RangeTo<const MAX: u64>;
351    #[doc = " Write field Proxy"]
352    pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
353        raw::FieldWriter<'a, REG, WI, FI, Safety>;
354    impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
355    where
356        REG: Writable + RegisterSpec,
357        FI: FieldSpec,
358    {
359        #[doc = " Field width"]
360        pub const WIDTH: u8 = WI;
361        #[doc = " Field width"]
362        #[inline(always)]
363        pub const fn width(&self) -> u8 {
364            WI
365        }
366        #[doc = " Field offset"]
367        #[inline(always)]
368        pub const fn offset(&self) -> u8 {
369            self.o
370        }
371    }
372    impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
373    where
374        REG: Writable + RegisterSpec,
375        FI: FieldSpec,
376        REG::Ux: From<FI::Ux>,
377    {
378        #[doc = " Writes raw bits to the field"]
379        #[doc = ""]
380        #[doc = " # Safety"]
381        #[doc = ""]
382        #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
383        #[inline(always)]
384        pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
385            self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
386            self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
387            self.w
388        }
389    }
390    impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
391    where
392        REG: Writable + RegisterSpec,
393        FI: FieldSpec,
394        REG::Ux: From<FI::Ux>,
395    {
396        #[doc = " Writes raw bits to the field"]
397        #[inline(always)]
398        pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
399            unsafe { self.bits(value) }
400        }
401    }
402    impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
403        FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
404    where
405        REG: Writable + RegisterSpec,
406        FI: FieldSpec,
407        REG::Ux: From<FI::Ux>,
408        u64: From<FI::Ux>,
409    {
410        #[doc = " Writes raw bits to the field"]
411        #[inline(always)]
412        pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
413            {
414                let value = u64::from(value);
415                assert!(value >= MIN && value <= MAX);
416            }
417            unsafe { self.bits(value) }
418        }
419    }
420    impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
421    where
422        REG: Writable + RegisterSpec,
423        FI: FieldSpec,
424        REG::Ux: From<FI::Ux>,
425        u64: From<FI::Ux>,
426    {
427        #[doc = " Writes raw bits to the field"]
428        #[inline(always)]
429        pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
430            {
431                let value = u64::from(value);
432                assert!(value >= MIN);
433            }
434            unsafe { self.bits(value) }
435        }
436    }
437    impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
438    where
439        REG: Writable + RegisterSpec,
440        FI: FieldSpec,
441        REG::Ux: From<FI::Ux>,
442        u64: From<FI::Ux>,
443    {
444        #[doc = " Writes raw bits to the field"]
445        #[inline(always)]
446        pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
447            {
448                let value = u64::from(value);
449                assert!(value <= MAX);
450            }
451            unsafe { self.bits(value) }
452        }
453    }
454    impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
455    where
456        REG: Writable + RegisterSpec,
457        FI: IsEnum,
458        REG::Ux: From<FI::Ux>,
459    {
460        #[doc = " Writes `variant` to the field"]
461        #[inline(always)]
462        pub fn variant(self, variant: FI) -> &'a mut W<REG> {
463            unsafe { self.bits(FI::Ux::from(variant)) }
464        }
465    }
466    macro_rules! bit_proxy {
467        ($ writer : ident , $ mwv : ident) => {
468            #[doc(hidden)]
469            pub struct $mwv;
470            #[doc = " Bit-wise write field proxy"]
471            pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>;
472            impl<'a, REG, FI> $writer<'a, REG, FI>
473            where
474                REG: Writable + RegisterSpec,
475                bool: From<FI>,
476            {
477                #[doc = " Field width"]
478                pub const WIDTH: u8 = 1;
479                #[doc = " Field width"]
480                #[inline(always)]
481                pub const fn width(&self) -> u8 {
482                    Self::WIDTH
483                }
484                #[doc = " Field offset"]
485                #[inline(always)]
486                pub const fn offset(&self) -> u8 {
487                    self.o
488                }
489                #[doc = " Writes bit to the field"]
490                #[inline(always)]
491                pub fn bit(self, value: bool) -> &'a mut W<REG> {
492                    self.w.bits &= !(REG::Ux::ONE << self.o);
493                    self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
494                    self.w
495                }
496                #[doc = " Writes `variant` to the field"]
497                #[inline(always)]
498                pub fn variant(self, variant: FI) -> &'a mut W<REG> {
499                    self.bit(bool::from(variant))
500                }
501            }
502        };
503    }
504    bit_proxy!(BitWriter, BitM);
505    bit_proxy!(BitWriter1S, Bit1S);
506    bit_proxy!(BitWriter0C, Bit0C);
507    bit_proxy!(BitWriter1C, Bit1C);
508    bit_proxy!(BitWriter0S, Bit0S);
509    bit_proxy!(BitWriter1T, Bit1T);
510    bit_proxy!(BitWriter0T, Bit0T);
511    impl<'a, REG, FI> BitWriter<'a, REG, FI>
512    where
513        REG: Writable + RegisterSpec,
514        bool: From<FI>,
515    {
516        #[doc = " Sets the field bit"]
517        #[inline(always)]
518        pub fn set_bit(self) -> &'a mut W<REG> {
519            self.w.bits |= REG::Ux::ONE << self.o;
520            self.w
521        }
522        #[doc = " Clears the field bit"]
523        #[inline(always)]
524        pub fn clear_bit(self) -> &'a mut W<REG> {
525            self.w.bits &= !(REG::Ux::ONE << self.o);
526            self.w
527        }
528    }
529    impl<'a, REG, FI> BitWriter1S<'a, REG, FI>
530    where
531        REG: Writable + RegisterSpec,
532        bool: From<FI>,
533    {
534        #[doc = " Sets the field bit"]
535        #[inline(always)]
536        pub fn set_bit(self) -> &'a mut W<REG> {
537            self.w.bits |= REG::Ux::ONE << self.o;
538            self.w
539        }
540    }
541    impl<'a, REG, FI> BitWriter0C<'a, REG, FI>
542    where
543        REG: Writable + RegisterSpec,
544        bool: From<FI>,
545    {
546        #[doc = " Clears the field bit"]
547        #[inline(always)]
548        pub fn clear_bit(self) -> &'a mut W<REG> {
549            self.w.bits &= !(REG::Ux::ONE << self.o);
550            self.w
551        }
552    }
553    impl<'a, REG, FI> BitWriter1C<'a, REG, FI>
554    where
555        REG: Writable + RegisterSpec,
556        bool: From<FI>,
557    {
558        #[doc = "Clears the field bit by passing one"]
559        #[inline(always)]
560        pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
561            self.w.bits |= REG::Ux::ONE << self.o;
562            self.w
563        }
564    }
565    impl<'a, REG, FI> BitWriter0S<'a, REG, FI>
566    where
567        REG: Writable + RegisterSpec,
568        bool: From<FI>,
569    {
570        #[doc = "Sets the field bit by passing zero"]
571        #[inline(always)]
572        pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
573            self.w.bits &= !(REG::Ux::ONE << self.o);
574            self.w
575        }
576    }
577    impl<'a, REG, FI> BitWriter1T<'a, REG, FI>
578    where
579        REG: Writable + RegisterSpec,
580        bool: From<FI>,
581    {
582        #[doc = "Toggle the field bit by passing one"]
583        #[inline(always)]
584        pub fn toggle_bit(self) -> &'a mut W<REG> {
585            self.w.bits |= REG::Ux::ONE << self.o;
586            self.w
587        }
588    }
589    impl<'a, REG, FI> BitWriter0T<'a, REG, FI>
590    where
591        REG: Writable + RegisterSpec,
592        bool: From<FI>,
593    {
594        #[doc = "Toggle the field bit by passing zero"]
595        #[inline(always)]
596        pub fn toggle_bit(self) -> &'a mut W<REG> {
597            self.w.bits &= !(REG::Ux::ONE << self.o);
598            self.w
599        }
600    }
601    #[doc = " This structure provides volatile access to registers."]
602    #[repr(transparent)]
603    pub struct Reg<REG: RegisterSpec> {
604        register: vcell::VolatileCell<REG::Ux>,
605        _marker: marker::PhantomData<REG>,
606    }
607    unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
608    impl<REG: RegisterSpec> Reg<REG> {
609        #[doc = " Returns the underlying memory address of register."]
610        #[doc = ""]
611        #[doc = " ```ignore"]
612        #[doc = " let reg_ptr = periph.reg.as_ptr();"]
613        #[doc = " ```"]
614        #[inline(always)]
615        pub fn as_ptr(&self) -> *mut REG::Ux {
616            self.register.as_ptr()
617        }
618    }
619    impl<REG: Readable> Reg<REG> {
620        #[doc = " Reads the contents of a `Readable` register."]
621        #[doc = ""]
622        #[doc = " You can read the raw contents of a register by using `bits`:"]
623        #[doc = " ```ignore"]
624        #[doc = " let bits = periph.reg.read().bits();"]
625        #[doc = " ```"]
626        #[doc = " or get the content of a particular field of a register:"]
627        #[doc = " ```ignore"]
628        #[doc = " let reader = periph.reg.read();"]
629        #[doc = " let bits = reader.field1().bits();"]
630        #[doc = " let flag = reader.field2().bit_is_set();"]
631        #[doc = " ```"]
632        #[inline(always)]
633        pub fn read(&self) -> R<REG> {
634            R {
635                bits: self.register.get(),
636                _reg: marker::PhantomData,
637            }
638        }
639    }
640    impl<REG: Resettable + Writable> Reg<REG> {
641        #[doc = " Writes the reset value to `Writable` register."]
642        #[doc = ""]
643        #[doc = " Resets the register to its initial state."]
644        #[inline(always)]
645        pub fn reset(&self) {
646            self.register.set(REG::RESET_VALUE)
647        }
648        #[doc = " Writes bits to a `Writable` register."]
649        #[doc = ""]
650        #[doc = " You can write raw bits into a register:"]
651        #[doc = " ```ignore"]
652        #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
653        #[doc = " ```"]
654        #[doc = " or write only the fields you need:"]
655        #[doc = " ```ignore"]
656        #[doc = " periph.reg.write(|w| w"]
657        #[doc = "     .field1().bits(newfield1bits)"]
658        #[doc = "     .field2().set_bit()"]
659        #[doc = "     .field3().variant(VARIANT)"]
660        #[doc = " );"]
661        #[doc = " ```"]
662        #[doc = " or an alternative way of saying the same:"]
663        #[doc = " ```ignore"]
664        #[doc = " periph.reg.write(|w| {"]
665        #[doc = "     w.field1().bits(newfield1bits);"]
666        #[doc = "     w.field2().set_bit();"]
667        #[doc = "     w.field3().variant(VARIANT)"]
668        #[doc = " });"]
669        #[doc = " ```"]
670        #[doc = " In the latter case, other fields will be set to their reset value."]
671        #[inline(always)]
672        pub fn write<F>(&self, f: F) -> REG::Ux
673        where
674            F: FnOnce(&mut W<REG>) -> &mut W<REG>,
675        {
676            let value = f(&mut W {
677                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
678                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
679                _reg: marker::PhantomData,
680            })
681            .bits;
682            self.register.set(value);
683            value
684        }
685        #[doc = " Writes bits to a `Writable` register and produce a value."]
686        #[doc = ""]
687        #[doc = " You can write raw bits into a register:"]
688        #[doc = " ```ignore"]
689        #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
690        #[doc = " ```"]
691        #[doc = " or write only the fields you need:"]
692        #[doc = " ```ignore"]
693        #[doc = " periph.reg.write_and(|w| {"]
694        #[doc = "     w.field1().bits(newfield1bits)"]
695        #[doc = "         .field2().set_bit()"]
696        #[doc = "         .field3().variant(VARIANT);"]
697        #[doc = " });"]
698        #[doc = " ```"]
699        #[doc = " or an alternative way of saying the same:"]
700        #[doc = " ```ignore"]
701        #[doc = " periph.reg.write_and(|w| {"]
702        #[doc = "     w.field1().bits(newfield1bits);"]
703        #[doc = "     w.field2().set_bit();"]
704        #[doc = "     w.field3().variant(VARIANT);"]
705        #[doc = " });"]
706        #[doc = " ```"]
707        #[doc = " In the latter case, other fields will be set to their reset value."]
708        #[doc = ""]
709        #[doc = " Values can be returned from the closure:"]
710        #[doc = " ```ignore"]
711        #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
712        #[doc = " ```"]
713        #[inline(always)]
714        pub fn from_write<F, T>(&self, f: F) -> T
715        where
716            F: FnOnce(&mut W<REG>) -> T,
717        {
718            let mut writer = W {
719                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
720                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
721                _reg: marker::PhantomData,
722            };
723            let result = f(&mut writer);
724            self.register.set(writer.bits);
725            result
726        }
727    }
728    impl<REG: Writable> Reg<REG> {
729        #[doc = " Writes 0 to a `Writable` register."]
730        #[doc = ""]
731        #[doc = " Similar to `write`, but unused bits will contain 0."]
732        #[doc = ""]
733        #[doc = " # Safety"]
734        #[doc = ""]
735        #[doc = " Unsafe to use with registers which don't allow to write 0."]
736        #[inline(always)]
737        pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
738        where
739            F: FnOnce(&mut W<REG>) -> &mut W<REG>,
740        {
741            let value = f(&mut W {
742                bits: REG::Ux::ZERO,
743                _reg: marker::PhantomData,
744            })
745            .bits;
746            self.register.set(value);
747            value
748        }
749        #[doc = " Writes 0 to a `Writable` register and produces a value."]
750        #[doc = ""]
751        #[doc = " Similar to `write`, but unused bits will contain 0."]
752        #[doc = ""]
753        #[doc = " # Safety"]
754        #[doc = ""]
755        #[doc = " Unsafe to use with registers which don't allow to write 0."]
756        #[inline(always)]
757        pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
758        where
759            F: FnOnce(&mut W<REG>) -> T,
760        {
761            let mut writer = W {
762                bits: REG::Ux::ZERO,
763                _reg: marker::PhantomData,
764            };
765            let result = f(&mut writer);
766            self.register.set(writer.bits);
767            result
768        }
769    }
770    impl<REG: Readable + Writable> Reg<REG> {
771        #[doc = " Modifies the contents of the register by reading and then writing it."]
772        #[doc = ""]
773        #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
774        #[doc = " ```ignore"]
775        #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
776        #[doc = "    r.bits() | 3"]
777        #[doc = " ) });"]
778        #[doc = " ```"]
779        #[doc = " or"]
780        #[doc = " ```ignore"]
781        #[doc = " periph.reg.modify(|_, w| w"]
782        #[doc = "     .field1().bits(newfield1bits)"]
783        #[doc = "     .field2().set_bit()"]
784        #[doc = "     .field3().variant(VARIANT)"]
785        #[doc = " );"]
786        #[doc = " ```"]
787        #[doc = " or an alternative way of saying the same:"]
788        #[doc = " ```ignore"]
789        #[doc = " periph.reg.modify(|_, w| {"]
790        #[doc = "     w.field1().bits(newfield1bits);"]
791        #[doc = "     w.field2().set_bit();"]
792        #[doc = "     w.field3().variant(VARIANT)"]
793        #[doc = " });"]
794        #[doc = " ```"]
795        #[doc = " Other fields will have the value they had before the call to `modify`."]
796        #[inline(always)]
797        pub fn modify<F>(&self, f: F) -> REG::Ux
798        where
799            for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
800        {
801            let bits = self.register.get();
802            let value = f(
803                &R {
804                    bits,
805                    _reg: marker::PhantomData,
806                },
807                &mut W {
808                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
809                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
810                    _reg: marker::PhantomData,
811                },
812            )
813            .bits;
814            self.register.set(value);
815            value
816        }
817        #[doc = " Modifies the contents of the register by reading and then writing it"]
818        #[doc = " and produces a value."]
819        #[doc = ""]
820        #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
821        #[doc = " ```ignore"]
822        #[doc = " let bits = periph.reg.modify(|r, w| {"]
823        #[doc = "     let new_bits = r.bits() | 3;"]
824        #[doc = "     unsafe {"]
825        #[doc = "         w.bits(new_bits);"]
826        #[doc = "     }"]
827        #[doc = ""]
828        #[doc = "     new_bits"]
829        #[doc = " });"]
830        #[doc = " ```"]
831        #[doc = " or"]
832        #[doc = " ```ignore"]
833        #[doc = " periph.reg.modify(|_, w| {"]
834        #[doc = "     w.field1().bits(newfield1bits)"]
835        #[doc = "         .field2().set_bit()"]
836        #[doc = "         .field3().variant(VARIANT);"]
837        #[doc = " });"]
838        #[doc = " ```"]
839        #[doc = " or an alternative way of saying the same:"]
840        #[doc = " ```ignore"]
841        #[doc = " periph.reg.modify(|_, w| {"]
842        #[doc = "     w.field1().bits(newfield1bits);"]
843        #[doc = "     w.field2().set_bit();"]
844        #[doc = "     w.field3().variant(VARIANT);"]
845        #[doc = " });"]
846        #[doc = " ```"]
847        #[doc = " Other fields will have the value they had before the call to `modify`."]
848        #[inline(always)]
849        pub fn from_modify<F, T>(&self, f: F) -> T
850        where
851            for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
852        {
853            let bits = self.register.get();
854            let mut writer = W {
855                bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
856                _reg: marker::PhantomData,
857            };
858            let result = f(
859                &R {
860                    bits,
861                    _reg: marker::PhantomData,
862                },
863                &mut writer,
864            );
865            self.register.set(writer.bits);
866            result
867        }
868    }
869    impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
870    where
871        R<REG>: core::fmt::Debug,
872    {
873        fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
874            core::fmt::Debug::fmt(&self.read(), f)
875        }
876    }
877}
878#[doc = r" Interrupt numbers, priority levels, and HART IDs."]
879pub mod interrupt {
880    #[cfg(target_arch = "riscv32")]
881    pub use riscv::interrupt::Exception;
882    #[cfg(target_arch = "riscv32")]
883    pub use riscv::interrupt::Interrupt as CoreInterrupt;
884    #[cfg(target_arch = "riscv32")]
885    pub use riscv::{
886        ExceptionNumber, HartIdNumber, InterruptNumber, PriorityNumber,
887        interrupt::{disable, enable, free, nested},
888    };
889    #[cfg(target_arch = "riscv32")]
890    pub type Trap = riscv::interrupt::Trap<CoreInterrupt, Exception>;
891    #[doc = r" Retrieves the cause of a trap in the current hart."]
892    #[doc = r""]
893    #[doc = r" If the raw cause is not a valid interrupt or exception for the target, it returns an error."]
894    #[inline]
895    #[cfg(target_arch = "riscv32")]
896    pub fn try_cause() -> riscv::result::Result<Trap> {
897        riscv::interrupt::try_cause()
898    }
899    #[doc = r" Retrieves the cause of a trap in the current hart (machine mode)."]
900    #[doc = r""]
901    #[doc = r" If the raw cause is not a valid interrupt or exception for the target, it panics."]
902    #[inline]
903    #[cfg(target_arch = "riscv32")]
904    pub fn cause() -> Trap {
905        try_cause().unwrap()
906    }
907    #[doc = r" External interrupts. These interrupts are handled by the external peripherals."]
908    #[cfg_attr(target_arch = "riscv32", riscv :: pac_enum (unsafe ExternalInterruptNumber))]
909    #[derive(Debug, Clone, Copy, PartialEq, Eq)]
910    pub enum ExternalInterrupt {
911        #[doc = "26 - TIMER_INT0"]
912        TIMER_INT0 = 26,
913        #[doc = "27 - TIMER_INT1"]
914        TIMER_INT1 = 27,
915        #[doc = "28 - TIMER_INT2"]
916        TIMER_INT2 = 28,
917        #[doc = "29 - RTC_IRQ"]
918        RTC_IRQ = 29,
919        #[doc = "31 - I2C0_INT"]
920        I2C0_INT = 31,
921        #[doc = "32 - I2C1_INT"]
922        I2C1_INT = 32,
923        #[doc = "33 - GPIO_INT0"]
924        GPIO_INT0 = 33,
925        #[doc = "34 - GPIO_INT1"]
926        GPIO_INT1 = 34,
927        #[doc = "35 - GPIO_INT2"]
928        GPIO_INT2 = 35,
929        #[doc = "40 - COEX_WL_INT"]
930        COEX_WL_INT = 40,
931        #[doc = "41 - COEX_BT_INT"]
932        COEX_BT_INT = 41,
933        #[doc = "42 - COEX_WIFI_RESUME_INT"]
934        COEX_WIFI_RESUME_INT = 42,
935        #[doc = "43 - SPI_INT"]
936        SPI_INT = 43,
937        #[doc = "44 - WLPHY_INT"]
938        WLPHY_INT = 44,
939        #[doc = "45 - WLMAC_INT"]
940        WLMAC_INT = 45,
941        #[doc = "46 - BLE_INT"]
942        BLE_INT = 46,
943        #[doc = "47 - SLE_INT"]
944        SLE_INT = 47,
945        #[doc = "48 - TSENSOR_INT"]
946        TSENSOR_INT = 48,
947        #[doc = "49 - PMU_CMU_ERR_INT"]
948        PMU_CMU_ERR_INT = 49,
949        #[doc = "50 - DIAG_INT"]
950        DIAG_INT = 50,
951        #[doc = "51 - I2S_INT"]
952        I2S_INT = 51,
953        #[doc = "52 - QSPI_INT"]
954        QSPI_INT = 52,
955        #[doc = "53 - UART0_INT"]
956        UART0_INT = 53,
957        #[doc = "54 - UART1_INT"]
958        UART1_INT = 54,
959        #[doc = "55 - UART2_INT"]
960        UART2_INT = 55,
961        #[doc = "56 - PWM_ABNOR_INT"]
962        PWM_ABNOR_INT = 56,
963        #[doc = "57 - PWM_CFG_INT"]
964        PWM_CFG_INT = 57,
965        #[doc = "58 - SFC_INT"]
966        SFC_INT = 58,
967        #[doc = "59 - DMA_INT"]
968        DMA_INT = 59,
969        #[doc = "60 - TIMER_ABNOR_INT"]
970        TIMER_ABNOR_INT = 60,
971        #[doc = "61 - I2S_TX_INT"]
972        I2S_TX_INT = 61,
973        #[doc = "62 - I2S_RX_INT"]
974        I2S_RX_INT = 62,
975        #[doc = "63 - PKE_REE_INT"]
976        PKE_REE_INT = 63,
977        #[doc = "64 - SPACC_REE_INT"]
978        SPACC_REE_INT = 64,
979        #[doc = "65 - RKP_REE_INT"]
980        RKP_REE_INT = 65,
981        #[doc = "66 - KLAD_REE_INT"]
982        KLAD_REE_INT = 66,
983        #[doc = "69 - MAC_MONITOR_INT"]
984        MAC_MONITOR_INT = 69,
985        #[doc = "70 - MEM_MONITOR_INT"]
986        MEM_MONITOR_INT = 70,
987        #[doc = "71 - TCM_MONITOR_INT"]
988        TCM_MONITOR_INT = 71,
989        #[doc = "72 - LSADC_INTR"]
990        LSADC_INTR = 72,
991    }
992}
993#[doc = "System Control 1 - Interrupt Controller"]
994pub type SysCtl1 = crate::Periph<sys_ctl1::RegisterBlock, 0x4400_0000>;
995impl core::fmt::Debug for SysCtl1 {
996    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
997        f.debug_struct("SysCtl1").finish()
998    }
999}
1000#[doc = "System Control 1 - Interrupt Controller"]
1001pub mod sys_ctl1 {
1002    #[repr(C)]
1003    #[doc = "Register block"]
1004    pub struct RegisterBlock {
1005        _reserved0: [u8; 0x40],
1006        nmi_int: NmiInt,
1007        _reserved1: [u8; 0x010c],
1008        soft_int_en: SoftIntEn,
1009        soft_int_set: SoftIntSet,
1010        soft_int_clr: SoftIntClr,
1011        soft_int_sts: SoftIntSts,
1012    }
1013    impl RegisterBlock {
1014        #[doc = "0x40 - WDT interrupt query and NMI interrupt configuration register"]
1015        #[inline(always)]
1016        pub const fn nmi_int(&self) -> &NmiInt {
1017            &self.nmi_int
1018        }
1019        #[doc = "0x150 - CPU soft interrupt enable register"]
1020        #[inline(always)]
1021        pub const fn soft_int_en(&self) -> &SoftIntEn {
1022            &self.soft_int_en
1023        }
1024        #[doc = "0x154 - CPU soft interrupt set register (self-clearing)"]
1025        #[inline(always)]
1026        pub const fn soft_int_set(&self) -> &SoftIntSet {
1027            &self.soft_int_set
1028        }
1029        #[doc = "0x158 - CPU soft interrupt clear register (self-clearing)"]
1030        #[inline(always)]
1031        pub const fn soft_int_clr(&self) -> &SoftIntClr {
1032            &self.soft_int_clr
1033        }
1034        #[doc = "0x15c - CPU soft interrupt status register"]
1035        #[inline(always)]
1036        pub const fn soft_int_sts(&self) -> &SoftIntSts {
1037            &self.soft_int_sts
1038        }
1039    }
1040    #[doc = "NMI_INT (rw) register accessor: WDT interrupt query and NMI interrupt configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmi_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi_int`] module"]
1041    #[doc(alias = "NMI_INT")]
1042    pub type NmiInt = crate::Reg<nmi_int::NmiIntSpec>;
1043    #[doc = "WDT interrupt query and NMI interrupt configuration register"]
1044    pub mod nmi_int {
1045        #[doc = "Register `NMI_INT` reader"]
1046        pub type R = crate::R<NmiIntSpec>;
1047        #[doc = "Register `NMI_INT` writer"]
1048        pub type W = crate::W<NmiIntSpec>;
1049        #[doc = "Field `tee_nmi_int` reader - Software NMI interrupt configuration. 0: pull low CPU NMI soft interrupt; 1: pull high CPU NMI soft interrupt"]
1050        pub type TeeNmiIntR = crate::BitReader;
1051        #[doc = "Field `tee_nmi_int` writer - Software NMI interrupt configuration. 0: pull low CPU NMI soft interrupt; 1: pull high CPU NMI soft interrupt"]
1052        pub type TeeNmiIntW<'a, REG> = crate::BitWriter<'a, REG>;
1053        #[doc = "Field `wdt_int` reader - Watchdog interrupt query. 0: WDT interrupt invalid; 1: WDT interrupt valid"]
1054        pub type WdtIntR = crate::BitReader;
1055        impl R {
1056            #[doc = "Bit 0 - Software NMI interrupt configuration. 0: pull low CPU NMI soft interrupt; 1: pull high CPU NMI soft interrupt"]
1057            #[inline(always)]
1058            pub fn tee_nmi_int(&self) -> TeeNmiIntR {
1059                TeeNmiIntR::new((self.bits & 1) != 0)
1060            }
1061            #[doc = "Bit 1 - Watchdog interrupt query. 0: WDT interrupt invalid; 1: WDT interrupt valid"]
1062            #[inline(always)]
1063            pub fn wdt_int(&self) -> WdtIntR {
1064                WdtIntR::new(((self.bits >> 1) & 1) != 0)
1065            }
1066        }
1067        impl W {
1068            #[doc = "Bit 0 - Software NMI interrupt configuration. 0: pull low CPU NMI soft interrupt; 1: pull high CPU NMI soft interrupt"]
1069            #[inline(always)]
1070            pub fn tee_nmi_int(&mut self) -> TeeNmiIntW<'_, NmiIntSpec> {
1071                TeeNmiIntW::new(self, 0)
1072            }
1073        }
1074        #[doc = "WDT interrupt query and NMI interrupt configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmi_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1075        pub struct NmiIntSpec;
1076        impl crate::RegisterSpec for NmiIntSpec {
1077            type Ux = u32;
1078        }
1079        #[doc = "`read()` method returns [`nmi_int::R`](R) reader structure"]
1080        impl crate::Readable for NmiIntSpec {}
1081        #[doc = "`write(|w| ..)` method takes [`nmi_int::W`](W) writer structure"]
1082        impl crate::Writable for NmiIntSpec {
1083            type Safety = crate::Unsafe;
1084        }
1085        #[doc = "`reset()` method sets NMI_INT to value 0"]
1086        impl crate::Resettable for NmiIntSpec {}
1087    }
1088    #[doc = "SOFT_INT_EN (rw) register accessor: CPU soft interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_int_en`] module"]
1089    #[doc(alias = "SOFT_INT_EN")]
1090    pub type SoftIntEn = crate::Reg<soft_int_en::SoftIntEnSpec>;
1091    #[doc = "CPU soft interrupt enable register"]
1092    pub mod soft_int_en {
1093        #[doc = "Register `SOFT_INT_EN` reader"]
1094        pub type R = crate::R<SoftIntEnSpec>;
1095        #[doc = "Register `SOFT_INT_EN` writer"]
1096        pub type W = crate::W<SoftIntEnSpec>;
1097        #[doc = "Field `soft_int0_en` reader - CPU soft interrupt 0 enable. 0: disabled; 1: enabled"]
1098        pub type SoftInt0EnR = crate::BitReader;
1099        #[doc = "Field `soft_int0_en` writer - CPU soft interrupt 0 enable. 0: disabled; 1: enabled"]
1100        pub type SoftInt0EnW<'a, REG> = crate::BitWriter<'a, REG>;
1101        #[doc = "Field `soft_int1_en` reader - CPU soft interrupt 1 enable. 0: disabled; 1: enabled"]
1102        pub type SoftInt1EnR = crate::BitReader;
1103        #[doc = "Field `soft_int1_en` writer - CPU soft interrupt 1 enable. 0: disabled; 1: enabled"]
1104        pub type SoftInt1EnW<'a, REG> = crate::BitWriter<'a, REG>;
1105        #[doc = "Field `soft_int2_en` reader - CPU soft interrupt 2 enable. 0: disabled; 1: enabled"]
1106        pub type SoftInt2EnR = crate::BitReader;
1107        #[doc = "Field `soft_int2_en` writer - CPU soft interrupt 2 enable. 0: disabled; 1: enabled"]
1108        pub type SoftInt2EnW<'a, REG> = crate::BitWriter<'a, REG>;
1109        #[doc = "Field `soft_int3_en` reader - CPU soft interrupt 3 enable. 0: disabled; 1: enabled"]
1110        pub type SoftInt3EnR = crate::BitReader;
1111        #[doc = "Field `soft_int3_en` writer - CPU soft interrupt 3 enable. 0: disabled; 1: enabled"]
1112        pub type SoftInt3EnW<'a, REG> = crate::BitWriter<'a, REG>;
1113        impl R {
1114            #[doc = "Bit 0 - CPU soft interrupt 0 enable. 0: disabled; 1: enabled"]
1115            #[inline(always)]
1116            pub fn soft_int0_en(&self) -> SoftInt0EnR {
1117                SoftInt0EnR::new((self.bits & 1) != 0)
1118            }
1119            #[doc = "Bit 1 - CPU soft interrupt 1 enable. 0: disabled; 1: enabled"]
1120            #[inline(always)]
1121            pub fn soft_int1_en(&self) -> SoftInt1EnR {
1122                SoftInt1EnR::new(((self.bits >> 1) & 1) != 0)
1123            }
1124            #[doc = "Bit 2 - CPU soft interrupt 2 enable. 0: disabled; 1: enabled"]
1125            #[inline(always)]
1126            pub fn soft_int2_en(&self) -> SoftInt2EnR {
1127                SoftInt2EnR::new(((self.bits >> 2) & 1) != 0)
1128            }
1129            #[doc = "Bit 3 - CPU soft interrupt 3 enable. 0: disabled; 1: enabled"]
1130            #[inline(always)]
1131            pub fn soft_int3_en(&self) -> SoftInt3EnR {
1132                SoftInt3EnR::new(((self.bits >> 3) & 1) != 0)
1133            }
1134        }
1135        impl W {
1136            #[doc = "Bit 0 - CPU soft interrupt 0 enable. 0: disabled; 1: enabled"]
1137            #[inline(always)]
1138            pub fn soft_int0_en(&mut self) -> SoftInt0EnW<'_, SoftIntEnSpec> {
1139                SoftInt0EnW::new(self, 0)
1140            }
1141            #[doc = "Bit 1 - CPU soft interrupt 1 enable. 0: disabled; 1: enabled"]
1142            #[inline(always)]
1143            pub fn soft_int1_en(&mut self) -> SoftInt1EnW<'_, SoftIntEnSpec> {
1144                SoftInt1EnW::new(self, 1)
1145            }
1146            #[doc = "Bit 2 - CPU soft interrupt 2 enable. 0: disabled; 1: enabled"]
1147            #[inline(always)]
1148            pub fn soft_int2_en(&mut self) -> SoftInt2EnW<'_, SoftIntEnSpec> {
1149                SoftInt2EnW::new(self, 2)
1150            }
1151            #[doc = "Bit 3 - CPU soft interrupt 3 enable. 0: disabled; 1: enabled"]
1152            #[inline(always)]
1153            pub fn soft_int3_en(&mut self) -> SoftInt3EnW<'_, SoftIntEnSpec> {
1154                SoftInt3EnW::new(self, 3)
1155            }
1156        }
1157        #[doc = "CPU soft interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1158        pub struct SoftIntEnSpec;
1159        impl crate::RegisterSpec for SoftIntEnSpec {
1160            type Ux = u32;
1161        }
1162        #[doc = "`read()` method returns [`soft_int_en::R`](R) reader structure"]
1163        impl crate::Readable for SoftIntEnSpec {}
1164        #[doc = "`write(|w| ..)` method takes [`soft_int_en::W`](W) writer structure"]
1165        impl crate::Writable for SoftIntEnSpec {
1166            type Safety = crate::Unsafe;
1167        }
1168        #[doc = "`reset()` method sets SOFT_INT_EN to value 0"]
1169        impl crate::Resettable for SoftIntEnSpec {}
1170    }
1171    #[doc = "SOFT_INT_SET (rw) register accessor: CPU soft interrupt set register (self-clearing)\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_int_set`] module"]
1172    #[doc(alias = "SOFT_INT_SET")]
1173    pub type SoftIntSet = crate::Reg<soft_int_set::SoftIntSetSpec>;
1174    #[doc = "CPU soft interrupt set register (self-clearing)"]
1175    pub mod soft_int_set {
1176        #[doc = "Register `SOFT_INT_SET` reader"]
1177        pub type R = crate::R<SoftIntSetSpec>;
1178        #[doc = "Register `SOFT_INT_SET` writer"]
1179        pub type W = crate::W<SoftIntSetSpec>;
1180        #[doc = "Field `soft_int0_set` writer - CPU soft interrupt 0 set. 0: no effect; 1: set effective"]
1181        pub type SoftInt0SetW<'a, REG> = crate::BitWriter<'a, REG>;
1182        #[doc = "Field `soft_int1_set` writer - CPU soft interrupt 1 set. 0: no effect; 1: set effective"]
1183        pub type SoftInt1SetW<'a, REG> = crate::BitWriter<'a, REG>;
1184        #[doc = "Field `soft_int2_set` writer - CPU soft interrupt 2 set. 0: no effect; 1: set effective"]
1185        pub type SoftInt2SetW<'a, REG> = crate::BitWriter<'a, REG>;
1186        #[doc = "Field `soft_int3_set` writer - CPU soft interrupt 3 set. 0: no effect; 1: set effective"]
1187        pub type SoftInt3SetW<'a, REG> = crate::BitWriter<'a, REG>;
1188        impl W {
1189            #[doc = "Bit 0 - CPU soft interrupt 0 set. 0: no effect; 1: set effective"]
1190            #[inline(always)]
1191            pub fn soft_int0_set(&mut self) -> SoftInt0SetW<'_, SoftIntSetSpec> {
1192                SoftInt0SetW::new(self, 0)
1193            }
1194            #[doc = "Bit 1 - CPU soft interrupt 1 set. 0: no effect; 1: set effective"]
1195            #[inline(always)]
1196            pub fn soft_int1_set(&mut self) -> SoftInt1SetW<'_, SoftIntSetSpec> {
1197                SoftInt1SetW::new(self, 1)
1198            }
1199            #[doc = "Bit 2 - CPU soft interrupt 2 set. 0: no effect; 1: set effective"]
1200            #[inline(always)]
1201            pub fn soft_int2_set(&mut self) -> SoftInt2SetW<'_, SoftIntSetSpec> {
1202                SoftInt2SetW::new(self, 2)
1203            }
1204            #[doc = "Bit 3 - CPU soft interrupt 3 set. 0: no effect; 1: set effective"]
1205            #[inline(always)]
1206            pub fn soft_int3_set(&mut self) -> SoftInt3SetW<'_, SoftIntSetSpec> {
1207                SoftInt3SetW::new(self, 3)
1208            }
1209        }
1210        #[doc = "CPU soft interrupt set register (self-clearing)\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1211        pub struct SoftIntSetSpec;
1212        impl crate::RegisterSpec for SoftIntSetSpec {
1213            type Ux = u32;
1214        }
1215        #[doc = "`read()` method returns [`soft_int_set::R`](R) reader structure"]
1216        impl crate::Readable for SoftIntSetSpec {}
1217        #[doc = "`write(|w| ..)` method takes [`soft_int_set::W`](W) writer structure"]
1218        impl crate::Writable for SoftIntSetSpec {
1219            type Safety = crate::Unsafe;
1220        }
1221        #[doc = "`reset()` method sets SOFT_INT_SET to value 0"]
1222        impl crate::Resettable for SoftIntSetSpec {}
1223    }
1224    #[doc = "SOFT_INT_CLR (rw) register accessor: CPU soft interrupt clear register (self-clearing)\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_int_clr`] module"]
1225    #[doc(alias = "SOFT_INT_CLR")]
1226    pub type SoftIntClr = crate::Reg<soft_int_clr::SoftIntClrSpec>;
1227    #[doc = "CPU soft interrupt clear register (self-clearing)"]
1228    pub mod soft_int_clr {
1229        #[doc = "Register `SOFT_INT_CLR` reader"]
1230        pub type R = crate::R<SoftIntClrSpec>;
1231        #[doc = "Register `SOFT_INT_CLR` writer"]
1232        pub type W = crate::W<SoftIntClrSpec>;
1233        #[doc = "Field `soft_int0_clr` writer - CPU soft interrupt 0 clear. 0: no effect; 1: clear effective"]
1234        pub type SoftInt0ClrW<'a, REG> = crate::BitWriter<'a, REG>;
1235        #[doc = "Field `soft_int1_clr` writer - CPU soft interrupt 1 clear. 0: no effect; 1: clear effective"]
1236        pub type SoftInt1ClrW<'a, REG> = crate::BitWriter<'a, REG>;
1237        #[doc = "Field `soft_int2_clr` writer - CPU soft interrupt 2 clear. 0: no effect; 1: clear effective"]
1238        pub type SoftInt2ClrW<'a, REG> = crate::BitWriter<'a, REG>;
1239        #[doc = "Field `soft_int3_clr` writer - CPU soft interrupt 3 clear. 0: no effect; 1: clear effective"]
1240        pub type SoftInt3ClrW<'a, REG> = crate::BitWriter<'a, REG>;
1241        impl W {
1242            #[doc = "Bit 0 - CPU soft interrupt 0 clear. 0: no effect; 1: clear effective"]
1243            #[inline(always)]
1244            pub fn soft_int0_clr(&mut self) -> SoftInt0ClrW<'_, SoftIntClrSpec> {
1245                SoftInt0ClrW::new(self, 0)
1246            }
1247            #[doc = "Bit 1 - CPU soft interrupt 1 clear. 0: no effect; 1: clear effective"]
1248            #[inline(always)]
1249            pub fn soft_int1_clr(&mut self) -> SoftInt1ClrW<'_, SoftIntClrSpec> {
1250                SoftInt1ClrW::new(self, 1)
1251            }
1252            #[doc = "Bit 2 - CPU soft interrupt 2 clear. 0: no effect; 1: clear effective"]
1253            #[inline(always)]
1254            pub fn soft_int2_clr(&mut self) -> SoftInt2ClrW<'_, SoftIntClrSpec> {
1255                SoftInt2ClrW::new(self, 2)
1256            }
1257            #[doc = "Bit 3 - CPU soft interrupt 3 clear. 0: no effect; 1: clear effective"]
1258            #[inline(always)]
1259            pub fn soft_int3_clr(&mut self) -> SoftInt3ClrW<'_, SoftIntClrSpec> {
1260                SoftInt3ClrW::new(self, 3)
1261            }
1262        }
1263        #[doc = "CPU soft interrupt clear register (self-clearing)\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1264        pub struct SoftIntClrSpec;
1265        impl crate::RegisterSpec for SoftIntClrSpec {
1266            type Ux = u32;
1267        }
1268        #[doc = "`read()` method returns [`soft_int_clr::R`](R) reader structure"]
1269        impl crate::Readable for SoftIntClrSpec {}
1270        #[doc = "`write(|w| ..)` method takes [`soft_int_clr::W`](W) writer structure"]
1271        impl crate::Writable for SoftIntClrSpec {
1272            type Safety = crate::Unsafe;
1273        }
1274        #[doc = "`reset()` method sets SOFT_INT_CLR to value 0"]
1275        impl crate::Resettable for SoftIntClrSpec {}
1276    }
1277    #[doc = "SOFT_INT_STS (rw) register accessor: CPU soft interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_int_sts`] module"]
1278    #[doc(alias = "SOFT_INT_STS")]
1279    pub type SoftIntSts = crate::Reg<soft_int_sts::SoftIntStsSpec>;
1280    #[doc = "CPU soft interrupt status register"]
1281    pub mod soft_int_sts {
1282        #[doc = "Register `SOFT_INT_STS` reader"]
1283        pub type R = crate::R<SoftIntStsSpec>;
1284        #[doc = "Register `SOFT_INT_STS` writer"]
1285        pub type W = crate::W<SoftIntStsSpec>;
1286        #[doc = "Field `soft_int0_sts` reader - CPU soft interrupt 0 status. 0: no interrupt; 1: interrupt active"]
1287        pub type SoftInt0StsR = crate::BitReader;
1288        #[doc = "Field `soft_int1_sts` reader - CPU soft interrupt 1 status. 0: no interrupt; 1: interrupt active"]
1289        pub type SoftInt1StsR = crate::BitReader;
1290        #[doc = "Field `soft_int2_sts` reader - CPU soft interrupt 2 status. 0: no interrupt; 1: interrupt active"]
1291        pub type SoftInt2StsR = crate::BitReader;
1292        #[doc = "Field `soft_int3_sts` reader - CPU soft interrupt 3 status. 0: no interrupt; 1: interrupt active"]
1293        pub type SoftInt3StsR = crate::BitReader;
1294        impl R {
1295            #[doc = "Bit 0 - CPU soft interrupt 0 status. 0: no interrupt; 1: interrupt active"]
1296            #[inline(always)]
1297            pub fn soft_int0_sts(&self) -> SoftInt0StsR {
1298                SoftInt0StsR::new((self.bits & 1) != 0)
1299            }
1300            #[doc = "Bit 1 - CPU soft interrupt 1 status. 0: no interrupt; 1: interrupt active"]
1301            #[inline(always)]
1302            pub fn soft_int1_sts(&self) -> SoftInt1StsR {
1303                SoftInt1StsR::new(((self.bits >> 1) & 1) != 0)
1304            }
1305            #[doc = "Bit 2 - CPU soft interrupt 2 status. 0: no interrupt; 1: interrupt active"]
1306            #[inline(always)]
1307            pub fn soft_int2_sts(&self) -> SoftInt2StsR {
1308                SoftInt2StsR::new(((self.bits >> 2) & 1) != 0)
1309            }
1310            #[doc = "Bit 3 - CPU soft interrupt 3 status. 0: no interrupt; 1: interrupt active"]
1311            #[inline(always)]
1312            pub fn soft_int3_sts(&self) -> SoftInt3StsR {
1313                SoftInt3StsR::new(((self.bits >> 3) & 1) != 0)
1314            }
1315        }
1316        impl W {}
1317        #[doc = "CPU soft interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1318        pub struct SoftIntStsSpec;
1319        impl crate::RegisterSpec for SoftIntStsSpec {
1320            type Ux = u32;
1321        }
1322        #[doc = "`read()` method returns [`soft_int_sts::R`](R) reader structure"]
1323        impl crate::Readable for SoftIntStsSpec {}
1324        #[doc = "`write(|w| ..)` method takes [`soft_int_sts::W`](W) writer structure"]
1325        impl crate::Writable for SoftIntStsSpec {
1326            type Safety = crate::Unsafe;
1327        }
1328        #[doc = "`reset()` method sets SOFT_INT_STS to value 0"]
1329        impl crate::Resettable for SoftIntStsSpec {}
1330    }
1331}
1332#[doc = "IO multiplexing and pad control"]
1333pub type IoConfig = crate::Periph<io_config::RegisterBlock, 0x4400_d000>;
1334impl core::fmt::Debug for IoConfig {
1335    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1336        f.debug_struct("IoConfig").finish()
1337    }
1338}
1339#[doc = "IO multiplexing and pad control"]
1340pub mod io_config {
1341    #[repr(C)]
1342    #[doc = "Register block"]
1343    pub struct RegisterBlock {
1344        gpio_00_sel: Gpio00Sel,
1345        gpio_01_sel: Gpio01Sel,
1346        gpio_02_sel: Gpio02Sel,
1347        gpio_03_sel: Gpio03Sel,
1348        gpio_04_sel: Gpio04Sel,
1349        gpio_05_sel: Gpio05Sel,
1350        gpio_06_sel: Gpio06Sel,
1351        gpio_07_sel: Gpio07Sel,
1352        gpio_08_sel: Gpio08Sel,
1353        gpio_09_sel: Gpio09Sel,
1354        gpio_10_sel: Gpio10Sel,
1355        gpio_11_sel: Gpio11Sel,
1356        gpio_12_sel: Gpio12Sel,
1357        gpio_13_sel: Gpio13Sel,
1358        gpio_14_sel: Gpio14Sel,
1359        uart1_txd_sel: Uart1TxdSel,
1360        uart1_rxd_sel: Uart1RxdSel,
1361        uart0_txd_sel: Uart0TxdSel,
1362        uart0_rxd_sel: Uart0RxdSel,
1363        _reserved19: [u8; 0x07b4],
1364        pad_gpio_00_ctrl: PadGpio00Ctrl,
1365        pad_gpio_01_ctrl: PadGpio01Ctrl,
1366        pad_gpio_02_ctrl: PadGpio02Ctrl,
1367        pad_gpio_03_ctrl: PadGpio03Ctrl,
1368        pad_gpio_04_ctrl: PadGpio04Ctrl,
1369        pad_gpio_05_ctrl: PadGpio05Ctrl,
1370        pad_gpio_06_ctrl: PadGpio06Ctrl,
1371        pad_gpio_07_ctrl: PadGpio07Ctrl,
1372        pad_gpio_08_ctrl: PadGpio08Ctrl,
1373        pad_gpio_09_ctrl: PadGpio09Ctrl,
1374        pad_gpio_10_ctrl: PadGpio10Ctrl,
1375        pad_gpio_11_ctrl: PadGpio11Ctrl,
1376        pad_gpio_12_ctrl: PadGpio12Ctrl,
1377        pad_gpio_13_ctrl: PadGpio13Ctrl,
1378        pad_gpio_14_ctrl: PadGpio14Ctrl,
1379        pad_uart1_txd_ctrl: PadUart1TxdCtrl,
1380        pad_uart1_rxd_ctrl: PadUart1RxdCtrl,
1381        pad_uart0_txd_ctrl: PadUart0TxdCtrl,
1382        pad_uart0_rxd_ctrl: PadUart0RxdCtrl,
1383        _reserved38: [u8; 0x1c],
1384        pad_sfc_clk_ctrl: PadSfcClkCtrl,
1385        pad_sfc_csn_ctrl: PadSfcCsnCtrl,
1386        pad_sfc_io0_ctrl: PadSfcIo0Ctrl,
1387        pad_sfc_io1_ctrl: PadSfcIo1Ctrl,
1388        pad_sfc_io2_ctrl: PadSfcIo2Ctrl,
1389        pad_sfc_io3_ctrl: PadSfcIo3Ctrl,
1390    }
1391    impl RegisterBlock {
1392        #[doc = "0x00 - GPIO_00 pin mux select"]
1393        #[inline(always)]
1394        pub const fn gpio_00_sel(&self) -> &Gpio00Sel {
1395            &self.gpio_00_sel
1396        }
1397        #[doc = "0x04 - GPIO_01 pin mux select"]
1398        #[inline(always)]
1399        pub const fn gpio_01_sel(&self) -> &Gpio01Sel {
1400            &self.gpio_01_sel
1401        }
1402        #[doc = "0x08 - GPIO_02 pin mux select"]
1403        #[inline(always)]
1404        pub const fn gpio_02_sel(&self) -> &Gpio02Sel {
1405            &self.gpio_02_sel
1406        }
1407        #[doc = "0x0c - GPIO_03 pin mux select"]
1408        #[inline(always)]
1409        pub const fn gpio_03_sel(&self) -> &Gpio03Sel {
1410            &self.gpio_03_sel
1411        }
1412        #[doc = "0x10 - GPIO_04 pin mux select"]
1413        #[inline(always)]
1414        pub const fn gpio_04_sel(&self) -> &Gpio04Sel {
1415            &self.gpio_04_sel
1416        }
1417        #[doc = "0x14 - GPIO_05 pin mux select"]
1418        #[inline(always)]
1419        pub const fn gpio_05_sel(&self) -> &Gpio05Sel {
1420            &self.gpio_05_sel
1421        }
1422        #[doc = "0x18 - GPIO_06 pin mux select"]
1423        #[inline(always)]
1424        pub const fn gpio_06_sel(&self) -> &Gpio06Sel {
1425            &self.gpio_06_sel
1426        }
1427        #[doc = "0x1c - GPIO_07 pin mux select"]
1428        #[inline(always)]
1429        pub const fn gpio_07_sel(&self) -> &Gpio07Sel {
1430            &self.gpio_07_sel
1431        }
1432        #[doc = "0x20 - GPIO_08 pin mux select"]
1433        #[inline(always)]
1434        pub const fn gpio_08_sel(&self) -> &Gpio08Sel {
1435            &self.gpio_08_sel
1436        }
1437        #[doc = "0x24 - GPIO_09 pin mux select"]
1438        #[inline(always)]
1439        pub const fn gpio_09_sel(&self) -> &Gpio09Sel {
1440            &self.gpio_09_sel
1441        }
1442        #[doc = "0x28 - GPIO_10 pin mux select"]
1443        #[inline(always)]
1444        pub const fn gpio_10_sel(&self) -> &Gpio10Sel {
1445            &self.gpio_10_sel
1446        }
1447        #[doc = "0x2c - GPIO_11 pin mux select"]
1448        #[inline(always)]
1449        pub const fn gpio_11_sel(&self) -> &Gpio11Sel {
1450            &self.gpio_11_sel
1451        }
1452        #[doc = "0x30 - GPIO_12 pin mux select"]
1453        #[inline(always)]
1454        pub const fn gpio_12_sel(&self) -> &Gpio12Sel {
1455            &self.gpio_12_sel
1456        }
1457        #[doc = "0x34 - GPIO_13 pin mux select"]
1458        #[inline(always)]
1459        pub const fn gpio_13_sel(&self) -> &Gpio13Sel {
1460            &self.gpio_13_sel
1461        }
1462        #[doc = "0x38 - GPIO_14 pin mux select"]
1463        #[inline(always)]
1464        pub const fn gpio_14_sel(&self) -> &Gpio14Sel {
1465            &self.gpio_14_sel
1466        }
1467        #[doc = "0x3c - UART1_TXD pin mux select"]
1468        #[inline(always)]
1469        pub const fn uart1_txd_sel(&self) -> &Uart1TxdSel {
1470            &self.uart1_txd_sel
1471        }
1472        #[doc = "0x40 - UART1_RXD pin mux select"]
1473        #[inline(always)]
1474        pub const fn uart1_rxd_sel(&self) -> &Uart1RxdSel {
1475            &self.uart1_rxd_sel
1476        }
1477        #[doc = "0x44 - UART0_TXD pin mux select"]
1478        #[inline(always)]
1479        pub const fn uart0_txd_sel(&self) -> &Uart0TxdSel {
1480            &self.uart0_txd_sel
1481        }
1482        #[doc = "0x48 - UART0_RXD pin mux select"]
1483        #[inline(always)]
1484        pub const fn uart0_rxd_sel(&self) -> &Uart0RxdSel {
1485            &self.uart0_rxd_sel
1486        }
1487        #[doc = "0x800 - GPIO_00 pad control register"]
1488        #[inline(always)]
1489        pub const fn pad_gpio_00_ctrl(&self) -> &PadGpio00Ctrl {
1490            &self.pad_gpio_00_ctrl
1491        }
1492        #[doc = "0x804 - GPIO_01 pad control register"]
1493        #[inline(always)]
1494        pub const fn pad_gpio_01_ctrl(&self) -> &PadGpio01Ctrl {
1495            &self.pad_gpio_01_ctrl
1496        }
1497        #[doc = "0x808 - GPIO_02 pad control register"]
1498        #[inline(always)]
1499        pub const fn pad_gpio_02_ctrl(&self) -> &PadGpio02Ctrl {
1500            &self.pad_gpio_02_ctrl
1501        }
1502        #[doc = "0x80c - GPIO_03 pad control register"]
1503        #[inline(always)]
1504        pub const fn pad_gpio_03_ctrl(&self) -> &PadGpio03Ctrl {
1505            &self.pad_gpio_03_ctrl
1506        }
1507        #[doc = "0x810 - GPIO_04 pad control register"]
1508        #[inline(always)]
1509        pub const fn pad_gpio_04_ctrl(&self) -> &PadGpio04Ctrl {
1510            &self.pad_gpio_04_ctrl
1511        }
1512        #[doc = "0x814 - GPIO_05 pad control register"]
1513        #[inline(always)]
1514        pub const fn pad_gpio_05_ctrl(&self) -> &PadGpio05Ctrl {
1515            &self.pad_gpio_05_ctrl
1516        }
1517        #[doc = "0x818 - GPIO_06 pad control register"]
1518        #[inline(always)]
1519        pub const fn pad_gpio_06_ctrl(&self) -> &PadGpio06Ctrl {
1520            &self.pad_gpio_06_ctrl
1521        }
1522        #[doc = "0x81c - GPIO_07 pad control register"]
1523        #[inline(always)]
1524        pub const fn pad_gpio_07_ctrl(&self) -> &PadGpio07Ctrl {
1525            &self.pad_gpio_07_ctrl
1526        }
1527        #[doc = "0x820 - GPIO_08 pad control register"]
1528        #[inline(always)]
1529        pub const fn pad_gpio_08_ctrl(&self) -> &PadGpio08Ctrl {
1530            &self.pad_gpio_08_ctrl
1531        }
1532        #[doc = "0x824 - GPIO_09 pad control register"]
1533        #[inline(always)]
1534        pub const fn pad_gpio_09_ctrl(&self) -> &PadGpio09Ctrl {
1535            &self.pad_gpio_09_ctrl
1536        }
1537        #[doc = "0x828 - GPIO_10 pad control register"]
1538        #[inline(always)]
1539        pub const fn pad_gpio_10_ctrl(&self) -> &PadGpio10Ctrl {
1540            &self.pad_gpio_10_ctrl
1541        }
1542        #[doc = "0x82c - GPIO_11 pad control register"]
1543        #[inline(always)]
1544        pub const fn pad_gpio_11_ctrl(&self) -> &PadGpio11Ctrl {
1545            &self.pad_gpio_11_ctrl
1546        }
1547        #[doc = "0x830 - GPIO_12 pad control register"]
1548        #[inline(always)]
1549        pub const fn pad_gpio_12_ctrl(&self) -> &PadGpio12Ctrl {
1550            &self.pad_gpio_12_ctrl
1551        }
1552        #[doc = "0x834 - GPIO_13 pad control register"]
1553        #[inline(always)]
1554        pub const fn pad_gpio_13_ctrl(&self) -> &PadGpio13Ctrl {
1555            &self.pad_gpio_13_ctrl
1556        }
1557        #[doc = "0x838 - GPIO_14 pad control register"]
1558        #[inline(always)]
1559        pub const fn pad_gpio_14_ctrl(&self) -> &PadGpio14Ctrl {
1560            &self.pad_gpio_14_ctrl
1561        }
1562        #[doc = "0x83c - UART1_TXD pad control register"]
1563        #[inline(always)]
1564        pub const fn pad_uart1_txd_ctrl(&self) -> &PadUart1TxdCtrl {
1565            &self.pad_uart1_txd_ctrl
1566        }
1567        #[doc = "0x840 - UART1_RXD pad control register"]
1568        #[inline(always)]
1569        pub const fn pad_uart1_rxd_ctrl(&self) -> &PadUart1RxdCtrl {
1570            &self.pad_uart1_rxd_ctrl
1571        }
1572        #[doc = "0x844 - UART0_TXD pad control register"]
1573        #[inline(always)]
1574        pub const fn pad_uart0_txd_ctrl(&self) -> &PadUart0TxdCtrl {
1575            &self.pad_uart0_txd_ctrl
1576        }
1577        #[doc = "0x848 - UART0_RXD pad control register"]
1578        #[inline(always)]
1579        pub const fn pad_uart0_rxd_ctrl(&self) -> &PadUart0RxdCtrl {
1580            &self.pad_uart0_rxd_ctrl
1581        }
1582        #[doc = "0x868 - SFC_CLK pad control register"]
1583        #[inline(always)]
1584        pub const fn pad_sfc_clk_ctrl(&self) -> &PadSfcClkCtrl {
1585            &self.pad_sfc_clk_ctrl
1586        }
1587        #[doc = "0x86c - SFC_CSN pad control register"]
1588        #[inline(always)]
1589        pub const fn pad_sfc_csn_ctrl(&self) -> &PadSfcCsnCtrl {
1590            &self.pad_sfc_csn_ctrl
1591        }
1592        #[doc = "0x870 - SFC_IO0 pad control register"]
1593        #[inline(always)]
1594        pub const fn pad_sfc_io0_ctrl(&self) -> &PadSfcIo0Ctrl {
1595            &self.pad_sfc_io0_ctrl
1596        }
1597        #[doc = "0x874 - SFC_IO1 pad control register"]
1598        #[inline(always)]
1599        pub const fn pad_sfc_io1_ctrl(&self) -> &PadSfcIo1Ctrl {
1600            &self.pad_sfc_io1_ctrl
1601        }
1602        #[doc = "0x878 - SFC_IO2 pad control register"]
1603        #[inline(always)]
1604        pub const fn pad_sfc_io2_ctrl(&self) -> &PadSfcIo2Ctrl {
1605            &self.pad_sfc_io2_ctrl
1606        }
1607        #[doc = "0x87c - SFC_IO3 pad control register"]
1608        #[inline(always)]
1609        pub const fn pad_sfc_io3_ctrl(&self) -> &PadSfcIo3Ctrl {
1610            &self.pad_sfc_io3_ctrl
1611        }
1612    }
1613    #[doc = "GPIO_00_SEL (rw) register accessor: GPIO_00 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_00_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_00_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_00_sel`] module"]
1614    #[doc(alias = "GPIO_00_SEL")]
1615    pub type Gpio00Sel = crate::Reg<gpio_00_sel::Gpio00SelSpec>;
1616    #[doc = "GPIO_00 pin mux select"]
1617    pub mod gpio_00_sel {
1618        #[doc = "Register `GPIO_00_SEL` reader"]
1619        pub type R = crate::R<Gpio00SelSpec>;
1620        #[doc = "Register `GPIO_00_SEL` writer"]
1621        pub type W = crate::W<Gpio00SelSpec>;
1622        #[doc = "Field `gpio_00_sel` reader - GPIO_00 pin mux: 0:GPIO_00; 1:PWM0; 2:DIAG\\[0\\]; 3:SPI1_CSN; 4:JTAG_TDI"]
1623        pub type Gpio00SelR = crate::FieldReader;
1624        #[doc = "Field `gpio_00_sel` writer - GPIO_00 pin mux: 0:GPIO_00; 1:PWM0; 2:DIAG\\[0\\]; 3:SPI1_CSN; 4:JTAG_TDI"]
1625        pub type Gpio00SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
1626        impl R {
1627            #[doc = "Bits 0:2 - GPIO_00 pin mux: 0:GPIO_00; 1:PWM0; 2:DIAG\\[0\\]; 3:SPI1_CSN; 4:JTAG_TDI"]
1628            #[inline(always)]
1629            pub fn gpio_00_sel(&self) -> Gpio00SelR {
1630                Gpio00SelR::new((self.bits & 7) as u8)
1631            }
1632        }
1633        impl W {
1634            #[doc = "Bits 0:2 - GPIO_00 pin mux: 0:GPIO_00; 1:PWM0; 2:DIAG\\[0\\]; 3:SPI1_CSN; 4:JTAG_TDI"]
1635            #[inline(always)]
1636            pub fn gpio_00_sel(&mut self) -> Gpio00SelW<'_, Gpio00SelSpec> {
1637                Gpio00SelW::new(self, 0)
1638            }
1639        }
1640        #[doc = "GPIO_00 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_00_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_00_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1641        pub struct Gpio00SelSpec;
1642        impl crate::RegisterSpec for Gpio00SelSpec {
1643            type Ux = u32;
1644        }
1645        #[doc = "`read()` method returns [`gpio_00_sel::R`](R) reader structure"]
1646        impl crate::Readable for Gpio00SelSpec {}
1647        #[doc = "`write(|w| ..)` method takes [`gpio_00_sel::W`](W) writer structure"]
1648        impl crate::Writable for Gpio00SelSpec {
1649            type Safety = crate::Unsafe;
1650        }
1651        #[doc = "`reset()` method sets GPIO_00_SEL to value 0"]
1652        impl crate::Resettable for Gpio00SelSpec {}
1653    }
1654    #[doc = "GPIO_01_SEL (rw) register accessor: GPIO_01 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_01_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_01_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_01_sel`] module"]
1655    #[doc(alias = "GPIO_01_SEL")]
1656    pub type Gpio01Sel = crate::Reg<gpio_01_sel::Gpio01SelSpec>;
1657    #[doc = "GPIO_01 pin mux select"]
1658    pub mod gpio_01_sel {
1659        #[doc = "Register `GPIO_01_SEL` reader"]
1660        pub type R = crate::R<Gpio01SelSpec>;
1661        #[doc = "Register `GPIO_01_SEL` writer"]
1662        pub type W = crate::W<Gpio01SelSpec>;
1663        #[doc = "Field `gpio_01_sel` reader - GPIO_01 pin mux: 0:GPIO_01; 1:PWM1; 2:DIAG\\[1\\]; 3:SPI1_IO0; 4:JTAG_MODE; 5:BT_SAMPLE"]
1664        pub type Gpio01SelR = crate::FieldReader;
1665        #[doc = "Field `gpio_01_sel` writer - GPIO_01 pin mux: 0:GPIO_01; 1:PWM1; 2:DIAG\\[1\\]; 3:SPI1_IO0; 4:JTAG_MODE; 5:BT_SAMPLE"]
1666        pub type Gpio01SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
1667        impl R {
1668            #[doc = "Bits 0:2 - GPIO_01 pin mux: 0:GPIO_01; 1:PWM1; 2:DIAG\\[1\\]; 3:SPI1_IO0; 4:JTAG_MODE; 5:BT_SAMPLE"]
1669            #[inline(always)]
1670            pub fn gpio_01_sel(&self) -> Gpio01SelR {
1671                Gpio01SelR::new((self.bits & 7) as u8)
1672            }
1673        }
1674        impl W {
1675            #[doc = "Bits 0:2 - GPIO_01 pin mux: 0:GPIO_01; 1:PWM1; 2:DIAG\\[1\\]; 3:SPI1_IO0; 4:JTAG_MODE; 5:BT_SAMPLE"]
1676            #[inline(always)]
1677            pub fn gpio_01_sel(&mut self) -> Gpio01SelW<'_, Gpio01SelSpec> {
1678                Gpio01SelW::new(self, 0)
1679            }
1680        }
1681        #[doc = "GPIO_01 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_01_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_01_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1682        pub struct Gpio01SelSpec;
1683        impl crate::RegisterSpec for Gpio01SelSpec {
1684            type Ux = u32;
1685        }
1686        #[doc = "`read()` method returns [`gpio_01_sel::R`](R) reader structure"]
1687        impl crate::Readable for Gpio01SelSpec {}
1688        #[doc = "`write(|w| ..)` method takes [`gpio_01_sel::W`](W) writer structure"]
1689        impl crate::Writable for Gpio01SelSpec {
1690            type Safety = crate::Unsafe;
1691        }
1692        #[doc = "`reset()` method sets GPIO_01_SEL to value 0"]
1693        impl crate::Resettable for Gpio01SelSpec {}
1694    }
1695    #[doc = "GPIO_02_SEL (rw) register accessor: GPIO_02 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_02_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_02_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_02_sel`] module"]
1696    #[doc(alias = "GPIO_02_SEL")]
1697    pub type Gpio02Sel = crate::Reg<gpio_02_sel::Gpio02SelSpec>;
1698    #[doc = "GPIO_02 pin mux select"]
1699    pub mod gpio_02_sel {
1700        #[doc = "Register `GPIO_02_SEL` reader"]
1701        pub type R = crate::R<Gpio02SelSpec>;
1702        #[doc = "Register `GPIO_02_SEL` writer"]
1703        pub type W = crate::W<Gpio02SelSpec>;
1704        #[doc = "Field `gpio_02_sel` reader - GPIO_02 pin mux: 0:GPIO_02; 1:PWM2; 2:DIAG\\[2\\]; 3:SPI1_IO3; 4:WIFI_TSF_SYNC; 5:WL_GLP_SYNC_PULSE; 6:BSLE_GLP_SYNC_PULSE"]
1705        pub type Gpio02SelR = crate::FieldReader;
1706        #[doc = "Field `gpio_02_sel` writer - GPIO_02 pin mux: 0:GPIO_02; 1:PWM2; 2:DIAG\\[2\\]; 3:SPI1_IO3; 4:WIFI_TSF_SYNC; 5:WL_GLP_SYNC_PULSE; 6:BSLE_GLP_SYNC_PULSE"]
1707        pub type Gpio02SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
1708        impl R {
1709            #[doc = "Bits 0:2 - GPIO_02 pin mux: 0:GPIO_02; 1:PWM2; 2:DIAG\\[2\\]; 3:SPI1_IO3; 4:WIFI_TSF_SYNC; 5:WL_GLP_SYNC_PULSE; 6:BSLE_GLP_SYNC_PULSE"]
1710            #[inline(always)]
1711            pub fn gpio_02_sel(&self) -> Gpio02SelR {
1712                Gpio02SelR::new((self.bits & 7) as u8)
1713            }
1714        }
1715        impl W {
1716            #[doc = "Bits 0:2 - GPIO_02 pin mux: 0:GPIO_02; 1:PWM2; 2:DIAG\\[2\\]; 3:SPI1_IO3; 4:WIFI_TSF_SYNC; 5:WL_GLP_SYNC_PULSE; 6:BSLE_GLP_SYNC_PULSE"]
1717            #[inline(always)]
1718            pub fn gpio_02_sel(&mut self) -> Gpio02SelW<'_, Gpio02SelSpec> {
1719                Gpio02SelW::new(self, 0)
1720            }
1721        }
1722        #[doc = "GPIO_02 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_02_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_02_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1723        pub struct Gpio02SelSpec;
1724        impl crate::RegisterSpec for Gpio02SelSpec {
1725            type Ux = u32;
1726        }
1727        #[doc = "`read()` method returns [`gpio_02_sel::R`](R) reader structure"]
1728        impl crate::Readable for Gpio02SelSpec {}
1729        #[doc = "`write(|w| ..)` method takes [`gpio_02_sel::W`](W) writer structure"]
1730        impl crate::Writable for Gpio02SelSpec {
1731            type Safety = crate::Unsafe;
1732        }
1733        #[doc = "`reset()` method sets GPIO_02_SEL to value 0"]
1734        impl crate::Resettable for Gpio02SelSpec {}
1735    }
1736    #[doc = "GPIO_03_SEL (rw) register accessor: GPIO_03 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_03_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_03_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_03_sel`] module"]
1737    #[doc(alias = "GPIO_03_SEL")]
1738    pub type Gpio03Sel = crate::Reg<gpio_03_sel::Gpio03SelSpec>;
1739    #[doc = "GPIO_03 pin mux select"]
1740    pub mod gpio_03_sel {
1741        #[doc = "Register `GPIO_03_SEL` reader"]
1742        pub type R = crate::R<Gpio03SelSpec>;
1743        #[doc = "Register `GPIO_03_SEL` writer"]
1744        pub type W = crate::W<Gpio03SelSpec>;
1745        #[doc = "Field `gpio_03_sel` reader - GPIO_03 pin mux: 0:GPIO_03; 1:PWM3; 2:PMU_32K_TEST; 3:SPI1_IO1; 4:HW_ID\\[0\\]; 5:DIAG\\[3\\]"]
1746        pub type Gpio03SelR = crate::FieldReader;
1747        #[doc = "Field `gpio_03_sel` writer - GPIO_03 pin mux: 0:GPIO_03; 1:PWM3; 2:PMU_32K_TEST; 3:SPI1_IO1; 4:HW_ID\\[0\\]; 5:DIAG\\[3\\]"]
1748        pub type Gpio03SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
1749        impl R {
1750            #[doc = "Bits 0:2 - GPIO_03 pin mux: 0:GPIO_03; 1:PWM3; 2:PMU_32K_TEST; 3:SPI1_IO1; 4:HW_ID\\[0\\]; 5:DIAG\\[3\\]"]
1751            #[inline(always)]
1752            pub fn gpio_03_sel(&self) -> Gpio03SelR {
1753                Gpio03SelR::new((self.bits & 7) as u8)
1754            }
1755        }
1756        impl W {
1757            #[doc = "Bits 0:2 - GPIO_03 pin mux: 0:GPIO_03; 1:PWM3; 2:PMU_32K_TEST; 3:SPI1_IO1; 4:HW_ID\\[0\\]; 5:DIAG\\[3\\]"]
1758            #[inline(always)]
1759            pub fn gpio_03_sel(&mut self) -> Gpio03SelW<'_, Gpio03SelSpec> {
1760                Gpio03SelW::new(self, 0)
1761            }
1762        }
1763        #[doc = "GPIO_03 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_03_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_03_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1764        pub struct Gpio03SelSpec;
1765        impl crate::RegisterSpec for Gpio03SelSpec {
1766            type Ux = u32;
1767        }
1768        #[doc = "`read()` method returns [`gpio_03_sel::R`](R) reader structure"]
1769        impl crate::Readable for Gpio03SelSpec {}
1770        #[doc = "`write(|w| ..)` method takes [`gpio_03_sel::W`](W) writer structure"]
1771        impl crate::Writable for Gpio03SelSpec {
1772            type Safety = crate::Unsafe;
1773        }
1774        #[doc = "`reset()` method sets GPIO_03_SEL to value 0"]
1775        impl crate::Resettable for Gpio03SelSpec {}
1776    }
1777    #[doc = "GPIO_04_SEL (rw) register accessor: GPIO_04 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_04_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_04_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_04_sel`] module"]
1778    #[doc(alias = "GPIO_04_SEL")]
1779    pub type Gpio04Sel = crate::Reg<gpio_04_sel::Gpio04SelSpec>;
1780    #[doc = "GPIO_04 pin mux select"]
1781    pub mod gpio_04_sel {
1782        #[doc = "Register `GPIO_04_SEL` reader"]
1783        pub type R = crate::R<Gpio04SelSpec>;
1784        #[doc = "Register `GPIO_04_SEL` writer"]
1785        pub type W = crate::W<Gpio04SelSpec>;
1786        #[doc = "Field `gpio_04_sel` reader - GPIO_04 pin mux: 0:SSI_CLK; 1:PWM4; 2:GPIO_04; 3:SPI1_IO1; 4:JTAG_ENABLE; 5:DFT_JTAG_TMS"]
1787        pub type Gpio04SelR = crate::FieldReader;
1788        #[doc = "Field `gpio_04_sel` writer - GPIO_04 pin mux: 0:SSI_CLK; 1:PWM4; 2:GPIO_04; 3:SPI1_IO1; 4:JTAG_ENABLE; 5:DFT_JTAG_TMS"]
1789        pub type Gpio04SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
1790        impl R {
1791            #[doc = "Bits 0:2 - GPIO_04 pin mux: 0:SSI_CLK; 1:PWM4; 2:GPIO_04; 3:SPI1_IO1; 4:JTAG_ENABLE; 5:DFT_JTAG_TMS"]
1792            #[inline(always)]
1793            pub fn gpio_04_sel(&self) -> Gpio04SelR {
1794                Gpio04SelR::new((self.bits & 7) as u8)
1795            }
1796        }
1797        impl W {
1798            #[doc = "Bits 0:2 - GPIO_04 pin mux: 0:SSI_CLK; 1:PWM4; 2:GPIO_04; 3:SPI1_IO1; 4:JTAG_ENABLE; 5:DFT_JTAG_TMS"]
1799            #[inline(always)]
1800            pub fn gpio_04_sel(&mut self) -> Gpio04SelW<'_, Gpio04SelSpec> {
1801                Gpio04SelW::new(self, 0)
1802            }
1803        }
1804        #[doc = "GPIO_04 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_04_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_04_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1805        pub struct Gpio04SelSpec;
1806        impl crate::RegisterSpec for Gpio04SelSpec {
1807            type Ux = u32;
1808        }
1809        #[doc = "`read()` method returns [`gpio_04_sel::R`](R) reader structure"]
1810        impl crate::Readable for Gpio04SelSpec {}
1811        #[doc = "`write(|w| ..)` method takes [`gpio_04_sel::W`](W) writer structure"]
1812        impl crate::Writable for Gpio04SelSpec {
1813            type Safety = crate::Unsafe;
1814        }
1815        #[doc = "`reset()` method sets GPIO_04_SEL to value 0"]
1816        impl crate::Resettable for Gpio04SelSpec {}
1817    }
1818    #[doc = "GPIO_05_SEL (rw) register accessor: GPIO_05 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_05_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_05_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_05_sel`] module"]
1819    #[doc(alias = "GPIO_05_SEL")]
1820    pub type Gpio05Sel = crate::Reg<gpio_05_sel::Gpio05SelSpec>;
1821    #[doc = "GPIO_05 pin mux select"]
1822    pub mod gpio_05_sel {
1823        #[doc = "Register `GPIO_05_SEL` reader"]
1824        pub type R = crate::R<Gpio05SelSpec>;
1825        #[doc = "Register `GPIO_05_SEL` writer"]
1826        pub type W = crate::W<Gpio05SelSpec>;
1827        #[doc = "Field `gpio_05_sel` reader - GPIO_05 pin mux: 0:SSI_DATA; 1:PWM5; 2:UART2_CTS; 3:SPI1_IO2; 4:GPIO_05; 5:SPI0_IN; 6:DFT_JTAG_TCK"]
1828        pub type Gpio05SelR = crate::FieldReader;
1829        #[doc = "Field `gpio_05_sel` writer - GPIO_05 pin mux: 0:SSI_DATA; 1:PWM5; 2:UART2_CTS; 3:SPI1_IO2; 4:GPIO_05; 5:SPI0_IN; 6:DFT_JTAG_TCK"]
1830        pub type Gpio05SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
1831        impl R {
1832            #[doc = "Bits 0:2 - GPIO_05 pin mux: 0:SSI_DATA; 1:PWM5; 2:UART2_CTS; 3:SPI1_IO2; 4:GPIO_05; 5:SPI0_IN; 6:DFT_JTAG_TCK"]
1833            #[inline(always)]
1834            pub fn gpio_05_sel(&self) -> Gpio05SelR {
1835                Gpio05SelR::new((self.bits & 7) as u8)
1836            }
1837        }
1838        impl W {
1839            #[doc = "Bits 0:2 - GPIO_05 pin mux: 0:SSI_DATA; 1:PWM5; 2:UART2_CTS; 3:SPI1_IO2; 4:GPIO_05; 5:SPI0_IN; 6:DFT_JTAG_TCK"]
1840            #[inline(always)]
1841            pub fn gpio_05_sel(&mut self) -> Gpio05SelW<'_, Gpio05SelSpec> {
1842                Gpio05SelW::new(self, 0)
1843            }
1844        }
1845        #[doc = "GPIO_05 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_05_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_05_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1846        pub struct Gpio05SelSpec;
1847        impl crate::RegisterSpec for Gpio05SelSpec {
1848            type Ux = u32;
1849        }
1850        #[doc = "`read()` method returns [`gpio_05_sel::R`](R) reader structure"]
1851        impl crate::Readable for Gpio05SelSpec {}
1852        #[doc = "`write(|w| ..)` method takes [`gpio_05_sel::W`](W) writer structure"]
1853        impl crate::Writable for Gpio05SelSpec {
1854            type Safety = crate::Unsafe;
1855        }
1856        #[doc = "`reset()` method sets GPIO_05_SEL to value 0"]
1857        impl crate::Resettable for Gpio05SelSpec {}
1858    }
1859    #[doc = "GPIO_06_SEL (rw) register accessor: GPIO_06 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_06_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_06_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_06_sel`] module"]
1860    #[doc(alias = "GPIO_06_SEL")]
1861    pub type Gpio06Sel = crate::Reg<gpio_06_sel::Gpio06SelSpec>;
1862    #[doc = "GPIO_06 pin mux select"]
1863    pub mod gpio_06_sel {
1864        #[doc = "Register `GPIO_06_SEL` reader"]
1865        pub type R = crate::R<Gpio06SelSpec>;
1866        #[doc = "Register `GPIO_06_SEL` writer"]
1867        pub type W = crate::W<Gpio06SelSpec>;
1868        #[doc = "Field `gpio_06_sel` reader - GPIO_06 pin mux: 0:GPIO_06; 1:PWM6; 2:UART2_RTS; 3:SPI1_SCK; 4:REFCLK_FREQ_STATUS; 5:DIAG\\[4\\]; 6:SPI0_OUT; 7:DFT_JTAG_TDI"]
1869        pub type Gpio06SelR = crate::FieldReader;
1870        #[doc = "Field `gpio_06_sel` writer - GPIO_06 pin mux: 0:GPIO_06; 1:PWM6; 2:UART2_RTS; 3:SPI1_SCK; 4:REFCLK_FREQ_STATUS; 5:DIAG\\[4\\]; 6:SPI0_OUT; 7:DFT_JTAG_TDI"]
1871        pub type Gpio06SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
1872        impl R {
1873            #[doc = "Bits 0:2 - GPIO_06 pin mux: 0:GPIO_06; 1:PWM6; 2:UART2_RTS; 3:SPI1_SCK; 4:REFCLK_FREQ_STATUS; 5:DIAG\\[4\\]; 6:SPI0_OUT; 7:DFT_JTAG_TDI"]
1874            #[inline(always)]
1875            pub fn gpio_06_sel(&self) -> Gpio06SelR {
1876                Gpio06SelR::new((self.bits & 7) as u8)
1877            }
1878        }
1879        impl W {
1880            #[doc = "Bits 0:2 - GPIO_06 pin mux: 0:GPIO_06; 1:PWM6; 2:UART2_RTS; 3:SPI1_SCK; 4:REFCLK_FREQ_STATUS; 5:DIAG\\[4\\]; 6:SPI0_OUT; 7:DFT_JTAG_TDI"]
1881            #[inline(always)]
1882            pub fn gpio_06_sel(&mut self) -> Gpio06SelW<'_, Gpio06SelSpec> {
1883                Gpio06SelW::new(self, 0)
1884            }
1885        }
1886        #[doc = "GPIO_06 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_06_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_06_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1887        pub struct Gpio06SelSpec;
1888        impl crate::RegisterSpec for Gpio06SelSpec {
1889            type Ux = u32;
1890        }
1891        #[doc = "`read()` method returns [`gpio_06_sel::R`](R) reader structure"]
1892        impl crate::Readable for Gpio06SelSpec {}
1893        #[doc = "`write(|w| ..)` method takes [`gpio_06_sel::W`](W) writer structure"]
1894        impl crate::Writable for Gpio06SelSpec {
1895            type Safety = crate::Unsafe;
1896        }
1897        #[doc = "`reset()` method sets GPIO_06_SEL to value 0"]
1898        impl crate::Resettable for Gpio06SelSpec {}
1899    }
1900    #[doc = "GPIO_07_SEL (rw) register accessor: GPIO_07 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_07_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_07_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_07_sel`] module"]
1901    #[doc(alias = "GPIO_07_SEL")]
1902    pub type Gpio07Sel = crate::Reg<gpio_07_sel::Gpio07SelSpec>;
1903    #[doc = "GPIO_07 pin mux select"]
1904    pub mod gpio_07_sel {
1905        #[doc = "Register `GPIO_07_SEL` reader"]
1906        pub type R = crate::R<Gpio07SelSpec>;
1907        #[doc = "Register `GPIO_07_SEL` writer"]
1908        pub type W = crate::W<Gpio07SelSpec>;
1909        #[doc = "Field `gpio_07_sel` reader - GPIO_07 pin mux: 0:GPIO_07; 1:PWM7; 2:UART2_RXD; 3:SPI0_SCK; 4:I2S_MCLK; 5:DIAG\\[5\\]"]
1910        pub type Gpio07SelR = crate::FieldReader;
1911        #[doc = "Field `gpio_07_sel` writer - GPIO_07 pin mux: 0:GPIO_07; 1:PWM7; 2:UART2_RXD; 3:SPI0_SCK; 4:I2S_MCLK; 5:DIAG\\[5\\]"]
1912        pub type Gpio07SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
1913        impl R {
1914            #[doc = "Bits 0:2 - GPIO_07 pin mux: 0:GPIO_07; 1:PWM7; 2:UART2_RXD; 3:SPI0_SCK; 4:I2S_MCLK; 5:DIAG\\[5\\]"]
1915            #[inline(always)]
1916            pub fn gpio_07_sel(&self) -> Gpio07SelR {
1917                Gpio07SelR::new((self.bits & 7) as u8)
1918            }
1919        }
1920        impl W {
1921            #[doc = "Bits 0:2 - GPIO_07 pin mux: 0:GPIO_07; 1:PWM7; 2:UART2_RXD; 3:SPI0_SCK; 4:I2S_MCLK; 5:DIAG\\[5\\]"]
1922            #[inline(always)]
1923            pub fn gpio_07_sel(&mut self) -> Gpio07SelW<'_, Gpio07SelSpec> {
1924                Gpio07SelW::new(self, 0)
1925            }
1926        }
1927        #[doc = "GPIO_07 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_07_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_07_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1928        pub struct Gpio07SelSpec;
1929        impl crate::RegisterSpec for Gpio07SelSpec {
1930            type Ux = u32;
1931        }
1932        #[doc = "`read()` method returns [`gpio_07_sel::R`](R) reader structure"]
1933        impl crate::Readable for Gpio07SelSpec {}
1934        #[doc = "`write(|w| ..)` method takes [`gpio_07_sel::W`](W) writer structure"]
1935        impl crate::Writable for Gpio07SelSpec {
1936            type Safety = crate::Unsafe;
1937        }
1938        #[doc = "`reset()` method sets GPIO_07_SEL to value 0"]
1939        impl crate::Resettable for Gpio07SelSpec {}
1940    }
1941    #[doc = "GPIO_08_SEL (rw) register accessor: GPIO_08 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_08_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_08_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_08_sel`] module"]
1942    #[doc(alias = "GPIO_08_SEL")]
1943    pub type Gpio08Sel = crate::Reg<gpio_08_sel::Gpio08SelSpec>;
1944    #[doc = "GPIO_08 pin mux select"]
1945    pub mod gpio_08_sel {
1946        #[doc = "Register `GPIO_08_SEL` reader"]
1947        pub type R = crate::R<Gpio08SelSpec>;
1948        #[doc = "Register `GPIO_08_SEL` writer"]
1949        pub type W = crate::W<Gpio08SelSpec>;
1950        #[doc = "Field `gpio_08_sel` reader - GPIO_08 pin mux: 0:GPIO_08; 1:PWM0; 2:UART2_TXD; 3:SPI0_CS1_N; 4:DIAG\\[6\\]"]
1951        pub type Gpio08SelR = crate::FieldReader;
1952        #[doc = "Field `gpio_08_sel` writer - GPIO_08 pin mux: 0:GPIO_08; 1:PWM0; 2:UART2_TXD; 3:SPI0_CS1_N; 4:DIAG\\[6\\]"]
1953        pub type Gpio08SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
1954        impl R {
1955            #[doc = "Bits 0:2 - GPIO_08 pin mux: 0:GPIO_08; 1:PWM0; 2:UART2_TXD; 3:SPI0_CS1_N; 4:DIAG\\[6\\]"]
1956            #[inline(always)]
1957            pub fn gpio_08_sel(&self) -> Gpio08SelR {
1958                Gpio08SelR::new((self.bits & 7) as u8)
1959            }
1960        }
1961        impl W {
1962            #[doc = "Bits 0:2 - GPIO_08 pin mux: 0:GPIO_08; 1:PWM0; 2:UART2_TXD; 3:SPI0_CS1_N; 4:DIAG\\[6\\]"]
1963            #[inline(always)]
1964            pub fn gpio_08_sel(&mut self) -> Gpio08SelW<'_, Gpio08SelSpec> {
1965                Gpio08SelW::new(self, 0)
1966            }
1967        }
1968        #[doc = "GPIO_08 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_08_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_08_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1969        pub struct Gpio08SelSpec;
1970        impl crate::RegisterSpec for Gpio08SelSpec {
1971            type Ux = u32;
1972        }
1973        #[doc = "`read()` method returns [`gpio_08_sel::R`](R) reader structure"]
1974        impl crate::Readable for Gpio08SelSpec {}
1975        #[doc = "`write(|w| ..)` method takes [`gpio_08_sel::W`](W) writer structure"]
1976        impl crate::Writable for Gpio08SelSpec {
1977            type Safety = crate::Unsafe;
1978        }
1979        #[doc = "`reset()` method sets GPIO_08_SEL to value 0"]
1980        impl crate::Resettable for Gpio08SelSpec {}
1981    }
1982    #[doc = "GPIO_09_SEL (rw) register accessor: GPIO_09 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_09_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_09_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_09_sel`] module"]
1983    #[doc(alias = "GPIO_09_SEL")]
1984    pub type Gpio09Sel = crate::Reg<gpio_09_sel::Gpio09SelSpec>;
1985    #[doc = "GPIO_09 pin mux select"]
1986    pub mod gpio_09_sel {
1987        #[doc = "Register `GPIO_09_SEL` reader"]
1988        pub type R = crate::R<Gpio09SelSpec>;
1989        #[doc = "Register `GPIO_09_SEL` writer"]
1990        pub type W = crate::W<Gpio09SelSpec>;
1991        #[doc = "Field `gpio_09_sel` reader - GPIO_09 pin mux: 0:GPIO_09; 1:PWM1; 2:RADAR_ANT0_SW; 3:SPI0_OUT; 4:I2S_DO; 5:HW_ID\\[1\\]; 6:DIAG\\[7\\]; 7:JTAG_TDO"]
1992        pub type Gpio09SelR = crate::FieldReader;
1993        #[doc = "Field `gpio_09_sel` writer - GPIO_09 pin mux: 0:GPIO_09; 1:PWM1; 2:RADAR_ANT0_SW; 3:SPI0_OUT; 4:I2S_DO; 5:HW_ID\\[1\\]; 6:DIAG\\[7\\]; 7:JTAG_TDO"]
1994        pub type Gpio09SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
1995        impl R {
1996            #[doc = "Bits 0:2 - GPIO_09 pin mux: 0:GPIO_09; 1:PWM1; 2:RADAR_ANT0_SW; 3:SPI0_OUT; 4:I2S_DO; 5:HW_ID\\[1\\]; 6:DIAG\\[7\\]; 7:JTAG_TDO"]
1997            #[inline(always)]
1998            pub fn gpio_09_sel(&self) -> Gpio09SelR {
1999                Gpio09SelR::new((self.bits & 7) as u8)
2000            }
2001        }
2002        impl W {
2003            #[doc = "Bits 0:2 - GPIO_09 pin mux: 0:GPIO_09; 1:PWM1; 2:RADAR_ANT0_SW; 3:SPI0_OUT; 4:I2S_DO; 5:HW_ID\\[1\\]; 6:DIAG\\[7\\]; 7:JTAG_TDO"]
2004            #[inline(always)]
2005            pub fn gpio_09_sel(&mut self) -> Gpio09SelW<'_, Gpio09SelSpec> {
2006                Gpio09SelW::new(self, 0)
2007            }
2008        }
2009        #[doc = "GPIO_09 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_09_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_09_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2010        pub struct Gpio09SelSpec;
2011        impl crate::RegisterSpec for Gpio09SelSpec {
2012            type Ux = u32;
2013        }
2014        #[doc = "`read()` method returns [`gpio_09_sel::R`](R) reader structure"]
2015        impl crate::Readable for Gpio09SelSpec {}
2016        #[doc = "`write(|w| ..)` method takes [`gpio_09_sel::W`](W) writer structure"]
2017        impl crate::Writable for Gpio09SelSpec {
2018            type Safety = crate::Unsafe;
2019        }
2020        #[doc = "`reset()` method sets GPIO_09_SEL to value 0"]
2021        impl crate::Resettable for Gpio09SelSpec {}
2022    }
2023    #[doc = "GPIO_10_SEL (rw) register accessor: GPIO_10 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_10_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_10_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_10_sel`] module"]
2024    #[doc(alias = "GPIO_10_SEL")]
2025    pub type Gpio10Sel = crate::Reg<gpio_10_sel::Gpio10SelSpec>;
2026    #[doc = "GPIO_10 pin mux select"]
2027    pub mod gpio_10_sel {
2028        #[doc = "Register `GPIO_10_SEL` reader"]
2029        pub type R = crate::R<Gpio10SelSpec>;
2030        #[doc = "Register `GPIO_10_SEL` writer"]
2031        pub type W = crate::W<Gpio10SelSpec>;
2032        #[doc = "Field `gpio_10_sel` reader - GPIO_10 pin mux: 0:GPIO_10; 1:PWM2; 2:ANT0_SW; 3:SPI0_CS0_N; 4:I2S_SCLK; 5:DIAG\\[0\\]"]
2033        pub type Gpio10SelR = crate::FieldReader;
2034        #[doc = "Field `gpio_10_sel` writer - GPIO_10 pin mux: 0:GPIO_10; 1:PWM2; 2:ANT0_SW; 3:SPI0_CS0_N; 4:I2S_SCLK; 5:DIAG\\[0\\]"]
2035        pub type Gpio10SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
2036        impl R {
2037            #[doc = "Bits 0:2 - GPIO_10 pin mux: 0:GPIO_10; 1:PWM2; 2:ANT0_SW; 3:SPI0_CS0_N; 4:I2S_SCLK; 5:DIAG\\[0\\]"]
2038            #[inline(always)]
2039            pub fn gpio_10_sel(&self) -> Gpio10SelR {
2040                Gpio10SelR::new((self.bits & 7) as u8)
2041            }
2042        }
2043        impl W {
2044            #[doc = "Bits 0:2 - GPIO_10 pin mux: 0:GPIO_10; 1:PWM2; 2:ANT0_SW; 3:SPI0_CS0_N; 4:I2S_SCLK; 5:DIAG\\[0\\]"]
2045            #[inline(always)]
2046            pub fn gpio_10_sel(&mut self) -> Gpio10SelW<'_, Gpio10SelSpec> {
2047                Gpio10SelW::new(self, 0)
2048            }
2049        }
2050        #[doc = "GPIO_10 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_10_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_10_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2051        pub struct Gpio10SelSpec;
2052        impl crate::RegisterSpec for Gpio10SelSpec {
2053            type Ux = u32;
2054        }
2055        #[doc = "`read()` method returns [`gpio_10_sel::R`](R) reader structure"]
2056        impl crate::Readable for Gpio10SelSpec {}
2057        #[doc = "`write(|w| ..)` method takes [`gpio_10_sel::W`](W) writer structure"]
2058        impl crate::Writable for Gpio10SelSpec {
2059            type Safety = crate::Unsafe;
2060        }
2061        #[doc = "`reset()` method sets GPIO_10_SEL to value 0"]
2062        impl crate::Resettable for Gpio10SelSpec {}
2063    }
2064    #[doc = "GPIO_11_SEL (rw) register accessor: GPIO_11 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_11_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_11_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_11_sel`] module"]
2065    #[doc(alias = "GPIO_11_SEL")]
2066    pub type Gpio11Sel = crate::Reg<gpio_11_sel::Gpio11SelSpec>;
2067    #[doc = "GPIO_11 pin mux select"]
2068    pub mod gpio_11_sel {
2069        #[doc = "Register `GPIO_11_SEL` reader"]
2070        pub type R = crate::R<Gpio11SelSpec>;
2071        #[doc = "Register `GPIO_11_SEL` writer"]
2072        pub type W = crate::W<Gpio11SelSpec>;
2073        #[doc = "Field `gpio_11_sel` reader - GPIO_11 pin mux: 0:GPIO_11; 1:PWM3; 2:RADAR_ANT1_SW; 3:SPI0_IN; 4:I2S_LRCLK; 5:DIAG\\[1\\]; 6:HW_ID\\[2\\]"]
2074        pub type Gpio11SelR = crate::FieldReader;
2075        #[doc = "Field `gpio_11_sel` writer - GPIO_11 pin mux: 0:GPIO_11; 1:PWM3; 2:RADAR_ANT1_SW; 3:SPI0_IN; 4:I2S_LRCLK; 5:DIAG\\[1\\]; 6:HW_ID\\[2\\]"]
2076        pub type Gpio11SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
2077        impl R {
2078            #[doc = "Bits 0:2 - GPIO_11 pin mux: 0:GPIO_11; 1:PWM3; 2:RADAR_ANT1_SW; 3:SPI0_IN; 4:I2S_LRCLK; 5:DIAG\\[1\\]; 6:HW_ID\\[2\\]"]
2079            #[inline(always)]
2080            pub fn gpio_11_sel(&self) -> Gpio11SelR {
2081                Gpio11SelR::new((self.bits & 7) as u8)
2082            }
2083        }
2084        impl W {
2085            #[doc = "Bits 0:2 - GPIO_11 pin mux: 0:GPIO_11; 1:PWM3; 2:RADAR_ANT1_SW; 3:SPI0_IN; 4:I2S_LRCLK; 5:DIAG\\[1\\]; 6:HW_ID\\[2\\]"]
2086            #[inline(always)]
2087            pub fn gpio_11_sel(&mut self) -> Gpio11SelW<'_, Gpio11SelSpec> {
2088                Gpio11SelW::new(self, 0)
2089            }
2090        }
2091        #[doc = "GPIO_11 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_11_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_11_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2092        pub struct Gpio11SelSpec;
2093        impl crate::RegisterSpec for Gpio11SelSpec {
2094            type Ux = u32;
2095        }
2096        #[doc = "`read()` method returns [`gpio_11_sel::R`](R) reader structure"]
2097        impl crate::Readable for Gpio11SelSpec {}
2098        #[doc = "`write(|w| ..)` method takes [`gpio_11_sel::W`](W) writer structure"]
2099        impl crate::Writable for Gpio11SelSpec {
2100            type Safety = crate::Unsafe;
2101        }
2102        #[doc = "`reset()` method sets GPIO_11_SEL to value 0"]
2103        impl crate::Resettable for Gpio11SelSpec {}
2104    }
2105    #[doc = "GPIO_12_SEL (rw) register accessor: GPIO_12 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_12_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_12_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_12_sel`] module"]
2106    #[doc(alias = "GPIO_12_SEL")]
2107    pub type Gpio12Sel = crate::Reg<gpio_12_sel::Gpio12SelSpec>;
2108    #[doc = "GPIO_12 pin mux select"]
2109    pub mod gpio_12_sel {
2110        #[doc = "Register `GPIO_12_SEL` reader"]
2111        pub type R = crate::R<Gpio12SelSpec>;
2112        #[doc = "Register `GPIO_12_SEL` writer"]
2113        pub type W = crate::W<Gpio12SelSpec>;
2114        #[doc = "Field `gpio_12_sel` reader - GPIO_12 pin mux: 0:GPIO_12; 1:PWM4; 2:ANT1_SW; 4:I2S_DI; 6:HW_ID\\[3\\]"]
2115        pub type Gpio12SelR = crate::FieldReader;
2116        #[doc = "Field `gpio_12_sel` writer - GPIO_12 pin mux: 0:GPIO_12; 1:PWM4; 2:ANT1_SW; 4:I2S_DI; 6:HW_ID\\[3\\]"]
2117        pub type Gpio12SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
2118        impl R {
2119            #[doc = "Bits 0:2 - GPIO_12 pin mux: 0:GPIO_12; 1:PWM4; 2:ANT1_SW; 4:I2S_DI; 6:HW_ID\\[3\\]"]
2120            #[inline(always)]
2121            pub fn gpio_12_sel(&self) -> Gpio12SelR {
2122                Gpio12SelR::new((self.bits & 7) as u8)
2123            }
2124        }
2125        impl W {
2126            #[doc = "Bits 0:2 - GPIO_12 pin mux: 0:GPIO_12; 1:PWM4; 2:ANT1_SW; 4:I2S_DI; 6:HW_ID\\[3\\]"]
2127            #[inline(always)]
2128            pub fn gpio_12_sel(&mut self) -> Gpio12SelW<'_, Gpio12SelSpec> {
2129                Gpio12SelW::new(self, 0)
2130            }
2131        }
2132        #[doc = "GPIO_12 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_12_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_12_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2133        pub struct Gpio12SelSpec;
2134        impl crate::RegisterSpec for Gpio12SelSpec {
2135            type Ux = u32;
2136        }
2137        #[doc = "`read()` method returns [`gpio_12_sel::R`](R) reader structure"]
2138        impl crate::Readable for Gpio12SelSpec {}
2139        #[doc = "`write(|w| ..)` method takes [`gpio_12_sel::W`](W) writer structure"]
2140        impl crate::Writable for Gpio12SelSpec {
2141            type Safety = crate::Unsafe;
2142        }
2143        #[doc = "`reset()` method sets GPIO_12_SEL to value 0"]
2144        impl crate::Resettable for Gpio12SelSpec {}
2145    }
2146    #[doc = "GPIO_13_SEL (rw) register accessor: GPIO_13 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_13_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_13_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_13_sel`] module"]
2147    #[doc(alias = "GPIO_13_SEL")]
2148    pub type Gpio13Sel = crate::Reg<gpio_13_sel::Gpio13SelSpec>;
2149    #[doc = "GPIO_13 pin mux select"]
2150    pub mod gpio_13_sel {
2151        #[doc = "Register `GPIO_13_SEL` reader"]
2152        pub type R = crate::R<Gpio13SelSpec>;
2153        #[doc = "Register `GPIO_13_SEL` writer"]
2154        pub type W = crate::W<Gpio13SelSpec>;
2155        #[doc = "Field `gpio_13_sel` reader - GPIO_13 pin mux: 0:GPIO_13; 1:UART1_CTS; 2:RADAR_ANT0_SW; 3:DFT_JTAG_TDO; 4:JTAG_TMS"]
2156        pub type Gpio13SelR = crate::FieldReader;
2157        #[doc = "Field `gpio_13_sel` writer - GPIO_13 pin mux: 0:GPIO_13; 1:UART1_CTS; 2:RADAR_ANT0_SW; 3:DFT_JTAG_TDO; 4:JTAG_TMS"]
2158        pub type Gpio13SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
2159        impl R {
2160            #[doc = "Bits 0:2 - GPIO_13 pin mux: 0:GPIO_13; 1:UART1_CTS; 2:RADAR_ANT0_SW; 3:DFT_JTAG_TDO; 4:JTAG_TMS"]
2161            #[inline(always)]
2162            pub fn gpio_13_sel(&self) -> Gpio13SelR {
2163                Gpio13SelR::new((self.bits & 7) as u8)
2164            }
2165        }
2166        impl W {
2167            #[doc = "Bits 0:2 - GPIO_13 pin mux: 0:GPIO_13; 1:UART1_CTS; 2:RADAR_ANT0_SW; 3:DFT_JTAG_TDO; 4:JTAG_TMS"]
2168            #[inline(always)]
2169            pub fn gpio_13_sel(&mut self) -> Gpio13SelW<'_, Gpio13SelSpec> {
2170                Gpio13SelW::new(self, 0)
2171            }
2172        }
2173        #[doc = "GPIO_13 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_13_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_13_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2174        pub struct Gpio13SelSpec;
2175        impl crate::RegisterSpec for Gpio13SelSpec {
2176            type Ux = u32;
2177        }
2178        #[doc = "`read()` method returns [`gpio_13_sel::R`](R) reader structure"]
2179        impl crate::Readable for Gpio13SelSpec {}
2180        #[doc = "`write(|w| ..)` method takes [`gpio_13_sel::W`](W) writer structure"]
2181        impl crate::Writable for Gpio13SelSpec {
2182            type Safety = crate::Unsafe;
2183        }
2184        #[doc = "`reset()` method sets GPIO_13_SEL to value 0"]
2185        impl crate::Resettable for Gpio13SelSpec {}
2186    }
2187    #[doc = "GPIO_14_SEL (rw) register accessor: GPIO_14 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_14_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_14_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_14_sel`] module"]
2188    #[doc(alias = "GPIO_14_SEL")]
2189    pub type Gpio14Sel = crate::Reg<gpio_14_sel::Gpio14SelSpec>;
2190    #[doc = "GPIO_14 pin mux select"]
2191    pub mod gpio_14_sel {
2192        #[doc = "Register `GPIO_14_SEL` reader"]
2193        pub type R = crate::R<Gpio14SelSpec>;
2194        #[doc = "Register `GPIO_14_SEL` writer"]
2195        pub type W = crate::W<Gpio14SelSpec>;
2196        #[doc = "Field `gpio_14_sel` reader - GPIO_14 pin mux: 0:GPIO_14; 1:UART1_RTS; 2:RADAR_ANT1_SW; 3:DFT_JTAG_TRSTN; 4:JTAG_TCK"]
2197        pub type Gpio14SelR = crate::FieldReader;
2198        #[doc = "Field `gpio_14_sel` writer - GPIO_14 pin mux: 0:GPIO_14; 1:UART1_RTS; 2:RADAR_ANT1_SW; 3:DFT_JTAG_TRSTN; 4:JTAG_TCK"]
2199        pub type Gpio14SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
2200        impl R {
2201            #[doc = "Bits 0:2 - GPIO_14 pin mux: 0:GPIO_14; 1:UART1_RTS; 2:RADAR_ANT1_SW; 3:DFT_JTAG_TRSTN; 4:JTAG_TCK"]
2202            #[inline(always)]
2203            pub fn gpio_14_sel(&self) -> Gpio14SelR {
2204                Gpio14SelR::new((self.bits & 7) as u8)
2205            }
2206        }
2207        impl W {
2208            #[doc = "Bits 0:2 - GPIO_14 pin mux: 0:GPIO_14; 1:UART1_RTS; 2:RADAR_ANT1_SW; 3:DFT_JTAG_TRSTN; 4:JTAG_TCK"]
2209            #[inline(always)]
2210            pub fn gpio_14_sel(&mut self) -> Gpio14SelW<'_, Gpio14SelSpec> {
2211                Gpio14SelW::new(self, 0)
2212            }
2213        }
2214        #[doc = "GPIO_14 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_14_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_14_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2215        pub struct Gpio14SelSpec;
2216        impl crate::RegisterSpec for Gpio14SelSpec {
2217            type Ux = u32;
2218        }
2219        #[doc = "`read()` method returns [`gpio_14_sel::R`](R) reader structure"]
2220        impl crate::Readable for Gpio14SelSpec {}
2221        #[doc = "`write(|w| ..)` method takes [`gpio_14_sel::W`](W) writer structure"]
2222        impl crate::Writable for Gpio14SelSpec {
2223            type Safety = crate::Unsafe;
2224        }
2225        #[doc = "`reset()` method sets GPIO_14_SEL to value 0"]
2226        impl crate::Resettable for Gpio14SelSpec {}
2227    }
2228    #[doc = "UART1_TXD_SEL (rw) register accessor: UART1_TXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_txd_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_txd_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_txd_sel`] module"]
2229    #[doc(alias = "UART1_TXD_SEL")]
2230    pub type Uart1TxdSel = crate::Reg<uart1_txd_sel::Uart1TxdSelSpec>;
2231    #[doc = "UART1_TXD pin mux select"]
2232    pub mod uart1_txd_sel {
2233        #[doc = "Register `UART1_TXD_SEL` reader"]
2234        pub type R = crate::R<Uart1TxdSelSpec>;
2235        #[doc = "Register `UART1_TXD_SEL` writer"]
2236        pub type W = crate::W<Uart1TxdSelSpec>;
2237        #[doc = "Field `uart1_txd_sel` reader - UART1_TXD pin mux: 0:GPIO_15; 1:UART1_TXD; 2:I2C1_SDA"]
2238        pub type Uart1TxdSelR = crate::FieldReader;
2239        #[doc = "Field `uart1_txd_sel` writer - UART1_TXD pin mux: 0:GPIO_15; 1:UART1_TXD; 2:I2C1_SDA"]
2240        pub type Uart1TxdSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
2241        impl R {
2242            #[doc = "Bits 0:1 - UART1_TXD pin mux: 0:GPIO_15; 1:UART1_TXD; 2:I2C1_SDA"]
2243            #[inline(always)]
2244            pub fn uart1_txd_sel(&self) -> Uart1TxdSelR {
2245                Uart1TxdSelR::new((self.bits & 3) as u8)
2246            }
2247        }
2248        impl W {
2249            #[doc = "Bits 0:1 - UART1_TXD pin mux: 0:GPIO_15; 1:UART1_TXD; 2:I2C1_SDA"]
2250            #[inline(always)]
2251            pub fn uart1_txd_sel(&mut self) -> Uart1TxdSelW<'_, Uart1TxdSelSpec> {
2252                Uart1TxdSelW::new(self, 0)
2253            }
2254        }
2255        #[doc = "UART1_TXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_txd_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_txd_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2256        pub struct Uart1TxdSelSpec;
2257        impl crate::RegisterSpec for Uart1TxdSelSpec {
2258            type Ux = u32;
2259        }
2260        #[doc = "`read()` method returns [`uart1_txd_sel::R`](R) reader structure"]
2261        impl crate::Readable for Uart1TxdSelSpec {}
2262        #[doc = "`write(|w| ..)` method takes [`uart1_txd_sel::W`](W) writer structure"]
2263        impl crate::Writable for Uart1TxdSelSpec {
2264            type Safety = crate::Unsafe;
2265        }
2266        #[doc = "`reset()` method sets UART1_TXD_SEL to value 0"]
2267        impl crate::Resettable for Uart1TxdSelSpec {}
2268    }
2269    #[doc = "UART1_RXD_SEL (rw) register accessor: UART1_RXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_rxd_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_rxd_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_rxd_sel`] module"]
2270    #[doc(alias = "UART1_RXD_SEL")]
2271    pub type Uart1RxdSel = crate::Reg<uart1_rxd_sel::Uart1RxdSelSpec>;
2272    #[doc = "UART1_RXD pin mux select"]
2273    pub mod uart1_rxd_sel {
2274        #[doc = "Register `UART1_RXD_SEL` reader"]
2275        pub type R = crate::R<Uart1RxdSelSpec>;
2276        #[doc = "Register `UART1_RXD_SEL` writer"]
2277        pub type W = crate::W<Uart1RxdSelSpec>;
2278        #[doc = "Field `uart1_rxd_sel` reader - UART1_RXD pin mux: 0:GPIO_16; 1:UART1_RXD; 2:I2C1_SCL"]
2279        pub type Uart1RxdSelR = crate::FieldReader;
2280        #[doc = "Field `uart1_rxd_sel` writer - UART1_RXD pin mux: 0:GPIO_16; 1:UART1_RXD; 2:I2C1_SCL"]
2281        pub type Uart1RxdSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
2282        impl R {
2283            #[doc = "Bits 0:1 - UART1_RXD pin mux: 0:GPIO_16; 1:UART1_RXD; 2:I2C1_SCL"]
2284            #[inline(always)]
2285            pub fn uart1_rxd_sel(&self) -> Uart1RxdSelR {
2286                Uart1RxdSelR::new((self.bits & 3) as u8)
2287            }
2288        }
2289        impl W {
2290            #[doc = "Bits 0:1 - UART1_RXD pin mux: 0:GPIO_16; 1:UART1_RXD; 2:I2C1_SCL"]
2291            #[inline(always)]
2292            pub fn uart1_rxd_sel(&mut self) -> Uart1RxdSelW<'_, Uart1RxdSelSpec> {
2293                Uart1RxdSelW::new(self, 0)
2294            }
2295        }
2296        #[doc = "UART1_RXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_rxd_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_rxd_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2297        pub struct Uart1RxdSelSpec;
2298        impl crate::RegisterSpec for Uart1RxdSelSpec {
2299            type Ux = u32;
2300        }
2301        #[doc = "`read()` method returns [`uart1_rxd_sel::R`](R) reader structure"]
2302        impl crate::Readable for Uart1RxdSelSpec {}
2303        #[doc = "`write(|w| ..)` method takes [`uart1_rxd_sel::W`](W) writer structure"]
2304        impl crate::Writable for Uart1RxdSelSpec {
2305            type Safety = crate::Unsafe;
2306        }
2307        #[doc = "`reset()` method sets UART1_RXD_SEL to value 0"]
2308        impl crate::Resettable for Uart1RxdSelSpec {}
2309    }
2310    #[doc = "UART0_TXD_SEL (rw) register accessor: UART0_TXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_txd_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_txd_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_txd_sel`] module"]
2311    #[doc(alias = "UART0_TXD_SEL")]
2312    pub type Uart0TxdSel = crate::Reg<uart0_txd_sel::Uart0TxdSelSpec>;
2313    #[doc = "UART0_TXD pin mux select"]
2314    pub mod uart0_txd_sel {
2315        #[doc = "Register `UART0_TXD_SEL` reader"]
2316        pub type R = crate::R<Uart0TxdSelSpec>;
2317        #[doc = "Register `UART0_TXD_SEL` writer"]
2318        pub type W = crate::W<Uart0TxdSelSpec>;
2319        #[doc = "Field `uart0_txd_sel` reader - UART0_TXD pin mux: 0:GPIO_17; 1:UART0_TXD; 2:I2C0_SDA"]
2320        pub type Uart0TxdSelR = crate::FieldReader;
2321        #[doc = "Field `uart0_txd_sel` writer - UART0_TXD pin mux: 0:GPIO_17; 1:UART0_TXD; 2:I2C0_SDA"]
2322        pub type Uart0TxdSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
2323        impl R {
2324            #[doc = "Bits 0:1 - UART0_TXD pin mux: 0:GPIO_17; 1:UART0_TXD; 2:I2C0_SDA"]
2325            #[inline(always)]
2326            pub fn uart0_txd_sel(&self) -> Uart0TxdSelR {
2327                Uart0TxdSelR::new((self.bits & 3) as u8)
2328            }
2329        }
2330        impl W {
2331            #[doc = "Bits 0:1 - UART0_TXD pin mux: 0:GPIO_17; 1:UART0_TXD; 2:I2C0_SDA"]
2332            #[inline(always)]
2333            pub fn uart0_txd_sel(&mut self) -> Uart0TxdSelW<'_, Uart0TxdSelSpec> {
2334                Uart0TxdSelW::new(self, 0)
2335            }
2336        }
2337        #[doc = "UART0_TXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_txd_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_txd_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2338        pub struct Uart0TxdSelSpec;
2339        impl crate::RegisterSpec for Uart0TxdSelSpec {
2340            type Ux = u32;
2341        }
2342        #[doc = "`read()` method returns [`uart0_txd_sel::R`](R) reader structure"]
2343        impl crate::Readable for Uart0TxdSelSpec {}
2344        #[doc = "`write(|w| ..)` method takes [`uart0_txd_sel::W`](W) writer structure"]
2345        impl crate::Writable for Uart0TxdSelSpec {
2346            type Safety = crate::Unsafe;
2347        }
2348        #[doc = "`reset()` method sets UART0_TXD_SEL to value 0"]
2349        impl crate::Resettable for Uart0TxdSelSpec {}
2350    }
2351    #[doc = "UART0_RXD_SEL (rw) register accessor: UART0_RXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_rxd_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_rxd_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_rxd_sel`] module"]
2352    #[doc(alias = "UART0_RXD_SEL")]
2353    pub type Uart0RxdSel = crate::Reg<uart0_rxd_sel::Uart0RxdSelSpec>;
2354    #[doc = "UART0_RXD pin mux select"]
2355    pub mod uart0_rxd_sel {
2356        #[doc = "Register `UART0_RXD_SEL` reader"]
2357        pub type R = crate::R<Uart0RxdSelSpec>;
2358        #[doc = "Register `UART0_RXD_SEL` writer"]
2359        pub type W = crate::W<Uart0RxdSelSpec>;
2360        #[doc = "Field `uart0_rxd_sel` reader - UART0_RXD pin mux: 0:GPIO_18; 1:UART0_RXD; 2:I2C0_SCL"]
2361        pub type Uart0RxdSelR = crate::FieldReader;
2362        #[doc = "Field `uart0_rxd_sel` writer - UART0_RXD pin mux: 0:GPIO_18; 1:UART0_RXD; 2:I2C0_SCL"]
2363        pub type Uart0RxdSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
2364        impl R {
2365            #[doc = "Bits 0:1 - UART0_RXD pin mux: 0:GPIO_18; 1:UART0_RXD; 2:I2C0_SCL"]
2366            #[inline(always)]
2367            pub fn uart0_rxd_sel(&self) -> Uart0RxdSelR {
2368                Uart0RxdSelR::new((self.bits & 3) as u8)
2369            }
2370        }
2371        impl W {
2372            #[doc = "Bits 0:1 - UART0_RXD pin mux: 0:GPIO_18; 1:UART0_RXD; 2:I2C0_SCL"]
2373            #[inline(always)]
2374            pub fn uart0_rxd_sel(&mut self) -> Uart0RxdSelW<'_, Uart0RxdSelSpec> {
2375                Uart0RxdSelW::new(self, 0)
2376            }
2377        }
2378        #[doc = "UART0_RXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_rxd_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_rxd_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2379        pub struct Uart0RxdSelSpec;
2380        impl crate::RegisterSpec for Uart0RxdSelSpec {
2381            type Ux = u32;
2382        }
2383        #[doc = "`read()` method returns [`uart0_rxd_sel::R`](R) reader structure"]
2384        impl crate::Readable for Uart0RxdSelSpec {}
2385        #[doc = "`write(|w| ..)` method takes [`uart0_rxd_sel::W`](W) writer structure"]
2386        impl crate::Writable for Uart0RxdSelSpec {
2387            type Safety = crate::Unsafe;
2388        }
2389        #[doc = "`reset()` method sets UART0_RXD_SEL to value 0"]
2390        impl crate::Resettable for Uart0RxdSelSpec {}
2391    }
2392    #[doc = "PAD_GPIO_00_CTRL (rw) register accessor: GPIO_00 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_00_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_00_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_00_ctrl`] module"]
2393    #[doc(alias = "PAD_GPIO_00_CTRL")]
2394    pub type PadGpio00Ctrl = crate::Reg<pad_gpio_00_ctrl::PadGpio00CtrlSpec>;
2395    #[doc = "GPIO_00 pad control register"]
2396    pub mod pad_gpio_00_ctrl {
2397        #[doc = "Register `PAD_GPIO_00_CTRL` reader"]
2398        pub type R = crate::R<PadGpio00CtrlSpec>;
2399        #[doc = "Register `PAD_GPIO_00_CTRL` writer"]
2400        pub type W = crate::W<PadGpio00CtrlSpec>;
2401        #[doc = "Field `pad_gpio_00_ctrl_st` reader - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
2402        pub type PadGpio00CtrlStR = crate::BitReader;
2403        #[doc = "Field `pad_gpio_00_ctrl_st` writer - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
2404        pub type PadGpio00CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
2405        #[doc = "Field `pad_gpio_00_ctrl_ds0` reader - Drive strength bit 0"]
2406        pub type PadGpio00CtrlDs0R = crate::BitReader;
2407        #[doc = "Field `pad_gpio_00_ctrl_ds0` writer - Drive strength bit 0"]
2408        pub type PadGpio00CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
2409        #[doc = "Field `pad_gpio_00_ctrl_ds1` reader - Drive strength bit 1"]
2410        pub type PadGpio00CtrlDs1R = crate::BitReader;
2411        #[doc = "Field `pad_gpio_00_ctrl_ds1` writer - Drive strength bit 1"]
2412        pub type PadGpio00CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
2413        #[doc = "Field `pad_gpio_00_ctrl_ds2` reader - Drive strength bit 2. DS2~DS0: 111~000, drive strength decreases"]
2414        pub type PadGpio00CtrlDs2R = crate::BitReader;
2415        #[doc = "Field `pad_gpio_00_ctrl_ds2` writer - Drive strength bit 2. DS2~DS0: 111~000, drive strength decreases"]
2416        pub type PadGpio00CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
2417        #[doc = "Field `pad_gpio_00_ctrl_pe` reader - Pull enable. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
2418        pub type PadGpio00CtrlPeR = crate::BitReader;
2419        #[doc = "Field `pad_gpio_00_ctrl_pe` writer - Pull enable. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
2420        pub type PadGpio00CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
2421        #[doc = "Field `pad_gpio_00_ctrl_ps` reader - Pull select. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
2422        pub type PadGpio00CtrlPsR = crate::BitReader;
2423        #[doc = "Field `pad_gpio_00_ctrl_ps` writer - Pull select. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
2424        pub type PadGpio00CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
2425        #[doc = "Field `pad_gpio_00_ctrl_ie` reader - Input enable: 0:input disabled; 1:input enabled"]
2426        pub type PadGpio00CtrlIeR = crate::BitReader;
2427        #[doc = "Field `pad_gpio_00_ctrl_ie` writer - Input enable: 0:input disabled; 1:input enabled"]
2428        pub type PadGpio00CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
2429        impl R {
2430            #[doc = "Bit 3 - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
2431            #[inline(always)]
2432            pub fn pad_gpio_00_ctrl_st(&self) -> PadGpio00CtrlStR {
2433                PadGpio00CtrlStR::new(((self.bits >> 3) & 1) != 0)
2434            }
2435            #[doc = "Bit 4 - Drive strength bit 0"]
2436            #[inline(always)]
2437            pub fn pad_gpio_00_ctrl_ds0(&self) -> PadGpio00CtrlDs0R {
2438                PadGpio00CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
2439            }
2440            #[doc = "Bit 5 - Drive strength bit 1"]
2441            #[inline(always)]
2442            pub fn pad_gpio_00_ctrl_ds1(&self) -> PadGpio00CtrlDs1R {
2443                PadGpio00CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
2444            }
2445            #[doc = "Bit 6 - Drive strength bit 2. DS2~DS0: 111~000, drive strength decreases"]
2446            #[inline(always)]
2447            pub fn pad_gpio_00_ctrl_ds2(&self) -> PadGpio00CtrlDs2R {
2448                PadGpio00CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
2449            }
2450            #[doc = "Bit 9 - Pull enable. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
2451            #[inline(always)]
2452            pub fn pad_gpio_00_ctrl_pe(&self) -> PadGpio00CtrlPeR {
2453                PadGpio00CtrlPeR::new(((self.bits >> 9) & 1) != 0)
2454            }
2455            #[doc = "Bit 10 - Pull select. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
2456            #[inline(always)]
2457            pub fn pad_gpio_00_ctrl_ps(&self) -> PadGpio00CtrlPsR {
2458                PadGpio00CtrlPsR::new(((self.bits >> 10) & 1) != 0)
2459            }
2460            #[doc = "Bit 11 - Input enable: 0:input disabled; 1:input enabled"]
2461            #[inline(always)]
2462            pub fn pad_gpio_00_ctrl_ie(&self) -> PadGpio00CtrlIeR {
2463                PadGpio00CtrlIeR::new(((self.bits >> 11) & 1) != 0)
2464            }
2465        }
2466        impl W {
2467            #[doc = "Bit 3 - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
2468            #[inline(always)]
2469            pub fn pad_gpio_00_ctrl_st(&mut self) -> PadGpio00CtrlStW<'_, PadGpio00CtrlSpec> {
2470                PadGpio00CtrlStW::new(self, 3)
2471            }
2472            #[doc = "Bit 4 - Drive strength bit 0"]
2473            #[inline(always)]
2474            pub fn pad_gpio_00_ctrl_ds0(&mut self) -> PadGpio00CtrlDs0W<'_, PadGpio00CtrlSpec> {
2475                PadGpio00CtrlDs0W::new(self, 4)
2476            }
2477            #[doc = "Bit 5 - Drive strength bit 1"]
2478            #[inline(always)]
2479            pub fn pad_gpio_00_ctrl_ds1(&mut self) -> PadGpio00CtrlDs1W<'_, PadGpio00CtrlSpec> {
2480                PadGpio00CtrlDs1W::new(self, 5)
2481            }
2482            #[doc = "Bit 6 - Drive strength bit 2. DS2~DS0: 111~000, drive strength decreases"]
2483            #[inline(always)]
2484            pub fn pad_gpio_00_ctrl_ds2(&mut self) -> PadGpio00CtrlDs2W<'_, PadGpio00CtrlSpec> {
2485                PadGpio00CtrlDs2W::new(self, 6)
2486            }
2487            #[doc = "Bit 9 - Pull enable. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
2488            #[inline(always)]
2489            pub fn pad_gpio_00_ctrl_pe(&mut self) -> PadGpio00CtrlPeW<'_, PadGpio00CtrlSpec> {
2490                PadGpio00CtrlPeW::new(self, 9)
2491            }
2492            #[doc = "Bit 10 - Pull select. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
2493            #[inline(always)]
2494            pub fn pad_gpio_00_ctrl_ps(&mut self) -> PadGpio00CtrlPsW<'_, PadGpio00CtrlSpec> {
2495                PadGpio00CtrlPsW::new(self, 10)
2496            }
2497            #[doc = "Bit 11 - Input enable: 0:input disabled; 1:input enabled"]
2498            #[inline(always)]
2499            pub fn pad_gpio_00_ctrl_ie(&mut self) -> PadGpio00CtrlIeW<'_, PadGpio00CtrlSpec> {
2500                PadGpio00CtrlIeW::new(self, 11)
2501            }
2502        }
2503        #[doc = "GPIO_00 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_00_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_00_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2504        pub struct PadGpio00CtrlSpec;
2505        impl crate::RegisterSpec for PadGpio00CtrlSpec {
2506            type Ux = u32;
2507        }
2508        #[doc = "`read()` method returns [`pad_gpio_00_ctrl::R`](R) reader structure"]
2509        impl crate::Readable for PadGpio00CtrlSpec {}
2510        #[doc = "`write(|w| ..)` method takes [`pad_gpio_00_ctrl::W`](W) writer structure"]
2511        impl crate::Writable for PadGpio00CtrlSpec {
2512            type Safety = crate::Unsafe;
2513        }
2514        #[doc = "`reset()` method sets PAD_GPIO_00_CTRL to value 0x0800"]
2515        impl crate::Resettable for PadGpio00CtrlSpec {
2516            const RESET_VALUE: u32 = 0x0800;
2517        }
2518    }
2519    #[doc = "PAD_GPIO_01_CTRL (rw) register accessor: GPIO_01 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_01_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_01_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_01_ctrl`] module"]
2520    #[doc(alias = "PAD_GPIO_01_CTRL")]
2521    pub type PadGpio01Ctrl = crate::Reg<pad_gpio_01_ctrl::PadGpio01CtrlSpec>;
2522    #[doc = "GPIO_01 pad control register"]
2523    pub mod pad_gpio_01_ctrl {
2524        #[doc = "Register `PAD_GPIO_01_CTRL` reader"]
2525        pub type R = crate::R<PadGpio01CtrlSpec>;
2526        #[doc = "Register `PAD_GPIO_01_CTRL` writer"]
2527        pub type W = crate::W<PadGpio01CtrlSpec>;
2528        #[doc = "Field `pad_gpio_01_ctrl_st` reader - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
2529        pub type PadGpio01CtrlStR = crate::BitReader;
2530        #[doc = "Field `pad_gpio_01_ctrl_st` writer - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
2531        pub type PadGpio01CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
2532        #[doc = "Field `pad_gpio_01_ctrl_ds0` reader - Drive strength bit 0"]
2533        pub type PadGpio01CtrlDs0R = crate::BitReader;
2534        #[doc = "Field `pad_gpio_01_ctrl_ds0` writer - Drive strength bit 0"]
2535        pub type PadGpio01CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
2536        #[doc = "Field `pad_gpio_01_ctrl_ds1` reader - Drive strength bit 1"]
2537        pub type PadGpio01CtrlDs1R = crate::BitReader;
2538        #[doc = "Field `pad_gpio_01_ctrl_ds1` writer - Drive strength bit 1"]
2539        pub type PadGpio01CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
2540        #[doc = "Field `pad_gpio_01_ctrl_ds2` reader - Drive strength bit 2"]
2541        pub type PadGpio01CtrlDs2R = crate::BitReader;
2542        #[doc = "Field `pad_gpio_01_ctrl_ds2` writer - Drive strength bit 2"]
2543        pub type PadGpio01CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
2544        #[doc = "Field `pad_gpio_01_ctrl_pe` reader - Pull enable"]
2545        pub type PadGpio01CtrlPeR = crate::BitReader;
2546        #[doc = "Field `pad_gpio_01_ctrl_pe` writer - Pull enable"]
2547        pub type PadGpio01CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
2548        #[doc = "Field `pad_gpio_01_ctrl_ps` reader - Pull select"]
2549        pub type PadGpio01CtrlPsR = crate::BitReader;
2550        #[doc = "Field `pad_gpio_01_ctrl_ps` writer - Pull select"]
2551        pub type PadGpio01CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
2552        #[doc = "Field `pad_gpio_01_ctrl_ie` reader - Input enable"]
2553        pub type PadGpio01CtrlIeR = crate::BitReader;
2554        #[doc = "Field `pad_gpio_01_ctrl_ie` writer - Input enable"]
2555        pub type PadGpio01CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
2556        impl R {
2557            #[doc = "Bit 3 - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
2558            #[inline(always)]
2559            pub fn pad_gpio_01_ctrl_st(&self) -> PadGpio01CtrlStR {
2560                PadGpio01CtrlStR::new(((self.bits >> 3) & 1) != 0)
2561            }
2562            #[doc = "Bit 4 - Drive strength bit 0"]
2563            #[inline(always)]
2564            pub fn pad_gpio_01_ctrl_ds0(&self) -> PadGpio01CtrlDs0R {
2565                PadGpio01CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
2566            }
2567            #[doc = "Bit 5 - Drive strength bit 1"]
2568            #[inline(always)]
2569            pub fn pad_gpio_01_ctrl_ds1(&self) -> PadGpio01CtrlDs1R {
2570                PadGpio01CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
2571            }
2572            #[doc = "Bit 6 - Drive strength bit 2"]
2573            #[inline(always)]
2574            pub fn pad_gpio_01_ctrl_ds2(&self) -> PadGpio01CtrlDs2R {
2575                PadGpio01CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
2576            }
2577            #[doc = "Bit 9 - Pull enable"]
2578            #[inline(always)]
2579            pub fn pad_gpio_01_ctrl_pe(&self) -> PadGpio01CtrlPeR {
2580                PadGpio01CtrlPeR::new(((self.bits >> 9) & 1) != 0)
2581            }
2582            #[doc = "Bit 10 - Pull select"]
2583            #[inline(always)]
2584            pub fn pad_gpio_01_ctrl_ps(&self) -> PadGpio01CtrlPsR {
2585                PadGpio01CtrlPsR::new(((self.bits >> 10) & 1) != 0)
2586            }
2587            #[doc = "Bit 11 - Input enable"]
2588            #[inline(always)]
2589            pub fn pad_gpio_01_ctrl_ie(&self) -> PadGpio01CtrlIeR {
2590                PadGpio01CtrlIeR::new(((self.bits >> 11) & 1) != 0)
2591            }
2592        }
2593        impl W {
2594            #[doc = "Bit 3 - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
2595            #[inline(always)]
2596            pub fn pad_gpio_01_ctrl_st(&mut self) -> PadGpio01CtrlStW<'_, PadGpio01CtrlSpec> {
2597                PadGpio01CtrlStW::new(self, 3)
2598            }
2599            #[doc = "Bit 4 - Drive strength bit 0"]
2600            #[inline(always)]
2601            pub fn pad_gpio_01_ctrl_ds0(&mut self) -> PadGpio01CtrlDs0W<'_, PadGpio01CtrlSpec> {
2602                PadGpio01CtrlDs0W::new(self, 4)
2603            }
2604            #[doc = "Bit 5 - Drive strength bit 1"]
2605            #[inline(always)]
2606            pub fn pad_gpio_01_ctrl_ds1(&mut self) -> PadGpio01CtrlDs1W<'_, PadGpio01CtrlSpec> {
2607                PadGpio01CtrlDs1W::new(self, 5)
2608            }
2609            #[doc = "Bit 6 - Drive strength bit 2"]
2610            #[inline(always)]
2611            pub fn pad_gpio_01_ctrl_ds2(&mut self) -> PadGpio01CtrlDs2W<'_, PadGpio01CtrlSpec> {
2612                PadGpio01CtrlDs2W::new(self, 6)
2613            }
2614            #[doc = "Bit 9 - Pull enable"]
2615            #[inline(always)]
2616            pub fn pad_gpio_01_ctrl_pe(&mut self) -> PadGpio01CtrlPeW<'_, PadGpio01CtrlSpec> {
2617                PadGpio01CtrlPeW::new(self, 9)
2618            }
2619            #[doc = "Bit 10 - Pull select"]
2620            #[inline(always)]
2621            pub fn pad_gpio_01_ctrl_ps(&mut self) -> PadGpio01CtrlPsW<'_, PadGpio01CtrlSpec> {
2622                PadGpio01CtrlPsW::new(self, 10)
2623            }
2624            #[doc = "Bit 11 - Input enable"]
2625            #[inline(always)]
2626            pub fn pad_gpio_01_ctrl_ie(&mut self) -> PadGpio01CtrlIeW<'_, PadGpio01CtrlSpec> {
2627                PadGpio01CtrlIeW::new(self, 11)
2628            }
2629        }
2630        #[doc = "GPIO_01 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_01_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_01_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2631        pub struct PadGpio01CtrlSpec;
2632        impl crate::RegisterSpec for PadGpio01CtrlSpec {
2633            type Ux = u32;
2634        }
2635        #[doc = "`read()` method returns [`pad_gpio_01_ctrl::R`](R) reader structure"]
2636        impl crate::Readable for PadGpio01CtrlSpec {}
2637        #[doc = "`write(|w| ..)` method takes [`pad_gpio_01_ctrl::W`](W) writer structure"]
2638        impl crate::Writable for PadGpio01CtrlSpec {
2639            type Safety = crate::Unsafe;
2640        }
2641        #[doc = "`reset()` method sets PAD_GPIO_01_CTRL to value 0x0a00"]
2642        impl crate::Resettable for PadGpio01CtrlSpec {
2643            const RESET_VALUE: u32 = 0x0a00;
2644        }
2645    }
2646    #[doc = "PAD_GPIO_02_CTRL (rw) register accessor: GPIO_02 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_02_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_02_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_02_ctrl`] module"]
2647    #[doc(alias = "PAD_GPIO_02_CTRL")]
2648    pub type PadGpio02Ctrl = crate::Reg<pad_gpio_02_ctrl::PadGpio02CtrlSpec>;
2649    #[doc = "GPIO_02 pad control register"]
2650    pub mod pad_gpio_02_ctrl {
2651        #[doc = "Register `PAD_GPIO_02_CTRL` reader"]
2652        pub type R = crate::R<PadGpio02CtrlSpec>;
2653        #[doc = "Register `PAD_GPIO_02_CTRL` writer"]
2654        pub type W = crate::W<PadGpio02CtrlSpec>;
2655        #[doc = "Field `pad_gpio_02_ctrl_st` reader - Schmitt trigger"]
2656        pub type PadGpio02CtrlStR = crate::BitReader;
2657        #[doc = "Field `pad_gpio_02_ctrl_st` writer - Schmitt trigger"]
2658        pub type PadGpio02CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
2659        #[doc = "Field `pad_gpio_02_ctrl_ds0` reader - Drive strength bit 0"]
2660        pub type PadGpio02CtrlDs0R = crate::BitReader;
2661        #[doc = "Field `pad_gpio_02_ctrl_ds0` writer - Drive strength bit 0"]
2662        pub type PadGpio02CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
2663        #[doc = "Field `pad_gpio_02_ctrl_ds1` reader - Drive strength bit 1"]
2664        pub type PadGpio02CtrlDs1R = crate::BitReader;
2665        #[doc = "Field `pad_gpio_02_ctrl_ds1` writer - Drive strength bit 1"]
2666        pub type PadGpio02CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
2667        #[doc = "Field `pad_gpio_02_ctrl_ds2` reader - Drive strength bit 2"]
2668        pub type PadGpio02CtrlDs2R = crate::BitReader;
2669        #[doc = "Field `pad_gpio_02_ctrl_ds2` writer - Drive strength bit 2"]
2670        pub type PadGpio02CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
2671        #[doc = "Field `pad_gpio_02_ctrl_pe` reader - Pull enable"]
2672        pub type PadGpio02CtrlPeR = crate::BitReader;
2673        #[doc = "Field `pad_gpio_02_ctrl_pe` writer - Pull enable"]
2674        pub type PadGpio02CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
2675        #[doc = "Field `pad_gpio_02_ctrl_ps` reader - Pull select"]
2676        pub type PadGpio02CtrlPsR = crate::BitReader;
2677        #[doc = "Field `pad_gpio_02_ctrl_ps` writer - Pull select"]
2678        pub type PadGpio02CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
2679        #[doc = "Field `pad_gpio_02_ctrl_ie` reader - Input enable"]
2680        pub type PadGpio02CtrlIeR = crate::BitReader;
2681        #[doc = "Field `pad_gpio_02_ctrl_ie` writer - Input enable"]
2682        pub type PadGpio02CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
2683        impl R {
2684            #[doc = "Bit 3 - Schmitt trigger"]
2685            #[inline(always)]
2686            pub fn pad_gpio_02_ctrl_st(&self) -> PadGpio02CtrlStR {
2687                PadGpio02CtrlStR::new(((self.bits >> 3) & 1) != 0)
2688            }
2689            #[doc = "Bit 4 - Drive strength bit 0"]
2690            #[inline(always)]
2691            pub fn pad_gpio_02_ctrl_ds0(&self) -> PadGpio02CtrlDs0R {
2692                PadGpio02CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
2693            }
2694            #[doc = "Bit 5 - Drive strength bit 1"]
2695            #[inline(always)]
2696            pub fn pad_gpio_02_ctrl_ds1(&self) -> PadGpio02CtrlDs1R {
2697                PadGpio02CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
2698            }
2699            #[doc = "Bit 6 - Drive strength bit 2"]
2700            #[inline(always)]
2701            pub fn pad_gpio_02_ctrl_ds2(&self) -> PadGpio02CtrlDs2R {
2702                PadGpio02CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
2703            }
2704            #[doc = "Bit 9 - Pull enable"]
2705            #[inline(always)]
2706            pub fn pad_gpio_02_ctrl_pe(&self) -> PadGpio02CtrlPeR {
2707                PadGpio02CtrlPeR::new(((self.bits >> 9) & 1) != 0)
2708            }
2709            #[doc = "Bit 10 - Pull select"]
2710            #[inline(always)]
2711            pub fn pad_gpio_02_ctrl_ps(&self) -> PadGpio02CtrlPsR {
2712                PadGpio02CtrlPsR::new(((self.bits >> 10) & 1) != 0)
2713            }
2714            #[doc = "Bit 11 - Input enable"]
2715            #[inline(always)]
2716            pub fn pad_gpio_02_ctrl_ie(&self) -> PadGpio02CtrlIeR {
2717                PadGpio02CtrlIeR::new(((self.bits >> 11) & 1) != 0)
2718            }
2719        }
2720        impl W {
2721            #[doc = "Bit 3 - Schmitt trigger"]
2722            #[inline(always)]
2723            pub fn pad_gpio_02_ctrl_st(&mut self) -> PadGpio02CtrlStW<'_, PadGpio02CtrlSpec> {
2724                PadGpio02CtrlStW::new(self, 3)
2725            }
2726            #[doc = "Bit 4 - Drive strength bit 0"]
2727            #[inline(always)]
2728            pub fn pad_gpio_02_ctrl_ds0(&mut self) -> PadGpio02CtrlDs0W<'_, PadGpio02CtrlSpec> {
2729                PadGpio02CtrlDs0W::new(self, 4)
2730            }
2731            #[doc = "Bit 5 - Drive strength bit 1"]
2732            #[inline(always)]
2733            pub fn pad_gpio_02_ctrl_ds1(&mut self) -> PadGpio02CtrlDs1W<'_, PadGpio02CtrlSpec> {
2734                PadGpio02CtrlDs1W::new(self, 5)
2735            }
2736            #[doc = "Bit 6 - Drive strength bit 2"]
2737            #[inline(always)]
2738            pub fn pad_gpio_02_ctrl_ds2(&mut self) -> PadGpio02CtrlDs2W<'_, PadGpio02CtrlSpec> {
2739                PadGpio02CtrlDs2W::new(self, 6)
2740            }
2741            #[doc = "Bit 9 - Pull enable"]
2742            #[inline(always)]
2743            pub fn pad_gpio_02_ctrl_pe(&mut self) -> PadGpio02CtrlPeW<'_, PadGpio02CtrlSpec> {
2744                PadGpio02CtrlPeW::new(self, 9)
2745            }
2746            #[doc = "Bit 10 - Pull select"]
2747            #[inline(always)]
2748            pub fn pad_gpio_02_ctrl_ps(&mut self) -> PadGpio02CtrlPsW<'_, PadGpio02CtrlSpec> {
2749                PadGpio02CtrlPsW::new(self, 10)
2750            }
2751            #[doc = "Bit 11 - Input enable"]
2752            #[inline(always)]
2753            pub fn pad_gpio_02_ctrl_ie(&mut self) -> PadGpio02CtrlIeW<'_, PadGpio02CtrlSpec> {
2754                PadGpio02CtrlIeW::new(self, 11)
2755            }
2756        }
2757        #[doc = "GPIO_02 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_02_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_02_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2758        pub struct PadGpio02CtrlSpec;
2759        impl crate::RegisterSpec for PadGpio02CtrlSpec {
2760            type Ux = u32;
2761        }
2762        #[doc = "`read()` method returns [`pad_gpio_02_ctrl::R`](R) reader structure"]
2763        impl crate::Readable for PadGpio02CtrlSpec {}
2764        #[doc = "`write(|w| ..)` method takes [`pad_gpio_02_ctrl::W`](W) writer structure"]
2765        impl crate::Writable for PadGpio02CtrlSpec {
2766            type Safety = crate::Unsafe;
2767        }
2768        #[doc = "`reset()` method sets PAD_GPIO_02_CTRL to value 0x0800"]
2769        impl crate::Resettable for PadGpio02CtrlSpec {
2770            const RESET_VALUE: u32 = 0x0800;
2771        }
2772    }
2773    #[doc = "PAD_GPIO_03_CTRL (rw) register accessor: GPIO_03 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_03_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_03_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_03_ctrl`] module"]
2774    #[doc(alias = "PAD_GPIO_03_CTRL")]
2775    pub type PadGpio03Ctrl = crate::Reg<pad_gpio_03_ctrl::PadGpio03CtrlSpec>;
2776    #[doc = "GPIO_03 pad control register"]
2777    pub mod pad_gpio_03_ctrl {
2778        #[doc = "Register `PAD_GPIO_03_CTRL` reader"]
2779        pub type R = crate::R<PadGpio03CtrlSpec>;
2780        #[doc = "Register `PAD_GPIO_03_CTRL` writer"]
2781        pub type W = crate::W<PadGpio03CtrlSpec>;
2782        #[doc = "Field `pad_gpio_03_ctrl_st` reader - Schmitt trigger"]
2783        pub type PadGpio03CtrlStR = crate::BitReader;
2784        #[doc = "Field `pad_gpio_03_ctrl_st` writer - Schmitt trigger"]
2785        pub type PadGpio03CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
2786        #[doc = "Field `pad_gpio_03_ctrl_ds0` reader - Drive strength bit 0"]
2787        pub type PadGpio03CtrlDs0R = crate::BitReader;
2788        #[doc = "Field `pad_gpio_03_ctrl_ds0` writer - Drive strength bit 0"]
2789        pub type PadGpio03CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
2790        #[doc = "Field `pad_gpio_03_ctrl_ds1` reader - Drive strength bit 1"]
2791        pub type PadGpio03CtrlDs1R = crate::BitReader;
2792        #[doc = "Field `pad_gpio_03_ctrl_ds1` writer - Drive strength bit 1"]
2793        pub type PadGpio03CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
2794        #[doc = "Field `pad_gpio_03_ctrl_ds2` reader - Drive strength bit 2"]
2795        pub type PadGpio03CtrlDs2R = crate::BitReader;
2796        #[doc = "Field `pad_gpio_03_ctrl_ds2` writer - Drive strength bit 2"]
2797        pub type PadGpio03CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
2798        #[doc = "Field `pad_gpio_03_ctrl_pe` reader - Pull enable"]
2799        pub type PadGpio03CtrlPeR = crate::BitReader;
2800        #[doc = "Field `pad_gpio_03_ctrl_pe` writer - Pull enable"]
2801        pub type PadGpio03CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
2802        #[doc = "Field `pad_gpio_03_ctrl_ps` reader - Pull select"]
2803        pub type PadGpio03CtrlPsR = crate::BitReader;
2804        #[doc = "Field `pad_gpio_03_ctrl_ps` writer - Pull select"]
2805        pub type PadGpio03CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
2806        #[doc = "Field `pad_gpio_03_ctrl_ie` reader - Input enable"]
2807        pub type PadGpio03CtrlIeR = crate::BitReader;
2808        #[doc = "Field `pad_gpio_03_ctrl_ie` writer - Input enable"]
2809        pub type PadGpio03CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
2810        impl R {
2811            #[doc = "Bit 3 - Schmitt trigger"]
2812            #[inline(always)]
2813            pub fn pad_gpio_03_ctrl_st(&self) -> PadGpio03CtrlStR {
2814                PadGpio03CtrlStR::new(((self.bits >> 3) & 1) != 0)
2815            }
2816            #[doc = "Bit 4 - Drive strength bit 0"]
2817            #[inline(always)]
2818            pub fn pad_gpio_03_ctrl_ds0(&self) -> PadGpio03CtrlDs0R {
2819                PadGpio03CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
2820            }
2821            #[doc = "Bit 5 - Drive strength bit 1"]
2822            #[inline(always)]
2823            pub fn pad_gpio_03_ctrl_ds1(&self) -> PadGpio03CtrlDs1R {
2824                PadGpio03CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
2825            }
2826            #[doc = "Bit 6 - Drive strength bit 2"]
2827            #[inline(always)]
2828            pub fn pad_gpio_03_ctrl_ds2(&self) -> PadGpio03CtrlDs2R {
2829                PadGpio03CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
2830            }
2831            #[doc = "Bit 9 - Pull enable"]
2832            #[inline(always)]
2833            pub fn pad_gpio_03_ctrl_pe(&self) -> PadGpio03CtrlPeR {
2834                PadGpio03CtrlPeR::new(((self.bits >> 9) & 1) != 0)
2835            }
2836            #[doc = "Bit 10 - Pull select"]
2837            #[inline(always)]
2838            pub fn pad_gpio_03_ctrl_ps(&self) -> PadGpio03CtrlPsR {
2839                PadGpio03CtrlPsR::new(((self.bits >> 10) & 1) != 0)
2840            }
2841            #[doc = "Bit 11 - Input enable"]
2842            #[inline(always)]
2843            pub fn pad_gpio_03_ctrl_ie(&self) -> PadGpio03CtrlIeR {
2844                PadGpio03CtrlIeR::new(((self.bits >> 11) & 1) != 0)
2845            }
2846        }
2847        impl W {
2848            #[doc = "Bit 3 - Schmitt trigger"]
2849            #[inline(always)]
2850            pub fn pad_gpio_03_ctrl_st(&mut self) -> PadGpio03CtrlStW<'_, PadGpio03CtrlSpec> {
2851                PadGpio03CtrlStW::new(self, 3)
2852            }
2853            #[doc = "Bit 4 - Drive strength bit 0"]
2854            #[inline(always)]
2855            pub fn pad_gpio_03_ctrl_ds0(&mut self) -> PadGpio03CtrlDs0W<'_, PadGpio03CtrlSpec> {
2856                PadGpio03CtrlDs0W::new(self, 4)
2857            }
2858            #[doc = "Bit 5 - Drive strength bit 1"]
2859            #[inline(always)]
2860            pub fn pad_gpio_03_ctrl_ds1(&mut self) -> PadGpio03CtrlDs1W<'_, PadGpio03CtrlSpec> {
2861                PadGpio03CtrlDs1W::new(self, 5)
2862            }
2863            #[doc = "Bit 6 - Drive strength bit 2"]
2864            #[inline(always)]
2865            pub fn pad_gpio_03_ctrl_ds2(&mut self) -> PadGpio03CtrlDs2W<'_, PadGpio03CtrlSpec> {
2866                PadGpio03CtrlDs2W::new(self, 6)
2867            }
2868            #[doc = "Bit 9 - Pull enable"]
2869            #[inline(always)]
2870            pub fn pad_gpio_03_ctrl_pe(&mut self) -> PadGpio03CtrlPeW<'_, PadGpio03CtrlSpec> {
2871                PadGpio03CtrlPeW::new(self, 9)
2872            }
2873            #[doc = "Bit 10 - Pull select"]
2874            #[inline(always)]
2875            pub fn pad_gpio_03_ctrl_ps(&mut self) -> PadGpio03CtrlPsW<'_, PadGpio03CtrlSpec> {
2876                PadGpio03CtrlPsW::new(self, 10)
2877            }
2878            #[doc = "Bit 11 - Input enable"]
2879            #[inline(always)]
2880            pub fn pad_gpio_03_ctrl_ie(&mut self) -> PadGpio03CtrlIeW<'_, PadGpio03CtrlSpec> {
2881                PadGpio03CtrlIeW::new(self, 11)
2882            }
2883        }
2884        #[doc = "GPIO_03 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_03_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_03_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2885        pub struct PadGpio03CtrlSpec;
2886        impl crate::RegisterSpec for PadGpio03CtrlSpec {
2887            type Ux = u32;
2888        }
2889        #[doc = "`read()` method returns [`pad_gpio_03_ctrl::R`](R) reader structure"]
2890        impl crate::Readable for PadGpio03CtrlSpec {}
2891        #[doc = "`write(|w| ..)` method takes [`pad_gpio_03_ctrl::W`](W) writer structure"]
2892        impl crate::Writable for PadGpio03CtrlSpec {
2893            type Safety = crate::Unsafe;
2894        }
2895        #[doc = "`reset()` method sets PAD_GPIO_03_CTRL to value 0x0a00"]
2896        impl crate::Resettable for PadGpio03CtrlSpec {
2897            const RESET_VALUE: u32 = 0x0a00;
2898        }
2899    }
2900    #[doc = "PAD_GPIO_04_CTRL (rw) register accessor: GPIO_04 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_04_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_04_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_04_ctrl`] module"]
2901    #[doc(alias = "PAD_GPIO_04_CTRL")]
2902    pub type PadGpio04Ctrl = crate::Reg<pad_gpio_04_ctrl::PadGpio04CtrlSpec>;
2903    #[doc = "GPIO_04 pad control register"]
2904    pub mod pad_gpio_04_ctrl {
2905        #[doc = "Register `PAD_GPIO_04_CTRL` reader"]
2906        pub type R = crate::R<PadGpio04CtrlSpec>;
2907        #[doc = "Register `PAD_GPIO_04_CTRL` writer"]
2908        pub type W = crate::W<PadGpio04CtrlSpec>;
2909        #[doc = "Field `pad_gpio_04_ctrl_st` reader - Schmitt trigger"]
2910        pub type PadGpio04CtrlStR = crate::BitReader;
2911        #[doc = "Field `pad_gpio_04_ctrl_st` writer - Schmitt trigger"]
2912        pub type PadGpio04CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
2913        #[doc = "Field `pad_gpio_04_ctrl_ds0` reader - Drive strength bit 0"]
2914        pub type PadGpio04CtrlDs0R = crate::BitReader;
2915        #[doc = "Field `pad_gpio_04_ctrl_ds0` writer - Drive strength bit 0"]
2916        pub type PadGpio04CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
2917        #[doc = "Field `pad_gpio_04_ctrl_ds1` reader - Drive strength bit 1"]
2918        pub type PadGpio04CtrlDs1R = crate::BitReader;
2919        #[doc = "Field `pad_gpio_04_ctrl_ds1` writer - Drive strength bit 1"]
2920        pub type PadGpio04CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
2921        #[doc = "Field `pad_gpio_04_ctrl_ds2` reader - Drive strength bit 2"]
2922        pub type PadGpio04CtrlDs2R = crate::BitReader;
2923        #[doc = "Field `pad_gpio_04_ctrl_ds2` writer - Drive strength bit 2"]
2924        pub type PadGpio04CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
2925        #[doc = "Field `pad_gpio_04_ctrl_pe` reader - Pull enable"]
2926        pub type PadGpio04CtrlPeR = crate::BitReader;
2927        #[doc = "Field `pad_gpio_04_ctrl_pe` writer - Pull enable"]
2928        pub type PadGpio04CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
2929        #[doc = "Field `pad_gpio_04_ctrl_ps` reader - Pull select"]
2930        pub type PadGpio04CtrlPsR = crate::BitReader;
2931        #[doc = "Field `pad_gpio_04_ctrl_ps` writer - Pull select"]
2932        pub type PadGpio04CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
2933        #[doc = "Field `pad_gpio_04_ctrl_ie` reader - Input enable"]
2934        pub type PadGpio04CtrlIeR = crate::BitReader;
2935        #[doc = "Field `pad_gpio_04_ctrl_ie` writer - Input enable"]
2936        pub type PadGpio04CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
2937        impl R {
2938            #[doc = "Bit 3 - Schmitt trigger"]
2939            #[inline(always)]
2940            pub fn pad_gpio_04_ctrl_st(&self) -> PadGpio04CtrlStR {
2941                PadGpio04CtrlStR::new(((self.bits >> 3) & 1) != 0)
2942            }
2943            #[doc = "Bit 4 - Drive strength bit 0"]
2944            #[inline(always)]
2945            pub fn pad_gpio_04_ctrl_ds0(&self) -> PadGpio04CtrlDs0R {
2946                PadGpio04CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
2947            }
2948            #[doc = "Bit 5 - Drive strength bit 1"]
2949            #[inline(always)]
2950            pub fn pad_gpio_04_ctrl_ds1(&self) -> PadGpio04CtrlDs1R {
2951                PadGpio04CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
2952            }
2953            #[doc = "Bit 6 - Drive strength bit 2"]
2954            #[inline(always)]
2955            pub fn pad_gpio_04_ctrl_ds2(&self) -> PadGpio04CtrlDs2R {
2956                PadGpio04CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
2957            }
2958            #[doc = "Bit 9 - Pull enable"]
2959            #[inline(always)]
2960            pub fn pad_gpio_04_ctrl_pe(&self) -> PadGpio04CtrlPeR {
2961                PadGpio04CtrlPeR::new(((self.bits >> 9) & 1) != 0)
2962            }
2963            #[doc = "Bit 10 - Pull select"]
2964            #[inline(always)]
2965            pub fn pad_gpio_04_ctrl_ps(&self) -> PadGpio04CtrlPsR {
2966                PadGpio04CtrlPsR::new(((self.bits >> 10) & 1) != 0)
2967            }
2968            #[doc = "Bit 11 - Input enable"]
2969            #[inline(always)]
2970            pub fn pad_gpio_04_ctrl_ie(&self) -> PadGpio04CtrlIeR {
2971                PadGpio04CtrlIeR::new(((self.bits >> 11) & 1) != 0)
2972            }
2973        }
2974        impl W {
2975            #[doc = "Bit 3 - Schmitt trigger"]
2976            #[inline(always)]
2977            pub fn pad_gpio_04_ctrl_st(&mut self) -> PadGpio04CtrlStW<'_, PadGpio04CtrlSpec> {
2978                PadGpio04CtrlStW::new(self, 3)
2979            }
2980            #[doc = "Bit 4 - Drive strength bit 0"]
2981            #[inline(always)]
2982            pub fn pad_gpio_04_ctrl_ds0(&mut self) -> PadGpio04CtrlDs0W<'_, PadGpio04CtrlSpec> {
2983                PadGpio04CtrlDs0W::new(self, 4)
2984            }
2985            #[doc = "Bit 5 - Drive strength bit 1"]
2986            #[inline(always)]
2987            pub fn pad_gpio_04_ctrl_ds1(&mut self) -> PadGpio04CtrlDs1W<'_, PadGpio04CtrlSpec> {
2988                PadGpio04CtrlDs1W::new(self, 5)
2989            }
2990            #[doc = "Bit 6 - Drive strength bit 2"]
2991            #[inline(always)]
2992            pub fn pad_gpio_04_ctrl_ds2(&mut self) -> PadGpio04CtrlDs2W<'_, PadGpio04CtrlSpec> {
2993                PadGpio04CtrlDs2W::new(self, 6)
2994            }
2995            #[doc = "Bit 9 - Pull enable"]
2996            #[inline(always)]
2997            pub fn pad_gpio_04_ctrl_pe(&mut self) -> PadGpio04CtrlPeW<'_, PadGpio04CtrlSpec> {
2998                PadGpio04CtrlPeW::new(self, 9)
2999            }
3000            #[doc = "Bit 10 - Pull select"]
3001            #[inline(always)]
3002            pub fn pad_gpio_04_ctrl_ps(&mut self) -> PadGpio04CtrlPsW<'_, PadGpio04CtrlSpec> {
3003                PadGpio04CtrlPsW::new(self, 10)
3004            }
3005            #[doc = "Bit 11 - Input enable"]
3006            #[inline(always)]
3007            pub fn pad_gpio_04_ctrl_ie(&mut self) -> PadGpio04CtrlIeW<'_, PadGpio04CtrlSpec> {
3008                PadGpio04CtrlIeW::new(self, 11)
3009            }
3010        }
3011        #[doc = "GPIO_04 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_04_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_04_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3012        pub struct PadGpio04CtrlSpec;
3013        impl crate::RegisterSpec for PadGpio04CtrlSpec {
3014            type Ux = u32;
3015        }
3016        #[doc = "`read()` method returns [`pad_gpio_04_ctrl::R`](R) reader structure"]
3017        impl crate::Readable for PadGpio04CtrlSpec {}
3018        #[doc = "`write(|w| ..)` method takes [`pad_gpio_04_ctrl::W`](W) writer structure"]
3019        impl crate::Writable for PadGpio04CtrlSpec {
3020            type Safety = crate::Unsafe;
3021        }
3022        #[doc = "`reset()` method sets PAD_GPIO_04_CTRL to value 0x0a00"]
3023        impl crate::Resettable for PadGpio04CtrlSpec {
3024            const RESET_VALUE: u32 = 0x0a00;
3025        }
3026    }
3027    #[doc = "PAD_GPIO_05_CTRL (rw) register accessor: GPIO_05 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_05_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_05_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_05_ctrl`] module"]
3028    #[doc(alias = "PAD_GPIO_05_CTRL")]
3029    pub type PadGpio05Ctrl = crate::Reg<pad_gpio_05_ctrl::PadGpio05CtrlSpec>;
3030    #[doc = "GPIO_05 pad control register"]
3031    pub mod pad_gpio_05_ctrl {
3032        #[doc = "Register `PAD_GPIO_05_CTRL` reader"]
3033        pub type R = crate::R<PadGpio05CtrlSpec>;
3034        #[doc = "Register `PAD_GPIO_05_CTRL` writer"]
3035        pub type W = crate::W<PadGpio05CtrlSpec>;
3036        #[doc = "Field `pad_gpio_05_ctrl_st` reader - Schmitt trigger"]
3037        pub type PadGpio05CtrlStR = crate::BitReader;
3038        #[doc = "Field `pad_gpio_05_ctrl_st` writer - Schmitt trigger"]
3039        pub type PadGpio05CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
3040        #[doc = "Field `pad_gpio_05_ctrl_ds0` reader - Drive strength bit 0"]
3041        pub type PadGpio05CtrlDs0R = crate::BitReader;
3042        #[doc = "Field `pad_gpio_05_ctrl_ds0` writer - Drive strength bit 0"]
3043        pub type PadGpio05CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
3044        #[doc = "Field `pad_gpio_05_ctrl_ds1` reader - Drive strength bit 1"]
3045        pub type PadGpio05CtrlDs1R = crate::BitReader;
3046        #[doc = "Field `pad_gpio_05_ctrl_ds1` writer - Drive strength bit 1"]
3047        pub type PadGpio05CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
3048        #[doc = "Field `pad_gpio_05_ctrl_ds2` reader - Drive strength bit 2"]
3049        pub type PadGpio05CtrlDs2R = crate::BitReader;
3050        #[doc = "Field `pad_gpio_05_ctrl_ds2` writer - Drive strength bit 2"]
3051        pub type PadGpio05CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
3052        #[doc = "Field `pad_gpio_05_ctrl_pe` reader - Pull enable"]
3053        pub type PadGpio05CtrlPeR = crate::BitReader;
3054        #[doc = "Field `pad_gpio_05_ctrl_pe` writer - Pull enable"]
3055        pub type PadGpio05CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
3056        #[doc = "Field `pad_gpio_05_ctrl_ps` reader - Pull select"]
3057        pub type PadGpio05CtrlPsR = crate::BitReader;
3058        #[doc = "Field `pad_gpio_05_ctrl_ps` writer - Pull select"]
3059        pub type PadGpio05CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
3060        #[doc = "Field `pad_gpio_05_ctrl_ie` reader - Input enable"]
3061        pub type PadGpio05CtrlIeR = crate::BitReader;
3062        #[doc = "Field `pad_gpio_05_ctrl_ie` writer - Input enable"]
3063        pub type PadGpio05CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
3064        impl R {
3065            #[doc = "Bit 3 - Schmitt trigger"]
3066            #[inline(always)]
3067            pub fn pad_gpio_05_ctrl_st(&self) -> PadGpio05CtrlStR {
3068                PadGpio05CtrlStR::new(((self.bits >> 3) & 1) != 0)
3069            }
3070            #[doc = "Bit 4 - Drive strength bit 0"]
3071            #[inline(always)]
3072            pub fn pad_gpio_05_ctrl_ds0(&self) -> PadGpio05CtrlDs0R {
3073                PadGpio05CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
3074            }
3075            #[doc = "Bit 5 - Drive strength bit 1"]
3076            #[inline(always)]
3077            pub fn pad_gpio_05_ctrl_ds1(&self) -> PadGpio05CtrlDs1R {
3078                PadGpio05CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
3079            }
3080            #[doc = "Bit 6 - Drive strength bit 2"]
3081            #[inline(always)]
3082            pub fn pad_gpio_05_ctrl_ds2(&self) -> PadGpio05CtrlDs2R {
3083                PadGpio05CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
3084            }
3085            #[doc = "Bit 9 - Pull enable"]
3086            #[inline(always)]
3087            pub fn pad_gpio_05_ctrl_pe(&self) -> PadGpio05CtrlPeR {
3088                PadGpio05CtrlPeR::new(((self.bits >> 9) & 1) != 0)
3089            }
3090            #[doc = "Bit 10 - Pull select"]
3091            #[inline(always)]
3092            pub fn pad_gpio_05_ctrl_ps(&self) -> PadGpio05CtrlPsR {
3093                PadGpio05CtrlPsR::new(((self.bits >> 10) & 1) != 0)
3094            }
3095            #[doc = "Bit 11 - Input enable"]
3096            #[inline(always)]
3097            pub fn pad_gpio_05_ctrl_ie(&self) -> PadGpio05CtrlIeR {
3098                PadGpio05CtrlIeR::new(((self.bits >> 11) & 1) != 0)
3099            }
3100        }
3101        impl W {
3102            #[doc = "Bit 3 - Schmitt trigger"]
3103            #[inline(always)]
3104            pub fn pad_gpio_05_ctrl_st(&mut self) -> PadGpio05CtrlStW<'_, PadGpio05CtrlSpec> {
3105                PadGpio05CtrlStW::new(self, 3)
3106            }
3107            #[doc = "Bit 4 - Drive strength bit 0"]
3108            #[inline(always)]
3109            pub fn pad_gpio_05_ctrl_ds0(&mut self) -> PadGpio05CtrlDs0W<'_, PadGpio05CtrlSpec> {
3110                PadGpio05CtrlDs0W::new(self, 4)
3111            }
3112            #[doc = "Bit 5 - Drive strength bit 1"]
3113            #[inline(always)]
3114            pub fn pad_gpio_05_ctrl_ds1(&mut self) -> PadGpio05CtrlDs1W<'_, PadGpio05CtrlSpec> {
3115                PadGpio05CtrlDs1W::new(self, 5)
3116            }
3117            #[doc = "Bit 6 - Drive strength bit 2"]
3118            #[inline(always)]
3119            pub fn pad_gpio_05_ctrl_ds2(&mut self) -> PadGpio05CtrlDs2W<'_, PadGpio05CtrlSpec> {
3120                PadGpio05CtrlDs2W::new(self, 6)
3121            }
3122            #[doc = "Bit 9 - Pull enable"]
3123            #[inline(always)]
3124            pub fn pad_gpio_05_ctrl_pe(&mut self) -> PadGpio05CtrlPeW<'_, PadGpio05CtrlSpec> {
3125                PadGpio05CtrlPeW::new(self, 9)
3126            }
3127            #[doc = "Bit 10 - Pull select"]
3128            #[inline(always)]
3129            pub fn pad_gpio_05_ctrl_ps(&mut self) -> PadGpio05CtrlPsW<'_, PadGpio05CtrlSpec> {
3130                PadGpio05CtrlPsW::new(self, 10)
3131            }
3132            #[doc = "Bit 11 - Input enable"]
3133            #[inline(always)]
3134            pub fn pad_gpio_05_ctrl_ie(&mut self) -> PadGpio05CtrlIeW<'_, PadGpio05CtrlSpec> {
3135                PadGpio05CtrlIeW::new(self, 11)
3136            }
3137        }
3138        #[doc = "GPIO_05 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_05_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_05_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3139        pub struct PadGpio05CtrlSpec;
3140        impl crate::RegisterSpec for PadGpio05CtrlSpec {
3141            type Ux = u32;
3142        }
3143        #[doc = "`read()` method returns [`pad_gpio_05_ctrl::R`](R) reader structure"]
3144        impl crate::Readable for PadGpio05CtrlSpec {}
3145        #[doc = "`write(|w| ..)` method takes [`pad_gpio_05_ctrl::W`](W) writer structure"]
3146        impl crate::Writable for PadGpio05CtrlSpec {
3147            type Safety = crate::Unsafe;
3148        }
3149        #[doc = "`reset()` method sets PAD_GPIO_05_CTRL to value 0x0820"]
3150        impl crate::Resettable for PadGpio05CtrlSpec {
3151            const RESET_VALUE: u32 = 0x0820;
3152        }
3153    }
3154    #[doc = "PAD_GPIO_06_CTRL (rw) register accessor: GPIO_06 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_06_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_06_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_06_ctrl`] module"]
3155    #[doc(alias = "PAD_GPIO_06_CTRL")]
3156    pub type PadGpio06Ctrl = crate::Reg<pad_gpio_06_ctrl::PadGpio06CtrlSpec>;
3157    #[doc = "GPIO_06 pad control register"]
3158    pub mod pad_gpio_06_ctrl {
3159        #[doc = "Register `PAD_GPIO_06_CTRL` reader"]
3160        pub type R = crate::R<PadGpio06CtrlSpec>;
3161        #[doc = "Register `PAD_GPIO_06_CTRL` writer"]
3162        pub type W = crate::W<PadGpio06CtrlSpec>;
3163        #[doc = "Field `pad_gpio_06_ctrl_st` reader - Schmitt trigger"]
3164        pub type PadGpio06CtrlStR = crate::BitReader;
3165        #[doc = "Field `pad_gpio_06_ctrl_st` writer - Schmitt trigger"]
3166        pub type PadGpio06CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
3167        #[doc = "Field `pad_gpio_06_ctrl_ds0` reader - Drive strength bit 0"]
3168        pub type PadGpio06CtrlDs0R = crate::BitReader;
3169        #[doc = "Field `pad_gpio_06_ctrl_ds0` writer - Drive strength bit 0"]
3170        pub type PadGpio06CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
3171        #[doc = "Field `pad_gpio_06_ctrl_ds1` reader - Drive strength bit 1"]
3172        pub type PadGpio06CtrlDs1R = crate::BitReader;
3173        #[doc = "Field `pad_gpio_06_ctrl_ds1` writer - Drive strength bit 1"]
3174        pub type PadGpio06CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
3175        #[doc = "Field `pad_gpio_06_ctrl_ds2` reader - Drive strength bit 2"]
3176        pub type PadGpio06CtrlDs2R = crate::BitReader;
3177        #[doc = "Field `pad_gpio_06_ctrl_ds2` writer - Drive strength bit 2"]
3178        pub type PadGpio06CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
3179        #[doc = "Field `pad_gpio_06_ctrl_pe` reader - Pull enable"]
3180        pub type PadGpio06CtrlPeR = crate::BitReader;
3181        #[doc = "Field `pad_gpio_06_ctrl_pe` writer - Pull enable"]
3182        pub type PadGpio06CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
3183        #[doc = "Field `pad_gpio_06_ctrl_ps` reader - Pull select"]
3184        pub type PadGpio06CtrlPsR = crate::BitReader;
3185        #[doc = "Field `pad_gpio_06_ctrl_ps` writer - Pull select"]
3186        pub type PadGpio06CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
3187        #[doc = "Field `pad_gpio_06_ctrl_ie` reader - Input enable"]
3188        pub type PadGpio06CtrlIeR = crate::BitReader;
3189        #[doc = "Field `pad_gpio_06_ctrl_ie` writer - Input enable"]
3190        pub type PadGpio06CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
3191        impl R {
3192            #[doc = "Bit 3 - Schmitt trigger"]
3193            #[inline(always)]
3194            pub fn pad_gpio_06_ctrl_st(&self) -> PadGpio06CtrlStR {
3195                PadGpio06CtrlStR::new(((self.bits >> 3) & 1) != 0)
3196            }
3197            #[doc = "Bit 4 - Drive strength bit 0"]
3198            #[inline(always)]
3199            pub fn pad_gpio_06_ctrl_ds0(&self) -> PadGpio06CtrlDs0R {
3200                PadGpio06CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
3201            }
3202            #[doc = "Bit 5 - Drive strength bit 1"]
3203            #[inline(always)]
3204            pub fn pad_gpio_06_ctrl_ds1(&self) -> PadGpio06CtrlDs1R {
3205                PadGpio06CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
3206            }
3207            #[doc = "Bit 6 - Drive strength bit 2"]
3208            #[inline(always)]
3209            pub fn pad_gpio_06_ctrl_ds2(&self) -> PadGpio06CtrlDs2R {
3210                PadGpio06CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
3211            }
3212            #[doc = "Bit 9 - Pull enable"]
3213            #[inline(always)]
3214            pub fn pad_gpio_06_ctrl_pe(&self) -> PadGpio06CtrlPeR {
3215                PadGpio06CtrlPeR::new(((self.bits >> 9) & 1) != 0)
3216            }
3217            #[doc = "Bit 10 - Pull select"]
3218            #[inline(always)]
3219            pub fn pad_gpio_06_ctrl_ps(&self) -> PadGpio06CtrlPsR {
3220                PadGpio06CtrlPsR::new(((self.bits >> 10) & 1) != 0)
3221            }
3222            #[doc = "Bit 11 - Input enable"]
3223            #[inline(always)]
3224            pub fn pad_gpio_06_ctrl_ie(&self) -> PadGpio06CtrlIeR {
3225                PadGpio06CtrlIeR::new(((self.bits >> 11) & 1) != 0)
3226            }
3227        }
3228        impl W {
3229            #[doc = "Bit 3 - Schmitt trigger"]
3230            #[inline(always)]
3231            pub fn pad_gpio_06_ctrl_st(&mut self) -> PadGpio06CtrlStW<'_, PadGpio06CtrlSpec> {
3232                PadGpio06CtrlStW::new(self, 3)
3233            }
3234            #[doc = "Bit 4 - Drive strength bit 0"]
3235            #[inline(always)]
3236            pub fn pad_gpio_06_ctrl_ds0(&mut self) -> PadGpio06CtrlDs0W<'_, PadGpio06CtrlSpec> {
3237                PadGpio06CtrlDs0W::new(self, 4)
3238            }
3239            #[doc = "Bit 5 - Drive strength bit 1"]
3240            #[inline(always)]
3241            pub fn pad_gpio_06_ctrl_ds1(&mut self) -> PadGpio06CtrlDs1W<'_, PadGpio06CtrlSpec> {
3242                PadGpio06CtrlDs1W::new(self, 5)
3243            }
3244            #[doc = "Bit 6 - Drive strength bit 2"]
3245            #[inline(always)]
3246            pub fn pad_gpio_06_ctrl_ds2(&mut self) -> PadGpio06CtrlDs2W<'_, PadGpio06CtrlSpec> {
3247                PadGpio06CtrlDs2W::new(self, 6)
3248            }
3249            #[doc = "Bit 9 - Pull enable"]
3250            #[inline(always)]
3251            pub fn pad_gpio_06_ctrl_pe(&mut self) -> PadGpio06CtrlPeW<'_, PadGpio06CtrlSpec> {
3252                PadGpio06CtrlPeW::new(self, 9)
3253            }
3254            #[doc = "Bit 10 - Pull select"]
3255            #[inline(always)]
3256            pub fn pad_gpio_06_ctrl_ps(&mut self) -> PadGpio06CtrlPsW<'_, PadGpio06CtrlSpec> {
3257                PadGpio06CtrlPsW::new(self, 10)
3258            }
3259            #[doc = "Bit 11 - Input enable"]
3260            #[inline(always)]
3261            pub fn pad_gpio_06_ctrl_ie(&mut self) -> PadGpio06CtrlIeW<'_, PadGpio06CtrlSpec> {
3262                PadGpio06CtrlIeW::new(self, 11)
3263            }
3264        }
3265        #[doc = "GPIO_06 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_06_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_06_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3266        pub struct PadGpio06CtrlSpec;
3267        impl crate::RegisterSpec for PadGpio06CtrlSpec {
3268            type Ux = u32;
3269        }
3270        #[doc = "`read()` method returns [`pad_gpio_06_ctrl::R`](R) reader structure"]
3271        impl crate::Readable for PadGpio06CtrlSpec {}
3272        #[doc = "`write(|w| ..)` method takes [`pad_gpio_06_ctrl::W`](W) writer structure"]
3273        impl crate::Writable for PadGpio06CtrlSpec {
3274            type Safety = crate::Unsafe;
3275        }
3276        #[doc = "`reset()` method sets PAD_GPIO_06_CTRL to value 0x0a00"]
3277        impl crate::Resettable for PadGpio06CtrlSpec {
3278            const RESET_VALUE: u32 = 0x0a00;
3279        }
3280    }
3281    #[doc = "PAD_GPIO_07_CTRL (rw) register accessor: GPIO_07 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_07_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_07_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_07_ctrl`] module"]
3282    #[doc(alias = "PAD_GPIO_07_CTRL")]
3283    pub type PadGpio07Ctrl = crate::Reg<pad_gpio_07_ctrl::PadGpio07CtrlSpec>;
3284    #[doc = "GPIO_07 pad control register"]
3285    pub mod pad_gpio_07_ctrl {
3286        #[doc = "Register `PAD_GPIO_07_CTRL` reader"]
3287        pub type R = crate::R<PadGpio07CtrlSpec>;
3288        #[doc = "Register `PAD_GPIO_07_CTRL` writer"]
3289        pub type W = crate::W<PadGpio07CtrlSpec>;
3290        #[doc = "Field `pad_gpio_07_ctrl_st` reader - Schmitt trigger"]
3291        pub type PadGpio07CtrlStR = crate::BitReader;
3292        #[doc = "Field `pad_gpio_07_ctrl_st` writer - Schmitt trigger"]
3293        pub type PadGpio07CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
3294        #[doc = "Field `pad_gpio_07_ctrl_ds0` reader - Drive strength bit 0"]
3295        pub type PadGpio07CtrlDs0R = crate::BitReader;
3296        #[doc = "Field `pad_gpio_07_ctrl_ds0` writer - Drive strength bit 0"]
3297        pub type PadGpio07CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
3298        #[doc = "Field `pad_gpio_07_ctrl_ds1` reader - Drive strength bit 1"]
3299        pub type PadGpio07CtrlDs1R = crate::BitReader;
3300        #[doc = "Field `pad_gpio_07_ctrl_ds1` writer - Drive strength bit 1"]
3301        pub type PadGpio07CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
3302        #[doc = "Field `pad_gpio_07_ctrl_ds2` reader - Drive strength bit 2"]
3303        pub type PadGpio07CtrlDs2R = crate::BitReader;
3304        #[doc = "Field `pad_gpio_07_ctrl_ds2` writer - Drive strength bit 2"]
3305        pub type PadGpio07CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
3306        #[doc = "Field `pad_gpio_07_ctrl_pe` reader - Pull enable"]
3307        pub type PadGpio07CtrlPeR = crate::BitReader;
3308        #[doc = "Field `pad_gpio_07_ctrl_pe` writer - Pull enable"]
3309        pub type PadGpio07CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
3310        #[doc = "Field `pad_gpio_07_ctrl_ps` reader - Pull select"]
3311        pub type PadGpio07CtrlPsR = crate::BitReader;
3312        #[doc = "Field `pad_gpio_07_ctrl_ps` writer - Pull select"]
3313        pub type PadGpio07CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
3314        #[doc = "Field `pad_gpio_07_ctrl_ie` reader - Input enable"]
3315        pub type PadGpio07CtrlIeR = crate::BitReader;
3316        #[doc = "Field `pad_gpio_07_ctrl_ie` writer - Input enable"]
3317        pub type PadGpio07CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
3318        impl R {
3319            #[doc = "Bit 3 - Schmitt trigger"]
3320            #[inline(always)]
3321            pub fn pad_gpio_07_ctrl_st(&self) -> PadGpio07CtrlStR {
3322                PadGpio07CtrlStR::new(((self.bits >> 3) & 1) != 0)
3323            }
3324            #[doc = "Bit 4 - Drive strength bit 0"]
3325            #[inline(always)]
3326            pub fn pad_gpio_07_ctrl_ds0(&self) -> PadGpio07CtrlDs0R {
3327                PadGpio07CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
3328            }
3329            #[doc = "Bit 5 - Drive strength bit 1"]
3330            #[inline(always)]
3331            pub fn pad_gpio_07_ctrl_ds1(&self) -> PadGpio07CtrlDs1R {
3332                PadGpio07CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
3333            }
3334            #[doc = "Bit 6 - Drive strength bit 2"]
3335            #[inline(always)]
3336            pub fn pad_gpio_07_ctrl_ds2(&self) -> PadGpio07CtrlDs2R {
3337                PadGpio07CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
3338            }
3339            #[doc = "Bit 9 - Pull enable"]
3340            #[inline(always)]
3341            pub fn pad_gpio_07_ctrl_pe(&self) -> PadGpio07CtrlPeR {
3342                PadGpio07CtrlPeR::new(((self.bits >> 9) & 1) != 0)
3343            }
3344            #[doc = "Bit 10 - Pull select"]
3345            #[inline(always)]
3346            pub fn pad_gpio_07_ctrl_ps(&self) -> PadGpio07CtrlPsR {
3347                PadGpio07CtrlPsR::new(((self.bits >> 10) & 1) != 0)
3348            }
3349            #[doc = "Bit 11 - Input enable"]
3350            #[inline(always)]
3351            pub fn pad_gpio_07_ctrl_ie(&self) -> PadGpio07CtrlIeR {
3352                PadGpio07CtrlIeR::new(((self.bits >> 11) & 1) != 0)
3353            }
3354        }
3355        impl W {
3356            #[doc = "Bit 3 - Schmitt trigger"]
3357            #[inline(always)]
3358            pub fn pad_gpio_07_ctrl_st(&mut self) -> PadGpio07CtrlStW<'_, PadGpio07CtrlSpec> {
3359                PadGpio07CtrlStW::new(self, 3)
3360            }
3361            #[doc = "Bit 4 - Drive strength bit 0"]
3362            #[inline(always)]
3363            pub fn pad_gpio_07_ctrl_ds0(&mut self) -> PadGpio07CtrlDs0W<'_, PadGpio07CtrlSpec> {
3364                PadGpio07CtrlDs0W::new(self, 4)
3365            }
3366            #[doc = "Bit 5 - Drive strength bit 1"]
3367            #[inline(always)]
3368            pub fn pad_gpio_07_ctrl_ds1(&mut self) -> PadGpio07CtrlDs1W<'_, PadGpio07CtrlSpec> {
3369                PadGpio07CtrlDs1W::new(self, 5)
3370            }
3371            #[doc = "Bit 6 - Drive strength bit 2"]
3372            #[inline(always)]
3373            pub fn pad_gpio_07_ctrl_ds2(&mut self) -> PadGpio07CtrlDs2W<'_, PadGpio07CtrlSpec> {
3374                PadGpio07CtrlDs2W::new(self, 6)
3375            }
3376            #[doc = "Bit 9 - Pull enable"]
3377            #[inline(always)]
3378            pub fn pad_gpio_07_ctrl_pe(&mut self) -> PadGpio07CtrlPeW<'_, PadGpio07CtrlSpec> {
3379                PadGpio07CtrlPeW::new(self, 9)
3380            }
3381            #[doc = "Bit 10 - Pull select"]
3382            #[inline(always)]
3383            pub fn pad_gpio_07_ctrl_ps(&mut self) -> PadGpio07CtrlPsW<'_, PadGpio07CtrlSpec> {
3384                PadGpio07CtrlPsW::new(self, 10)
3385            }
3386            #[doc = "Bit 11 - Input enable"]
3387            #[inline(always)]
3388            pub fn pad_gpio_07_ctrl_ie(&mut self) -> PadGpio07CtrlIeW<'_, PadGpio07CtrlSpec> {
3389                PadGpio07CtrlIeW::new(self, 11)
3390            }
3391        }
3392        #[doc = "GPIO_07 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_07_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_07_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3393        pub struct PadGpio07CtrlSpec;
3394        impl crate::RegisterSpec for PadGpio07CtrlSpec {
3395            type Ux = u32;
3396        }
3397        #[doc = "`read()` method returns [`pad_gpio_07_ctrl::R`](R) reader structure"]
3398        impl crate::Readable for PadGpio07CtrlSpec {}
3399        #[doc = "`write(|w| ..)` method takes [`pad_gpio_07_ctrl::W`](W) writer structure"]
3400        impl crate::Writable for PadGpio07CtrlSpec {
3401            type Safety = crate::Unsafe;
3402        }
3403        #[doc = "`reset()` method sets PAD_GPIO_07_CTRL to value 0x0800"]
3404        impl crate::Resettable for PadGpio07CtrlSpec {
3405            const RESET_VALUE: u32 = 0x0800;
3406        }
3407    }
3408    #[doc = "PAD_GPIO_08_CTRL (rw) register accessor: GPIO_08 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_08_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_08_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_08_ctrl`] module"]
3409    #[doc(alias = "PAD_GPIO_08_CTRL")]
3410    pub type PadGpio08Ctrl = crate::Reg<pad_gpio_08_ctrl::PadGpio08CtrlSpec>;
3411    #[doc = "GPIO_08 pad control register"]
3412    pub mod pad_gpio_08_ctrl {
3413        #[doc = "Register `PAD_GPIO_08_CTRL` reader"]
3414        pub type R = crate::R<PadGpio08CtrlSpec>;
3415        #[doc = "Register `PAD_GPIO_08_CTRL` writer"]
3416        pub type W = crate::W<PadGpio08CtrlSpec>;
3417        #[doc = "Field `pad_gpio_08_ctrl_st` reader - Schmitt trigger"]
3418        pub type PadGpio08CtrlStR = crate::BitReader;
3419        #[doc = "Field `pad_gpio_08_ctrl_st` writer - Schmitt trigger"]
3420        pub type PadGpio08CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
3421        #[doc = "Field `pad_gpio_08_ctrl_ds0` reader - Drive strength bit 0"]
3422        pub type PadGpio08CtrlDs0R = crate::BitReader;
3423        #[doc = "Field `pad_gpio_08_ctrl_ds0` writer - Drive strength bit 0"]
3424        pub type PadGpio08CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
3425        #[doc = "Field `pad_gpio_08_ctrl_ds1` reader - Drive strength bit 1"]
3426        pub type PadGpio08CtrlDs1R = crate::BitReader;
3427        #[doc = "Field `pad_gpio_08_ctrl_ds1` writer - Drive strength bit 1"]
3428        pub type PadGpio08CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
3429        #[doc = "Field `pad_gpio_08_ctrl_ds2` reader - Drive strength bit 2"]
3430        pub type PadGpio08CtrlDs2R = crate::BitReader;
3431        #[doc = "Field `pad_gpio_08_ctrl_ds2` writer - Drive strength bit 2"]
3432        pub type PadGpio08CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
3433        #[doc = "Field `pad_gpio_08_ctrl_pe` reader - Pull enable"]
3434        pub type PadGpio08CtrlPeR = crate::BitReader;
3435        #[doc = "Field `pad_gpio_08_ctrl_pe` writer - Pull enable"]
3436        pub type PadGpio08CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
3437        #[doc = "Field `pad_gpio_08_ctrl_ps` reader - Pull select"]
3438        pub type PadGpio08CtrlPsR = crate::BitReader;
3439        #[doc = "Field `pad_gpio_08_ctrl_ps` writer - Pull select"]
3440        pub type PadGpio08CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
3441        #[doc = "Field `pad_gpio_08_ctrl_ie` reader - Input enable"]
3442        pub type PadGpio08CtrlIeR = crate::BitReader;
3443        #[doc = "Field `pad_gpio_08_ctrl_ie` writer - Input enable"]
3444        pub type PadGpio08CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
3445        impl R {
3446            #[doc = "Bit 3 - Schmitt trigger"]
3447            #[inline(always)]
3448            pub fn pad_gpio_08_ctrl_st(&self) -> PadGpio08CtrlStR {
3449                PadGpio08CtrlStR::new(((self.bits >> 3) & 1) != 0)
3450            }
3451            #[doc = "Bit 4 - Drive strength bit 0"]
3452            #[inline(always)]
3453            pub fn pad_gpio_08_ctrl_ds0(&self) -> PadGpio08CtrlDs0R {
3454                PadGpio08CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
3455            }
3456            #[doc = "Bit 5 - Drive strength bit 1"]
3457            #[inline(always)]
3458            pub fn pad_gpio_08_ctrl_ds1(&self) -> PadGpio08CtrlDs1R {
3459                PadGpio08CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
3460            }
3461            #[doc = "Bit 6 - Drive strength bit 2"]
3462            #[inline(always)]
3463            pub fn pad_gpio_08_ctrl_ds2(&self) -> PadGpio08CtrlDs2R {
3464                PadGpio08CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
3465            }
3466            #[doc = "Bit 9 - Pull enable"]
3467            #[inline(always)]
3468            pub fn pad_gpio_08_ctrl_pe(&self) -> PadGpio08CtrlPeR {
3469                PadGpio08CtrlPeR::new(((self.bits >> 9) & 1) != 0)
3470            }
3471            #[doc = "Bit 10 - Pull select"]
3472            #[inline(always)]
3473            pub fn pad_gpio_08_ctrl_ps(&self) -> PadGpio08CtrlPsR {
3474                PadGpio08CtrlPsR::new(((self.bits >> 10) & 1) != 0)
3475            }
3476            #[doc = "Bit 11 - Input enable"]
3477            #[inline(always)]
3478            pub fn pad_gpio_08_ctrl_ie(&self) -> PadGpio08CtrlIeR {
3479                PadGpio08CtrlIeR::new(((self.bits >> 11) & 1) != 0)
3480            }
3481        }
3482        impl W {
3483            #[doc = "Bit 3 - Schmitt trigger"]
3484            #[inline(always)]
3485            pub fn pad_gpio_08_ctrl_st(&mut self) -> PadGpio08CtrlStW<'_, PadGpio08CtrlSpec> {
3486                PadGpio08CtrlStW::new(self, 3)
3487            }
3488            #[doc = "Bit 4 - Drive strength bit 0"]
3489            #[inline(always)]
3490            pub fn pad_gpio_08_ctrl_ds0(&mut self) -> PadGpio08CtrlDs0W<'_, PadGpio08CtrlSpec> {
3491                PadGpio08CtrlDs0W::new(self, 4)
3492            }
3493            #[doc = "Bit 5 - Drive strength bit 1"]
3494            #[inline(always)]
3495            pub fn pad_gpio_08_ctrl_ds1(&mut self) -> PadGpio08CtrlDs1W<'_, PadGpio08CtrlSpec> {
3496                PadGpio08CtrlDs1W::new(self, 5)
3497            }
3498            #[doc = "Bit 6 - Drive strength bit 2"]
3499            #[inline(always)]
3500            pub fn pad_gpio_08_ctrl_ds2(&mut self) -> PadGpio08CtrlDs2W<'_, PadGpio08CtrlSpec> {
3501                PadGpio08CtrlDs2W::new(self, 6)
3502            }
3503            #[doc = "Bit 9 - Pull enable"]
3504            #[inline(always)]
3505            pub fn pad_gpio_08_ctrl_pe(&mut self) -> PadGpio08CtrlPeW<'_, PadGpio08CtrlSpec> {
3506                PadGpio08CtrlPeW::new(self, 9)
3507            }
3508            #[doc = "Bit 10 - Pull select"]
3509            #[inline(always)]
3510            pub fn pad_gpio_08_ctrl_ps(&mut self) -> PadGpio08CtrlPsW<'_, PadGpio08CtrlSpec> {
3511                PadGpio08CtrlPsW::new(self, 10)
3512            }
3513            #[doc = "Bit 11 - Input enable"]
3514            #[inline(always)]
3515            pub fn pad_gpio_08_ctrl_ie(&mut self) -> PadGpio08CtrlIeW<'_, PadGpio08CtrlSpec> {
3516                PadGpio08CtrlIeW::new(self, 11)
3517            }
3518        }
3519        #[doc = "GPIO_08 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_08_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_08_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3520        pub struct PadGpio08CtrlSpec;
3521        impl crate::RegisterSpec for PadGpio08CtrlSpec {
3522            type Ux = u32;
3523        }
3524        #[doc = "`read()` method returns [`pad_gpio_08_ctrl::R`](R) reader structure"]
3525        impl crate::Readable for PadGpio08CtrlSpec {}
3526        #[doc = "`write(|w| ..)` method takes [`pad_gpio_08_ctrl::W`](W) writer structure"]
3527        impl crate::Writable for PadGpio08CtrlSpec {
3528            type Safety = crate::Unsafe;
3529        }
3530        #[doc = "`reset()` method sets PAD_GPIO_08_CTRL to value 0x0800"]
3531        impl crate::Resettable for PadGpio08CtrlSpec {
3532            const RESET_VALUE: u32 = 0x0800;
3533        }
3534    }
3535    #[doc = "PAD_GPIO_09_CTRL (rw) register accessor: GPIO_09 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_09_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_09_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_09_ctrl`] module"]
3536    #[doc(alias = "PAD_GPIO_09_CTRL")]
3537    pub type PadGpio09Ctrl = crate::Reg<pad_gpio_09_ctrl::PadGpio09CtrlSpec>;
3538    #[doc = "GPIO_09 pad control register"]
3539    pub mod pad_gpio_09_ctrl {
3540        #[doc = "Register `PAD_GPIO_09_CTRL` reader"]
3541        pub type R = crate::R<PadGpio09CtrlSpec>;
3542        #[doc = "Register `PAD_GPIO_09_CTRL` writer"]
3543        pub type W = crate::W<PadGpio09CtrlSpec>;
3544        #[doc = "Field `pad_gpio_09_ctrl_st` reader - Schmitt trigger"]
3545        pub type PadGpio09CtrlStR = crate::BitReader;
3546        #[doc = "Field `pad_gpio_09_ctrl_st` writer - Schmitt trigger"]
3547        pub type PadGpio09CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
3548        #[doc = "Field `pad_gpio_09_ctrl_ds0` reader - Drive strength bit 0"]
3549        pub type PadGpio09CtrlDs0R = crate::BitReader;
3550        #[doc = "Field `pad_gpio_09_ctrl_ds0` writer - Drive strength bit 0"]
3551        pub type PadGpio09CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
3552        #[doc = "Field `pad_gpio_09_ctrl_ds1` reader - Drive strength bit 1"]
3553        pub type PadGpio09CtrlDs1R = crate::BitReader;
3554        #[doc = "Field `pad_gpio_09_ctrl_ds1` writer - Drive strength bit 1"]
3555        pub type PadGpio09CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
3556        #[doc = "Field `pad_gpio_09_ctrl_ds2` reader - Drive strength bit 2"]
3557        pub type PadGpio09CtrlDs2R = crate::BitReader;
3558        #[doc = "Field `pad_gpio_09_ctrl_ds2` writer - Drive strength bit 2"]
3559        pub type PadGpio09CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
3560        #[doc = "Field `pad_gpio_09_ctrl_pe` reader - Pull enable"]
3561        pub type PadGpio09CtrlPeR = crate::BitReader;
3562        #[doc = "Field `pad_gpio_09_ctrl_pe` writer - Pull enable"]
3563        pub type PadGpio09CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
3564        #[doc = "Field `pad_gpio_09_ctrl_ps` reader - Pull select"]
3565        pub type PadGpio09CtrlPsR = crate::BitReader;
3566        #[doc = "Field `pad_gpio_09_ctrl_ps` writer - Pull select"]
3567        pub type PadGpio09CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
3568        #[doc = "Field `pad_gpio_09_ctrl_ie` reader - Input enable"]
3569        pub type PadGpio09CtrlIeR = crate::BitReader;
3570        #[doc = "Field `pad_gpio_09_ctrl_ie` writer - Input enable"]
3571        pub type PadGpio09CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
3572        impl R {
3573            #[doc = "Bit 3 - Schmitt trigger"]
3574            #[inline(always)]
3575            pub fn pad_gpio_09_ctrl_st(&self) -> PadGpio09CtrlStR {
3576                PadGpio09CtrlStR::new(((self.bits >> 3) & 1) != 0)
3577            }
3578            #[doc = "Bit 4 - Drive strength bit 0"]
3579            #[inline(always)]
3580            pub fn pad_gpio_09_ctrl_ds0(&self) -> PadGpio09CtrlDs0R {
3581                PadGpio09CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
3582            }
3583            #[doc = "Bit 5 - Drive strength bit 1"]
3584            #[inline(always)]
3585            pub fn pad_gpio_09_ctrl_ds1(&self) -> PadGpio09CtrlDs1R {
3586                PadGpio09CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
3587            }
3588            #[doc = "Bit 6 - Drive strength bit 2"]
3589            #[inline(always)]
3590            pub fn pad_gpio_09_ctrl_ds2(&self) -> PadGpio09CtrlDs2R {
3591                PadGpio09CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
3592            }
3593            #[doc = "Bit 9 - Pull enable"]
3594            #[inline(always)]
3595            pub fn pad_gpio_09_ctrl_pe(&self) -> PadGpio09CtrlPeR {
3596                PadGpio09CtrlPeR::new(((self.bits >> 9) & 1) != 0)
3597            }
3598            #[doc = "Bit 10 - Pull select"]
3599            #[inline(always)]
3600            pub fn pad_gpio_09_ctrl_ps(&self) -> PadGpio09CtrlPsR {
3601                PadGpio09CtrlPsR::new(((self.bits >> 10) & 1) != 0)
3602            }
3603            #[doc = "Bit 11 - Input enable"]
3604            #[inline(always)]
3605            pub fn pad_gpio_09_ctrl_ie(&self) -> PadGpio09CtrlIeR {
3606                PadGpio09CtrlIeR::new(((self.bits >> 11) & 1) != 0)
3607            }
3608        }
3609        impl W {
3610            #[doc = "Bit 3 - Schmitt trigger"]
3611            #[inline(always)]
3612            pub fn pad_gpio_09_ctrl_st(&mut self) -> PadGpio09CtrlStW<'_, PadGpio09CtrlSpec> {
3613                PadGpio09CtrlStW::new(self, 3)
3614            }
3615            #[doc = "Bit 4 - Drive strength bit 0"]
3616            #[inline(always)]
3617            pub fn pad_gpio_09_ctrl_ds0(&mut self) -> PadGpio09CtrlDs0W<'_, PadGpio09CtrlSpec> {
3618                PadGpio09CtrlDs0W::new(self, 4)
3619            }
3620            #[doc = "Bit 5 - Drive strength bit 1"]
3621            #[inline(always)]
3622            pub fn pad_gpio_09_ctrl_ds1(&mut self) -> PadGpio09CtrlDs1W<'_, PadGpio09CtrlSpec> {
3623                PadGpio09CtrlDs1W::new(self, 5)
3624            }
3625            #[doc = "Bit 6 - Drive strength bit 2"]
3626            #[inline(always)]
3627            pub fn pad_gpio_09_ctrl_ds2(&mut self) -> PadGpio09CtrlDs2W<'_, PadGpio09CtrlSpec> {
3628                PadGpio09CtrlDs2W::new(self, 6)
3629            }
3630            #[doc = "Bit 9 - Pull enable"]
3631            #[inline(always)]
3632            pub fn pad_gpio_09_ctrl_pe(&mut self) -> PadGpio09CtrlPeW<'_, PadGpio09CtrlSpec> {
3633                PadGpio09CtrlPeW::new(self, 9)
3634            }
3635            #[doc = "Bit 10 - Pull select"]
3636            #[inline(always)]
3637            pub fn pad_gpio_09_ctrl_ps(&mut self) -> PadGpio09CtrlPsW<'_, PadGpio09CtrlSpec> {
3638                PadGpio09CtrlPsW::new(self, 10)
3639            }
3640            #[doc = "Bit 11 - Input enable"]
3641            #[inline(always)]
3642            pub fn pad_gpio_09_ctrl_ie(&mut self) -> PadGpio09CtrlIeW<'_, PadGpio09CtrlSpec> {
3643                PadGpio09CtrlIeW::new(self, 11)
3644            }
3645        }
3646        #[doc = "GPIO_09 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_09_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_09_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3647        pub struct PadGpio09CtrlSpec;
3648        impl crate::RegisterSpec for PadGpio09CtrlSpec {
3649            type Ux = u32;
3650        }
3651        #[doc = "`read()` method returns [`pad_gpio_09_ctrl::R`](R) reader structure"]
3652        impl crate::Readable for PadGpio09CtrlSpec {}
3653        #[doc = "`write(|w| ..)` method takes [`pad_gpio_09_ctrl::W`](W) writer structure"]
3654        impl crate::Writable for PadGpio09CtrlSpec {
3655            type Safety = crate::Unsafe;
3656        }
3657        #[doc = "`reset()` method sets PAD_GPIO_09_CTRL to value 0x0a00"]
3658        impl crate::Resettable for PadGpio09CtrlSpec {
3659            const RESET_VALUE: u32 = 0x0a00;
3660        }
3661    }
3662    #[doc = "PAD_GPIO_10_CTRL (rw) register accessor: GPIO_10 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_10_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_10_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_10_ctrl`] module"]
3663    #[doc(alias = "PAD_GPIO_10_CTRL")]
3664    pub type PadGpio10Ctrl = crate::Reg<pad_gpio_10_ctrl::PadGpio10CtrlSpec>;
3665    #[doc = "GPIO_10 pad control register"]
3666    pub mod pad_gpio_10_ctrl {
3667        #[doc = "Register `PAD_GPIO_10_CTRL` reader"]
3668        pub type R = crate::R<PadGpio10CtrlSpec>;
3669        #[doc = "Register `PAD_GPIO_10_CTRL` writer"]
3670        pub type W = crate::W<PadGpio10CtrlSpec>;
3671        #[doc = "Field `pad_gpio_10_ctrl_st` reader - Schmitt trigger"]
3672        pub type PadGpio10CtrlStR = crate::BitReader;
3673        #[doc = "Field `pad_gpio_10_ctrl_st` writer - Schmitt trigger"]
3674        pub type PadGpio10CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
3675        #[doc = "Field `pad_gpio_10_ctrl_ds0` reader - Drive strength bit 0"]
3676        pub type PadGpio10CtrlDs0R = crate::BitReader;
3677        #[doc = "Field `pad_gpio_10_ctrl_ds0` writer - Drive strength bit 0"]
3678        pub type PadGpio10CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
3679        #[doc = "Field `pad_gpio_10_ctrl_ds1` reader - Drive strength bit 1"]
3680        pub type PadGpio10CtrlDs1R = crate::BitReader;
3681        #[doc = "Field `pad_gpio_10_ctrl_ds1` writer - Drive strength bit 1"]
3682        pub type PadGpio10CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
3683        #[doc = "Field `pad_gpio_10_ctrl_ds2` reader - Drive strength bit 2"]
3684        pub type PadGpio10CtrlDs2R = crate::BitReader;
3685        #[doc = "Field `pad_gpio_10_ctrl_ds2` writer - Drive strength bit 2"]
3686        pub type PadGpio10CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
3687        #[doc = "Field `pad_gpio_10_ctrl_pe` reader - Pull enable"]
3688        pub type PadGpio10CtrlPeR = crate::BitReader;
3689        #[doc = "Field `pad_gpio_10_ctrl_pe` writer - Pull enable"]
3690        pub type PadGpio10CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
3691        #[doc = "Field `pad_gpio_10_ctrl_ps` reader - Pull select"]
3692        pub type PadGpio10CtrlPsR = crate::BitReader;
3693        #[doc = "Field `pad_gpio_10_ctrl_ps` writer - Pull select"]
3694        pub type PadGpio10CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
3695        #[doc = "Field `pad_gpio_10_ctrl_ie` reader - Input enable"]
3696        pub type PadGpio10CtrlIeR = crate::BitReader;
3697        #[doc = "Field `pad_gpio_10_ctrl_ie` writer - Input enable"]
3698        pub type PadGpio10CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
3699        impl R {
3700            #[doc = "Bit 3 - Schmitt trigger"]
3701            #[inline(always)]
3702            pub fn pad_gpio_10_ctrl_st(&self) -> PadGpio10CtrlStR {
3703                PadGpio10CtrlStR::new(((self.bits >> 3) & 1) != 0)
3704            }
3705            #[doc = "Bit 4 - Drive strength bit 0"]
3706            #[inline(always)]
3707            pub fn pad_gpio_10_ctrl_ds0(&self) -> PadGpio10CtrlDs0R {
3708                PadGpio10CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
3709            }
3710            #[doc = "Bit 5 - Drive strength bit 1"]
3711            #[inline(always)]
3712            pub fn pad_gpio_10_ctrl_ds1(&self) -> PadGpio10CtrlDs1R {
3713                PadGpio10CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
3714            }
3715            #[doc = "Bit 6 - Drive strength bit 2"]
3716            #[inline(always)]
3717            pub fn pad_gpio_10_ctrl_ds2(&self) -> PadGpio10CtrlDs2R {
3718                PadGpio10CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
3719            }
3720            #[doc = "Bit 9 - Pull enable"]
3721            #[inline(always)]
3722            pub fn pad_gpio_10_ctrl_pe(&self) -> PadGpio10CtrlPeR {
3723                PadGpio10CtrlPeR::new(((self.bits >> 9) & 1) != 0)
3724            }
3725            #[doc = "Bit 10 - Pull select"]
3726            #[inline(always)]
3727            pub fn pad_gpio_10_ctrl_ps(&self) -> PadGpio10CtrlPsR {
3728                PadGpio10CtrlPsR::new(((self.bits >> 10) & 1) != 0)
3729            }
3730            #[doc = "Bit 11 - Input enable"]
3731            #[inline(always)]
3732            pub fn pad_gpio_10_ctrl_ie(&self) -> PadGpio10CtrlIeR {
3733                PadGpio10CtrlIeR::new(((self.bits >> 11) & 1) != 0)
3734            }
3735        }
3736        impl W {
3737            #[doc = "Bit 3 - Schmitt trigger"]
3738            #[inline(always)]
3739            pub fn pad_gpio_10_ctrl_st(&mut self) -> PadGpio10CtrlStW<'_, PadGpio10CtrlSpec> {
3740                PadGpio10CtrlStW::new(self, 3)
3741            }
3742            #[doc = "Bit 4 - Drive strength bit 0"]
3743            #[inline(always)]
3744            pub fn pad_gpio_10_ctrl_ds0(&mut self) -> PadGpio10CtrlDs0W<'_, PadGpio10CtrlSpec> {
3745                PadGpio10CtrlDs0W::new(self, 4)
3746            }
3747            #[doc = "Bit 5 - Drive strength bit 1"]
3748            #[inline(always)]
3749            pub fn pad_gpio_10_ctrl_ds1(&mut self) -> PadGpio10CtrlDs1W<'_, PadGpio10CtrlSpec> {
3750                PadGpio10CtrlDs1W::new(self, 5)
3751            }
3752            #[doc = "Bit 6 - Drive strength bit 2"]
3753            #[inline(always)]
3754            pub fn pad_gpio_10_ctrl_ds2(&mut self) -> PadGpio10CtrlDs2W<'_, PadGpio10CtrlSpec> {
3755                PadGpio10CtrlDs2W::new(self, 6)
3756            }
3757            #[doc = "Bit 9 - Pull enable"]
3758            #[inline(always)]
3759            pub fn pad_gpio_10_ctrl_pe(&mut self) -> PadGpio10CtrlPeW<'_, PadGpio10CtrlSpec> {
3760                PadGpio10CtrlPeW::new(self, 9)
3761            }
3762            #[doc = "Bit 10 - Pull select"]
3763            #[inline(always)]
3764            pub fn pad_gpio_10_ctrl_ps(&mut self) -> PadGpio10CtrlPsW<'_, PadGpio10CtrlSpec> {
3765                PadGpio10CtrlPsW::new(self, 10)
3766            }
3767            #[doc = "Bit 11 - Input enable"]
3768            #[inline(always)]
3769            pub fn pad_gpio_10_ctrl_ie(&mut self) -> PadGpio10CtrlIeW<'_, PadGpio10CtrlSpec> {
3770                PadGpio10CtrlIeW::new(self, 11)
3771            }
3772        }
3773        #[doc = "GPIO_10 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_10_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_10_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3774        pub struct PadGpio10CtrlSpec;
3775        impl crate::RegisterSpec for PadGpio10CtrlSpec {
3776            type Ux = u32;
3777        }
3778        #[doc = "`read()` method returns [`pad_gpio_10_ctrl::R`](R) reader structure"]
3779        impl crate::Readable for PadGpio10CtrlSpec {}
3780        #[doc = "`write(|w| ..)` method takes [`pad_gpio_10_ctrl::W`](W) writer structure"]
3781        impl crate::Writable for PadGpio10CtrlSpec {
3782            type Safety = crate::Unsafe;
3783        }
3784        #[doc = "`reset()` method sets PAD_GPIO_10_CTRL to value 0x0800"]
3785        impl crate::Resettable for PadGpio10CtrlSpec {
3786            const RESET_VALUE: u32 = 0x0800;
3787        }
3788    }
3789    #[doc = "PAD_GPIO_11_CTRL (rw) register accessor: GPIO_11 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_11_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_11_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_11_ctrl`] module"]
3790    #[doc(alias = "PAD_GPIO_11_CTRL")]
3791    pub type PadGpio11Ctrl = crate::Reg<pad_gpio_11_ctrl::PadGpio11CtrlSpec>;
3792    #[doc = "GPIO_11 pad control register"]
3793    pub mod pad_gpio_11_ctrl {
3794        #[doc = "Register `PAD_GPIO_11_CTRL` reader"]
3795        pub type R = crate::R<PadGpio11CtrlSpec>;
3796        #[doc = "Register `PAD_GPIO_11_CTRL` writer"]
3797        pub type W = crate::W<PadGpio11CtrlSpec>;
3798        #[doc = "Field `pad_gpio_11_ctrl_st` reader - Schmitt trigger"]
3799        pub type PadGpio11CtrlStR = crate::BitReader;
3800        #[doc = "Field `pad_gpio_11_ctrl_st` writer - Schmitt trigger"]
3801        pub type PadGpio11CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
3802        #[doc = "Field `pad_gpio_11_ctrl_ds0` reader - Drive strength bit 0"]
3803        pub type PadGpio11CtrlDs0R = crate::BitReader;
3804        #[doc = "Field `pad_gpio_11_ctrl_ds0` writer - Drive strength bit 0"]
3805        pub type PadGpio11CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
3806        #[doc = "Field `pad_gpio_11_ctrl_ds1` reader - Drive strength bit 1"]
3807        pub type PadGpio11CtrlDs1R = crate::BitReader;
3808        #[doc = "Field `pad_gpio_11_ctrl_ds1` writer - Drive strength bit 1"]
3809        pub type PadGpio11CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
3810        #[doc = "Field `pad_gpio_11_ctrl_ds2` reader - Drive strength bit 2"]
3811        pub type PadGpio11CtrlDs2R = crate::BitReader;
3812        #[doc = "Field `pad_gpio_11_ctrl_ds2` writer - Drive strength bit 2"]
3813        pub type PadGpio11CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
3814        #[doc = "Field `pad_gpio_11_ctrl_pe` reader - Pull enable"]
3815        pub type PadGpio11CtrlPeR = crate::BitReader;
3816        #[doc = "Field `pad_gpio_11_ctrl_pe` writer - Pull enable"]
3817        pub type PadGpio11CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
3818        #[doc = "Field `pad_gpio_11_ctrl_ps` reader - Pull select"]
3819        pub type PadGpio11CtrlPsR = crate::BitReader;
3820        #[doc = "Field `pad_gpio_11_ctrl_ps` writer - Pull select"]
3821        pub type PadGpio11CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
3822        #[doc = "Field `pad_gpio_11_ctrl_ie` reader - Input enable"]
3823        pub type PadGpio11CtrlIeR = crate::BitReader;
3824        #[doc = "Field `pad_gpio_11_ctrl_ie` writer - Input enable"]
3825        pub type PadGpio11CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
3826        impl R {
3827            #[doc = "Bit 3 - Schmitt trigger"]
3828            #[inline(always)]
3829            pub fn pad_gpio_11_ctrl_st(&self) -> PadGpio11CtrlStR {
3830                PadGpio11CtrlStR::new(((self.bits >> 3) & 1) != 0)
3831            }
3832            #[doc = "Bit 4 - Drive strength bit 0"]
3833            #[inline(always)]
3834            pub fn pad_gpio_11_ctrl_ds0(&self) -> PadGpio11CtrlDs0R {
3835                PadGpio11CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
3836            }
3837            #[doc = "Bit 5 - Drive strength bit 1"]
3838            #[inline(always)]
3839            pub fn pad_gpio_11_ctrl_ds1(&self) -> PadGpio11CtrlDs1R {
3840                PadGpio11CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
3841            }
3842            #[doc = "Bit 6 - Drive strength bit 2"]
3843            #[inline(always)]
3844            pub fn pad_gpio_11_ctrl_ds2(&self) -> PadGpio11CtrlDs2R {
3845                PadGpio11CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
3846            }
3847            #[doc = "Bit 9 - Pull enable"]
3848            #[inline(always)]
3849            pub fn pad_gpio_11_ctrl_pe(&self) -> PadGpio11CtrlPeR {
3850                PadGpio11CtrlPeR::new(((self.bits >> 9) & 1) != 0)
3851            }
3852            #[doc = "Bit 10 - Pull select"]
3853            #[inline(always)]
3854            pub fn pad_gpio_11_ctrl_ps(&self) -> PadGpio11CtrlPsR {
3855                PadGpio11CtrlPsR::new(((self.bits >> 10) & 1) != 0)
3856            }
3857            #[doc = "Bit 11 - Input enable"]
3858            #[inline(always)]
3859            pub fn pad_gpio_11_ctrl_ie(&self) -> PadGpio11CtrlIeR {
3860                PadGpio11CtrlIeR::new(((self.bits >> 11) & 1) != 0)
3861            }
3862        }
3863        impl W {
3864            #[doc = "Bit 3 - Schmitt trigger"]
3865            #[inline(always)]
3866            pub fn pad_gpio_11_ctrl_st(&mut self) -> PadGpio11CtrlStW<'_, PadGpio11CtrlSpec> {
3867                PadGpio11CtrlStW::new(self, 3)
3868            }
3869            #[doc = "Bit 4 - Drive strength bit 0"]
3870            #[inline(always)]
3871            pub fn pad_gpio_11_ctrl_ds0(&mut self) -> PadGpio11CtrlDs0W<'_, PadGpio11CtrlSpec> {
3872                PadGpio11CtrlDs0W::new(self, 4)
3873            }
3874            #[doc = "Bit 5 - Drive strength bit 1"]
3875            #[inline(always)]
3876            pub fn pad_gpio_11_ctrl_ds1(&mut self) -> PadGpio11CtrlDs1W<'_, PadGpio11CtrlSpec> {
3877                PadGpio11CtrlDs1W::new(self, 5)
3878            }
3879            #[doc = "Bit 6 - Drive strength bit 2"]
3880            #[inline(always)]
3881            pub fn pad_gpio_11_ctrl_ds2(&mut self) -> PadGpio11CtrlDs2W<'_, PadGpio11CtrlSpec> {
3882                PadGpio11CtrlDs2W::new(self, 6)
3883            }
3884            #[doc = "Bit 9 - Pull enable"]
3885            #[inline(always)]
3886            pub fn pad_gpio_11_ctrl_pe(&mut self) -> PadGpio11CtrlPeW<'_, PadGpio11CtrlSpec> {
3887                PadGpio11CtrlPeW::new(self, 9)
3888            }
3889            #[doc = "Bit 10 - Pull select"]
3890            #[inline(always)]
3891            pub fn pad_gpio_11_ctrl_ps(&mut self) -> PadGpio11CtrlPsW<'_, PadGpio11CtrlSpec> {
3892                PadGpio11CtrlPsW::new(self, 10)
3893            }
3894            #[doc = "Bit 11 - Input enable"]
3895            #[inline(always)]
3896            pub fn pad_gpio_11_ctrl_ie(&mut self) -> PadGpio11CtrlIeW<'_, PadGpio11CtrlSpec> {
3897                PadGpio11CtrlIeW::new(self, 11)
3898            }
3899        }
3900        #[doc = "GPIO_11 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_11_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_11_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3901        pub struct PadGpio11CtrlSpec;
3902        impl crate::RegisterSpec for PadGpio11CtrlSpec {
3903            type Ux = u32;
3904        }
3905        #[doc = "`read()` method returns [`pad_gpio_11_ctrl::R`](R) reader structure"]
3906        impl crate::Readable for PadGpio11CtrlSpec {}
3907        #[doc = "`write(|w| ..)` method takes [`pad_gpio_11_ctrl::W`](W) writer structure"]
3908        impl crate::Writable for PadGpio11CtrlSpec {
3909            type Safety = crate::Unsafe;
3910        }
3911        #[doc = "`reset()` method sets PAD_GPIO_11_CTRL to value 0x0a00"]
3912        impl crate::Resettable for PadGpio11CtrlSpec {
3913            const RESET_VALUE: u32 = 0x0a00;
3914        }
3915    }
3916    #[doc = "PAD_GPIO_12_CTRL (rw) register accessor: GPIO_12 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_12_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_12_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_12_ctrl`] module"]
3917    #[doc(alias = "PAD_GPIO_12_CTRL")]
3918    pub type PadGpio12Ctrl = crate::Reg<pad_gpio_12_ctrl::PadGpio12CtrlSpec>;
3919    #[doc = "GPIO_12 pad control register"]
3920    pub mod pad_gpio_12_ctrl {
3921        #[doc = "Register `PAD_GPIO_12_CTRL` reader"]
3922        pub type R = crate::R<PadGpio12CtrlSpec>;
3923        #[doc = "Register `PAD_GPIO_12_CTRL` writer"]
3924        pub type W = crate::W<PadGpio12CtrlSpec>;
3925        #[doc = "Field `pad_gpio_12_ctrl_st` reader - Schmitt trigger"]
3926        pub type PadGpio12CtrlStR = crate::BitReader;
3927        #[doc = "Field `pad_gpio_12_ctrl_st` writer - Schmitt trigger"]
3928        pub type PadGpio12CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
3929        #[doc = "Field `pad_gpio_12_ctrl_ds0` reader - Drive strength bit 0"]
3930        pub type PadGpio12CtrlDs0R = crate::BitReader;
3931        #[doc = "Field `pad_gpio_12_ctrl_ds0` writer - Drive strength bit 0"]
3932        pub type PadGpio12CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
3933        #[doc = "Field `pad_gpio_12_ctrl_ds1` reader - Drive strength bit 1"]
3934        pub type PadGpio12CtrlDs1R = crate::BitReader;
3935        #[doc = "Field `pad_gpio_12_ctrl_ds1` writer - Drive strength bit 1"]
3936        pub type PadGpio12CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
3937        #[doc = "Field `pad_gpio_12_ctrl_ds2` reader - Drive strength bit 2"]
3938        pub type PadGpio12CtrlDs2R = crate::BitReader;
3939        #[doc = "Field `pad_gpio_12_ctrl_ds2` writer - Drive strength bit 2"]
3940        pub type PadGpio12CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
3941        #[doc = "Field `pad_gpio_12_ctrl_pe` reader - Pull enable"]
3942        pub type PadGpio12CtrlPeR = crate::BitReader;
3943        #[doc = "Field `pad_gpio_12_ctrl_pe` writer - Pull enable"]
3944        pub type PadGpio12CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
3945        #[doc = "Field `pad_gpio_12_ctrl_ps` reader - Pull select"]
3946        pub type PadGpio12CtrlPsR = crate::BitReader;
3947        #[doc = "Field `pad_gpio_12_ctrl_ps` writer - Pull select"]
3948        pub type PadGpio12CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
3949        #[doc = "Field `pad_gpio_12_ctrl_ie` reader - Input enable"]
3950        pub type PadGpio12CtrlIeR = crate::BitReader;
3951        #[doc = "Field `pad_gpio_12_ctrl_ie` writer - Input enable"]
3952        pub type PadGpio12CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
3953        impl R {
3954            #[doc = "Bit 3 - Schmitt trigger"]
3955            #[inline(always)]
3956            pub fn pad_gpio_12_ctrl_st(&self) -> PadGpio12CtrlStR {
3957                PadGpio12CtrlStR::new(((self.bits >> 3) & 1) != 0)
3958            }
3959            #[doc = "Bit 4 - Drive strength bit 0"]
3960            #[inline(always)]
3961            pub fn pad_gpio_12_ctrl_ds0(&self) -> PadGpio12CtrlDs0R {
3962                PadGpio12CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
3963            }
3964            #[doc = "Bit 5 - Drive strength bit 1"]
3965            #[inline(always)]
3966            pub fn pad_gpio_12_ctrl_ds1(&self) -> PadGpio12CtrlDs1R {
3967                PadGpio12CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
3968            }
3969            #[doc = "Bit 6 - Drive strength bit 2"]
3970            #[inline(always)]
3971            pub fn pad_gpio_12_ctrl_ds2(&self) -> PadGpio12CtrlDs2R {
3972                PadGpio12CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
3973            }
3974            #[doc = "Bit 9 - Pull enable"]
3975            #[inline(always)]
3976            pub fn pad_gpio_12_ctrl_pe(&self) -> PadGpio12CtrlPeR {
3977                PadGpio12CtrlPeR::new(((self.bits >> 9) & 1) != 0)
3978            }
3979            #[doc = "Bit 10 - Pull select"]
3980            #[inline(always)]
3981            pub fn pad_gpio_12_ctrl_ps(&self) -> PadGpio12CtrlPsR {
3982                PadGpio12CtrlPsR::new(((self.bits >> 10) & 1) != 0)
3983            }
3984            #[doc = "Bit 11 - Input enable"]
3985            #[inline(always)]
3986            pub fn pad_gpio_12_ctrl_ie(&self) -> PadGpio12CtrlIeR {
3987                PadGpio12CtrlIeR::new(((self.bits >> 11) & 1) != 0)
3988            }
3989        }
3990        impl W {
3991            #[doc = "Bit 3 - Schmitt trigger"]
3992            #[inline(always)]
3993            pub fn pad_gpio_12_ctrl_st(&mut self) -> PadGpio12CtrlStW<'_, PadGpio12CtrlSpec> {
3994                PadGpio12CtrlStW::new(self, 3)
3995            }
3996            #[doc = "Bit 4 - Drive strength bit 0"]
3997            #[inline(always)]
3998            pub fn pad_gpio_12_ctrl_ds0(&mut self) -> PadGpio12CtrlDs0W<'_, PadGpio12CtrlSpec> {
3999                PadGpio12CtrlDs0W::new(self, 4)
4000            }
4001            #[doc = "Bit 5 - Drive strength bit 1"]
4002            #[inline(always)]
4003            pub fn pad_gpio_12_ctrl_ds1(&mut self) -> PadGpio12CtrlDs1W<'_, PadGpio12CtrlSpec> {
4004                PadGpio12CtrlDs1W::new(self, 5)
4005            }
4006            #[doc = "Bit 6 - Drive strength bit 2"]
4007            #[inline(always)]
4008            pub fn pad_gpio_12_ctrl_ds2(&mut self) -> PadGpio12CtrlDs2W<'_, PadGpio12CtrlSpec> {
4009                PadGpio12CtrlDs2W::new(self, 6)
4010            }
4011            #[doc = "Bit 9 - Pull enable"]
4012            #[inline(always)]
4013            pub fn pad_gpio_12_ctrl_pe(&mut self) -> PadGpio12CtrlPeW<'_, PadGpio12CtrlSpec> {
4014                PadGpio12CtrlPeW::new(self, 9)
4015            }
4016            #[doc = "Bit 10 - Pull select"]
4017            #[inline(always)]
4018            pub fn pad_gpio_12_ctrl_ps(&mut self) -> PadGpio12CtrlPsW<'_, PadGpio12CtrlSpec> {
4019                PadGpio12CtrlPsW::new(self, 10)
4020            }
4021            #[doc = "Bit 11 - Input enable"]
4022            #[inline(always)]
4023            pub fn pad_gpio_12_ctrl_ie(&mut self) -> PadGpio12CtrlIeW<'_, PadGpio12CtrlSpec> {
4024                PadGpio12CtrlIeW::new(self, 11)
4025            }
4026        }
4027        #[doc = "GPIO_12 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_12_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_12_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4028        pub struct PadGpio12CtrlSpec;
4029        impl crate::RegisterSpec for PadGpio12CtrlSpec {
4030            type Ux = u32;
4031        }
4032        #[doc = "`read()` method returns [`pad_gpio_12_ctrl::R`](R) reader structure"]
4033        impl crate::Readable for PadGpio12CtrlSpec {}
4034        #[doc = "`write(|w| ..)` method takes [`pad_gpio_12_ctrl::W`](W) writer structure"]
4035        impl crate::Writable for PadGpio12CtrlSpec {
4036            type Safety = crate::Unsafe;
4037        }
4038        #[doc = "`reset()` method sets PAD_GPIO_12_CTRL to value 0x0a00"]
4039        impl crate::Resettable for PadGpio12CtrlSpec {
4040            const RESET_VALUE: u32 = 0x0a00;
4041        }
4042    }
4043    #[doc = "PAD_GPIO_13_CTRL (rw) register accessor: GPIO_13 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_13_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_13_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_13_ctrl`] module"]
4044    #[doc(alias = "PAD_GPIO_13_CTRL")]
4045    pub type PadGpio13Ctrl = crate::Reg<pad_gpio_13_ctrl::PadGpio13CtrlSpec>;
4046    #[doc = "GPIO_13 pad control register"]
4047    pub mod pad_gpio_13_ctrl {
4048        #[doc = "Register `PAD_GPIO_13_CTRL` reader"]
4049        pub type R = crate::R<PadGpio13CtrlSpec>;
4050        #[doc = "Register `PAD_GPIO_13_CTRL` writer"]
4051        pub type W = crate::W<PadGpio13CtrlSpec>;
4052        #[doc = "Field `pad_gpio_13_ctrl_st` reader - Schmitt trigger"]
4053        pub type PadGpio13CtrlStR = crate::BitReader;
4054        #[doc = "Field `pad_gpio_13_ctrl_st` writer - Schmitt trigger"]
4055        pub type PadGpio13CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
4056        #[doc = "Field `pad_gpio_13_ctrl_ds0` reader - Drive strength bit 0"]
4057        pub type PadGpio13CtrlDs0R = crate::BitReader;
4058        #[doc = "Field `pad_gpio_13_ctrl_ds0` writer - Drive strength bit 0"]
4059        pub type PadGpio13CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
4060        #[doc = "Field `pad_gpio_13_ctrl_ds1` reader - Drive strength bit 1"]
4061        pub type PadGpio13CtrlDs1R = crate::BitReader;
4062        #[doc = "Field `pad_gpio_13_ctrl_ds1` writer - Drive strength bit 1"]
4063        pub type PadGpio13CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
4064        #[doc = "Field `pad_gpio_13_ctrl_ds2` reader - Drive strength bit 2"]
4065        pub type PadGpio13CtrlDs2R = crate::BitReader;
4066        #[doc = "Field `pad_gpio_13_ctrl_ds2` writer - Drive strength bit 2"]
4067        pub type PadGpio13CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
4068        #[doc = "Field `pad_gpio_13_ctrl_pe` reader - Pull enable"]
4069        pub type PadGpio13CtrlPeR = crate::BitReader;
4070        #[doc = "Field `pad_gpio_13_ctrl_pe` writer - Pull enable"]
4071        pub type PadGpio13CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
4072        #[doc = "Field `pad_gpio_13_ctrl_ps` reader - Pull select"]
4073        pub type PadGpio13CtrlPsR = crate::BitReader;
4074        #[doc = "Field `pad_gpio_13_ctrl_ps` writer - Pull select"]
4075        pub type PadGpio13CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
4076        #[doc = "Field `pad_gpio_13_ctrl_ie` reader - Input enable"]
4077        pub type PadGpio13CtrlIeR = crate::BitReader;
4078        #[doc = "Field `pad_gpio_13_ctrl_ie` writer - Input enable"]
4079        pub type PadGpio13CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
4080        impl R {
4081            #[doc = "Bit 3 - Schmitt trigger"]
4082            #[inline(always)]
4083            pub fn pad_gpio_13_ctrl_st(&self) -> PadGpio13CtrlStR {
4084                PadGpio13CtrlStR::new(((self.bits >> 3) & 1) != 0)
4085            }
4086            #[doc = "Bit 4 - Drive strength bit 0"]
4087            #[inline(always)]
4088            pub fn pad_gpio_13_ctrl_ds0(&self) -> PadGpio13CtrlDs0R {
4089                PadGpio13CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
4090            }
4091            #[doc = "Bit 5 - Drive strength bit 1"]
4092            #[inline(always)]
4093            pub fn pad_gpio_13_ctrl_ds1(&self) -> PadGpio13CtrlDs1R {
4094                PadGpio13CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
4095            }
4096            #[doc = "Bit 6 - Drive strength bit 2"]
4097            #[inline(always)]
4098            pub fn pad_gpio_13_ctrl_ds2(&self) -> PadGpio13CtrlDs2R {
4099                PadGpio13CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
4100            }
4101            #[doc = "Bit 9 - Pull enable"]
4102            #[inline(always)]
4103            pub fn pad_gpio_13_ctrl_pe(&self) -> PadGpio13CtrlPeR {
4104                PadGpio13CtrlPeR::new(((self.bits >> 9) & 1) != 0)
4105            }
4106            #[doc = "Bit 10 - Pull select"]
4107            #[inline(always)]
4108            pub fn pad_gpio_13_ctrl_ps(&self) -> PadGpio13CtrlPsR {
4109                PadGpio13CtrlPsR::new(((self.bits >> 10) & 1) != 0)
4110            }
4111            #[doc = "Bit 11 - Input enable"]
4112            #[inline(always)]
4113            pub fn pad_gpio_13_ctrl_ie(&self) -> PadGpio13CtrlIeR {
4114                PadGpio13CtrlIeR::new(((self.bits >> 11) & 1) != 0)
4115            }
4116        }
4117        impl W {
4118            #[doc = "Bit 3 - Schmitt trigger"]
4119            #[inline(always)]
4120            pub fn pad_gpio_13_ctrl_st(&mut self) -> PadGpio13CtrlStW<'_, PadGpio13CtrlSpec> {
4121                PadGpio13CtrlStW::new(self, 3)
4122            }
4123            #[doc = "Bit 4 - Drive strength bit 0"]
4124            #[inline(always)]
4125            pub fn pad_gpio_13_ctrl_ds0(&mut self) -> PadGpio13CtrlDs0W<'_, PadGpio13CtrlSpec> {
4126                PadGpio13CtrlDs0W::new(self, 4)
4127            }
4128            #[doc = "Bit 5 - Drive strength bit 1"]
4129            #[inline(always)]
4130            pub fn pad_gpio_13_ctrl_ds1(&mut self) -> PadGpio13CtrlDs1W<'_, PadGpio13CtrlSpec> {
4131                PadGpio13CtrlDs1W::new(self, 5)
4132            }
4133            #[doc = "Bit 6 - Drive strength bit 2"]
4134            #[inline(always)]
4135            pub fn pad_gpio_13_ctrl_ds2(&mut self) -> PadGpio13CtrlDs2W<'_, PadGpio13CtrlSpec> {
4136                PadGpio13CtrlDs2W::new(self, 6)
4137            }
4138            #[doc = "Bit 9 - Pull enable"]
4139            #[inline(always)]
4140            pub fn pad_gpio_13_ctrl_pe(&mut self) -> PadGpio13CtrlPeW<'_, PadGpio13CtrlSpec> {
4141                PadGpio13CtrlPeW::new(self, 9)
4142            }
4143            #[doc = "Bit 10 - Pull select"]
4144            #[inline(always)]
4145            pub fn pad_gpio_13_ctrl_ps(&mut self) -> PadGpio13CtrlPsW<'_, PadGpio13CtrlSpec> {
4146                PadGpio13CtrlPsW::new(self, 10)
4147            }
4148            #[doc = "Bit 11 - Input enable"]
4149            #[inline(always)]
4150            pub fn pad_gpio_13_ctrl_ie(&mut self) -> PadGpio13CtrlIeW<'_, PadGpio13CtrlSpec> {
4151                PadGpio13CtrlIeW::new(self, 11)
4152            }
4153        }
4154        #[doc = "GPIO_13 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_13_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_13_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4155        pub struct PadGpio13CtrlSpec;
4156        impl crate::RegisterSpec for PadGpio13CtrlSpec {
4157            type Ux = u32;
4158        }
4159        #[doc = "`read()` method returns [`pad_gpio_13_ctrl::R`](R) reader structure"]
4160        impl crate::Readable for PadGpio13CtrlSpec {}
4161        #[doc = "`write(|w| ..)` method takes [`pad_gpio_13_ctrl::W`](W) writer structure"]
4162        impl crate::Writable for PadGpio13CtrlSpec {
4163            type Safety = crate::Unsafe;
4164        }
4165        #[doc = "`reset()` method sets PAD_GPIO_13_CTRL to value 0x0800"]
4166        impl crate::Resettable for PadGpio13CtrlSpec {
4167            const RESET_VALUE: u32 = 0x0800;
4168        }
4169    }
4170    #[doc = "PAD_GPIO_14_CTRL (rw) register accessor: GPIO_14 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_14_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_14_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_14_ctrl`] module"]
4171    #[doc(alias = "PAD_GPIO_14_CTRL")]
4172    pub type PadGpio14Ctrl = crate::Reg<pad_gpio_14_ctrl::PadGpio14CtrlSpec>;
4173    #[doc = "GPIO_14 pad control register"]
4174    pub mod pad_gpio_14_ctrl {
4175        #[doc = "Register `PAD_GPIO_14_CTRL` reader"]
4176        pub type R = crate::R<PadGpio14CtrlSpec>;
4177        #[doc = "Register `PAD_GPIO_14_CTRL` writer"]
4178        pub type W = crate::W<PadGpio14CtrlSpec>;
4179        #[doc = "Field `pad_gpio_14_ctrl_st` reader - Schmitt trigger"]
4180        pub type PadGpio14CtrlStR = crate::BitReader;
4181        #[doc = "Field `pad_gpio_14_ctrl_st` writer - Schmitt trigger"]
4182        pub type PadGpio14CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
4183        #[doc = "Field `pad_gpio_14_ctrl_ds0` reader - Drive strength bit 0"]
4184        pub type PadGpio14CtrlDs0R = crate::BitReader;
4185        #[doc = "Field `pad_gpio_14_ctrl_ds0` writer - Drive strength bit 0"]
4186        pub type PadGpio14CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
4187        #[doc = "Field `pad_gpio_14_ctrl_ds1` reader - Drive strength bit 1"]
4188        pub type PadGpio14CtrlDs1R = crate::BitReader;
4189        #[doc = "Field `pad_gpio_14_ctrl_ds1` writer - Drive strength bit 1"]
4190        pub type PadGpio14CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
4191        #[doc = "Field `pad_gpio_14_ctrl_ds2` reader - Drive strength bit 2"]
4192        pub type PadGpio14CtrlDs2R = crate::BitReader;
4193        #[doc = "Field `pad_gpio_14_ctrl_ds2` writer - Drive strength bit 2"]
4194        pub type PadGpio14CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
4195        #[doc = "Field `pad_gpio_14_ctrl_pe` reader - Pull enable"]
4196        pub type PadGpio14CtrlPeR = crate::BitReader;
4197        #[doc = "Field `pad_gpio_14_ctrl_pe` writer - Pull enable"]
4198        pub type PadGpio14CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
4199        #[doc = "Field `pad_gpio_14_ctrl_ps` reader - Pull select"]
4200        pub type PadGpio14CtrlPsR = crate::BitReader;
4201        #[doc = "Field `pad_gpio_14_ctrl_ps` writer - Pull select"]
4202        pub type PadGpio14CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
4203        #[doc = "Field `pad_gpio_14_ctrl_ie` reader - Input enable"]
4204        pub type PadGpio14CtrlIeR = crate::BitReader;
4205        #[doc = "Field `pad_gpio_14_ctrl_ie` writer - Input enable"]
4206        pub type PadGpio14CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
4207        impl R {
4208            #[doc = "Bit 3 - Schmitt trigger"]
4209            #[inline(always)]
4210            pub fn pad_gpio_14_ctrl_st(&self) -> PadGpio14CtrlStR {
4211                PadGpio14CtrlStR::new(((self.bits >> 3) & 1) != 0)
4212            }
4213            #[doc = "Bit 4 - Drive strength bit 0"]
4214            #[inline(always)]
4215            pub fn pad_gpio_14_ctrl_ds0(&self) -> PadGpio14CtrlDs0R {
4216                PadGpio14CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
4217            }
4218            #[doc = "Bit 5 - Drive strength bit 1"]
4219            #[inline(always)]
4220            pub fn pad_gpio_14_ctrl_ds1(&self) -> PadGpio14CtrlDs1R {
4221                PadGpio14CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
4222            }
4223            #[doc = "Bit 6 - Drive strength bit 2"]
4224            #[inline(always)]
4225            pub fn pad_gpio_14_ctrl_ds2(&self) -> PadGpio14CtrlDs2R {
4226                PadGpio14CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
4227            }
4228            #[doc = "Bit 9 - Pull enable"]
4229            #[inline(always)]
4230            pub fn pad_gpio_14_ctrl_pe(&self) -> PadGpio14CtrlPeR {
4231                PadGpio14CtrlPeR::new(((self.bits >> 9) & 1) != 0)
4232            }
4233            #[doc = "Bit 10 - Pull select"]
4234            #[inline(always)]
4235            pub fn pad_gpio_14_ctrl_ps(&self) -> PadGpio14CtrlPsR {
4236                PadGpio14CtrlPsR::new(((self.bits >> 10) & 1) != 0)
4237            }
4238            #[doc = "Bit 11 - Input enable"]
4239            #[inline(always)]
4240            pub fn pad_gpio_14_ctrl_ie(&self) -> PadGpio14CtrlIeR {
4241                PadGpio14CtrlIeR::new(((self.bits >> 11) & 1) != 0)
4242            }
4243        }
4244        impl W {
4245            #[doc = "Bit 3 - Schmitt trigger"]
4246            #[inline(always)]
4247            pub fn pad_gpio_14_ctrl_st(&mut self) -> PadGpio14CtrlStW<'_, PadGpio14CtrlSpec> {
4248                PadGpio14CtrlStW::new(self, 3)
4249            }
4250            #[doc = "Bit 4 - Drive strength bit 0"]
4251            #[inline(always)]
4252            pub fn pad_gpio_14_ctrl_ds0(&mut self) -> PadGpio14CtrlDs0W<'_, PadGpio14CtrlSpec> {
4253                PadGpio14CtrlDs0W::new(self, 4)
4254            }
4255            #[doc = "Bit 5 - Drive strength bit 1"]
4256            #[inline(always)]
4257            pub fn pad_gpio_14_ctrl_ds1(&mut self) -> PadGpio14CtrlDs1W<'_, PadGpio14CtrlSpec> {
4258                PadGpio14CtrlDs1W::new(self, 5)
4259            }
4260            #[doc = "Bit 6 - Drive strength bit 2"]
4261            #[inline(always)]
4262            pub fn pad_gpio_14_ctrl_ds2(&mut self) -> PadGpio14CtrlDs2W<'_, PadGpio14CtrlSpec> {
4263                PadGpio14CtrlDs2W::new(self, 6)
4264            }
4265            #[doc = "Bit 9 - Pull enable"]
4266            #[inline(always)]
4267            pub fn pad_gpio_14_ctrl_pe(&mut self) -> PadGpio14CtrlPeW<'_, PadGpio14CtrlSpec> {
4268                PadGpio14CtrlPeW::new(self, 9)
4269            }
4270            #[doc = "Bit 10 - Pull select"]
4271            #[inline(always)]
4272            pub fn pad_gpio_14_ctrl_ps(&mut self) -> PadGpio14CtrlPsW<'_, PadGpio14CtrlSpec> {
4273                PadGpio14CtrlPsW::new(self, 10)
4274            }
4275            #[doc = "Bit 11 - Input enable"]
4276            #[inline(always)]
4277            pub fn pad_gpio_14_ctrl_ie(&mut self) -> PadGpio14CtrlIeW<'_, PadGpio14CtrlSpec> {
4278                PadGpio14CtrlIeW::new(self, 11)
4279            }
4280        }
4281        #[doc = "GPIO_14 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_14_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_14_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4282        pub struct PadGpio14CtrlSpec;
4283        impl crate::RegisterSpec for PadGpio14CtrlSpec {
4284            type Ux = u32;
4285        }
4286        #[doc = "`read()` method returns [`pad_gpio_14_ctrl::R`](R) reader structure"]
4287        impl crate::Readable for PadGpio14CtrlSpec {}
4288        #[doc = "`write(|w| ..)` method takes [`pad_gpio_14_ctrl::W`](W) writer structure"]
4289        impl crate::Writable for PadGpio14CtrlSpec {
4290            type Safety = crate::Unsafe;
4291        }
4292        #[doc = "`reset()` method sets PAD_GPIO_14_CTRL to value 0x0800"]
4293        impl crate::Resettable for PadGpio14CtrlSpec {
4294            const RESET_VALUE: u32 = 0x0800;
4295        }
4296    }
4297    #[doc = "PAD_UART1_TXD_CTRL (rw) register accessor: UART1_TXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart1_txd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart1_txd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_uart1_txd_ctrl`] module"]
4298    #[doc(alias = "PAD_UART1_TXD_CTRL")]
4299    pub type PadUart1TxdCtrl = crate::Reg<pad_uart1_txd_ctrl::PadUart1TxdCtrlSpec>;
4300    #[doc = "UART1_TXD pad control register"]
4301    pub mod pad_uart1_txd_ctrl {
4302        #[doc = "Register `PAD_UART1_TXD_CTRL` reader"]
4303        pub type R = crate::R<PadUart1TxdCtrlSpec>;
4304        #[doc = "Register `PAD_UART1_TXD_CTRL` writer"]
4305        pub type W = crate::W<PadUart1TxdCtrlSpec>;
4306        #[doc = "Field `pad_uart1_txd_ctrl_st` reader - Schmitt trigger"]
4307        pub type PadUart1TxdCtrlStR = crate::BitReader;
4308        #[doc = "Field `pad_uart1_txd_ctrl_st` writer - Schmitt trigger"]
4309        pub type PadUart1TxdCtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
4310        #[doc = "Field `pad_uart1_txd_ctrl_ie` reader - Input enable"]
4311        pub type PadUart1TxdCtrlIeR = crate::BitReader;
4312        #[doc = "Field `pad_uart1_txd_ctrl_ie` writer - Input enable"]
4313        pub type PadUart1TxdCtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
4314        impl R {
4315            #[doc = "Bit 3 - Schmitt trigger"]
4316            #[inline(always)]
4317            pub fn pad_uart1_txd_ctrl_st(&self) -> PadUart1TxdCtrlStR {
4318                PadUart1TxdCtrlStR::new(((self.bits >> 3) & 1) != 0)
4319            }
4320            #[doc = "Bit 11 - Input enable"]
4321            #[inline(always)]
4322            pub fn pad_uart1_txd_ctrl_ie(&self) -> PadUart1TxdCtrlIeR {
4323                PadUart1TxdCtrlIeR::new(((self.bits >> 11) & 1) != 0)
4324            }
4325        }
4326        impl W {
4327            #[doc = "Bit 3 - Schmitt trigger"]
4328            #[inline(always)]
4329            pub fn pad_uart1_txd_ctrl_st(&mut self) -> PadUart1TxdCtrlStW<'_, PadUart1TxdCtrlSpec> {
4330                PadUart1TxdCtrlStW::new(self, 3)
4331            }
4332            #[doc = "Bit 11 - Input enable"]
4333            #[inline(always)]
4334            pub fn pad_uart1_txd_ctrl_ie(&mut self) -> PadUart1TxdCtrlIeW<'_, PadUart1TxdCtrlSpec> {
4335                PadUart1TxdCtrlIeW::new(self, 11)
4336            }
4337        }
4338        #[doc = "UART1_TXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart1_txd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart1_txd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4339        pub struct PadUart1TxdCtrlSpec;
4340        impl crate::RegisterSpec for PadUart1TxdCtrlSpec {
4341            type Ux = u32;
4342        }
4343        #[doc = "`read()` method returns [`pad_uart1_txd_ctrl::R`](R) reader structure"]
4344        impl crate::Readable for PadUart1TxdCtrlSpec {}
4345        #[doc = "`write(|w| ..)` method takes [`pad_uart1_txd_ctrl::W`](W) writer structure"]
4346        impl crate::Writable for PadUart1TxdCtrlSpec {
4347            type Safety = crate::Unsafe;
4348        }
4349        #[doc = "`reset()` method sets PAD_UART1_TXD_CTRL to value 0x0800"]
4350        impl crate::Resettable for PadUart1TxdCtrlSpec {
4351            const RESET_VALUE: u32 = 0x0800;
4352        }
4353    }
4354    #[doc = "PAD_UART1_RXD_CTRL (rw) register accessor: UART1_RXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart1_rxd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart1_rxd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_uart1_rxd_ctrl`] module"]
4355    #[doc(alias = "PAD_UART1_RXD_CTRL")]
4356    pub type PadUart1RxdCtrl = crate::Reg<pad_uart1_rxd_ctrl::PadUart1RxdCtrlSpec>;
4357    #[doc = "UART1_RXD pad control register"]
4358    pub mod pad_uart1_rxd_ctrl {
4359        #[doc = "Register `PAD_UART1_RXD_CTRL` reader"]
4360        pub type R = crate::R<PadUart1RxdCtrlSpec>;
4361        #[doc = "Register `PAD_UART1_RXD_CTRL` writer"]
4362        pub type W = crate::W<PadUart1RxdCtrlSpec>;
4363        #[doc = "Field `pad_uart1_rxd_ctrl_st` reader - Schmitt trigger"]
4364        pub type PadUart1RxdCtrlStR = crate::BitReader;
4365        #[doc = "Field `pad_uart1_rxd_ctrl_st` writer - Schmitt trigger"]
4366        pub type PadUart1RxdCtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
4367        #[doc = "Field `pad_uart1_rxd_ctrl_ie` reader - Input enable"]
4368        pub type PadUart1RxdCtrlIeR = crate::BitReader;
4369        #[doc = "Field `pad_uart1_rxd_ctrl_ie` writer - Input enable"]
4370        pub type PadUart1RxdCtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
4371        impl R {
4372            #[doc = "Bit 3 - Schmitt trigger"]
4373            #[inline(always)]
4374            pub fn pad_uart1_rxd_ctrl_st(&self) -> PadUart1RxdCtrlStR {
4375                PadUart1RxdCtrlStR::new(((self.bits >> 3) & 1) != 0)
4376            }
4377            #[doc = "Bit 11 - Input enable"]
4378            #[inline(always)]
4379            pub fn pad_uart1_rxd_ctrl_ie(&self) -> PadUart1RxdCtrlIeR {
4380                PadUart1RxdCtrlIeR::new(((self.bits >> 11) & 1) != 0)
4381            }
4382        }
4383        impl W {
4384            #[doc = "Bit 3 - Schmitt trigger"]
4385            #[inline(always)]
4386            pub fn pad_uart1_rxd_ctrl_st(&mut self) -> PadUart1RxdCtrlStW<'_, PadUart1RxdCtrlSpec> {
4387                PadUart1RxdCtrlStW::new(self, 3)
4388            }
4389            #[doc = "Bit 11 - Input enable"]
4390            #[inline(always)]
4391            pub fn pad_uart1_rxd_ctrl_ie(&mut self) -> PadUart1RxdCtrlIeW<'_, PadUart1RxdCtrlSpec> {
4392                PadUart1RxdCtrlIeW::new(self, 11)
4393            }
4394        }
4395        #[doc = "UART1_RXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart1_rxd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart1_rxd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4396        pub struct PadUart1RxdCtrlSpec;
4397        impl crate::RegisterSpec for PadUart1RxdCtrlSpec {
4398            type Ux = u32;
4399        }
4400        #[doc = "`read()` method returns [`pad_uart1_rxd_ctrl::R`](R) reader structure"]
4401        impl crate::Readable for PadUart1RxdCtrlSpec {}
4402        #[doc = "`write(|w| ..)` method takes [`pad_uart1_rxd_ctrl::W`](W) writer structure"]
4403        impl crate::Writable for PadUart1RxdCtrlSpec {
4404            type Safety = crate::Unsafe;
4405        }
4406        #[doc = "`reset()` method sets PAD_UART1_RXD_CTRL to value 0x0800"]
4407        impl crate::Resettable for PadUart1RxdCtrlSpec {
4408            const RESET_VALUE: u32 = 0x0800;
4409        }
4410    }
4411    #[doc = "PAD_UART0_TXD_CTRL (rw) register accessor: UART0_TXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart0_txd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart0_txd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_uart0_txd_ctrl`] module"]
4412    #[doc(alias = "PAD_UART0_TXD_CTRL")]
4413    pub type PadUart0TxdCtrl = crate::Reg<pad_uart0_txd_ctrl::PadUart0TxdCtrlSpec>;
4414    #[doc = "UART0_TXD pad control register"]
4415    pub mod pad_uart0_txd_ctrl {
4416        #[doc = "Register `PAD_UART0_TXD_CTRL` reader"]
4417        pub type R = crate::R<PadUart0TxdCtrlSpec>;
4418        #[doc = "Register `PAD_UART0_TXD_CTRL` writer"]
4419        pub type W = crate::W<PadUart0TxdCtrlSpec>;
4420        #[doc = "Field `pad_uart0_txd_ctrl_st` reader - Schmitt trigger"]
4421        pub type PadUart0TxdCtrlStR = crate::BitReader;
4422        #[doc = "Field `pad_uart0_txd_ctrl_st` writer - Schmitt trigger"]
4423        pub type PadUart0TxdCtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
4424        #[doc = "Field `pad_uart0_txd_ctrl_ie` reader - Input enable"]
4425        pub type PadUart0TxdCtrlIeR = crate::BitReader;
4426        #[doc = "Field `pad_uart0_txd_ctrl_ie` writer - Input enable"]
4427        pub type PadUart0TxdCtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
4428        impl R {
4429            #[doc = "Bit 3 - Schmitt trigger"]
4430            #[inline(always)]
4431            pub fn pad_uart0_txd_ctrl_st(&self) -> PadUart0TxdCtrlStR {
4432                PadUart0TxdCtrlStR::new(((self.bits >> 3) & 1) != 0)
4433            }
4434            #[doc = "Bit 11 - Input enable"]
4435            #[inline(always)]
4436            pub fn pad_uart0_txd_ctrl_ie(&self) -> PadUart0TxdCtrlIeR {
4437                PadUart0TxdCtrlIeR::new(((self.bits >> 11) & 1) != 0)
4438            }
4439        }
4440        impl W {
4441            #[doc = "Bit 3 - Schmitt trigger"]
4442            #[inline(always)]
4443            pub fn pad_uart0_txd_ctrl_st(&mut self) -> PadUart0TxdCtrlStW<'_, PadUart0TxdCtrlSpec> {
4444                PadUart0TxdCtrlStW::new(self, 3)
4445            }
4446            #[doc = "Bit 11 - Input enable"]
4447            #[inline(always)]
4448            pub fn pad_uart0_txd_ctrl_ie(&mut self) -> PadUart0TxdCtrlIeW<'_, PadUart0TxdCtrlSpec> {
4449                PadUart0TxdCtrlIeW::new(self, 11)
4450            }
4451        }
4452        #[doc = "UART0_TXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart0_txd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart0_txd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4453        pub struct PadUart0TxdCtrlSpec;
4454        impl crate::RegisterSpec for PadUart0TxdCtrlSpec {
4455            type Ux = u32;
4456        }
4457        #[doc = "`read()` method returns [`pad_uart0_txd_ctrl::R`](R) reader structure"]
4458        impl crate::Readable for PadUart0TxdCtrlSpec {}
4459        #[doc = "`write(|w| ..)` method takes [`pad_uart0_txd_ctrl::W`](W) writer structure"]
4460        impl crate::Writable for PadUart0TxdCtrlSpec {
4461            type Safety = crate::Unsafe;
4462        }
4463        #[doc = "`reset()` method sets PAD_UART0_TXD_CTRL to value 0x0800"]
4464        impl crate::Resettable for PadUart0TxdCtrlSpec {
4465            const RESET_VALUE: u32 = 0x0800;
4466        }
4467    }
4468    #[doc = "PAD_UART0_RXD_CTRL (rw) register accessor: UART0_RXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart0_rxd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart0_rxd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_uart0_rxd_ctrl`] module"]
4469    #[doc(alias = "PAD_UART0_RXD_CTRL")]
4470    pub type PadUart0RxdCtrl = crate::Reg<pad_uart0_rxd_ctrl::PadUart0RxdCtrlSpec>;
4471    #[doc = "UART0_RXD pad control register"]
4472    pub mod pad_uart0_rxd_ctrl {
4473        #[doc = "Register `PAD_UART0_RXD_CTRL` reader"]
4474        pub type R = crate::R<PadUart0RxdCtrlSpec>;
4475        #[doc = "Register `PAD_UART0_RXD_CTRL` writer"]
4476        pub type W = crate::W<PadUart0RxdCtrlSpec>;
4477        #[doc = "Field `pad_uart0_rxd_ctrl_st` reader - Schmitt trigger"]
4478        pub type PadUart0RxdCtrlStR = crate::BitReader;
4479        #[doc = "Field `pad_uart0_rxd_ctrl_st` writer - Schmitt trigger"]
4480        pub type PadUart0RxdCtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
4481        #[doc = "Field `pad_uart0_rxd_ctrl_ie` reader - Input enable"]
4482        pub type PadUart0RxdCtrlIeR = crate::BitReader;
4483        #[doc = "Field `pad_uart0_rxd_ctrl_ie` writer - Input enable"]
4484        pub type PadUart0RxdCtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
4485        impl R {
4486            #[doc = "Bit 3 - Schmitt trigger"]
4487            #[inline(always)]
4488            pub fn pad_uart0_rxd_ctrl_st(&self) -> PadUart0RxdCtrlStR {
4489                PadUart0RxdCtrlStR::new(((self.bits >> 3) & 1) != 0)
4490            }
4491            #[doc = "Bit 11 - Input enable"]
4492            #[inline(always)]
4493            pub fn pad_uart0_rxd_ctrl_ie(&self) -> PadUart0RxdCtrlIeR {
4494                PadUart0RxdCtrlIeR::new(((self.bits >> 11) & 1) != 0)
4495            }
4496        }
4497        impl W {
4498            #[doc = "Bit 3 - Schmitt trigger"]
4499            #[inline(always)]
4500            pub fn pad_uart0_rxd_ctrl_st(&mut self) -> PadUart0RxdCtrlStW<'_, PadUart0RxdCtrlSpec> {
4501                PadUart0RxdCtrlStW::new(self, 3)
4502            }
4503            #[doc = "Bit 11 - Input enable"]
4504            #[inline(always)]
4505            pub fn pad_uart0_rxd_ctrl_ie(&mut self) -> PadUart0RxdCtrlIeW<'_, PadUart0RxdCtrlSpec> {
4506                PadUart0RxdCtrlIeW::new(self, 11)
4507            }
4508        }
4509        #[doc = "UART0_RXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart0_rxd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart0_rxd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4510        pub struct PadUart0RxdCtrlSpec;
4511        impl crate::RegisterSpec for PadUart0RxdCtrlSpec {
4512            type Ux = u32;
4513        }
4514        #[doc = "`read()` method returns [`pad_uart0_rxd_ctrl::R`](R) reader structure"]
4515        impl crate::Readable for PadUart0RxdCtrlSpec {}
4516        #[doc = "`write(|w| ..)` method takes [`pad_uart0_rxd_ctrl::W`](W) writer structure"]
4517        impl crate::Writable for PadUart0RxdCtrlSpec {
4518            type Safety = crate::Unsafe;
4519        }
4520        #[doc = "`reset()` method sets PAD_UART0_RXD_CTRL to value 0x0800"]
4521        impl crate::Resettable for PadUart0RxdCtrlSpec {
4522            const RESET_VALUE: u32 = 0x0800;
4523        }
4524    }
4525    #[doc = "PAD_SFC_CLK_CTRL (rw) register accessor: SFC_CLK pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_clk_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_clk_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_clk_ctrl`] module"]
4526    #[doc(alias = "PAD_SFC_CLK_CTRL")]
4527    pub type PadSfcClkCtrl = crate::Reg<pad_sfc_clk_ctrl::PadSfcClkCtrlSpec>;
4528    #[doc = "SFC_CLK pad control register"]
4529    pub mod pad_sfc_clk_ctrl {
4530        #[doc = "Register `PAD_SFC_CLK_CTRL` reader"]
4531        pub type R = crate::R<PadSfcClkCtrlSpec>;
4532        #[doc = "Register `PAD_SFC_CLK_CTRL` writer"]
4533        pub type W = crate::W<PadSfcClkCtrlSpec>;
4534        #[doc = "Field `pad_sfc_clk_ctrl_st` reader - Schmitt trigger"]
4535        pub type PadSfcClkCtrlStR = crate::BitReader;
4536        #[doc = "Field `pad_sfc_clk_ctrl_st` writer - Schmitt trigger"]
4537        pub type PadSfcClkCtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
4538        #[doc = "Field `pad_sfc_clk_ctrl_ds0` reader - Drive strength bit 0"]
4539        pub type PadSfcClkCtrlDs0R = crate::BitReader;
4540        #[doc = "Field `pad_sfc_clk_ctrl_ds0` writer - Drive strength bit 0"]
4541        pub type PadSfcClkCtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
4542        #[doc = "Field `pad_sfc_clk_ctrl_ds1` reader - Drive strength bit 1"]
4543        pub type PadSfcClkCtrlDs1R = crate::BitReader;
4544        #[doc = "Field `pad_sfc_clk_ctrl_ds1` writer - Drive strength bit 1"]
4545        pub type PadSfcClkCtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
4546        #[doc = "Field `pad_sfc_clk_ctrl_ds2` reader - Drive strength bit 2"]
4547        pub type PadSfcClkCtrlDs2R = crate::BitReader;
4548        #[doc = "Field `pad_sfc_clk_ctrl_ds2` writer - Drive strength bit 2"]
4549        pub type PadSfcClkCtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
4550        #[doc = "Field `pad_sfc_clk_ctrl_pe` reader - Pull enable"]
4551        pub type PadSfcClkCtrlPeR = crate::BitReader;
4552        #[doc = "Field `pad_sfc_clk_ctrl_pe` writer - Pull enable"]
4553        pub type PadSfcClkCtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
4554        #[doc = "Field `pad_sfc_clk_ctrl_ps` reader - Pull select"]
4555        pub type PadSfcClkCtrlPsR = crate::BitReader;
4556        #[doc = "Field `pad_sfc_clk_ctrl_ps` writer - Pull select"]
4557        pub type PadSfcClkCtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
4558        #[doc = "Field `pad_sfc_clk_ctrl_ie` reader - Input enable"]
4559        pub type PadSfcClkCtrlIeR = crate::BitReader;
4560        #[doc = "Field `pad_sfc_clk_ctrl_ie` writer - Input enable"]
4561        pub type PadSfcClkCtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
4562        impl R {
4563            #[doc = "Bit 3 - Schmitt trigger"]
4564            #[inline(always)]
4565            pub fn pad_sfc_clk_ctrl_st(&self) -> PadSfcClkCtrlStR {
4566                PadSfcClkCtrlStR::new(((self.bits >> 3) & 1) != 0)
4567            }
4568            #[doc = "Bit 4 - Drive strength bit 0"]
4569            #[inline(always)]
4570            pub fn pad_sfc_clk_ctrl_ds0(&self) -> PadSfcClkCtrlDs0R {
4571                PadSfcClkCtrlDs0R::new(((self.bits >> 4) & 1) != 0)
4572            }
4573            #[doc = "Bit 5 - Drive strength bit 1"]
4574            #[inline(always)]
4575            pub fn pad_sfc_clk_ctrl_ds1(&self) -> PadSfcClkCtrlDs1R {
4576                PadSfcClkCtrlDs1R::new(((self.bits >> 5) & 1) != 0)
4577            }
4578            #[doc = "Bit 6 - Drive strength bit 2"]
4579            #[inline(always)]
4580            pub fn pad_sfc_clk_ctrl_ds2(&self) -> PadSfcClkCtrlDs2R {
4581                PadSfcClkCtrlDs2R::new(((self.bits >> 6) & 1) != 0)
4582            }
4583            #[doc = "Bit 9 - Pull enable"]
4584            #[inline(always)]
4585            pub fn pad_sfc_clk_ctrl_pe(&self) -> PadSfcClkCtrlPeR {
4586                PadSfcClkCtrlPeR::new(((self.bits >> 9) & 1) != 0)
4587            }
4588            #[doc = "Bit 10 - Pull select"]
4589            #[inline(always)]
4590            pub fn pad_sfc_clk_ctrl_ps(&self) -> PadSfcClkCtrlPsR {
4591                PadSfcClkCtrlPsR::new(((self.bits >> 10) & 1) != 0)
4592            }
4593            #[doc = "Bit 11 - Input enable"]
4594            #[inline(always)]
4595            pub fn pad_sfc_clk_ctrl_ie(&self) -> PadSfcClkCtrlIeR {
4596                PadSfcClkCtrlIeR::new(((self.bits >> 11) & 1) != 0)
4597            }
4598        }
4599        impl W {
4600            #[doc = "Bit 3 - Schmitt trigger"]
4601            #[inline(always)]
4602            pub fn pad_sfc_clk_ctrl_st(&mut self) -> PadSfcClkCtrlStW<'_, PadSfcClkCtrlSpec> {
4603                PadSfcClkCtrlStW::new(self, 3)
4604            }
4605            #[doc = "Bit 4 - Drive strength bit 0"]
4606            #[inline(always)]
4607            pub fn pad_sfc_clk_ctrl_ds0(&mut self) -> PadSfcClkCtrlDs0W<'_, PadSfcClkCtrlSpec> {
4608                PadSfcClkCtrlDs0W::new(self, 4)
4609            }
4610            #[doc = "Bit 5 - Drive strength bit 1"]
4611            #[inline(always)]
4612            pub fn pad_sfc_clk_ctrl_ds1(&mut self) -> PadSfcClkCtrlDs1W<'_, PadSfcClkCtrlSpec> {
4613                PadSfcClkCtrlDs1W::new(self, 5)
4614            }
4615            #[doc = "Bit 6 - Drive strength bit 2"]
4616            #[inline(always)]
4617            pub fn pad_sfc_clk_ctrl_ds2(&mut self) -> PadSfcClkCtrlDs2W<'_, PadSfcClkCtrlSpec> {
4618                PadSfcClkCtrlDs2W::new(self, 6)
4619            }
4620            #[doc = "Bit 9 - Pull enable"]
4621            #[inline(always)]
4622            pub fn pad_sfc_clk_ctrl_pe(&mut self) -> PadSfcClkCtrlPeW<'_, PadSfcClkCtrlSpec> {
4623                PadSfcClkCtrlPeW::new(self, 9)
4624            }
4625            #[doc = "Bit 10 - Pull select"]
4626            #[inline(always)]
4627            pub fn pad_sfc_clk_ctrl_ps(&mut self) -> PadSfcClkCtrlPsW<'_, PadSfcClkCtrlSpec> {
4628                PadSfcClkCtrlPsW::new(self, 10)
4629            }
4630            #[doc = "Bit 11 - Input enable"]
4631            #[inline(always)]
4632            pub fn pad_sfc_clk_ctrl_ie(&mut self) -> PadSfcClkCtrlIeW<'_, PadSfcClkCtrlSpec> {
4633                PadSfcClkCtrlIeW::new(self, 11)
4634            }
4635        }
4636        #[doc = "SFC_CLK pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_clk_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_clk_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4637        pub struct PadSfcClkCtrlSpec;
4638        impl crate::RegisterSpec for PadSfcClkCtrlSpec {
4639            type Ux = u32;
4640        }
4641        #[doc = "`read()` method returns [`pad_sfc_clk_ctrl::R`](R) reader structure"]
4642        impl crate::Readable for PadSfcClkCtrlSpec {}
4643        #[doc = "`write(|w| ..)` method takes [`pad_sfc_clk_ctrl::W`](W) writer structure"]
4644        impl crate::Writable for PadSfcClkCtrlSpec {
4645            type Safety = crate::Unsafe;
4646        }
4647        #[doc = "`reset()` method sets PAD_SFC_CLK_CTRL to value 0x0810"]
4648        impl crate::Resettable for PadSfcClkCtrlSpec {
4649            const RESET_VALUE: u32 = 0x0810;
4650        }
4651    }
4652    #[doc = "PAD_SFC_CSN_CTRL (rw) register accessor: SFC_CSN pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_csn_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_csn_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_csn_ctrl`] module"]
4653    #[doc(alias = "PAD_SFC_CSN_CTRL")]
4654    pub type PadSfcCsnCtrl = crate::Reg<pad_sfc_csn_ctrl::PadSfcCsnCtrlSpec>;
4655    #[doc = "SFC_CSN pad control register"]
4656    pub mod pad_sfc_csn_ctrl {
4657        #[doc = "Register `PAD_SFC_CSN_CTRL` reader"]
4658        pub type R = crate::R<PadSfcCsnCtrlSpec>;
4659        #[doc = "Register `PAD_SFC_CSN_CTRL` writer"]
4660        pub type W = crate::W<PadSfcCsnCtrlSpec>;
4661        #[doc = "Field `pad_sfc_csn_ctrl_st` reader - Schmitt trigger"]
4662        pub type PadSfcCsnCtrlStR = crate::BitReader;
4663        #[doc = "Field `pad_sfc_csn_ctrl_st` writer - Schmitt trigger"]
4664        pub type PadSfcCsnCtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
4665        #[doc = "Field `pad_sfc_csn_ctrl_ds0` reader - Drive strength bit 0"]
4666        pub type PadSfcCsnCtrlDs0R = crate::BitReader;
4667        #[doc = "Field `pad_sfc_csn_ctrl_ds0` writer - Drive strength bit 0"]
4668        pub type PadSfcCsnCtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
4669        #[doc = "Field `pad_sfc_csn_ctrl_ds1` reader - Drive strength bit 1"]
4670        pub type PadSfcCsnCtrlDs1R = crate::BitReader;
4671        #[doc = "Field `pad_sfc_csn_ctrl_ds1` writer - Drive strength bit 1"]
4672        pub type PadSfcCsnCtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
4673        #[doc = "Field `pad_sfc_csn_ctrl_ds2` reader - Drive strength bit 2"]
4674        pub type PadSfcCsnCtrlDs2R = crate::BitReader;
4675        #[doc = "Field `pad_sfc_csn_ctrl_ds2` writer - Drive strength bit 2"]
4676        pub type PadSfcCsnCtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
4677        #[doc = "Field `pad_sfc_csn_ctrl_pe` reader - Pull enable"]
4678        pub type PadSfcCsnCtrlPeR = crate::BitReader;
4679        #[doc = "Field `pad_sfc_csn_ctrl_pe` writer - Pull enable"]
4680        pub type PadSfcCsnCtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
4681        #[doc = "Field `pad_sfc_csn_ctrl_ps` reader - Pull select"]
4682        pub type PadSfcCsnCtrlPsR = crate::BitReader;
4683        #[doc = "Field `pad_sfc_csn_ctrl_ps` writer - Pull select"]
4684        pub type PadSfcCsnCtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
4685        #[doc = "Field `pad_sfc_csn_ctrl_ie` reader - Input enable"]
4686        pub type PadSfcCsnCtrlIeR = crate::BitReader;
4687        #[doc = "Field `pad_sfc_csn_ctrl_ie` writer - Input enable"]
4688        pub type PadSfcCsnCtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
4689        impl R {
4690            #[doc = "Bit 3 - Schmitt trigger"]
4691            #[inline(always)]
4692            pub fn pad_sfc_csn_ctrl_st(&self) -> PadSfcCsnCtrlStR {
4693                PadSfcCsnCtrlStR::new(((self.bits >> 3) & 1) != 0)
4694            }
4695            #[doc = "Bit 4 - Drive strength bit 0"]
4696            #[inline(always)]
4697            pub fn pad_sfc_csn_ctrl_ds0(&self) -> PadSfcCsnCtrlDs0R {
4698                PadSfcCsnCtrlDs0R::new(((self.bits >> 4) & 1) != 0)
4699            }
4700            #[doc = "Bit 5 - Drive strength bit 1"]
4701            #[inline(always)]
4702            pub fn pad_sfc_csn_ctrl_ds1(&self) -> PadSfcCsnCtrlDs1R {
4703                PadSfcCsnCtrlDs1R::new(((self.bits >> 5) & 1) != 0)
4704            }
4705            #[doc = "Bit 6 - Drive strength bit 2"]
4706            #[inline(always)]
4707            pub fn pad_sfc_csn_ctrl_ds2(&self) -> PadSfcCsnCtrlDs2R {
4708                PadSfcCsnCtrlDs2R::new(((self.bits >> 6) & 1) != 0)
4709            }
4710            #[doc = "Bit 9 - Pull enable"]
4711            #[inline(always)]
4712            pub fn pad_sfc_csn_ctrl_pe(&self) -> PadSfcCsnCtrlPeR {
4713                PadSfcCsnCtrlPeR::new(((self.bits >> 9) & 1) != 0)
4714            }
4715            #[doc = "Bit 10 - Pull select"]
4716            #[inline(always)]
4717            pub fn pad_sfc_csn_ctrl_ps(&self) -> PadSfcCsnCtrlPsR {
4718                PadSfcCsnCtrlPsR::new(((self.bits >> 10) & 1) != 0)
4719            }
4720            #[doc = "Bit 11 - Input enable"]
4721            #[inline(always)]
4722            pub fn pad_sfc_csn_ctrl_ie(&self) -> PadSfcCsnCtrlIeR {
4723                PadSfcCsnCtrlIeR::new(((self.bits >> 11) & 1) != 0)
4724            }
4725        }
4726        impl W {
4727            #[doc = "Bit 3 - Schmitt trigger"]
4728            #[inline(always)]
4729            pub fn pad_sfc_csn_ctrl_st(&mut self) -> PadSfcCsnCtrlStW<'_, PadSfcCsnCtrlSpec> {
4730                PadSfcCsnCtrlStW::new(self, 3)
4731            }
4732            #[doc = "Bit 4 - Drive strength bit 0"]
4733            #[inline(always)]
4734            pub fn pad_sfc_csn_ctrl_ds0(&mut self) -> PadSfcCsnCtrlDs0W<'_, PadSfcCsnCtrlSpec> {
4735                PadSfcCsnCtrlDs0W::new(self, 4)
4736            }
4737            #[doc = "Bit 5 - Drive strength bit 1"]
4738            #[inline(always)]
4739            pub fn pad_sfc_csn_ctrl_ds1(&mut self) -> PadSfcCsnCtrlDs1W<'_, PadSfcCsnCtrlSpec> {
4740                PadSfcCsnCtrlDs1W::new(self, 5)
4741            }
4742            #[doc = "Bit 6 - Drive strength bit 2"]
4743            #[inline(always)]
4744            pub fn pad_sfc_csn_ctrl_ds2(&mut self) -> PadSfcCsnCtrlDs2W<'_, PadSfcCsnCtrlSpec> {
4745                PadSfcCsnCtrlDs2W::new(self, 6)
4746            }
4747            #[doc = "Bit 9 - Pull enable"]
4748            #[inline(always)]
4749            pub fn pad_sfc_csn_ctrl_pe(&mut self) -> PadSfcCsnCtrlPeW<'_, PadSfcCsnCtrlSpec> {
4750                PadSfcCsnCtrlPeW::new(self, 9)
4751            }
4752            #[doc = "Bit 10 - Pull select"]
4753            #[inline(always)]
4754            pub fn pad_sfc_csn_ctrl_ps(&mut self) -> PadSfcCsnCtrlPsW<'_, PadSfcCsnCtrlSpec> {
4755                PadSfcCsnCtrlPsW::new(self, 10)
4756            }
4757            #[doc = "Bit 11 - Input enable"]
4758            #[inline(always)]
4759            pub fn pad_sfc_csn_ctrl_ie(&mut self) -> PadSfcCsnCtrlIeW<'_, PadSfcCsnCtrlSpec> {
4760                PadSfcCsnCtrlIeW::new(self, 11)
4761            }
4762        }
4763        #[doc = "SFC_CSN pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_csn_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_csn_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4764        pub struct PadSfcCsnCtrlSpec;
4765        impl crate::RegisterSpec for PadSfcCsnCtrlSpec {
4766            type Ux = u32;
4767        }
4768        #[doc = "`read()` method returns [`pad_sfc_csn_ctrl::R`](R) reader structure"]
4769        impl crate::Readable for PadSfcCsnCtrlSpec {}
4770        #[doc = "`write(|w| ..)` method takes [`pad_sfc_csn_ctrl::W`](W) writer structure"]
4771        impl crate::Writable for PadSfcCsnCtrlSpec {
4772            type Safety = crate::Unsafe;
4773        }
4774        #[doc = "`reset()` method sets PAD_SFC_CSN_CTRL to value 0x0e10"]
4775        impl crate::Resettable for PadSfcCsnCtrlSpec {
4776            const RESET_VALUE: u32 = 0x0e10;
4777        }
4778    }
4779    #[doc = "PAD_SFC_IO0_CTRL (rw) register accessor: SFC_IO0 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_io0_ctrl`] module"]
4780    #[doc(alias = "PAD_SFC_IO0_CTRL")]
4781    pub type PadSfcIo0Ctrl = crate::Reg<pad_sfc_io0_ctrl::PadSfcIo0CtrlSpec>;
4782    #[doc = "SFC_IO0 pad control register"]
4783    pub mod pad_sfc_io0_ctrl {
4784        #[doc = "Register `PAD_SFC_IO0_CTRL` reader"]
4785        pub type R = crate::R<PadSfcIo0CtrlSpec>;
4786        #[doc = "Register `PAD_SFC_IO0_CTRL` writer"]
4787        pub type W = crate::W<PadSfcIo0CtrlSpec>;
4788        #[doc = "Field `pad_sfc_io0_ctrl_st` reader - Schmitt trigger"]
4789        pub type PadSfcIo0CtrlStR = crate::BitReader;
4790        #[doc = "Field `pad_sfc_io0_ctrl_st` writer - Schmitt trigger"]
4791        pub type PadSfcIo0CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
4792        #[doc = "Field `pad_sfc_io0_ctrl_ds0` reader - Drive strength bit 0"]
4793        pub type PadSfcIo0CtrlDs0R = crate::BitReader;
4794        #[doc = "Field `pad_sfc_io0_ctrl_ds0` writer - Drive strength bit 0"]
4795        pub type PadSfcIo0CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
4796        #[doc = "Field `pad_sfc_io0_ctrl_ds1` reader - Drive strength bit 1"]
4797        pub type PadSfcIo0CtrlDs1R = crate::BitReader;
4798        #[doc = "Field `pad_sfc_io0_ctrl_ds1` writer - Drive strength bit 1"]
4799        pub type PadSfcIo0CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
4800        #[doc = "Field `pad_sfc_io0_ctrl_ds2` reader - Drive strength bit 2"]
4801        pub type PadSfcIo0CtrlDs2R = crate::BitReader;
4802        #[doc = "Field `pad_sfc_io0_ctrl_ds2` writer - Drive strength bit 2"]
4803        pub type PadSfcIo0CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
4804        #[doc = "Field `pad_sfc_io0_ctrl_pe` reader - Pull enable"]
4805        pub type PadSfcIo0CtrlPeR = crate::BitReader;
4806        #[doc = "Field `pad_sfc_io0_ctrl_pe` writer - Pull enable"]
4807        pub type PadSfcIo0CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
4808        #[doc = "Field `pad_sfc_io0_ctrl_ps` reader - Pull select"]
4809        pub type PadSfcIo0CtrlPsR = crate::BitReader;
4810        #[doc = "Field `pad_sfc_io0_ctrl_ps` writer - Pull select"]
4811        pub type PadSfcIo0CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
4812        #[doc = "Field `pad_sfc_io0_ctrl_ie` reader - Input enable"]
4813        pub type PadSfcIo0CtrlIeR = crate::BitReader;
4814        #[doc = "Field `pad_sfc_io0_ctrl_ie` writer - Input enable"]
4815        pub type PadSfcIo0CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
4816        impl R {
4817            #[doc = "Bit 3 - Schmitt trigger"]
4818            #[inline(always)]
4819            pub fn pad_sfc_io0_ctrl_st(&self) -> PadSfcIo0CtrlStR {
4820                PadSfcIo0CtrlStR::new(((self.bits >> 3) & 1) != 0)
4821            }
4822            #[doc = "Bit 4 - Drive strength bit 0"]
4823            #[inline(always)]
4824            pub fn pad_sfc_io0_ctrl_ds0(&self) -> PadSfcIo0CtrlDs0R {
4825                PadSfcIo0CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
4826            }
4827            #[doc = "Bit 5 - Drive strength bit 1"]
4828            #[inline(always)]
4829            pub fn pad_sfc_io0_ctrl_ds1(&self) -> PadSfcIo0CtrlDs1R {
4830                PadSfcIo0CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
4831            }
4832            #[doc = "Bit 6 - Drive strength bit 2"]
4833            #[inline(always)]
4834            pub fn pad_sfc_io0_ctrl_ds2(&self) -> PadSfcIo0CtrlDs2R {
4835                PadSfcIo0CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
4836            }
4837            #[doc = "Bit 9 - Pull enable"]
4838            #[inline(always)]
4839            pub fn pad_sfc_io0_ctrl_pe(&self) -> PadSfcIo0CtrlPeR {
4840                PadSfcIo0CtrlPeR::new(((self.bits >> 9) & 1) != 0)
4841            }
4842            #[doc = "Bit 10 - Pull select"]
4843            #[inline(always)]
4844            pub fn pad_sfc_io0_ctrl_ps(&self) -> PadSfcIo0CtrlPsR {
4845                PadSfcIo0CtrlPsR::new(((self.bits >> 10) & 1) != 0)
4846            }
4847            #[doc = "Bit 11 - Input enable"]
4848            #[inline(always)]
4849            pub fn pad_sfc_io0_ctrl_ie(&self) -> PadSfcIo0CtrlIeR {
4850                PadSfcIo0CtrlIeR::new(((self.bits >> 11) & 1) != 0)
4851            }
4852        }
4853        impl W {
4854            #[doc = "Bit 3 - Schmitt trigger"]
4855            #[inline(always)]
4856            pub fn pad_sfc_io0_ctrl_st(&mut self) -> PadSfcIo0CtrlStW<'_, PadSfcIo0CtrlSpec> {
4857                PadSfcIo0CtrlStW::new(self, 3)
4858            }
4859            #[doc = "Bit 4 - Drive strength bit 0"]
4860            #[inline(always)]
4861            pub fn pad_sfc_io0_ctrl_ds0(&mut self) -> PadSfcIo0CtrlDs0W<'_, PadSfcIo0CtrlSpec> {
4862                PadSfcIo0CtrlDs0W::new(self, 4)
4863            }
4864            #[doc = "Bit 5 - Drive strength bit 1"]
4865            #[inline(always)]
4866            pub fn pad_sfc_io0_ctrl_ds1(&mut self) -> PadSfcIo0CtrlDs1W<'_, PadSfcIo0CtrlSpec> {
4867                PadSfcIo0CtrlDs1W::new(self, 5)
4868            }
4869            #[doc = "Bit 6 - Drive strength bit 2"]
4870            #[inline(always)]
4871            pub fn pad_sfc_io0_ctrl_ds2(&mut self) -> PadSfcIo0CtrlDs2W<'_, PadSfcIo0CtrlSpec> {
4872                PadSfcIo0CtrlDs2W::new(self, 6)
4873            }
4874            #[doc = "Bit 9 - Pull enable"]
4875            #[inline(always)]
4876            pub fn pad_sfc_io0_ctrl_pe(&mut self) -> PadSfcIo0CtrlPeW<'_, PadSfcIo0CtrlSpec> {
4877                PadSfcIo0CtrlPeW::new(self, 9)
4878            }
4879            #[doc = "Bit 10 - Pull select"]
4880            #[inline(always)]
4881            pub fn pad_sfc_io0_ctrl_ps(&mut self) -> PadSfcIo0CtrlPsW<'_, PadSfcIo0CtrlSpec> {
4882                PadSfcIo0CtrlPsW::new(self, 10)
4883            }
4884            #[doc = "Bit 11 - Input enable"]
4885            #[inline(always)]
4886            pub fn pad_sfc_io0_ctrl_ie(&mut self) -> PadSfcIo0CtrlIeW<'_, PadSfcIo0CtrlSpec> {
4887                PadSfcIo0CtrlIeW::new(self, 11)
4888            }
4889        }
4890        #[doc = "SFC_IO0 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4891        pub struct PadSfcIo0CtrlSpec;
4892        impl crate::RegisterSpec for PadSfcIo0CtrlSpec {
4893            type Ux = u32;
4894        }
4895        #[doc = "`read()` method returns [`pad_sfc_io0_ctrl::R`](R) reader structure"]
4896        impl crate::Readable for PadSfcIo0CtrlSpec {}
4897        #[doc = "`write(|w| ..)` method takes [`pad_sfc_io0_ctrl::W`](W) writer structure"]
4898        impl crate::Writable for PadSfcIo0CtrlSpec {
4899            type Safety = crate::Unsafe;
4900        }
4901        #[doc = "`reset()` method sets PAD_SFC_IO0_CTRL to value 0x0e10"]
4902        impl crate::Resettable for PadSfcIo0CtrlSpec {
4903            const RESET_VALUE: u32 = 0x0e10;
4904        }
4905    }
4906    #[doc = "PAD_SFC_IO1_CTRL (rw) register accessor: SFC_IO1 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io1_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io1_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_io1_ctrl`] module"]
4907    #[doc(alias = "PAD_SFC_IO1_CTRL")]
4908    pub type PadSfcIo1Ctrl = crate::Reg<pad_sfc_io1_ctrl::PadSfcIo1CtrlSpec>;
4909    #[doc = "SFC_IO1 pad control register"]
4910    pub mod pad_sfc_io1_ctrl {
4911        #[doc = "Register `PAD_SFC_IO1_CTRL` reader"]
4912        pub type R = crate::R<PadSfcIo1CtrlSpec>;
4913        #[doc = "Register `PAD_SFC_IO1_CTRL` writer"]
4914        pub type W = crate::W<PadSfcIo1CtrlSpec>;
4915        #[doc = "Field `pad_sfc_io1_ctrl_st` reader - Schmitt trigger"]
4916        pub type PadSfcIo1CtrlStR = crate::BitReader;
4917        #[doc = "Field `pad_sfc_io1_ctrl_st` writer - Schmitt trigger"]
4918        pub type PadSfcIo1CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
4919        #[doc = "Field `pad_sfc_io1_ctrl_ds0` reader - Drive strength bit 0"]
4920        pub type PadSfcIo1CtrlDs0R = crate::BitReader;
4921        #[doc = "Field `pad_sfc_io1_ctrl_ds0` writer - Drive strength bit 0"]
4922        pub type PadSfcIo1CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
4923        #[doc = "Field `pad_sfc_io1_ctrl_ds1` reader - Drive strength bit 1"]
4924        pub type PadSfcIo1CtrlDs1R = crate::BitReader;
4925        #[doc = "Field `pad_sfc_io1_ctrl_ds1` writer - Drive strength bit 1"]
4926        pub type PadSfcIo1CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
4927        #[doc = "Field `pad_sfc_io1_ctrl_ds2` reader - Drive strength bit 2"]
4928        pub type PadSfcIo1CtrlDs2R = crate::BitReader;
4929        #[doc = "Field `pad_sfc_io1_ctrl_ds2` writer - Drive strength bit 2"]
4930        pub type PadSfcIo1CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
4931        #[doc = "Field `pad_sfc_io1_ctrl_pe` reader - Pull enable"]
4932        pub type PadSfcIo1CtrlPeR = crate::BitReader;
4933        #[doc = "Field `pad_sfc_io1_ctrl_pe` writer - Pull enable"]
4934        pub type PadSfcIo1CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
4935        #[doc = "Field `pad_sfc_io1_ctrl_ps` reader - Pull select"]
4936        pub type PadSfcIo1CtrlPsR = crate::BitReader;
4937        #[doc = "Field `pad_sfc_io1_ctrl_ps` writer - Pull select"]
4938        pub type PadSfcIo1CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
4939        #[doc = "Field `pad_sfc_io1_ctrl_ie` reader - Input enable"]
4940        pub type PadSfcIo1CtrlIeR = crate::BitReader;
4941        #[doc = "Field `pad_sfc_io1_ctrl_ie` writer - Input enable"]
4942        pub type PadSfcIo1CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
4943        impl R {
4944            #[doc = "Bit 3 - Schmitt trigger"]
4945            #[inline(always)]
4946            pub fn pad_sfc_io1_ctrl_st(&self) -> PadSfcIo1CtrlStR {
4947                PadSfcIo1CtrlStR::new(((self.bits >> 3) & 1) != 0)
4948            }
4949            #[doc = "Bit 4 - Drive strength bit 0"]
4950            #[inline(always)]
4951            pub fn pad_sfc_io1_ctrl_ds0(&self) -> PadSfcIo1CtrlDs0R {
4952                PadSfcIo1CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
4953            }
4954            #[doc = "Bit 5 - Drive strength bit 1"]
4955            #[inline(always)]
4956            pub fn pad_sfc_io1_ctrl_ds1(&self) -> PadSfcIo1CtrlDs1R {
4957                PadSfcIo1CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
4958            }
4959            #[doc = "Bit 6 - Drive strength bit 2"]
4960            #[inline(always)]
4961            pub fn pad_sfc_io1_ctrl_ds2(&self) -> PadSfcIo1CtrlDs2R {
4962                PadSfcIo1CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
4963            }
4964            #[doc = "Bit 9 - Pull enable"]
4965            #[inline(always)]
4966            pub fn pad_sfc_io1_ctrl_pe(&self) -> PadSfcIo1CtrlPeR {
4967                PadSfcIo1CtrlPeR::new(((self.bits >> 9) & 1) != 0)
4968            }
4969            #[doc = "Bit 10 - Pull select"]
4970            #[inline(always)]
4971            pub fn pad_sfc_io1_ctrl_ps(&self) -> PadSfcIo1CtrlPsR {
4972                PadSfcIo1CtrlPsR::new(((self.bits >> 10) & 1) != 0)
4973            }
4974            #[doc = "Bit 11 - Input enable"]
4975            #[inline(always)]
4976            pub fn pad_sfc_io1_ctrl_ie(&self) -> PadSfcIo1CtrlIeR {
4977                PadSfcIo1CtrlIeR::new(((self.bits >> 11) & 1) != 0)
4978            }
4979        }
4980        impl W {
4981            #[doc = "Bit 3 - Schmitt trigger"]
4982            #[inline(always)]
4983            pub fn pad_sfc_io1_ctrl_st(&mut self) -> PadSfcIo1CtrlStW<'_, PadSfcIo1CtrlSpec> {
4984                PadSfcIo1CtrlStW::new(self, 3)
4985            }
4986            #[doc = "Bit 4 - Drive strength bit 0"]
4987            #[inline(always)]
4988            pub fn pad_sfc_io1_ctrl_ds0(&mut self) -> PadSfcIo1CtrlDs0W<'_, PadSfcIo1CtrlSpec> {
4989                PadSfcIo1CtrlDs0W::new(self, 4)
4990            }
4991            #[doc = "Bit 5 - Drive strength bit 1"]
4992            #[inline(always)]
4993            pub fn pad_sfc_io1_ctrl_ds1(&mut self) -> PadSfcIo1CtrlDs1W<'_, PadSfcIo1CtrlSpec> {
4994                PadSfcIo1CtrlDs1W::new(self, 5)
4995            }
4996            #[doc = "Bit 6 - Drive strength bit 2"]
4997            #[inline(always)]
4998            pub fn pad_sfc_io1_ctrl_ds2(&mut self) -> PadSfcIo1CtrlDs2W<'_, PadSfcIo1CtrlSpec> {
4999                PadSfcIo1CtrlDs2W::new(self, 6)
5000            }
5001            #[doc = "Bit 9 - Pull enable"]
5002            #[inline(always)]
5003            pub fn pad_sfc_io1_ctrl_pe(&mut self) -> PadSfcIo1CtrlPeW<'_, PadSfcIo1CtrlSpec> {
5004                PadSfcIo1CtrlPeW::new(self, 9)
5005            }
5006            #[doc = "Bit 10 - Pull select"]
5007            #[inline(always)]
5008            pub fn pad_sfc_io1_ctrl_ps(&mut self) -> PadSfcIo1CtrlPsW<'_, PadSfcIo1CtrlSpec> {
5009                PadSfcIo1CtrlPsW::new(self, 10)
5010            }
5011            #[doc = "Bit 11 - Input enable"]
5012            #[inline(always)]
5013            pub fn pad_sfc_io1_ctrl_ie(&mut self) -> PadSfcIo1CtrlIeW<'_, PadSfcIo1CtrlSpec> {
5014                PadSfcIo1CtrlIeW::new(self, 11)
5015            }
5016        }
5017        #[doc = "SFC_IO1 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5018        pub struct PadSfcIo1CtrlSpec;
5019        impl crate::RegisterSpec for PadSfcIo1CtrlSpec {
5020            type Ux = u32;
5021        }
5022        #[doc = "`read()` method returns [`pad_sfc_io1_ctrl::R`](R) reader structure"]
5023        impl crate::Readable for PadSfcIo1CtrlSpec {}
5024        #[doc = "`write(|w| ..)` method takes [`pad_sfc_io1_ctrl::W`](W) writer structure"]
5025        impl crate::Writable for PadSfcIo1CtrlSpec {
5026            type Safety = crate::Unsafe;
5027        }
5028        #[doc = "`reset()` method sets PAD_SFC_IO1_CTRL to value 0x0e10"]
5029        impl crate::Resettable for PadSfcIo1CtrlSpec {
5030            const RESET_VALUE: u32 = 0x0e10;
5031        }
5032    }
5033    #[doc = "PAD_SFC_IO2_CTRL (rw) register accessor: SFC_IO2 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io2_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io2_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_io2_ctrl`] module"]
5034    #[doc(alias = "PAD_SFC_IO2_CTRL")]
5035    pub type PadSfcIo2Ctrl = crate::Reg<pad_sfc_io2_ctrl::PadSfcIo2CtrlSpec>;
5036    #[doc = "SFC_IO2 pad control register"]
5037    pub mod pad_sfc_io2_ctrl {
5038        #[doc = "Register `PAD_SFC_IO2_CTRL` reader"]
5039        pub type R = crate::R<PadSfcIo2CtrlSpec>;
5040        #[doc = "Register `PAD_SFC_IO2_CTRL` writer"]
5041        pub type W = crate::W<PadSfcIo2CtrlSpec>;
5042        #[doc = "Field `pad_sfc_io2_ctrl_st` reader - Schmitt trigger"]
5043        pub type PadSfcIo2CtrlStR = crate::BitReader;
5044        #[doc = "Field `pad_sfc_io2_ctrl_st` writer - Schmitt trigger"]
5045        pub type PadSfcIo2CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
5046        #[doc = "Field `pad_sfc_io2_ctrl_ds0` reader - Drive strength bit 0"]
5047        pub type PadSfcIo2CtrlDs0R = crate::BitReader;
5048        #[doc = "Field `pad_sfc_io2_ctrl_ds0` writer - Drive strength bit 0"]
5049        pub type PadSfcIo2CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
5050        #[doc = "Field `pad_sfc_io2_ctrl_ds1` reader - Drive strength bit 1"]
5051        pub type PadSfcIo2CtrlDs1R = crate::BitReader;
5052        #[doc = "Field `pad_sfc_io2_ctrl_ds1` writer - Drive strength bit 1"]
5053        pub type PadSfcIo2CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
5054        #[doc = "Field `pad_sfc_io2_ctrl_ds2` reader - Drive strength bit 2"]
5055        pub type PadSfcIo2CtrlDs2R = crate::BitReader;
5056        #[doc = "Field `pad_sfc_io2_ctrl_ds2` writer - Drive strength bit 2"]
5057        pub type PadSfcIo2CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
5058        #[doc = "Field `pad_sfc_io2_ctrl_pe` reader - Pull enable"]
5059        pub type PadSfcIo2CtrlPeR = crate::BitReader;
5060        #[doc = "Field `pad_sfc_io2_ctrl_pe` writer - Pull enable"]
5061        pub type PadSfcIo2CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
5062        #[doc = "Field `pad_sfc_io2_ctrl_ps` reader - Pull select"]
5063        pub type PadSfcIo2CtrlPsR = crate::BitReader;
5064        #[doc = "Field `pad_sfc_io2_ctrl_ps` writer - Pull select"]
5065        pub type PadSfcIo2CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
5066        #[doc = "Field `pad_sfc_io2_ctrl_ie` reader - Input enable"]
5067        pub type PadSfcIo2CtrlIeR = crate::BitReader;
5068        #[doc = "Field `pad_sfc_io2_ctrl_ie` writer - Input enable"]
5069        pub type PadSfcIo2CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
5070        impl R {
5071            #[doc = "Bit 3 - Schmitt trigger"]
5072            #[inline(always)]
5073            pub fn pad_sfc_io2_ctrl_st(&self) -> PadSfcIo2CtrlStR {
5074                PadSfcIo2CtrlStR::new(((self.bits >> 3) & 1) != 0)
5075            }
5076            #[doc = "Bit 4 - Drive strength bit 0"]
5077            #[inline(always)]
5078            pub fn pad_sfc_io2_ctrl_ds0(&self) -> PadSfcIo2CtrlDs0R {
5079                PadSfcIo2CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
5080            }
5081            #[doc = "Bit 5 - Drive strength bit 1"]
5082            #[inline(always)]
5083            pub fn pad_sfc_io2_ctrl_ds1(&self) -> PadSfcIo2CtrlDs1R {
5084                PadSfcIo2CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
5085            }
5086            #[doc = "Bit 6 - Drive strength bit 2"]
5087            #[inline(always)]
5088            pub fn pad_sfc_io2_ctrl_ds2(&self) -> PadSfcIo2CtrlDs2R {
5089                PadSfcIo2CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
5090            }
5091            #[doc = "Bit 9 - Pull enable"]
5092            #[inline(always)]
5093            pub fn pad_sfc_io2_ctrl_pe(&self) -> PadSfcIo2CtrlPeR {
5094                PadSfcIo2CtrlPeR::new(((self.bits >> 9) & 1) != 0)
5095            }
5096            #[doc = "Bit 10 - Pull select"]
5097            #[inline(always)]
5098            pub fn pad_sfc_io2_ctrl_ps(&self) -> PadSfcIo2CtrlPsR {
5099                PadSfcIo2CtrlPsR::new(((self.bits >> 10) & 1) != 0)
5100            }
5101            #[doc = "Bit 11 - Input enable"]
5102            #[inline(always)]
5103            pub fn pad_sfc_io2_ctrl_ie(&self) -> PadSfcIo2CtrlIeR {
5104                PadSfcIo2CtrlIeR::new(((self.bits >> 11) & 1) != 0)
5105            }
5106        }
5107        impl W {
5108            #[doc = "Bit 3 - Schmitt trigger"]
5109            #[inline(always)]
5110            pub fn pad_sfc_io2_ctrl_st(&mut self) -> PadSfcIo2CtrlStW<'_, PadSfcIo2CtrlSpec> {
5111                PadSfcIo2CtrlStW::new(self, 3)
5112            }
5113            #[doc = "Bit 4 - Drive strength bit 0"]
5114            #[inline(always)]
5115            pub fn pad_sfc_io2_ctrl_ds0(&mut self) -> PadSfcIo2CtrlDs0W<'_, PadSfcIo2CtrlSpec> {
5116                PadSfcIo2CtrlDs0W::new(self, 4)
5117            }
5118            #[doc = "Bit 5 - Drive strength bit 1"]
5119            #[inline(always)]
5120            pub fn pad_sfc_io2_ctrl_ds1(&mut self) -> PadSfcIo2CtrlDs1W<'_, PadSfcIo2CtrlSpec> {
5121                PadSfcIo2CtrlDs1W::new(self, 5)
5122            }
5123            #[doc = "Bit 6 - Drive strength bit 2"]
5124            #[inline(always)]
5125            pub fn pad_sfc_io2_ctrl_ds2(&mut self) -> PadSfcIo2CtrlDs2W<'_, PadSfcIo2CtrlSpec> {
5126                PadSfcIo2CtrlDs2W::new(self, 6)
5127            }
5128            #[doc = "Bit 9 - Pull enable"]
5129            #[inline(always)]
5130            pub fn pad_sfc_io2_ctrl_pe(&mut self) -> PadSfcIo2CtrlPeW<'_, PadSfcIo2CtrlSpec> {
5131                PadSfcIo2CtrlPeW::new(self, 9)
5132            }
5133            #[doc = "Bit 10 - Pull select"]
5134            #[inline(always)]
5135            pub fn pad_sfc_io2_ctrl_ps(&mut self) -> PadSfcIo2CtrlPsW<'_, PadSfcIo2CtrlSpec> {
5136                PadSfcIo2CtrlPsW::new(self, 10)
5137            }
5138            #[doc = "Bit 11 - Input enable"]
5139            #[inline(always)]
5140            pub fn pad_sfc_io2_ctrl_ie(&mut self) -> PadSfcIo2CtrlIeW<'_, PadSfcIo2CtrlSpec> {
5141                PadSfcIo2CtrlIeW::new(self, 11)
5142            }
5143        }
5144        #[doc = "SFC_IO2 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5145        pub struct PadSfcIo2CtrlSpec;
5146        impl crate::RegisterSpec for PadSfcIo2CtrlSpec {
5147            type Ux = u32;
5148        }
5149        #[doc = "`read()` method returns [`pad_sfc_io2_ctrl::R`](R) reader structure"]
5150        impl crate::Readable for PadSfcIo2CtrlSpec {}
5151        #[doc = "`write(|w| ..)` method takes [`pad_sfc_io2_ctrl::W`](W) writer structure"]
5152        impl crate::Writable for PadSfcIo2CtrlSpec {
5153            type Safety = crate::Unsafe;
5154        }
5155        #[doc = "`reset()` method sets PAD_SFC_IO2_CTRL to value 0x0e10"]
5156        impl crate::Resettable for PadSfcIo2CtrlSpec {
5157            const RESET_VALUE: u32 = 0x0e10;
5158        }
5159    }
5160    #[doc = "PAD_SFC_IO3_CTRL (rw) register accessor: SFC_IO3 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io3_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io3_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_io3_ctrl`] module"]
5161    #[doc(alias = "PAD_SFC_IO3_CTRL")]
5162    pub type PadSfcIo3Ctrl = crate::Reg<pad_sfc_io3_ctrl::PadSfcIo3CtrlSpec>;
5163    #[doc = "SFC_IO3 pad control register"]
5164    pub mod pad_sfc_io3_ctrl {
5165        #[doc = "Register `PAD_SFC_IO3_CTRL` reader"]
5166        pub type R = crate::R<PadSfcIo3CtrlSpec>;
5167        #[doc = "Register `PAD_SFC_IO3_CTRL` writer"]
5168        pub type W = crate::W<PadSfcIo3CtrlSpec>;
5169        #[doc = "Field `pad_sfc_io3_ctrl_st` reader - Schmitt trigger"]
5170        pub type PadSfcIo3CtrlStR = crate::BitReader;
5171        #[doc = "Field `pad_sfc_io3_ctrl_st` writer - Schmitt trigger"]
5172        pub type PadSfcIo3CtrlStW<'a, REG> = crate::BitWriter<'a, REG>;
5173        #[doc = "Field `pad_sfc_io3_ctrl_ds0` reader - Drive strength bit 0"]
5174        pub type PadSfcIo3CtrlDs0R = crate::BitReader;
5175        #[doc = "Field `pad_sfc_io3_ctrl_ds0` writer - Drive strength bit 0"]
5176        pub type PadSfcIo3CtrlDs0W<'a, REG> = crate::BitWriter<'a, REG>;
5177        #[doc = "Field `pad_sfc_io3_ctrl_ds1` reader - Drive strength bit 1"]
5178        pub type PadSfcIo3CtrlDs1R = crate::BitReader;
5179        #[doc = "Field `pad_sfc_io3_ctrl_ds1` writer - Drive strength bit 1"]
5180        pub type PadSfcIo3CtrlDs1W<'a, REG> = crate::BitWriter<'a, REG>;
5181        #[doc = "Field `pad_sfc_io3_ctrl_ds2` reader - Drive strength bit 2"]
5182        pub type PadSfcIo3CtrlDs2R = crate::BitReader;
5183        #[doc = "Field `pad_sfc_io3_ctrl_ds2` writer - Drive strength bit 2"]
5184        pub type PadSfcIo3CtrlDs2W<'a, REG> = crate::BitWriter<'a, REG>;
5185        #[doc = "Field `pad_sfc_io3_ctrl_pe` reader - Pull enable"]
5186        pub type PadSfcIo3CtrlPeR = crate::BitReader;
5187        #[doc = "Field `pad_sfc_io3_ctrl_pe` writer - Pull enable"]
5188        pub type PadSfcIo3CtrlPeW<'a, REG> = crate::BitWriter<'a, REG>;
5189        #[doc = "Field `pad_sfc_io3_ctrl_ps` reader - Pull select"]
5190        pub type PadSfcIo3CtrlPsR = crate::BitReader;
5191        #[doc = "Field `pad_sfc_io3_ctrl_ps` writer - Pull select"]
5192        pub type PadSfcIo3CtrlPsW<'a, REG> = crate::BitWriter<'a, REG>;
5193        #[doc = "Field `pad_sfc_io3_ctrl_ie` reader - Input enable"]
5194        pub type PadSfcIo3CtrlIeR = crate::BitReader;
5195        #[doc = "Field `pad_sfc_io3_ctrl_ie` writer - Input enable"]
5196        pub type PadSfcIo3CtrlIeW<'a, REG> = crate::BitWriter<'a, REG>;
5197        impl R {
5198            #[doc = "Bit 3 - Schmitt trigger"]
5199            #[inline(always)]
5200            pub fn pad_sfc_io3_ctrl_st(&self) -> PadSfcIo3CtrlStR {
5201                PadSfcIo3CtrlStR::new(((self.bits >> 3) & 1) != 0)
5202            }
5203            #[doc = "Bit 4 - Drive strength bit 0"]
5204            #[inline(always)]
5205            pub fn pad_sfc_io3_ctrl_ds0(&self) -> PadSfcIo3CtrlDs0R {
5206                PadSfcIo3CtrlDs0R::new(((self.bits >> 4) & 1) != 0)
5207            }
5208            #[doc = "Bit 5 - Drive strength bit 1"]
5209            #[inline(always)]
5210            pub fn pad_sfc_io3_ctrl_ds1(&self) -> PadSfcIo3CtrlDs1R {
5211                PadSfcIo3CtrlDs1R::new(((self.bits >> 5) & 1) != 0)
5212            }
5213            #[doc = "Bit 6 - Drive strength bit 2"]
5214            #[inline(always)]
5215            pub fn pad_sfc_io3_ctrl_ds2(&self) -> PadSfcIo3CtrlDs2R {
5216                PadSfcIo3CtrlDs2R::new(((self.bits >> 6) & 1) != 0)
5217            }
5218            #[doc = "Bit 9 - Pull enable"]
5219            #[inline(always)]
5220            pub fn pad_sfc_io3_ctrl_pe(&self) -> PadSfcIo3CtrlPeR {
5221                PadSfcIo3CtrlPeR::new(((self.bits >> 9) & 1) != 0)
5222            }
5223            #[doc = "Bit 10 - Pull select"]
5224            #[inline(always)]
5225            pub fn pad_sfc_io3_ctrl_ps(&self) -> PadSfcIo3CtrlPsR {
5226                PadSfcIo3CtrlPsR::new(((self.bits >> 10) & 1) != 0)
5227            }
5228            #[doc = "Bit 11 - Input enable"]
5229            #[inline(always)]
5230            pub fn pad_sfc_io3_ctrl_ie(&self) -> PadSfcIo3CtrlIeR {
5231                PadSfcIo3CtrlIeR::new(((self.bits >> 11) & 1) != 0)
5232            }
5233        }
5234        impl W {
5235            #[doc = "Bit 3 - Schmitt trigger"]
5236            #[inline(always)]
5237            pub fn pad_sfc_io3_ctrl_st(&mut self) -> PadSfcIo3CtrlStW<'_, PadSfcIo3CtrlSpec> {
5238                PadSfcIo3CtrlStW::new(self, 3)
5239            }
5240            #[doc = "Bit 4 - Drive strength bit 0"]
5241            #[inline(always)]
5242            pub fn pad_sfc_io3_ctrl_ds0(&mut self) -> PadSfcIo3CtrlDs0W<'_, PadSfcIo3CtrlSpec> {
5243                PadSfcIo3CtrlDs0W::new(self, 4)
5244            }
5245            #[doc = "Bit 5 - Drive strength bit 1"]
5246            #[inline(always)]
5247            pub fn pad_sfc_io3_ctrl_ds1(&mut self) -> PadSfcIo3CtrlDs1W<'_, PadSfcIo3CtrlSpec> {
5248                PadSfcIo3CtrlDs1W::new(self, 5)
5249            }
5250            #[doc = "Bit 6 - Drive strength bit 2"]
5251            #[inline(always)]
5252            pub fn pad_sfc_io3_ctrl_ds2(&mut self) -> PadSfcIo3CtrlDs2W<'_, PadSfcIo3CtrlSpec> {
5253                PadSfcIo3CtrlDs2W::new(self, 6)
5254            }
5255            #[doc = "Bit 9 - Pull enable"]
5256            #[inline(always)]
5257            pub fn pad_sfc_io3_ctrl_pe(&mut self) -> PadSfcIo3CtrlPeW<'_, PadSfcIo3CtrlSpec> {
5258                PadSfcIo3CtrlPeW::new(self, 9)
5259            }
5260            #[doc = "Bit 10 - Pull select"]
5261            #[inline(always)]
5262            pub fn pad_sfc_io3_ctrl_ps(&mut self) -> PadSfcIo3CtrlPsW<'_, PadSfcIo3CtrlSpec> {
5263                PadSfcIo3CtrlPsW::new(self, 10)
5264            }
5265            #[doc = "Bit 11 - Input enable"]
5266            #[inline(always)]
5267            pub fn pad_sfc_io3_ctrl_ie(&mut self) -> PadSfcIo3CtrlIeW<'_, PadSfcIo3CtrlSpec> {
5268                PadSfcIo3CtrlIeW::new(self, 11)
5269            }
5270        }
5271        #[doc = "SFC_IO3 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io3_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io3_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5272        pub struct PadSfcIo3CtrlSpec;
5273        impl crate::RegisterSpec for PadSfcIo3CtrlSpec {
5274            type Ux = u32;
5275        }
5276        #[doc = "`read()` method returns [`pad_sfc_io3_ctrl::R`](R) reader structure"]
5277        impl crate::Readable for PadSfcIo3CtrlSpec {}
5278        #[doc = "`write(|w| ..)` method takes [`pad_sfc_io3_ctrl::W`](W) writer structure"]
5279        impl crate::Writable for PadSfcIo3CtrlSpec {
5280            type Safety = crate::Unsafe;
5281        }
5282        #[doc = "`reset()` method sets PAD_SFC_IO3_CTRL to value 0x0e10"]
5283        impl crate::Resettable for PadSfcIo3CtrlSpec {
5284            const RESET_VALUE: u32 = 0x0e10;
5285        }
5286    }
5287}
5288#[doc = "GPIO controller for GPIO\\[7:0\\]"]
5289pub type Gpio0 = crate::Periph<gpio0::RegisterBlock, 0x4402_8000>;
5290impl core::fmt::Debug for Gpio0 {
5291    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5292        f.debug_struct("Gpio0").finish()
5293    }
5294}
5295#[doc = "GPIO controller for GPIO\\[7:0\\]"]
5296pub mod gpio0 {
5297    #[repr(C)]
5298    #[doc = "Register block"]
5299    pub struct RegisterBlock {
5300        gpio_sw_out: GpioSwOut,
5301        gpio_sw_oen: GpioSwOen,
5302        _reserved2: [u8; 0x04],
5303        gpio_int_en: GpioIntEn,
5304        gpio_int_mask: GpioIntMask,
5305        gpio_int_type: GpioIntType,
5306        gpio_int_polarity: GpioIntPolarity,
5307        gpio_int_dedge: GpioIntDedge,
5308        gpio_int_debounce: GpioIntDebounce,
5309        gpio_int_raw: GpioIntRaw,
5310        gpio_intr: GpioIntr,
5311        gpio_int_eoi: GpioIntEoi,
5312        gpio_data_set: GpioDataSet,
5313        gpio_data_clr: GpioDataClr,
5314    }
5315    impl RegisterBlock {
5316        #[doc = "0x00 - GPIO data register"]
5317        #[inline(always)]
5318        pub const fn gpio_sw_out(&self) -> &GpioSwOut {
5319            &self.gpio_sw_out
5320        }
5321        #[doc = "0x04 - GPIO data direction register"]
5322        #[inline(always)]
5323        pub const fn gpio_sw_oen(&self) -> &GpioSwOen {
5324            &self.gpio_sw_oen
5325        }
5326        #[doc = "0x0c - GPIO interrupt enable register"]
5327        #[inline(always)]
5328        pub const fn gpio_int_en(&self) -> &GpioIntEn {
5329            &self.gpio_int_en
5330        }
5331        #[doc = "0x10 - GPIO interrupt mask register"]
5332        #[inline(always)]
5333        pub const fn gpio_int_mask(&self) -> &GpioIntMask {
5334            &self.gpio_int_mask
5335        }
5336        #[doc = "0x14 - GPIO interrupt type register"]
5337        #[inline(always)]
5338        pub const fn gpio_int_type(&self) -> &GpioIntType {
5339            &self.gpio_int_type
5340        }
5341        #[doc = "0x18 - GPIO interrupt polarity register"]
5342        #[inline(always)]
5343        pub const fn gpio_int_polarity(&self) -> &GpioIntPolarity {
5344            &self.gpio_int_polarity
5345        }
5346        #[doc = "0x1c - GPIO dual-edge interrupt enable register"]
5347        #[inline(always)]
5348        pub const fn gpio_int_dedge(&self) -> &GpioIntDedge {
5349            &self.gpio_int_dedge
5350        }
5351        #[doc = "0x20 - GPIO interrupt debounce control register"]
5352        #[inline(always)]
5353        pub const fn gpio_int_debounce(&self) -> &GpioIntDebounce {
5354            &self.gpio_int_debounce
5355        }
5356        #[doc = "0x24 - GPIO raw interrupt status register"]
5357        #[inline(always)]
5358        pub const fn gpio_int_raw(&self) -> &GpioIntRaw {
5359            &self.gpio_int_raw
5360        }
5361        #[doc = "0x28 - GPIO interrupt status register"]
5362        #[inline(always)]
5363        pub const fn gpio_intr(&self) -> &GpioIntr {
5364            &self.gpio_intr
5365        }
5366        #[doc = "0x2c - GPIO interrupt clear register"]
5367        #[inline(always)]
5368        pub const fn gpio_int_eoi(&self) -> &GpioIntEoi {
5369            &self.gpio_int_eoi
5370        }
5371        #[doc = "0x30 - GPIO data set register"]
5372        #[inline(always)]
5373        pub const fn gpio_data_set(&self) -> &GpioDataSet {
5374            &self.gpio_data_set
5375        }
5376        #[doc = "0x34 - GPIO data clear register"]
5377        #[inline(always)]
5378        pub const fn gpio_data_clr(&self) -> &GpioDataClr {
5379            &self.gpio_data_clr
5380        }
5381    }
5382    #[doc = "GPIO_SW_OUT (rw) register accessor: GPIO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_sw_out`] module"]
5383    #[doc(alias = "GPIO_SW_OUT")]
5384    pub type GpioSwOut = crate::Reg<gpio_sw_out::GpioSwOutSpec>;
5385    #[doc = "GPIO data register"]
5386    pub mod gpio_sw_out {
5387        #[doc = "Register `GPIO_SW_OUT` reader"]
5388        pub type R = crate::R<GpioSwOutSpec>;
5389        #[doc = "Register `GPIO_SW_OUT` writer"]
5390        pub type W = crate::W<GpioSwOutSpec>;
5391        #[doc = "Field `gpio_sw_out` reader - GPIO data. Output: written value drives I/O; Input: reads external port"]
5392        pub type GpioSwOutR = crate::FieldReader;
5393        #[doc = "Field `gpio_sw_out` writer - GPIO data. Output: written value drives I/O; Input: reads external port"]
5394        pub type GpioSwOutW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
5395        impl R {
5396            #[doc = "Bits 0:7 - GPIO data. Output: written value drives I/O; Input: reads external port"]
5397            #[inline(always)]
5398            pub fn gpio_sw_out(&self) -> GpioSwOutR {
5399                GpioSwOutR::new((self.bits & 0xff) as u8)
5400            }
5401        }
5402        impl W {
5403            #[doc = "Bits 0:7 - GPIO data. Output: written value drives I/O; Input: reads external port"]
5404            #[inline(always)]
5405            pub fn gpio_sw_out(&mut self) -> GpioSwOutW<'_, GpioSwOutSpec> {
5406                GpioSwOutW::new(self, 0)
5407            }
5408        }
5409        #[doc = "GPIO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5410        pub struct GpioSwOutSpec;
5411        impl crate::RegisterSpec for GpioSwOutSpec {
5412            type Ux = u32;
5413        }
5414        #[doc = "`read()` method returns [`gpio_sw_out::R`](R) reader structure"]
5415        impl crate::Readable for GpioSwOutSpec {}
5416        #[doc = "`write(|w| ..)` method takes [`gpio_sw_out::W`](W) writer structure"]
5417        impl crate::Writable for GpioSwOutSpec {
5418            type Safety = crate::Unsafe;
5419        }
5420        #[doc = "`reset()` method sets GPIO_SW_OUT to value 0"]
5421        impl crate::Resettable for GpioSwOutSpec {}
5422    }
5423    #[doc = "GPIO_SW_OEN (rw) register accessor: GPIO data direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_oen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_oen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_sw_oen`] module"]
5424    #[doc(alias = "GPIO_SW_OEN")]
5425    pub type GpioSwOen = crate::Reg<gpio_sw_oen::GpioSwOenSpec>;
5426    #[doc = "GPIO data direction register"]
5427    pub mod gpio_sw_oen {
5428        #[doc = "Register `GPIO_SW_OEN` reader"]
5429        pub type R = crate::R<GpioSwOenSpec>;
5430        #[doc = "Register `GPIO_SW_OEN` writer"]
5431        pub type W = crate::W<GpioSwOenSpec>;
5432        #[doc = "GPIO direction: 0=output; 1=input (default)\n\nValue on reset: 255"]
5433        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
5434        #[repr(u8)]
5435        pub enum GpioSwOen {
5436            #[doc = "0: Output direction"]
5437            Output = 0,
5438            #[doc = "1: Input direction"]
5439            Input = 1,
5440        }
5441        impl From<GpioSwOen> for u8 {
5442            #[inline(always)]
5443            fn from(variant: GpioSwOen) -> Self {
5444                variant as _
5445            }
5446        }
5447        impl crate::FieldSpec for GpioSwOen {
5448            type Ux = u8;
5449        }
5450        impl crate::IsEnum for GpioSwOen {}
5451        #[doc = "Field `gpio_sw_oen` reader - GPIO direction: 0=output; 1=input (default)"]
5452        pub type GpioSwOenR = crate::FieldReader<GpioSwOen>;
5453        impl GpioSwOenR {
5454            #[doc = "Get enumerated values variant"]
5455            #[inline(always)]
5456            pub const fn variant(&self) -> Option<GpioSwOen> {
5457                match self.bits {
5458                    0 => Some(GpioSwOen::Output),
5459                    1 => Some(GpioSwOen::Input),
5460                    _ => None,
5461                }
5462            }
5463            #[doc = "Output direction"]
5464            #[inline(always)]
5465            pub fn is_output(&self) -> bool {
5466                *self == GpioSwOen::Output
5467            }
5468            #[doc = "Input direction"]
5469            #[inline(always)]
5470            pub fn is_input(&self) -> bool {
5471                *self == GpioSwOen::Input
5472            }
5473        }
5474        #[doc = "Field `gpio_sw_oen` writer - GPIO direction: 0=output; 1=input (default)"]
5475        pub type GpioSwOenW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioSwOen>;
5476        impl<'a, REG> GpioSwOenW<'a, REG>
5477        where
5478            REG: crate::Writable + crate::RegisterSpec,
5479            REG::Ux: From<u8>,
5480        {
5481            #[doc = "Output direction"]
5482            #[inline(always)]
5483            pub fn output(self) -> &'a mut crate::W<REG> {
5484                self.variant(GpioSwOen::Output)
5485            }
5486            #[doc = "Input direction"]
5487            #[inline(always)]
5488            pub fn input(self) -> &'a mut crate::W<REG> {
5489                self.variant(GpioSwOen::Input)
5490            }
5491        }
5492        impl R {
5493            #[doc = "Bits 0:7 - GPIO direction: 0=output; 1=input (default)"]
5494            #[inline(always)]
5495            pub fn gpio_sw_oen(&self) -> GpioSwOenR {
5496                GpioSwOenR::new((self.bits & 0xff) as u8)
5497            }
5498        }
5499        impl W {
5500            #[doc = "Bits 0:7 - GPIO direction: 0=output; 1=input (default)"]
5501            #[inline(always)]
5502            pub fn gpio_sw_oen(&mut self) -> GpioSwOenW<'_, GpioSwOenSpec> {
5503                GpioSwOenW::new(self, 0)
5504            }
5505        }
5506        #[doc = "GPIO data direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_oen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_oen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5507        pub struct GpioSwOenSpec;
5508        impl crate::RegisterSpec for GpioSwOenSpec {
5509            type Ux = u32;
5510        }
5511        #[doc = "`read()` method returns [`gpio_sw_oen::R`](R) reader structure"]
5512        impl crate::Readable for GpioSwOenSpec {}
5513        #[doc = "`write(|w| ..)` method takes [`gpio_sw_oen::W`](W) writer structure"]
5514        impl crate::Writable for GpioSwOenSpec {
5515            type Safety = crate::Unsafe;
5516        }
5517        #[doc = "`reset()` method sets GPIO_SW_OEN to value 0xff"]
5518        impl crate::Resettable for GpioSwOenSpec {
5519            const RESET_VALUE: u32 = 0xff;
5520        }
5521    }
5522    #[doc = "GPIO_INT_EN (rw) register accessor: GPIO interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_en`] module"]
5523    #[doc(alias = "GPIO_INT_EN")]
5524    pub type GpioIntEn = crate::Reg<gpio_int_en::GpioIntEnSpec>;
5525    #[doc = "GPIO interrupt enable register"]
5526    pub mod gpio_int_en {
5527        #[doc = "Register `GPIO_INT_EN` reader"]
5528        pub type R = crate::R<GpioIntEnSpec>;
5529        #[doc = "Register `GPIO_INT_EN` writer"]
5530        pub type W = crate::W<GpioIntEnSpec>;
5531        #[doc = "Field `gpio_int_en` reader - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
5532        pub type GpioIntEnR = crate::FieldReader;
5533        #[doc = "Field `gpio_int_en` writer - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
5534        pub type GpioIntEnW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
5535        impl R {
5536            #[doc = "Bits 0:7 - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
5537            #[inline(always)]
5538            pub fn gpio_int_en(&self) -> GpioIntEnR {
5539                GpioIntEnR::new((self.bits & 0xff) as u8)
5540            }
5541        }
5542        impl W {
5543            #[doc = "Bits 0:7 - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
5544            #[inline(always)]
5545            pub fn gpio_int_en(&mut self) -> GpioIntEnW<'_, GpioIntEnSpec> {
5546                GpioIntEnW::new(self, 0)
5547            }
5548        }
5549        #[doc = "GPIO interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5550        pub struct GpioIntEnSpec;
5551        impl crate::RegisterSpec for GpioIntEnSpec {
5552            type Ux = u32;
5553        }
5554        #[doc = "`read()` method returns [`gpio_int_en::R`](R) reader structure"]
5555        impl crate::Readable for GpioIntEnSpec {}
5556        #[doc = "`write(|w| ..)` method takes [`gpio_int_en::W`](W) writer structure"]
5557        impl crate::Writable for GpioIntEnSpec {
5558            type Safety = crate::Unsafe;
5559        }
5560        #[doc = "`reset()` method sets GPIO_INT_EN to value 0"]
5561        impl crate::Resettable for GpioIntEnSpec {}
5562    }
5563    #[doc = "GPIO_INT_MASK (rw) register accessor: GPIO interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_mask`] module"]
5564    #[doc(alias = "GPIO_INT_MASK")]
5565    pub type GpioIntMask = crate::Reg<gpio_int_mask::GpioIntMaskSpec>;
5566    #[doc = "GPIO interrupt mask register"]
5567    pub mod gpio_int_mask {
5568        #[doc = "Register `GPIO_INT_MASK` reader"]
5569        pub type R = crate::R<GpioIntMaskSpec>;
5570        #[doc = "Register `GPIO_INT_MASK` writer"]
5571        pub type W = crate::W<GpioIntMaskSpec>;
5572        #[doc = "Field `gpio_int_mask` reader - Interrupt mask: 0=not masked; 1=masked"]
5573        pub type GpioIntMaskR = crate::FieldReader;
5574        #[doc = "Field `gpio_int_mask` writer - Interrupt mask: 0=not masked; 1=masked"]
5575        pub type GpioIntMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
5576        impl R {
5577            #[doc = "Bits 0:7 - Interrupt mask: 0=not masked; 1=masked"]
5578            #[inline(always)]
5579            pub fn gpio_int_mask(&self) -> GpioIntMaskR {
5580                GpioIntMaskR::new((self.bits & 0xff) as u8)
5581            }
5582        }
5583        impl W {
5584            #[doc = "Bits 0:7 - Interrupt mask: 0=not masked; 1=masked"]
5585            #[inline(always)]
5586            pub fn gpio_int_mask(&mut self) -> GpioIntMaskW<'_, GpioIntMaskSpec> {
5587                GpioIntMaskW::new(self, 0)
5588            }
5589        }
5590        #[doc = "GPIO interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5591        pub struct GpioIntMaskSpec;
5592        impl crate::RegisterSpec for GpioIntMaskSpec {
5593            type Ux = u32;
5594        }
5595        #[doc = "`read()` method returns [`gpio_int_mask::R`](R) reader structure"]
5596        impl crate::Readable for GpioIntMaskSpec {}
5597        #[doc = "`write(|w| ..)` method takes [`gpio_int_mask::W`](W) writer structure"]
5598        impl crate::Writable for GpioIntMaskSpec {
5599            type Safety = crate::Unsafe;
5600        }
5601        #[doc = "`reset()` method sets GPIO_INT_MASK to value 0"]
5602        impl crate::Resettable for GpioIntMaskSpec {}
5603    }
5604    #[doc = "GPIO_INT_TYPE (rw) register accessor: GPIO interrupt type register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_type`] module"]
5605    #[doc(alias = "GPIO_INT_TYPE")]
5606    pub type GpioIntType = crate::Reg<gpio_int_type::GpioIntTypeSpec>;
5607    #[doc = "GPIO interrupt type register"]
5608    pub mod gpio_int_type {
5609        #[doc = "Register `GPIO_INT_TYPE` reader"]
5610        pub type R = crate::R<GpioIntTypeSpec>;
5611        #[doc = "Register `GPIO_INT_TYPE` writer"]
5612        pub type W = crate::W<GpioIntTypeSpec>;
5613        #[doc = "Interrupt type: 0=level; 1=edge\n\nValue on reset: 0"]
5614        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
5615        #[repr(u8)]
5616        pub enum GpioIntType {
5617            #[doc = "0: Level-sensitive"]
5618            Level = 0,
5619            #[doc = "1: Edge-triggered"]
5620            Edge = 1,
5621        }
5622        impl From<GpioIntType> for u8 {
5623            #[inline(always)]
5624            fn from(variant: GpioIntType) -> Self {
5625                variant as _
5626            }
5627        }
5628        impl crate::FieldSpec for GpioIntType {
5629            type Ux = u8;
5630        }
5631        impl crate::IsEnum for GpioIntType {}
5632        #[doc = "Field `gpio_int_type` reader - Interrupt type: 0=level; 1=edge"]
5633        pub type GpioIntTypeR = crate::FieldReader<GpioIntType>;
5634        impl GpioIntTypeR {
5635            #[doc = "Get enumerated values variant"]
5636            #[inline(always)]
5637            pub const fn variant(&self) -> Option<GpioIntType> {
5638                match self.bits {
5639                    0 => Some(GpioIntType::Level),
5640                    1 => Some(GpioIntType::Edge),
5641                    _ => None,
5642                }
5643            }
5644            #[doc = "Level-sensitive"]
5645            #[inline(always)]
5646            pub fn is_level(&self) -> bool {
5647                *self == GpioIntType::Level
5648            }
5649            #[doc = "Edge-triggered"]
5650            #[inline(always)]
5651            pub fn is_edge(&self) -> bool {
5652                *self == GpioIntType::Edge
5653            }
5654        }
5655        #[doc = "Field `gpio_int_type` writer - Interrupt type: 0=level; 1=edge"]
5656        pub type GpioIntTypeW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioIntType>;
5657        impl<'a, REG> GpioIntTypeW<'a, REG>
5658        where
5659            REG: crate::Writable + crate::RegisterSpec,
5660            REG::Ux: From<u8>,
5661        {
5662            #[doc = "Level-sensitive"]
5663            #[inline(always)]
5664            pub fn level(self) -> &'a mut crate::W<REG> {
5665                self.variant(GpioIntType::Level)
5666            }
5667            #[doc = "Edge-triggered"]
5668            #[inline(always)]
5669            pub fn edge(self) -> &'a mut crate::W<REG> {
5670                self.variant(GpioIntType::Edge)
5671            }
5672        }
5673        impl R {
5674            #[doc = "Bits 0:7 - Interrupt type: 0=level; 1=edge"]
5675            #[inline(always)]
5676            pub fn gpio_int_type(&self) -> GpioIntTypeR {
5677                GpioIntTypeR::new((self.bits & 0xff) as u8)
5678            }
5679        }
5680        impl W {
5681            #[doc = "Bits 0:7 - Interrupt type: 0=level; 1=edge"]
5682            #[inline(always)]
5683            pub fn gpio_int_type(&mut self) -> GpioIntTypeW<'_, GpioIntTypeSpec> {
5684                GpioIntTypeW::new(self, 0)
5685            }
5686        }
5687        #[doc = "GPIO interrupt type register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_type::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_type::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5688        pub struct GpioIntTypeSpec;
5689        impl crate::RegisterSpec for GpioIntTypeSpec {
5690            type Ux = u32;
5691        }
5692        #[doc = "`read()` method returns [`gpio_int_type::R`](R) reader structure"]
5693        impl crate::Readable for GpioIntTypeSpec {}
5694        #[doc = "`write(|w| ..)` method takes [`gpio_int_type::W`](W) writer structure"]
5695        impl crate::Writable for GpioIntTypeSpec {
5696            type Safety = crate::Unsafe;
5697        }
5698        #[doc = "`reset()` method sets GPIO_INT_TYPE to value 0"]
5699        impl crate::Resettable for GpioIntTypeSpec {}
5700    }
5701    #[doc = "GPIO_INT_POLARITY (rw) register accessor: GPIO interrupt polarity register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_polarity::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_polarity::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_polarity`] module"]
5702    #[doc(alias = "GPIO_INT_POLARITY")]
5703    pub type GpioIntPolarity = crate::Reg<gpio_int_polarity::GpioIntPolaritySpec>;
5704    #[doc = "GPIO interrupt polarity register"]
5705    pub mod gpio_int_polarity {
5706        #[doc = "Register `GPIO_INT_POLARITY` reader"]
5707        pub type R = crate::R<GpioIntPolaritySpec>;
5708        #[doc = "Register `GPIO_INT_POLARITY` writer"]
5709        pub type W = crate::W<GpioIntPolaritySpec>;
5710        #[doc = "Interrupt polarity: 0=low/falling; 1=high/rising\n\nValue on reset: 0"]
5711        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
5712        #[repr(u8)]
5713        pub enum GpioIntPolarity {
5714            #[doc = "0: Low level or falling edge"]
5715            LowFalling = 0,
5716            #[doc = "1: High level or rising edge"]
5717            HighRising = 1,
5718        }
5719        impl From<GpioIntPolarity> for u8 {
5720            #[inline(always)]
5721            fn from(variant: GpioIntPolarity) -> Self {
5722                variant as _
5723            }
5724        }
5725        impl crate::FieldSpec for GpioIntPolarity {
5726            type Ux = u8;
5727        }
5728        impl crate::IsEnum for GpioIntPolarity {}
5729        #[doc = "Field `gpio_int_polarity` reader - Interrupt polarity: 0=low/falling; 1=high/rising"]
5730        pub type GpioIntPolarityR = crate::FieldReader<GpioIntPolarity>;
5731        impl GpioIntPolarityR {
5732            #[doc = "Get enumerated values variant"]
5733            #[inline(always)]
5734            pub const fn variant(&self) -> Option<GpioIntPolarity> {
5735                match self.bits {
5736                    0 => Some(GpioIntPolarity::LowFalling),
5737                    1 => Some(GpioIntPolarity::HighRising),
5738                    _ => None,
5739                }
5740            }
5741            #[doc = "Low level or falling edge"]
5742            #[inline(always)]
5743            pub fn is_low_falling(&self) -> bool {
5744                *self == GpioIntPolarity::LowFalling
5745            }
5746            #[doc = "High level or rising edge"]
5747            #[inline(always)]
5748            pub fn is_high_rising(&self) -> bool {
5749                *self == GpioIntPolarity::HighRising
5750            }
5751        }
5752        #[doc = "Field `gpio_int_polarity` writer - Interrupt polarity: 0=low/falling; 1=high/rising"]
5753        pub type GpioIntPolarityW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioIntPolarity>;
5754        impl<'a, REG> GpioIntPolarityW<'a, REG>
5755        where
5756            REG: crate::Writable + crate::RegisterSpec,
5757            REG::Ux: From<u8>,
5758        {
5759            #[doc = "Low level or falling edge"]
5760            #[inline(always)]
5761            pub fn low_falling(self) -> &'a mut crate::W<REG> {
5762                self.variant(GpioIntPolarity::LowFalling)
5763            }
5764            #[doc = "High level or rising edge"]
5765            #[inline(always)]
5766            pub fn high_rising(self) -> &'a mut crate::W<REG> {
5767                self.variant(GpioIntPolarity::HighRising)
5768            }
5769        }
5770        impl R {
5771            #[doc = "Bits 0:7 - Interrupt polarity: 0=low/falling; 1=high/rising"]
5772            #[inline(always)]
5773            pub fn gpio_int_polarity(&self) -> GpioIntPolarityR {
5774                GpioIntPolarityR::new((self.bits & 0xff) as u8)
5775            }
5776        }
5777        impl W {
5778            #[doc = "Bits 0:7 - Interrupt polarity: 0=low/falling; 1=high/rising"]
5779            #[inline(always)]
5780            pub fn gpio_int_polarity(&mut self) -> GpioIntPolarityW<'_, GpioIntPolaritySpec> {
5781                GpioIntPolarityW::new(self, 0)
5782            }
5783        }
5784        #[doc = "GPIO interrupt polarity register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_polarity::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_polarity::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5785        pub struct GpioIntPolaritySpec;
5786        impl crate::RegisterSpec for GpioIntPolaritySpec {
5787            type Ux = u32;
5788        }
5789        #[doc = "`read()` method returns [`gpio_int_polarity::R`](R) reader structure"]
5790        impl crate::Readable for GpioIntPolaritySpec {}
5791        #[doc = "`write(|w| ..)` method takes [`gpio_int_polarity::W`](W) writer structure"]
5792        impl crate::Writable for GpioIntPolaritySpec {
5793            type Safety = crate::Unsafe;
5794        }
5795        #[doc = "`reset()` method sets GPIO_INT_POLARITY to value 0"]
5796        impl crate::Resettable for GpioIntPolaritySpec {}
5797    }
5798    #[doc = "GPIO_INT_DEDGE (rw) register accessor: GPIO dual-edge interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_dedge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_dedge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_dedge`] module"]
5799    #[doc(alias = "GPIO_INT_DEDGE")]
5800    pub type GpioIntDedge = crate::Reg<gpio_int_dedge::GpioIntDedgeSpec>;
5801    #[doc = "GPIO dual-edge interrupt enable register"]
5802    pub mod gpio_int_dedge {
5803        #[doc = "Register `GPIO_INT_DEDGE` reader"]
5804        pub type R = crate::R<GpioIntDedgeSpec>;
5805        #[doc = "Register `GPIO_INT_DEDGE` writer"]
5806        pub type W = crate::W<GpioIntDedgeSpec>;
5807        #[doc = "Dual-edge interrupt enable: 0=disabled; 1=enabled\n\nValue on reset: 0"]
5808        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
5809        #[repr(u8)]
5810        pub enum GpioIntDedge {
5811            #[doc = "0: Single-edge mode"]
5812            Disabled = 0,
5813            #[doc = "1: Dual-edge triggered"]
5814            Enabled = 1,
5815        }
5816        impl From<GpioIntDedge> for u8 {
5817            #[inline(always)]
5818            fn from(variant: GpioIntDedge) -> Self {
5819                variant as _
5820            }
5821        }
5822        impl crate::FieldSpec for GpioIntDedge {
5823            type Ux = u8;
5824        }
5825        impl crate::IsEnum for GpioIntDedge {}
5826        #[doc = "Field `gpio_int_dedge` reader - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
5827        pub type GpioIntDedgeR = crate::FieldReader<GpioIntDedge>;
5828        impl GpioIntDedgeR {
5829            #[doc = "Get enumerated values variant"]
5830            #[inline(always)]
5831            pub const fn variant(&self) -> Option<GpioIntDedge> {
5832                match self.bits {
5833                    0 => Some(GpioIntDedge::Disabled),
5834                    1 => Some(GpioIntDedge::Enabled),
5835                    _ => None,
5836                }
5837            }
5838            #[doc = "Single-edge mode"]
5839            #[inline(always)]
5840            pub fn is_disabled(&self) -> bool {
5841                *self == GpioIntDedge::Disabled
5842            }
5843            #[doc = "Dual-edge triggered"]
5844            #[inline(always)]
5845            pub fn is_enabled(&self) -> bool {
5846                *self == GpioIntDedge::Enabled
5847            }
5848        }
5849        #[doc = "Field `gpio_int_dedge` writer - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
5850        pub type GpioIntDedgeW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioIntDedge>;
5851        impl<'a, REG> GpioIntDedgeW<'a, REG>
5852        where
5853            REG: crate::Writable + crate::RegisterSpec,
5854            REG::Ux: From<u8>,
5855        {
5856            #[doc = "Single-edge mode"]
5857            #[inline(always)]
5858            pub fn disabled(self) -> &'a mut crate::W<REG> {
5859                self.variant(GpioIntDedge::Disabled)
5860            }
5861            #[doc = "Dual-edge triggered"]
5862            #[inline(always)]
5863            pub fn enabled(self) -> &'a mut crate::W<REG> {
5864                self.variant(GpioIntDedge::Enabled)
5865            }
5866        }
5867        impl R {
5868            #[doc = "Bits 0:7 - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
5869            #[inline(always)]
5870            pub fn gpio_int_dedge(&self) -> GpioIntDedgeR {
5871                GpioIntDedgeR::new((self.bits & 0xff) as u8)
5872            }
5873        }
5874        impl W {
5875            #[doc = "Bits 0:7 - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
5876            #[inline(always)]
5877            pub fn gpio_int_dedge(&mut self) -> GpioIntDedgeW<'_, GpioIntDedgeSpec> {
5878                GpioIntDedgeW::new(self, 0)
5879            }
5880        }
5881        #[doc = "GPIO dual-edge interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_dedge::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_dedge::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5882        pub struct GpioIntDedgeSpec;
5883        impl crate::RegisterSpec for GpioIntDedgeSpec {
5884            type Ux = u32;
5885        }
5886        #[doc = "`read()` method returns [`gpio_int_dedge::R`](R) reader structure"]
5887        impl crate::Readable for GpioIntDedgeSpec {}
5888        #[doc = "`write(|w| ..)` method takes [`gpio_int_dedge::W`](W) writer structure"]
5889        impl crate::Writable for GpioIntDedgeSpec {
5890            type Safety = crate::Unsafe;
5891        }
5892        #[doc = "`reset()` method sets GPIO_INT_DEDGE to value 0"]
5893        impl crate::Resettable for GpioIntDedgeSpec {}
5894    }
5895    #[doc = "GPIO_INT_DEBOUNCE (rw) register accessor: GPIO interrupt debounce control register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_debounce::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_debounce::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_debounce`] module"]
5896    #[doc(alias = "GPIO_INT_DEBOUNCE")]
5897    pub type GpioIntDebounce = crate::Reg<gpio_int_debounce::GpioIntDebounceSpec>;
5898    #[doc = "GPIO interrupt debounce control register"]
5899    pub mod gpio_int_debounce {
5900        #[doc = "Register `GPIO_INT_DEBOUNCE` reader"]
5901        pub type R = crate::R<GpioIntDebounceSpec>;
5902        #[doc = "Register `GPIO_INT_DEBOUNCE` writer"]
5903        pub type W = crate::W<GpioIntDebounceSpec>;
5904        #[doc = "Field `gpio_int_debounce` reader - Debounce enable: 0=disabled; 1=enabled"]
5905        pub type GpioIntDebounceR = crate::FieldReader;
5906        #[doc = "Field `gpio_int_debounce` writer - Debounce enable: 0=disabled; 1=enabled"]
5907        pub type GpioIntDebounceW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
5908        impl R {
5909            #[doc = "Bits 0:7 - Debounce enable: 0=disabled; 1=enabled"]
5910            #[inline(always)]
5911            pub fn gpio_int_debounce(&self) -> GpioIntDebounceR {
5912                GpioIntDebounceR::new((self.bits & 0xff) as u8)
5913            }
5914        }
5915        impl W {
5916            #[doc = "Bits 0:7 - Debounce enable: 0=disabled; 1=enabled"]
5917            #[inline(always)]
5918            pub fn gpio_int_debounce(&mut self) -> GpioIntDebounceW<'_, GpioIntDebounceSpec> {
5919                GpioIntDebounceW::new(self, 0)
5920            }
5921        }
5922        #[doc = "GPIO interrupt debounce control register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_debounce::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_debounce::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5923        pub struct GpioIntDebounceSpec;
5924        impl crate::RegisterSpec for GpioIntDebounceSpec {
5925            type Ux = u32;
5926        }
5927        #[doc = "`read()` method returns [`gpio_int_debounce::R`](R) reader structure"]
5928        impl crate::Readable for GpioIntDebounceSpec {}
5929        #[doc = "`write(|w| ..)` method takes [`gpio_int_debounce::W`](W) writer structure"]
5930        impl crate::Writable for GpioIntDebounceSpec {
5931            type Safety = crate::Unsafe;
5932        }
5933        #[doc = "`reset()` method sets GPIO_INT_DEBOUNCE to value 0"]
5934        impl crate::Resettable for GpioIntDebounceSpec {}
5935    }
5936    #[doc = "GPIO_INT_RAW (rw) register accessor: GPIO raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_raw`] module"]
5937    #[doc(alias = "GPIO_INT_RAW")]
5938    pub type GpioIntRaw = crate::Reg<gpio_int_raw::GpioIntRawSpec>;
5939    #[doc = "GPIO raw interrupt status register"]
5940    pub mod gpio_int_raw {
5941        #[doc = "Register `GPIO_INT_RAW` reader"]
5942        pub type R = crate::R<GpioIntRawSpec>;
5943        #[doc = "Register `GPIO_INT_RAW` writer"]
5944        pub type W = crate::W<GpioIntRawSpec>;
5945        #[doc = "Field `gpio_int_raw` reader - Raw interrupt status (before mask): 0=no interrupt; 1=interrupt"]
5946        pub type GpioIntRawR = crate::FieldReader;
5947        impl R {
5948            #[doc = "Bits 0:7 - Raw interrupt status (before mask): 0=no interrupt; 1=interrupt"]
5949            #[inline(always)]
5950            pub fn gpio_int_raw(&self) -> GpioIntRawR {
5951                GpioIntRawR::new((self.bits & 0xff) as u8)
5952            }
5953        }
5954        impl W {}
5955        #[doc = "GPIO raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5956        pub struct GpioIntRawSpec;
5957        impl crate::RegisterSpec for GpioIntRawSpec {
5958            type Ux = u32;
5959        }
5960        #[doc = "`read()` method returns [`gpio_int_raw::R`](R) reader structure"]
5961        impl crate::Readable for GpioIntRawSpec {}
5962        #[doc = "`write(|w| ..)` method takes [`gpio_int_raw::W`](W) writer structure"]
5963        impl crate::Writable for GpioIntRawSpec {
5964            type Safety = crate::Unsafe;
5965        }
5966        #[doc = "`reset()` method sets GPIO_INT_RAW to value 0"]
5967        impl crate::Resettable for GpioIntRawSpec {}
5968    }
5969    #[doc = "GPIO_INTR (rw) register accessor: GPIO interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_intr`] module"]
5970    #[doc(alias = "GPIO_INTR")]
5971    pub type GpioIntr = crate::Reg<gpio_intr::GpioIntrSpec>;
5972    #[doc = "GPIO interrupt status register"]
5973    pub mod gpio_intr {
5974        #[doc = "Register `GPIO_INTR` reader"]
5975        pub type R = crate::R<GpioIntrSpec>;
5976        #[doc = "Register `GPIO_INTR` writer"]
5977        pub type W = crate::W<GpioIntrSpec>;
5978        #[doc = "Field `gpio_intr` reader - Interrupt status (after mask): 0=no interrupt; 1=interrupt"]
5979        pub type GpioIntrR = crate::FieldReader;
5980        impl R {
5981            #[doc = "Bits 0:7 - Interrupt status (after mask): 0=no interrupt; 1=interrupt"]
5982            #[inline(always)]
5983            pub fn gpio_intr(&self) -> GpioIntrR {
5984                GpioIntrR::new((self.bits & 0xff) as u8)
5985            }
5986        }
5987        impl W {}
5988        #[doc = "GPIO interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5989        pub struct GpioIntrSpec;
5990        impl crate::RegisterSpec for GpioIntrSpec {
5991            type Ux = u32;
5992        }
5993        #[doc = "`read()` method returns [`gpio_intr::R`](R) reader structure"]
5994        impl crate::Readable for GpioIntrSpec {}
5995        #[doc = "`write(|w| ..)` method takes [`gpio_intr::W`](W) writer structure"]
5996        impl crate::Writable for GpioIntrSpec {
5997            type Safety = crate::Unsafe;
5998        }
5999        #[doc = "`reset()` method sets GPIO_INTR to value 0"]
6000        impl crate::Resettable for GpioIntrSpec {}
6001    }
6002    #[doc = "GPIO_INT_EOI (rw) register accessor: GPIO interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_eoi`] module"]
6003    #[doc(alias = "GPIO_INT_EOI")]
6004    pub type GpioIntEoi = crate::Reg<gpio_int_eoi::GpioIntEoiSpec>;
6005    #[doc = "GPIO interrupt clear register"]
6006    pub mod gpio_int_eoi {
6007        #[doc = "Register `GPIO_INT_EOI` reader"]
6008        pub type R = crate::R<GpioIntEoiSpec>;
6009        #[doc = "Register `GPIO_INT_EOI` writer"]
6010        pub type W = crate::W<GpioIntEoiSpec>;
6011        #[doc = "Field `gpio_int_eoi` writer - Edge interrupt clear: 0=no clear; 1=clear interrupt"]
6012        pub type GpioIntEoiW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
6013        impl W {
6014            #[doc = "Bits 0:7 - Edge interrupt clear: 0=no clear; 1=clear interrupt"]
6015            #[inline(always)]
6016            pub fn gpio_int_eoi(&mut self) -> GpioIntEoiW<'_, GpioIntEoiSpec> {
6017                GpioIntEoiW::new(self, 0)
6018            }
6019        }
6020        #[doc = "GPIO interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6021        pub struct GpioIntEoiSpec;
6022        impl crate::RegisterSpec for GpioIntEoiSpec {
6023            type Ux = u32;
6024        }
6025        #[doc = "`read()` method returns [`gpio_int_eoi::R`](R) reader structure"]
6026        impl crate::Readable for GpioIntEoiSpec {}
6027        #[doc = "`write(|w| ..)` method takes [`gpio_int_eoi::W`](W) writer structure"]
6028        impl crate::Writable for GpioIntEoiSpec {
6029            type Safety = crate::Unsafe;
6030        }
6031        #[doc = "`reset()` method sets GPIO_INT_EOI to value 0"]
6032        impl crate::Resettable for GpioIntEoiSpec {}
6033    }
6034    #[doc = "GPIO_DATA_SET (rw) register accessor: GPIO data set register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_data_set`] module"]
6035    #[doc(alias = "GPIO_DATA_SET")]
6036    pub type GpioDataSet = crate::Reg<gpio_data_set::GpioDataSetSpec>;
6037    #[doc = "GPIO data set register"]
6038    pub mod gpio_data_set {
6039        #[doc = "Register `GPIO_DATA_SET` reader"]
6040        pub type R = crate::R<GpioDataSetSpec>;
6041        #[doc = "Register `GPIO_DATA_SET` writer"]
6042        pub type W = crate::W<GpioDataSetSpec>;
6043        #[doc = "Field `gpio_data_set` writer - Write 1 to set corresponding GPIO_SW_OUT bits"]
6044        pub type GpioDataSetW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
6045        impl W {
6046            #[doc = "Bits 0:7 - Write 1 to set corresponding GPIO_SW_OUT bits"]
6047            #[inline(always)]
6048            pub fn gpio_data_set(&mut self) -> GpioDataSetW<'_, GpioDataSetSpec> {
6049                GpioDataSetW::new(self, 0)
6050            }
6051        }
6052        #[doc = "GPIO data set register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6053        pub struct GpioDataSetSpec;
6054        impl crate::RegisterSpec for GpioDataSetSpec {
6055            type Ux = u32;
6056        }
6057        #[doc = "`read()` method returns [`gpio_data_set::R`](R) reader structure"]
6058        impl crate::Readable for GpioDataSetSpec {}
6059        #[doc = "`write(|w| ..)` method takes [`gpio_data_set::W`](W) writer structure"]
6060        impl crate::Writable for GpioDataSetSpec {
6061            type Safety = crate::Unsafe;
6062        }
6063        #[doc = "`reset()` method sets GPIO_DATA_SET to value 0"]
6064        impl crate::Resettable for GpioDataSetSpec {}
6065    }
6066    #[doc = "GPIO_DATA_CLR (rw) register accessor: GPIO data clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_data_clr`] module"]
6067    #[doc(alias = "GPIO_DATA_CLR")]
6068    pub type GpioDataClr = crate::Reg<gpio_data_clr::GpioDataClrSpec>;
6069    #[doc = "GPIO data clear register"]
6070    pub mod gpio_data_clr {
6071        #[doc = "Register `GPIO_DATA_CLR` reader"]
6072        pub type R = crate::R<GpioDataClrSpec>;
6073        #[doc = "Register `GPIO_DATA_CLR` writer"]
6074        pub type W = crate::W<GpioDataClrSpec>;
6075        #[doc = "Field `gpio_data_clr` writer - Write 1 to clear corresponding GPIO_SW_OUT bits"]
6076        pub type GpioDataClrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
6077        impl W {
6078            #[doc = "Bits 0:7 - Write 1 to clear corresponding GPIO_SW_OUT bits"]
6079            #[inline(always)]
6080            pub fn gpio_data_clr(&mut self) -> GpioDataClrW<'_, GpioDataClrSpec> {
6081                GpioDataClrW::new(self, 0)
6082            }
6083        }
6084        #[doc = "GPIO data clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6085        pub struct GpioDataClrSpec;
6086        impl crate::RegisterSpec for GpioDataClrSpec {
6087            type Ux = u32;
6088        }
6089        #[doc = "`read()` method returns [`gpio_data_clr::R`](R) reader structure"]
6090        impl crate::Readable for GpioDataClrSpec {}
6091        #[doc = "`write(|w| ..)` method takes [`gpio_data_clr::W`](W) writer structure"]
6092        impl crate::Writable for GpioDataClrSpec {
6093            type Safety = crate::Unsafe;
6094        }
6095        #[doc = "`reset()` method sets GPIO_DATA_CLR to value 0"]
6096        impl crate::Resettable for GpioDataClrSpec {}
6097    }
6098}
6099#[doc = "GPIO controller for GPIO\\[15:8\\]"]
6100pub type Gpio1 = crate::Periph<gpio0::RegisterBlock, 0x4402_9000>;
6101impl core::fmt::Debug for Gpio1 {
6102    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6103        f.debug_struct("Gpio1").finish()
6104    }
6105}
6106#[doc = "GPIO controller for GPIO\\[15:8\\]"]
6107pub use self::gpio0 as gpio1;
6108#[doc = "GPIO controller for GPIO\\[18:16\\] — only 3 bits used; bits \\[7:3\\] are reserved and unused."]
6109pub type Gpio2 = crate::Periph<gpio0::RegisterBlock, 0x4402_a000>;
6110impl core::fmt::Debug for Gpio2 {
6111    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6112        f.debug_struct("Gpio2").finish()
6113    }
6114}
6115#[doc = "GPIO controller for GPIO\\[18:16\\] — only 3 bits used; bits \\[7:3\\] are reserved and unused."]
6116pub use self::gpio0 as gpio2;
6117#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
6118pub type Uart0 = crate::Periph<uart0::RegisterBlock, 0x4401_0000>;
6119impl core::fmt::Debug for Uart0 {
6120    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6121        f.debug_struct("Uart0").finish()
6122    }
6123}
6124#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
6125pub mod uart0 {
6126    #[repr(C)]
6127    #[doc = "Register block"]
6128    pub struct RegisterBlock {
6129        intr_id: IntrId,
6130        _reserved1: [u8; 0x02],
6131        data: Data,
6132        _reserved2: [u8; 0x02],
6133        uart_ctl: UartCtl,
6134        _reserved3: [u8; 0x02],
6135        div_h: DivH,
6136        _reserved4: [u8; 0x02],
6137        div_l: DivL,
6138        _reserved5: [u8; 0x02],
6139        div_fra: DivFra,
6140        _reserved6: [u8; 0x02],
6141        intr_en: IntrEn,
6142        _reserved7: [u8; 0x02],
6143        intr_status: IntrStatus,
6144        _reserved8: [u8; 0x06],
6145        fifo_ctl: FifoCtl,
6146        _reserved9: [u8; 0x02],
6147        far: Far,
6148        _reserved10: [u8; 0x02],
6149        modem_ctl: ModemCtl,
6150        _reserved11: [u8; 0x02],
6151        modem_status: ModemStatus,
6152        _reserved12: [u8; 0x02],
6153        line_status: LineStatus,
6154        _reserved13: [u8; 0x02],
6155        uart_gp_reg: UartGpReg,
6156        _reserved14: [u8; 0x02],
6157        tx_fifo_read: TxFifoRead,
6158        _reserved15: [u8; 0x02],
6159        rx_fifo_write: RxFifoWrite,
6160        _reserved16: [u8; 0x02],
6161        fifo_status: FifoStatus,
6162        _reserved17: [u8; 0x02],
6163        tx_fifo_cnt: TxFifoCnt,
6164        _reserved18: [u8; 0x02],
6165        rx_fifo_cnt: RxFifoCnt,
6166        _reserved19: [u8; 0x02],
6167        halt_tx: HaltTx,
6168        _reserved20: [u8; 0x02],
6169        dma_sw_ack: DmaSwAck,
6170        _reserved21: [u8; 0x02],
6171        baud_ctl: BaudCtl,
6172        _reserved22: [u8; 0x02],
6173        stp_ctl: StpCtl,
6174        _reserved23: [u8; 0x02],
6175        uart_parameter: UartParameter,
6176    }
6177    impl RegisterBlock {
6178        #[doc = "0x00 - Interrupt ID register"]
6179        #[inline(always)]
6180        pub const fn intr_id(&self) -> &IntrId {
6181            &self.intr_id
6182        }
6183        #[doc = "0x04 - Data register"]
6184        #[inline(always)]
6185        pub const fn data(&self) -> &Data {
6186            &self.data
6187        }
6188        #[doc = "0x08 - UART control register"]
6189        #[inline(always)]
6190        pub const fn uart_ctl(&self) -> &UartCtl {
6191            &self.uart_ctl
6192        }
6193        #[doc = "0x0c - Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
6194        #[inline(always)]
6195        pub const fn div_h(&self) -> &DivH {
6196            &self.div_h
6197        }
6198        #[doc = "0x10 - Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
6199        #[inline(always)]
6200        pub const fn div_l(&self) -> &DivL {
6201            &self.div_l
6202        }
6203        #[doc = "0x14 - Baud rate divider fractional part"]
6204        #[inline(always)]
6205        pub const fn div_fra(&self) -> &DivFra {
6206            &self.div_fra
6207        }
6208        #[doc = "0x18 - Interrupt enable register"]
6209        #[inline(always)]
6210        pub const fn intr_en(&self) -> &IntrEn {
6211            &self.intr_en
6212        }
6213        #[doc = "0x1c - Interrupt status register"]
6214        #[inline(always)]
6215        pub const fn intr_status(&self) -> &IntrStatus {
6216            &self.intr_status
6217        }
6218        #[doc = "0x24 - FIFO control register"]
6219        #[inline(always)]
6220        pub const fn fifo_ctl(&self) -> &FifoCtl {
6221            &self.fifo_ctl
6222        }
6223        #[doc = "0x28 - FIFO access mode enable register"]
6224        #[inline(always)]
6225        pub const fn far(&self) -> &Far {
6226            &self.far
6227        }
6228        #[doc = "0x2c - Modem control register"]
6229        #[inline(always)]
6230        pub const fn modem_ctl(&self) -> &ModemCtl {
6231            &self.modem_ctl
6232        }
6233        #[doc = "0x30 - Modem status register"]
6234        #[inline(always)]
6235        pub const fn modem_status(&self) -> &ModemStatus {
6236            &self.modem_status
6237        }
6238        #[doc = "0x34 - Line status register"]
6239        #[inline(always)]
6240        pub const fn line_status(&self) -> &LineStatus {
6241            &self.line_status
6242        }
6243        #[doc = "0x38 - UART general purpose register"]
6244        #[inline(always)]
6245        pub const fn uart_gp_reg(&self) -> &UartGpReg {
6246            &self.uart_gp_reg
6247        }
6248        #[doc = "0x3c - TX FIFO read register"]
6249        #[inline(always)]
6250        pub const fn tx_fifo_read(&self) -> &TxFifoRead {
6251            &self.tx_fifo_read
6252        }
6253        #[doc = "0x40 - RX FIFO write register"]
6254        #[inline(always)]
6255        pub const fn rx_fifo_write(&self) -> &RxFifoWrite {
6256            &self.rx_fifo_write
6257        }
6258        #[doc = "0x44 - FIFO status register"]
6259        #[inline(always)]
6260        pub const fn fifo_status(&self) -> &FifoStatus {
6261            &self.fifo_status
6262        }
6263        #[doc = "0x48 - TX FIFO data counter"]
6264        #[inline(always)]
6265        pub const fn tx_fifo_cnt(&self) -> &TxFifoCnt {
6266            &self.tx_fifo_cnt
6267        }
6268        #[doc = "0x4c - RX FIFO data counter"]
6269        #[inline(always)]
6270        pub const fn rx_fifo_cnt(&self) -> &RxFifoCnt {
6271            &self.rx_fifo_cnt
6272        }
6273        #[doc = "0x50 - TX halt register"]
6274        #[inline(always)]
6275        pub const fn halt_tx(&self) -> &HaltTx {
6276            &self.halt_tx
6277        }
6278        #[doc = "0x54 - DMA software acknowledge register"]
6279        #[inline(always)]
6280        pub const fn dma_sw_ack(&self) -> &DmaSwAck {
6281            &self.dma_sw_ack
6282        }
6283        #[doc = "0x58 - Baud rate control register"]
6284        #[inline(always)]
6285        pub const fn baud_ctl(&self) -> &BaudCtl {
6286            &self.baud_ctl
6287        }
6288        #[doc = "0x5c - Stop bit control register"]
6289        #[inline(always)]
6290        pub const fn stp_ctl(&self) -> &StpCtl {
6291            &self.stp_ctl
6292        }
6293        #[doc = "0x60 - UART parameter register"]
6294        #[inline(always)]
6295        pub const fn uart_parameter(&self) -> &UartParameter {
6296            &self.uart_parameter
6297        }
6298    }
6299    #[doc = "INTR_ID (rw) register accessor: Interrupt ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_id`] module"]
6300    #[doc(alias = "INTR_ID")]
6301    pub type IntrId = crate::Reg<intr_id::IntrIdSpec>;
6302    #[doc = "Interrupt ID register"]
6303    pub mod intr_id {
6304        #[doc = "Register `INTR_ID` reader"]
6305        pub type R = crate::R<IntrIdSpec>;
6306        #[doc = "Register `INTR_ID` writer"]
6307        pub type W = crate::W<IntrIdSpec>;
6308        #[doc = "Field `intr_id` reader - Interrupt ID: 0x0=modem status; 0x1=no interrupt; 0x2=THR empty; 0x4=rx data; 0x6=rx line status; 0x7=busy; 0xC=char timeout"]
6309        pub type IntrIdR = crate::FieldReader;
6310        #[doc = "Field `fifo_en_s` reader - FIFO enable status: 0=FIFO disabled; 1=FIFO enabled"]
6311        pub type FifoEnSR = crate::BitReader;
6312        impl R {
6313            #[doc = "Bits 0:3 - Interrupt ID: 0x0=modem status; 0x1=no interrupt; 0x2=THR empty; 0x4=rx data; 0x6=rx line status; 0x7=busy; 0xC=char timeout"]
6314            #[inline(always)]
6315            pub fn intr_id(&self) -> IntrIdR {
6316                IntrIdR::new((self.bits & 0x0f) as u8)
6317            }
6318            #[doc = "Bit 4 - FIFO enable status: 0=FIFO disabled; 1=FIFO enabled"]
6319            #[inline(always)]
6320            pub fn fifo_en_s(&self) -> FifoEnSR {
6321                FifoEnSR::new(((self.bits >> 4) & 1) != 0)
6322            }
6323        }
6324        impl W {}
6325        #[doc = "Interrupt ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6326        pub struct IntrIdSpec;
6327        impl crate::RegisterSpec for IntrIdSpec {
6328            type Ux = u16;
6329        }
6330        #[doc = "`read()` method returns [`intr_id::R`](R) reader structure"]
6331        impl crate::Readable for IntrIdSpec {}
6332        #[doc = "`write(|w| ..)` method takes [`intr_id::W`](W) writer structure"]
6333        impl crate::Writable for IntrIdSpec {
6334            type Safety = crate::Unsafe;
6335        }
6336        #[doc = "`reset()` method sets INTR_ID to value 0x01"]
6337        impl crate::Resettable for IntrIdSpec {
6338            const RESET_VALUE: u16 = 0x01;
6339        }
6340    }
6341    #[doc = "DATA (rw) register accessor: Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
6342    #[doc(alias = "DATA")]
6343    pub type Data = crate::Reg<data::DataSpec>;
6344    #[doc = "Data register"]
6345    pub mod data {
6346        #[doc = "Register `DATA` reader"]
6347        pub type R = crate::R<DataSpec>;
6348        #[doc = "Register `DATA` writer"]
6349        pub type W = crate::W<DataSpec>;
6350        #[doc = "Field `data` reader - Write: TX data; Read: RX data"]
6351        pub type DataR = crate::FieldReader;
6352        #[doc = "Field `data` writer - Write: TX data; Read: RX data"]
6353        pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
6354        impl R {
6355            #[doc = "Bits 0:7 - Write: TX data; Read: RX data"]
6356            #[inline(always)]
6357            pub fn data(&self) -> DataR {
6358                DataR::new((self.bits & 0xff) as u8)
6359            }
6360        }
6361        impl W {
6362            #[doc = "Bits 0:7 - Write: TX data; Read: RX data"]
6363            #[inline(always)]
6364            pub fn data(&mut self) -> DataW<'_, DataSpec> {
6365                DataW::new(self, 0)
6366            }
6367        }
6368        #[doc = "Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6369        pub struct DataSpec;
6370        impl crate::RegisterSpec for DataSpec {
6371            type Ux = u16;
6372        }
6373        #[doc = "`read()` method returns [`data::R`](R) reader structure"]
6374        impl crate::Readable for DataSpec {}
6375        #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
6376        impl crate::Writable for DataSpec {
6377            type Safety = crate::Unsafe;
6378        }
6379        #[doc = "`reset()` method sets DATA to value 0"]
6380        impl crate::Resettable for DataSpec {}
6381    }
6382    #[doc = "UART_CTL (rw) register accessor: UART control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_ctl`] module"]
6383    #[doc(alias = "UART_CTL")]
6384    pub type UartCtl = crate::Reg<uart_ctl::UartCtlSpec>;
6385    #[doc = "UART control register"]
6386    pub mod uart_ctl {
6387        #[doc = "Register `UART_CTL` reader"]
6388        pub type R = crate::R<UartCtlSpec>;
6389        #[doc = "Register `UART_CTL` writer"]
6390        pub type W = crate::W<UartCtlSpec>;
6391        #[doc = "Field `div_en` reader - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
6392        pub type DivEnR = crate::BitReader;
6393        #[doc = "Field `div_en` writer - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
6394        pub type DivEnW<'a, REG> = crate::BitWriter<'a, REG>;
6395        #[doc = "Field `xbreak` reader - Break control: 0=normal; 1=force TX to space"]
6396        pub type XbreakR = crate::BitReader;
6397        #[doc = "Field `xbreak` writer - Break control: 0=normal; 1=force TX to space"]
6398        pub type XbreakW<'a, REG> = crate::BitWriter<'a, REG>;
6399        #[doc = "Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit\n\nValue on reset: 0"]
6400        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6401        #[repr(u8)]
6402        pub enum Dlen {
6403            #[doc = "0: 5-bit data"]
6404            Bits5 = 0,
6405            #[doc = "1: 6-bit data"]
6406            Bits6 = 1,
6407            #[doc = "2: 7-bit data"]
6408            Bits7 = 2,
6409            #[doc = "3: 8-bit data"]
6410            Bits8 = 3,
6411        }
6412        impl From<Dlen> for u8 {
6413            #[inline(always)]
6414            fn from(variant: Dlen) -> Self {
6415                variant as _
6416            }
6417        }
6418        impl crate::FieldSpec for Dlen {
6419            type Ux = u8;
6420        }
6421        impl crate::IsEnum for Dlen {}
6422        #[doc = "Field `dlen` reader - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
6423        pub type DlenR = crate::FieldReader<Dlen>;
6424        impl DlenR {
6425            #[doc = "Get enumerated values variant"]
6426            #[inline(always)]
6427            pub const fn variant(&self) -> Dlen {
6428                match self.bits {
6429                    0 => Dlen::Bits5,
6430                    1 => Dlen::Bits6,
6431                    2 => Dlen::Bits7,
6432                    3 => Dlen::Bits8,
6433                    _ => unreachable!(),
6434                }
6435            }
6436            #[doc = "5-bit data"]
6437            #[inline(always)]
6438            pub fn is_bits5(&self) -> bool {
6439                *self == Dlen::Bits5
6440            }
6441            #[doc = "6-bit data"]
6442            #[inline(always)]
6443            pub fn is_bits6(&self) -> bool {
6444                *self == Dlen::Bits6
6445            }
6446            #[doc = "7-bit data"]
6447            #[inline(always)]
6448            pub fn is_bits7(&self) -> bool {
6449                *self == Dlen::Bits7
6450            }
6451            #[doc = "8-bit data"]
6452            #[inline(always)]
6453            pub fn is_bits8(&self) -> bool {
6454                *self == Dlen::Bits8
6455            }
6456        }
6457        #[doc = "Field `dlen` writer - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
6458        pub type DlenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dlen, crate::Safe>;
6459        impl<'a, REG> DlenW<'a, REG>
6460        where
6461            REG: crate::Writable + crate::RegisterSpec,
6462            REG::Ux: From<u8>,
6463        {
6464            #[doc = "5-bit data"]
6465            #[inline(always)]
6466            pub fn bits5(self) -> &'a mut crate::W<REG> {
6467                self.variant(Dlen::Bits5)
6468            }
6469            #[doc = "6-bit data"]
6470            #[inline(always)]
6471            pub fn bits6(self) -> &'a mut crate::W<REG> {
6472                self.variant(Dlen::Bits6)
6473            }
6474            #[doc = "7-bit data"]
6475            #[inline(always)]
6476            pub fn bits7(self) -> &'a mut crate::W<REG> {
6477                self.variant(Dlen::Bits7)
6478            }
6479            #[doc = "8-bit data"]
6480            #[inline(always)]
6481            pub fn bits8(self) -> &'a mut crate::W<REG> {
6482                self.variant(Dlen::Bits8)
6483            }
6484        }
6485        #[doc = "Parity select: 0=odd; 1=even\n\nValue on reset: 0"]
6486        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6487        pub enum Eps {
6488            #[doc = "0: Odd parity"]
6489            Odd = 0,
6490            #[doc = "1: Even parity"]
6491            Even = 1,
6492        }
6493        impl From<Eps> for bool {
6494            #[inline(always)]
6495            fn from(variant: Eps) -> Self {
6496                variant as u8 != 0
6497            }
6498        }
6499        #[doc = "Field `eps` reader - Parity select: 0=odd; 1=even"]
6500        pub type EpsR = crate::BitReader<Eps>;
6501        impl EpsR {
6502            #[doc = "Get enumerated values variant"]
6503            #[inline(always)]
6504            pub const fn variant(&self) -> Eps {
6505                match self.bits {
6506                    false => Eps::Odd,
6507                    true => Eps::Even,
6508                }
6509            }
6510            #[doc = "Odd parity"]
6511            #[inline(always)]
6512            pub fn is_odd(&self) -> bool {
6513                *self == Eps::Odd
6514            }
6515            #[doc = "Even parity"]
6516            #[inline(always)]
6517            pub fn is_even(&self) -> bool {
6518                *self == Eps::Even
6519            }
6520        }
6521        #[doc = "Field `eps` writer - Parity select: 0=odd; 1=even"]
6522        pub type EpsW<'a, REG> = crate::BitWriter<'a, REG, Eps>;
6523        impl<'a, REG> EpsW<'a, REG>
6524        where
6525            REG: crate::Writable + crate::RegisterSpec,
6526        {
6527            #[doc = "Odd parity"]
6528            #[inline(always)]
6529            pub fn odd(self) -> &'a mut crate::W<REG> {
6530                self.variant(Eps::Odd)
6531            }
6532            #[doc = "Even parity"]
6533            #[inline(always)]
6534            pub fn even(self) -> &'a mut crate::W<REG> {
6535                self.variant(Eps::Even)
6536            }
6537        }
6538        #[doc = "Parity enable: 0=disabled; 1=enabled\n\nValue on reset: 0"]
6539        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6540        pub enum Pen {
6541            #[doc = "0: No parity"]
6542            Disabled = 0,
6543            #[doc = "1: Parity enabled"]
6544            Enabled = 1,
6545        }
6546        impl From<Pen> for bool {
6547            #[inline(always)]
6548            fn from(variant: Pen) -> Self {
6549                variant as u8 != 0
6550            }
6551        }
6552        #[doc = "Field `pen` reader - Parity enable: 0=disabled; 1=enabled"]
6553        pub type PenR = crate::BitReader<Pen>;
6554        impl PenR {
6555            #[doc = "Get enumerated values variant"]
6556            #[inline(always)]
6557            pub const fn variant(&self) -> Pen {
6558                match self.bits {
6559                    false => Pen::Disabled,
6560                    true => Pen::Enabled,
6561                }
6562            }
6563            #[doc = "No parity"]
6564            #[inline(always)]
6565            pub fn is_disabled(&self) -> bool {
6566                *self == Pen::Disabled
6567            }
6568            #[doc = "Parity enabled"]
6569            #[inline(always)]
6570            pub fn is_enabled(&self) -> bool {
6571                *self == Pen::Enabled
6572            }
6573        }
6574        #[doc = "Field `pen` writer - Parity enable: 0=disabled; 1=enabled"]
6575        pub type PenW<'a, REG> = crate::BitWriter<'a, REG, Pen>;
6576        impl<'a, REG> PenW<'a, REG>
6577        where
6578            REG: crate::Writable + crate::RegisterSpec,
6579        {
6580            #[doc = "No parity"]
6581            #[inline(always)]
6582            pub fn disabled(self) -> &'a mut crate::W<REG> {
6583                self.variant(Pen::Disabled)
6584            }
6585            #[doc = "Parity enabled"]
6586            #[inline(always)]
6587            pub fn enabled(self) -> &'a mut crate::W<REG> {
6588                self.variant(Pen::Enabled)
6589            }
6590        }
6591        #[doc = "Field `sps` reader - Sticky parity: 0=disabled; 1=enabled"]
6592        pub type SpsR = crate::BitReader;
6593        #[doc = "Field `sps` writer - Sticky parity: 0=disabled; 1=enabled"]
6594        pub type SpsW<'a, REG> = crate::BitWriter<'a, REG>;
6595        #[doc = "Stop bits: 0=1bit; 1=1.5/2bit\n\nValue on reset: 0"]
6596        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
6597        pub enum Stp {
6598            #[doc = "0: 1 stop bit"]
6599            Stop1 = 0,
6600            #[doc = "1: 1.5 (5-bit data) or 2 stop bits"]
6601            Stop1_5Or2 = 1,
6602        }
6603        impl From<Stp> for bool {
6604            #[inline(always)]
6605            fn from(variant: Stp) -> Self {
6606                variant as u8 != 0
6607            }
6608        }
6609        #[doc = "Field `stp` reader - Stop bits: 0=1bit; 1=1.5/2bit"]
6610        pub type StpR = crate::BitReader<Stp>;
6611        impl StpR {
6612            #[doc = "Get enumerated values variant"]
6613            #[inline(always)]
6614            pub const fn variant(&self) -> Stp {
6615                match self.bits {
6616                    false => Stp::Stop1,
6617                    true => Stp::Stop1_5Or2,
6618                }
6619            }
6620            #[doc = "1 stop bit"]
6621            #[inline(always)]
6622            pub fn is_stop1(&self) -> bool {
6623                *self == Stp::Stop1
6624            }
6625            #[doc = "1.5 (5-bit data) or 2 stop bits"]
6626            #[inline(always)]
6627            pub fn is_stop1_5_or_2(&self) -> bool {
6628                *self == Stp::Stop1_5Or2
6629            }
6630        }
6631        #[doc = "Field `stp` writer - Stop bits: 0=1bit; 1=1.5/2bit"]
6632        pub type StpW<'a, REG> = crate::BitWriter<'a, REG, Stp>;
6633        impl<'a, REG> StpW<'a, REG>
6634        where
6635            REG: crate::Writable + crate::RegisterSpec,
6636        {
6637            #[doc = "1 stop bit"]
6638            #[inline(always)]
6639            pub fn stop1(self) -> &'a mut crate::W<REG> {
6640                self.variant(Stp::Stop1)
6641            }
6642            #[doc = "1.5 (5-bit data) or 2 stop bits"]
6643            #[inline(always)]
6644            pub fn stop1_5_or_2(self) -> &'a mut crate::W<REG> {
6645                self.variant(Stp::Stop1_5Or2)
6646            }
6647        }
6648        impl R {
6649            #[doc = "Bit 0 - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
6650            #[inline(always)]
6651            pub fn div_en(&self) -> DivEnR {
6652                DivEnR::new((self.bits & 1) != 0)
6653            }
6654            #[doc = "Bit 1 - Break control: 0=normal; 1=force TX to space"]
6655            #[inline(always)]
6656            pub fn xbreak(&self) -> XbreakR {
6657                XbreakR::new(((self.bits >> 1) & 1) != 0)
6658            }
6659            #[doc = "Bits 2:3 - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
6660            #[inline(always)]
6661            pub fn dlen(&self) -> DlenR {
6662                DlenR::new(((self.bits >> 2) & 3) as u8)
6663            }
6664            #[doc = "Bit 4 - Parity select: 0=odd; 1=even"]
6665            #[inline(always)]
6666            pub fn eps(&self) -> EpsR {
6667                EpsR::new(((self.bits >> 4) & 1) != 0)
6668            }
6669            #[doc = "Bit 5 - Parity enable: 0=disabled; 1=enabled"]
6670            #[inline(always)]
6671            pub fn pen(&self) -> PenR {
6672                PenR::new(((self.bits >> 5) & 1) != 0)
6673            }
6674            #[doc = "Bit 6 - Sticky parity: 0=disabled; 1=enabled"]
6675            #[inline(always)]
6676            pub fn sps(&self) -> SpsR {
6677                SpsR::new(((self.bits >> 6) & 1) != 0)
6678            }
6679            #[doc = "Bit 7 - Stop bits: 0=1bit; 1=1.5/2bit"]
6680            #[inline(always)]
6681            pub fn stp(&self) -> StpR {
6682                StpR::new(((self.bits >> 7) & 1) != 0)
6683            }
6684        }
6685        impl W {
6686            #[doc = "Bit 0 - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
6687            #[inline(always)]
6688            pub fn div_en(&mut self) -> DivEnW<'_, UartCtlSpec> {
6689                DivEnW::new(self, 0)
6690            }
6691            #[doc = "Bit 1 - Break control: 0=normal; 1=force TX to space"]
6692            #[inline(always)]
6693            pub fn xbreak(&mut self) -> XbreakW<'_, UartCtlSpec> {
6694                XbreakW::new(self, 1)
6695            }
6696            #[doc = "Bits 2:3 - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
6697            #[inline(always)]
6698            pub fn dlen(&mut self) -> DlenW<'_, UartCtlSpec> {
6699                DlenW::new(self, 2)
6700            }
6701            #[doc = "Bit 4 - Parity select: 0=odd; 1=even"]
6702            #[inline(always)]
6703            pub fn eps(&mut self) -> EpsW<'_, UartCtlSpec> {
6704                EpsW::new(self, 4)
6705            }
6706            #[doc = "Bit 5 - Parity enable: 0=disabled; 1=enabled"]
6707            #[inline(always)]
6708            pub fn pen(&mut self) -> PenW<'_, UartCtlSpec> {
6709                PenW::new(self, 5)
6710            }
6711            #[doc = "Bit 6 - Sticky parity: 0=disabled; 1=enabled"]
6712            #[inline(always)]
6713            pub fn sps(&mut self) -> SpsW<'_, UartCtlSpec> {
6714                SpsW::new(self, 6)
6715            }
6716            #[doc = "Bit 7 - Stop bits: 0=1bit; 1=1.5/2bit"]
6717            #[inline(always)]
6718            pub fn stp(&mut self) -> StpW<'_, UartCtlSpec> {
6719                StpW::new(self, 7)
6720            }
6721        }
6722        #[doc = "UART control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6723        pub struct UartCtlSpec;
6724        impl crate::RegisterSpec for UartCtlSpec {
6725            type Ux = u16;
6726        }
6727        #[doc = "`read()` method returns [`uart_ctl::R`](R) reader structure"]
6728        impl crate::Readable for UartCtlSpec {}
6729        #[doc = "`write(|w| ..)` method takes [`uart_ctl::W`](W) writer structure"]
6730        impl crate::Writable for UartCtlSpec {
6731            type Safety = crate::Unsafe;
6732        }
6733        #[doc = "`reset()` method sets UART_CTL to value 0"]
6734        impl crate::Resettable for UartCtlSpec {}
6735    }
6736    #[doc = "DIV_H (rw) register accessor: Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_h`] module"]
6737    #[doc(alias = "DIV_H")]
6738    pub type DivH = crate::Reg<div_h::DivHSpec>;
6739    #[doc = "Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
6740    pub mod div_h {
6741        #[doc = "Register `DIV_H` reader"]
6742        pub type R = crate::R<DivHSpec>;
6743        #[doc = "Register `DIV_H` writer"]
6744        pub type W = crate::W<DivHSpec>;
6745        #[doc = "Field `div_h` reader - Divider integer high 8 bits"]
6746        pub type DivHR = crate::FieldReader;
6747        #[doc = "Field `div_h` writer - Divider integer high 8 bits"]
6748        pub type DivHW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
6749        impl R {
6750            #[doc = "Bits 0:7 - Divider integer high 8 bits"]
6751            #[inline(always)]
6752            pub fn div_h(&self) -> DivHR {
6753                DivHR::new((self.bits & 0xff) as u8)
6754            }
6755        }
6756        impl W {
6757            #[doc = "Bits 0:7 - Divider integer high 8 bits"]
6758            #[inline(always)]
6759            pub fn div_h(&mut self) -> DivHW<'_, DivHSpec> {
6760                DivHW::new(self, 0)
6761            }
6762        }
6763        #[doc = "Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6764        pub struct DivHSpec;
6765        impl crate::RegisterSpec for DivHSpec {
6766            type Ux = u16;
6767        }
6768        #[doc = "`read()` method returns [`div_h::R`](R) reader structure"]
6769        impl crate::Readable for DivHSpec {}
6770        #[doc = "`write(|w| ..)` method takes [`div_h::W`](W) writer structure"]
6771        impl crate::Writable for DivHSpec {
6772            type Safety = crate::Unsafe;
6773        }
6774        #[doc = "`reset()` method sets DIV_H to value 0"]
6775        impl crate::Resettable for DivHSpec {}
6776    }
6777    #[doc = "DIV_L (rw) register accessor: Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_l`] module"]
6778    #[doc(alias = "DIV_L")]
6779    pub type DivL = crate::Reg<div_l::DivLSpec>;
6780    #[doc = "Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
6781    pub mod div_l {
6782        #[doc = "Register `DIV_L` reader"]
6783        pub type R = crate::R<DivLSpec>;
6784        #[doc = "Register `DIV_L` writer"]
6785        pub type W = crate::W<DivLSpec>;
6786        #[doc = "Field `div_l` reader - Divider integer low 8 bits"]
6787        pub type DivLR = crate::FieldReader;
6788        #[doc = "Field `div_l` writer - Divider integer low 8 bits"]
6789        pub type DivLW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
6790        impl R {
6791            #[doc = "Bits 0:7 - Divider integer low 8 bits"]
6792            #[inline(always)]
6793            pub fn div_l(&self) -> DivLR {
6794                DivLR::new((self.bits & 0xff) as u8)
6795            }
6796        }
6797        impl W {
6798            #[doc = "Bits 0:7 - Divider integer low 8 bits"]
6799            #[inline(always)]
6800            pub fn div_l(&mut self) -> DivLW<'_, DivLSpec> {
6801                DivLW::new(self, 0)
6802            }
6803        }
6804        #[doc = "Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6805        pub struct DivLSpec;
6806        impl crate::RegisterSpec for DivLSpec {
6807            type Ux = u16;
6808        }
6809        #[doc = "`read()` method returns [`div_l::R`](R) reader structure"]
6810        impl crate::Readable for DivLSpec {}
6811        #[doc = "`write(|w| ..)` method takes [`div_l::W`](W) writer structure"]
6812        impl crate::Writable for DivLSpec {
6813            type Safety = crate::Unsafe;
6814        }
6815        #[doc = "`reset()` method sets DIV_L to value 0"]
6816        impl crate::Resettable for DivLSpec {}
6817    }
6818    #[doc = "DIV_FRA (rw) register accessor: Baud rate divider fractional part\n\nYou can [`read`](crate::Reg::read) this register and get [`div_fra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_fra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_fra`] module"]
6819    #[doc(alias = "DIV_FRA")]
6820    pub type DivFra = crate::Reg<div_fra::DivFraSpec>;
6821    #[doc = "Baud rate divider fractional part"]
6822    pub mod div_fra {
6823        #[doc = "Register `DIV_FRA` reader"]
6824        pub type R = crate::R<DivFraSpec>;
6825        #[doc = "Register `DIV_FRA` writer"]
6826        pub type W = crate::W<DivFraSpec>;
6827        #[doc = "Field `div_fra` reader - Divider fractional part (divided by 2^6)"]
6828        pub type DivFraR = crate::FieldReader;
6829        #[doc = "Field `div_fra` writer - Divider fractional part (divided by 2^6)"]
6830        pub type DivFraW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
6831        impl R {
6832            #[doc = "Bits 0:5 - Divider fractional part (divided by 2^6)"]
6833            #[inline(always)]
6834            pub fn div_fra(&self) -> DivFraR {
6835                DivFraR::new((self.bits & 0x3f) as u8)
6836            }
6837        }
6838        impl W {
6839            #[doc = "Bits 0:5 - Divider fractional part (divided by 2^6)"]
6840            #[inline(always)]
6841            pub fn div_fra(&mut self) -> DivFraW<'_, DivFraSpec> {
6842                DivFraW::new(self, 0)
6843            }
6844        }
6845        #[doc = "Baud rate divider fractional part\n\nYou can [`read`](crate::Reg::read) this register and get [`div_fra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_fra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6846        pub struct DivFraSpec;
6847        impl crate::RegisterSpec for DivFraSpec {
6848            type Ux = u16;
6849        }
6850        #[doc = "`read()` method returns [`div_fra::R`](R) reader structure"]
6851        impl crate::Readable for DivFraSpec {}
6852        #[doc = "`write(|w| ..)` method takes [`div_fra::W`](W) writer structure"]
6853        impl crate::Writable for DivFraSpec {
6854            type Safety = crate::Unsafe;
6855        }
6856        #[doc = "`reset()` method sets DIV_FRA to value 0"]
6857        impl crate::Resettable for DivFraSpec {}
6858    }
6859    #[doc = "INTR_EN (rw) register accessor: Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_en`] module"]
6860    #[doc(alias = "INTR_EN")]
6861    pub type IntrEn = crate::Reg<intr_en::IntrEnSpec>;
6862    #[doc = "Interrupt enable register"]
6863    pub mod intr_en {
6864        #[doc = "Register `INTR_EN` reader"]
6865        pub type R = crate::R<IntrEnSpec>;
6866        #[doc = "Register `INTR_EN` writer"]
6867        pub type W = crate::W<IntrEnSpec>;
6868        #[doc = "Field `rece_line_stat_intr_en` reader - RX line status interrupt enable"]
6869        pub type ReceLineStatIntrEnR = crate::BitReader;
6870        #[doc = "Field `rece_line_stat_intr_en` writer - RX line status interrupt enable"]
6871        pub type ReceLineStatIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
6872        #[doc = "Field `modem_intr_en` reader - Modem status interrupt enable"]
6873        pub type ModemIntrEnR = crate::BitReader;
6874        #[doc = "Field `modem_intr_en` writer - Modem status interrupt enable"]
6875        pub type ModemIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
6876        #[doc = "Field `rece_data_intr_en` reader - RX data available interrupt enable"]
6877        pub type ReceDataIntrEnR = crate::BitReader;
6878        #[doc = "Field `rece_data_intr_en` writer - RX data available interrupt enable"]
6879        pub type ReceDataIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
6880        #[doc = "Field `tran_em_intr_en` reader - TX empty interrupt enable"]
6881        pub type TranEmIntrEnR = crate::BitReader;
6882        #[doc = "Field `tran_em_intr_en` writer - TX empty interrupt enable"]
6883        pub type TranEmIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
6884        #[doc = "Field `ptim_en` reader - Programmable THRE interrupt mode enable"]
6885        pub type PtimEnR = crate::BitReader;
6886        #[doc = "Field `ptim_en` writer - Programmable THRE interrupt mode enable"]
6887        pub type PtimEnW<'a, REG> = crate::BitWriter<'a, REG>;
6888        impl R {
6889            #[doc = "Bit 0 - RX line status interrupt enable"]
6890            #[inline(always)]
6891            pub fn rece_line_stat_intr_en(&self) -> ReceLineStatIntrEnR {
6892                ReceLineStatIntrEnR::new((self.bits & 1) != 0)
6893            }
6894            #[doc = "Bit 1 - Modem status interrupt enable"]
6895            #[inline(always)]
6896            pub fn modem_intr_en(&self) -> ModemIntrEnR {
6897                ModemIntrEnR::new(((self.bits >> 1) & 1) != 0)
6898            }
6899            #[doc = "Bit 2 - RX data available interrupt enable"]
6900            #[inline(always)]
6901            pub fn rece_data_intr_en(&self) -> ReceDataIntrEnR {
6902                ReceDataIntrEnR::new(((self.bits >> 2) & 1) != 0)
6903            }
6904            #[doc = "Bit 3 - TX empty interrupt enable"]
6905            #[inline(always)]
6906            pub fn tran_em_intr_en(&self) -> TranEmIntrEnR {
6907                TranEmIntrEnR::new(((self.bits >> 3) & 1) != 0)
6908            }
6909            #[doc = "Bit 4 - Programmable THRE interrupt mode enable"]
6910            #[inline(always)]
6911            pub fn ptim_en(&self) -> PtimEnR {
6912                PtimEnR::new(((self.bits >> 4) & 1) != 0)
6913            }
6914        }
6915        impl W {
6916            #[doc = "Bit 0 - RX line status interrupt enable"]
6917            #[inline(always)]
6918            pub fn rece_line_stat_intr_en(&mut self) -> ReceLineStatIntrEnW<'_, IntrEnSpec> {
6919                ReceLineStatIntrEnW::new(self, 0)
6920            }
6921            #[doc = "Bit 1 - Modem status interrupt enable"]
6922            #[inline(always)]
6923            pub fn modem_intr_en(&mut self) -> ModemIntrEnW<'_, IntrEnSpec> {
6924                ModemIntrEnW::new(self, 1)
6925            }
6926            #[doc = "Bit 2 - RX data available interrupt enable"]
6927            #[inline(always)]
6928            pub fn rece_data_intr_en(&mut self) -> ReceDataIntrEnW<'_, IntrEnSpec> {
6929                ReceDataIntrEnW::new(self, 2)
6930            }
6931            #[doc = "Bit 3 - TX empty interrupt enable"]
6932            #[inline(always)]
6933            pub fn tran_em_intr_en(&mut self) -> TranEmIntrEnW<'_, IntrEnSpec> {
6934                TranEmIntrEnW::new(self, 3)
6935            }
6936            #[doc = "Bit 4 - Programmable THRE interrupt mode enable"]
6937            #[inline(always)]
6938            pub fn ptim_en(&mut self) -> PtimEnW<'_, IntrEnSpec> {
6939                PtimEnW::new(self, 4)
6940            }
6941        }
6942        #[doc = "Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6943        pub struct IntrEnSpec;
6944        impl crate::RegisterSpec for IntrEnSpec {
6945            type Ux = u16;
6946        }
6947        #[doc = "`read()` method returns [`intr_en::R`](R) reader structure"]
6948        impl crate::Readable for IntrEnSpec {}
6949        #[doc = "`write(|w| ..)` method takes [`intr_en::W`](W) writer structure"]
6950        impl crate::Writable for IntrEnSpec {
6951            type Safety = crate::Unsafe;
6952        }
6953        #[doc = "`reset()` method sets INTR_EN to value 0"]
6954        impl crate::Resettable for IntrEnSpec {}
6955    }
6956    #[doc = "INTR_STATUS (rw) register accessor: Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status`] module"]
6957    #[doc(alias = "INTR_STATUS")]
6958    pub type IntrStatus = crate::Reg<intr_status::IntrStatusSpec>;
6959    #[doc = "Interrupt status register"]
6960    pub mod intr_status {
6961        #[doc = "Register `INTR_STATUS` reader"]
6962        pub type R = crate::R<IntrStatusSpec>;
6963        #[doc = "Register `INTR_STATUS` writer"]
6964        pub type W = crate::W<IntrStatusSpec>;
6965        #[doc = "Field `busy_det_intr` reader - Busy detect interrupt status"]
6966        pub type BusyDetIntrR = crate::BitReader;
6967        #[doc = "Field `modem_intr_status` reader - Modem interrupt status"]
6968        pub type ModemIntrStatusR = crate::BitReader;
6969        #[doc = "Field `thre_intr_status` reader - THR empty interrupt status"]
6970        pub type ThreIntrStatusR = crate::BitReader;
6971        #[doc = "Field `char_to_intr_status` reader - Character timeout interrupt status"]
6972        pub type CharToIntrStatusR = crate::BitReader;
6973        #[doc = "Field `data_avail_intr_status` reader - RX data available interrupt status"]
6974        pub type DataAvailIntrStatusR = crate::BitReader;
6975        #[doc = "Field `line_intr_status` reader - RX line interrupt status"]
6976        pub type LineIntrStatusR = crate::BitReader;
6977        impl R {
6978            #[doc = "Bit 0 - Busy detect interrupt status"]
6979            #[inline(always)]
6980            pub fn busy_det_intr(&self) -> BusyDetIntrR {
6981                BusyDetIntrR::new((self.bits & 1) != 0)
6982            }
6983            #[doc = "Bit 1 - Modem interrupt status"]
6984            #[inline(always)]
6985            pub fn modem_intr_status(&self) -> ModemIntrStatusR {
6986                ModemIntrStatusR::new(((self.bits >> 1) & 1) != 0)
6987            }
6988            #[doc = "Bit 2 - THR empty interrupt status"]
6989            #[inline(always)]
6990            pub fn thre_intr_status(&self) -> ThreIntrStatusR {
6991                ThreIntrStatusR::new(((self.bits >> 2) & 1) != 0)
6992            }
6993            #[doc = "Bit 3 - Character timeout interrupt status"]
6994            #[inline(always)]
6995            pub fn char_to_intr_status(&self) -> CharToIntrStatusR {
6996                CharToIntrStatusR::new(((self.bits >> 3) & 1) != 0)
6997            }
6998            #[doc = "Bit 4 - RX data available interrupt status"]
6999            #[inline(always)]
7000            pub fn data_avail_intr_status(&self) -> DataAvailIntrStatusR {
7001                DataAvailIntrStatusR::new(((self.bits >> 4) & 1) != 0)
7002            }
7003            #[doc = "Bit 5 - RX line interrupt status"]
7004            #[inline(always)]
7005            pub fn line_intr_status(&self) -> LineIntrStatusR {
7006                LineIntrStatusR::new(((self.bits >> 5) & 1) != 0)
7007            }
7008        }
7009        impl W {}
7010        #[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7011        pub struct IntrStatusSpec;
7012        impl crate::RegisterSpec for IntrStatusSpec {
7013            type Ux = u16;
7014        }
7015        #[doc = "`read()` method returns [`intr_status::R`](R) reader structure"]
7016        impl crate::Readable for IntrStatusSpec {}
7017        #[doc = "`write(|w| ..)` method takes [`intr_status::W`](W) writer structure"]
7018        impl crate::Writable for IntrStatusSpec {
7019            type Safety = crate::Unsafe;
7020        }
7021        #[doc = "`reset()` method sets INTR_STATUS to value 0"]
7022        impl crate::Resettable for IntrStatusSpec {}
7023    }
7024    #[doc = "FIFO_CTL (rw) register accessor: FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_ctl`] module"]
7025    #[doc(alias = "FIFO_CTL")]
7026    pub type FifoCtl = crate::Reg<fifo_ctl::FifoCtlSpec>;
7027    #[doc = "FIFO control register"]
7028    pub mod fifo_ctl {
7029        #[doc = "Register `FIFO_CTL` reader"]
7030        pub type R = crate::R<FifoCtlSpec>;
7031        #[doc = "Register `FIFO_CTL` writer"]
7032        pub type W = crate::W<FifoCtlSpec>;
7033        #[doc = "TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2\n\nValue on reset: 0"]
7034        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
7035        #[repr(u8)]
7036        pub enum TxEmptyTrig {
7037            #[doc = "0: FIFO empty"]
7038            Empty = 0,
7039            #[doc = "1: 2 characters remaining"]
7040            Chars2 = 1,
7041            #[doc = "2: FIFO 1/4 full"]
7042            Quarter = 2,
7043            #[doc = "3: FIFO 1/2 full"]
7044            Half = 3,
7045        }
7046        impl From<TxEmptyTrig> for u8 {
7047            #[inline(always)]
7048            fn from(variant: TxEmptyTrig) -> Self {
7049                variant as _
7050            }
7051        }
7052        impl crate::FieldSpec for TxEmptyTrig {
7053            type Ux = u8;
7054        }
7055        impl crate::IsEnum for TxEmptyTrig {}
7056        #[doc = "Field `tx_empty_trig` writer - TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2"]
7057        pub type TxEmptyTrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, TxEmptyTrig, crate::Safe>;
7058        impl<'a, REG> TxEmptyTrigW<'a, REG>
7059        where
7060            REG: crate::Writable + crate::RegisterSpec,
7061            REG::Ux: From<u8>,
7062        {
7063            #[doc = "FIFO empty"]
7064            #[inline(always)]
7065            pub fn empty(self) -> &'a mut crate::W<REG> {
7066                self.variant(TxEmptyTrig::Empty)
7067            }
7068            #[doc = "2 characters remaining"]
7069            #[inline(always)]
7070            pub fn chars2(self) -> &'a mut crate::W<REG> {
7071                self.variant(TxEmptyTrig::Chars2)
7072            }
7073            #[doc = "FIFO 1/4 full"]
7074            #[inline(always)]
7075            pub fn quarter(self) -> &'a mut crate::W<REG> {
7076                self.variant(TxEmptyTrig::Quarter)
7077            }
7078            #[doc = "FIFO 1/2 full"]
7079            #[inline(always)]
7080            pub fn half(self) -> &'a mut crate::W<REG> {
7081                self.variant(TxEmptyTrig::Half)
7082            }
7083        }
7084        #[doc = "RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full\n\nValue on reset: 0"]
7085        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
7086        #[repr(u8)]
7087        pub enum RxEmptyTrig {
7088            #[doc = "0: 1 character in FIFO"]
7089            Char1 = 0,
7090            #[doc = "1: FIFO 1/4 full"]
7091            Quarter = 1,
7092            #[doc = "2: FIFO 1/2 full"]
7093            Half = 2,
7094            #[doc = "3: 2 below full"]
7095            Less2 = 3,
7096        }
7097        impl From<RxEmptyTrig> for u8 {
7098            #[inline(always)]
7099            fn from(variant: RxEmptyTrig) -> Self {
7100                variant as _
7101            }
7102        }
7103        impl crate::FieldSpec for RxEmptyTrig {
7104            type Ux = u8;
7105        }
7106        impl crate::IsEnum for RxEmptyTrig {}
7107        #[doc = "Field `rx_empty_trig` writer - RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full"]
7108        pub type RxEmptyTrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, RxEmptyTrig, crate::Safe>;
7109        impl<'a, REG> RxEmptyTrigW<'a, REG>
7110        where
7111            REG: crate::Writable + crate::RegisterSpec,
7112            REG::Ux: From<u8>,
7113        {
7114            #[doc = "1 character in FIFO"]
7115            #[inline(always)]
7116            pub fn char1(self) -> &'a mut crate::W<REG> {
7117                self.variant(RxEmptyTrig::Char1)
7118            }
7119            #[doc = "FIFO 1/4 full"]
7120            #[inline(always)]
7121            pub fn quarter(self) -> &'a mut crate::W<REG> {
7122                self.variant(RxEmptyTrig::Quarter)
7123            }
7124            #[doc = "FIFO 1/2 full"]
7125            #[inline(always)]
7126            pub fn half(self) -> &'a mut crate::W<REG> {
7127                self.variant(RxEmptyTrig::Half)
7128            }
7129            #[doc = "2 below full"]
7130            #[inline(always)]
7131            pub fn less2(self) -> &'a mut crate::W<REG> {
7132                self.variant(RxEmptyTrig::Less2)
7133            }
7134        }
7135        #[doc = "Field `fifo_en` writer - FIFO enable"]
7136        pub type FifoEnW<'a, REG> = crate::BitWriter<'a, REG>;
7137        #[doc = "Field `tx_fifo_rst` writer - TX FIFO reset: 0=no reset; 1=reset"]
7138        pub type TxFifoRstW<'a, REG> = crate::BitWriter<'a, REG>;
7139        #[doc = "Field `rx_fifo_rst` writer - RX FIFO reset: 0=no reset; 1=reset"]
7140        pub type RxFifoRstW<'a, REG> = crate::BitWriter<'a, REG>;
7141        impl W {
7142            #[doc = "Bits 0:1 - TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2"]
7143            #[inline(always)]
7144            pub fn tx_empty_trig(&mut self) -> TxEmptyTrigW<'_, FifoCtlSpec> {
7145                TxEmptyTrigW::new(self, 0)
7146            }
7147            #[doc = "Bits 2:3 - RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full"]
7148            #[inline(always)]
7149            pub fn rx_empty_trig(&mut self) -> RxEmptyTrigW<'_, FifoCtlSpec> {
7150                RxEmptyTrigW::new(self, 2)
7151            }
7152            #[doc = "Bit 4 - FIFO enable"]
7153            #[inline(always)]
7154            pub fn fifo_en(&mut self) -> FifoEnW<'_, FifoCtlSpec> {
7155                FifoEnW::new(self, 4)
7156            }
7157            #[doc = "Bit 5 - TX FIFO reset: 0=no reset; 1=reset"]
7158            #[inline(always)]
7159            pub fn tx_fifo_rst(&mut self) -> TxFifoRstW<'_, FifoCtlSpec> {
7160                TxFifoRstW::new(self, 5)
7161            }
7162            #[doc = "Bit 6 - RX FIFO reset: 0=no reset; 1=reset"]
7163            #[inline(always)]
7164            pub fn rx_fifo_rst(&mut self) -> RxFifoRstW<'_, FifoCtlSpec> {
7165                RxFifoRstW::new(self, 6)
7166            }
7167        }
7168        #[doc = "FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7169        pub struct FifoCtlSpec;
7170        impl crate::RegisterSpec for FifoCtlSpec {
7171            type Ux = u16;
7172        }
7173        #[doc = "`read()` method returns [`fifo_ctl::R`](R) reader structure"]
7174        impl crate::Readable for FifoCtlSpec {}
7175        #[doc = "`write(|w| ..)` method takes [`fifo_ctl::W`](W) writer structure"]
7176        impl crate::Writable for FifoCtlSpec {
7177            type Safety = crate::Unsafe;
7178        }
7179        #[doc = "`reset()` method sets FIFO_CTL to value 0"]
7180        impl crate::Resettable for FifoCtlSpec {}
7181    }
7182    #[doc = "FAR (rw) register accessor: FIFO access mode enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"]
7183    #[doc(alias = "FAR")]
7184    pub type Far = crate::Reg<far::FarSpec>;
7185    #[doc = "FIFO access mode enable register"]
7186    pub mod far {
7187        #[doc = "Register `FAR` reader"]
7188        pub type R = crate::R<FarSpec>;
7189        #[doc = "Register `FAR` writer"]
7190        pub type W = crate::W<FarSpec>;
7191        #[doc = "Field `far` reader - FIFO access mode: 0=disabled; 1=enabled"]
7192        pub type FarR = crate::BitReader;
7193        #[doc = "Field `far` writer - FIFO access mode: 0=disabled; 1=enabled"]
7194        pub type FarW<'a, REG> = crate::BitWriter<'a, REG>;
7195        impl R {
7196            #[doc = "Bit 0 - FIFO access mode: 0=disabled; 1=enabled"]
7197            #[inline(always)]
7198            pub fn far(&self) -> FarR {
7199                FarR::new((self.bits & 1) != 0)
7200            }
7201        }
7202        impl W {
7203            #[doc = "Bit 0 - FIFO access mode: 0=disabled; 1=enabled"]
7204            #[inline(always)]
7205            pub fn far(&mut self) -> FarW<'_, FarSpec> {
7206                FarW::new(self, 0)
7207            }
7208        }
7209        #[doc = "FIFO access mode enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`far::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`far::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7210        pub struct FarSpec;
7211        impl crate::RegisterSpec for FarSpec {
7212            type Ux = u16;
7213        }
7214        #[doc = "`read()` method returns [`far::R`](R) reader structure"]
7215        impl crate::Readable for FarSpec {}
7216        #[doc = "`write(|w| ..)` method takes [`far::W`](W) writer structure"]
7217        impl crate::Writable for FarSpec {
7218            type Safety = crate::Unsafe;
7219        }
7220        #[doc = "`reset()` method sets FAR to value 0"]
7221        impl crate::Resettable for FarSpec {}
7222    }
7223    #[doc = "MODEM_CTL (rw) register accessor: Modem control register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modem_ctl`] module"]
7224    #[doc(alias = "MODEM_CTL")]
7225    pub type ModemCtl = crate::Reg<modem_ctl::ModemCtlSpec>;
7226    #[doc = "Modem control register"]
7227    pub mod modem_ctl {
7228        #[doc = "Register `MODEM_CTL` reader"]
7229        pub type R = crate::R<ModemCtlSpec>;
7230        #[doc = "Register `MODEM_CTL` writer"]
7231        pub type W = crate::W<ModemCtlSpec>;
7232        #[doc = "Field `afc_en` reader - Auto flow control enable"]
7233        pub type AfcEnR = crate::BitReader;
7234        #[doc = "Field `afc_en` writer - Auto flow control enable"]
7235        pub type AfcEnW<'a, REG> = crate::BitWriter<'a, REG>;
7236        #[doc = "Field `lb_mode` reader - Loopback mode: 0=disabled; 1=enabled"]
7237        pub type LbModeR = crate::BitReader;
7238        #[doc = "Field `lb_mode` writer - Loopback mode: 0=disabled; 1=enabled"]
7239        pub type LbModeW<'a, REG> = crate::BitWriter<'a, REG>;
7240        #[doc = "Field `rts` reader - RTS software control"]
7241        pub type RtsR = crate::BitReader;
7242        #[doc = "Field `rts` writer - RTS software control"]
7243        pub type RtsW<'a, REG> = crate::BitWriter<'a, REG>;
7244        impl R {
7245            #[doc = "Bit 0 - Auto flow control enable"]
7246            #[inline(always)]
7247            pub fn afc_en(&self) -> AfcEnR {
7248                AfcEnR::new((self.bits & 1) != 0)
7249            }
7250            #[doc = "Bit 1 - Loopback mode: 0=disabled; 1=enabled"]
7251            #[inline(always)]
7252            pub fn lb_mode(&self) -> LbModeR {
7253                LbModeR::new(((self.bits >> 1) & 1) != 0)
7254            }
7255            #[doc = "Bit 2 - RTS software control"]
7256            #[inline(always)]
7257            pub fn rts(&self) -> RtsR {
7258                RtsR::new(((self.bits >> 2) & 1) != 0)
7259            }
7260        }
7261        impl W {
7262            #[doc = "Bit 0 - Auto flow control enable"]
7263            #[inline(always)]
7264            pub fn afc_en(&mut self) -> AfcEnW<'_, ModemCtlSpec> {
7265                AfcEnW::new(self, 0)
7266            }
7267            #[doc = "Bit 1 - Loopback mode: 0=disabled; 1=enabled"]
7268            #[inline(always)]
7269            pub fn lb_mode(&mut self) -> LbModeW<'_, ModemCtlSpec> {
7270                LbModeW::new(self, 1)
7271            }
7272            #[doc = "Bit 2 - RTS software control"]
7273            #[inline(always)]
7274            pub fn rts(&mut self) -> RtsW<'_, ModemCtlSpec> {
7275                RtsW::new(self, 2)
7276            }
7277        }
7278        #[doc = "Modem control register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7279        pub struct ModemCtlSpec;
7280        impl crate::RegisterSpec for ModemCtlSpec {
7281            type Ux = u16;
7282        }
7283        #[doc = "`read()` method returns [`modem_ctl::R`](R) reader structure"]
7284        impl crate::Readable for ModemCtlSpec {}
7285        #[doc = "`write(|w| ..)` method takes [`modem_ctl::W`](W) writer structure"]
7286        impl crate::Writable for ModemCtlSpec {
7287            type Safety = crate::Unsafe;
7288        }
7289        #[doc = "`reset()` method sets MODEM_CTL to value 0"]
7290        impl crate::Resettable for ModemCtlSpec {}
7291    }
7292    #[doc = "MODEM_STATUS (rw) register accessor: Modem status register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modem_status`] module"]
7293    #[doc(alias = "MODEM_STATUS")]
7294    pub type ModemStatus = crate::Reg<modem_status::ModemStatusSpec>;
7295    #[doc = "Modem status register"]
7296    pub mod modem_status {
7297        #[doc = "Register `MODEM_STATUS` reader"]
7298        pub type R = crate::R<ModemStatusSpec>;
7299        #[doc = "Register `MODEM_STATUS` writer"]
7300        pub type W = crate::W<ModemStatusSpec>;
7301        #[doc = "Field `dcts` reader - CTS change indicator"]
7302        pub type DctsR = crate::BitReader;
7303        #[doc = "Field `cts` reader - CTS signal state"]
7304        pub type CtsR = crate::BitReader;
7305        impl R {
7306            #[doc = "Bit 0 - CTS change indicator"]
7307            #[inline(always)]
7308            pub fn dcts(&self) -> DctsR {
7309                DctsR::new((self.bits & 1) != 0)
7310            }
7311            #[doc = "Bit 1 - CTS signal state"]
7312            #[inline(always)]
7313            pub fn cts(&self) -> CtsR {
7314                CtsR::new(((self.bits >> 1) & 1) != 0)
7315            }
7316        }
7317        impl W {}
7318        #[doc = "Modem status register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7319        pub struct ModemStatusSpec;
7320        impl crate::RegisterSpec for ModemStatusSpec {
7321            type Ux = u16;
7322        }
7323        #[doc = "`read()` method returns [`modem_status::R`](R) reader structure"]
7324        impl crate::Readable for ModemStatusSpec {}
7325        #[doc = "`write(|w| ..)` method takes [`modem_status::W`](W) writer structure"]
7326        impl crate::Writable for ModemStatusSpec {
7327            type Safety = crate::Unsafe;
7328        }
7329        #[doc = "`reset()` method sets MODEM_STATUS to value 0"]
7330        impl crate::Resettable for ModemStatusSpec {}
7331    }
7332    #[doc = "LINE_STATUS (rw) register accessor: Line status register\n\nYou can [`read`](crate::Reg::read) this register and get [`line_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`line_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@line_status`] module"]
7333    #[doc(alias = "LINE_STATUS")]
7334    pub type LineStatus = crate::Reg<line_status::LineStatusSpec>;
7335    #[doc = "Line status register"]
7336    pub mod line_status {
7337        #[doc = "Register `LINE_STATUS` reader"]
7338        pub type R = crate::R<LineStatusSpec>;
7339        #[doc = "Register `LINE_STATUS` writer"]
7340        pub type W = crate::W<LineStatusSpec>;
7341        #[doc = "Field `rx_fifo_err` reader - RX FIFO error status"]
7342        pub type RxFifoErrR = crate::BitReader;
7343        #[doc = "Field `frame_err` reader - Framing error"]
7344        pub type FrameErrR = crate::BitReader;
7345        #[doc = "Field `parity_err` reader - Parity error"]
7346        pub type ParityErrR = crate::BitReader;
7347        #[doc = "Field `overrun_err` reader - Overrun error"]
7348        pub type OverrunErrR = crate::BitReader;
7349        #[doc = "Field `break_intr` reader - Break interrupt"]
7350        pub type BreakIntrR = crate::BitReader;
7351        #[doc = "Field `data_available` reader - Data available in RX FIFO/RBR"]
7352        pub type DataAvailableR = crate::BitReader;
7353        #[doc = "Field `thre_s` reader - THR empty flag"]
7354        pub type ThreSR = crate::BitReader;
7355        #[doc = "Field `tx_empty_s` reader - Transmitter empty flag"]
7356        pub type TxEmptySR = crate::BitReader;
7357        impl R {
7358            #[doc = "Bit 0 - RX FIFO error status"]
7359            #[inline(always)]
7360            pub fn rx_fifo_err(&self) -> RxFifoErrR {
7361                RxFifoErrR::new((self.bits & 1) != 0)
7362            }
7363            #[doc = "Bit 1 - Framing error"]
7364            #[inline(always)]
7365            pub fn frame_err(&self) -> FrameErrR {
7366                FrameErrR::new(((self.bits >> 1) & 1) != 0)
7367            }
7368            #[doc = "Bit 2 - Parity error"]
7369            #[inline(always)]
7370            pub fn parity_err(&self) -> ParityErrR {
7371                ParityErrR::new(((self.bits >> 2) & 1) != 0)
7372            }
7373            #[doc = "Bit 3 - Overrun error"]
7374            #[inline(always)]
7375            pub fn overrun_err(&self) -> OverrunErrR {
7376                OverrunErrR::new(((self.bits >> 3) & 1) != 0)
7377            }
7378            #[doc = "Bit 4 - Break interrupt"]
7379            #[inline(always)]
7380            pub fn break_intr(&self) -> BreakIntrR {
7381                BreakIntrR::new(((self.bits >> 4) & 1) != 0)
7382            }
7383            #[doc = "Bit 5 - Data available in RX FIFO/RBR"]
7384            #[inline(always)]
7385            pub fn data_available(&self) -> DataAvailableR {
7386                DataAvailableR::new(((self.bits >> 5) & 1) != 0)
7387            }
7388            #[doc = "Bit 6 - THR empty flag"]
7389            #[inline(always)]
7390            pub fn thre_s(&self) -> ThreSR {
7391                ThreSR::new(((self.bits >> 6) & 1) != 0)
7392            }
7393            #[doc = "Bit 7 - Transmitter empty flag"]
7394            #[inline(always)]
7395            pub fn tx_empty_s(&self) -> TxEmptySR {
7396                TxEmptySR::new(((self.bits >> 7) & 1) != 0)
7397            }
7398        }
7399        impl W {}
7400        #[doc = "Line status register\n\nYou can [`read`](crate::Reg::read) this register and get [`line_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`line_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7401        pub struct LineStatusSpec;
7402        impl crate::RegisterSpec for LineStatusSpec {
7403            type Ux = u16;
7404        }
7405        #[doc = "`read()` method returns [`line_status::R`](R) reader structure"]
7406        impl crate::Readable for LineStatusSpec {}
7407        #[doc = "`write(|w| ..)` method takes [`line_status::W`](W) writer structure"]
7408        impl crate::Writable for LineStatusSpec {
7409            type Safety = crate::Unsafe;
7410        }
7411        #[doc = "`reset()` method sets LINE_STATUS to value 0xc0"]
7412        impl crate::Resettable for LineStatusSpec {
7413            const RESET_VALUE: u16 = 0xc0;
7414        }
7415    }
7416    #[doc = "UART_GP_REG (rw) register accessor: UART general purpose register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_gp_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_gp_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_gp_reg`] module"]
7417    #[doc(alias = "UART_GP_REG")]
7418    pub type UartGpReg = crate::Reg<uart_gp_reg::UartGpRegSpec>;
7419    #[doc = "UART general purpose register"]
7420    pub mod uart_gp_reg {
7421        #[doc = "Register `UART_GP_REG` reader"]
7422        pub type R = crate::R<UartGpRegSpec>;
7423        #[doc = "Register `UART_GP_REG` writer"]
7424        pub type W = crate::W<UartGpRegSpec>;
7425        #[doc = "Field `uart_gp_reg` reader - General purpose storage"]
7426        pub type UartGpRegR = crate::FieldReader;
7427        #[doc = "Field `uart_gp_reg` writer - General purpose storage"]
7428        pub type UartGpRegW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
7429        impl R {
7430            #[doc = "Bits 0:7 - General purpose storage"]
7431            #[inline(always)]
7432            pub fn uart_gp_reg(&self) -> UartGpRegR {
7433                UartGpRegR::new((self.bits & 0xff) as u8)
7434            }
7435        }
7436        impl W {
7437            #[doc = "Bits 0:7 - General purpose storage"]
7438            #[inline(always)]
7439            pub fn uart_gp_reg(&mut self) -> UartGpRegW<'_, UartGpRegSpec> {
7440                UartGpRegW::new(self, 0)
7441            }
7442        }
7443        #[doc = "UART general purpose register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_gp_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_gp_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7444        pub struct UartGpRegSpec;
7445        impl crate::RegisterSpec for UartGpRegSpec {
7446            type Ux = u16;
7447        }
7448        #[doc = "`read()` method returns [`uart_gp_reg::R`](R) reader structure"]
7449        impl crate::Readable for UartGpRegSpec {}
7450        #[doc = "`write(|w| ..)` method takes [`uart_gp_reg::W`](W) writer structure"]
7451        impl crate::Writable for UartGpRegSpec {
7452            type Safety = crate::Unsafe;
7453        }
7454        #[doc = "`reset()` method sets UART_GP_REG to value 0"]
7455        impl crate::Resettable for UartGpRegSpec {}
7456    }
7457    #[doc = "TX_FIFO_READ (rw) register accessor: TX FIFO read register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_read::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_read::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_fifo_read`] module"]
7458    #[doc(alias = "TX_FIFO_READ")]
7459    pub type TxFifoRead = crate::Reg<tx_fifo_read::TxFifoReadSpec>;
7460    #[doc = "TX FIFO read register"]
7461    pub mod tx_fifo_read {
7462        #[doc = "Register `TX_FIFO_READ` reader"]
7463        pub type R = crate::R<TxFifoReadSpec>;
7464        #[doc = "Register `TX_FIFO_READ` writer"]
7465        pub type W = crate::W<TxFifoReadSpec>;
7466        #[doc = "Field `tx_fifo_read` reader - TX FIFO top data"]
7467        pub type TxFifoReadR = crate::FieldReader;
7468        impl R {
7469            #[doc = "Bits 0:7 - TX FIFO top data"]
7470            #[inline(always)]
7471            pub fn tx_fifo_read(&self) -> TxFifoReadR {
7472                TxFifoReadR::new((self.bits & 0xff) as u8)
7473            }
7474        }
7475        impl W {}
7476        #[doc = "TX FIFO read register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_read::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_read::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7477        pub struct TxFifoReadSpec;
7478        impl crate::RegisterSpec for TxFifoReadSpec {
7479            type Ux = u16;
7480        }
7481        #[doc = "`read()` method returns [`tx_fifo_read::R`](R) reader structure"]
7482        impl crate::Readable for TxFifoReadSpec {}
7483        #[doc = "`write(|w| ..)` method takes [`tx_fifo_read::W`](W) writer structure"]
7484        impl crate::Writable for TxFifoReadSpec {
7485            type Safety = crate::Unsafe;
7486        }
7487        #[doc = "`reset()` method sets TX_FIFO_READ to value 0"]
7488        impl crate::Resettable for TxFifoReadSpec {}
7489    }
7490    #[doc = "RX_FIFO_WRITE (rw) register accessor: RX FIFO write register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_write::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_write::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_fifo_write`] module"]
7491    #[doc(alias = "RX_FIFO_WRITE")]
7492    pub type RxFifoWrite = crate::Reg<rx_fifo_write::RxFifoWriteSpec>;
7493    #[doc = "RX FIFO write register"]
7494    pub mod rx_fifo_write {
7495        #[doc = "Register `RX_FIFO_WRITE` reader"]
7496        pub type R = crate::R<RxFifoWriteSpec>;
7497        #[doc = "Register `RX_FIFO_WRITE` writer"]
7498        pub type W = crate::W<RxFifoWriteSpec>;
7499        #[doc = "Field `rx_fifo_write` reader - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
7500        pub type RxFifoWriteR = crate::FieldReader;
7501        #[doc = "Field `rx_fifo_write` writer - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
7502        pub type RxFifoWriteW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
7503        #[doc = "Field `rx_fifo_pe` writer - RX FIFO parity error"]
7504        pub type RxFifoPeW<'a, REG> = crate::BitWriter<'a, REG>;
7505        #[doc = "Field `rx_fifo_fe` writer - RX FIFO framing error"]
7506        pub type RxFifoFeW<'a, REG> = crate::BitWriter<'a, REG>;
7507        impl R {
7508            #[doc = "Bits 0:7 - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
7509            #[inline(always)]
7510            pub fn rx_fifo_write(&self) -> RxFifoWriteR {
7511                RxFifoWriteR::new((self.bits & 0xff) as u8)
7512            }
7513        }
7514        impl W {
7515            #[doc = "Bits 0:7 - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
7516            #[inline(always)]
7517            pub fn rx_fifo_write(&mut self) -> RxFifoWriteW<'_, RxFifoWriteSpec> {
7518                RxFifoWriteW::new(self, 0)
7519            }
7520            #[doc = "Bit 8 - RX FIFO parity error"]
7521            #[inline(always)]
7522            pub fn rx_fifo_pe(&mut self) -> RxFifoPeW<'_, RxFifoWriteSpec> {
7523                RxFifoPeW::new(self, 8)
7524            }
7525            #[doc = "Bit 9 - RX FIFO framing error"]
7526            #[inline(always)]
7527            pub fn rx_fifo_fe(&mut self) -> RxFifoFeW<'_, RxFifoWriteSpec> {
7528                RxFifoFeW::new(self, 9)
7529            }
7530        }
7531        #[doc = "RX FIFO write register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_write::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_write::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7532        pub struct RxFifoWriteSpec;
7533        impl crate::RegisterSpec for RxFifoWriteSpec {
7534            type Ux = u16;
7535        }
7536        #[doc = "`read()` method returns [`rx_fifo_write::R`](R) reader structure"]
7537        impl crate::Readable for RxFifoWriteSpec {}
7538        #[doc = "`write(|w| ..)` method takes [`rx_fifo_write::W`](W) writer structure"]
7539        impl crate::Writable for RxFifoWriteSpec {
7540            type Safety = crate::Unsafe;
7541        }
7542        #[doc = "`reset()` method sets RX_FIFO_WRITE to value 0"]
7543        impl crate::Resettable for RxFifoWriteSpec {}
7544    }
7545    #[doc = "FIFO_STATUS (rw) register accessor: FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_status`] module"]
7546    #[doc(alias = "FIFO_STATUS")]
7547    pub type FifoStatus = crate::Reg<fifo_status::FifoStatusSpec>;
7548    #[doc = "FIFO status register"]
7549    pub mod fifo_status {
7550        #[doc = "Register `FIFO_STATUS` reader"]
7551        pub type R = crate::R<FifoStatusSpec>;
7552        #[doc = "Register `FIFO_STATUS` writer"]
7553        pub type W = crate::W<FifoStatusSpec>;
7554        #[doc = "Field `tx_fifo_full` reader - TX FIFO full flag"]
7555        pub type TxFifoFullR = crate::BitReader;
7556        #[doc = "Field `tx_fifo_empty` reader - TX FIFO empty flag"]
7557        pub type TxFifoEmptyR = crate::BitReader;
7558        #[doc = "Field `rx_fifo_full` reader - RX FIFO full flag"]
7559        pub type RxFifoFullR = crate::BitReader;
7560        #[doc = "Field `rx_fifo_empty` reader - RX FIFO empty flag"]
7561        pub type RxFifoEmptyR = crate::BitReader;
7562        impl R {
7563            #[doc = "Bit 0 - TX FIFO full flag"]
7564            #[inline(always)]
7565            pub fn tx_fifo_full(&self) -> TxFifoFullR {
7566                TxFifoFullR::new((self.bits & 1) != 0)
7567            }
7568            #[doc = "Bit 1 - TX FIFO empty flag"]
7569            #[inline(always)]
7570            pub fn tx_fifo_empty(&self) -> TxFifoEmptyR {
7571                TxFifoEmptyR::new(((self.bits >> 1) & 1) != 0)
7572            }
7573            #[doc = "Bit 2 - RX FIFO full flag"]
7574            #[inline(always)]
7575            pub fn rx_fifo_full(&self) -> RxFifoFullR {
7576                RxFifoFullR::new(((self.bits >> 2) & 1) != 0)
7577            }
7578            #[doc = "Bit 3 - RX FIFO empty flag"]
7579            #[inline(always)]
7580            pub fn rx_fifo_empty(&self) -> RxFifoEmptyR {
7581                RxFifoEmptyR::new(((self.bits >> 3) & 1) != 0)
7582            }
7583        }
7584        impl W {}
7585        #[doc = "FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7586        pub struct FifoStatusSpec;
7587        impl crate::RegisterSpec for FifoStatusSpec {
7588            type Ux = u16;
7589        }
7590        #[doc = "`read()` method returns [`fifo_status::R`](R) reader structure"]
7591        impl crate::Readable for FifoStatusSpec {}
7592        #[doc = "`write(|w| ..)` method takes [`fifo_status::W`](W) writer structure"]
7593        impl crate::Writable for FifoStatusSpec {
7594            type Safety = crate::Unsafe;
7595        }
7596        #[doc = "`reset()` method sets FIFO_STATUS to value 0x02"]
7597        impl crate::Resettable for FifoStatusSpec {
7598            const RESET_VALUE: u16 = 0x02;
7599        }
7600    }
7601    #[doc = "TX_FIFO_CNT (rw) register accessor: TX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_fifo_cnt`] module"]
7602    #[doc(alias = "TX_FIFO_CNT")]
7603    pub type TxFifoCnt = crate::Reg<tx_fifo_cnt::TxFifoCntSpec>;
7604    #[doc = "TX FIFO data counter"]
7605    pub mod tx_fifo_cnt {
7606        #[doc = "Register `TX_FIFO_CNT` reader"]
7607        pub type R = crate::R<TxFifoCntSpec>;
7608        #[doc = "Register `TX_FIFO_CNT` writer"]
7609        pub type W = crate::W<TxFifoCntSpec>;
7610        #[doc = "Field `tx_fifo_level` reader - TX FIFO data count"]
7611        pub type TxFifoLevelR = crate::FieldReader;
7612        impl R {
7613            #[doc = "Bits 0:6 - TX FIFO data count"]
7614            #[inline(always)]
7615            pub fn tx_fifo_level(&self) -> TxFifoLevelR {
7616                TxFifoLevelR::new((self.bits & 0x7f) as u8)
7617            }
7618        }
7619        impl W {}
7620        #[doc = "TX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7621        pub struct TxFifoCntSpec;
7622        impl crate::RegisterSpec for TxFifoCntSpec {
7623            type Ux = u16;
7624        }
7625        #[doc = "`read()` method returns [`tx_fifo_cnt::R`](R) reader structure"]
7626        impl crate::Readable for TxFifoCntSpec {}
7627        #[doc = "`write(|w| ..)` method takes [`tx_fifo_cnt::W`](W) writer structure"]
7628        impl crate::Writable for TxFifoCntSpec {
7629            type Safety = crate::Unsafe;
7630        }
7631        #[doc = "`reset()` method sets TX_FIFO_CNT to value 0"]
7632        impl crate::Resettable for TxFifoCntSpec {}
7633    }
7634    #[doc = "RX_FIFO_CNT (rw) register accessor: RX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_fifo_cnt`] module"]
7635    #[doc(alias = "RX_FIFO_CNT")]
7636    pub type RxFifoCnt = crate::Reg<rx_fifo_cnt::RxFifoCntSpec>;
7637    #[doc = "RX FIFO data counter"]
7638    pub mod rx_fifo_cnt {
7639        #[doc = "Register `RX_FIFO_CNT` reader"]
7640        pub type R = crate::R<RxFifoCntSpec>;
7641        #[doc = "Register `RX_FIFO_CNT` writer"]
7642        pub type W = crate::W<RxFifoCntSpec>;
7643        impl W {}
7644        #[doc = "RX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7645        pub struct RxFifoCntSpec;
7646        impl crate::RegisterSpec for RxFifoCntSpec {
7647            type Ux = u16;
7648        }
7649        #[doc = "`read()` method returns [`rx_fifo_cnt::R`](R) reader structure"]
7650        impl crate::Readable for RxFifoCntSpec {}
7651        #[doc = "`write(|w| ..)` method takes [`rx_fifo_cnt::W`](W) writer structure"]
7652        impl crate::Writable for RxFifoCntSpec {
7653            type Safety = crate::Unsafe;
7654        }
7655        #[doc = "`reset()` method sets RX_FIFO_CNT to value 0"]
7656        impl crate::Resettable for RxFifoCntSpec {}
7657    }
7658    #[doc = "HALT_TX (rw) register accessor: TX halt register\n\nYou can [`read`](crate::Reg::read) this register and get [`halt_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halt_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@halt_tx`] module"]
7659    #[doc(alias = "HALT_TX")]
7660    pub type HaltTx = crate::Reg<halt_tx::HaltTxSpec>;
7661    #[doc = "TX halt register"]
7662    pub mod halt_tx {
7663        #[doc = "Register `HALT_TX` reader"]
7664        pub type R = crate::R<HaltTxSpec>;
7665        #[doc = "Register `HALT_TX` writer"]
7666        pub type W = crate::W<HaltTxSpec>;
7667        #[doc = "Field `halt_tx` reader - TX halt: 0=disabled; 1=enabled"]
7668        pub type HaltTxR = crate::BitReader;
7669        #[doc = "Field `halt_tx` writer - TX halt: 0=disabled; 1=enabled"]
7670        pub type HaltTxW<'a, REG> = crate::BitWriter<'a, REG>;
7671        impl R {
7672            #[doc = "Bit 0 - TX halt: 0=disabled; 1=enabled"]
7673            #[inline(always)]
7674            pub fn halt_tx(&self) -> HaltTxR {
7675                HaltTxR::new((self.bits & 1) != 0)
7676            }
7677        }
7678        impl W {
7679            #[doc = "Bit 0 - TX halt: 0=disabled; 1=enabled"]
7680            #[inline(always)]
7681            pub fn halt_tx(&mut self) -> HaltTxW<'_, HaltTxSpec> {
7682                HaltTxW::new(self, 0)
7683            }
7684        }
7685        #[doc = "TX halt register\n\nYou can [`read`](crate::Reg::read) this register and get [`halt_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halt_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7686        pub struct HaltTxSpec;
7687        impl crate::RegisterSpec for HaltTxSpec {
7688            type Ux = u16;
7689        }
7690        #[doc = "`read()` method returns [`halt_tx::R`](R) reader structure"]
7691        impl crate::Readable for HaltTxSpec {}
7692        #[doc = "`write(|w| ..)` method takes [`halt_tx::W`](W) writer structure"]
7693        impl crate::Writable for HaltTxSpec {
7694            type Safety = crate::Unsafe;
7695        }
7696        #[doc = "`reset()` method sets HALT_TX to value 0"]
7697        impl crate::Resettable for HaltTxSpec {}
7698    }
7699    #[doc = "DMA_SW_ACK (rw) register accessor: DMA software acknowledge register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_sw_ack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_sw_ack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_sw_ack`] module"]
7700    #[doc(alias = "DMA_SW_ACK")]
7701    pub type DmaSwAck = crate::Reg<dma_sw_ack::DmaSwAckSpec>;
7702    #[doc = "DMA software acknowledge register"]
7703    pub mod dma_sw_ack {
7704        #[doc = "Register `DMA_SW_ACK` reader"]
7705        pub type R = crate::R<DmaSwAckSpec>;
7706        #[doc = "Register `DMA_SW_ACK` writer"]
7707        pub type W = crate::W<DmaSwAckSpec>;
7708        #[doc = "Field `dma_sw_ack` writer - DMA software acknowledge (write-clear)"]
7709        pub type DmaSwAckW<'a, REG> = crate::BitWriter<'a, REG>;
7710        impl W {
7711            #[doc = "Bit 0 - DMA software acknowledge (write-clear)"]
7712            #[inline(always)]
7713            pub fn dma_sw_ack(&mut self) -> DmaSwAckW<'_, DmaSwAckSpec> {
7714                DmaSwAckW::new(self, 0)
7715            }
7716        }
7717        #[doc = "DMA software acknowledge register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_sw_ack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_sw_ack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7718        pub struct DmaSwAckSpec;
7719        impl crate::RegisterSpec for DmaSwAckSpec {
7720            type Ux = u16;
7721        }
7722        #[doc = "`read()` method returns [`dma_sw_ack::R`](R) reader structure"]
7723        impl crate::Readable for DmaSwAckSpec {}
7724        #[doc = "`write(|w| ..)` method takes [`dma_sw_ack::W`](W) writer structure"]
7725        impl crate::Writable for DmaSwAckSpec {
7726            type Safety = crate::Unsafe;
7727        }
7728        #[doc = "`reset()` method sets DMA_SW_ACK to value 0"]
7729        impl crate::Resettable for DmaSwAckSpec {}
7730    }
7731    #[doc = "BAUD_CTL (rw) register accessor: Baud rate control register\n\nYou can [`read`](crate::Reg::read) this register and get [`baud_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud_ctl`] module"]
7732    #[doc(alias = "BAUD_CTL")]
7733    pub type BaudCtl = crate::Reg<baud_ctl::BaudCtlSpec>;
7734    #[doc = "Baud rate control register"]
7735    pub mod baud_ctl {
7736        #[doc = "Register `BAUD_CTL` reader"]
7737        pub type R = crate::R<BaudCtlSpec>;
7738        #[doc = "Register `BAUD_CTL` writer"]
7739        pub type W = crate::W<BaudCtlSpec>;
7740        #[doc = "Baud rate oversampling: 0x7=8x; 0xF=16x\n\nValue on reset: 15"]
7741        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
7742        #[repr(u8)]
7743        pub enum BaudDiv {
7744            #[doc = "7: 8x oversampling"]
7745            Div8 = 7,
7746            #[doc = "15: 16x oversampling"]
7747            Div16 = 15,
7748        }
7749        impl From<BaudDiv> for u8 {
7750            #[inline(always)]
7751            fn from(variant: BaudDiv) -> Self {
7752                variant as _
7753            }
7754        }
7755        impl crate::FieldSpec for BaudDiv {
7756            type Ux = u8;
7757        }
7758        impl crate::IsEnum for BaudDiv {}
7759        #[doc = "Field `baud_div` reader - Baud rate oversampling: 0x7=8x; 0xF=16x"]
7760        pub type BaudDivR = crate::FieldReader<BaudDiv>;
7761        impl BaudDivR {
7762            #[doc = "Get enumerated values variant"]
7763            #[inline(always)]
7764            pub const fn variant(&self) -> Option<BaudDiv> {
7765                match self.bits {
7766                    7 => Some(BaudDiv::Div8),
7767                    15 => Some(BaudDiv::Div16),
7768                    _ => None,
7769                }
7770            }
7771            #[doc = "8x oversampling"]
7772            #[inline(always)]
7773            pub fn is_div8(&self) -> bool {
7774                *self == BaudDiv::Div8
7775            }
7776            #[doc = "16x oversampling"]
7777            #[inline(always)]
7778            pub fn is_div16(&self) -> bool {
7779                *self == BaudDiv::Div16
7780            }
7781        }
7782        #[doc = "Field `baud_div` writer - Baud rate oversampling: 0x7=8x; 0xF=16x"]
7783        pub type BaudDivW<'a, REG> = crate::FieldWriter<'a, REG, 4, BaudDiv>;
7784        impl<'a, REG> BaudDivW<'a, REG>
7785        where
7786            REG: crate::Writable + crate::RegisterSpec,
7787            REG::Ux: From<u8>,
7788        {
7789            #[doc = "8x oversampling"]
7790            #[inline(always)]
7791            pub fn div8(self) -> &'a mut crate::W<REG> {
7792                self.variant(BaudDiv::Div8)
7793            }
7794            #[doc = "16x oversampling"]
7795            #[inline(always)]
7796            pub fn div16(self) -> &'a mut crate::W<REG> {
7797                self.variant(BaudDiv::Div16)
7798            }
7799        }
7800        #[doc = "Field `sample_phase` reader - RX sample phase"]
7801        pub type SamplePhaseR = crate::FieldReader;
7802        #[doc = "Field `sample_phase` writer - RX sample phase"]
7803        pub type SamplePhaseW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
7804        impl R {
7805            #[doc = "Bits 0:3 - Baud rate oversampling: 0x7=8x; 0xF=16x"]
7806            #[inline(always)]
7807            pub fn baud_div(&self) -> BaudDivR {
7808                BaudDivR::new((self.bits & 0x0f) as u8)
7809            }
7810            #[doc = "Bits 4:7 - RX sample phase"]
7811            #[inline(always)]
7812            pub fn sample_phase(&self) -> SamplePhaseR {
7813                SamplePhaseR::new(((self.bits >> 4) & 0x0f) as u8)
7814            }
7815        }
7816        impl W {
7817            #[doc = "Bits 0:3 - Baud rate oversampling: 0x7=8x; 0xF=16x"]
7818            #[inline(always)]
7819            pub fn baud_div(&mut self) -> BaudDivW<'_, BaudCtlSpec> {
7820                BaudDivW::new(self, 0)
7821            }
7822            #[doc = "Bits 4:7 - RX sample phase"]
7823            #[inline(always)]
7824            pub fn sample_phase(&mut self) -> SamplePhaseW<'_, BaudCtlSpec> {
7825                SamplePhaseW::new(self, 4)
7826            }
7827        }
7828        #[doc = "Baud rate control register\n\nYou can [`read`](crate::Reg::read) this register and get [`baud_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7829        pub struct BaudCtlSpec;
7830        impl crate::RegisterSpec for BaudCtlSpec {
7831            type Ux = u16;
7832        }
7833        #[doc = "`read()` method returns [`baud_ctl::R`](R) reader structure"]
7834        impl crate::Readable for BaudCtlSpec {}
7835        #[doc = "`write(|w| ..)` method takes [`baud_ctl::W`](W) writer structure"]
7836        impl crate::Writable for BaudCtlSpec {
7837            type Safety = crate::Unsafe;
7838        }
7839        #[doc = "`reset()` method sets BAUD_CTL to value 0x7f"]
7840        impl crate::Resettable for BaudCtlSpec {
7841            const RESET_VALUE: u16 = 0x7f;
7842        }
7843    }
7844    #[doc = "STP_CTL (rw) register accessor: Stop bit control register\n\nYou can [`read`](crate::Reg::read) this register and get [`stp_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stp_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stp_ctl`] module"]
7845    #[doc(alias = "STP_CTL")]
7846    pub type StpCtl = crate::Reg<stp_ctl::StpCtlSpec>;
7847    #[doc = "Stop bit control register"]
7848    pub mod stp_ctl {
7849        #[doc = "Register `STP_CTL` reader"]
7850        pub type R = crate::R<StpCtlSpec>;
7851        #[doc = "Register `STP_CTL` writer"]
7852        pub type W = crate::W<StpCtlSpec>;
7853        #[doc = "Field `rx_sp` reader - RX stop bits when stp_mode=1"]
7854        pub type RxSpR = crate::BitReader;
7855        #[doc = "Field `rx_sp` writer - RX stop bits when stp_mode=1"]
7856        pub type RxSpW<'a, REG> = crate::BitWriter<'a, REG>;
7857        #[doc = "Field `tx_sp` reader - TX stop bits when stp_mode=1"]
7858        pub type TxSpR = crate::BitReader;
7859        #[doc = "Field `tx_sp` writer - TX stop bits when stp_mode=1"]
7860        pub type TxSpW<'a, REG> = crate::BitWriter<'a, REG>;
7861        #[doc = "Field `stp_mode` reader - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
7862        pub type StpModeR = crate::BitReader;
7863        #[doc = "Field `stp_mode` writer - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
7864        pub type StpModeW<'a, REG> = crate::BitWriter<'a, REG>;
7865        impl R {
7866            #[doc = "Bit 0 - RX stop bits when stp_mode=1"]
7867            #[inline(always)]
7868            pub fn rx_sp(&self) -> RxSpR {
7869                RxSpR::new((self.bits & 1) != 0)
7870            }
7871            #[doc = "Bit 1 - TX stop bits when stp_mode=1"]
7872            #[inline(always)]
7873            pub fn tx_sp(&self) -> TxSpR {
7874                TxSpR::new(((self.bits >> 1) & 1) != 0)
7875            }
7876            #[doc = "Bit 2 - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
7877            #[inline(always)]
7878            pub fn stp_mode(&self) -> StpModeR {
7879                StpModeR::new(((self.bits >> 2) & 1) != 0)
7880            }
7881        }
7882        impl W {
7883            #[doc = "Bit 0 - RX stop bits when stp_mode=1"]
7884            #[inline(always)]
7885            pub fn rx_sp(&mut self) -> RxSpW<'_, StpCtlSpec> {
7886                RxSpW::new(self, 0)
7887            }
7888            #[doc = "Bit 1 - TX stop bits when stp_mode=1"]
7889            #[inline(always)]
7890            pub fn tx_sp(&mut self) -> TxSpW<'_, StpCtlSpec> {
7891                TxSpW::new(self, 1)
7892            }
7893            #[doc = "Bit 2 - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
7894            #[inline(always)]
7895            pub fn stp_mode(&mut self) -> StpModeW<'_, StpCtlSpec> {
7896                StpModeW::new(self, 2)
7897            }
7898        }
7899        #[doc = "Stop bit control register\n\nYou can [`read`](crate::Reg::read) this register and get [`stp_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stp_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7900        pub struct StpCtlSpec;
7901        impl crate::RegisterSpec for StpCtlSpec {
7902            type Ux = u16;
7903        }
7904        #[doc = "`read()` method returns [`stp_ctl::R`](R) reader structure"]
7905        impl crate::Readable for StpCtlSpec {}
7906        #[doc = "`write(|w| ..)` method takes [`stp_ctl::W`](W) writer structure"]
7907        impl crate::Writable for StpCtlSpec {
7908            type Safety = crate::Unsafe;
7909        }
7910        #[doc = "`reset()` method sets STP_CTL to value 0"]
7911        impl crate::Resettable for StpCtlSpec {}
7912    }
7913    #[doc = "UART_PARAMETER (rw) register accessor: UART parameter register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_parameter::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_parameter::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_parameter`] module"]
7914    #[doc(alias = "UART_PARAMETER")]
7915    pub type UartParameter = crate::Reg<uart_parameter::UartParameterSpec>;
7916    #[doc = "UART parameter register"]
7917    pub mod uart_parameter {
7918        #[doc = "Register `UART_PARAMETER` reader"]
7919        pub type R = crate::R<UartParameterSpec>;
7920        #[doc = "Register `UART_PARAMETER` writer"]
7921        pub type W = crate::W<UartParameterSpec>;
7922        #[doc = "Field `fifo_depth` reader - FIFO depth: 0x4=64"]
7923        pub type FifoDepthR = crate::FieldReader;
7924        #[doc = "Field `apb_data_width` reader - APB data width: 0x1=16bit"]
7925        pub type ApbDataWidthR = crate::FieldReader;
7926        #[doc = "Field `afce_mode` reader - AFCE mode: 0=disabled; 1=enabled"]
7927        pub type AfceModeR = crate::BitReader;
7928        #[doc = "Field `dma_mode` reader - DMA mode: 0=DMA_EXTRA disabled; 1=enabled"]
7929        pub type DmaModeR = crate::BitReader;
7930        #[doc = "Field `shadow` reader - Shadow feature enable"]
7931        pub type ShadowR = crate::BitReader;
7932        impl R {
7933            #[doc = "Bits 0:7 - FIFO depth: 0x4=64"]
7934            #[inline(always)]
7935            pub fn fifo_depth(&self) -> FifoDepthR {
7936                FifoDepthR::new((self.bits & 0xff) as u8)
7937            }
7938            #[doc = "Bits 8:9 - APB data width: 0x1=16bit"]
7939            #[inline(always)]
7940            pub fn apb_data_width(&self) -> ApbDataWidthR {
7941                ApbDataWidthR::new(((self.bits >> 8) & 3) as u8)
7942            }
7943            #[doc = "Bit 10 - AFCE mode: 0=disabled; 1=enabled"]
7944            #[inline(always)]
7945            pub fn afce_mode(&self) -> AfceModeR {
7946                AfceModeR::new(((self.bits >> 10) & 1) != 0)
7947            }
7948            #[doc = "Bit 11 - DMA mode: 0=DMA_EXTRA disabled; 1=enabled"]
7949            #[inline(always)]
7950            pub fn dma_mode(&self) -> DmaModeR {
7951                DmaModeR::new(((self.bits >> 11) & 1) != 0)
7952            }
7953            #[doc = "Bit 12 - Shadow feature enable"]
7954            #[inline(always)]
7955            pub fn shadow(&self) -> ShadowR {
7956                ShadowR::new(((self.bits >> 12) & 1) != 0)
7957            }
7958        }
7959        impl W {}
7960        #[doc = "UART parameter register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_parameter::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_parameter::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7961        pub struct UartParameterSpec;
7962        impl crate::RegisterSpec for UartParameterSpec {
7963            type Ux = u16;
7964        }
7965        #[doc = "`read()` method returns [`uart_parameter::R`](R) reader structure"]
7966        impl crate::Readable for UartParameterSpec {}
7967        #[doc = "`write(|w| ..)` method takes [`uart_parameter::W`](W) writer structure"]
7968        impl crate::Writable for UartParameterSpec {
7969            type Safety = crate::Unsafe;
7970        }
7971        #[doc = "`reset()` method sets UART_PARAMETER to value 0x0d04"]
7972        impl crate::Resettable for UartParameterSpec {
7973            const RESET_VALUE: u16 = 0x0d04;
7974        }
7975    }
7976}
7977#[doc = "UART1 with flow control support"]
7978pub type Uart1 = crate::Periph<uart0::RegisterBlock, 0x4401_1000>;
7979impl core::fmt::Debug for Uart1 {
7980    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7981        f.debug_struct("Uart1").finish()
7982    }
7983}
7984#[doc = "UART1 with flow control support"]
7985pub use self::uart0 as uart1;
7986#[doc = "UART2 with flow control support"]
7987pub type Uart2 = crate::Periph<uart0::RegisterBlock, 0x4401_2000>;
7988impl core::fmt::Debug for Uart2 {
7989    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7990        f.debug_struct("Uart2").finish()
7991    }
7992}
7993#[doc = "UART2 with flow control support"]
7994pub use self::uart0 as uart2;
7995#[doc = "I2C0 master controller"]
7996pub type I2c0 = crate::Periph<i2c0::RegisterBlock, 0x4401_8000>;
7997impl core::fmt::Debug for I2c0 {
7998    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7999        f.debug_struct("I2c0").finish()
8000    }
8001}
8002#[doc = "I2C0 master controller"]
8003pub mod i2c0 {
8004    #[repr(C)]
8005    #[doc = "Register block"]
8006    pub struct RegisterBlock {
8007        i2c_ctrl: I2cCtrl,
8008        i2c_com: I2cCom,
8009        i2c_icr: I2cIcr,
8010        i2c_sr: I2cSr,
8011        i2c_scl_h: I2cSclH,
8012        i2c_scl_l: I2cSclL,
8013        i2c_txr: I2cTxr,
8014        i2c_rxr: I2cRxr,
8015        i2c_fifostatus: I2cFifostatus,
8016        i2c_txcount: I2cTxcount,
8017        i2c_rxcount: I2cRxcount,
8018        i2c_rxtide: I2cRxtide,
8019        i2c_txtide: I2cTxtide,
8020        i2c_ftrper: I2cFtrper,
8021    }
8022    impl RegisterBlock {
8023        #[doc = "0x00 - I2C control register"]
8024        #[inline(always)]
8025        pub const fn i2c_ctrl(&self) -> &I2cCtrl {
8026            &self.i2c_ctrl
8027        }
8028        #[doc = "0x04 - I2C command register"]
8029        #[inline(always)]
8030        pub const fn i2c_com(&self) -> &I2cCom {
8031            &self.i2c_com
8032        }
8033        #[doc = "0x08 - I2C interrupt clear register"]
8034        #[inline(always)]
8035        pub const fn i2c_icr(&self) -> &I2cIcr {
8036            &self.i2c_icr
8037        }
8038        #[doc = "0x0c - I2C status register"]
8039        #[inline(always)]
8040        pub const fn i2c_sr(&self) -> &I2cSr {
8041            &self.i2c_sr
8042        }
8043        #[doc = "0x10 - SCL high period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]"]
8044        #[inline(always)]
8045        pub const fn i2c_scl_h(&self) -> &I2cSclH {
8046            &self.i2c_scl_h
8047        }
8048        #[doc = "0x14 - SCL low period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]"]
8049        #[inline(always)]
8050        pub const fn i2c_scl_l(&self) -> &I2cSclL {
8051            &self.i2c_scl_l
8052        }
8053        #[doc = "0x18 - I2C TX data register"]
8054        #[inline(always)]
8055        pub const fn i2c_txr(&self) -> &I2cTxr {
8056            &self.i2c_txr
8057        }
8058        #[doc = "0x1c - I2C RX data register"]
8059        #[inline(always)]
8060        pub const fn i2c_rxr(&self) -> &I2cRxr {
8061            &self.i2c_rxr
8062        }
8063        #[doc = "0x20 - FIFO status register"]
8064        #[inline(always)]
8065        pub const fn i2c_fifostatus(&self) -> &I2cFifostatus {
8066            &self.i2c_fifostatus
8067        }
8068        #[doc = "0x24 - TX FIFO count register"]
8069        #[inline(always)]
8070        pub const fn i2c_txcount(&self) -> &I2cTxcount {
8071            &self.i2c_txcount
8072        }
8073        #[doc = "0x28 - RX FIFO count register"]
8074        #[inline(always)]
8075        pub const fn i2c_rxcount(&self) -> &I2cRxcount {
8076            &self.i2c_rxcount
8077        }
8078        #[doc = "0x2c - RX FIFO threshold register"]
8079        #[inline(always)]
8080        pub const fn i2c_rxtide(&self) -> &I2cRxtide {
8081            &self.i2c_rxtide
8082        }
8083        #[doc = "0x30 - TX FIFO threshold register"]
8084        #[inline(always)]
8085        pub const fn i2c_txtide(&self) -> &I2cTxtide {
8086            &self.i2c_txtide
8087        }
8088        #[doc = "0x34 - Glitch filter configuration register"]
8089        #[inline(always)]
8090        pub const fn i2c_ftrper(&self) -> &I2cFtrper {
8091            &self.i2c_ftrper
8092        }
8093    }
8094    #[doc = "I2C_CTRL (rw) register accessor: I2C control register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_ctrl`] module"]
8095    #[doc(alias = "I2C_CTRL")]
8096    pub type I2cCtrl = crate::Reg<i2c_ctrl::I2cCtrlSpec>;
8097    #[doc = "I2C control register"]
8098    pub mod i2c_ctrl {
8099        #[doc = "Register `I2C_CTRL` reader"]
8100        pub type R = crate::R<I2cCtrlSpec>;
8101        #[doc = "Register `I2C_CTRL` writer"]
8102        pub type W = crate::W<I2cCtrlSpec>;
8103        #[doc = "Field `int_done_mask` reader - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
8104        pub type IntDoneMaskR = crate::BitReader;
8105        #[doc = "Field `int_done_mask` writer - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
8106        pub type IntDoneMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8107        #[doc = "Field `int_arb_loss_mask` reader - Arbitration loss interrupt mask"]
8108        pub type IntArbLossMaskR = crate::BitReader;
8109        #[doc = "Field `int_arb_loss_mask` writer - Arbitration loss interrupt mask"]
8110        pub type IntArbLossMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8111        #[doc = "Field `int_ack_err_mask` reader - ACK error interrupt mask"]
8112        pub type IntAckErrMaskR = crate::BitReader;
8113        #[doc = "Field `int_ack_err_mask` writer - ACK error interrupt mask"]
8114        pub type IntAckErrMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8115        #[doc = "Field `int_rx_mask` reader - RX interrupt mask"]
8116        pub type IntRxMaskR = crate::BitReader;
8117        #[doc = "Field `int_rx_mask` writer - RX interrupt mask"]
8118        pub type IntRxMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8119        #[doc = "Field `int_tx_mask` reader - TX interrupt mask"]
8120        pub type IntTxMaskR = crate::BitReader;
8121        #[doc = "Field `int_tx_mask` writer - TX interrupt mask"]
8122        pub type IntTxMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8123        #[doc = "Field `int_stop_mask` reader - Stop condition interrupt mask"]
8124        pub type IntStopMaskR = crate::BitReader;
8125        #[doc = "Field `int_stop_mask` writer - Stop condition interrupt mask"]
8126        pub type IntStopMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8127        #[doc = "Field `int_start_mask` reader - Start condition interrupt mask"]
8128        pub type IntStartMaskR = crate::BitReader;
8129        #[doc = "Field `int_start_mask` writer - Start condition interrupt mask"]
8130        pub type IntStartMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8131        #[doc = "Field `int_mask` reader - I2C interrupt master mask"]
8132        pub type IntMaskR = crate::BitReader;
8133        #[doc = "Field `int_mask` writer - I2C interrupt master mask"]
8134        pub type IntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8135        #[doc = "Field `i2c_en` reader - I2C enable: 0=disabled; 1=enabled"]
8136        pub type I2cEnR = crate::BitReader;
8137        #[doc = "Field `i2c_en` writer - I2C enable: 0=disabled; 1=enabled"]
8138        pub type I2cEnW<'a, REG> = crate::BitWriter<'a, REG>;
8139        #[doc = "Field `int_rxtide_mask` reader - RX FIFO overflow interrupt mask"]
8140        pub type IntRxtideMaskR = crate::BitReader;
8141        #[doc = "Field `int_rxtide_mask` writer - RX FIFO overflow interrupt mask"]
8142        pub type IntRxtideMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8143        #[doc = "Field `int_txtide_mask` reader - TX FIFO overflow interrupt mask"]
8144        pub type IntTxtideMaskR = crate::BitReader;
8145        #[doc = "Field `int_txtide_mask` writer - TX FIFO overflow interrupt mask"]
8146        pub type IntTxtideMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8147        #[doc = "I2C mode: 0=no FIFO; 1=FIFO mode\n\nValue on reset: 0"]
8148        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
8149        pub enum ModeCtrl {
8150            #[doc = "0: No FIFO transfer mode"]
8151            NoFifo = 0,
8152            #[doc = "1: FIFO transfer mode"]
8153            Fifo = 1,
8154        }
8155        impl From<ModeCtrl> for bool {
8156            #[inline(always)]
8157            fn from(variant: ModeCtrl) -> Self {
8158                variant as u8 != 0
8159            }
8160        }
8161        #[doc = "Field `mode_ctrl` reader - I2C mode: 0=no FIFO; 1=FIFO mode"]
8162        pub type ModeCtrlR = crate::BitReader<ModeCtrl>;
8163        impl ModeCtrlR {
8164            #[doc = "Get enumerated values variant"]
8165            #[inline(always)]
8166            pub const fn variant(&self) -> ModeCtrl {
8167                match self.bits {
8168                    false => ModeCtrl::NoFifo,
8169                    true => ModeCtrl::Fifo,
8170                }
8171            }
8172            #[doc = "No FIFO transfer mode"]
8173            #[inline(always)]
8174            pub fn is_no_fifo(&self) -> bool {
8175                *self == ModeCtrl::NoFifo
8176            }
8177            #[doc = "FIFO transfer mode"]
8178            #[inline(always)]
8179            pub fn is_fifo(&self) -> bool {
8180                *self == ModeCtrl::Fifo
8181            }
8182        }
8183        #[doc = "Field `mode_ctrl` writer - I2C mode: 0=no FIFO; 1=FIFO mode"]
8184        pub type ModeCtrlW<'a, REG> = crate::BitWriter<'a, REG, ModeCtrl>;
8185        impl<'a, REG> ModeCtrlW<'a, REG>
8186        where
8187            REG: crate::Writable + crate::RegisterSpec,
8188        {
8189            #[doc = "No FIFO transfer mode"]
8190            #[inline(always)]
8191            pub fn no_fifo(self) -> &'a mut crate::W<REG> {
8192                self.variant(ModeCtrl::NoFifo)
8193            }
8194            #[doc = "FIFO transfer mode"]
8195            #[inline(always)]
8196            pub fn fifo(self) -> &'a mut crate::W<REG> {
8197                self.variant(ModeCtrl::Fifo)
8198            }
8199        }
8200        #[doc = "Field `int_txfifo_over_mask` reader - TX FIFO complete interrupt mask"]
8201        pub type IntTxfifoOverMaskR = crate::BitReader;
8202        #[doc = "Field `int_txfifo_over_mask` writer - TX FIFO complete interrupt mask"]
8203        pub type IntTxfifoOverMaskW<'a, REG> = crate::BitWriter<'a, REG>;
8204        impl R {
8205            #[doc = "Bit 0 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
8206            #[inline(always)]
8207            pub fn int_done_mask(&self) -> IntDoneMaskR {
8208                IntDoneMaskR::new((self.bits & 1) != 0)
8209            }
8210            #[doc = "Bit 1 - Arbitration loss interrupt mask"]
8211            #[inline(always)]
8212            pub fn int_arb_loss_mask(&self) -> IntArbLossMaskR {
8213                IntArbLossMaskR::new(((self.bits >> 1) & 1) != 0)
8214            }
8215            #[doc = "Bit 2 - ACK error interrupt mask"]
8216            #[inline(always)]
8217            pub fn int_ack_err_mask(&self) -> IntAckErrMaskR {
8218                IntAckErrMaskR::new(((self.bits >> 2) & 1) != 0)
8219            }
8220            #[doc = "Bit 3 - RX interrupt mask"]
8221            #[inline(always)]
8222            pub fn int_rx_mask(&self) -> IntRxMaskR {
8223                IntRxMaskR::new(((self.bits >> 3) & 1) != 0)
8224            }
8225            #[doc = "Bit 4 - TX interrupt mask"]
8226            #[inline(always)]
8227            pub fn int_tx_mask(&self) -> IntTxMaskR {
8228                IntTxMaskR::new(((self.bits >> 4) & 1) != 0)
8229            }
8230            #[doc = "Bit 5 - Stop condition interrupt mask"]
8231            #[inline(always)]
8232            pub fn int_stop_mask(&self) -> IntStopMaskR {
8233                IntStopMaskR::new(((self.bits >> 5) & 1) != 0)
8234            }
8235            #[doc = "Bit 6 - Start condition interrupt mask"]
8236            #[inline(always)]
8237            pub fn int_start_mask(&self) -> IntStartMaskR {
8238                IntStartMaskR::new(((self.bits >> 6) & 1) != 0)
8239            }
8240            #[doc = "Bit 7 - I2C interrupt master mask"]
8241            #[inline(always)]
8242            pub fn int_mask(&self) -> IntMaskR {
8243                IntMaskR::new(((self.bits >> 7) & 1) != 0)
8244            }
8245            #[doc = "Bit 8 - I2C enable: 0=disabled; 1=enabled"]
8246            #[inline(always)]
8247            pub fn i2c_en(&self) -> I2cEnR {
8248                I2cEnR::new(((self.bits >> 8) & 1) != 0)
8249            }
8250            #[doc = "Bit 9 - RX FIFO overflow interrupt mask"]
8251            #[inline(always)]
8252            pub fn int_rxtide_mask(&self) -> IntRxtideMaskR {
8253                IntRxtideMaskR::new(((self.bits >> 9) & 1) != 0)
8254            }
8255            #[doc = "Bit 10 - TX FIFO overflow interrupt mask"]
8256            #[inline(always)]
8257            pub fn int_txtide_mask(&self) -> IntTxtideMaskR {
8258                IntTxtideMaskR::new(((self.bits >> 10) & 1) != 0)
8259            }
8260            #[doc = "Bit 11 - I2C mode: 0=no FIFO; 1=FIFO mode"]
8261            #[inline(always)]
8262            pub fn mode_ctrl(&self) -> ModeCtrlR {
8263                ModeCtrlR::new(((self.bits >> 11) & 1) != 0)
8264            }
8265            #[doc = "Bit 12 - TX FIFO complete interrupt mask"]
8266            #[inline(always)]
8267            pub fn int_txfifo_over_mask(&self) -> IntTxfifoOverMaskR {
8268                IntTxfifoOverMaskR::new(((self.bits >> 12) & 1) != 0)
8269            }
8270        }
8271        impl W {
8272            #[doc = "Bit 0 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
8273            #[inline(always)]
8274            pub fn int_done_mask(&mut self) -> IntDoneMaskW<'_, I2cCtrlSpec> {
8275                IntDoneMaskW::new(self, 0)
8276            }
8277            #[doc = "Bit 1 - Arbitration loss interrupt mask"]
8278            #[inline(always)]
8279            pub fn int_arb_loss_mask(&mut self) -> IntArbLossMaskW<'_, I2cCtrlSpec> {
8280                IntArbLossMaskW::new(self, 1)
8281            }
8282            #[doc = "Bit 2 - ACK error interrupt mask"]
8283            #[inline(always)]
8284            pub fn int_ack_err_mask(&mut self) -> IntAckErrMaskW<'_, I2cCtrlSpec> {
8285                IntAckErrMaskW::new(self, 2)
8286            }
8287            #[doc = "Bit 3 - RX interrupt mask"]
8288            #[inline(always)]
8289            pub fn int_rx_mask(&mut self) -> IntRxMaskW<'_, I2cCtrlSpec> {
8290                IntRxMaskW::new(self, 3)
8291            }
8292            #[doc = "Bit 4 - TX interrupt mask"]
8293            #[inline(always)]
8294            pub fn int_tx_mask(&mut self) -> IntTxMaskW<'_, I2cCtrlSpec> {
8295                IntTxMaskW::new(self, 4)
8296            }
8297            #[doc = "Bit 5 - Stop condition interrupt mask"]
8298            #[inline(always)]
8299            pub fn int_stop_mask(&mut self) -> IntStopMaskW<'_, I2cCtrlSpec> {
8300                IntStopMaskW::new(self, 5)
8301            }
8302            #[doc = "Bit 6 - Start condition interrupt mask"]
8303            #[inline(always)]
8304            pub fn int_start_mask(&mut self) -> IntStartMaskW<'_, I2cCtrlSpec> {
8305                IntStartMaskW::new(self, 6)
8306            }
8307            #[doc = "Bit 7 - I2C interrupt master mask"]
8308            #[inline(always)]
8309            pub fn int_mask(&mut self) -> IntMaskW<'_, I2cCtrlSpec> {
8310                IntMaskW::new(self, 7)
8311            }
8312            #[doc = "Bit 8 - I2C enable: 0=disabled; 1=enabled"]
8313            #[inline(always)]
8314            pub fn i2c_en(&mut self) -> I2cEnW<'_, I2cCtrlSpec> {
8315                I2cEnW::new(self, 8)
8316            }
8317            #[doc = "Bit 9 - RX FIFO overflow interrupt mask"]
8318            #[inline(always)]
8319            pub fn int_rxtide_mask(&mut self) -> IntRxtideMaskW<'_, I2cCtrlSpec> {
8320                IntRxtideMaskW::new(self, 9)
8321            }
8322            #[doc = "Bit 10 - TX FIFO overflow interrupt mask"]
8323            #[inline(always)]
8324            pub fn int_txtide_mask(&mut self) -> IntTxtideMaskW<'_, I2cCtrlSpec> {
8325                IntTxtideMaskW::new(self, 10)
8326            }
8327            #[doc = "Bit 11 - I2C mode: 0=no FIFO; 1=FIFO mode"]
8328            #[inline(always)]
8329            pub fn mode_ctrl(&mut self) -> ModeCtrlW<'_, I2cCtrlSpec> {
8330                ModeCtrlW::new(self, 11)
8331            }
8332            #[doc = "Bit 12 - TX FIFO complete interrupt mask"]
8333            #[inline(always)]
8334            pub fn int_txfifo_over_mask(&mut self) -> IntTxfifoOverMaskW<'_, I2cCtrlSpec> {
8335                IntTxfifoOverMaskW::new(self, 12)
8336            }
8337        }
8338        #[doc = "I2C control register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8339        pub struct I2cCtrlSpec;
8340        impl crate::RegisterSpec for I2cCtrlSpec {
8341            type Ux = u32;
8342        }
8343        #[doc = "`read()` method returns [`i2c_ctrl::R`](R) reader structure"]
8344        impl crate::Readable for I2cCtrlSpec {}
8345        #[doc = "`write(|w| ..)` method takes [`i2c_ctrl::W`](W) writer structure"]
8346        impl crate::Writable for I2cCtrlSpec {
8347            type Safety = crate::Unsafe;
8348        }
8349        #[doc = "`reset()` method sets I2C_CTRL to value 0"]
8350        impl crate::Resettable for I2cCtrlSpec {}
8351    }
8352    #[doc = "I2C_COM (rw) register accessor: I2C command register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_com::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_com::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_com`] module"]
8353    #[doc(alias = "I2C_COM")]
8354    pub type I2cCom = crate::Reg<i2c_com::I2cComSpec>;
8355    #[doc = "I2C command register"]
8356    pub mod i2c_com {
8357        #[doc = "Register `I2C_COM` reader"]
8358        pub type R = crate::R<I2cComSpec>;
8359        #[doc = "Register `I2C_COM` writer"]
8360        pub type W = crate::W<I2cComSpec>;
8361        #[doc = "Field `op_stop` reader - Generate stop condition: 0=end; 1=active"]
8362        pub type OpStopR = crate::BitReader;
8363        #[doc = "Field `op_stop` writer - Generate stop condition: 0=end; 1=active"]
8364        pub type OpStopW<'a, REG> = crate::BitWriter<'a, REG>;
8365        #[doc = "Field `op_we` reader - Generate write operation"]
8366        pub type OpWeR = crate::BitReader;
8367        #[doc = "Field `op_we` writer - Generate write operation"]
8368        pub type OpWeW<'a, REG> = crate::BitWriter<'a, REG>;
8369        #[doc = "Field `op_rd` reader - Generate read operation"]
8370        pub type OpRdR = crate::BitReader;
8371        #[doc = "Field `op_rd` writer - Generate read operation"]
8372        pub type OpRdW<'a, REG> = crate::BitWriter<'a, REG>;
8373        #[doc = "Field `op_start` reader - Generate start condition"]
8374        pub type OpStartR = crate::BitReader;
8375        #[doc = "Field `op_start` writer - Generate start condition"]
8376        pub type OpStartW<'a, REG> = crate::BitWriter<'a, REG>;
8377        #[doc = "Field `op_ack` reader - Master RX ACK: 0=send ACK; 1=no ACK"]
8378        pub type OpAckR = crate::BitReader;
8379        #[doc = "Field `op_ack` writer - Master RX ACK: 0=send ACK; 1=no ACK"]
8380        pub type OpAckW<'a, REG> = crate::BitWriter<'a, REG>;
8381        impl R {
8382            #[doc = "Bit 0 - Generate stop condition: 0=end; 1=active"]
8383            #[inline(always)]
8384            pub fn op_stop(&self) -> OpStopR {
8385                OpStopR::new((self.bits & 1) != 0)
8386            }
8387            #[doc = "Bit 1 - Generate write operation"]
8388            #[inline(always)]
8389            pub fn op_we(&self) -> OpWeR {
8390                OpWeR::new(((self.bits >> 1) & 1) != 0)
8391            }
8392            #[doc = "Bit 2 - Generate read operation"]
8393            #[inline(always)]
8394            pub fn op_rd(&self) -> OpRdR {
8395                OpRdR::new(((self.bits >> 2) & 1) != 0)
8396            }
8397            #[doc = "Bit 3 - Generate start condition"]
8398            #[inline(always)]
8399            pub fn op_start(&self) -> OpStartR {
8400                OpStartR::new(((self.bits >> 3) & 1) != 0)
8401            }
8402            #[doc = "Bit 4 - Master RX ACK: 0=send ACK; 1=no ACK"]
8403            #[inline(always)]
8404            pub fn op_ack(&self) -> OpAckR {
8405                OpAckR::new(((self.bits >> 4) & 1) != 0)
8406            }
8407        }
8408        impl W {
8409            #[doc = "Bit 0 - Generate stop condition: 0=end; 1=active"]
8410            #[inline(always)]
8411            pub fn op_stop(&mut self) -> OpStopW<'_, I2cComSpec> {
8412                OpStopW::new(self, 0)
8413            }
8414            #[doc = "Bit 1 - Generate write operation"]
8415            #[inline(always)]
8416            pub fn op_we(&mut self) -> OpWeW<'_, I2cComSpec> {
8417                OpWeW::new(self, 1)
8418            }
8419            #[doc = "Bit 2 - Generate read operation"]
8420            #[inline(always)]
8421            pub fn op_rd(&mut self) -> OpRdW<'_, I2cComSpec> {
8422                OpRdW::new(self, 2)
8423            }
8424            #[doc = "Bit 3 - Generate start condition"]
8425            #[inline(always)]
8426            pub fn op_start(&mut self) -> OpStartW<'_, I2cComSpec> {
8427                OpStartW::new(self, 3)
8428            }
8429            #[doc = "Bit 4 - Master RX ACK: 0=send ACK; 1=no ACK"]
8430            #[inline(always)]
8431            pub fn op_ack(&mut self) -> OpAckW<'_, I2cComSpec> {
8432                OpAckW::new(self, 4)
8433            }
8434        }
8435        #[doc = "I2C command register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_com::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_com::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8436        pub struct I2cComSpec;
8437        impl crate::RegisterSpec for I2cComSpec {
8438            type Ux = u32;
8439        }
8440        #[doc = "`read()` method returns [`i2c_com::R`](R) reader structure"]
8441        impl crate::Readable for I2cComSpec {}
8442        #[doc = "`write(|w| ..)` method takes [`i2c_com::W`](W) writer structure"]
8443        impl crate::Writable for I2cComSpec {
8444            type Safety = crate::Unsafe;
8445        }
8446        #[doc = "`reset()` method sets I2C_COM to value 0"]
8447        impl crate::Resettable for I2cComSpec {}
8448    }
8449    #[doc = "I2C_ICR (rw) register accessor: I2C interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_icr`] module"]
8450    #[doc(alias = "I2C_ICR")]
8451    pub type I2cIcr = crate::Reg<i2c_icr::I2cIcrSpec>;
8452    #[doc = "I2C interrupt clear register"]
8453    pub mod i2c_icr {
8454        #[doc = "Register `I2C_ICR` reader"]
8455        pub type R = crate::R<I2cIcrSpec>;
8456        #[doc = "Register `I2C_ICR` writer"]
8457        pub type W = crate::W<I2cIcrSpec>;
8458        #[doc = "Field `clr_int_done` writer - Clear transfer complete interrupt"]
8459        pub type ClrIntDoneW<'a, REG> = crate::BitWriter<'a, REG>;
8460        #[doc = "Field `clr_int_arb_loss` writer - Clear arbitration loss interrupt"]
8461        pub type ClrIntArbLossW<'a, REG> = crate::BitWriter<'a, REG>;
8462        #[doc = "Field `clr_int_ack_err` writer - Clear ACK error interrupt"]
8463        pub type ClrIntAckErrW<'a, REG> = crate::BitWriter<'a, REG>;
8464        #[doc = "Field `clr_int_rx` writer - Clear RX interrupt"]
8465        pub type ClrIntRxW<'a, REG> = crate::BitWriter<'a, REG>;
8466        #[doc = "Field `clr_int_tx` writer - Clear TX interrupt"]
8467        pub type ClrIntTxW<'a, REG> = crate::BitWriter<'a, REG>;
8468        #[doc = "Field `clr_int_stop` writer - Clear stop interrupt"]
8469        pub type ClrIntStopW<'a, REG> = crate::BitWriter<'a, REG>;
8470        #[doc = "Field `clr_int_start` writer - Clear start interrupt"]
8471        pub type ClrIntStartW<'a, REG> = crate::BitWriter<'a, REG>;
8472        #[doc = "Field `clr_int_rxtide` writer - Clear RX FIFO overflow interrupt"]
8473        pub type ClrIntRxtideW<'a, REG> = crate::BitWriter<'a, REG>;
8474        #[doc = "Field `clr_int_txtide` writer - Clear TX FIFO overflow interrupt"]
8475        pub type ClrIntTxtideW<'a, REG> = crate::BitWriter<'a, REG>;
8476        #[doc = "Field `clr_int_txfifo_over` writer - Clear TX FIFO complete interrupt"]
8477        pub type ClrIntTxfifoOverW<'a, REG> = crate::BitWriter<'a, REG>;
8478        impl W {
8479            #[doc = "Bit 0 - Clear transfer complete interrupt"]
8480            #[inline(always)]
8481            pub fn clr_int_done(&mut self) -> ClrIntDoneW<'_, I2cIcrSpec> {
8482                ClrIntDoneW::new(self, 0)
8483            }
8484            #[doc = "Bit 1 - Clear arbitration loss interrupt"]
8485            #[inline(always)]
8486            pub fn clr_int_arb_loss(&mut self) -> ClrIntArbLossW<'_, I2cIcrSpec> {
8487                ClrIntArbLossW::new(self, 1)
8488            }
8489            #[doc = "Bit 2 - Clear ACK error interrupt"]
8490            #[inline(always)]
8491            pub fn clr_int_ack_err(&mut self) -> ClrIntAckErrW<'_, I2cIcrSpec> {
8492                ClrIntAckErrW::new(self, 2)
8493            }
8494            #[doc = "Bit 3 - Clear RX interrupt"]
8495            #[inline(always)]
8496            pub fn clr_int_rx(&mut self) -> ClrIntRxW<'_, I2cIcrSpec> {
8497                ClrIntRxW::new(self, 3)
8498            }
8499            #[doc = "Bit 4 - Clear TX interrupt"]
8500            #[inline(always)]
8501            pub fn clr_int_tx(&mut self) -> ClrIntTxW<'_, I2cIcrSpec> {
8502                ClrIntTxW::new(self, 4)
8503            }
8504            #[doc = "Bit 5 - Clear stop interrupt"]
8505            #[inline(always)]
8506            pub fn clr_int_stop(&mut self) -> ClrIntStopW<'_, I2cIcrSpec> {
8507                ClrIntStopW::new(self, 5)
8508            }
8509            #[doc = "Bit 6 - Clear start interrupt"]
8510            #[inline(always)]
8511            pub fn clr_int_start(&mut self) -> ClrIntStartW<'_, I2cIcrSpec> {
8512                ClrIntStartW::new(self, 6)
8513            }
8514            #[doc = "Bit 7 - Clear RX FIFO overflow interrupt"]
8515            #[inline(always)]
8516            pub fn clr_int_rxtide(&mut self) -> ClrIntRxtideW<'_, I2cIcrSpec> {
8517                ClrIntRxtideW::new(self, 7)
8518            }
8519            #[doc = "Bit 8 - Clear TX FIFO overflow interrupt"]
8520            #[inline(always)]
8521            pub fn clr_int_txtide(&mut self) -> ClrIntTxtideW<'_, I2cIcrSpec> {
8522                ClrIntTxtideW::new(self, 8)
8523            }
8524            #[doc = "Bit 9 - Clear TX FIFO complete interrupt"]
8525            #[inline(always)]
8526            pub fn clr_int_txfifo_over(&mut self) -> ClrIntTxfifoOverW<'_, I2cIcrSpec> {
8527                ClrIntTxfifoOverW::new(self, 9)
8528            }
8529        }
8530        #[doc = "I2C interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8531        pub struct I2cIcrSpec;
8532        impl crate::RegisterSpec for I2cIcrSpec {
8533            type Ux = u32;
8534        }
8535        #[doc = "`read()` method returns [`i2c_icr::R`](R) reader structure"]
8536        impl crate::Readable for I2cIcrSpec {}
8537        #[doc = "`write(|w| ..)` method takes [`i2c_icr::W`](W) writer structure"]
8538        impl crate::Writable for I2cIcrSpec {
8539            type Safety = crate::Unsafe;
8540        }
8541        #[doc = "`reset()` method sets I2C_ICR to value 0"]
8542        impl crate::Resettable for I2cIcrSpec {}
8543    }
8544    #[doc = "I2C_SR (rw) register accessor: I2C status register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_sr`] module"]
8545    #[doc(alias = "I2C_SR")]
8546    pub type I2cSr = crate::Reg<i2c_sr::I2cSrSpec>;
8547    #[doc = "I2C status register"]
8548    pub mod i2c_sr {
8549        #[doc = "Register `I2C_SR` reader"]
8550        pub type R = crate::R<I2cSrSpec>;
8551        #[doc = "Register `I2C_SR` writer"]
8552        pub type W = crate::W<I2cSrSpec>;
8553        #[doc = "Field `int_done` reader - Transfer complete interrupt flag"]
8554        pub type IntDoneR = crate::BitReader;
8555        #[doc = "Field `int_arb_loss` reader - Arbitration loss interrupt flag"]
8556        pub type IntArbLossR = crate::BitReader;
8557        #[doc = "Field `int_ack_err` reader - ACK error interrupt flag"]
8558        pub type IntAckErrR = crate::BitReader;
8559        #[doc = "Field `int_rx` reader - RX interrupt flag"]
8560        pub type IntRxR = crate::BitReader;
8561        #[doc = "Field `int_tx` reader - TX interrupt flag"]
8562        pub type IntTxR = crate::BitReader;
8563        #[doc = "Field `int_stop` reader - Stop interrupt flag"]
8564        pub type IntStopR = crate::BitReader;
8565        #[doc = "Field `int_start` reader - Start interrupt flag"]
8566        pub type IntStartR = crate::BitReader;
8567        #[doc = "Field `bus_busy` reader - Bus busy: 0=idle; 1=busy"]
8568        pub type BusBusyR = crate::BitReader;
8569        #[doc = "Field `int_rxtide` reader - RX FIFO overflow flag"]
8570        pub type IntRxtideR = crate::BitReader;
8571        #[doc = "Field `int_txtide` reader - TX FIFO overflow flag"]
8572        pub type IntTxtideR = crate::BitReader;
8573        #[doc = "Field `int_txfifo_over` reader - TX FIFO complete flag"]
8574        pub type IntTxfifoOverR = crate::BitReader;
8575        impl R {
8576            #[doc = "Bit 0 - Transfer complete interrupt flag"]
8577            #[inline(always)]
8578            pub fn int_done(&self) -> IntDoneR {
8579                IntDoneR::new((self.bits & 1) != 0)
8580            }
8581            #[doc = "Bit 1 - Arbitration loss interrupt flag"]
8582            #[inline(always)]
8583            pub fn int_arb_loss(&self) -> IntArbLossR {
8584                IntArbLossR::new(((self.bits >> 1) & 1) != 0)
8585            }
8586            #[doc = "Bit 2 - ACK error interrupt flag"]
8587            #[inline(always)]
8588            pub fn int_ack_err(&self) -> IntAckErrR {
8589                IntAckErrR::new(((self.bits >> 2) & 1) != 0)
8590            }
8591            #[doc = "Bit 3 - RX interrupt flag"]
8592            #[inline(always)]
8593            pub fn int_rx(&self) -> IntRxR {
8594                IntRxR::new(((self.bits >> 3) & 1) != 0)
8595            }
8596            #[doc = "Bit 4 - TX interrupt flag"]
8597            #[inline(always)]
8598            pub fn int_tx(&self) -> IntTxR {
8599                IntTxR::new(((self.bits >> 4) & 1) != 0)
8600            }
8601            #[doc = "Bit 5 - Stop interrupt flag"]
8602            #[inline(always)]
8603            pub fn int_stop(&self) -> IntStopR {
8604                IntStopR::new(((self.bits >> 5) & 1) != 0)
8605            }
8606            #[doc = "Bit 6 - Start interrupt flag"]
8607            #[inline(always)]
8608            pub fn int_start(&self) -> IntStartR {
8609                IntStartR::new(((self.bits >> 6) & 1) != 0)
8610            }
8611            #[doc = "Bit 7 - Bus busy: 0=idle; 1=busy"]
8612            #[inline(always)]
8613            pub fn bus_busy(&self) -> BusBusyR {
8614                BusBusyR::new(((self.bits >> 7) & 1) != 0)
8615            }
8616            #[doc = "Bit 8 - RX FIFO overflow flag"]
8617            #[inline(always)]
8618            pub fn int_rxtide(&self) -> IntRxtideR {
8619                IntRxtideR::new(((self.bits >> 8) & 1) != 0)
8620            }
8621            #[doc = "Bit 9 - TX FIFO overflow flag"]
8622            #[inline(always)]
8623            pub fn int_txtide(&self) -> IntTxtideR {
8624                IntTxtideR::new(((self.bits >> 9) & 1) != 0)
8625            }
8626            #[doc = "Bit 10 - TX FIFO complete flag"]
8627            #[inline(always)]
8628            pub fn int_txfifo_over(&self) -> IntTxfifoOverR {
8629                IntTxfifoOverR::new(((self.bits >> 10) & 1) != 0)
8630            }
8631        }
8632        impl W {}
8633        #[doc = "I2C status register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8634        pub struct I2cSrSpec;
8635        impl crate::RegisterSpec for I2cSrSpec {
8636            type Ux = u32;
8637        }
8638        #[doc = "`read()` method returns [`i2c_sr::R`](R) reader structure"]
8639        impl crate::Readable for I2cSrSpec {}
8640        #[doc = "`write(|w| ..)` method takes [`i2c_sr::W`](W) writer structure"]
8641        impl crate::Writable for I2cSrSpec {
8642            type Safety = crate::Unsafe;
8643        }
8644        #[doc = "`reset()` method sets I2C_SR to value 0"]
8645        impl crate::Resettable for I2cSrSpec {}
8646    }
8647    #[doc = "I2C_SCL_H (rw) register accessor: SCL high period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_h`] module"]
8648    #[doc(alias = "I2C_SCL_H")]
8649    pub type I2cSclH = crate::Reg<i2c_scl_h::I2cSclHSpec>;
8650    #[doc = "SCL high period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]"]
8651    pub mod i2c_scl_h {
8652        #[doc = "Register `I2C_SCL_H` reader"]
8653        pub type R = crate::R<I2cSclHSpec>;
8654        #[doc = "Register `I2C_SCL_H` writer"]
8655        pub type W = crate::W<I2cSclHSpec>;
8656        #[doc = "Field `scl_h` reader - SCL high period (value*2 = actual period)"]
8657        pub type SclHR = crate::FieldReader<u16>;
8658        #[doc = "Field `scl_h` writer - SCL high period (value*2 = actual period)"]
8659        pub type SclHW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
8660        impl R {
8661            #[doc = "Bits 0:15 - SCL high period (value*2 = actual period)"]
8662            #[inline(always)]
8663            pub fn scl_h(&self) -> SclHR {
8664                SclHR::new((self.bits & 0xffff) as u16)
8665            }
8666        }
8667        impl W {
8668            #[doc = "Bits 0:15 - SCL high period (value*2 = actual period)"]
8669            #[inline(always)]
8670            pub fn scl_h(&mut self) -> SclHW<'_, I2cSclHSpec> {
8671                SclHW::new(self, 0)
8672            }
8673        }
8674        #[doc = "SCL high period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8675        pub struct I2cSclHSpec;
8676        impl crate::RegisterSpec for I2cSclHSpec {
8677            type Ux = u32;
8678        }
8679        #[doc = "`read()` method returns [`i2c_scl_h::R`](R) reader structure"]
8680        impl crate::Readable for I2cSclHSpec {}
8681        #[doc = "`write(|w| ..)` method takes [`i2c_scl_h::W`](W) writer structure"]
8682        impl crate::Writable for I2cSclHSpec {
8683            type Safety = crate::Unsafe;
8684        }
8685        #[doc = "`reset()` method sets I2C_SCL_H to value 0"]
8686        impl crate::Resettable for I2cSclHSpec {}
8687    }
8688    #[doc = "I2C_SCL_L (rw) register accessor: SCL low period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_l`] module"]
8689    #[doc(alias = "I2C_SCL_L")]
8690    pub type I2cSclL = crate::Reg<i2c_scl_l::I2cSclLSpec>;
8691    #[doc = "SCL low period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]"]
8692    pub mod i2c_scl_l {
8693        #[doc = "Register `I2C_SCL_L` reader"]
8694        pub type R = crate::R<I2cSclLSpec>;
8695        #[doc = "Register `I2C_SCL_L` writer"]
8696        pub type W = crate::W<I2cSclLSpec>;
8697        #[doc = "Field `scl_l` reader - SCL low period (value*2 = actual period)"]
8698        pub type SclLR = crate::FieldReader<u16>;
8699        #[doc = "Field `scl_l` writer - SCL low period (value*2 = actual period)"]
8700        pub type SclLW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
8701        impl R {
8702            #[doc = "Bits 0:15 - SCL low period (value*2 = actual period)"]
8703            #[inline(always)]
8704            pub fn scl_l(&self) -> SclLR {
8705                SclLR::new((self.bits & 0xffff) as u16)
8706            }
8707        }
8708        impl W {
8709            #[doc = "Bits 0:15 - SCL low period (value*2 = actual period)"]
8710            #[inline(always)]
8711            pub fn scl_l(&mut self) -> SclLW<'_, I2cSclLSpec> {
8712                SclLW::new(self, 0)
8713            }
8714        }
8715        #[doc = "SCL low period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8716        pub struct I2cSclLSpec;
8717        impl crate::RegisterSpec for I2cSclLSpec {
8718            type Ux = u32;
8719        }
8720        #[doc = "`read()` method returns [`i2c_scl_l::R`](R) reader structure"]
8721        impl crate::Readable for I2cSclLSpec {}
8722        #[doc = "`write(|w| ..)` method takes [`i2c_scl_l::W`](W) writer structure"]
8723        impl crate::Writable for I2cSclLSpec {
8724            type Safety = crate::Unsafe;
8725        }
8726        #[doc = "`reset()` method sets I2C_SCL_L to value 0"]
8727        impl crate::Resettable for I2cSclLSpec {}
8728    }
8729    #[doc = "I2C_TXR (rw) register accessor: I2C TX data register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_txr`] module"]
8730    #[doc(alias = "I2C_TXR")]
8731    pub type I2cTxr = crate::Reg<i2c_txr::I2cTxrSpec>;
8732    #[doc = "I2C TX data register"]
8733    pub mod i2c_txr {
8734        #[doc = "Register `I2C_TXR` reader"]
8735        pub type R = crate::R<I2cTxrSpec>;
8736        #[doc = "Register `I2C_TXR` writer"]
8737        pub type W = crate::W<I2cTxrSpec>;
8738        #[doc = "Field `i2c_txr` reader - TX data byte"]
8739        pub type I2cTxrR = crate::FieldReader;
8740        #[doc = "Field `i2c_txr` writer - TX data byte"]
8741        pub type I2cTxrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
8742        impl R {
8743            #[doc = "Bits 0:7 - TX data byte"]
8744            #[inline(always)]
8745            pub fn i2c_txr(&self) -> I2cTxrR {
8746                I2cTxrR::new((self.bits & 0xff) as u8)
8747            }
8748        }
8749        impl W {
8750            #[doc = "Bits 0:7 - TX data byte"]
8751            #[inline(always)]
8752            pub fn i2c_txr(&mut self) -> I2cTxrW<'_, I2cTxrSpec> {
8753                I2cTxrW::new(self, 0)
8754            }
8755        }
8756        #[doc = "I2C TX data register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8757        pub struct I2cTxrSpec;
8758        impl crate::RegisterSpec for I2cTxrSpec {
8759            type Ux = u32;
8760        }
8761        #[doc = "`read()` method returns [`i2c_txr::R`](R) reader structure"]
8762        impl crate::Readable for I2cTxrSpec {}
8763        #[doc = "`write(|w| ..)` method takes [`i2c_txr::W`](W) writer structure"]
8764        impl crate::Writable for I2cTxrSpec {
8765            type Safety = crate::Unsafe;
8766        }
8767        #[doc = "`reset()` method sets I2C_TXR to value 0"]
8768        impl crate::Resettable for I2cTxrSpec {}
8769    }
8770    #[doc = "I2C_RXR (rw) register accessor: I2C RX data register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_rxr`] module"]
8771    #[doc(alias = "I2C_RXR")]
8772    pub type I2cRxr = crate::Reg<i2c_rxr::I2cRxrSpec>;
8773    #[doc = "I2C RX data register"]
8774    pub mod i2c_rxr {
8775        #[doc = "Register `I2C_RXR` reader"]
8776        pub type R = crate::R<I2cRxrSpec>;
8777        #[doc = "Register `I2C_RXR` writer"]
8778        pub type W = crate::W<I2cRxrSpec>;
8779        #[doc = "Field `i2c_rxr` reader - RX data byte"]
8780        pub type I2cRxrR = crate::FieldReader;
8781        impl R {
8782            #[doc = "Bits 0:7 - RX data byte"]
8783            #[inline(always)]
8784            pub fn i2c_rxr(&self) -> I2cRxrR {
8785                I2cRxrR::new((self.bits & 0xff) as u8)
8786            }
8787        }
8788        impl W {}
8789        #[doc = "I2C RX data register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8790        pub struct I2cRxrSpec;
8791        impl crate::RegisterSpec for I2cRxrSpec {
8792            type Ux = u32;
8793        }
8794        #[doc = "`read()` method returns [`i2c_rxr::R`](R) reader structure"]
8795        impl crate::Readable for I2cRxrSpec {}
8796        #[doc = "`write(|w| ..)` method takes [`i2c_rxr::W`](W) writer structure"]
8797        impl crate::Writable for I2cRxrSpec {
8798            type Safety = crate::Unsafe;
8799        }
8800        #[doc = "`reset()` method sets I2C_RXR to value 0"]
8801        impl crate::Resettable for I2cRxrSpec {}
8802    }
8803    #[doc = "I2C_FIFOSTATUS (rw) register accessor: FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_fifostatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_fifostatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_fifostatus`] module"]
8804    #[doc(alias = "I2C_FIFOSTATUS")]
8805    pub type I2cFifostatus = crate::Reg<i2c_fifostatus::I2cFifostatusSpec>;
8806    #[doc = "FIFO status register"]
8807    pub mod i2c_fifostatus {
8808        #[doc = "Register `I2C_FIFOSTATUS` reader"]
8809        pub type R = crate::R<I2cFifostatusSpec>;
8810        #[doc = "Register `I2C_FIFOSTATUS` writer"]
8811        pub type W = crate::W<I2cFifostatusSpec>;
8812        #[doc = "Field `txff` reader - TX FIFO full: 0=not full; 1=full"]
8813        pub type TxffR = crate::BitReader;
8814        #[doc = "Field `txfe` reader - TX FIFO empty: 0=not empty; 1=empty"]
8815        pub type TxfeR = crate::BitReader;
8816        #[doc = "Field `rxff` reader - RX FIFO full"]
8817        pub type RxffR = crate::BitReader;
8818        #[doc = "Field `rxfe` reader - RX FIFO empty"]
8819        pub type RxfeR = crate::BitReader;
8820        impl R {
8821            #[doc = "Bit 0 - TX FIFO full: 0=not full; 1=full"]
8822            #[inline(always)]
8823            pub fn txff(&self) -> TxffR {
8824                TxffR::new((self.bits & 1) != 0)
8825            }
8826            #[doc = "Bit 1 - TX FIFO empty: 0=not empty; 1=empty"]
8827            #[inline(always)]
8828            pub fn txfe(&self) -> TxfeR {
8829                TxfeR::new(((self.bits >> 1) & 1) != 0)
8830            }
8831            #[doc = "Bit 2 - RX FIFO full"]
8832            #[inline(always)]
8833            pub fn rxff(&self) -> RxffR {
8834                RxffR::new(((self.bits >> 2) & 1) != 0)
8835            }
8836            #[doc = "Bit 3 - RX FIFO empty"]
8837            #[inline(always)]
8838            pub fn rxfe(&self) -> RxfeR {
8839                RxfeR::new(((self.bits >> 3) & 1) != 0)
8840            }
8841        }
8842        impl W {}
8843        #[doc = "FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_fifostatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_fifostatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8844        pub struct I2cFifostatusSpec;
8845        impl crate::RegisterSpec for I2cFifostatusSpec {
8846            type Ux = u32;
8847        }
8848        #[doc = "`read()` method returns [`i2c_fifostatus::R`](R) reader structure"]
8849        impl crate::Readable for I2cFifostatusSpec {}
8850        #[doc = "`write(|w| ..)` method takes [`i2c_fifostatus::W`](W) writer structure"]
8851        impl crate::Writable for I2cFifostatusSpec {
8852            type Safety = crate::Unsafe;
8853        }
8854        #[doc = "`reset()` method sets I2C_FIFOSTATUS to value 0"]
8855        impl crate::Resettable for I2cFifostatusSpec {}
8856    }
8857    #[doc = "I2C_TXCOUNT (rw) register accessor: TX FIFO count register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txcount::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txcount::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_txcount`] module"]
8858    #[doc(alias = "I2C_TXCOUNT")]
8859    pub type I2cTxcount = crate::Reg<i2c_txcount::I2cTxcountSpec>;
8860    #[doc = "TX FIFO count register"]
8861    pub mod i2c_txcount {
8862        #[doc = "Register `I2C_TXCOUNT` reader"]
8863        pub type R = crate::R<I2cTxcountSpec>;
8864        #[doc = "Register `I2C_TXCOUNT` writer"]
8865        pub type W = crate::W<I2cTxcountSpec>;
8866        #[doc = "Field `txcount` reader - TX FIFO character count (write any value to clear TX FIFO)"]
8867        pub type TxcountR = crate::FieldReader;
8868        #[doc = "Field `txcount` writer - TX FIFO character count (write any value to clear TX FIFO)"]
8869        pub type TxcountW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
8870        impl R {
8871            #[doc = "Bits 0:5 - TX FIFO character count (write any value to clear TX FIFO)"]
8872            #[inline(always)]
8873            pub fn txcount(&self) -> TxcountR {
8874                TxcountR::new((self.bits & 0x3f) as u8)
8875            }
8876        }
8877        impl W {
8878            #[doc = "Bits 0:5 - TX FIFO character count (write any value to clear TX FIFO)"]
8879            #[inline(always)]
8880            pub fn txcount(&mut self) -> TxcountW<'_, I2cTxcountSpec> {
8881                TxcountW::new(self, 0)
8882            }
8883        }
8884        #[doc = "TX FIFO count register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txcount::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txcount::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8885        pub struct I2cTxcountSpec;
8886        impl crate::RegisterSpec for I2cTxcountSpec {
8887            type Ux = u32;
8888        }
8889        #[doc = "`read()` method returns [`i2c_txcount::R`](R) reader structure"]
8890        impl crate::Readable for I2cTxcountSpec {}
8891        #[doc = "`write(|w| ..)` method takes [`i2c_txcount::W`](W) writer structure"]
8892        impl crate::Writable for I2cTxcountSpec {
8893            type Safety = crate::Unsafe;
8894        }
8895        #[doc = "`reset()` method sets I2C_TXCOUNT to value 0"]
8896        impl crate::Resettable for I2cTxcountSpec {}
8897    }
8898    #[doc = "I2C_RXCOUNT (rw) register accessor: RX FIFO count register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxcount::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxcount::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_rxcount`] module"]
8899    #[doc(alias = "I2C_RXCOUNT")]
8900    pub type I2cRxcount = crate::Reg<i2c_rxcount::I2cRxcountSpec>;
8901    #[doc = "RX FIFO count register"]
8902    pub mod i2c_rxcount {
8903        #[doc = "Register `I2C_RXCOUNT` reader"]
8904        pub type R = crate::R<I2cRxcountSpec>;
8905        #[doc = "Register `I2C_RXCOUNT` writer"]
8906        pub type W = crate::W<I2cRxcountSpec>;
8907        #[doc = "Field `rxcount` reader - RX FIFO character count (write any value to clear RX FIFO)"]
8908        pub type RxcountR = crate::FieldReader;
8909        #[doc = "Field `rxcount` writer - RX FIFO character count (write any value to clear RX FIFO)"]
8910        pub type RxcountW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
8911        impl R {
8912            #[doc = "Bits 0:5 - RX FIFO character count (write any value to clear RX FIFO)"]
8913            #[inline(always)]
8914            pub fn rxcount(&self) -> RxcountR {
8915                RxcountR::new((self.bits & 0x3f) as u8)
8916            }
8917        }
8918        impl W {
8919            #[doc = "Bits 0:5 - RX FIFO character count (write any value to clear RX FIFO)"]
8920            #[inline(always)]
8921            pub fn rxcount(&mut self) -> RxcountW<'_, I2cRxcountSpec> {
8922                RxcountW::new(self, 0)
8923            }
8924        }
8925        #[doc = "RX FIFO count register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxcount::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxcount::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8926        pub struct I2cRxcountSpec;
8927        impl crate::RegisterSpec for I2cRxcountSpec {
8928            type Ux = u32;
8929        }
8930        #[doc = "`read()` method returns [`i2c_rxcount::R`](R) reader structure"]
8931        impl crate::Readable for I2cRxcountSpec {}
8932        #[doc = "`write(|w| ..)` method takes [`i2c_rxcount::W`](W) writer structure"]
8933        impl crate::Writable for I2cRxcountSpec {
8934            type Safety = crate::Unsafe;
8935        }
8936        #[doc = "`reset()` method sets I2C_RXCOUNT to value 0"]
8937        impl crate::Resettable for I2cRxcountSpec {}
8938    }
8939    #[doc = "I2C_RXTIDE (rw) register accessor: RX FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxtide::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxtide::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_rxtide`] module"]
8940    #[doc(alias = "I2C_RXTIDE")]
8941    pub type I2cRxtide = crate::Reg<i2c_rxtide::I2cRxtideSpec>;
8942    #[doc = "RX FIFO threshold register"]
8943    pub mod i2c_rxtide {
8944        #[doc = "Register `I2C_RXTIDE` reader"]
8945        pub type R = crate::R<I2cRxtideSpec>;
8946        #[doc = "Register `I2C_RXTIDE` writer"]
8947        pub type W = crate::W<I2cRxtideSpec>;
8948        #[doc = "Field `rxtide` reader - RX FIFO overflow interrupt trigger value"]
8949        pub type RxtideR = crate::FieldReader;
8950        #[doc = "Field `rxtide` writer - RX FIFO overflow interrupt trigger value"]
8951        pub type RxtideW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
8952        impl R {
8953            #[doc = "Bits 0:5 - RX FIFO overflow interrupt trigger value"]
8954            #[inline(always)]
8955            pub fn rxtide(&self) -> RxtideR {
8956                RxtideR::new((self.bits & 0x3f) as u8)
8957            }
8958        }
8959        impl W {
8960            #[doc = "Bits 0:5 - RX FIFO overflow interrupt trigger value"]
8961            #[inline(always)]
8962            pub fn rxtide(&mut self) -> RxtideW<'_, I2cRxtideSpec> {
8963                RxtideW::new(self, 0)
8964            }
8965        }
8966        #[doc = "RX FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxtide::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxtide::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8967        pub struct I2cRxtideSpec;
8968        impl crate::RegisterSpec for I2cRxtideSpec {
8969            type Ux = u32;
8970        }
8971        #[doc = "`read()` method returns [`i2c_rxtide::R`](R) reader structure"]
8972        impl crate::Readable for I2cRxtideSpec {}
8973        #[doc = "`write(|w| ..)` method takes [`i2c_rxtide::W`](W) writer structure"]
8974        impl crate::Writable for I2cRxtideSpec {
8975            type Safety = crate::Unsafe;
8976        }
8977        #[doc = "`reset()` method sets I2C_RXTIDE to value 0x01"]
8978        impl crate::Resettable for I2cRxtideSpec {
8979            const RESET_VALUE: u32 = 0x01;
8980        }
8981    }
8982    #[doc = "I2C_TXTIDE (rw) register accessor: TX FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txtide::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txtide::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_txtide`] module"]
8983    #[doc(alias = "I2C_TXTIDE")]
8984    pub type I2cTxtide = crate::Reg<i2c_txtide::I2cTxtideSpec>;
8985    #[doc = "TX FIFO threshold register"]
8986    pub mod i2c_txtide {
8987        #[doc = "Register `I2C_TXTIDE` reader"]
8988        pub type R = crate::R<I2cTxtideSpec>;
8989        #[doc = "Register `I2C_TXTIDE` writer"]
8990        pub type W = crate::W<I2cTxtideSpec>;
8991        #[doc = "Field `txtide` reader - TX FIFO overflow interrupt trigger value"]
8992        pub type TxtideR = crate::FieldReader;
8993        #[doc = "Field `txtide` writer - TX FIFO overflow interrupt trigger value"]
8994        pub type TxtideW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
8995        impl R {
8996            #[doc = "Bits 0:5 - TX FIFO overflow interrupt trigger value"]
8997            #[inline(always)]
8998            pub fn txtide(&self) -> TxtideR {
8999                TxtideR::new((self.bits & 0x3f) as u8)
9000            }
9001        }
9002        impl W {
9003            #[doc = "Bits 0:5 - TX FIFO overflow interrupt trigger value"]
9004            #[inline(always)]
9005            pub fn txtide(&mut self) -> TxtideW<'_, I2cTxtideSpec> {
9006                TxtideW::new(self, 0)
9007            }
9008        }
9009        #[doc = "TX FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txtide::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txtide::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9010        pub struct I2cTxtideSpec;
9011        impl crate::RegisterSpec for I2cTxtideSpec {
9012            type Ux = u32;
9013        }
9014        #[doc = "`read()` method returns [`i2c_txtide::R`](R) reader structure"]
9015        impl crate::Readable for I2cTxtideSpec {}
9016        #[doc = "`write(|w| ..)` method takes [`i2c_txtide::W`](W) writer structure"]
9017        impl crate::Writable for I2cTxtideSpec {
9018            type Safety = crate::Unsafe;
9019        }
9020        #[doc = "`reset()` method sets I2C_TXTIDE to value 0x01"]
9021        impl crate::Resettable for I2cTxtideSpec {
9022            const RESET_VALUE: u32 = 0x01;
9023        }
9024    }
9025    #[doc = "I2C_FTRPER (rw) register accessor: Glitch filter configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ftrper::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ftrper::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_ftrper`] module"]
9026    #[doc(alias = "I2C_FTRPER")]
9027    pub type I2cFtrper = crate::Reg<i2c_ftrper::I2cFtrperSpec>;
9028    #[doc = "Glitch filter configuration register"]
9029    pub mod i2c_ftrper {
9030        #[doc = "Register `I2C_FTRPER` reader"]
9031        pub type R = crate::R<I2cFtrperSpec>;
9032        #[doc = "Register `I2C_FTRPER` writer"]
9033        pub type W = crate::W<I2cFtrperSpec>;
9034        #[doc = "Field `ftrper` reader - Glitch filter period in ic_clk cycles"]
9035        pub type FtrperR = crate::FieldReader;
9036        #[doc = "Field `ftrper` writer - Glitch filter period in ic_clk cycles"]
9037        pub type FtrperW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9038        impl R {
9039            #[doc = "Bits 0:3 - Glitch filter period in ic_clk cycles"]
9040            #[inline(always)]
9041            pub fn ftrper(&self) -> FtrperR {
9042                FtrperR::new((self.bits & 0x0f) as u8)
9043            }
9044        }
9045        impl W {
9046            #[doc = "Bits 0:3 - Glitch filter period in ic_clk cycles"]
9047            #[inline(always)]
9048            pub fn ftrper(&mut self) -> FtrperW<'_, I2cFtrperSpec> {
9049                FtrperW::new(self, 0)
9050            }
9051        }
9052        #[doc = "Glitch filter configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ftrper::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ftrper::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9053        pub struct I2cFtrperSpec;
9054        impl crate::RegisterSpec for I2cFtrperSpec {
9055            type Ux = u32;
9056        }
9057        #[doc = "`read()` method returns [`i2c_ftrper::R`](R) reader structure"]
9058        impl crate::Readable for I2cFtrperSpec {}
9059        #[doc = "`write(|w| ..)` method takes [`i2c_ftrper::W`](W) writer structure"]
9060        impl crate::Writable for I2cFtrperSpec {
9061            type Safety = crate::Unsafe;
9062        }
9063        #[doc = "`reset()` method sets I2C_FTRPER to value 0x0f"]
9064        impl crate::Resettable for I2cFtrperSpec {
9065            const RESET_VALUE: u32 = 0x0f;
9066        }
9067    }
9068}
9069#[doc = "I2C1 master controller"]
9070pub type I2c1 = crate::Periph<i2c0::RegisterBlock, 0x4401_8100>;
9071impl core::fmt::Debug for I2c1 {
9072    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9073        f.debug_struct("I2c1").finish()
9074    }
9075}
9076#[doc = "I2C1 master controller"]
9077pub use self::i2c0 as i2c1;
9078#[doc = "PWM controller with 8 channels"]
9079pub type Pwm = crate::Periph<pwm::RegisterBlock, 0x4402_4000>;
9080impl core::fmt::Debug for Pwm {
9081    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9082        f.debug_struct("Pwm").finish()
9083    }
9084}
9085#[doc = "PWM controller with 8 channels"]
9086pub mod pwm {
9087    #[repr(C)]
9088    #[doc = "Register block"]
9089    pub struct RegisterBlock {
9090        pwm_sel0: PwmSel0,
9091        pwm_startclrcnt_en0: PwmStartclrcntEn0,
9092        pwm_start0: PwmStart0,
9093        _reserved3: [u8; 0x04],
9094        pwm_sel1: PwmSel1,
9095        pwm_startclrcnt_en1: PwmStartclrcntEn1,
9096        pwm_start1: PwmStart1,
9097        _reserved6: [u8; 0x04],
9098        pwm_sel2: PwmSel2,
9099        pwm_startclrcnt_en2: PwmStartclrcntEn2,
9100        pwm_start2: PwmStart2,
9101        _reserved9: [u8; 0x04],
9102        pwm_sel3: PwmSel3,
9103        pwm_startclrcnt_en3: PwmStartclrcntEn3,
9104        pwm_start3: PwmStart3,
9105        _reserved12: [u8; 0xc4],
9106        pwm_en0: PwmEn0,
9107        pwm_portity0: PwmPortity0,
9108        pwm_oen_cfg0: PwmOenCfg0,
9109        pwm_offset_l0: PwmOffsetL0,
9110        pwm_offset_h0: PwmOffsetH0,
9111        pwm_freq_l0: PwmFreqL0,
9112        pwm_freq_h0: PwmFreqH0,
9113        pwm_duty_l0: PwmDutyL0,
9114        pwm_duty_h0: PwmDutyH0,
9115        pwm_periodload_flag0: PwmPeriodloadFlag0,
9116        pwm_period_val0: PwmPeriodVal0,
9117        pwm_periodcnt0: PwmPeriodcnt0,
9118        _reserved24: [u8; 0x10],
9119        pwm_en1: PwmEn1,
9120        pwm_portity1: PwmPortity1,
9121        pwm_oen_cfg1: PwmOenCfg1,
9122        pwm_offset_l1: PwmOffsetL1,
9123        pwm_offset_h1: PwmOffsetH1,
9124        pwm_freq_l1: PwmFreqL1,
9125        pwm_freq_h1: PwmFreqH1,
9126        pwm_duty_l1: PwmDutyL1,
9127        pwm_duty_h1: PwmDutyH1,
9128        pwm_periodload_flag1: PwmPeriodloadFlag1,
9129        pwm_period_val1: PwmPeriodVal1,
9130        pwm_periodcnt1: PwmPeriodcnt1,
9131        _reserved36: [u8; 0x10],
9132        pwm_en2: PwmEn2,
9133        pwm_portity2: PwmPortity2,
9134        pwm_oen_cfg2: PwmOenCfg2,
9135        pwm_offset_l2: PwmOffsetL2,
9136        pwm_offset_h2: PwmOffsetH2,
9137        pwm_freq_l2: PwmFreqL2,
9138        pwm_freq_h2: PwmFreqH2,
9139        pwm_duty_l2: PwmDutyL2,
9140        pwm_duty_h2: PwmDutyH2,
9141        pwm_periodload_flag2: PwmPeriodloadFlag2,
9142        pwm_period_val2: PwmPeriodVal2,
9143        pwm_periodcnt2: PwmPeriodcnt2,
9144        _reserved48: [u8; 0x10],
9145        pwm_en3: PwmEn3,
9146        pwm_portity3: PwmPortity3,
9147        pwm_oen_cfg3: PwmOenCfg3,
9148        pwm_offset_l3: PwmOffsetL3,
9149        pwm_offset_h3: PwmOffsetH3,
9150        pwm_freq_l3: PwmFreqL3,
9151        pwm_freq_h3: PwmFreqH3,
9152        pwm_duty_l3: PwmDutyL3,
9153        pwm_duty_h3: PwmDutyH3,
9154        pwm_periodload_flag3: PwmPeriodloadFlag3,
9155        pwm_period_val3: PwmPeriodVal3,
9156        pwm_periodcnt3: PwmPeriodcnt3,
9157        _reserved60: [u8; 0x10],
9158        pwm_en4: PwmEn4,
9159        pwm_portity4: PwmPortity4,
9160        pwm_oen_cfg4: PwmOenCfg4,
9161        pwm_offset_l4: PwmOffsetL4,
9162        pwm_offset_h4: PwmOffsetH4,
9163        pwm_freq_l4: PwmFreqL4,
9164        pwm_freq_h4: PwmFreqH4,
9165        pwm_duty_l4: PwmDutyL4,
9166        pwm_duty_h4: PwmDutyH4,
9167        pwm_periodload_flag4: PwmPeriodloadFlag4,
9168        pwm_period_val4: PwmPeriodVal4,
9169        pwm_periodcnt4: PwmPeriodcnt4,
9170        _reserved72: [u8; 0x10],
9171        pwm_en5: PwmEn5,
9172        pwm_portity5: PwmPortity5,
9173        pwm_oen_cfg5: PwmOenCfg5,
9174        pwm_offset_l5: PwmOffsetL5,
9175        pwm_offset_h5: PwmOffsetH5,
9176        pwm_freq_l5: PwmFreqL5,
9177        pwm_freq_h5: PwmFreqH5,
9178        pwm_duty_l5: PwmDutyL5,
9179        pwm_duty_h5: PwmDutyH5,
9180        pwm_periodload_flag5: PwmPeriodloadFlag5,
9181        pwm_period_val5: PwmPeriodVal5,
9182        pwm_periodcnt5: PwmPeriodcnt5,
9183        _reserved84: [u8; 0x10],
9184        pwm_en6: PwmEn6,
9185        pwm_portity6: PwmPortity6,
9186        pwm_oen_cfg6: PwmOenCfg6,
9187        pwm_offset_l6: PwmOffsetL6,
9188        pwm_offset_h6: PwmOffsetH6,
9189        pwm_freq_l6: PwmFreqL6,
9190        pwm_freq_h6: PwmFreqH6,
9191        pwm_duty_l6: PwmDutyL6,
9192        pwm_duty_h6: PwmDutyH6,
9193        pwm_periodload_flag6: PwmPeriodloadFlag6,
9194        pwm_period_val6: PwmPeriodVal6,
9195        pwm_periodcnt6: PwmPeriodcnt6,
9196        _reserved96: [u8; 0x10],
9197        pwm_en7: PwmEn7,
9198        pwm_portity7: PwmPortity7,
9199        pwm_oen_cfg7: PwmOenCfg7,
9200        pwm_offset_l7: PwmOffsetL7,
9201        pwm_offset_h7: PwmOffsetH7,
9202        pwm_freq_l7: PwmFreqL7,
9203        pwm_freq_h7: PwmFreqH7,
9204        pwm_duty_l7: PwmDutyL7,
9205        pwm_duty_h7: PwmDutyH7,
9206        pwm_periodload_flag7: PwmPeriodloadFlag7,
9207        pwm_period_val7: PwmPeriodVal7,
9208        pwm_periodcnt7: PwmPeriodcnt7,
9209        _reserved108: [u8; 0x0210],
9210        pwm_abnor_state0: PwmAbnorState0,
9211        pwm_abnor_state1: PwmAbnorState1,
9212        pwm_abnor_state_clr0: PwmAbnorStateClr0,
9213        pwm_abnor_state_clr1: PwmAbnorStateClr1,
9214        pwm_int_mask: PwmIntMask,
9215        pwm_dma_en: PwmDmaEn,
9216        pwm_cfg_int_clr0: PwmCfgIntClr0,
9217    }
9218    impl RegisterBlock {
9219        #[doc = "0x00 - PWM group 0 select"]
9220        #[inline(always)]
9221        pub const fn pwm_sel0(&self) -> &PwmSel0 {
9222            &self.pwm_sel0
9223        }
9224        #[doc = "0x04 - PWM group 0 start clear counter enable"]
9225        #[inline(always)]
9226        pub const fn pwm_startclrcnt_en0(&self) -> &PwmStartclrcntEn0 {
9227            &self.pwm_startclrcnt_en0
9228        }
9229        #[doc = "0x08 - PWM group 0 start"]
9230        #[inline(always)]
9231        pub const fn pwm_start0(&self) -> &PwmStart0 {
9232            &self.pwm_start0
9233        }
9234        #[doc = "0x10 - PWM group 1 select"]
9235        #[inline(always)]
9236        pub const fn pwm_sel1(&self) -> &PwmSel1 {
9237            &self.pwm_sel1
9238        }
9239        #[doc = "0x14 - PWM group 1 start clear counter enable"]
9240        #[inline(always)]
9241        pub const fn pwm_startclrcnt_en1(&self) -> &PwmStartclrcntEn1 {
9242            &self.pwm_startclrcnt_en1
9243        }
9244        #[doc = "0x18 - PWM group 1 start"]
9245        #[inline(always)]
9246        pub const fn pwm_start1(&self) -> &PwmStart1 {
9247            &self.pwm_start1
9248        }
9249        #[doc = "0x20 - PWM group 2 select"]
9250        #[inline(always)]
9251        pub const fn pwm_sel2(&self) -> &PwmSel2 {
9252            &self.pwm_sel2
9253        }
9254        #[doc = "0x24 - PWM group 2 start clear counter enable"]
9255        #[inline(always)]
9256        pub const fn pwm_startclrcnt_en2(&self) -> &PwmStartclrcntEn2 {
9257            &self.pwm_startclrcnt_en2
9258        }
9259        #[doc = "0x28 - PWM group 2 start"]
9260        #[inline(always)]
9261        pub const fn pwm_start2(&self) -> &PwmStart2 {
9262            &self.pwm_start2
9263        }
9264        #[doc = "0x30 - PWM group 3 select"]
9265        #[inline(always)]
9266        pub const fn pwm_sel3(&self) -> &PwmSel3 {
9267            &self.pwm_sel3
9268        }
9269        #[doc = "0x34 - PWM group 3 start clear counter enable"]
9270        #[inline(always)]
9271        pub const fn pwm_startclrcnt_en3(&self) -> &PwmStartclrcntEn3 {
9272            &self.pwm_startclrcnt_en3
9273        }
9274        #[doc = "0x38 - PWM group 3 start"]
9275        #[inline(always)]
9276        pub const fn pwm_start3(&self) -> &PwmStart3 {
9277            &self.pwm_start3
9278        }
9279        #[doc = "0x100 - PWM0 enable"]
9280        #[inline(always)]
9281        pub const fn pwm_en0(&self) -> &PwmEn0 {
9282            &self.pwm_en0
9283        }
9284        #[doc = "0x104 - PWM0 polarity"]
9285        #[inline(always)]
9286        pub const fn pwm_portity0(&self) -> &PwmPortity0 {
9287            &self.pwm_portity0
9288        }
9289        #[doc = "0x108 - PWM0 high-impedance config"]
9290        #[inline(always)]
9291        pub const fn pwm_oen_cfg0(&self) -> &PwmOenCfg0 {
9292            &self.pwm_oen_cfg0
9293        }
9294        #[doc = "0x10c - PWM0 phase offset low 16 bits"]
9295        #[inline(always)]
9296        pub const fn pwm_offset_l0(&self) -> &PwmOffsetL0 {
9297            &self.pwm_offset_l0
9298        }
9299        #[doc = "0x110 - PWM0 phase offset high 16 bits"]
9300        #[inline(always)]
9301        pub const fn pwm_offset_h0(&self) -> &PwmOffsetH0 {
9302            &self.pwm_offset_h0
9303        }
9304        #[doc = "0x114 - PWM0 frequency low 16 bits"]
9305        #[inline(always)]
9306        pub const fn pwm_freq_l0(&self) -> &PwmFreqL0 {
9307            &self.pwm_freq_l0
9308        }
9309        #[doc = "0x118 - PWM0 frequency high 16 bits"]
9310        #[inline(always)]
9311        pub const fn pwm_freq_h0(&self) -> &PwmFreqH0 {
9312            &self.pwm_freq_h0
9313        }
9314        #[doc = "0x11c - PWM0 duty cycle low 16 bits"]
9315        #[inline(always)]
9316        pub const fn pwm_duty_l0(&self) -> &PwmDutyL0 {
9317            &self.pwm_duty_l0
9318        }
9319        #[doc = "0x120 - PWM0 duty cycle high 16 bits"]
9320        #[inline(always)]
9321        pub const fn pwm_duty_h0(&self) -> &PwmDutyH0 {
9322            &self.pwm_duty_h0
9323        }
9324        #[doc = "0x124 - PWM0 period load flag"]
9325        #[inline(always)]
9326        pub const fn pwm_periodload_flag0(&self) -> &PwmPeriodloadFlag0 {
9327            &self.pwm_periodload_flag0
9328        }
9329        #[doc = "0x128 - PWM0 pulse count value"]
9330        #[inline(always)]
9331        pub const fn pwm_period_val0(&self) -> &PwmPeriodVal0 {
9332            &self.pwm_period_val0
9333        }
9334        #[doc = "0x12c - PWM0 pulse count current value"]
9335        #[inline(always)]
9336        pub const fn pwm_periodcnt0(&self) -> &PwmPeriodcnt0 {
9337            &self.pwm_periodcnt0
9338        }
9339        #[doc = "0x140 - PWM1 enable"]
9340        #[inline(always)]
9341        pub const fn pwm_en1(&self) -> &PwmEn1 {
9342            &self.pwm_en1
9343        }
9344        #[doc = "0x144 - PWM1 polarity"]
9345        #[inline(always)]
9346        pub const fn pwm_portity1(&self) -> &PwmPortity1 {
9347            &self.pwm_portity1
9348        }
9349        #[doc = "0x148 - PWM1 high-impedance config"]
9350        #[inline(always)]
9351        pub const fn pwm_oen_cfg1(&self) -> &PwmOenCfg1 {
9352            &self.pwm_oen_cfg1
9353        }
9354        #[doc = "0x14c - PWM1 phase offset low"]
9355        #[inline(always)]
9356        pub const fn pwm_offset_l1(&self) -> &PwmOffsetL1 {
9357            &self.pwm_offset_l1
9358        }
9359        #[doc = "0x150 - PWM1 phase offset high"]
9360        #[inline(always)]
9361        pub const fn pwm_offset_h1(&self) -> &PwmOffsetH1 {
9362            &self.pwm_offset_h1
9363        }
9364        #[doc = "0x154 - PWM1 frequency low"]
9365        #[inline(always)]
9366        pub const fn pwm_freq_l1(&self) -> &PwmFreqL1 {
9367            &self.pwm_freq_l1
9368        }
9369        #[doc = "0x158 - PWM1 frequency high"]
9370        #[inline(always)]
9371        pub const fn pwm_freq_h1(&self) -> &PwmFreqH1 {
9372            &self.pwm_freq_h1
9373        }
9374        #[doc = "0x15c - PWM1 duty cycle low"]
9375        #[inline(always)]
9376        pub const fn pwm_duty_l1(&self) -> &PwmDutyL1 {
9377            &self.pwm_duty_l1
9378        }
9379        #[doc = "0x160 - PWM1 duty cycle high"]
9380        #[inline(always)]
9381        pub const fn pwm_duty_h1(&self) -> &PwmDutyH1 {
9382            &self.pwm_duty_h1
9383        }
9384        #[doc = "0x164 - PWM1 period load flag"]
9385        #[inline(always)]
9386        pub const fn pwm_periodload_flag1(&self) -> &PwmPeriodloadFlag1 {
9387            &self.pwm_periodload_flag1
9388        }
9389        #[doc = "0x168 - PWM1 pulse count"]
9390        #[inline(always)]
9391        pub const fn pwm_period_val1(&self) -> &PwmPeriodVal1 {
9392            &self.pwm_period_val1
9393        }
9394        #[doc = "0x16c - PWM1 pulse count current"]
9395        #[inline(always)]
9396        pub const fn pwm_periodcnt1(&self) -> &PwmPeriodcnt1 {
9397            &self.pwm_periodcnt1
9398        }
9399        #[doc = "0x180 - PWM2 enable"]
9400        #[inline(always)]
9401        pub const fn pwm_en2(&self) -> &PwmEn2 {
9402            &self.pwm_en2
9403        }
9404        #[doc = "0x184 - PWM2 polarity"]
9405        #[inline(always)]
9406        pub const fn pwm_portity2(&self) -> &PwmPortity2 {
9407            &self.pwm_portity2
9408        }
9409        #[doc = "0x188 - PWM2 high-impedance config"]
9410        #[inline(always)]
9411        pub const fn pwm_oen_cfg2(&self) -> &PwmOenCfg2 {
9412            &self.pwm_oen_cfg2
9413        }
9414        #[doc = "0x18c - PWM2 phase offset low 16 bits"]
9415        #[inline(always)]
9416        pub const fn pwm_offset_l2(&self) -> &PwmOffsetL2 {
9417            &self.pwm_offset_l2
9418        }
9419        #[doc = "0x190 - PWM2 phase offset high 16 bits"]
9420        #[inline(always)]
9421        pub const fn pwm_offset_h2(&self) -> &PwmOffsetH2 {
9422            &self.pwm_offset_h2
9423        }
9424        #[doc = "0x194 - PWM2 frequency low 16 bits"]
9425        #[inline(always)]
9426        pub const fn pwm_freq_l2(&self) -> &PwmFreqL2 {
9427            &self.pwm_freq_l2
9428        }
9429        #[doc = "0x198 - PWM2 frequency high 16 bits"]
9430        #[inline(always)]
9431        pub const fn pwm_freq_h2(&self) -> &PwmFreqH2 {
9432            &self.pwm_freq_h2
9433        }
9434        #[doc = "0x19c - PWM2 duty cycle low 16 bits"]
9435        #[inline(always)]
9436        pub const fn pwm_duty_l2(&self) -> &PwmDutyL2 {
9437            &self.pwm_duty_l2
9438        }
9439        #[doc = "0x1a0 - PWM2 duty cycle high 16 bits"]
9440        #[inline(always)]
9441        pub const fn pwm_duty_h2(&self) -> &PwmDutyH2 {
9442            &self.pwm_duty_h2
9443        }
9444        #[doc = "0x1a4 - PWM2 period load flag"]
9445        #[inline(always)]
9446        pub const fn pwm_periodload_flag2(&self) -> &PwmPeriodloadFlag2 {
9447            &self.pwm_periodload_flag2
9448        }
9449        #[doc = "0x1a8 - PWM2 pulse count value"]
9450        #[inline(always)]
9451        pub const fn pwm_period_val2(&self) -> &PwmPeriodVal2 {
9452            &self.pwm_period_val2
9453        }
9454        #[doc = "0x1ac - PWM2 pulse count current value"]
9455        #[inline(always)]
9456        pub const fn pwm_periodcnt2(&self) -> &PwmPeriodcnt2 {
9457            &self.pwm_periodcnt2
9458        }
9459        #[doc = "0x1c0 - PWM3 enable"]
9460        #[inline(always)]
9461        pub const fn pwm_en3(&self) -> &PwmEn3 {
9462            &self.pwm_en3
9463        }
9464        #[doc = "0x1c4 - PWM3 polarity"]
9465        #[inline(always)]
9466        pub const fn pwm_portity3(&self) -> &PwmPortity3 {
9467            &self.pwm_portity3
9468        }
9469        #[doc = "0x1c8 - PWM3 high-impedance config"]
9470        #[inline(always)]
9471        pub const fn pwm_oen_cfg3(&self) -> &PwmOenCfg3 {
9472            &self.pwm_oen_cfg3
9473        }
9474        #[doc = "0x1cc - PWM3 phase offset low 16 bits"]
9475        #[inline(always)]
9476        pub const fn pwm_offset_l3(&self) -> &PwmOffsetL3 {
9477            &self.pwm_offset_l3
9478        }
9479        #[doc = "0x1d0 - PWM3 phase offset high 16 bits"]
9480        #[inline(always)]
9481        pub const fn pwm_offset_h3(&self) -> &PwmOffsetH3 {
9482            &self.pwm_offset_h3
9483        }
9484        #[doc = "0x1d4 - PWM3 frequency low 16 bits"]
9485        #[inline(always)]
9486        pub const fn pwm_freq_l3(&self) -> &PwmFreqL3 {
9487            &self.pwm_freq_l3
9488        }
9489        #[doc = "0x1d8 - PWM3 frequency high 16 bits"]
9490        #[inline(always)]
9491        pub const fn pwm_freq_h3(&self) -> &PwmFreqH3 {
9492            &self.pwm_freq_h3
9493        }
9494        #[doc = "0x1dc - PWM3 duty cycle low 16 bits"]
9495        #[inline(always)]
9496        pub const fn pwm_duty_l3(&self) -> &PwmDutyL3 {
9497            &self.pwm_duty_l3
9498        }
9499        #[doc = "0x1e0 - PWM3 duty cycle high 16 bits"]
9500        #[inline(always)]
9501        pub const fn pwm_duty_h3(&self) -> &PwmDutyH3 {
9502            &self.pwm_duty_h3
9503        }
9504        #[doc = "0x1e4 - PWM3 period load flag"]
9505        #[inline(always)]
9506        pub const fn pwm_periodload_flag3(&self) -> &PwmPeriodloadFlag3 {
9507            &self.pwm_periodload_flag3
9508        }
9509        #[doc = "0x1e8 - PWM3 pulse count value"]
9510        #[inline(always)]
9511        pub const fn pwm_period_val3(&self) -> &PwmPeriodVal3 {
9512            &self.pwm_period_val3
9513        }
9514        #[doc = "0x1ec - PWM3 pulse count current value"]
9515        #[inline(always)]
9516        pub const fn pwm_periodcnt3(&self) -> &PwmPeriodcnt3 {
9517            &self.pwm_periodcnt3
9518        }
9519        #[doc = "0x200 - PWM4 enable"]
9520        #[inline(always)]
9521        pub const fn pwm_en4(&self) -> &PwmEn4 {
9522            &self.pwm_en4
9523        }
9524        #[doc = "0x204 - PWM4 polarity"]
9525        #[inline(always)]
9526        pub const fn pwm_portity4(&self) -> &PwmPortity4 {
9527            &self.pwm_portity4
9528        }
9529        #[doc = "0x208 - PWM4 high-impedance config"]
9530        #[inline(always)]
9531        pub const fn pwm_oen_cfg4(&self) -> &PwmOenCfg4 {
9532            &self.pwm_oen_cfg4
9533        }
9534        #[doc = "0x20c - PWM4 phase offset low 16 bits"]
9535        #[inline(always)]
9536        pub const fn pwm_offset_l4(&self) -> &PwmOffsetL4 {
9537            &self.pwm_offset_l4
9538        }
9539        #[doc = "0x210 - PWM4 phase offset high 16 bits"]
9540        #[inline(always)]
9541        pub const fn pwm_offset_h4(&self) -> &PwmOffsetH4 {
9542            &self.pwm_offset_h4
9543        }
9544        #[doc = "0x214 - PWM4 frequency low 16 bits"]
9545        #[inline(always)]
9546        pub const fn pwm_freq_l4(&self) -> &PwmFreqL4 {
9547            &self.pwm_freq_l4
9548        }
9549        #[doc = "0x218 - PWM4 frequency high 16 bits"]
9550        #[inline(always)]
9551        pub const fn pwm_freq_h4(&self) -> &PwmFreqH4 {
9552            &self.pwm_freq_h4
9553        }
9554        #[doc = "0x21c - PWM4 duty cycle low 16 bits"]
9555        #[inline(always)]
9556        pub const fn pwm_duty_l4(&self) -> &PwmDutyL4 {
9557            &self.pwm_duty_l4
9558        }
9559        #[doc = "0x220 - PWM4 duty cycle high 16 bits"]
9560        #[inline(always)]
9561        pub const fn pwm_duty_h4(&self) -> &PwmDutyH4 {
9562            &self.pwm_duty_h4
9563        }
9564        #[doc = "0x224 - PWM4 period load flag"]
9565        #[inline(always)]
9566        pub const fn pwm_periodload_flag4(&self) -> &PwmPeriodloadFlag4 {
9567            &self.pwm_periodload_flag4
9568        }
9569        #[doc = "0x228 - PWM4 pulse count value"]
9570        #[inline(always)]
9571        pub const fn pwm_period_val4(&self) -> &PwmPeriodVal4 {
9572            &self.pwm_period_val4
9573        }
9574        #[doc = "0x22c - PWM4 pulse count current value"]
9575        #[inline(always)]
9576        pub const fn pwm_periodcnt4(&self) -> &PwmPeriodcnt4 {
9577            &self.pwm_periodcnt4
9578        }
9579        #[doc = "0x240 - PWM5 enable"]
9580        #[inline(always)]
9581        pub const fn pwm_en5(&self) -> &PwmEn5 {
9582            &self.pwm_en5
9583        }
9584        #[doc = "0x244 - PWM5 polarity"]
9585        #[inline(always)]
9586        pub const fn pwm_portity5(&self) -> &PwmPortity5 {
9587            &self.pwm_portity5
9588        }
9589        #[doc = "0x248 - PWM5 high-impedance config"]
9590        #[inline(always)]
9591        pub const fn pwm_oen_cfg5(&self) -> &PwmOenCfg5 {
9592            &self.pwm_oen_cfg5
9593        }
9594        #[doc = "0x24c - PWM5 phase offset low 16 bits"]
9595        #[inline(always)]
9596        pub const fn pwm_offset_l5(&self) -> &PwmOffsetL5 {
9597            &self.pwm_offset_l5
9598        }
9599        #[doc = "0x250 - PWM5 phase offset high 16 bits"]
9600        #[inline(always)]
9601        pub const fn pwm_offset_h5(&self) -> &PwmOffsetH5 {
9602            &self.pwm_offset_h5
9603        }
9604        #[doc = "0x254 - PWM5 frequency low 16 bits"]
9605        #[inline(always)]
9606        pub const fn pwm_freq_l5(&self) -> &PwmFreqL5 {
9607            &self.pwm_freq_l5
9608        }
9609        #[doc = "0x258 - PWM5 frequency high 16 bits"]
9610        #[inline(always)]
9611        pub const fn pwm_freq_h5(&self) -> &PwmFreqH5 {
9612            &self.pwm_freq_h5
9613        }
9614        #[doc = "0x25c - PWM5 duty cycle low 16 bits"]
9615        #[inline(always)]
9616        pub const fn pwm_duty_l5(&self) -> &PwmDutyL5 {
9617            &self.pwm_duty_l5
9618        }
9619        #[doc = "0x260 - PWM5 duty cycle high 16 bits"]
9620        #[inline(always)]
9621        pub const fn pwm_duty_h5(&self) -> &PwmDutyH5 {
9622            &self.pwm_duty_h5
9623        }
9624        #[doc = "0x264 - PWM5 period load flag"]
9625        #[inline(always)]
9626        pub const fn pwm_periodload_flag5(&self) -> &PwmPeriodloadFlag5 {
9627            &self.pwm_periodload_flag5
9628        }
9629        #[doc = "0x268 - PWM5 pulse count value"]
9630        #[inline(always)]
9631        pub const fn pwm_period_val5(&self) -> &PwmPeriodVal5 {
9632            &self.pwm_period_val5
9633        }
9634        #[doc = "0x26c - PWM5 pulse count current value"]
9635        #[inline(always)]
9636        pub const fn pwm_periodcnt5(&self) -> &PwmPeriodcnt5 {
9637            &self.pwm_periodcnt5
9638        }
9639        #[doc = "0x280 - PWM6 enable"]
9640        #[inline(always)]
9641        pub const fn pwm_en6(&self) -> &PwmEn6 {
9642            &self.pwm_en6
9643        }
9644        #[doc = "0x284 - PWM6 polarity"]
9645        #[inline(always)]
9646        pub const fn pwm_portity6(&self) -> &PwmPortity6 {
9647            &self.pwm_portity6
9648        }
9649        #[doc = "0x288 - PWM6 high-impedance config"]
9650        #[inline(always)]
9651        pub const fn pwm_oen_cfg6(&self) -> &PwmOenCfg6 {
9652            &self.pwm_oen_cfg6
9653        }
9654        #[doc = "0x28c - PWM6 phase offset low 16 bits"]
9655        #[inline(always)]
9656        pub const fn pwm_offset_l6(&self) -> &PwmOffsetL6 {
9657            &self.pwm_offset_l6
9658        }
9659        #[doc = "0x290 - PWM6 phase offset high 16 bits"]
9660        #[inline(always)]
9661        pub const fn pwm_offset_h6(&self) -> &PwmOffsetH6 {
9662            &self.pwm_offset_h6
9663        }
9664        #[doc = "0x294 - PWM6 frequency low 16 bits"]
9665        #[inline(always)]
9666        pub const fn pwm_freq_l6(&self) -> &PwmFreqL6 {
9667            &self.pwm_freq_l6
9668        }
9669        #[doc = "0x298 - PWM6 frequency high 16 bits"]
9670        #[inline(always)]
9671        pub const fn pwm_freq_h6(&self) -> &PwmFreqH6 {
9672            &self.pwm_freq_h6
9673        }
9674        #[doc = "0x29c - PWM6 duty cycle low 16 bits"]
9675        #[inline(always)]
9676        pub const fn pwm_duty_l6(&self) -> &PwmDutyL6 {
9677            &self.pwm_duty_l6
9678        }
9679        #[doc = "0x2a0 - PWM6 duty cycle high 16 bits"]
9680        #[inline(always)]
9681        pub const fn pwm_duty_h6(&self) -> &PwmDutyH6 {
9682            &self.pwm_duty_h6
9683        }
9684        #[doc = "0x2a4 - PWM6 period load flag"]
9685        #[inline(always)]
9686        pub const fn pwm_periodload_flag6(&self) -> &PwmPeriodloadFlag6 {
9687            &self.pwm_periodload_flag6
9688        }
9689        #[doc = "0x2a8 - PWM6 pulse count value"]
9690        #[inline(always)]
9691        pub const fn pwm_period_val6(&self) -> &PwmPeriodVal6 {
9692            &self.pwm_period_val6
9693        }
9694        #[doc = "0x2ac - PWM6 pulse count current value"]
9695        #[inline(always)]
9696        pub const fn pwm_periodcnt6(&self) -> &PwmPeriodcnt6 {
9697            &self.pwm_periodcnt6
9698        }
9699        #[doc = "0x2c0 - PWM7 enable"]
9700        #[inline(always)]
9701        pub const fn pwm_en7(&self) -> &PwmEn7 {
9702            &self.pwm_en7
9703        }
9704        #[doc = "0x2c4 - PWM7 polarity"]
9705        #[inline(always)]
9706        pub const fn pwm_portity7(&self) -> &PwmPortity7 {
9707            &self.pwm_portity7
9708        }
9709        #[doc = "0x2c8 - PWM7 high-impedance config"]
9710        #[inline(always)]
9711        pub const fn pwm_oen_cfg7(&self) -> &PwmOenCfg7 {
9712            &self.pwm_oen_cfg7
9713        }
9714        #[doc = "0x2cc - PWM7 phase offset low 16 bits"]
9715        #[inline(always)]
9716        pub const fn pwm_offset_l7(&self) -> &PwmOffsetL7 {
9717            &self.pwm_offset_l7
9718        }
9719        #[doc = "0x2d0 - PWM7 phase offset high 16 bits"]
9720        #[inline(always)]
9721        pub const fn pwm_offset_h7(&self) -> &PwmOffsetH7 {
9722            &self.pwm_offset_h7
9723        }
9724        #[doc = "0x2d4 - PWM7 frequency low 16 bits"]
9725        #[inline(always)]
9726        pub const fn pwm_freq_l7(&self) -> &PwmFreqL7 {
9727            &self.pwm_freq_l7
9728        }
9729        #[doc = "0x2d8 - PWM7 frequency high 16 bits"]
9730        #[inline(always)]
9731        pub const fn pwm_freq_h7(&self) -> &PwmFreqH7 {
9732            &self.pwm_freq_h7
9733        }
9734        #[doc = "0x2dc - PWM7 duty cycle low 16 bits"]
9735        #[inline(always)]
9736        pub const fn pwm_duty_l7(&self) -> &PwmDutyL7 {
9737            &self.pwm_duty_l7
9738        }
9739        #[doc = "0x2e0 - PWM7 duty cycle high 16 bits"]
9740        #[inline(always)]
9741        pub const fn pwm_duty_h7(&self) -> &PwmDutyH7 {
9742            &self.pwm_duty_h7
9743        }
9744        #[doc = "0x2e4 - PWM7 period load flag"]
9745        #[inline(always)]
9746        pub const fn pwm_periodload_flag7(&self) -> &PwmPeriodloadFlag7 {
9747            &self.pwm_periodload_flag7
9748        }
9749        #[doc = "0x2e8 - PWM7 pulse count value"]
9750        #[inline(always)]
9751        pub const fn pwm_period_val7(&self) -> &PwmPeriodVal7 {
9752            &self.pwm_period_val7
9753        }
9754        #[doc = "0x2ec - PWM7 pulse count current value"]
9755        #[inline(always)]
9756        pub const fn pwm_periodcnt7(&self) -> &PwmPeriodcnt7 {
9757            &self.pwm_periodcnt7
9758        }
9759        #[doc = "0x500 - PWM abnormal state register 0"]
9760        #[inline(always)]
9761        pub const fn pwm_abnor_state0(&self) -> &PwmAbnorState0 {
9762            &self.pwm_abnor_state0
9763        }
9764        #[doc = "0x504 - PWM abnormal state register 1"]
9765        #[inline(always)]
9766        pub const fn pwm_abnor_state1(&self) -> &PwmAbnorState1 {
9767            &self.pwm_abnor_state1
9768        }
9769        #[doc = "0x508 - PWM abnormal state clear 0"]
9770        #[inline(always)]
9771        pub const fn pwm_abnor_state_clr0(&self) -> &PwmAbnorStateClr0 {
9772            &self.pwm_abnor_state_clr0
9773        }
9774        #[doc = "0x50c - PWM abnormal state clear 1"]
9775        #[inline(always)]
9776        pub const fn pwm_abnor_state_clr1(&self) -> &PwmAbnorStateClr1 {
9777            &self.pwm_abnor_state_clr1
9778        }
9779        #[doc = "0x510 - PWM interrupt mask"]
9780        #[inline(always)]
9781        pub const fn pwm_int_mask(&self) -> &PwmIntMask {
9782            &self.pwm_int_mask
9783        }
9784        #[doc = "0x514 - PWM DMA enable"]
9785        #[inline(always)]
9786        pub const fn pwm_dma_en(&self) -> &PwmDmaEn {
9787            &self.pwm_dma_en
9788        }
9789        #[doc = "0x518 - PWM stepping cycle end interrupt clear"]
9790        #[inline(always)]
9791        pub const fn pwm_cfg_int_clr0(&self) -> &PwmCfgIntClr0 {
9792            &self.pwm_cfg_int_clr0
9793        }
9794    }
9795    #[doc = "PWM_SEL0 (rw) register accessor: PWM group 0 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel0`] module"]
9796    #[doc(alias = "PWM_SEL0")]
9797    pub type PwmSel0 = crate::Reg<pwm_sel0::PwmSel0Spec>;
9798    #[doc = "PWM group 0 select"]
9799    pub mod pwm_sel0 {
9800        #[doc = "Register `PWM_SEL0` reader"]
9801        pub type R = crate::R<PwmSel0Spec>;
9802        #[doc = "Register `PWM_SEL0` writer"]
9803        pub type W = crate::W<PwmSel0Spec>;
9804        #[doc = "Field `pwm_sel_0` reader - Group 0 PWM select, each bit corresponds to one PWM channel"]
9805        pub type PwmSel0R = crate::FieldReader<u16>;
9806        #[doc = "Field `pwm_sel_0` writer - Group 0 PWM select, each bit corresponds to one PWM channel"]
9807        pub type PwmSel0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9808        impl R {
9809            #[doc = "Bits 0:15 - Group 0 PWM select, each bit corresponds to one PWM channel"]
9810            #[inline(always)]
9811            pub fn pwm_sel_0(&self) -> PwmSel0R {
9812                PwmSel0R::new((self.bits & 0xffff) as u16)
9813            }
9814        }
9815        impl W {
9816            #[doc = "Bits 0:15 - Group 0 PWM select, each bit corresponds to one PWM channel"]
9817            #[inline(always)]
9818            pub fn pwm_sel_0(&mut self) -> PwmSel0W<'_, PwmSel0Spec> {
9819                PwmSel0W::new(self, 0)
9820            }
9821        }
9822        #[doc = "PWM group 0 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9823        pub struct PwmSel0Spec;
9824        impl crate::RegisterSpec for PwmSel0Spec {
9825            type Ux = u32;
9826        }
9827        #[doc = "`read()` method returns [`pwm_sel0::R`](R) reader structure"]
9828        impl crate::Readable for PwmSel0Spec {}
9829        #[doc = "`write(|w| ..)` method takes [`pwm_sel0::W`](W) writer structure"]
9830        impl crate::Writable for PwmSel0Spec {
9831            type Safety = crate::Unsafe;
9832        }
9833        #[doc = "`reset()` method sets PWM_SEL0 to value 0"]
9834        impl crate::Resettable for PwmSel0Spec {}
9835    }
9836    #[doc = "PWM_STARTCLRCNT_EN0 (rw) register accessor: PWM group 0 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en0`] module"]
9837    #[doc(alias = "PWM_STARTCLRCNT_EN0")]
9838    pub type PwmStartclrcntEn0 = crate::Reg<pwm_startclrcnt_en0::PwmStartclrcntEn0Spec>;
9839    #[doc = "PWM group 0 start clear counter enable"]
9840    pub mod pwm_startclrcnt_en0 {
9841        #[doc = "Register `PWM_STARTCLRCNT_EN0` reader"]
9842        pub type R = crate::R<PwmStartclrcntEn0Spec>;
9843        #[doc = "Register `PWM_STARTCLRCNT_EN0` writer"]
9844        pub type W = crate::W<PwmStartclrcntEn0Spec>;
9845        #[doc = "Field `pwm_startclrcnt_en_0` reader - Start clear counter enable for group 0"]
9846        pub type PwmStartclrcntEn0R = crate::BitReader;
9847        #[doc = "Field `pwm_startclrcnt_en_0` writer - Start clear counter enable for group 0"]
9848        pub type PwmStartclrcntEn0W<'a, REG> = crate::BitWriter<'a, REG>;
9849        impl R {
9850            #[doc = "Bit 0 - Start clear counter enable for group 0"]
9851            #[inline(always)]
9852            pub fn pwm_startclrcnt_en_0(&self) -> PwmStartclrcntEn0R {
9853                PwmStartclrcntEn0R::new((self.bits & 1) != 0)
9854            }
9855        }
9856        impl W {
9857            #[doc = "Bit 0 - Start clear counter enable for group 0"]
9858            #[inline(always)]
9859            pub fn pwm_startclrcnt_en_0(
9860                &mut self,
9861            ) -> PwmStartclrcntEn0W<'_, PwmStartclrcntEn0Spec> {
9862                PwmStartclrcntEn0W::new(self, 0)
9863            }
9864        }
9865        #[doc = "PWM group 0 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9866        pub struct PwmStartclrcntEn0Spec;
9867        impl crate::RegisterSpec for PwmStartclrcntEn0Spec {
9868            type Ux = u32;
9869        }
9870        #[doc = "`read()` method returns [`pwm_startclrcnt_en0::R`](R) reader structure"]
9871        impl crate::Readable for PwmStartclrcntEn0Spec {}
9872        #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en0::W`](W) writer structure"]
9873        impl crate::Writable for PwmStartclrcntEn0Spec {
9874            type Safety = crate::Unsafe;
9875        }
9876        #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN0 to value 0"]
9877        impl crate::Resettable for PwmStartclrcntEn0Spec {}
9878    }
9879    #[doc = "PWM_START0 (rw) register accessor: PWM group 0 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start0`] module"]
9880    #[doc(alias = "PWM_START0")]
9881    pub type PwmStart0 = crate::Reg<pwm_start0::PwmStart0Spec>;
9882    #[doc = "PWM group 0 start"]
9883    pub mod pwm_start0 {
9884        #[doc = "Register `PWM_START0` reader"]
9885        pub type R = crate::R<PwmStart0Spec>;
9886        #[doc = "Register `PWM_START0` writer"]
9887        pub type W = crate::W<PwmStart0Spec>;
9888        #[doc = "Field `pwm_start_0` writer - Start group 0 (self-clearing)"]
9889        pub type PwmStart0W<'a, REG> = crate::BitWriter<'a, REG>;
9890        impl W {
9891            #[doc = "Bit 0 - Start group 0 (self-clearing)"]
9892            #[inline(always)]
9893            pub fn pwm_start_0(&mut self) -> PwmStart0W<'_, PwmStart0Spec> {
9894                PwmStart0W::new(self, 0)
9895            }
9896        }
9897        #[doc = "PWM group 0 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9898        pub struct PwmStart0Spec;
9899        impl crate::RegisterSpec for PwmStart0Spec {
9900            type Ux = u32;
9901        }
9902        #[doc = "`read()` method returns [`pwm_start0::R`](R) reader structure"]
9903        impl crate::Readable for PwmStart0Spec {}
9904        #[doc = "`write(|w| ..)` method takes [`pwm_start0::W`](W) writer structure"]
9905        impl crate::Writable for PwmStart0Spec {
9906            type Safety = crate::Unsafe;
9907        }
9908        #[doc = "`reset()` method sets PWM_START0 to value 0"]
9909        impl crate::Resettable for PwmStart0Spec {}
9910    }
9911    #[doc = "PWM_SEL1 (rw) register accessor: PWM group 1 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel1`] module"]
9912    #[doc(alias = "PWM_SEL1")]
9913    pub type PwmSel1 = crate::Reg<pwm_sel1::PwmSel1Spec>;
9914    #[doc = "PWM group 1 select"]
9915    pub mod pwm_sel1 {
9916        #[doc = "Register `PWM_SEL1` reader"]
9917        pub type R = crate::R<PwmSel1Spec>;
9918        #[doc = "Register `PWM_SEL1` writer"]
9919        pub type W = crate::W<PwmSel1Spec>;
9920        #[doc = "Field `pwm_sel_1` reader - Group 1 PWM select"]
9921        pub type PwmSel1R = crate::FieldReader<u16>;
9922        #[doc = "Field `pwm_sel_1` writer - Group 1 PWM select"]
9923        pub type PwmSel1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9924        impl R {
9925            #[doc = "Bits 0:15 - Group 1 PWM select"]
9926            #[inline(always)]
9927            pub fn pwm_sel_1(&self) -> PwmSel1R {
9928                PwmSel1R::new((self.bits & 0xffff) as u16)
9929            }
9930        }
9931        impl W {
9932            #[doc = "Bits 0:15 - Group 1 PWM select"]
9933            #[inline(always)]
9934            pub fn pwm_sel_1(&mut self) -> PwmSel1W<'_, PwmSel1Spec> {
9935                PwmSel1W::new(self, 0)
9936            }
9937        }
9938        #[doc = "PWM group 1 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9939        pub struct PwmSel1Spec;
9940        impl crate::RegisterSpec for PwmSel1Spec {
9941            type Ux = u32;
9942        }
9943        #[doc = "`read()` method returns [`pwm_sel1::R`](R) reader structure"]
9944        impl crate::Readable for PwmSel1Spec {}
9945        #[doc = "`write(|w| ..)` method takes [`pwm_sel1::W`](W) writer structure"]
9946        impl crate::Writable for PwmSel1Spec {
9947            type Safety = crate::Unsafe;
9948        }
9949        #[doc = "`reset()` method sets PWM_SEL1 to value 0"]
9950        impl crate::Resettable for PwmSel1Spec {}
9951    }
9952    #[doc = "PWM_STARTCLRCNT_EN1 (rw) register accessor: PWM group 1 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en1`] module"]
9953    #[doc(alias = "PWM_STARTCLRCNT_EN1")]
9954    pub type PwmStartclrcntEn1 = crate::Reg<pwm_startclrcnt_en1::PwmStartclrcntEn1Spec>;
9955    #[doc = "PWM group 1 start clear counter enable"]
9956    pub mod pwm_startclrcnt_en1 {
9957        #[doc = "Register `PWM_STARTCLRCNT_EN1` reader"]
9958        pub type R = crate::R<PwmStartclrcntEn1Spec>;
9959        #[doc = "Register `PWM_STARTCLRCNT_EN1` writer"]
9960        pub type W = crate::W<PwmStartclrcntEn1Spec>;
9961        #[doc = "Field `pwm_startclrcnt_en_1` reader - Start clear counter enable for group 1"]
9962        pub type PwmStartclrcntEn1R = crate::BitReader;
9963        #[doc = "Field `pwm_startclrcnt_en_1` writer - Start clear counter enable for group 1"]
9964        pub type PwmStartclrcntEn1W<'a, REG> = crate::BitWriter<'a, REG>;
9965        impl R {
9966            #[doc = "Bit 0 - Start clear counter enable for group 1"]
9967            #[inline(always)]
9968            pub fn pwm_startclrcnt_en_1(&self) -> PwmStartclrcntEn1R {
9969                PwmStartclrcntEn1R::new((self.bits & 1) != 0)
9970            }
9971        }
9972        impl W {
9973            #[doc = "Bit 0 - Start clear counter enable for group 1"]
9974            #[inline(always)]
9975            pub fn pwm_startclrcnt_en_1(
9976                &mut self,
9977            ) -> PwmStartclrcntEn1W<'_, PwmStartclrcntEn1Spec> {
9978                PwmStartclrcntEn1W::new(self, 0)
9979            }
9980        }
9981        #[doc = "PWM group 1 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9982        pub struct PwmStartclrcntEn1Spec;
9983        impl crate::RegisterSpec for PwmStartclrcntEn1Spec {
9984            type Ux = u32;
9985        }
9986        #[doc = "`read()` method returns [`pwm_startclrcnt_en1::R`](R) reader structure"]
9987        impl crate::Readable for PwmStartclrcntEn1Spec {}
9988        #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en1::W`](W) writer structure"]
9989        impl crate::Writable for PwmStartclrcntEn1Spec {
9990            type Safety = crate::Unsafe;
9991        }
9992        #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN1 to value 0"]
9993        impl crate::Resettable for PwmStartclrcntEn1Spec {}
9994    }
9995    #[doc = "PWM_START1 (rw) register accessor: PWM group 1 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start1`] module"]
9996    #[doc(alias = "PWM_START1")]
9997    pub type PwmStart1 = crate::Reg<pwm_start1::PwmStart1Spec>;
9998    #[doc = "PWM group 1 start"]
9999    pub mod pwm_start1 {
10000        #[doc = "Register `PWM_START1` reader"]
10001        pub type R = crate::R<PwmStart1Spec>;
10002        #[doc = "Register `PWM_START1` writer"]
10003        pub type W = crate::W<PwmStart1Spec>;
10004        #[doc = "Field `pwm_start_1` writer - Start group 1 (self-clearing)"]
10005        pub type PwmStart1W<'a, REG> = crate::BitWriter<'a, REG>;
10006        impl W {
10007            #[doc = "Bit 0 - Start group 1 (self-clearing)"]
10008            #[inline(always)]
10009            pub fn pwm_start_1(&mut self) -> PwmStart1W<'_, PwmStart1Spec> {
10010                PwmStart1W::new(self, 0)
10011            }
10012        }
10013        #[doc = "PWM group 1 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10014        pub struct PwmStart1Spec;
10015        impl crate::RegisterSpec for PwmStart1Spec {
10016            type Ux = u32;
10017        }
10018        #[doc = "`read()` method returns [`pwm_start1::R`](R) reader structure"]
10019        impl crate::Readable for PwmStart1Spec {}
10020        #[doc = "`write(|w| ..)` method takes [`pwm_start1::W`](W) writer structure"]
10021        impl crate::Writable for PwmStart1Spec {
10022            type Safety = crate::Unsafe;
10023        }
10024        #[doc = "`reset()` method sets PWM_START1 to value 0"]
10025        impl crate::Resettable for PwmStart1Spec {}
10026    }
10027    #[doc = "PWM_SEL2 (rw) register accessor: PWM group 2 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel2`] module"]
10028    #[doc(alias = "PWM_SEL2")]
10029    pub type PwmSel2 = crate::Reg<pwm_sel2::PwmSel2Spec>;
10030    #[doc = "PWM group 2 select"]
10031    pub mod pwm_sel2 {
10032        #[doc = "Register `PWM_SEL2` reader"]
10033        pub type R = crate::R<PwmSel2Spec>;
10034        #[doc = "Register `PWM_SEL2` writer"]
10035        pub type W = crate::W<PwmSel2Spec>;
10036        #[doc = "Field `pwm_sel_2` reader - Group 2 PWM select"]
10037        pub type PwmSel2R = crate::FieldReader<u16>;
10038        #[doc = "Field `pwm_sel_2` writer - Group 2 PWM select"]
10039        pub type PwmSel2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10040        impl R {
10041            #[doc = "Bits 0:15 - Group 2 PWM select"]
10042            #[inline(always)]
10043            pub fn pwm_sel_2(&self) -> PwmSel2R {
10044                PwmSel2R::new((self.bits & 0xffff) as u16)
10045            }
10046        }
10047        impl W {
10048            #[doc = "Bits 0:15 - Group 2 PWM select"]
10049            #[inline(always)]
10050            pub fn pwm_sel_2(&mut self) -> PwmSel2W<'_, PwmSel2Spec> {
10051                PwmSel2W::new(self, 0)
10052            }
10053        }
10054        #[doc = "PWM group 2 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10055        pub struct PwmSel2Spec;
10056        impl crate::RegisterSpec for PwmSel2Spec {
10057            type Ux = u32;
10058        }
10059        #[doc = "`read()` method returns [`pwm_sel2::R`](R) reader structure"]
10060        impl crate::Readable for PwmSel2Spec {}
10061        #[doc = "`write(|w| ..)` method takes [`pwm_sel2::W`](W) writer structure"]
10062        impl crate::Writable for PwmSel2Spec {
10063            type Safety = crate::Unsafe;
10064        }
10065        #[doc = "`reset()` method sets PWM_SEL2 to value 0"]
10066        impl crate::Resettable for PwmSel2Spec {}
10067    }
10068    #[doc = "PWM_STARTCLRCNT_EN2 (rw) register accessor: PWM group 2 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en2`] module"]
10069    #[doc(alias = "PWM_STARTCLRCNT_EN2")]
10070    pub type PwmStartclrcntEn2 = crate::Reg<pwm_startclrcnt_en2::PwmStartclrcntEn2Spec>;
10071    #[doc = "PWM group 2 start clear counter enable"]
10072    pub mod pwm_startclrcnt_en2 {
10073        #[doc = "Register `PWM_STARTCLRCNT_EN2` reader"]
10074        pub type R = crate::R<PwmStartclrcntEn2Spec>;
10075        #[doc = "Register `PWM_STARTCLRCNT_EN2` writer"]
10076        pub type W = crate::W<PwmStartclrcntEn2Spec>;
10077        #[doc = "Field `pwm_startclrcnt_en_2` reader - Start clear counter enable for group 2"]
10078        pub type PwmStartclrcntEn2R = crate::BitReader;
10079        #[doc = "Field `pwm_startclrcnt_en_2` writer - Start clear counter enable for group 2"]
10080        pub type PwmStartclrcntEn2W<'a, REG> = crate::BitWriter<'a, REG>;
10081        impl R {
10082            #[doc = "Bit 0 - Start clear counter enable for group 2"]
10083            #[inline(always)]
10084            pub fn pwm_startclrcnt_en_2(&self) -> PwmStartclrcntEn2R {
10085                PwmStartclrcntEn2R::new((self.bits & 1) != 0)
10086            }
10087        }
10088        impl W {
10089            #[doc = "Bit 0 - Start clear counter enable for group 2"]
10090            #[inline(always)]
10091            pub fn pwm_startclrcnt_en_2(
10092                &mut self,
10093            ) -> PwmStartclrcntEn2W<'_, PwmStartclrcntEn2Spec> {
10094                PwmStartclrcntEn2W::new(self, 0)
10095            }
10096        }
10097        #[doc = "PWM group 2 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10098        pub struct PwmStartclrcntEn2Spec;
10099        impl crate::RegisterSpec for PwmStartclrcntEn2Spec {
10100            type Ux = u32;
10101        }
10102        #[doc = "`read()` method returns [`pwm_startclrcnt_en2::R`](R) reader structure"]
10103        impl crate::Readable for PwmStartclrcntEn2Spec {}
10104        #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en2::W`](W) writer structure"]
10105        impl crate::Writable for PwmStartclrcntEn2Spec {
10106            type Safety = crate::Unsafe;
10107        }
10108        #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN2 to value 0"]
10109        impl crate::Resettable for PwmStartclrcntEn2Spec {}
10110    }
10111    #[doc = "PWM_START2 (rw) register accessor: PWM group 2 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start2`] module"]
10112    #[doc(alias = "PWM_START2")]
10113    pub type PwmStart2 = crate::Reg<pwm_start2::PwmStart2Spec>;
10114    #[doc = "PWM group 2 start"]
10115    pub mod pwm_start2 {
10116        #[doc = "Register `PWM_START2` reader"]
10117        pub type R = crate::R<PwmStart2Spec>;
10118        #[doc = "Register `PWM_START2` writer"]
10119        pub type W = crate::W<PwmStart2Spec>;
10120        #[doc = "Field `pwm_start_2` writer - Start group 2 (self-clearing)"]
10121        pub type PwmStart2W<'a, REG> = crate::BitWriter<'a, REG>;
10122        impl W {
10123            #[doc = "Bit 0 - Start group 2 (self-clearing)"]
10124            #[inline(always)]
10125            pub fn pwm_start_2(&mut self) -> PwmStart2W<'_, PwmStart2Spec> {
10126                PwmStart2W::new(self, 0)
10127            }
10128        }
10129        #[doc = "PWM group 2 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10130        pub struct PwmStart2Spec;
10131        impl crate::RegisterSpec for PwmStart2Spec {
10132            type Ux = u32;
10133        }
10134        #[doc = "`read()` method returns [`pwm_start2::R`](R) reader structure"]
10135        impl crate::Readable for PwmStart2Spec {}
10136        #[doc = "`write(|w| ..)` method takes [`pwm_start2::W`](W) writer structure"]
10137        impl crate::Writable for PwmStart2Spec {
10138            type Safety = crate::Unsafe;
10139        }
10140        #[doc = "`reset()` method sets PWM_START2 to value 0"]
10141        impl crate::Resettable for PwmStart2Spec {}
10142    }
10143    #[doc = "PWM_SEL3 (rw) register accessor: PWM group 3 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel3`] module"]
10144    #[doc(alias = "PWM_SEL3")]
10145    pub type PwmSel3 = crate::Reg<pwm_sel3::PwmSel3Spec>;
10146    #[doc = "PWM group 3 select"]
10147    pub mod pwm_sel3 {
10148        #[doc = "Register `PWM_SEL3` reader"]
10149        pub type R = crate::R<PwmSel3Spec>;
10150        #[doc = "Register `PWM_SEL3` writer"]
10151        pub type W = crate::W<PwmSel3Spec>;
10152        #[doc = "Field `pwm_sel_3` reader - Group 3 PWM select"]
10153        pub type PwmSel3R = crate::FieldReader<u16>;
10154        #[doc = "Field `pwm_sel_3` writer - Group 3 PWM select"]
10155        pub type PwmSel3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10156        impl R {
10157            #[doc = "Bits 0:15 - Group 3 PWM select"]
10158            #[inline(always)]
10159            pub fn pwm_sel_3(&self) -> PwmSel3R {
10160                PwmSel3R::new((self.bits & 0xffff) as u16)
10161            }
10162        }
10163        impl W {
10164            #[doc = "Bits 0:15 - Group 3 PWM select"]
10165            #[inline(always)]
10166            pub fn pwm_sel_3(&mut self) -> PwmSel3W<'_, PwmSel3Spec> {
10167                PwmSel3W::new(self, 0)
10168            }
10169        }
10170        #[doc = "PWM group 3 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10171        pub struct PwmSel3Spec;
10172        impl crate::RegisterSpec for PwmSel3Spec {
10173            type Ux = u32;
10174        }
10175        #[doc = "`read()` method returns [`pwm_sel3::R`](R) reader structure"]
10176        impl crate::Readable for PwmSel3Spec {}
10177        #[doc = "`write(|w| ..)` method takes [`pwm_sel3::W`](W) writer structure"]
10178        impl crate::Writable for PwmSel3Spec {
10179            type Safety = crate::Unsafe;
10180        }
10181        #[doc = "`reset()` method sets PWM_SEL3 to value 0"]
10182        impl crate::Resettable for PwmSel3Spec {}
10183    }
10184    #[doc = "PWM_STARTCLRCNT_EN3 (rw) register accessor: PWM group 3 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en3`] module"]
10185    #[doc(alias = "PWM_STARTCLRCNT_EN3")]
10186    pub type PwmStartclrcntEn3 = crate::Reg<pwm_startclrcnt_en3::PwmStartclrcntEn3Spec>;
10187    #[doc = "PWM group 3 start clear counter enable"]
10188    pub mod pwm_startclrcnt_en3 {
10189        #[doc = "Register `PWM_STARTCLRCNT_EN3` reader"]
10190        pub type R = crate::R<PwmStartclrcntEn3Spec>;
10191        #[doc = "Register `PWM_STARTCLRCNT_EN3` writer"]
10192        pub type W = crate::W<PwmStartclrcntEn3Spec>;
10193        #[doc = "Field `pwm_startclrcnt_en_3` reader - Start clear counter enable for group 3"]
10194        pub type PwmStartclrcntEn3R = crate::BitReader;
10195        #[doc = "Field `pwm_startclrcnt_en_3` writer - Start clear counter enable for group 3"]
10196        pub type PwmStartclrcntEn3W<'a, REG> = crate::BitWriter<'a, REG>;
10197        impl R {
10198            #[doc = "Bit 0 - Start clear counter enable for group 3"]
10199            #[inline(always)]
10200            pub fn pwm_startclrcnt_en_3(&self) -> PwmStartclrcntEn3R {
10201                PwmStartclrcntEn3R::new((self.bits & 1) != 0)
10202            }
10203        }
10204        impl W {
10205            #[doc = "Bit 0 - Start clear counter enable for group 3"]
10206            #[inline(always)]
10207            pub fn pwm_startclrcnt_en_3(
10208                &mut self,
10209            ) -> PwmStartclrcntEn3W<'_, PwmStartclrcntEn3Spec> {
10210                PwmStartclrcntEn3W::new(self, 0)
10211            }
10212        }
10213        #[doc = "PWM group 3 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10214        pub struct PwmStartclrcntEn3Spec;
10215        impl crate::RegisterSpec for PwmStartclrcntEn3Spec {
10216            type Ux = u32;
10217        }
10218        #[doc = "`read()` method returns [`pwm_startclrcnt_en3::R`](R) reader structure"]
10219        impl crate::Readable for PwmStartclrcntEn3Spec {}
10220        #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en3::W`](W) writer structure"]
10221        impl crate::Writable for PwmStartclrcntEn3Spec {
10222            type Safety = crate::Unsafe;
10223        }
10224        #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN3 to value 0"]
10225        impl crate::Resettable for PwmStartclrcntEn3Spec {}
10226    }
10227    #[doc = "PWM_START3 (rw) register accessor: PWM group 3 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start3`] module"]
10228    #[doc(alias = "PWM_START3")]
10229    pub type PwmStart3 = crate::Reg<pwm_start3::PwmStart3Spec>;
10230    #[doc = "PWM group 3 start"]
10231    pub mod pwm_start3 {
10232        #[doc = "Register `PWM_START3` reader"]
10233        pub type R = crate::R<PwmStart3Spec>;
10234        #[doc = "Register `PWM_START3` writer"]
10235        pub type W = crate::W<PwmStart3Spec>;
10236        #[doc = "Field `pwm_start_3` writer - Start group 3 (self-clearing)"]
10237        pub type PwmStart3W<'a, REG> = crate::BitWriter<'a, REG>;
10238        impl W {
10239            #[doc = "Bit 0 - Start group 3 (self-clearing)"]
10240            #[inline(always)]
10241            pub fn pwm_start_3(&mut self) -> PwmStart3W<'_, PwmStart3Spec> {
10242                PwmStart3W::new(self, 0)
10243            }
10244        }
10245        #[doc = "PWM group 3 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10246        pub struct PwmStart3Spec;
10247        impl crate::RegisterSpec for PwmStart3Spec {
10248            type Ux = u32;
10249        }
10250        #[doc = "`read()` method returns [`pwm_start3::R`](R) reader structure"]
10251        impl crate::Readable for PwmStart3Spec {}
10252        #[doc = "`write(|w| ..)` method takes [`pwm_start3::W`](W) writer structure"]
10253        impl crate::Writable for PwmStart3Spec {
10254            type Safety = crate::Unsafe;
10255        }
10256        #[doc = "`reset()` method sets PWM_START3 to value 0"]
10257        impl crate::Resettable for PwmStart3Spec {}
10258    }
10259    #[doc = "PWM_EN0 (rw) register accessor: PWM0 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en0`] module"]
10260    #[doc(alias = "PWM_EN0")]
10261    pub type PwmEn0 = crate::Reg<pwm_en0::PwmEn0Spec>;
10262    #[doc = "PWM0 enable"]
10263    pub mod pwm_en0 {
10264        #[doc = "Register `PWM_EN0` reader"]
10265        pub type R = crate::R<PwmEn0Spec>;
10266        #[doc = "Register `PWM_EN0` writer"]
10267        pub type W = crate::W<PwmEn0Spec>;
10268        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
10269        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
10270        pub enum PwmEn0 {
10271            #[doc = "0: PWM disabled, output low"]
10272            Off = 0,
10273            #[doc = "1: PWM enabled"]
10274            On = 1,
10275        }
10276        impl From<PwmEn0> for bool {
10277            #[inline(always)]
10278            fn from(variant: PwmEn0) -> Self {
10279                variant as u8 != 0
10280            }
10281        }
10282        #[doc = "Field `pwm_en_0` reader - PWM0 enable: 0=off; 1=on"]
10283        pub type PwmEn0R = crate::BitReader<PwmEn0>;
10284        impl PwmEn0R {
10285            #[doc = "Get enumerated values variant"]
10286            #[inline(always)]
10287            pub const fn variant(&self) -> PwmEn0 {
10288                match self.bits {
10289                    false => PwmEn0::Off,
10290                    true => PwmEn0::On,
10291                }
10292            }
10293            #[doc = "PWM disabled, output low"]
10294            #[inline(always)]
10295            pub fn is_off(&self) -> bool {
10296                *self == PwmEn0::Off
10297            }
10298            #[doc = "PWM enabled"]
10299            #[inline(always)]
10300            pub fn is_on(&self) -> bool {
10301                *self == PwmEn0::On
10302            }
10303        }
10304        #[doc = "Field `pwm_en_0` writer - PWM0 enable: 0=off; 1=on"]
10305        pub type PwmEn0W<'a, REG> = crate::BitWriter<'a, REG, PwmEn0>;
10306        impl<'a, REG> PwmEn0W<'a, REG>
10307        where
10308            REG: crate::Writable + crate::RegisterSpec,
10309        {
10310            #[doc = "PWM disabled, output low"]
10311            #[inline(always)]
10312            pub fn off(self) -> &'a mut crate::W<REG> {
10313                self.variant(PwmEn0::Off)
10314            }
10315            #[doc = "PWM enabled"]
10316            #[inline(always)]
10317            pub fn on(self) -> &'a mut crate::W<REG> {
10318                self.variant(PwmEn0::On)
10319            }
10320        }
10321        impl R {
10322            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
10323            #[inline(always)]
10324            pub fn pwm_en_0(&self) -> PwmEn0R {
10325                PwmEn0R::new((self.bits & 1) != 0)
10326            }
10327        }
10328        impl W {
10329            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
10330            #[inline(always)]
10331            pub fn pwm_en_0(&mut self) -> PwmEn0W<'_, PwmEn0Spec> {
10332                PwmEn0W::new(self, 0)
10333            }
10334        }
10335        #[doc = "PWM0 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10336        pub struct PwmEn0Spec;
10337        impl crate::RegisterSpec for PwmEn0Spec {
10338            type Ux = u32;
10339        }
10340        #[doc = "`read()` method returns [`pwm_en0::R`](R) reader structure"]
10341        impl crate::Readable for PwmEn0Spec {}
10342        #[doc = "`write(|w| ..)` method takes [`pwm_en0::W`](W) writer structure"]
10343        impl crate::Writable for PwmEn0Spec {
10344            type Safety = crate::Unsafe;
10345        }
10346        #[doc = "`reset()` method sets PWM_EN0 to value 0"]
10347        impl crate::Resettable for PwmEn0Spec {}
10348    }
10349    #[doc = "PWM_PORTITY0 (rw) register accessor: PWM0 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity0`] module"]
10350    #[doc(alias = "PWM_PORTITY0")]
10351    pub type PwmPortity0 = crate::Reg<pwm_portity0::PwmPortity0Spec>;
10352    #[doc = "PWM0 polarity"]
10353    pub mod pwm_portity0 {
10354        #[doc = "Register `PWM_PORTITY0` reader"]
10355        pub type R = crate::R<PwmPortity0Spec>;
10356        #[doc = "Register `PWM_PORTITY0` writer"]
10357        pub type W = crate::W<PwmPortity0Spec>;
10358        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
10359        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
10360        pub enum PwmPoarity0 {
10361            #[doc = "0: Normal polarity"]
10362            Normal = 0,
10363            #[doc = "1: Inverted polarity"]
10364            Inverted = 1,
10365        }
10366        impl From<PwmPoarity0> for bool {
10367            #[inline(always)]
10368            fn from(variant: PwmPoarity0) -> Self {
10369                variant as u8 != 0
10370            }
10371        }
10372        #[doc = "Field `pwm_poarity_0` reader - PWM0 polarity: 0=normal; 1=inverted"]
10373        pub type PwmPoarity0R = crate::BitReader<PwmPoarity0>;
10374        impl PwmPoarity0R {
10375            #[doc = "Get enumerated values variant"]
10376            #[inline(always)]
10377            pub const fn variant(&self) -> PwmPoarity0 {
10378                match self.bits {
10379                    false => PwmPoarity0::Normal,
10380                    true => PwmPoarity0::Inverted,
10381                }
10382            }
10383            #[doc = "Normal polarity"]
10384            #[inline(always)]
10385            pub fn is_normal(&self) -> bool {
10386                *self == PwmPoarity0::Normal
10387            }
10388            #[doc = "Inverted polarity"]
10389            #[inline(always)]
10390            pub fn is_inverted(&self) -> bool {
10391                *self == PwmPoarity0::Inverted
10392            }
10393        }
10394        #[doc = "Field `pwm_poarity_0` writer - PWM0 polarity: 0=normal; 1=inverted"]
10395        pub type PwmPoarity0W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity0>;
10396        impl<'a, REG> PwmPoarity0W<'a, REG>
10397        where
10398            REG: crate::Writable + crate::RegisterSpec,
10399        {
10400            #[doc = "Normal polarity"]
10401            #[inline(always)]
10402            pub fn normal(self) -> &'a mut crate::W<REG> {
10403                self.variant(PwmPoarity0::Normal)
10404            }
10405            #[doc = "Inverted polarity"]
10406            #[inline(always)]
10407            pub fn inverted(self) -> &'a mut crate::W<REG> {
10408                self.variant(PwmPoarity0::Inverted)
10409            }
10410        }
10411        impl R {
10412            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
10413            #[inline(always)]
10414            pub fn pwm_poarity_0(&self) -> PwmPoarity0R {
10415                PwmPoarity0R::new((self.bits & 1) != 0)
10416            }
10417        }
10418        impl W {
10419            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
10420            #[inline(always)]
10421            pub fn pwm_poarity_0(&mut self) -> PwmPoarity0W<'_, PwmPortity0Spec> {
10422                PwmPoarity0W::new(self, 0)
10423            }
10424        }
10425        #[doc = "PWM0 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10426        pub struct PwmPortity0Spec;
10427        impl crate::RegisterSpec for PwmPortity0Spec {
10428            type Ux = u32;
10429        }
10430        #[doc = "`read()` method returns [`pwm_portity0::R`](R) reader structure"]
10431        impl crate::Readable for PwmPortity0Spec {}
10432        #[doc = "`write(|w| ..)` method takes [`pwm_portity0::W`](W) writer structure"]
10433        impl crate::Writable for PwmPortity0Spec {
10434            type Safety = crate::Unsafe;
10435        }
10436        #[doc = "`reset()` method sets PWM_PORTITY0 to value 0"]
10437        impl crate::Resettable for PwmPortity0Spec {}
10438    }
10439    #[doc = "PWM_OEN_CFG0 (rw) register accessor: PWM0 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg0`] module"]
10440    #[doc(alias = "PWM_OEN_CFG0")]
10441    pub type PwmOenCfg0 = crate::Reg<pwm_oen_cfg0::PwmOenCfg0Spec>;
10442    #[doc = "PWM0 high-impedance config"]
10443    pub mod pwm_oen_cfg0 {
10444        #[doc = "Register `PWM_OEN_CFG0` reader"]
10445        pub type R = crate::R<PwmOenCfg0Spec>;
10446        #[doc = "Register `PWM_OEN_CFG0` writer"]
10447        pub type W = crate::W<PwmOenCfg0Spec>;
10448        #[doc = "Field `pwm_oen_cfg_0` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
10449        pub type PwmOenCfg0R = crate::BitReader;
10450        #[doc = "Field `pwm_oen_cfg_0` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
10451        pub type PwmOenCfg0W<'a, REG> = crate::BitWriter<'a, REG>;
10452        impl R {
10453            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
10454            #[inline(always)]
10455            pub fn pwm_oen_cfg_0(&self) -> PwmOenCfg0R {
10456                PwmOenCfg0R::new((self.bits & 1) != 0)
10457            }
10458        }
10459        impl W {
10460            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
10461            #[inline(always)]
10462            pub fn pwm_oen_cfg_0(&mut self) -> PwmOenCfg0W<'_, PwmOenCfg0Spec> {
10463                PwmOenCfg0W::new(self, 0)
10464            }
10465        }
10466        #[doc = "PWM0 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10467        pub struct PwmOenCfg0Spec;
10468        impl crate::RegisterSpec for PwmOenCfg0Spec {
10469            type Ux = u32;
10470        }
10471        #[doc = "`read()` method returns [`pwm_oen_cfg0::R`](R) reader structure"]
10472        impl crate::Readable for PwmOenCfg0Spec {}
10473        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg0::W`](W) writer structure"]
10474        impl crate::Writable for PwmOenCfg0Spec {
10475            type Safety = crate::Unsafe;
10476        }
10477        #[doc = "`reset()` method sets PWM_OEN_CFG0 to value 0"]
10478        impl crate::Resettable for PwmOenCfg0Spec {}
10479    }
10480    #[doc = "PWM_OFFSET_L0 (rw) register accessor: PWM0 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l0`] module"]
10481    #[doc(alias = "PWM_OFFSET_L0")]
10482    pub type PwmOffsetL0 = crate::Reg<pwm_offset_l0::PwmOffsetL0Spec>;
10483    #[doc = "PWM0 phase offset low 16 bits"]
10484    pub mod pwm_offset_l0 {
10485        #[doc = "Register `PWM_OFFSET_L0` reader"]
10486        pub type R = crate::R<PwmOffsetL0Spec>;
10487        #[doc = "Register `PWM_OFFSET_L0` writer"]
10488        pub type W = crate::W<PwmOffsetL0Spec>;
10489        #[doc = "Field `pwm_offset_l_0` reader - PWM0 phase offset low 16 bits"]
10490        pub type PwmOffsetL0R = crate::FieldReader<u16>;
10491        #[doc = "Field `pwm_offset_l_0` writer - PWM0 phase offset low 16 bits"]
10492        pub type PwmOffsetL0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10493        impl R {
10494            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
10495            #[inline(always)]
10496            pub fn pwm_offset_l_0(&self) -> PwmOffsetL0R {
10497                PwmOffsetL0R::new((self.bits & 0xffff) as u16)
10498            }
10499        }
10500        impl W {
10501            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
10502            #[inline(always)]
10503            pub fn pwm_offset_l_0(&mut self) -> PwmOffsetL0W<'_, PwmOffsetL0Spec> {
10504                PwmOffsetL0W::new(self, 0)
10505            }
10506        }
10507        #[doc = "PWM0 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10508        pub struct PwmOffsetL0Spec;
10509        impl crate::RegisterSpec for PwmOffsetL0Spec {
10510            type Ux = u32;
10511        }
10512        #[doc = "`read()` method returns [`pwm_offset_l0::R`](R) reader structure"]
10513        impl crate::Readable for PwmOffsetL0Spec {}
10514        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l0::W`](W) writer structure"]
10515        impl crate::Writable for PwmOffsetL0Spec {
10516            type Safety = crate::Unsafe;
10517        }
10518        #[doc = "`reset()` method sets PWM_OFFSET_L0 to value 0"]
10519        impl crate::Resettable for PwmOffsetL0Spec {}
10520    }
10521    #[doc = "PWM_OFFSET_H0 (rw) register accessor: PWM0 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h0`] module"]
10522    #[doc(alias = "PWM_OFFSET_H0")]
10523    pub type PwmOffsetH0 = crate::Reg<pwm_offset_h0::PwmOffsetH0Spec>;
10524    #[doc = "PWM0 phase offset high 16 bits"]
10525    pub mod pwm_offset_h0 {
10526        #[doc = "Register `PWM_OFFSET_H0` reader"]
10527        pub type R = crate::R<PwmOffsetH0Spec>;
10528        #[doc = "Register `PWM_OFFSET_H0` writer"]
10529        pub type W = crate::W<PwmOffsetH0Spec>;
10530        #[doc = "Field `pwm_offset_h_0` reader - PWM0 phase offset high 16 bits"]
10531        pub type PwmOffsetH0R = crate::FieldReader<u16>;
10532        #[doc = "Field `pwm_offset_h_0` writer - PWM0 phase offset high 16 bits"]
10533        pub type PwmOffsetH0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10534        impl R {
10535            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
10536            #[inline(always)]
10537            pub fn pwm_offset_h_0(&self) -> PwmOffsetH0R {
10538                PwmOffsetH0R::new((self.bits & 0xffff) as u16)
10539            }
10540        }
10541        impl W {
10542            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
10543            #[inline(always)]
10544            pub fn pwm_offset_h_0(&mut self) -> PwmOffsetH0W<'_, PwmOffsetH0Spec> {
10545                PwmOffsetH0W::new(self, 0)
10546            }
10547        }
10548        #[doc = "PWM0 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10549        pub struct PwmOffsetH0Spec;
10550        impl crate::RegisterSpec for PwmOffsetH0Spec {
10551            type Ux = u32;
10552        }
10553        #[doc = "`read()` method returns [`pwm_offset_h0::R`](R) reader structure"]
10554        impl crate::Readable for PwmOffsetH0Spec {}
10555        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h0::W`](W) writer structure"]
10556        impl crate::Writable for PwmOffsetH0Spec {
10557            type Safety = crate::Unsafe;
10558        }
10559        #[doc = "`reset()` method sets PWM_OFFSET_H0 to value 0"]
10560        impl crate::Resettable for PwmOffsetH0Spec {}
10561    }
10562    #[doc = "PWM_FREQ_L0 (rw) register accessor: PWM0 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l0`] module"]
10563    #[doc(alias = "PWM_FREQ_L0")]
10564    pub type PwmFreqL0 = crate::Reg<pwm_freq_l0::PwmFreqL0Spec>;
10565    #[doc = "PWM0 frequency low 16 bits"]
10566    pub mod pwm_freq_l0 {
10567        #[doc = "Register `PWM_FREQ_L0` reader"]
10568        pub type R = crate::R<PwmFreqL0Spec>;
10569        #[doc = "Register `PWM_FREQ_L0` writer"]
10570        pub type W = crate::W<PwmFreqL0Spec>;
10571        #[doc = "Field `pwm_freq_l_0` reader - PWM0 clock divider low 16 bits"]
10572        pub type PwmFreqL0R = crate::FieldReader<u16>;
10573        #[doc = "Field `pwm_freq_l_0` writer - PWM0 clock divider low 16 bits"]
10574        pub type PwmFreqL0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10575        impl R {
10576            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
10577            #[inline(always)]
10578            pub fn pwm_freq_l_0(&self) -> PwmFreqL0R {
10579                PwmFreqL0R::new((self.bits & 0xffff) as u16)
10580            }
10581        }
10582        impl W {
10583            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
10584            #[inline(always)]
10585            pub fn pwm_freq_l_0(&mut self) -> PwmFreqL0W<'_, PwmFreqL0Spec> {
10586                PwmFreqL0W::new(self, 0)
10587            }
10588        }
10589        #[doc = "PWM0 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10590        pub struct PwmFreqL0Spec;
10591        impl crate::RegisterSpec for PwmFreqL0Spec {
10592            type Ux = u32;
10593        }
10594        #[doc = "`read()` method returns [`pwm_freq_l0::R`](R) reader structure"]
10595        impl crate::Readable for PwmFreqL0Spec {}
10596        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l0::W`](W) writer structure"]
10597        impl crate::Writable for PwmFreqL0Spec {
10598            type Safety = crate::Unsafe;
10599        }
10600        #[doc = "`reset()` method sets PWM_FREQ_L0 to value 0"]
10601        impl crate::Resettable for PwmFreqL0Spec {}
10602    }
10603    #[doc = "PWM_FREQ_H0 (rw) register accessor: PWM0 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h0`] module"]
10604    #[doc(alias = "PWM_FREQ_H0")]
10605    pub type PwmFreqH0 = crate::Reg<pwm_freq_h0::PwmFreqH0Spec>;
10606    #[doc = "PWM0 frequency high 16 bits"]
10607    pub mod pwm_freq_h0 {
10608        #[doc = "Register `PWM_FREQ_H0` reader"]
10609        pub type R = crate::R<PwmFreqH0Spec>;
10610        #[doc = "Register `PWM_FREQ_H0` writer"]
10611        pub type W = crate::W<PwmFreqH0Spec>;
10612        #[doc = "Field `pwm_freq_h_0` reader - PWM0 clock divider high 16 bits"]
10613        pub type PwmFreqH0R = crate::FieldReader<u16>;
10614        #[doc = "Field `pwm_freq_h_0` writer - PWM0 clock divider high 16 bits"]
10615        pub type PwmFreqH0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10616        impl R {
10617            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
10618            #[inline(always)]
10619            pub fn pwm_freq_h_0(&self) -> PwmFreqH0R {
10620                PwmFreqH0R::new((self.bits & 0xffff) as u16)
10621            }
10622        }
10623        impl W {
10624            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
10625            #[inline(always)]
10626            pub fn pwm_freq_h_0(&mut self) -> PwmFreqH0W<'_, PwmFreqH0Spec> {
10627                PwmFreqH0W::new(self, 0)
10628            }
10629        }
10630        #[doc = "PWM0 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10631        pub struct PwmFreqH0Spec;
10632        impl crate::RegisterSpec for PwmFreqH0Spec {
10633            type Ux = u32;
10634        }
10635        #[doc = "`read()` method returns [`pwm_freq_h0::R`](R) reader structure"]
10636        impl crate::Readable for PwmFreqH0Spec {}
10637        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h0::W`](W) writer structure"]
10638        impl crate::Writable for PwmFreqH0Spec {
10639            type Safety = crate::Unsafe;
10640        }
10641        #[doc = "`reset()` method sets PWM_FREQ_H0 to value 0"]
10642        impl crate::Resettable for PwmFreqH0Spec {}
10643    }
10644    #[doc = "PWM_DUTY_L0 (rw) register accessor: PWM0 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l0`] module"]
10645    #[doc(alias = "PWM_DUTY_L0")]
10646    pub type PwmDutyL0 = crate::Reg<pwm_duty_l0::PwmDutyL0Spec>;
10647    #[doc = "PWM0 duty cycle low 16 bits"]
10648    pub mod pwm_duty_l0 {
10649        #[doc = "Register `PWM_DUTY_L0` reader"]
10650        pub type R = crate::R<PwmDutyL0Spec>;
10651        #[doc = "Register `PWM_DUTY_L0` writer"]
10652        pub type W = crate::W<PwmDutyL0Spec>;
10653        #[doc = "Field `pwm_duty_l_0` reader - PWM0 duty cycle low 16 bits"]
10654        pub type PwmDutyL0R = crate::FieldReader<u16>;
10655        #[doc = "Field `pwm_duty_l_0` writer - PWM0 duty cycle low 16 bits"]
10656        pub type PwmDutyL0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10657        impl R {
10658            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
10659            #[inline(always)]
10660            pub fn pwm_duty_l_0(&self) -> PwmDutyL0R {
10661                PwmDutyL0R::new((self.bits & 0xffff) as u16)
10662            }
10663        }
10664        impl W {
10665            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
10666            #[inline(always)]
10667            pub fn pwm_duty_l_0(&mut self) -> PwmDutyL0W<'_, PwmDutyL0Spec> {
10668                PwmDutyL0W::new(self, 0)
10669            }
10670        }
10671        #[doc = "PWM0 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10672        pub struct PwmDutyL0Spec;
10673        impl crate::RegisterSpec for PwmDutyL0Spec {
10674            type Ux = u32;
10675        }
10676        #[doc = "`read()` method returns [`pwm_duty_l0::R`](R) reader structure"]
10677        impl crate::Readable for PwmDutyL0Spec {}
10678        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l0::W`](W) writer structure"]
10679        impl crate::Writable for PwmDutyL0Spec {
10680            type Safety = crate::Unsafe;
10681        }
10682        #[doc = "`reset()` method sets PWM_DUTY_L0 to value 0"]
10683        impl crate::Resettable for PwmDutyL0Spec {}
10684    }
10685    #[doc = "PWM_DUTY_H0 (rw) register accessor: PWM0 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h0`] module"]
10686    #[doc(alias = "PWM_DUTY_H0")]
10687    pub type PwmDutyH0 = crate::Reg<pwm_duty_h0::PwmDutyH0Spec>;
10688    #[doc = "PWM0 duty cycle high 16 bits"]
10689    pub mod pwm_duty_h0 {
10690        #[doc = "Register `PWM_DUTY_H0` reader"]
10691        pub type R = crate::R<PwmDutyH0Spec>;
10692        #[doc = "Register `PWM_DUTY_H0` writer"]
10693        pub type W = crate::W<PwmDutyH0Spec>;
10694        #[doc = "Field `pwm_duty_h_0` reader - PWM0 duty cycle high 16 bits"]
10695        pub type PwmDutyH0R = crate::FieldReader<u16>;
10696        #[doc = "Field `pwm_duty_h_0` writer - PWM0 duty cycle high 16 bits"]
10697        pub type PwmDutyH0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10698        impl R {
10699            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
10700            #[inline(always)]
10701            pub fn pwm_duty_h_0(&self) -> PwmDutyH0R {
10702                PwmDutyH0R::new((self.bits & 0xffff) as u16)
10703            }
10704        }
10705        impl W {
10706            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
10707            #[inline(always)]
10708            pub fn pwm_duty_h_0(&mut self) -> PwmDutyH0W<'_, PwmDutyH0Spec> {
10709                PwmDutyH0W::new(self, 0)
10710            }
10711        }
10712        #[doc = "PWM0 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10713        pub struct PwmDutyH0Spec;
10714        impl crate::RegisterSpec for PwmDutyH0Spec {
10715            type Ux = u32;
10716        }
10717        #[doc = "`read()` method returns [`pwm_duty_h0::R`](R) reader structure"]
10718        impl crate::Readable for PwmDutyH0Spec {}
10719        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h0::W`](W) writer structure"]
10720        impl crate::Writable for PwmDutyH0Spec {
10721            type Safety = crate::Unsafe;
10722        }
10723        #[doc = "`reset()` method sets PWM_DUTY_H0 to value 0"]
10724        impl crate::Resettable for PwmDutyH0Spec {}
10725    }
10726    #[doc = "PWM_PERIODLOAD_FLAG0 (rw) register accessor: PWM0 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag0`] module"]
10727    #[doc(alias = "PWM_PERIODLOAD_FLAG0")]
10728    pub type PwmPeriodloadFlag0 = crate::Reg<pwm_periodload_flag0::PwmPeriodloadFlag0Spec>;
10729    #[doc = "PWM0 period load flag"]
10730    pub mod pwm_periodload_flag0 {
10731        #[doc = "Register `PWM_PERIODLOAD_FLAG0` reader"]
10732        pub type R = crate::R<PwmPeriodloadFlag0Spec>;
10733        #[doc = "Register `PWM_PERIODLOAD_FLAG0` writer"]
10734        pub type W = crate::W<PwmPeriodloadFlag0Spec>;
10735        #[doc = "Field `pwm_periodload_flag_0` reader - Period load complete flag"]
10736        pub type PwmPeriodloadFlag0R = crate::BitReader;
10737        impl R {
10738            #[doc = "Bit 0 - Period load complete flag"]
10739            #[inline(always)]
10740            pub fn pwm_periodload_flag_0(&self) -> PwmPeriodloadFlag0R {
10741                PwmPeriodloadFlag0R::new((self.bits & 1) != 0)
10742            }
10743        }
10744        impl W {}
10745        #[doc = "PWM0 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10746        pub struct PwmPeriodloadFlag0Spec;
10747        impl crate::RegisterSpec for PwmPeriodloadFlag0Spec {
10748            type Ux = u32;
10749        }
10750        #[doc = "`read()` method returns [`pwm_periodload_flag0::R`](R) reader structure"]
10751        impl crate::Readable for PwmPeriodloadFlag0Spec {}
10752        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag0::W`](W) writer structure"]
10753        impl crate::Writable for PwmPeriodloadFlag0Spec {
10754            type Safety = crate::Unsafe;
10755        }
10756        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG0 to value 0"]
10757        impl crate::Resettable for PwmPeriodloadFlag0Spec {}
10758    }
10759    #[doc = "PWM_PERIOD_VAL0 (rw) register accessor: PWM0 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val0`] module"]
10760    #[doc(alias = "PWM_PERIOD_VAL0")]
10761    pub type PwmPeriodVal0 = crate::Reg<pwm_period_val0::PwmPeriodVal0Spec>;
10762    #[doc = "PWM0 pulse count value"]
10763    pub mod pwm_period_val0 {
10764        #[doc = "Register `PWM_PERIOD_VAL0` reader"]
10765        pub type R = crate::R<PwmPeriodVal0Spec>;
10766        #[doc = "Register `PWM_PERIOD_VAL0` writer"]
10767        pub type W = crate::W<PwmPeriodVal0Spec>;
10768        #[doc = "Field `pwm_period_val_0` reader - Pulse count for stepping mode"]
10769        pub type PwmPeriodVal0R = crate::FieldReader<u16>;
10770        #[doc = "Field `pwm_period_val_0` writer - Pulse count for stepping mode"]
10771        pub type PwmPeriodVal0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10772        impl R {
10773            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
10774            #[inline(always)]
10775            pub fn pwm_period_val_0(&self) -> PwmPeriodVal0R {
10776                PwmPeriodVal0R::new((self.bits & 0xffff) as u16)
10777            }
10778        }
10779        impl W {
10780            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
10781            #[inline(always)]
10782            pub fn pwm_period_val_0(&mut self) -> PwmPeriodVal0W<'_, PwmPeriodVal0Spec> {
10783                PwmPeriodVal0W::new(self, 0)
10784            }
10785        }
10786        #[doc = "PWM0 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10787        pub struct PwmPeriodVal0Spec;
10788        impl crate::RegisterSpec for PwmPeriodVal0Spec {
10789            type Ux = u32;
10790        }
10791        #[doc = "`read()` method returns [`pwm_period_val0::R`](R) reader structure"]
10792        impl crate::Readable for PwmPeriodVal0Spec {}
10793        #[doc = "`write(|w| ..)` method takes [`pwm_period_val0::W`](W) writer structure"]
10794        impl crate::Writable for PwmPeriodVal0Spec {
10795            type Safety = crate::Unsafe;
10796        }
10797        #[doc = "`reset()` method sets PWM_PERIOD_VAL0 to value 0"]
10798        impl crate::Resettable for PwmPeriodVal0Spec {}
10799    }
10800    #[doc = "PWM_PERIODCNT0 (rw) register accessor: PWM0 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt0`] module"]
10801    #[doc(alias = "PWM_PERIODCNT0")]
10802    pub type PwmPeriodcnt0 = crate::Reg<pwm_periodcnt0::PwmPeriodcnt0Spec>;
10803    #[doc = "PWM0 pulse count current value"]
10804    pub mod pwm_periodcnt0 {
10805        #[doc = "Register `PWM_PERIODCNT0` reader"]
10806        pub type R = crate::R<PwmPeriodcnt0Spec>;
10807        #[doc = "Register `PWM_PERIODCNT0` writer"]
10808        pub type W = crate::W<PwmPeriodcnt0Spec>;
10809        #[doc = "Field `pwm_periodcnt_0` reader - Current pulse count"]
10810        pub type PwmPeriodcnt0R = crate::FieldReader<u16>;
10811        impl R {
10812            #[doc = "Bits 0:15 - Current pulse count"]
10813            #[inline(always)]
10814            pub fn pwm_periodcnt_0(&self) -> PwmPeriodcnt0R {
10815                PwmPeriodcnt0R::new((self.bits & 0xffff) as u16)
10816            }
10817        }
10818        impl W {}
10819        #[doc = "PWM0 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10820        pub struct PwmPeriodcnt0Spec;
10821        impl crate::RegisterSpec for PwmPeriodcnt0Spec {
10822            type Ux = u32;
10823        }
10824        #[doc = "`read()` method returns [`pwm_periodcnt0::R`](R) reader structure"]
10825        impl crate::Readable for PwmPeriodcnt0Spec {}
10826        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt0::W`](W) writer structure"]
10827        impl crate::Writable for PwmPeriodcnt0Spec {
10828            type Safety = crate::Unsafe;
10829        }
10830        #[doc = "`reset()` method sets PWM_PERIODCNT0 to value 0"]
10831        impl crate::Resettable for PwmPeriodcnt0Spec {}
10832    }
10833    #[doc = "PWM_EN1 (rw) register accessor: PWM1 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en1`] module"]
10834    #[doc(alias = "PWM_EN1")]
10835    pub type PwmEn1 = crate::Reg<pwm_en1::PwmEn1Spec>;
10836    #[doc = "PWM1 enable"]
10837    pub mod pwm_en1 {
10838        #[doc = "Register `PWM_EN1` reader"]
10839        pub type R = crate::R<PwmEn1Spec>;
10840        #[doc = "Register `PWM_EN1` writer"]
10841        pub type W = crate::W<PwmEn1Spec>;
10842        #[doc = "Field `pwm_en_1` reader - PWM1 enable"]
10843        pub type PwmEn1R = crate::BitReader;
10844        #[doc = "Field `pwm_en_1` writer - PWM1 enable"]
10845        pub type PwmEn1W<'a, REG> = crate::BitWriter<'a, REG>;
10846        impl R {
10847            #[doc = "Bit 0 - PWM1 enable"]
10848            #[inline(always)]
10849            pub fn pwm_en_1(&self) -> PwmEn1R {
10850                PwmEn1R::new((self.bits & 1) != 0)
10851            }
10852        }
10853        impl W {
10854            #[doc = "Bit 0 - PWM1 enable"]
10855            #[inline(always)]
10856            pub fn pwm_en_1(&mut self) -> PwmEn1W<'_, PwmEn1Spec> {
10857                PwmEn1W::new(self, 0)
10858            }
10859        }
10860        #[doc = "PWM1 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10861        pub struct PwmEn1Spec;
10862        impl crate::RegisterSpec for PwmEn1Spec {
10863            type Ux = u32;
10864        }
10865        #[doc = "`read()` method returns [`pwm_en1::R`](R) reader structure"]
10866        impl crate::Readable for PwmEn1Spec {}
10867        #[doc = "`write(|w| ..)` method takes [`pwm_en1::W`](W) writer structure"]
10868        impl crate::Writable for PwmEn1Spec {
10869            type Safety = crate::Unsafe;
10870        }
10871        #[doc = "`reset()` method sets PWM_EN1 to value 0"]
10872        impl crate::Resettable for PwmEn1Spec {}
10873    }
10874    #[doc = "PWM_PORTITY1 (rw) register accessor: PWM1 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity1`] module"]
10875    #[doc(alias = "PWM_PORTITY1")]
10876    pub type PwmPortity1 = crate::Reg<pwm_portity1::PwmPortity1Spec>;
10877    #[doc = "PWM1 polarity"]
10878    pub mod pwm_portity1 {
10879        #[doc = "Register `PWM_PORTITY1` reader"]
10880        pub type R = crate::R<PwmPortity1Spec>;
10881        #[doc = "Register `PWM_PORTITY1` writer"]
10882        pub type W = crate::W<PwmPortity1Spec>;
10883        #[doc = "Field `pwm_poarity_1` reader - PWM1 polarity"]
10884        pub type PwmPoarity1R = crate::BitReader;
10885        #[doc = "Field `pwm_poarity_1` writer - PWM1 polarity"]
10886        pub type PwmPoarity1W<'a, REG> = crate::BitWriter<'a, REG>;
10887        impl R {
10888            #[doc = "Bit 0 - PWM1 polarity"]
10889            #[inline(always)]
10890            pub fn pwm_poarity_1(&self) -> PwmPoarity1R {
10891                PwmPoarity1R::new((self.bits & 1) != 0)
10892            }
10893        }
10894        impl W {
10895            #[doc = "Bit 0 - PWM1 polarity"]
10896            #[inline(always)]
10897            pub fn pwm_poarity_1(&mut self) -> PwmPoarity1W<'_, PwmPortity1Spec> {
10898                PwmPoarity1W::new(self, 0)
10899            }
10900        }
10901        #[doc = "PWM1 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10902        pub struct PwmPortity1Spec;
10903        impl crate::RegisterSpec for PwmPortity1Spec {
10904            type Ux = u32;
10905        }
10906        #[doc = "`read()` method returns [`pwm_portity1::R`](R) reader structure"]
10907        impl crate::Readable for PwmPortity1Spec {}
10908        #[doc = "`write(|w| ..)` method takes [`pwm_portity1::W`](W) writer structure"]
10909        impl crate::Writable for PwmPortity1Spec {
10910            type Safety = crate::Unsafe;
10911        }
10912        #[doc = "`reset()` method sets PWM_PORTITY1 to value 0"]
10913        impl crate::Resettable for PwmPortity1Spec {}
10914    }
10915    #[doc = "PWM_OEN_CFG1 (rw) register accessor: PWM1 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg1`] module"]
10916    #[doc(alias = "PWM_OEN_CFG1")]
10917    pub type PwmOenCfg1 = crate::Reg<pwm_oen_cfg1::PwmOenCfg1Spec>;
10918    #[doc = "PWM1 high-impedance config"]
10919    pub mod pwm_oen_cfg1 {
10920        #[doc = "Register `PWM_OEN_CFG1` reader"]
10921        pub type R = crate::R<PwmOenCfg1Spec>;
10922        #[doc = "Register `PWM_OEN_CFG1` writer"]
10923        pub type W = crate::W<PwmOenCfg1Spec>;
10924        #[doc = "Field `pwm_oen_cfg_1` reader - PWM1 high-Z enable"]
10925        pub type PwmOenCfg1R = crate::BitReader;
10926        #[doc = "Field `pwm_oen_cfg_1` writer - PWM1 high-Z enable"]
10927        pub type PwmOenCfg1W<'a, REG> = crate::BitWriter<'a, REG>;
10928        impl R {
10929            #[doc = "Bit 0 - PWM1 high-Z enable"]
10930            #[inline(always)]
10931            pub fn pwm_oen_cfg_1(&self) -> PwmOenCfg1R {
10932                PwmOenCfg1R::new((self.bits & 1) != 0)
10933            }
10934        }
10935        impl W {
10936            #[doc = "Bit 0 - PWM1 high-Z enable"]
10937            #[inline(always)]
10938            pub fn pwm_oen_cfg_1(&mut self) -> PwmOenCfg1W<'_, PwmOenCfg1Spec> {
10939                PwmOenCfg1W::new(self, 0)
10940            }
10941        }
10942        #[doc = "PWM1 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10943        pub struct PwmOenCfg1Spec;
10944        impl crate::RegisterSpec for PwmOenCfg1Spec {
10945            type Ux = u32;
10946        }
10947        #[doc = "`read()` method returns [`pwm_oen_cfg1::R`](R) reader structure"]
10948        impl crate::Readable for PwmOenCfg1Spec {}
10949        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg1::W`](W) writer structure"]
10950        impl crate::Writable for PwmOenCfg1Spec {
10951            type Safety = crate::Unsafe;
10952        }
10953        #[doc = "`reset()` method sets PWM_OEN_CFG1 to value 0"]
10954        impl crate::Resettable for PwmOenCfg1Spec {}
10955    }
10956    #[doc = "PWM_OFFSET_L1 (rw) register accessor: PWM1 phase offset low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l1`] module"]
10957    #[doc(alias = "PWM_OFFSET_L1")]
10958    pub type PwmOffsetL1 = crate::Reg<pwm_offset_l1::PwmOffsetL1Spec>;
10959    #[doc = "PWM1 phase offset low"]
10960    pub mod pwm_offset_l1 {
10961        #[doc = "Register `PWM_OFFSET_L1` reader"]
10962        pub type R = crate::R<PwmOffsetL1Spec>;
10963        #[doc = "Register `PWM_OFFSET_L1` writer"]
10964        pub type W = crate::W<PwmOffsetL1Spec>;
10965        #[doc = "Field `pwm_offset_l_1` reader - PWM1 phase offset low 16 bits"]
10966        pub type PwmOffsetL1R = crate::FieldReader<u16>;
10967        #[doc = "Field `pwm_offset_l_1` writer - PWM1 phase offset low 16 bits"]
10968        pub type PwmOffsetL1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10969        impl R {
10970            #[doc = "Bits 0:15 - PWM1 phase offset low 16 bits"]
10971            #[inline(always)]
10972            pub fn pwm_offset_l_1(&self) -> PwmOffsetL1R {
10973                PwmOffsetL1R::new((self.bits & 0xffff) as u16)
10974            }
10975        }
10976        impl W {
10977            #[doc = "Bits 0:15 - PWM1 phase offset low 16 bits"]
10978            #[inline(always)]
10979            pub fn pwm_offset_l_1(&mut self) -> PwmOffsetL1W<'_, PwmOffsetL1Spec> {
10980                PwmOffsetL1W::new(self, 0)
10981            }
10982        }
10983        #[doc = "PWM1 phase offset low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10984        pub struct PwmOffsetL1Spec;
10985        impl crate::RegisterSpec for PwmOffsetL1Spec {
10986            type Ux = u32;
10987        }
10988        #[doc = "`read()` method returns [`pwm_offset_l1::R`](R) reader structure"]
10989        impl crate::Readable for PwmOffsetL1Spec {}
10990        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l1::W`](W) writer structure"]
10991        impl crate::Writable for PwmOffsetL1Spec {
10992            type Safety = crate::Unsafe;
10993        }
10994        #[doc = "`reset()` method sets PWM_OFFSET_L1 to value 0"]
10995        impl crate::Resettable for PwmOffsetL1Spec {}
10996    }
10997    #[doc = "PWM_OFFSET_H1 (rw) register accessor: PWM1 phase offset high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h1`] module"]
10998    #[doc(alias = "PWM_OFFSET_H1")]
10999    pub type PwmOffsetH1 = crate::Reg<pwm_offset_h1::PwmOffsetH1Spec>;
11000    #[doc = "PWM1 phase offset high"]
11001    pub mod pwm_offset_h1 {
11002        #[doc = "Register `PWM_OFFSET_H1` reader"]
11003        pub type R = crate::R<PwmOffsetH1Spec>;
11004        #[doc = "Register `PWM_OFFSET_H1` writer"]
11005        pub type W = crate::W<PwmOffsetH1Spec>;
11006        #[doc = "Field `pwm_offset_h_1` reader - PWM1 phase offset high 16 bits"]
11007        pub type PwmOffsetH1R = crate::FieldReader<u16>;
11008        #[doc = "Field `pwm_offset_h_1` writer - PWM1 phase offset high 16 bits"]
11009        pub type PwmOffsetH1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11010        impl R {
11011            #[doc = "Bits 0:15 - PWM1 phase offset high 16 bits"]
11012            #[inline(always)]
11013            pub fn pwm_offset_h_1(&self) -> PwmOffsetH1R {
11014                PwmOffsetH1R::new((self.bits & 0xffff) as u16)
11015            }
11016        }
11017        impl W {
11018            #[doc = "Bits 0:15 - PWM1 phase offset high 16 bits"]
11019            #[inline(always)]
11020            pub fn pwm_offset_h_1(&mut self) -> PwmOffsetH1W<'_, PwmOffsetH1Spec> {
11021                PwmOffsetH1W::new(self, 0)
11022            }
11023        }
11024        #[doc = "PWM1 phase offset high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11025        pub struct PwmOffsetH1Spec;
11026        impl crate::RegisterSpec for PwmOffsetH1Spec {
11027            type Ux = u32;
11028        }
11029        #[doc = "`read()` method returns [`pwm_offset_h1::R`](R) reader structure"]
11030        impl crate::Readable for PwmOffsetH1Spec {}
11031        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h1::W`](W) writer structure"]
11032        impl crate::Writable for PwmOffsetH1Spec {
11033            type Safety = crate::Unsafe;
11034        }
11035        #[doc = "`reset()` method sets PWM_OFFSET_H1 to value 0"]
11036        impl crate::Resettable for PwmOffsetH1Spec {}
11037    }
11038    #[doc = "PWM_FREQ_L1 (rw) register accessor: PWM1 frequency low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l1`] module"]
11039    #[doc(alias = "PWM_FREQ_L1")]
11040    pub type PwmFreqL1 = crate::Reg<pwm_freq_l1::PwmFreqL1Spec>;
11041    #[doc = "PWM1 frequency low"]
11042    pub mod pwm_freq_l1 {
11043        #[doc = "Register `PWM_FREQ_L1` reader"]
11044        pub type R = crate::R<PwmFreqL1Spec>;
11045        #[doc = "Register `PWM_FREQ_L1` writer"]
11046        pub type W = crate::W<PwmFreqL1Spec>;
11047        #[doc = "Field `pwm_freq_l_1` reader - PWM1 clock divider low 16 bits"]
11048        pub type PwmFreqL1R = crate::FieldReader<u16>;
11049        #[doc = "Field `pwm_freq_l_1` writer - PWM1 clock divider low 16 bits"]
11050        pub type PwmFreqL1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11051        impl R {
11052            #[doc = "Bits 0:15 - PWM1 clock divider low 16 bits"]
11053            #[inline(always)]
11054            pub fn pwm_freq_l_1(&self) -> PwmFreqL1R {
11055                PwmFreqL1R::new((self.bits & 0xffff) as u16)
11056            }
11057        }
11058        impl W {
11059            #[doc = "Bits 0:15 - PWM1 clock divider low 16 bits"]
11060            #[inline(always)]
11061            pub fn pwm_freq_l_1(&mut self) -> PwmFreqL1W<'_, PwmFreqL1Spec> {
11062                PwmFreqL1W::new(self, 0)
11063            }
11064        }
11065        #[doc = "PWM1 frequency low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11066        pub struct PwmFreqL1Spec;
11067        impl crate::RegisterSpec for PwmFreqL1Spec {
11068            type Ux = u32;
11069        }
11070        #[doc = "`read()` method returns [`pwm_freq_l1::R`](R) reader structure"]
11071        impl crate::Readable for PwmFreqL1Spec {}
11072        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l1::W`](W) writer structure"]
11073        impl crate::Writable for PwmFreqL1Spec {
11074            type Safety = crate::Unsafe;
11075        }
11076        #[doc = "`reset()` method sets PWM_FREQ_L1 to value 0"]
11077        impl crate::Resettable for PwmFreqL1Spec {}
11078    }
11079    #[doc = "PWM_FREQ_H1 (rw) register accessor: PWM1 frequency high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h1`] module"]
11080    #[doc(alias = "PWM_FREQ_H1")]
11081    pub type PwmFreqH1 = crate::Reg<pwm_freq_h1::PwmFreqH1Spec>;
11082    #[doc = "PWM1 frequency high"]
11083    pub mod pwm_freq_h1 {
11084        #[doc = "Register `PWM_FREQ_H1` reader"]
11085        pub type R = crate::R<PwmFreqH1Spec>;
11086        #[doc = "Register `PWM_FREQ_H1` writer"]
11087        pub type W = crate::W<PwmFreqH1Spec>;
11088        #[doc = "Field `pwm_freq_h_1` reader - PWM1 clock divider high 16 bits"]
11089        pub type PwmFreqH1R = crate::FieldReader<u16>;
11090        #[doc = "Field `pwm_freq_h_1` writer - PWM1 clock divider high 16 bits"]
11091        pub type PwmFreqH1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11092        impl R {
11093            #[doc = "Bits 0:15 - PWM1 clock divider high 16 bits"]
11094            #[inline(always)]
11095            pub fn pwm_freq_h_1(&self) -> PwmFreqH1R {
11096                PwmFreqH1R::new((self.bits & 0xffff) as u16)
11097            }
11098        }
11099        impl W {
11100            #[doc = "Bits 0:15 - PWM1 clock divider high 16 bits"]
11101            #[inline(always)]
11102            pub fn pwm_freq_h_1(&mut self) -> PwmFreqH1W<'_, PwmFreqH1Spec> {
11103                PwmFreqH1W::new(self, 0)
11104            }
11105        }
11106        #[doc = "PWM1 frequency high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11107        pub struct PwmFreqH1Spec;
11108        impl crate::RegisterSpec for PwmFreqH1Spec {
11109            type Ux = u32;
11110        }
11111        #[doc = "`read()` method returns [`pwm_freq_h1::R`](R) reader structure"]
11112        impl crate::Readable for PwmFreqH1Spec {}
11113        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h1::W`](W) writer structure"]
11114        impl crate::Writable for PwmFreqH1Spec {
11115            type Safety = crate::Unsafe;
11116        }
11117        #[doc = "`reset()` method sets PWM_FREQ_H1 to value 0"]
11118        impl crate::Resettable for PwmFreqH1Spec {}
11119    }
11120    #[doc = "PWM_DUTY_L1 (rw) register accessor: PWM1 duty cycle low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l1`] module"]
11121    #[doc(alias = "PWM_DUTY_L1")]
11122    pub type PwmDutyL1 = crate::Reg<pwm_duty_l1::PwmDutyL1Spec>;
11123    #[doc = "PWM1 duty cycle low"]
11124    pub mod pwm_duty_l1 {
11125        #[doc = "Register `PWM_DUTY_L1` reader"]
11126        pub type R = crate::R<PwmDutyL1Spec>;
11127        #[doc = "Register `PWM_DUTY_L1` writer"]
11128        pub type W = crate::W<PwmDutyL1Spec>;
11129        #[doc = "Field `pwm_duty_l_1` reader - PWM1 duty low 16 bits"]
11130        pub type PwmDutyL1R = crate::FieldReader<u16>;
11131        #[doc = "Field `pwm_duty_l_1` writer - PWM1 duty low 16 bits"]
11132        pub type PwmDutyL1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11133        impl R {
11134            #[doc = "Bits 0:15 - PWM1 duty low 16 bits"]
11135            #[inline(always)]
11136            pub fn pwm_duty_l_1(&self) -> PwmDutyL1R {
11137                PwmDutyL1R::new((self.bits & 0xffff) as u16)
11138            }
11139        }
11140        impl W {
11141            #[doc = "Bits 0:15 - PWM1 duty low 16 bits"]
11142            #[inline(always)]
11143            pub fn pwm_duty_l_1(&mut self) -> PwmDutyL1W<'_, PwmDutyL1Spec> {
11144                PwmDutyL1W::new(self, 0)
11145            }
11146        }
11147        #[doc = "PWM1 duty cycle low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11148        pub struct PwmDutyL1Spec;
11149        impl crate::RegisterSpec for PwmDutyL1Spec {
11150            type Ux = u32;
11151        }
11152        #[doc = "`read()` method returns [`pwm_duty_l1::R`](R) reader structure"]
11153        impl crate::Readable for PwmDutyL1Spec {}
11154        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l1::W`](W) writer structure"]
11155        impl crate::Writable for PwmDutyL1Spec {
11156            type Safety = crate::Unsafe;
11157        }
11158        #[doc = "`reset()` method sets PWM_DUTY_L1 to value 0"]
11159        impl crate::Resettable for PwmDutyL1Spec {}
11160    }
11161    #[doc = "PWM_DUTY_H1 (rw) register accessor: PWM1 duty cycle high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h1`] module"]
11162    #[doc(alias = "PWM_DUTY_H1")]
11163    pub type PwmDutyH1 = crate::Reg<pwm_duty_h1::PwmDutyH1Spec>;
11164    #[doc = "PWM1 duty cycle high"]
11165    pub mod pwm_duty_h1 {
11166        #[doc = "Register `PWM_DUTY_H1` reader"]
11167        pub type R = crate::R<PwmDutyH1Spec>;
11168        #[doc = "Register `PWM_DUTY_H1` writer"]
11169        pub type W = crate::W<PwmDutyH1Spec>;
11170        #[doc = "Field `pwm_duty_h_1` reader - PWM1 duty high 16 bits"]
11171        pub type PwmDutyH1R = crate::FieldReader<u16>;
11172        #[doc = "Field `pwm_duty_h_1` writer - PWM1 duty high 16 bits"]
11173        pub type PwmDutyH1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11174        impl R {
11175            #[doc = "Bits 0:15 - PWM1 duty high 16 bits"]
11176            #[inline(always)]
11177            pub fn pwm_duty_h_1(&self) -> PwmDutyH1R {
11178                PwmDutyH1R::new((self.bits & 0xffff) as u16)
11179            }
11180        }
11181        impl W {
11182            #[doc = "Bits 0:15 - PWM1 duty high 16 bits"]
11183            #[inline(always)]
11184            pub fn pwm_duty_h_1(&mut self) -> PwmDutyH1W<'_, PwmDutyH1Spec> {
11185                PwmDutyH1W::new(self, 0)
11186            }
11187        }
11188        #[doc = "PWM1 duty cycle high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11189        pub struct PwmDutyH1Spec;
11190        impl crate::RegisterSpec for PwmDutyH1Spec {
11191            type Ux = u32;
11192        }
11193        #[doc = "`read()` method returns [`pwm_duty_h1::R`](R) reader structure"]
11194        impl crate::Readable for PwmDutyH1Spec {}
11195        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h1::W`](W) writer structure"]
11196        impl crate::Writable for PwmDutyH1Spec {
11197            type Safety = crate::Unsafe;
11198        }
11199        #[doc = "`reset()` method sets PWM_DUTY_H1 to value 0"]
11200        impl crate::Resettable for PwmDutyH1Spec {}
11201    }
11202    #[doc = "PWM_PERIODLOAD_FLAG1 (rw) register accessor: PWM1 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag1`] module"]
11203    #[doc(alias = "PWM_PERIODLOAD_FLAG1")]
11204    pub type PwmPeriodloadFlag1 = crate::Reg<pwm_periodload_flag1::PwmPeriodloadFlag1Spec>;
11205    #[doc = "PWM1 period load flag"]
11206    pub mod pwm_periodload_flag1 {
11207        #[doc = "Register `PWM_PERIODLOAD_FLAG1` reader"]
11208        pub type R = crate::R<PwmPeriodloadFlag1Spec>;
11209        #[doc = "Register `PWM_PERIODLOAD_FLAG1` writer"]
11210        pub type W = crate::W<PwmPeriodloadFlag1Spec>;
11211        #[doc = "Field `pwm_periodload_flag_1` reader - Period load flag"]
11212        pub type PwmPeriodloadFlag1R = crate::BitReader;
11213        impl R {
11214            #[doc = "Bit 0 - Period load flag"]
11215            #[inline(always)]
11216            pub fn pwm_periodload_flag_1(&self) -> PwmPeriodloadFlag1R {
11217                PwmPeriodloadFlag1R::new((self.bits & 1) != 0)
11218            }
11219        }
11220        impl W {}
11221        #[doc = "PWM1 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11222        pub struct PwmPeriodloadFlag1Spec;
11223        impl crate::RegisterSpec for PwmPeriodloadFlag1Spec {
11224            type Ux = u32;
11225        }
11226        #[doc = "`read()` method returns [`pwm_periodload_flag1::R`](R) reader structure"]
11227        impl crate::Readable for PwmPeriodloadFlag1Spec {}
11228        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag1::W`](W) writer structure"]
11229        impl crate::Writable for PwmPeriodloadFlag1Spec {
11230            type Safety = crate::Unsafe;
11231        }
11232        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG1 to value 0"]
11233        impl crate::Resettable for PwmPeriodloadFlag1Spec {}
11234    }
11235    #[doc = "PWM_PERIOD_VAL1 (rw) register accessor: PWM1 pulse count\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val1`] module"]
11236    #[doc(alias = "PWM_PERIOD_VAL1")]
11237    pub type PwmPeriodVal1 = crate::Reg<pwm_period_val1::PwmPeriodVal1Spec>;
11238    #[doc = "PWM1 pulse count"]
11239    pub mod pwm_period_val1 {
11240        #[doc = "Register `PWM_PERIOD_VAL1` reader"]
11241        pub type R = crate::R<PwmPeriodVal1Spec>;
11242        #[doc = "Register `PWM_PERIOD_VAL1` writer"]
11243        pub type W = crate::W<PwmPeriodVal1Spec>;
11244        #[doc = "Field `pwm_period_val_1` reader - Pulse count"]
11245        pub type PwmPeriodVal1R = crate::FieldReader<u16>;
11246        #[doc = "Field `pwm_period_val_1` writer - Pulse count"]
11247        pub type PwmPeriodVal1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11248        impl R {
11249            #[doc = "Bits 0:15 - Pulse count"]
11250            #[inline(always)]
11251            pub fn pwm_period_val_1(&self) -> PwmPeriodVal1R {
11252                PwmPeriodVal1R::new((self.bits & 0xffff) as u16)
11253            }
11254        }
11255        impl W {
11256            #[doc = "Bits 0:15 - Pulse count"]
11257            #[inline(always)]
11258            pub fn pwm_period_val_1(&mut self) -> PwmPeriodVal1W<'_, PwmPeriodVal1Spec> {
11259                PwmPeriodVal1W::new(self, 0)
11260            }
11261        }
11262        #[doc = "PWM1 pulse count\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11263        pub struct PwmPeriodVal1Spec;
11264        impl crate::RegisterSpec for PwmPeriodVal1Spec {
11265            type Ux = u32;
11266        }
11267        #[doc = "`read()` method returns [`pwm_period_val1::R`](R) reader structure"]
11268        impl crate::Readable for PwmPeriodVal1Spec {}
11269        #[doc = "`write(|w| ..)` method takes [`pwm_period_val1::W`](W) writer structure"]
11270        impl crate::Writable for PwmPeriodVal1Spec {
11271            type Safety = crate::Unsafe;
11272        }
11273        #[doc = "`reset()` method sets PWM_PERIOD_VAL1 to value 0"]
11274        impl crate::Resettable for PwmPeriodVal1Spec {}
11275    }
11276    #[doc = "PWM_PERIODCNT1 (rw) register accessor: PWM1 pulse count current\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt1`] module"]
11277    #[doc(alias = "PWM_PERIODCNT1")]
11278    pub type PwmPeriodcnt1 = crate::Reg<pwm_periodcnt1::PwmPeriodcnt1Spec>;
11279    #[doc = "PWM1 pulse count current"]
11280    pub mod pwm_periodcnt1 {
11281        #[doc = "Register `PWM_PERIODCNT1` reader"]
11282        pub type R = crate::R<PwmPeriodcnt1Spec>;
11283        #[doc = "Register `PWM_PERIODCNT1` writer"]
11284        pub type W = crate::W<PwmPeriodcnt1Spec>;
11285        #[doc = "Field `pwm_periodcnt_1` reader - Current pulse count"]
11286        pub type PwmPeriodcnt1R = crate::FieldReader<u16>;
11287        impl R {
11288            #[doc = "Bits 0:15 - Current pulse count"]
11289            #[inline(always)]
11290            pub fn pwm_periodcnt_1(&self) -> PwmPeriodcnt1R {
11291                PwmPeriodcnt1R::new((self.bits & 0xffff) as u16)
11292            }
11293        }
11294        impl W {}
11295        #[doc = "PWM1 pulse count current\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11296        pub struct PwmPeriodcnt1Spec;
11297        impl crate::RegisterSpec for PwmPeriodcnt1Spec {
11298            type Ux = u32;
11299        }
11300        #[doc = "`read()` method returns [`pwm_periodcnt1::R`](R) reader structure"]
11301        impl crate::Readable for PwmPeriodcnt1Spec {}
11302        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt1::W`](W) writer structure"]
11303        impl crate::Writable for PwmPeriodcnt1Spec {
11304            type Safety = crate::Unsafe;
11305        }
11306        #[doc = "`reset()` method sets PWM_PERIODCNT1 to value 0"]
11307        impl crate::Resettable for PwmPeriodcnt1Spec {}
11308    }
11309    #[doc = "PWM_ABNOR_STATE0 (rw) register accessor: PWM abnormal state register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state0`] module"]
11310    #[doc(alias = "PWM_ABNOR_STATE0")]
11311    pub type PwmAbnorState0 = crate::Reg<pwm_abnor_state0::PwmAbnorState0Spec>;
11312    #[doc = "PWM abnormal state register 0"]
11313    pub mod pwm_abnor_state0 {
11314        #[doc = "Register `PWM_ABNOR_STATE0` reader"]
11315        pub type R = crate::R<PwmAbnorState0Spec>;
11316        #[doc = "Register `PWM_ABNOR_STATE0` writer"]
11317        pub type W = crate::W<PwmAbnorState0Spec>;
11318        #[doc = "Field `pwm_abnor_state0` reader - Multi-channel config abnormal state, each bit per PWM"]
11319        pub type PwmAbnorState0R = crate::FieldReader<u16>;
11320        impl R {
11321            #[doc = "Bits 0:15 - Multi-channel config abnormal state, each bit per PWM"]
11322            #[inline(always)]
11323            pub fn pwm_abnor_state0(&self) -> PwmAbnorState0R {
11324                PwmAbnorState0R::new((self.bits & 0xffff) as u16)
11325            }
11326        }
11327        impl W {}
11328        #[doc = "PWM abnormal state register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11329        pub struct PwmAbnorState0Spec;
11330        impl crate::RegisterSpec for PwmAbnorState0Spec {
11331            type Ux = u32;
11332        }
11333        #[doc = "`read()` method returns [`pwm_abnor_state0::R`](R) reader structure"]
11334        impl crate::Readable for PwmAbnorState0Spec {}
11335        #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state0::W`](W) writer structure"]
11336        impl crate::Writable for PwmAbnorState0Spec {
11337            type Safety = crate::Unsafe;
11338        }
11339        #[doc = "`reset()` method sets PWM_ABNOR_STATE0 to value 0"]
11340        impl crate::Resettable for PwmAbnorState0Spec {}
11341    }
11342    #[doc = "PWM_ABNOR_STATE1 (rw) register accessor: PWM abnormal state register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state1`] module"]
11343    #[doc(alias = "PWM_ABNOR_STATE1")]
11344    pub type PwmAbnorState1 = crate::Reg<pwm_abnor_state1::PwmAbnorState1Spec>;
11345    #[doc = "PWM abnormal state register 1"]
11346    pub mod pwm_abnor_state1 {
11347        #[doc = "Register `PWM_ABNOR_STATE1` reader"]
11348        pub type R = crate::R<PwmAbnorState1Spec>;
11349        #[doc = "Register `PWM_ABNOR_STATE1` writer"]
11350        pub type W = crate::W<PwmAbnorState1Spec>;
11351        #[doc = "Field `pwm_abnor_state1` reader - Counter config abnormal state, each bit per PWM"]
11352        pub type PwmAbnorState1R = crate::FieldReader<u16>;
11353        impl R {
11354            #[doc = "Bits 0:15 - Counter config abnormal state, each bit per PWM"]
11355            #[inline(always)]
11356            pub fn pwm_abnor_state1(&self) -> PwmAbnorState1R {
11357                PwmAbnorState1R::new((self.bits & 0xffff) as u16)
11358            }
11359        }
11360        impl W {}
11361        #[doc = "PWM abnormal state register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11362        pub struct PwmAbnorState1Spec;
11363        impl crate::RegisterSpec for PwmAbnorState1Spec {
11364            type Ux = u32;
11365        }
11366        #[doc = "`read()` method returns [`pwm_abnor_state1::R`](R) reader structure"]
11367        impl crate::Readable for PwmAbnorState1Spec {}
11368        #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state1::W`](W) writer structure"]
11369        impl crate::Writable for PwmAbnorState1Spec {
11370            type Safety = crate::Unsafe;
11371        }
11372        #[doc = "`reset()` method sets PWM_ABNOR_STATE1 to value 0"]
11373        impl crate::Resettable for PwmAbnorState1Spec {}
11374    }
11375    #[doc = "PWM_ABNOR_STATE_CLR0 (rw) register accessor: PWM abnormal state clear 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state_clr0`] module"]
11376    #[doc(alias = "PWM_ABNOR_STATE_CLR0")]
11377    pub type PwmAbnorStateClr0 = crate::Reg<pwm_abnor_state_clr0::PwmAbnorStateClr0Spec>;
11378    #[doc = "PWM abnormal state clear 0"]
11379    pub mod pwm_abnor_state_clr0 {
11380        #[doc = "Register `PWM_ABNOR_STATE_CLR0` reader"]
11381        pub type R = crate::R<PwmAbnorStateClr0Spec>;
11382        #[doc = "Register `PWM_ABNOR_STATE_CLR0` writer"]
11383        pub type W = crate::W<PwmAbnorStateClr0Spec>;
11384        #[doc = "Field `pwm_abnor_state_clr0` writer - Clear abnormal state 0 (self-clearing)"]
11385        pub type PwmAbnorStateClr0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11386        impl W {
11387            #[doc = "Bits 0:15 - Clear abnormal state 0 (self-clearing)"]
11388            #[inline(always)]
11389            pub fn pwm_abnor_state_clr0(
11390                &mut self,
11391            ) -> PwmAbnorStateClr0W<'_, PwmAbnorStateClr0Spec> {
11392                PwmAbnorStateClr0W::new(self, 0)
11393            }
11394        }
11395        #[doc = "PWM abnormal state clear 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11396        pub struct PwmAbnorStateClr0Spec;
11397        impl crate::RegisterSpec for PwmAbnorStateClr0Spec {
11398            type Ux = u32;
11399        }
11400        #[doc = "`read()` method returns [`pwm_abnor_state_clr0::R`](R) reader structure"]
11401        impl crate::Readable for PwmAbnorStateClr0Spec {}
11402        #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state_clr0::W`](W) writer structure"]
11403        impl crate::Writable for PwmAbnorStateClr0Spec {
11404            type Safety = crate::Unsafe;
11405        }
11406        #[doc = "`reset()` method sets PWM_ABNOR_STATE_CLR0 to value 0"]
11407        impl crate::Resettable for PwmAbnorStateClr0Spec {}
11408    }
11409    #[doc = "PWM_ABNOR_STATE_CLR1 (rw) register accessor: PWM abnormal state clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state_clr1`] module"]
11410    #[doc(alias = "PWM_ABNOR_STATE_CLR1")]
11411    pub type PwmAbnorStateClr1 = crate::Reg<pwm_abnor_state_clr1::PwmAbnorStateClr1Spec>;
11412    #[doc = "PWM abnormal state clear 1"]
11413    pub mod pwm_abnor_state_clr1 {
11414        #[doc = "Register `PWM_ABNOR_STATE_CLR1` reader"]
11415        pub type R = crate::R<PwmAbnorStateClr1Spec>;
11416        #[doc = "Register `PWM_ABNOR_STATE_CLR1` writer"]
11417        pub type W = crate::W<PwmAbnorStateClr1Spec>;
11418        #[doc = "Field `pwm_abnor_state_clr1` writer - Clear abnormal state 1 (self-clearing)"]
11419        pub type PwmAbnorStateClr1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11420        impl W {
11421            #[doc = "Bits 0:15 - Clear abnormal state 1 (self-clearing)"]
11422            #[inline(always)]
11423            pub fn pwm_abnor_state_clr1(
11424                &mut self,
11425            ) -> PwmAbnorStateClr1W<'_, PwmAbnorStateClr1Spec> {
11426                PwmAbnorStateClr1W::new(self, 0)
11427            }
11428        }
11429        #[doc = "PWM abnormal state clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11430        pub struct PwmAbnorStateClr1Spec;
11431        impl crate::RegisterSpec for PwmAbnorStateClr1Spec {
11432            type Ux = u32;
11433        }
11434        #[doc = "`read()` method returns [`pwm_abnor_state_clr1::R`](R) reader structure"]
11435        impl crate::Readable for PwmAbnorStateClr1Spec {}
11436        #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state_clr1::W`](W) writer structure"]
11437        impl crate::Writable for PwmAbnorStateClr1Spec {
11438            type Safety = crate::Unsafe;
11439        }
11440        #[doc = "`reset()` method sets PWM_ABNOR_STATE_CLR1 to value 0"]
11441        impl crate::Resettable for PwmAbnorStateClr1Spec {}
11442    }
11443    #[doc = "PWM_INT_MASK (rw) register accessor: PWM interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_int_mask`] module"]
11444    #[doc(alias = "PWM_INT_MASK")]
11445    pub type PwmIntMask = crate::Reg<pwm_int_mask::PwmIntMaskSpec>;
11446    #[doc = "PWM interrupt mask"]
11447    pub mod pwm_int_mask {
11448        #[doc = "Register `PWM_INT_MASK` reader"]
11449        pub type R = crate::R<PwmIntMaskSpec>;
11450        #[doc = "Register `PWM_INT_MASK` writer"]
11451        pub type W = crate::W<PwmIntMaskSpec>;
11452        #[doc = "Field `pwm_int_mask` reader - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
11453        pub type PwmIntMaskR = crate::FieldReader;
11454        #[doc = "Field `pwm_int_mask` writer - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
11455        pub type PwmIntMaskW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
11456        impl R {
11457            #[doc = "Bits 0:1 - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
11458            #[inline(always)]
11459            pub fn pwm_int_mask(&self) -> PwmIntMaskR {
11460                PwmIntMaskR::new((self.bits & 3) as u8)
11461            }
11462        }
11463        impl W {
11464            #[doc = "Bits 0:1 - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
11465            #[inline(always)]
11466            pub fn pwm_int_mask(&mut self) -> PwmIntMaskW<'_, PwmIntMaskSpec> {
11467                PwmIntMaskW::new(self, 0)
11468            }
11469        }
11470        #[doc = "PWM interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11471        pub struct PwmIntMaskSpec;
11472        impl crate::RegisterSpec for PwmIntMaskSpec {
11473            type Ux = u32;
11474        }
11475        #[doc = "`read()` method returns [`pwm_int_mask::R`](R) reader structure"]
11476        impl crate::Readable for PwmIntMaskSpec {}
11477        #[doc = "`write(|w| ..)` method takes [`pwm_int_mask::W`](W) writer structure"]
11478        impl crate::Writable for PwmIntMaskSpec {
11479            type Safety = crate::Unsafe;
11480        }
11481        #[doc = "`reset()` method sets PWM_INT_MASK to value 0"]
11482        impl crate::Resettable for PwmIntMaskSpec {}
11483    }
11484    #[doc = "PWM_DMA_EN (rw) register accessor: PWM DMA enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_dma_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_dma_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_dma_en`] module"]
11485    #[doc(alias = "PWM_DMA_EN")]
11486    pub type PwmDmaEn = crate::Reg<pwm_dma_en::PwmDmaEnSpec>;
11487    #[doc = "PWM DMA enable"]
11488    pub mod pwm_dma_en {
11489        #[doc = "Register `PWM_DMA_EN` reader"]
11490        pub type R = crate::R<PwmDmaEnSpec>;
11491        #[doc = "Register `PWM_DMA_EN` writer"]
11492        pub type W = crate::W<PwmDmaEnSpec>;
11493        #[doc = "Field `pwm_dma_en` reader - DMA enable: 0=disabled; 1=enabled"]
11494        pub type PwmDmaEnR = crate::BitReader;
11495        #[doc = "Field `pwm_dma_en` writer - DMA enable: 0=disabled; 1=enabled"]
11496        pub type PwmDmaEnW<'a, REG> = crate::BitWriter<'a, REG>;
11497        impl R {
11498            #[doc = "Bit 0 - DMA enable: 0=disabled; 1=enabled"]
11499            #[inline(always)]
11500            pub fn pwm_dma_en(&self) -> PwmDmaEnR {
11501                PwmDmaEnR::new((self.bits & 1) != 0)
11502            }
11503        }
11504        impl W {
11505            #[doc = "Bit 0 - DMA enable: 0=disabled; 1=enabled"]
11506            #[inline(always)]
11507            pub fn pwm_dma_en(&mut self) -> PwmDmaEnW<'_, PwmDmaEnSpec> {
11508                PwmDmaEnW::new(self, 0)
11509            }
11510        }
11511        #[doc = "PWM DMA enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_dma_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_dma_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11512        pub struct PwmDmaEnSpec;
11513        impl crate::RegisterSpec for PwmDmaEnSpec {
11514            type Ux = u32;
11515        }
11516        #[doc = "`read()` method returns [`pwm_dma_en::R`](R) reader structure"]
11517        impl crate::Readable for PwmDmaEnSpec {}
11518        #[doc = "`write(|w| ..)` method takes [`pwm_dma_en::W`](W) writer structure"]
11519        impl crate::Writable for PwmDmaEnSpec {
11520            type Safety = crate::Unsafe;
11521        }
11522        #[doc = "`reset()` method sets PWM_DMA_EN to value 0"]
11523        impl crate::Resettable for PwmDmaEnSpec {}
11524    }
11525    #[doc = "PWM_CFG_INT_CLR0 (rw) register accessor: PWM stepping cycle end interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_cfg_int_clr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_cfg_int_clr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_cfg_int_clr0`] module"]
11526    #[doc(alias = "PWM_CFG_INT_CLR0")]
11527    pub type PwmCfgIntClr0 = crate::Reg<pwm_cfg_int_clr0::PwmCfgIntClr0Spec>;
11528    #[doc = "PWM stepping cycle end interrupt clear"]
11529    pub mod pwm_cfg_int_clr0 {
11530        #[doc = "Register `PWM_CFG_INT_CLR0` reader"]
11531        pub type R = crate::R<PwmCfgIntClr0Spec>;
11532        #[doc = "Register `PWM_CFG_INT_CLR0` writer"]
11533        pub type W = crate::W<PwmCfgIntClr0Spec>;
11534        #[doc = "Field `pwm_cfg_int_clr0` writer - Stepping cycle end interrupt clear (self-clearing)"]
11535        pub type PwmCfgIntClr0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11536        impl W {
11537            #[doc = "Bits 0:15 - Stepping cycle end interrupt clear (self-clearing)"]
11538            #[inline(always)]
11539            pub fn pwm_cfg_int_clr0(&mut self) -> PwmCfgIntClr0W<'_, PwmCfgIntClr0Spec> {
11540                PwmCfgIntClr0W::new(self, 0)
11541            }
11542        }
11543        #[doc = "PWM stepping cycle end interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_cfg_int_clr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_cfg_int_clr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11544        pub struct PwmCfgIntClr0Spec;
11545        impl crate::RegisterSpec for PwmCfgIntClr0Spec {
11546            type Ux = u32;
11547        }
11548        #[doc = "`read()` method returns [`pwm_cfg_int_clr0::R`](R) reader structure"]
11549        impl crate::Readable for PwmCfgIntClr0Spec {}
11550        #[doc = "`write(|w| ..)` method takes [`pwm_cfg_int_clr0::W`](W) writer structure"]
11551        impl crate::Writable for PwmCfgIntClr0Spec {
11552            type Safety = crate::Unsafe;
11553        }
11554        #[doc = "`reset()` method sets PWM_CFG_INT_CLR0 to value 0"]
11555        impl crate::Resettable for PwmCfgIntClr0Spec {}
11556    }
11557    #[doc = "PWM_EN2 (rw) register accessor: PWM2 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en2`] module"]
11558    #[doc(alias = "PWM_EN2")]
11559    pub type PwmEn2 = crate::Reg<pwm_en2::PwmEn2Spec>;
11560    #[doc = "PWM2 enable"]
11561    pub mod pwm_en2 {
11562        #[doc = "Register `PWM_EN2` reader"]
11563        pub type R = crate::R<PwmEn2Spec>;
11564        #[doc = "Register `PWM_EN2` writer"]
11565        pub type W = crate::W<PwmEn2Spec>;
11566        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
11567        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
11568        pub enum PwmEn2 {
11569            #[doc = "0: PWM disabled, output low"]
11570            Off = 0,
11571            #[doc = "1: PWM enabled"]
11572            On = 1,
11573        }
11574        impl From<PwmEn2> for bool {
11575            #[inline(always)]
11576            fn from(variant: PwmEn2) -> Self {
11577                variant as u8 != 0
11578            }
11579        }
11580        #[doc = "Field `pwm_en_2` reader - PWM0 enable: 0=off; 1=on"]
11581        pub type PwmEn2R = crate::BitReader<PwmEn2>;
11582        impl PwmEn2R {
11583            #[doc = "Get enumerated values variant"]
11584            #[inline(always)]
11585            pub const fn variant(&self) -> PwmEn2 {
11586                match self.bits {
11587                    false => PwmEn2::Off,
11588                    true => PwmEn2::On,
11589                }
11590            }
11591            #[doc = "PWM disabled, output low"]
11592            #[inline(always)]
11593            pub fn is_off(&self) -> bool {
11594                *self == PwmEn2::Off
11595            }
11596            #[doc = "PWM enabled"]
11597            #[inline(always)]
11598            pub fn is_on(&self) -> bool {
11599                *self == PwmEn2::On
11600            }
11601        }
11602        #[doc = "Field `pwm_en_2` writer - PWM0 enable: 0=off; 1=on"]
11603        pub type PwmEn2W<'a, REG> = crate::BitWriter<'a, REG, PwmEn2>;
11604        impl<'a, REG> PwmEn2W<'a, REG>
11605        where
11606            REG: crate::Writable + crate::RegisterSpec,
11607        {
11608            #[doc = "PWM disabled, output low"]
11609            #[inline(always)]
11610            pub fn off(self) -> &'a mut crate::W<REG> {
11611                self.variant(PwmEn2::Off)
11612            }
11613            #[doc = "PWM enabled"]
11614            #[inline(always)]
11615            pub fn on(self) -> &'a mut crate::W<REG> {
11616                self.variant(PwmEn2::On)
11617            }
11618        }
11619        impl R {
11620            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
11621            #[inline(always)]
11622            pub fn pwm_en_2(&self) -> PwmEn2R {
11623                PwmEn2R::new((self.bits & 1) != 0)
11624            }
11625        }
11626        impl W {
11627            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
11628            #[inline(always)]
11629            pub fn pwm_en_2(&mut self) -> PwmEn2W<'_, PwmEn2Spec> {
11630                PwmEn2W::new(self, 0)
11631            }
11632        }
11633        #[doc = "PWM2 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11634        pub struct PwmEn2Spec;
11635        impl crate::RegisterSpec for PwmEn2Spec {
11636            type Ux = u32;
11637        }
11638        #[doc = "`read()` method returns [`pwm_en2::R`](R) reader structure"]
11639        impl crate::Readable for PwmEn2Spec {}
11640        #[doc = "`write(|w| ..)` method takes [`pwm_en2::W`](W) writer structure"]
11641        impl crate::Writable for PwmEn2Spec {
11642            type Safety = crate::Unsafe;
11643        }
11644        #[doc = "`reset()` method sets PWM_EN2 to value 0"]
11645        impl crate::Resettable for PwmEn2Spec {}
11646    }
11647    #[doc = "PWM_PORTITY2 (rw) register accessor: PWM2 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity2`] module"]
11648    #[doc(alias = "PWM_PORTITY2")]
11649    pub type PwmPortity2 = crate::Reg<pwm_portity2::PwmPortity2Spec>;
11650    #[doc = "PWM2 polarity"]
11651    pub mod pwm_portity2 {
11652        #[doc = "Register `PWM_PORTITY2` reader"]
11653        pub type R = crate::R<PwmPortity2Spec>;
11654        #[doc = "Register `PWM_PORTITY2` writer"]
11655        pub type W = crate::W<PwmPortity2Spec>;
11656        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
11657        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
11658        pub enum PwmPoarity2 {
11659            #[doc = "0: Normal polarity"]
11660            Normal = 0,
11661            #[doc = "1: Inverted polarity"]
11662            Inverted = 1,
11663        }
11664        impl From<PwmPoarity2> for bool {
11665            #[inline(always)]
11666            fn from(variant: PwmPoarity2) -> Self {
11667                variant as u8 != 0
11668            }
11669        }
11670        #[doc = "Field `pwm_poarity_2` reader - PWM0 polarity: 0=normal; 1=inverted"]
11671        pub type PwmPoarity2R = crate::BitReader<PwmPoarity2>;
11672        impl PwmPoarity2R {
11673            #[doc = "Get enumerated values variant"]
11674            #[inline(always)]
11675            pub const fn variant(&self) -> PwmPoarity2 {
11676                match self.bits {
11677                    false => PwmPoarity2::Normal,
11678                    true => PwmPoarity2::Inverted,
11679                }
11680            }
11681            #[doc = "Normal polarity"]
11682            #[inline(always)]
11683            pub fn is_normal(&self) -> bool {
11684                *self == PwmPoarity2::Normal
11685            }
11686            #[doc = "Inverted polarity"]
11687            #[inline(always)]
11688            pub fn is_inverted(&self) -> bool {
11689                *self == PwmPoarity2::Inverted
11690            }
11691        }
11692        #[doc = "Field `pwm_poarity_2` writer - PWM0 polarity: 0=normal; 1=inverted"]
11693        pub type PwmPoarity2W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity2>;
11694        impl<'a, REG> PwmPoarity2W<'a, REG>
11695        where
11696            REG: crate::Writable + crate::RegisterSpec,
11697        {
11698            #[doc = "Normal polarity"]
11699            #[inline(always)]
11700            pub fn normal(self) -> &'a mut crate::W<REG> {
11701                self.variant(PwmPoarity2::Normal)
11702            }
11703            #[doc = "Inverted polarity"]
11704            #[inline(always)]
11705            pub fn inverted(self) -> &'a mut crate::W<REG> {
11706                self.variant(PwmPoarity2::Inverted)
11707            }
11708        }
11709        impl R {
11710            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
11711            #[inline(always)]
11712            pub fn pwm_poarity_2(&self) -> PwmPoarity2R {
11713                PwmPoarity2R::new((self.bits & 1) != 0)
11714            }
11715        }
11716        impl W {
11717            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
11718            #[inline(always)]
11719            pub fn pwm_poarity_2(&mut self) -> PwmPoarity2W<'_, PwmPortity2Spec> {
11720                PwmPoarity2W::new(self, 0)
11721            }
11722        }
11723        #[doc = "PWM2 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11724        pub struct PwmPortity2Spec;
11725        impl crate::RegisterSpec for PwmPortity2Spec {
11726            type Ux = u32;
11727        }
11728        #[doc = "`read()` method returns [`pwm_portity2::R`](R) reader structure"]
11729        impl crate::Readable for PwmPortity2Spec {}
11730        #[doc = "`write(|w| ..)` method takes [`pwm_portity2::W`](W) writer structure"]
11731        impl crate::Writable for PwmPortity2Spec {
11732            type Safety = crate::Unsafe;
11733        }
11734        #[doc = "`reset()` method sets PWM_PORTITY2 to value 0"]
11735        impl crate::Resettable for PwmPortity2Spec {}
11736    }
11737    #[doc = "PWM_OEN_CFG2 (rw) register accessor: PWM2 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg2`] module"]
11738    #[doc(alias = "PWM_OEN_CFG2")]
11739    pub type PwmOenCfg2 = crate::Reg<pwm_oen_cfg2::PwmOenCfg2Spec>;
11740    #[doc = "PWM2 high-impedance config"]
11741    pub mod pwm_oen_cfg2 {
11742        #[doc = "Register `PWM_OEN_CFG2` reader"]
11743        pub type R = crate::R<PwmOenCfg2Spec>;
11744        #[doc = "Register `PWM_OEN_CFG2` writer"]
11745        pub type W = crate::W<PwmOenCfg2Spec>;
11746        #[doc = "Field `pwm_oen_cfg_2` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
11747        pub type PwmOenCfg2R = crate::BitReader;
11748        #[doc = "Field `pwm_oen_cfg_2` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
11749        pub type PwmOenCfg2W<'a, REG> = crate::BitWriter<'a, REG>;
11750        impl R {
11751            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
11752            #[inline(always)]
11753            pub fn pwm_oen_cfg_2(&self) -> PwmOenCfg2R {
11754                PwmOenCfg2R::new((self.bits & 1) != 0)
11755            }
11756        }
11757        impl W {
11758            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
11759            #[inline(always)]
11760            pub fn pwm_oen_cfg_2(&mut self) -> PwmOenCfg2W<'_, PwmOenCfg2Spec> {
11761                PwmOenCfg2W::new(self, 0)
11762            }
11763        }
11764        #[doc = "PWM2 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11765        pub struct PwmOenCfg2Spec;
11766        impl crate::RegisterSpec for PwmOenCfg2Spec {
11767            type Ux = u32;
11768        }
11769        #[doc = "`read()` method returns [`pwm_oen_cfg2::R`](R) reader structure"]
11770        impl crate::Readable for PwmOenCfg2Spec {}
11771        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg2::W`](W) writer structure"]
11772        impl crate::Writable for PwmOenCfg2Spec {
11773            type Safety = crate::Unsafe;
11774        }
11775        #[doc = "`reset()` method sets PWM_OEN_CFG2 to value 0"]
11776        impl crate::Resettable for PwmOenCfg2Spec {}
11777    }
11778    #[doc = "PWM_OFFSET_L2 (rw) register accessor: PWM2 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l2`] module"]
11779    #[doc(alias = "PWM_OFFSET_L2")]
11780    pub type PwmOffsetL2 = crate::Reg<pwm_offset_l2::PwmOffsetL2Spec>;
11781    #[doc = "PWM2 phase offset low 16 bits"]
11782    pub mod pwm_offset_l2 {
11783        #[doc = "Register `PWM_OFFSET_L2` reader"]
11784        pub type R = crate::R<PwmOffsetL2Spec>;
11785        #[doc = "Register `PWM_OFFSET_L2` writer"]
11786        pub type W = crate::W<PwmOffsetL2Spec>;
11787        #[doc = "Field `pwm_offset_l_2` reader - PWM0 phase offset low 16 bits"]
11788        pub type PwmOffsetL2R = crate::FieldReader<u16>;
11789        #[doc = "Field `pwm_offset_l_2` writer - PWM0 phase offset low 16 bits"]
11790        pub type PwmOffsetL2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11791        impl R {
11792            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
11793            #[inline(always)]
11794            pub fn pwm_offset_l_2(&self) -> PwmOffsetL2R {
11795                PwmOffsetL2R::new((self.bits & 0xffff) as u16)
11796            }
11797        }
11798        impl W {
11799            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
11800            #[inline(always)]
11801            pub fn pwm_offset_l_2(&mut self) -> PwmOffsetL2W<'_, PwmOffsetL2Spec> {
11802                PwmOffsetL2W::new(self, 0)
11803            }
11804        }
11805        #[doc = "PWM2 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11806        pub struct PwmOffsetL2Spec;
11807        impl crate::RegisterSpec for PwmOffsetL2Spec {
11808            type Ux = u32;
11809        }
11810        #[doc = "`read()` method returns [`pwm_offset_l2::R`](R) reader structure"]
11811        impl crate::Readable for PwmOffsetL2Spec {}
11812        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l2::W`](W) writer structure"]
11813        impl crate::Writable for PwmOffsetL2Spec {
11814            type Safety = crate::Unsafe;
11815        }
11816        #[doc = "`reset()` method sets PWM_OFFSET_L2 to value 0"]
11817        impl crate::Resettable for PwmOffsetL2Spec {}
11818    }
11819    #[doc = "PWM_OFFSET_H2 (rw) register accessor: PWM2 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h2`] module"]
11820    #[doc(alias = "PWM_OFFSET_H2")]
11821    pub type PwmOffsetH2 = crate::Reg<pwm_offset_h2::PwmOffsetH2Spec>;
11822    #[doc = "PWM2 phase offset high 16 bits"]
11823    pub mod pwm_offset_h2 {
11824        #[doc = "Register `PWM_OFFSET_H2` reader"]
11825        pub type R = crate::R<PwmOffsetH2Spec>;
11826        #[doc = "Register `PWM_OFFSET_H2` writer"]
11827        pub type W = crate::W<PwmOffsetH2Spec>;
11828        #[doc = "Field `pwm_offset_h_2` reader - PWM0 phase offset high 16 bits"]
11829        pub type PwmOffsetH2R = crate::FieldReader<u16>;
11830        #[doc = "Field `pwm_offset_h_2` writer - PWM0 phase offset high 16 bits"]
11831        pub type PwmOffsetH2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11832        impl R {
11833            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
11834            #[inline(always)]
11835            pub fn pwm_offset_h_2(&self) -> PwmOffsetH2R {
11836                PwmOffsetH2R::new((self.bits & 0xffff) as u16)
11837            }
11838        }
11839        impl W {
11840            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
11841            #[inline(always)]
11842            pub fn pwm_offset_h_2(&mut self) -> PwmOffsetH2W<'_, PwmOffsetH2Spec> {
11843                PwmOffsetH2W::new(self, 0)
11844            }
11845        }
11846        #[doc = "PWM2 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11847        pub struct PwmOffsetH2Spec;
11848        impl crate::RegisterSpec for PwmOffsetH2Spec {
11849            type Ux = u32;
11850        }
11851        #[doc = "`read()` method returns [`pwm_offset_h2::R`](R) reader structure"]
11852        impl crate::Readable for PwmOffsetH2Spec {}
11853        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h2::W`](W) writer structure"]
11854        impl crate::Writable for PwmOffsetH2Spec {
11855            type Safety = crate::Unsafe;
11856        }
11857        #[doc = "`reset()` method sets PWM_OFFSET_H2 to value 0"]
11858        impl crate::Resettable for PwmOffsetH2Spec {}
11859    }
11860    #[doc = "PWM_FREQ_L2 (rw) register accessor: PWM2 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l2`] module"]
11861    #[doc(alias = "PWM_FREQ_L2")]
11862    pub type PwmFreqL2 = crate::Reg<pwm_freq_l2::PwmFreqL2Spec>;
11863    #[doc = "PWM2 frequency low 16 bits"]
11864    pub mod pwm_freq_l2 {
11865        #[doc = "Register `PWM_FREQ_L2` reader"]
11866        pub type R = crate::R<PwmFreqL2Spec>;
11867        #[doc = "Register `PWM_FREQ_L2` writer"]
11868        pub type W = crate::W<PwmFreqL2Spec>;
11869        #[doc = "Field `pwm_freq_l_2` reader - PWM0 clock divider low 16 bits"]
11870        pub type PwmFreqL2R = crate::FieldReader<u16>;
11871        #[doc = "Field `pwm_freq_l_2` writer - PWM0 clock divider low 16 bits"]
11872        pub type PwmFreqL2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11873        impl R {
11874            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
11875            #[inline(always)]
11876            pub fn pwm_freq_l_2(&self) -> PwmFreqL2R {
11877                PwmFreqL2R::new((self.bits & 0xffff) as u16)
11878            }
11879        }
11880        impl W {
11881            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
11882            #[inline(always)]
11883            pub fn pwm_freq_l_2(&mut self) -> PwmFreqL2W<'_, PwmFreqL2Spec> {
11884                PwmFreqL2W::new(self, 0)
11885            }
11886        }
11887        #[doc = "PWM2 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11888        pub struct PwmFreqL2Spec;
11889        impl crate::RegisterSpec for PwmFreqL2Spec {
11890            type Ux = u32;
11891        }
11892        #[doc = "`read()` method returns [`pwm_freq_l2::R`](R) reader structure"]
11893        impl crate::Readable for PwmFreqL2Spec {}
11894        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l2::W`](W) writer structure"]
11895        impl crate::Writable for PwmFreqL2Spec {
11896            type Safety = crate::Unsafe;
11897        }
11898        #[doc = "`reset()` method sets PWM_FREQ_L2 to value 0"]
11899        impl crate::Resettable for PwmFreqL2Spec {}
11900    }
11901    #[doc = "PWM_FREQ_H2 (rw) register accessor: PWM2 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h2`] module"]
11902    #[doc(alias = "PWM_FREQ_H2")]
11903    pub type PwmFreqH2 = crate::Reg<pwm_freq_h2::PwmFreqH2Spec>;
11904    #[doc = "PWM2 frequency high 16 bits"]
11905    pub mod pwm_freq_h2 {
11906        #[doc = "Register `PWM_FREQ_H2` reader"]
11907        pub type R = crate::R<PwmFreqH2Spec>;
11908        #[doc = "Register `PWM_FREQ_H2` writer"]
11909        pub type W = crate::W<PwmFreqH2Spec>;
11910        #[doc = "Field `pwm_freq_h_2` reader - PWM0 clock divider high 16 bits"]
11911        pub type PwmFreqH2R = crate::FieldReader<u16>;
11912        #[doc = "Field `pwm_freq_h_2` writer - PWM0 clock divider high 16 bits"]
11913        pub type PwmFreqH2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11914        impl R {
11915            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
11916            #[inline(always)]
11917            pub fn pwm_freq_h_2(&self) -> PwmFreqH2R {
11918                PwmFreqH2R::new((self.bits & 0xffff) as u16)
11919            }
11920        }
11921        impl W {
11922            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
11923            #[inline(always)]
11924            pub fn pwm_freq_h_2(&mut self) -> PwmFreqH2W<'_, PwmFreqH2Spec> {
11925                PwmFreqH2W::new(self, 0)
11926            }
11927        }
11928        #[doc = "PWM2 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11929        pub struct PwmFreqH2Spec;
11930        impl crate::RegisterSpec for PwmFreqH2Spec {
11931            type Ux = u32;
11932        }
11933        #[doc = "`read()` method returns [`pwm_freq_h2::R`](R) reader structure"]
11934        impl crate::Readable for PwmFreqH2Spec {}
11935        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h2::W`](W) writer structure"]
11936        impl crate::Writable for PwmFreqH2Spec {
11937            type Safety = crate::Unsafe;
11938        }
11939        #[doc = "`reset()` method sets PWM_FREQ_H2 to value 0"]
11940        impl crate::Resettable for PwmFreqH2Spec {}
11941    }
11942    #[doc = "PWM_DUTY_L2 (rw) register accessor: PWM2 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l2`] module"]
11943    #[doc(alias = "PWM_DUTY_L2")]
11944    pub type PwmDutyL2 = crate::Reg<pwm_duty_l2::PwmDutyL2Spec>;
11945    #[doc = "PWM2 duty cycle low 16 bits"]
11946    pub mod pwm_duty_l2 {
11947        #[doc = "Register `PWM_DUTY_L2` reader"]
11948        pub type R = crate::R<PwmDutyL2Spec>;
11949        #[doc = "Register `PWM_DUTY_L2` writer"]
11950        pub type W = crate::W<PwmDutyL2Spec>;
11951        #[doc = "Field `pwm_duty_l_2` reader - PWM0 duty cycle low 16 bits"]
11952        pub type PwmDutyL2R = crate::FieldReader<u16>;
11953        #[doc = "Field `pwm_duty_l_2` writer - PWM0 duty cycle low 16 bits"]
11954        pub type PwmDutyL2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11955        impl R {
11956            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
11957            #[inline(always)]
11958            pub fn pwm_duty_l_2(&self) -> PwmDutyL2R {
11959                PwmDutyL2R::new((self.bits & 0xffff) as u16)
11960            }
11961        }
11962        impl W {
11963            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
11964            #[inline(always)]
11965            pub fn pwm_duty_l_2(&mut self) -> PwmDutyL2W<'_, PwmDutyL2Spec> {
11966                PwmDutyL2W::new(self, 0)
11967            }
11968        }
11969        #[doc = "PWM2 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11970        pub struct PwmDutyL2Spec;
11971        impl crate::RegisterSpec for PwmDutyL2Spec {
11972            type Ux = u32;
11973        }
11974        #[doc = "`read()` method returns [`pwm_duty_l2::R`](R) reader structure"]
11975        impl crate::Readable for PwmDutyL2Spec {}
11976        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l2::W`](W) writer structure"]
11977        impl crate::Writable for PwmDutyL2Spec {
11978            type Safety = crate::Unsafe;
11979        }
11980        #[doc = "`reset()` method sets PWM_DUTY_L2 to value 0"]
11981        impl crate::Resettable for PwmDutyL2Spec {}
11982    }
11983    #[doc = "PWM_DUTY_H2 (rw) register accessor: PWM2 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h2`] module"]
11984    #[doc(alias = "PWM_DUTY_H2")]
11985    pub type PwmDutyH2 = crate::Reg<pwm_duty_h2::PwmDutyH2Spec>;
11986    #[doc = "PWM2 duty cycle high 16 bits"]
11987    pub mod pwm_duty_h2 {
11988        #[doc = "Register `PWM_DUTY_H2` reader"]
11989        pub type R = crate::R<PwmDutyH2Spec>;
11990        #[doc = "Register `PWM_DUTY_H2` writer"]
11991        pub type W = crate::W<PwmDutyH2Spec>;
11992        #[doc = "Field `pwm_duty_h_2` reader - PWM0 duty cycle high 16 bits"]
11993        pub type PwmDutyH2R = crate::FieldReader<u16>;
11994        #[doc = "Field `pwm_duty_h_2` writer - PWM0 duty cycle high 16 bits"]
11995        pub type PwmDutyH2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11996        impl R {
11997            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
11998            #[inline(always)]
11999            pub fn pwm_duty_h_2(&self) -> PwmDutyH2R {
12000                PwmDutyH2R::new((self.bits & 0xffff) as u16)
12001            }
12002        }
12003        impl W {
12004            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
12005            #[inline(always)]
12006            pub fn pwm_duty_h_2(&mut self) -> PwmDutyH2W<'_, PwmDutyH2Spec> {
12007                PwmDutyH2W::new(self, 0)
12008            }
12009        }
12010        #[doc = "PWM2 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12011        pub struct PwmDutyH2Spec;
12012        impl crate::RegisterSpec for PwmDutyH2Spec {
12013            type Ux = u32;
12014        }
12015        #[doc = "`read()` method returns [`pwm_duty_h2::R`](R) reader structure"]
12016        impl crate::Readable for PwmDutyH2Spec {}
12017        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h2::W`](W) writer structure"]
12018        impl crate::Writable for PwmDutyH2Spec {
12019            type Safety = crate::Unsafe;
12020        }
12021        #[doc = "`reset()` method sets PWM_DUTY_H2 to value 0"]
12022        impl crate::Resettable for PwmDutyH2Spec {}
12023    }
12024    #[doc = "PWM_PERIODLOAD_FLAG2 (rw) register accessor: PWM2 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag2`] module"]
12025    #[doc(alias = "PWM_PERIODLOAD_FLAG2")]
12026    pub type PwmPeriodloadFlag2 = crate::Reg<pwm_periodload_flag2::PwmPeriodloadFlag2Spec>;
12027    #[doc = "PWM2 period load flag"]
12028    pub mod pwm_periodload_flag2 {
12029        #[doc = "Register `PWM_PERIODLOAD_FLAG2` reader"]
12030        pub type R = crate::R<PwmPeriodloadFlag2Spec>;
12031        #[doc = "Register `PWM_PERIODLOAD_FLAG2` writer"]
12032        pub type W = crate::W<PwmPeriodloadFlag2Spec>;
12033        #[doc = "Field `pwm_periodload_flag_2` reader - Period load complete flag"]
12034        pub type PwmPeriodloadFlag2R = crate::BitReader;
12035        impl R {
12036            #[doc = "Bit 0 - Period load complete flag"]
12037            #[inline(always)]
12038            pub fn pwm_periodload_flag_2(&self) -> PwmPeriodloadFlag2R {
12039                PwmPeriodloadFlag2R::new((self.bits & 1) != 0)
12040            }
12041        }
12042        impl W {}
12043        #[doc = "PWM2 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12044        pub struct PwmPeriodloadFlag2Spec;
12045        impl crate::RegisterSpec for PwmPeriodloadFlag2Spec {
12046            type Ux = u32;
12047        }
12048        #[doc = "`read()` method returns [`pwm_periodload_flag2::R`](R) reader structure"]
12049        impl crate::Readable for PwmPeriodloadFlag2Spec {}
12050        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag2::W`](W) writer structure"]
12051        impl crate::Writable for PwmPeriodloadFlag2Spec {
12052            type Safety = crate::Unsafe;
12053        }
12054        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG2 to value 0"]
12055        impl crate::Resettable for PwmPeriodloadFlag2Spec {}
12056    }
12057    #[doc = "PWM_PERIOD_VAL2 (rw) register accessor: PWM2 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val2`] module"]
12058    #[doc(alias = "PWM_PERIOD_VAL2")]
12059    pub type PwmPeriodVal2 = crate::Reg<pwm_period_val2::PwmPeriodVal2Spec>;
12060    #[doc = "PWM2 pulse count value"]
12061    pub mod pwm_period_val2 {
12062        #[doc = "Register `PWM_PERIOD_VAL2` reader"]
12063        pub type R = crate::R<PwmPeriodVal2Spec>;
12064        #[doc = "Register `PWM_PERIOD_VAL2` writer"]
12065        pub type W = crate::W<PwmPeriodVal2Spec>;
12066        #[doc = "Field `pwm_period_val_2` reader - Pulse count for stepping mode"]
12067        pub type PwmPeriodVal2R = crate::FieldReader<u16>;
12068        #[doc = "Field `pwm_period_val_2` writer - Pulse count for stepping mode"]
12069        pub type PwmPeriodVal2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12070        impl R {
12071            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
12072            #[inline(always)]
12073            pub fn pwm_period_val_2(&self) -> PwmPeriodVal2R {
12074                PwmPeriodVal2R::new((self.bits & 0xffff) as u16)
12075            }
12076        }
12077        impl W {
12078            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
12079            #[inline(always)]
12080            pub fn pwm_period_val_2(&mut self) -> PwmPeriodVal2W<'_, PwmPeriodVal2Spec> {
12081                PwmPeriodVal2W::new(self, 0)
12082            }
12083        }
12084        #[doc = "PWM2 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12085        pub struct PwmPeriodVal2Spec;
12086        impl crate::RegisterSpec for PwmPeriodVal2Spec {
12087            type Ux = u32;
12088        }
12089        #[doc = "`read()` method returns [`pwm_period_val2::R`](R) reader structure"]
12090        impl crate::Readable for PwmPeriodVal2Spec {}
12091        #[doc = "`write(|w| ..)` method takes [`pwm_period_val2::W`](W) writer structure"]
12092        impl crate::Writable for PwmPeriodVal2Spec {
12093            type Safety = crate::Unsafe;
12094        }
12095        #[doc = "`reset()` method sets PWM_PERIOD_VAL2 to value 0"]
12096        impl crate::Resettable for PwmPeriodVal2Spec {}
12097    }
12098    #[doc = "PWM_PERIODCNT2 (rw) register accessor: PWM2 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt2`] module"]
12099    #[doc(alias = "PWM_PERIODCNT2")]
12100    pub type PwmPeriodcnt2 = crate::Reg<pwm_periodcnt2::PwmPeriodcnt2Spec>;
12101    #[doc = "PWM2 pulse count current value"]
12102    pub mod pwm_periodcnt2 {
12103        #[doc = "Register `PWM_PERIODCNT2` reader"]
12104        pub type R = crate::R<PwmPeriodcnt2Spec>;
12105        #[doc = "Register `PWM_PERIODCNT2` writer"]
12106        pub type W = crate::W<PwmPeriodcnt2Spec>;
12107        #[doc = "Field `pwm_periodcnt_2` reader - Current pulse count"]
12108        pub type PwmPeriodcnt2R = crate::FieldReader<u16>;
12109        impl R {
12110            #[doc = "Bits 0:15 - Current pulse count"]
12111            #[inline(always)]
12112            pub fn pwm_periodcnt_2(&self) -> PwmPeriodcnt2R {
12113                PwmPeriodcnt2R::new((self.bits & 0xffff) as u16)
12114            }
12115        }
12116        impl W {}
12117        #[doc = "PWM2 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12118        pub struct PwmPeriodcnt2Spec;
12119        impl crate::RegisterSpec for PwmPeriodcnt2Spec {
12120            type Ux = u32;
12121        }
12122        #[doc = "`read()` method returns [`pwm_periodcnt2::R`](R) reader structure"]
12123        impl crate::Readable for PwmPeriodcnt2Spec {}
12124        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt2::W`](W) writer structure"]
12125        impl crate::Writable for PwmPeriodcnt2Spec {
12126            type Safety = crate::Unsafe;
12127        }
12128        #[doc = "`reset()` method sets PWM_PERIODCNT2 to value 0"]
12129        impl crate::Resettable for PwmPeriodcnt2Spec {}
12130    }
12131    #[doc = "PWM_EN3 (rw) register accessor: PWM3 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en3`] module"]
12132    #[doc(alias = "PWM_EN3")]
12133    pub type PwmEn3 = crate::Reg<pwm_en3::PwmEn3Spec>;
12134    #[doc = "PWM3 enable"]
12135    pub mod pwm_en3 {
12136        #[doc = "Register `PWM_EN3` reader"]
12137        pub type R = crate::R<PwmEn3Spec>;
12138        #[doc = "Register `PWM_EN3` writer"]
12139        pub type W = crate::W<PwmEn3Spec>;
12140        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
12141        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
12142        pub enum PwmEn3 {
12143            #[doc = "0: PWM disabled, output low"]
12144            Off = 0,
12145            #[doc = "1: PWM enabled"]
12146            On = 1,
12147        }
12148        impl From<PwmEn3> for bool {
12149            #[inline(always)]
12150            fn from(variant: PwmEn3) -> Self {
12151                variant as u8 != 0
12152            }
12153        }
12154        #[doc = "Field `pwm_en_3` reader - PWM0 enable: 0=off; 1=on"]
12155        pub type PwmEn3R = crate::BitReader<PwmEn3>;
12156        impl PwmEn3R {
12157            #[doc = "Get enumerated values variant"]
12158            #[inline(always)]
12159            pub const fn variant(&self) -> PwmEn3 {
12160                match self.bits {
12161                    false => PwmEn3::Off,
12162                    true => PwmEn3::On,
12163                }
12164            }
12165            #[doc = "PWM disabled, output low"]
12166            #[inline(always)]
12167            pub fn is_off(&self) -> bool {
12168                *self == PwmEn3::Off
12169            }
12170            #[doc = "PWM enabled"]
12171            #[inline(always)]
12172            pub fn is_on(&self) -> bool {
12173                *self == PwmEn3::On
12174            }
12175        }
12176        #[doc = "Field `pwm_en_3` writer - PWM0 enable: 0=off; 1=on"]
12177        pub type PwmEn3W<'a, REG> = crate::BitWriter<'a, REG, PwmEn3>;
12178        impl<'a, REG> PwmEn3W<'a, REG>
12179        where
12180            REG: crate::Writable + crate::RegisterSpec,
12181        {
12182            #[doc = "PWM disabled, output low"]
12183            #[inline(always)]
12184            pub fn off(self) -> &'a mut crate::W<REG> {
12185                self.variant(PwmEn3::Off)
12186            }
12187            #[doc = "PWM enabled"]
12188            #[inline(always)]
12189            pub fn on(self) -> &'a mut crate::W<REG> {
12190                self.variant(PwmEn3::On)
12191            }
12192        }
12193        impl R {
12194            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
12195            #[inline(always)]
12196            pub fn pwm_en_3(&self) -> PwmEn3R {
12197                PwmEn3R::new((self.bits & 1) != 0)
12198            }
12199        }
12200        impl W {
12201            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
12202            #[inline(always)]
12203            pub fn pwm_en_3(&mut self) -> PwmEn3W<'_, PwmEn3Spec> {
12204                PwmEn3W::new(self, 0)
12205            }
12206        }
12207        #[doc = "PWM3 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12208        pub struct PwmEn3Spec;
12209        impl crate::RegisterSpec for PwmEn3Spec {
12210            type Ux = u32;
12211        }
12212        #[doc = "`read()` method returns [`pwm_en3::R`](R) reader structure"]
12213        impl crate::Readable for PwmEn3Spec {}
12214        #[doc = "`write(|w| ..)` method takes [`pwm_en3::W`](W) writer structure"]
12215        impl crate::Writable for PwmEn3Spec {
12216            type Safety = crate::Unsafe;
12217        }
12218        #[doc = "`reset()` method sets PWM_EN3 to value 0"]
12219        impl crate::Resettable for PwmEn3Spec {}
12220    }
12221    #[doc = "PWM_PORTITY3 (rw) register accessor: PWM3 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity3`] module"]
12222    #[doc(alias = "PWM_PORTITY3")]
12223    pub type PwmPortity3 = crate::Reg<pwm_portity3::PwmPortity3Spec>;
12224    #[doc = "PWM3 polarity"]
12225    pub mod pwm_portity3 {
12226        #[doc = "Register `PWM_PORTITY3` reader"]
12227        pub type R = crate::R<PwmPortity3Spec>;
12228        #[doc = "Register `PWM_PORTITY3` writer"]
12229        pub type W = crate::W<PwmPortity3Spec>;
12230        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
12231        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
12232        pub enum PwmPoarity3 {
12233            #[doc = "0: Normal polarity"]
12234            Normal = 0,
12235            #[doc = "1: Inverted polarity"]
12236            Inverted = 1,
12237        }
12238        impl From<PwmPoarity3> for bool {
12239            #[inline(always)]
12240            fn from(variant: PwmPoarity3) -> Self {
12241                variant as u8 != 0
12242            }
12243        }
12244        #[doc = "Field `pwm_poarity_3` reader - PWM0 polarity: 0=normal; 1=inverted"]
12245        pub type PwmPoarity3R = crate::BitReader<PwmPoarity3>;
12246        impl PwmPoarity3R {
12247            #[doc = "Get enumerated values variant"]
12248            #[inline(always)]
12249            pub const fn variant(&self) -> PwmPoarity3 {
12250                match self.bits {
12251                    false => PwmPoarity3::Normal,
12252                    true => PwmPoarity3::Inverted,
12253                }
12254            }
12255            #[doc = "Normal polarity"]
12256            #[inline(always)]
12257            pub fn is_normal(&self) -> bool {
12258                *self == PwmPoarity3::Normal
12259            }
12260            #[doc = "Inverted polarity"]
12261            #[inline(always)]
12262            pub fn is_inverted(&self) -> bool {
12263                *self == PwmPoarity3::Inverted
12264            }
12265        }
12266        #[doc = "Field `pwm_poarity_3` writer - PWM0 polarity: 0=normal; 1=inverted"]
12267        pub type PwmPoarity3W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity3>;
12268        impl<'a, REG> PwmPoarity3W<'a, REG>
12269        where
12270            REG: crate::Writable + crate::RegisterSpec,
12271        {
12272            #[doc = "Normal polarity"]
12273            #[inline(always)]
12274            pub fn normal(self) -> &'a mut crate::W<REG> {
12275                self.variant(PwmPoarity3::Normal)
12276            }
12277            #[doc = "Inverted polarity"]
12278            #[inline(always)]
12279            pub fn inverted(self) -> &'a mut crate::W<REG> {
12280                self.variant(PwmPoarity3::Inverted)
12281            }
12282        }
12283        impl R {
12284            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
12285            #[inline(always)]
12286            pub fn pwm_poarity_3(&self) -> PwmPoarity3R {
12287                PwmPoarity3R::new((self.bits & 1) != 0)
12288            }
12289        }
12290        impl W {
12291            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
12292            #[inline(always)]
12293            pub fn pwm_poarity_3(&mut self) -> PwmPoarity3W<'_, PwmPortity3Spec> {
12294                PwmPoarity3W::new(self, 0)
12295            }
12296        }
12297        #[doc = "PWM3 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12298        pub struct PwmPortity3Spec;
12299        impl crate::RegisterSpec for PwmPortity3Spec {
12300            type Ux = u32;
12301        }
12302        #[doc = "`read()` method returns [`pwm_portity3::R`](R) reader structure"]
12303        impl crate::Readable for PwmPortity3Spec {}
12304        #[doc = "`write(|w| ..)` method takes [`pwm_portity3::W`](W) writer structure"]
12305        impl crate::Writable for PwmPortity3Spec {
12306            type Safety = crate::Unsafe;
12307        }
12308        #[doc = "`reset()` method sets PWM_PORTITY3 to value 0"]
12309        impl crate::Resettable for PwmPortity3Spec {}
12310    }
12311    #[doc = "PWM_OEN_CFG3 (rw) register accessor: PWM3 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg3`] module"]
12312    #[doc(alias = "PWM_OEN_CFG3")]
12313    pub type PwmOenCfg3 = crate::Reg<pwm_oen_cfg3::PwmOenCfg3Spec>;
12314    #[doc = "PWM3 high-impedance config"]
12315    pub mod pwm_oen_cfg3 {
12316        #[doc = "Register `PWM_OEN_CFG3` reader"]
12317        pub type R = crate::R<PwmOenCfg3Spec>;
12318        #[doc = "Register `PWM_OEN_CFG3` writer"]
12319        pub type W = crate::W<PwmOenCfg3Spec>;
12320        #[doc = "Field `pwm_oen_cfg_3` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12321        pub type PwmOenCfg3R = crate::BitReader;
12322        #[doc = "Field `pwm_oen_cfg_3` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12323        pub type PwmOenCfg3W<'a, REG> = crate::BitWriter<'a, REG>;
12324        impl R {
12325            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12326            #[inline(always)]
12327            pub fn pwm_oen_cfg_3(&self) -> PwmOenCfg3R {
12328                PwmOenCfg3R::new((self.bits & 1) != 0)
12329            }
12330        }
12331        impl W {
12332            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12333            #[inline(always)]
12334            pub fn pwm_oen_cfg_3(&mut self) -> PwmOenCfg3W<'_, PwmOenCfg3Spec> {
12335                PwmOenCfg3W::new(self, 0)
12336            }
12337        }
12338        #[doc = "PWM3 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12339        pub struct PwmOenCfg3Spec;
12340        impl crate::RegisterSpec for PwmOenCfg3Spec {
12341            type Ux = u32;
12342        }
12343        #[doc = "`read()` method returns [`pwm_oen_cfg3::R`](R) reader structure"]
12344        impl crate::Readable for PwmOenCfg3Spec {}
12345        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg3::W`](W) writer structure"]
12346        impl crate::Writable for PwmOenCfg3Spec {
12347            type Safety = crate::Unsafe;
12348        }
12349        #[doc = "`reset()` method sets PWM_OEN_CFG3 to value 0"]
12350        impl crate::Resettable for PwmOenCfg3Spec {}
12351    }
12352    #[doc = "PWM_OFFSET_L3 (rw) register accessor: PWM3 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l3`] module"]
12353    #[doc(alias = "PWM_OFFSET_L3")]
12354    pub type PwmOffsetL3 = crate::Reg<pwm_offset_l3::PwmOffsetL3Spec>;
12355    #[doc = "PWM3 phase offset low 16 bits"]
12356    pub mod pwm_offset_l3 {
12357        #[doc = "Register `PWM_OFFSET_L3` reader"]
12358        pub type R = crate::R<PwmOffsetL3Spec>;
12359        #[doc = "Register `PWM_OFFSET_L3` writer"]
12360        pub type W = crate::W<PwmOffsetL3Spec>;
12361        #[doc = "Field `pwm_offset_l_3` reader - PWM0 phase offset low 16 bits"]
12362        pub type PwmOffsetL3R = crate::FieldReader<u16>;
12363        #[doc = "Field `pwm_offset_l_3` writer - PWM0 phase offset low 16 bits"]
12364        pub type PwmOffsetL3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12365        impl R {
12366            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
12367            #[inline(always)]
12368            pub fn pwm_offset_l_3(&self) -> PwmOffsetL3R {
12369                PwmOffsetL3R::new((self.bits & 0xffff) as u16)
12370            }
12371        }
12372        impl W {
12373            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
12374            #[inline(always)]
12375            pub fn pwm_offset_l_3(&mut self) -> PwmOffsetL3W<'_, PwmOffsetL3Spec> {
12376                PwmOffsetL3W::new(self, 0)
12377            }
12378        }
12379        #[doc = "PWM3 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12380        pub struct PwmOffsetL3Spec;
12381        impl crate::RegisterSpec for PwmOffsetL3Spec {
12382            type Ux = u32;
12383        }
12384        #[doc = "`read()` method returns [`pwm_offset_l3::R`](R) reader structure"]
12385        impl crate::Readable for PwmOffsetL3Spec {}
12386        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l3::W`](W) writer structure"]
12387        impl crate::Writable for PwmOffsetL3Spec {
12388            type Safety = crate::Unsafe;
12389        }
12390        #[doc = "`reset()` method sets PWM_OFFSET_L3 to value 0"]
12391        impl crate::Resettable for PwmOffsetL3Spec {}
12392    }
12393    #[doc = "PWM_OFFSET_H3 (rw) register accessor: PWM3 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h3`] module"]
12394    #[doc(alias = "PWM_OFFSET_H3")]
12395    pub type PwmOffsetH3 = crate::Reg<pwm_offset_h3::PwmOffsetH3Spec>;
12396    #[doc = "PWM3 phase offset high 16 bits"]
12397    pub mod pwm_offset_h3 {
12398        #[doc = "Register `PWM_OFFSET_H3` reader"]
12399        pub type R = crate::R<PwmOffsetH3Spec>;
12400        #[doc = "Register `PWM_OFFSET_H3` writer"]
12401        pub type W = crate::W<PwmOffsetH3Spec>;
12402        #[doc = "Field `pwm_offset_h_3` reader - PWM0 phase offset high 16 bits"]
12403        pub type PwmOffsetH3R = crate::FieldReader<u16>;
12404        #[doc = "Field `pwm_offset_h_3` writer - PWM0 phase offset high 16 bits"]
12405        pub type PwmOffsetH3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12406        impl R {
12407            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
12408            #[inline(always)]
12409            pub fn pwm_offset_h_3(&self) -> PwmOffsetH3R {
12410                PwmOffsetH3R::new((self.bits & 0xffff) as u16)
12411            }
12412        }
12413        impl W {
12414            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
12415            #[inline(always)]
12416            pub fn pwm_offset_h_3(&mut self) -> PwmOffsetH3W<'_, PwmOffsetH3Spec> {
12417                PwmOffsetH3W::new(self, 0)
12418            }
12419        }
12420        #[doc = "PWM3 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12421        pub struct PwmOffsetH3Spec;
12422        impl crate::RegisterSpec for PwmOffsetH3Spec {
12423            type Ux = u32;
12424        }
12425        #[doc = "`read()` method returns [`pwm_offset_h3::R`](R) reader structure"]
12426        impl crate::Readable for PwmOffsetH3Spec {}
12427        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h3::W`](W) writer structure"]
12428        impl crate::Writable for PwmOffsetH3Spec {
12429            type Safety = crate::Unsafe;
12430        }
12431        #[doc = "`reset()` method sets PWM_OFFSET_H3 to value 0"]
12432        impl crate::Resettable for PwmOffsetH3Spec {}
12433    }
12434    #[doc = "PWM_FREQ_L3 (rw) register accessor: PWM3 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l3`] module"]
12435    #[doc(alias = "PWM_FREQ_L3")]
12436    pub type PwmFreqL3 = crate::Reg<pwm_freq_l3::PwmFreqL3Spec>;
12437    #[doc = "PWM3 frequency low 16 bits"]
12438    pub mod pwm_freq_l3 {
12439        #[doc = "Register `PWM_FREQ_L3` reader"]
12440        pub type R = crate::R<PwmFreqL3Spec>;
12441        #[doc = "Register `PWM_FREQ_L3` writer"]
12442        pub type W = crate::W<PwmFreqL3Spec>;
12443        #[doc = "Field `pwm_freq_l_3` reader - PWM0 clock divider low 16 bits"]
12444        pub type PwmFreqL3R = crate::FieldReader<u16>;
12445        #[doc = "Field `pwm_freq_l_3` writer - PWM0 clock divider low 16 bits"]
12446        pub type PwmFreqL3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12447        impl R {
12448            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
12449            #[inline(always)]
12450            pub fn pwm_freq_l_3(&self) -> PwmFreqL3R {
12451                PwmFreqL3R::new((self.bits & 0xffff) as u16)
12452            }
12453        }
12454        impl W {
12455            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
12456            #[inline(always)]
12457            pub fn pwm_freq_l_3(&mut self) -> PwmFreqL3W<'_, PwmFreqL3Spec> {
12458                PwmFreqL3W::new(self, 0)
12459            }
12460        }
12461        #[doc = "PWM3 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12462        pub struct PwmFreqL3Spec;
12463        impl crate::RegisterSpec for PwmFreqL3Spec {
12464            type Ux = u32;
12465        }
12466        #[doc = "`read()` method returns [`pwm_freq_l3::R`](R) reader structure"]
12467        impl crate::Readable for PwmFreqL3Spec {}
12468        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l3::W`](W) writer structure"]
12469        impl crate::Writable for PwmFreqL3Spec {
12470            type Safety = crate::Unsafe;
12471        }
12472        #[doc = "`reset()` method sets PWM_FREQ_L3 to value 0"]
12473        impl crate::Resettable for PwmFreqL3Spec {}
12474    }
12475    #[doc = "PWM_FREQ_H3 (rw) register accessor: PWM3 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h3`] module"]
12476    #[doc(alias = "PWM_FREQ_H3")]
12477    pub type PwmFreqH3 = crate::Reg<pwm_freq_h3::PwmFreqH3Spec>;
12478    #[doc = "PWM3 frequency high 16 bits"]
12479    pub mod pwm_freq_h3 {
12480        #[doc = "Register `PWM_FREQ_H3` reader"]
12481        pub type R = crate::R<PwmFreqH3Spec>;
12482        #[doc = "Register `PWM_FREQ_H3` writer"]
12483        pub type W = crate::W<PwmFreqH3Spec>;
12484        #[doc = "Field `pwm_freq_h_3` reader - PWM0 clock divider high 16 bits"]
12485        pub type PwmFreqH3R = crate::FieldReader<u16>;
12486        #[doc = "Field `pwm_freq_h_3` writer - PWM0 clock divider high 16 bits"]
12487        pub type PwmFreqH3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12488        impl R {
12489            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
12490            #[inline(always)]
12491            pub fn pwm_freq_h_3(&self) -> PwmFreqH3R {
12492                PwmFreqH3R::new((self.bits & 0xffff) as u16)
12493            }
12494        }
12495        impl W {
12496            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
12497            #[inline(always)]
12498            pub fn pwm_freq_h_3(&mut self) -> PwmFreqH3W<'_, PwmFreqH3Spec> {
12499                PwmFreqH3W::new(self, 0)
12500            }
12501        }
12502        #[doc = "PWM3 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12503        pub struct PwmFreqH3Spec;
12504        impl crate::RegisterSpec for PwmFreqH3Spec {
12505            type Ux = u32;
12506        }
12507        #[doc = "`read()` method returns [`pwm_freq_h3::R`](R) reader structure"]
12508        impl crate::Readable for PwmFreqH3Spec {}
12509        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h3::W`](W) writer structure"]
12510        impl crate::Writable for PwmFreqH3Spec {
12511            type Safety = crate::Unsafe;
12512        }
12513        #[doc = "`reset()` method sets PWM_FREQ_H3 to value 0"]
12514        impl crate::Resettable for PwmFreqH3Spec {}
12515    }
12516    #[doc = "PWM_DUTY_L3 (rw) register accessor: PWM3 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l3`] module"]
12517    #[doc(alias = "PWM_DUTY_L3")]
12518    pub type PwmDutyL3 = crate::Reg<pwm_duty_l3::PwmDutyL3Spec>;
12519    #[doc = "PWM3 duty cycle low 16 bits"]
12520    pub mod pwm_duty_l3 {
12521        #[doc = "Register `PWM_DUTY_L3` reader"]
12522        pub type R = crate::R<PwmDutyL3Spec>;
12523        #[doc = "Register `PWM_DUTY_L3` writer"]
12524        pub type W = crate::W<PwmDutyL3Spec>;
12525        #[doc = "Field `pwm_duty_l_3` reader - PWM0 duty cycle low 16 bits"]
12526        pub type PwmDutyL3R = crate::FieldReader<u16>;
12527        #[doc = "Field `pwm_duty_l_3` writer - PWM0 duty cycle low 16 bits"]
12528        pub type PwmDutyL3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12529        impl R {
12530            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
12531            #[inline(always)]
12532            pub fn pwm_duty_l_3(&self) -> PwmDutyL3R {
12533                PwmDutyL3R::new((self.bits & 0xffff) as u16)
12534            }
12535        }
12536        impl W {
12537            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
12538            #[inline(always)]
12539            pub fn pwm_duty_l_3(&mut self) -> PwmDutyL3W<'_, PwmDutyL3Spec> {
12540                PwmDutyL3W::new(self, 0)
12541            }
12542        }
12543        #[doc = "PWM3 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12544        pub struct PwmDutyL3Spec;
12545        impl crate::RegisterSpec for PwmDutyL3Spec {
12546            type Ux = u32;
12547        }
12548        #[doc = "`read()` method returns [`pwm_duty_l3::R`](R) reader structure"]
12549        impl crate::Readable for PwmDutyL3Spec {}
12550        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l3::W`](W) writer structure"]
12551        impl crate::Writable for PwmDutyL3Spec {
12552            type Safety = crate::Unsafe;
12553        }
12554        #[doc = "`reset()` method sets PWM_DUTY_L3 to value 0"]
12555        impl crate::Resettable for PwmDutyL3Spec {}
12556    }
12557    #[doc = "PWM_DUTY_H3 (rw) register accessor: PWM3 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h3`] module"]
12558    #[doc(alias = "PWM_DUTY_H3")]
12559    pub type PwmDutyH3 = crate::Reg<pwm_duty_h3::PwmDutyH3Spec>;
12560    #[doc = "PWM3 duty cycle high 16 bits"]
12561    pub mod pwm_duty_h3 {
12562        #[doc = "Register `PWM_DUTY_H3` reader"]
12563        pub type R = crate::R<PwmDutyH3Spec>;
12564        #[doc = "Register `PWM_DUTY_H3` writer"]
12565        pub type W = crate::W<PwmDutyH3Spec>;
12566        #[doc = "Field `pwm_duty_h_3` reader - PWM0 duty cycle high 16 bits"]
12567        pub type PwmDutyH3R = crate::FieldReader<u16>;
12568        #[doc = "Field `pwm_duty_h_3` writer - PWM0 duty cycle high 16 bits"]
12569        pub type PwmDutyH3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12570        impl R {
12571            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
12572            #[inline(always)]
12573            pub fn pwm_duty_h_3(&self) -> PwmDutyH3R {
12574                PwmDutyH3R::new((self.bits & 0xffff) as u16)
12575            }
12576        }
12577        impl W {
12578            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
12579            #[inline(always)]
12580            pub fn pwm_duty_h_3(&mut self) -> PwmDutyH3W<'_, PwmDutyH3Spec> {
12581                PwmDutyH3W::new(self, 0)
12582            }
12583        }
12584        #[doc = "PWM3 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12585        pub struct PwmDutyH3Spec;
12586        impl crate::RegisterSpec for PwmDutyH3Spec {
12587            type Ux = u32;
12588        }
12589        #[doc = "`read()` method returns [`pwm_duty_h3::R`](R) reader structure"]
12590        impl crate::Readable for PwmDutyH3Spec {}
12591        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h3::W`](W) writer structure"]
12592        impl crate::Writable for PwmDutyH3Spec {
12593            type Safety = crate::Unsafe;
12594        }
12595        #[doc = "`reset()` method sets PWM_DUTY_H3 to value 0"]
12596        impl crate::Resettable for PwmDutyH3Spec {}
12597    }
12598    #[doc = "PWM_PERIODLOAD_FLAG3 (rw) register accessor: PWM3 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag3`] module"]
12599    #[doc(alias = "PWM_PERIODLOAD_FLAG3")]
12600    pub type PwmPeriodloadFlag3 = crate::Reg<pwm_periodload_flag3::PwmPeriodloadFlag3Spec>;
12601    #[doc = "PWM3 period load flag"]
12602    pub mod pwm_periodload_flag3 {
12603        #[doc = "Register `PWM_PERIODLOAD_FLAG3` reader"]
12604        pub type R = crate::R<PwmPeriodloadFlag3Spec>;
12605        #[doc = "Register `PWM_PERIODLOAD_FLAG3` writer"]
12606        pub type W = crate::W<PwmPeriodloadFlag3Spec>;
12607        #[doc = "Field `pwm_periodload_flag_3` reader - Period load complete flag"]
12608        pub type PwmPeriodloadFlag3R = crate::BitReader;
12609        impl R {
12610            #[doc = "Bit 0 - Period load complete flag"]
12611            #[inline(always)]
12612            pub fn pwm_periodload_flag_3(&self) -> PwmPeriodloadFlag3R {
12613                PwmPeriodloadFlag3R::new((self.bits & 1) != 0)
12614            }
12615        }
12616        impl W {}
12617        #[doc = "PWM3 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12618        pub struct PwmPeriodloadFlag3Spec;
12619        impl crate::RegisterSpec for PwmPeriodloadFlag3Spec {
12620            type Ux = u32;
12621        }
12622        #[doc = "`read()` method returns [`pwm_periodload_flag3::R`](R) reader structure"]
12623        impl crate::Readable for PwmPeriodloadFlag3Spec {}
12624        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag3::W`](W) writer structure"]
12625        impl crate::Writable for PwmPeriodloadFlag3Spec {
12626            type Safety = crate::Unsafe;
12627        }
12628        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG3 to value 0"]
12629        impl crate::Resettable for PwmPeriodloadFlag3Spec {}
12630    }
12631    #[doc = "PWM_PERIOD_VAL3 (rw) register accessor: PWM3 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val3`] module"]
12632    #[doc(alias = "PWM_PERIOD_VAL3")]
12633    pub type PwmPeriodVal3 = crate::Reg<pwm_period_val3::PwmPeriodVal3Spec>;
12634    #[doc = "PWM3 pulse count value"]
12635    pub mod pwm_period_val3 {
12636        #[doc = "Register `PWM_PERIOD_VAL3` reader"]
12637        pub type R = crate::R<PwmPeriodVal3Spec>;
12638        #[doc = "Register `PWM_PERIOD_VAL3` writer"]
12639        pub type W = crate::W<PwmPeriodVal3Spec>;
12640        #[doc = "Field `pwm_period_val_3` reader - Pulse count for stepping mode"]
12641        pub type PwmPeriodVal3R = crate::FieldReader<u16>;
12642        #[doc = "Field `pwm_period_val_3` writer - Pulse count for stepping mode"]
12643        pub type PwmPeriodVal3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12644        impl R {
12645            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
12646            #[inline(always)]
12647            pub fn pwm_period_val_3(&self) -> PwmPeriodVal3R {
12648                PwmPeriodVal3R::new((self.bits & 0xffff) as u16)
12649            }
12650        }
12651        impl W {
12652            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
12653            #[inline(always)]
12654            pub fn pwm_period_val_3(&mut self) -> PwmPeriodVal3W<'_, PwmPeriodVal3Spec> {
12655                PwmPeriodVal3W::new(self, 0)
12656            }
12657        }
12658        #[doc = "PWM3 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12659        pub struct PwmPeriodVal3Spec;
12660        impl crate::RegisterSpec for PwmPeriodVal3Spec {
12661            type Ux = u32;
12662        }
12663        #[doc = "`read()` method returns [`pwm_period_val3::R`](R) reader structure"]
12664        impl crate::Readable for PwmPeriodVal3Spec {}
12665        #[doc = "`write(|w| ..)` method takes [`pwm_period_val3::W`](W) writer structure"]
12666        impl crate::Writable for PwmPeriodVal3Spec {
12667            type Safety = crate::Unsafe;
12668        }
12669        #[doc = "`reset()` method sets PWM_PERIOD_VAL3 to value 0"]
12670        impl crate::Resettable for PwmPeriodVal3Spec {}
12671    }
12672    #[doc = "PWM_PERIODCNT3 (rw) register accessor: PWM3 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt3`] module"]
12673    #[doc(alias = "PWM_PERIODCNT3")]
12674    pub type PwmPeriodcnt3 = crate::Reg<pwm_periodcnt3::PwmPeriodcnt3Spec>;
12675    #[doc = "PWM3 pulse count current value"]
12676    pub mod pwm_periodcnt3 {
12677        #[doc = "Register `PWM_PERIODCNT3` reader"]
12678        pub type R = crate::R<PwmPeriodcnt3Spec>;
12679        #[doc = "Register `PWM_PERIODCNT3` writer"]
12680        pub type W = crate::W<PwmPeriodcnt3Spec>;
12681        #[doc = "Field `pwm_periodcnt_3` reader - Current pulse count"]
12682        pub type PwmPeriodcnt3R = crate::FieldReader<u16>;
12683        impl R {
12684            #[doc = "Bits 0:15 - Current pulse count"]
12685            #[inline(always)]
12686            pub fn pwm_periodcnt_3(&self) -> PwmPeriodcnt3R {
12687                PwmPeriodcnt3R::new((self.bits & 0xffff) as u16)
12688            }
12689        }
12690        impl W {}
12691        #[doc = "PWM3 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12692        pub struct PwmPeriodcnt3Spec;
12693        impl crate::RegisterSpec for PwmPeriodcnt3Spec {
12694            type Ux = u32;
12695        }
12696        #[doc = "`read()` method returns [`pwm_periodcnt3::R`](R) reader structure"]
12697        impl crate::Readable for PwmPeriodcnt3Spec {}
12698        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt3::W`](W) writer structure"]
12699        impl crate::Writable for PwmPeriodcnt3Spec {
12700            type Safety = crate::Unsafe;
12701        }
12702        #[doc = "`reset()` method sets PWM_PERIODCNT3 to value 0"]
12703        impl crate::Resettable for PwmPeriodcnt3Spec {}
12704    }
12705    #[doc = "PWM_EN4 (rw) register accessor: PWM4 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en4`] module"]
12706    #[doc(alias = "PWM_EN4")]
12707    pub type PwmEn4 = crate::Reg<pwm_en4::PwmEn4Spec>;
12708    #[doc = "PWM4 enable"]
12709    pub mod pwm_en4 {
12710        #[doc = "Register `PWM_EN4` reader"]
12711        pub type R = crate::R<PwmEn4Spec>;
12712        #[doc = "Register `PWM_EN4` writer"]
12713        pub type W = crate::W<PwmEn4Spec>;
12714        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
12715        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
12716        pub enum PwmEn4 {
12717            #[doc = "0: PWM disabled, output low"]
12718            Off = 0,
12719            #[doc = "1: PWM enabled"]
12720            On = 1,
12721        }
12722        impl From<PwmEn4> for bool {
12723            #[inline(always)]
12724            fn from(variant: PwmEn4) -> Self {
12725                variant as u8 != 0
12726            }
12727        }
12728        #[doc = "Field `pwm_en_4` reader - PWM0 enable: 0=off; 1=on"]
12729        pub type PwmEn4R = crate::BitReader<PwmEn4>;
12730        impl PwmEn4R {
12731            #[doc = "Get enumerated values variant"]
12732            #[inline(always)]
12733            pub const fn variant(&self) -> PwmEn4 {
12734                match self.bits {
12735                    false => PwmEn4::Off,
12736                    true => PwmEn4::On,
12737                }
12738            }
12739            #[doc = "PWM disabled, output low"]
12740            #[inline(always)]
12741            pub fn is_off(&self) -> bool {
12742                *self == PwmEn4::Off
12743            }
12744            #[doc = "PWM enabled"]
12745            #[inline(always)]
12746            pub fn is_on(&self) -> bool {
12747                *self == PwmEn4::On
12748            }
12749        }
12750        #[doc = "Field `pwm_en_4` writer - PWM0 enable: 0=off; 1=on"]
12751        pub type PwmEn4W<'a, REG> = crate::BitWriter<'a, REG, PwmEn4>;
12752        impl<'a, REG> PwmEn4W<'a, REG>
12753        where
12754            REG: crate::Writable + crate::RegisterSpec,
12755        {
12756            #[doc = "PWM disabled, output low"]
12757            #[inline(always)]
12758            pub fn off(self) -> &'a mut crate::W<REG> {
12759                self.variant(PwmEn4::Off)
12760            }
12761            #[doc = "PWM enabled"]
12762            #[inline(always)]
12763            pub fn on(self) -> &'a mut crate::W<REG> {
12764                self.variant(PwmEn4::On)
12765            }
12766        }
12767        impl R {
12768            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
12769            #[inline(always)]
12770            pub fn pwm_en_4(&self) -> PwmEn4R {
12771                PwmEn4R::new((self.bits & 1) != 0)
12772            }
12773        }
12774        impl W {
12775            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
12776            #[inline(always)]
12777            pub fn pwm_en_4(&mut self) -> PwmEn4W<'_, PwmEn4Spec> {
12778                PwmEn4W::new(self, 0)
12779            }
12780        }
12781        #[doc = "PWM4 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12782        pub struct PwmEn4Spec;
12783        impl crate::RegisterSpec for PwmEn4Spec {
12784            type Ux = u32;
12785        }
12786        #[doc = "`read()` method returns [`pwm_en4::R`](R) reader structure"]
12787        impl crate::Readable for PwmEn4Spec {}
12788        #[doc = "`write(|w| ..)` method takes [`pwm_en4::W`](W) writer structure"]
12789        impl crate::Writable for PwmEn4Spec {
12790            type Safety = crate::Unsafe;
12791        }
12792        #[doc = "`reset()` method sets PWM_EN4 to value 0"]
12793        impl crate::Resettable for PwmEn4Spec {}
12794    }
12795    #[doc = "PWM_PORTITY4 (rw) register accessor: PWM4 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity4`] module"]
12796    #[doc(alias = "PWM_PORTITY4")]
12797    pub type PwmPortity4 = crate::Reg<pwm_portity4::PwmPortity4Spec>;
12798    #[doc = "PWM4 polarity"]
12799    pub mod pwm_portity4 {
12800        #[doc = "Register `PWM_PORTITY4` reader"]
12801        pub type R = crate::R<PwmPortity4Spec>;
12802        #[doc = "Register `PWM_PORTITY4` writer"]
12803        pub type W = crate::W<PwmPortity4Spec>;
12804        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
12805        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
12806        pub enum PwmPoarity4 {
12807            #[doc = "0: Normal polarity"]
12808            Normal = 0,
12809            #[doc = "1: Inverted polarity"]
12810            Inverted = 1,
12811        }
12812        impl From<PwmPoarity4> for bool {
12813            #[inline(always)]
12814            fn from(variant: PwmPoarity4) -> Self {
12815                variant as u8 != 0
12816            }
12817        }
12818        #[doc = "Field `pwm_poarity_4` reader - PWM0 polarity: 0=normal; 1=inverted"]
12819        pub type PwmPoarity4R = crate::BitReader<PwmPoarity4>;
12820        impl PwmPoarity4R {
12821            #[doc = "Get enumerated values variant"]
12822            #[inline(always)]
12823            pub const fn variant(&self) -> PwmPoarity4 {
12824                match self.bits {
12825                    false => PwmPoarity4::Normal,
12826                    true => PwmPoarity4::Inverted,
12827                }
12828            }
12829            #[doc = "Normal polarity"]
12830            #[inline(always)]
12831            pub fn is_normal(&self) -> bool {
12832                *self == PwmPoarity4::Normal
12833            }
12834            #[doc = "Inverted polarity"]
12835            #[inline(always)]
12836            pub fn is_inverted(&self) -> bool {
12837                *self == PwmPoarity4::Inverted
12838            }
12839        }
12840        #[doc = "Field `pwm_poarity_4` writer - PWM0 polarity: 0=normal; 1=inverted"]
12841        pub type PwmPoarity4W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity4>;
12842        impl<'a, REG> PwmPoarity4W<'a, REG>
12843        where
12844            REG: crate::Writable + crate::RegisterSpec,
12845        {
12846            #[doc = "Normal polarity"]
12847            #[inline(always)]
12848            pub fn normal(self) -> &'a mut crate::W<REG> {
12849                self.variant(PwmPoarity4::Normal)
12850            }
12851            #[doc = "Inverted polarity"]
12852            #[inline(always)]
12853            pub fn inverted(self) -> &'a mut crate::W<REG> {
12854                self.variant(PwmPoarity4::Inverted)
12855            }
12856        }
12857        impl R {
12858            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
12859            #[inline(always)]
12860            pub fn pwm_poarity_4(&self) -> PwmPoarity4R {
12861                PwmPoarity4R::new((self.bits & 1) != 0)
12862            }
12863        }
12864        impl W {
12865            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
12866            #[inline(always)]
12867            pub fn pwm_poarity_4(&mut self) -> PwmPoarity4W<'_, PwmPortity4Spec> {
12868                PwmPoarity4W::new(self, 0)
12869            }
12870        }
12871        #[doc = "PWM4 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12872        pub struct PwmPortity4Spec;
12873        impl crate::RegisterSpec for PwmPortity4Spec {
12874            type Ux = u32;
12875        }
12876        #[doc = "`read()` method returns [`pwm_portity4::R`](R) reader structure"]
12877        impl crate::Readable for PwmPortity4Spec {}
12878        #[doc = "`write(|w| ..)` method takes [`pwm_portity4::W`](W) writer structure"]
12879        impl crate::Writable for PwmPortity4Spec {
12880            type Safety = crate::Unsafe;
12881        }
12882        #[doc = "`reset()` method sets PWM_PORTITY4 to value 0"]
12883        impl crate::Resettable for PwmPortity4Spec {}
12884    }
12885    #[doc = "PWM_OEN_CFG4 (rw) register accessor: PWM4 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg4`] module"]
12886    #[doc(alias = "PWM_OEN_CFG4")]
12887    pub type PwmOenCfg4 = crate::Reg<pwm_oen_cfg4::PwmOenCfg4Spec>;
12888    #[doc = "PWM4 high-impedance config"]
12889    pub mod pwm_oen_cfg4 {
12890        #[doc = "Register `PWM_OEN_CFG4` reader"]
12891        pub type R = crate::R<PwmOenCfg4Spec>;
12892        #[doc = "Register `PWM_OEN_CFG4` writer"]
12893        pub type W = crate::W<PwmOenCfg4Spec>;
12894        #[doc = "Field `pwm_oen_cfg_4` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12895        pub type PwmOenCfg4R = crate::BitReader;
12896        #[doc = "Field `pwm_oen_cfg_4` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12897        pub type PwmOenCfg4W<'a, REG> = crate::BitWriter<'a, REG>;
12898        impl R {
12899            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12900            #[inline(always)]
12901            pub fn pwm_oen_cfg_4(&self) -> PwmOenCfg4R {
12902                PwmOenCfg4R::new((self.bits & 1) != 0)
12903            }
12904        }
12905        impl W {
12906            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12907            #[inline(always)]
12908            pub fn pwm_oen_cfg_4(&mut self) -> PwmOenCfg4W<'_, PwmOenCfg4Spec> {
12909                PwmOenCfg4W::new(self, 0)
12910            }
12911        }
12912        #[doc = "PWM4 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12913        pub struct PwmOenCfg4Spec;
12914        impl crate::RegisterSpec for PwmOenCfg4Spec {
12915            type Ux = u32;
12916        }
12917        #[doc = "`read()` method returns [`pwm_oen_cfg4::R`](R) reader structure"]
12918        impl crate::Readable for PwmOenCfg4Spec {}
12919        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg4::W`](W) writer structure"]
12920        impl crate::Writable for PwmOenCfg4Spec {
12921            type Safety = crate::Unsafe;
12922        }
12923        #[doc = "`reset()` method sets PWM_OEN_CFG4 to value 0"]
12924        impl crate::Resettable for PwmOenCfg4Spec {}
12925    }
12926    #[doc = "PWM_OFFSET_L4 (rw) register accessor: PWM4 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l4`] module"]
12927    #[doc(alias = "PWM_OFFSET_L4")]
12928    pub type PwmOffsetL4 = crate::Reg<pwm_offset_l4::PwmOffsetL4Spec>;
12929    #[doc = "PWM4 phase offset low 16 bits"]
12930    pub mod pwm_offset_l4 {
12931        #[doc = "Register `PWM_OFFSET_L4` reader"]
12932        pub type R = crate::R<PwmOffsetL4Spec>;
12933        #[doc = "Register `PWM_OFFSET_L4` writer"]
12934        pub type W = crate::W<PwmOffsetL4Spec>;
12935        #[doc = "Field `pwm_offset_l_4` reader - PWM0 phase offset low 16 bits"]
12936        pub type PwmOffsetL4R = crate::FieldReader<u16>;
12937        #[doc = "Field `pwm_offset_l_4` writer - PWM0 phase offset low 16 bits"]
12938        pub type PwmOffsetL4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12939        impl R {
12940            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
12941            #[inline(always)]
12942            pub fn pwm_offset_l_4(&self) -> PwmOffsetL4R {
12943                PwmOffsetL4R::new((self.bits & 0xffff) as u16)
12944            }
12945        }
12946        impl W {
12947            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
12948            #[inline(always)]
12949            pub fn pwm_offset_l_4(&mut self) -> PwmOffsetL4W<'_, PwmOffsetL4Spec> {
12950                PwmOffsetL4W::new(self, 0)
12951            }
12952        }
12953        #[doc = "PWM4 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12954        pub struct PwmOffsetL4Spec;
12955        impl crate::RegisterSpec for PwmOffsetL4Spec {
12956            type Ux = u32;
12957        }
12958        #[doc = "`read()` method returns [`pwm_offset_l4::R`](R) reader structure"]
12959        impl crate::Readable for PwmOffsetL4Spec {}
12960        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l4::W`](W) writer structure"]
12961        impl crate::Writable for PwmOffsetL4Spec {
12962            type Safety = crate::Unsafe;
12963        }
12964        #[doc = "`reset()` method sets PWM_OFFSET_L4 to value 0"]
12965        impl crate::Resettable for PwmOffsetL4Spec {}
12966    }
12967    #[doc = "PWM_OFFSET_H4 (rw) register accessor: PWM4 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h4`] module"]
12968    #[doc(alias = "PWM_OFFSET_H4")]
12969    pub type PwmOffsetH4 = crate::Reg<pwm_offset_h4::PwmOffsetH4Spec>;
12970    #[doc = "PWM4 phase offset high 16 bits"]
12971    pub mod pwm_offset_h4 {
12972        #[doc = "Register `PWM_OFFSET_H4` reader"]
12973        pub type R = crate::R<PwmOffsetH4Spec>;
12974        #[doc = "Register `PWM_OFFSET_H4` writer"]
12975        pub type W = crate::W<PwmOffsetH4Spec>;
12976        #[doc = "Field `pwm_offset_h_4` reader - PWM0 phase offset high 16 bits"]
12977        pub type PwmOffsetH4R = crate::FieldReader<u16>;
12978        #[doc = "Field `pwm_offset_h_4` writer - PWM0 phase offset high 16 bits"]
12979        pub type PwmOffsetH4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12980        impl R {
12981            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
12982            #[inline(always)]
12983            pub fn pwm_offset_h_4(&self) -> PwmOffsetH4R {
12984                PwmOffsetH4R::new((self.bits & 0xffff) as u16)
12985            }
12986        }
12987        impl W {
12988            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
12989            #[inline(always)]
12990            pub fn pwm_offset_h_4(&mut self) -> PwmOffsetH4W<'_, PwmOffsetH4Spec> {
12991                PwmOffsetH4W::new(self, 0)
12992            }
12993        }
12994        #[doc = "PWM4 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12995        pub struct PwmOffsetH4Spec;
12996        impl crate::RegisterSpec for PwmOffsetH4Spec {
12997            type Ux = u32;
12998        }
12999        #[doc = "`read()` method returns [`pwm_offset_h4::R`](R) reader structure"]
13000        impl crate::Readable for PwmOffsetH4Spec {}
13001        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h4::W`](W) writer structure"]
13002        impl crate::Writable for PwmOffsetH4Spec {
13003            type Safety = crate::Unsafe;
13004        }
13005        #[doc = "`reset()` method sets PWM_OFFSET_H4 to value 0"]
13006        impl crate::Resettable for PwmOffsetH4Spec {}
13007    }
13008    #[doc = "PWM_FREQ_L4 (rw) register accessor: PWM4 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l4`] module"]
13009    #[doc(alias = "PWM_FREQ_L4")]
13010    pub type PwmFreqL4 = crate::Reg<pwm_freq_l4::PwmFreqL4Spec>;
13011    #[doc = "PWM4 frequency low 16 bits"]
13012    pub mod pwm_freq_l4 {
13013        #[doc = "Register `PWM_FREQ_L4` reader"]
13014        pub type R = crate::R<PwmFreqL4Spec>;
13015        #[doc = "Register `PWM_FREQ_L4` writer"]
13016        pub type W = crate::W<PwmFreqL4Spec>;
13017        #[doc = "Field `pwm_freq_l_4` reader - PWM0 clock divider low 16 bits"]
13018        pub type PwmFreqL4R = crate::FieldReader<u16>;
13019        #[doc = "Field `pwm_freq_l_4` writer - PWM0 clock divider low 16 bits"]
13020        pub type PwmFreqL4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13021        impl R {
13022            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
13023            #[inline(always)]
13024            pub fn pwm_freq_l_4(&self) -> PwmFreqL4R {
13025                PwmFreqL4R::new((self.bits & 0xffff) as u16)
13026            }
13027        }
13028        impl W {
13029            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
13030            #[inline(always)]
13031            pub fn pwm_freq_l_4(&mut self) -> PwmFreqL4W<'_, PwmFreqL4Spec> {
13032                PwmFreqL4W::new(self, 0)
13033            }
13034        }
13035        #[doc = "PWM4 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13036        pub struct PwmFreqL4Spec;
13037        impl crate::RegisterSpec for PwmFreqL4Spec {
13038            type Ux = u32;
13039        }
13040        #[doc = "`read()` method returns [`pwm_freq_l4::R`](R) reader structure"]
13041        impl crate::Readable for PwmFreqL4Spec {}
13042        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l4::W`](W) writer structure"]
13043        impl crate::Writable for PwmFreqL4Spec {
13044            type Safety = crate::Unsafe;
13045        }
13046        #[doc = "`reset()` method sets PWM_FREQ_L4 to value 0"]
13047        impl crate::Resettable for PwmFreqL4Spec {}
13048    }
13049    #[doc = "PWM_FREQ_H4 (rw) register accessor: PWM4 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h4`] module"]
13050    #[doc(alias = "PWM_FREQ_H4")]
13051    pub type PwmFreqH4 = crate::Reg<pwm_freq_h4::PwmFreqH4Spec>;
13052    #[doc = "PWM4 frequency high 16 bits"]
13053    pub mod pwm_freq_h4 {
13054        #[doc = "Register `PWM_FREQ_H4` reader"]
13055        pub type R = crate::R<PwmFreqH4Spec>;
13056        #[doc = "Register `PWM_FREQ_H4` writer"]
13057        pub type W = crate::W<PwmFreqH4Spec>;
13058        #[doc = "Field `pwm_freq_h_4` reader - PWM0 clock divider high 16 bits"]
13059        pub type PwmFreqH4R = crate::FieldReader<u16>;
13060        #[doc = "Field `pwm_freq_h_4` writer - PWM0 clock divider high 16 bits"]
13061        pub type PwmFreqH4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13062        impl R {
13063            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
13064            #[inline(always)]
13065            pub fn pwm_freq_h_4(&self) -> PwmFreqH4R {
13066                PwmFreqH4R::new((self.bits & 0xffff) as u16)
13067            }
13068        }
13069        impl W {
13070            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
13071            #[inline(always)]
13072            pub fn pwm_freq_h_4(&mut self) -> PwmFreqH4W<'_, PwmFreqH4Spec> {
13073                PwmFreqH4W::new(self, 0)
13074            }
13075        }
13076        #[doc = "PWM4 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13077        pub struct PwmFreqH4Spec;
13078        impl crate::RegisterSpec for PwmFreqH4Spec {
13079            type Ux = u32;
13080        }
13081        #[doc = "`read()` method returns [`pwm_freq_h4::R`](R) reader structure"]
13082        impl crate::Readable for PwmFreqH4Spec {}
13083        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h4::W`](W) writer structure"]
13084        impl crate::Writable for PwmFreqH4Spec {
13085            type Safety = crate::Unsafe;
13086        }
13087        #[doc = "`reset()` method sets PWM_FREQ_H4 to value 0"]
13088        impl crate::Resettable for PwmFreqH4Spec {}
13089    }
13090    #[doc = "PWM_DUTY_L4 (rw) register accessor: PWM4 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l4`] module"]
13091    #[doc(alias = "PWM_DUTY_L4")]
13092    pub type PwmDutyL4 = crate::Reg<pwm_duty_l4::PwmDutyL4Spec>;
13093    #[doc = "PWM4 duty cycle low 16 bits"]
13094    pub mod pwm_duty_l4 {
13095        #[doc = "Register `PWM_DUTY_L4` reader"]
13096        pub type R = crate::R<PwmDutyL4Spec>;
13097        #[doc = "Register `PWM_DUTY_L4` writer"]
13098        pub type W = crate::W<PwmDutyL4Spec>;
13099        #[doc = "Field `pwm_duty_l_4` reader - PWM0 duty cycle low 16 bits"]
13100        pub type PwmDutyL4R = crate::FieldReader<u16>;
13101        #[doc = "Field `pwm_duty_l_4` writer - PWM0 duty cycle low 16 bits"]
13102        pub type PwmDutyL4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13103        impl R {
13104            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
13105            #[inline(always)]
13106            pub fn pwm_duty_l_4(&self) -> PwmDutyL4R {
13107                PwmDutyL4R::new((self.bits & 0xffff) as u16)
13108            }
13109        }
13110        impl W {
13111            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
13112            #[inline(always)]
13113            pub fn pwm_duty_l_4(&mut self) -> PwmDutyL4W<'_, PwmDutyL4Spec> {
13114                PwmDutyL4W::new(self, 0)
13115            }
13116        }
13117        #[doc = "PWM4 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13118        pub struct PwmDutyL4Spec;
13119        impl crate::RegisterSpec for PwmDutyL4Spec {
13120            type Ux = u32;
13121        }
13122        #[doc = "`read()` method returns [`pwm_duty_l4::R`](R) reader structure"]
13123        impl crate::Readable for PwmDutyL4Spec {}
13124        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l4::W`](W) writer structure"]
13125        impl crate::Writable for PwmDutyL4Spec {
13126            type Safety = crate::Unsafe;
13127        }
13128        #[doc = "`reset()` method sets PWM_DUTY_L4 to value 0"]
13129        impl crate::Resettable for PwmDutyL4Spec {}
13130    }
13131    #[doc = "PWM_DUTY_H4 (rw) register accessor: PWM4 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h4`] module"]
13132    #[doc(alias = "PWM_DUTY_H4")]
13133    pub type PwmDutyH4 = crate::Reg<pwm_duty_h4::PwmDutyH4Spec>;
13134    #[doc = "PWM4 duty cycle high 16 bits"]
13135    pub mod pwm_duty_h4 {
13136        #[doc = "Register `PWM_DUTY_H4` reader"]
13137        pub type R = crate::R<PwmDutyH4Spec>;
13138        #[doc = "Register `PWM_DUTY_H4` writer"]
13139        pub type W = crate::W<PwmDutyH4Spec>;
13140        #[doc = "Field `pwm_duty_h_4` reader - PWM0 duty cycle high 16 bits"]
13141        pub type PwmDutyH4R = crate::FieldReader<u16>;
13142        #[doc = "Field `pwm_duty_h_4` writer - PWM0 duty cycle high 16 bits"]
13143        pub type PwmDutyH4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13144        impl R {
13145            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
13146            #[inline(always)]
13147            pub fn pwm_duty_h_4(&self) -> PwmDutyH4R {
13148                PwmDutyH4R::new((self.bits & 0xffff) as u16)
13149            }
13150        }
13151        impl W {
13152            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
13153            #[inline(always)]
13154            pub fn pwm_duty_h_4(&mut self) -> PwmDutyH4W<'_, PwmDutyH4Spec> {
13155                PwmDutyH4W::new(self, 0)
13156            }
13157        }
13158        #[doc = "PWM4 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13159        pub struct PwmDutyH4Spec;
13160        impl crate::RegisterSpec for PwmDutyH4Spec {
13161            type Ux = u32;
13162        }
13163        #[doc = "`read()` method returns [`pwm_duty_h4::R`](R) reader structure"]
13164        impl crate::Readable for PwmDutyH4Spec {}
13165        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h4::W`](W) writer structure"]
13166        impl crate::Writable for PwmDutyH4Spec {
13167            type Safety = crate::Unsafe;
13168        }
13169        #[doc = "`reset()` method sets PWM_DUTY_H4 to value 0"]
13170        impl crate::Resettable for PwmDutyH4Spec {}
13171    }
13172    #[doc = "PWM_PERIODLOAD_FLAG4 (rw) register accessor: PWM4 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag4`] module"]
13173    #[doc(alias = "PWM_PERIODLOAD_FLAG4")]
13174    pub type PwmPeriodloadFlag4 = crate::Reg<pwm_periodload_flag4::PwmPeriodloadFlag4Spec>;
13175    #[doc = "PWM4 period load flag"]
13176    pub mod pwm_periodload_flag4 {
13177        #[doc = "Register `PWM_PERIODLOAD_FLAG4` reader"]
13178        pub type R = crate::R<PwmPeriodloadFlag4Spec>;
13179        #[doc = "Register `PWM_PERIODLOAD_FLAG4` writer"]
13180        pub type W = crate::W<PwmPeriodloadFlag4Spec>;
13181        #[doc = "Field `pwm_periodload_flag_4` reader - Period load complete flag"]
13182        pub type PwmPeriodloadFlag4R = crate::BitReader;
13183        impl R {
13184            #[doc = "Bit 0 - Period load complete flag"]
13185            #[inline(always)]
13186            pub fn pwm_periodload_flag_4(&self) -> PwmPeriodloadFlag4R {
13187                PwmPeriodloadFlag4R::new((self.bits & 1) != 0)
13188            }
13189        }
13190        impl W {}
13191        #[doc = "PWM4 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13192        pub struct PwmPeriodloadFlag4Spec;
13193        impl crate::RegisterSpec for PwmPeriodloadFlag4Spec {
13194            type Ux = u32;
13195        }
13196        #[doc = "`read()` method returns [`pwm_periodload_flag4::R`](R) reader structure"]
13197        impl crate::Readable for PwmPeriodloadFlag4Spec {}
13198        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag4::W`](W) writer structure"]
13199        impl crate::Writable for PwmPeriodloadFlag4Spec {
13200            type Safety = crate::Unsafe;
13201        }
13202        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG4 to value 0"]
13203        impl crate::Resettable for PwmPeriodloadFlag4Spec {}
13204    }
13205    #[doc = "PWM_PERIOD_VAL4 (rw) register accessor: PWM4 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val4`] module"]
13206    #[doc(alias = "PWM_PERIOD_VAL4")]
13207    pub type PwmPeriodVal4 = crate::Reg<pwm_period_val4::PwmPeriodVal4Spec>;
13208    #[doc = "PWM4 pulse count value"]
13209    pub mod pwm_period_val4 {
13210        #[doc = "Register `PWM_PERIOD_VAL4` reader"]
13211        pub type R = crate::R<PwmPeriodVal4Spec>;
13212        #[doc = "Register `PWM_PERIOD_VAL4` writer"]
13213        pub type W = crate::W<PwmPeriodVal4Spec>;
13214        #[doc = "Field `pwm_period_val_4` reader - Pulse count for stepping mode"]
13215        pub type PwmPeriodVal4R = crate::FieldReader<u16>;
13216        #[doc = "Field `pwm_period_val_4` writer - Pulse count for stepping mode"]
13217        pub type PwmPeriodVal4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13218        impl R {
13219            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
13220            #[inline(always)]
13221            pub fn pwm_period_val_4(&self) -> PwmPeriodVal4R {
13222                PwmPeriodVal4R::new((self.bits & 0xffff) as u16)
13223            }
13224        }
13225        impl W {
13226            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
13227            #[inline(always)]
13228            pub fn pwm_period_val_4(&mut self) -> PwmPeriodVal4W<'_, PwmPeriodVal4Spec> {
13229                PwmPeriodVal4W::new(self, 0)
13230            }
13231        }
13232        #[doc = "PWM4 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13233        pub struct PwmPeriodVal4Spec;
13234        impl crate::RegisterSpec for PwmPeriodVal4Spec {
13235            type Ux = u32;
13236        }
13237        #[doc = "`read()` method returns [`pwm_period_val4::R`](R) reader structure"]
13238        impl crate::Readable for PwmPeriodVal4Spec {}
13239        #[doc = "`write(|w| ..)` method takes [`pwm_period_val4::W`](W) writer structure"]
13240        impl crate::Writable for PwmPeriodVal4Spec {
13241            type Safety = crate::Unsafe;
13242        }
13243        #[doc = "`reset()` method sets PWM_PERIOD_VAL4 to value 0"]
13244        impl crate::Resettable for PwmPeriodVal4Spec {}
13245    }
13246    #[doc = "PWM_PERIODCNT4 (rw) register accessor: PWM4 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt4`] module"]
13247    #[doc(alias = "PWM_PERIODCNT4")]
13248    pub type PwmPeriodcnt4 = crate::Reg<pwm_periodcnt4::PwmPeriodcnt4Spec>;
13249    #[doc = "PWM4 pulse count current value"]
13250    pub mod pwm_periodcnt4 {
13251        #[doc = "Register `PWM_PERIODCNT4` reader"]
13252        pub type R = crate::R<PwmPeriodcnt4Spec>;
13253        #[doc = "Register `PWM_PERIODCNT4` writer"]
13254        pub type W = crate::W<PwmPeriodcnt4Spec>;
13255        #[doc = "Field `pwm_periodcnt_4` reader - Current pulse count"]
13256        pub type PwmPeriodcnt4R = crate::FieldReader<u16>;
13257        impl R {
13258            #[doc = "Bits 0:15 - Current pulse count"]
13259            #[inline(always)]
13260            pub fn pwm_periodcnt_4(&self) -> PwmPeriodcnt4R {
13261                PwmPeriodcnt4R::new((self.bits & 0xffff) as u16)
13262            }
13263        }
13264        impl W {}
13265        #[doc = "PWM4 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13266        pub struct PwmPeriodcnt4Spec;
13267        impl crate::RegisterSpec for PwmPeriodcnt4Spec {
13268            type Ux = u32;
13269        }
13270        #[doc = "`read()` method returns [`pwm_periodcnt4::R`](R) reader structure"]
13271        impl crate::Readable for PwmPeriodcnt4Spec {}
13272        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt4::W`](W) writer structure"]
13273        impl crate::Writable for PwmPeriodcnt4Spec {
13274            type Safety = crate::Unsafe;
13275        }
13276        #[doc = "`reset()` method sets PWM_PERIODCNT4 to value 0"]
13277        impl crate::Resettable for PwmPeriodcnt4Spec {}
13278    }
13279    #[doc = "PWM_EN5 (rw) register accessor: PWM5 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en5`] module"]
13280    #[doc(alias = "PWM_EN5")]
13281    pub type PwmEn5 = crate::Reg<pwm_en5::PwmEn5Spec>;
13282    #[doc = "PWM5 enable"]
13283    pub mod pwm_en5 {
13284        #[doc = "Register `PWM_EN5` reader"]
13285        pub type R = crate::R<PwmEn5Spec>;
13286        #[doc = "Register `PWM_EN5` writer"]
13287        pub type W = crate::W<PwmEn5Spec>;
13288        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
13289        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
13290        pub enum PwmEn5 {
13291            #[doc = "0: PWM disabled, output low"]
13292            Off = 0,
13293            #[doc = "1: PWM enabled"]
13294            On = 1,
13295        }
13296        impl From<PwmEn5> for bool {
13297            #[inline(always)]
13298            fn from(variant: PwmEn5) -> Self {
13299                variant as u8 != 0
13300            }
13301        }
13302        #[doc = "Field `pwm_en_5` reader - PWM0 enable: 0=off; 1=on"]
13303        pub type PwmEn5R = crate::BitReader<PwmEn5>;
13304        impl PwmEn5R {
13305            #[doc = "Get enumerated values variant"]
13306            #[inline(always)]
13307            pub const fn variant(&self) -> PwmEn5 {
13308                match self.bits {
13309                    false => PwmEn5::Off,
13310                    true => PwmEn5::On,
13311                }
13312            }
13313            #[doc = "PWM disabled, output low"]
13314            #[inline(always)]
13315            pub fn is_off(&self) -> bool {
13316                *self == PwmEn5::Off
13317            }
13318            #[doc = "PWM enabled"]
13319            #[inline(always)]
13320            pub fn is_on(&self) -> bool {
13321                *self == PwmEn5::On
13322            }
13323        }
13324        #[doc = "Field `pwm_en_5` writer - PWM0 enable: 0=off; 1=on"]
13325        pub type PwmEn5W<'a, REG> = crate::BitWriter<'a, REG, PwmEn5>;
13326        impl<'a, REG> PwmEn5W<'a, REG>
13327        where
13328            REG: crate::Writable + crate::RegisterSpec,
13329        {
13330            #[doc = "PWM disabled, output low"]
13331            #[inline(always)]
13332            pub fn off(self) -> &'a mut crate::W<REG> {
13333                self.variant(PwmEn5::Off)
13334            }
13335            #[doc = "PWM enabled"]
13336            #[inline(always)]
13337            pub fn on(self) -> &'a mut crate::W<REG> {
13338                self.variant(PwmEn5::On)
13339            }
13340        }
13341        impl R {
13342            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
13343            #[inline(always)]
13344            pub fn pwm_en_5(&self) -> PwmEn5R {
13345                PwmEn5R::new((self.bits & 1) != 0)
13346            }
13347        }
13348        impl W {
13349            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
13350            #[inline(always)]
13351            pub fn pwm_en_5(&mut self) -> PwmEn5W<'_, PwmEn5Spec> {
13352                PwmEn5W::new(self, 0)
13353            }
13354        }
13355        #[doc = "PWM5 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13356        pub struct PwmEn5Spec;
13357        impl crate::RegisterSpec for PwmEn5Spec {
13358            type Ux = u32;
13359        }
13360        #[doc = "`read()` method returns [`pwm_en5::R`](R) reader structure"]
13361        impl crate::Readable for PwmEn5Spec {}
13362        #[doc = "`write(|w| ..)` method takes [`pwm_en5::W`](W) writer structure"]
13363        impl crate::Writable for PwmEn5Spec {
13364            type Safety = crate::Unsafe;
13365        }
13366        #[doc = "`reset()` method sets PWM_EN5 to value 0"]
13367        impl crate::Resettable for PwmEn5Spec {}
13368    }
13369    #[doc = "PWM_PORTITY5 (rw) register accessor: PWM5 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity5`] module"]
13370    #[doc(alias = "PWM_PORTITY5")]
13371    pub type PwmPortity5 = crate::Reg<pwm_portity5::PwmPortity5Spec>;
13372    #[doc = "PWM5 polarity"]
13373    pub mod pwm_portity5 {
13374        #[doc = "Register `PWM_PORTITY5` reader"]
13375        pub type R = crate::R<PwmPortity5Spec>;
13376        #[doc = "Register `PWM_PORTITY5` writer"]
13377        pub type W = crate::W<PwmPortity5Spec>;
13378        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
13379        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
13380        pub enum PwmPoarity5 {
13381            #[doc = "0: Normal polarity"]
13382            Normal = 0,
13383            #[doc = "1: Inverted polarity"]
13384            Inverted = 1,
13385        }
13386        impl From<PwmPoarity5> for bool {
13387            #[inline(always)]
13388            fn from(variant: PwmPoarity5) -> Self {
13389                variant as u8 != 0
13390            }
13391        }
13392        #[doc = "Field `pwm_poarity_5` reader - PWM0 polarity: 0=normal; 1=inverted"]
13393        pub type PwmPoarity5R = crate::BitReader<PwmPoarity5>;
13394        impl PwmPoarity5R {
13395            #[doc = "Get enumerated values variant"]
13396            #[inline(always)]
13397            pub const fn variant(&self) -> PwmPoarity5 {
13398                match self.bits {
13399                    false => PwmPoarity5::Normal,
13400                    true => PwmPoarity5::Inverted,
13401                }
13402            }
13403            #[doc = "Normal polarity"]
13404            #[inline(always)]
13405            pub fn is_normal(&self) -> bool {
13406                *self == PwmPoarity5::Normal
13407            }
13408            #[doc = "Inverted polarity"]
13409            #[inline(always)]
13410            pub fn is_inverted(&self) -> bool {
13411                *self == PwmPoarity5::Inverted
13412            }
13413        }
13414        #[doc = "Field `pwm_poarity_5` writer - PWM0 polarity: 0=normal; 1=inverted"]
13415        pub type PwmPoarity5W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity5>;
13416        impl<'a, REG> PwmPoarity5W<'a, REG>
13417        where
13418            REG: crate::Writable + crate::RegisterSpec,
13419        {
13420            #[doc = "Normal polarity"]
13421            #[inline(always)]
13422            pub fn normal(self) -> &'a mut crate::W<REG> {
13423                self.variant(PwmPoarity5::Normal)
13424            }
13425            #[doc = "Inverted polarity"]
13426            #[inline(always)]
13427            pub fn inverted(self) -> &'a mut crate::W<REG> {
13428                self.variant(PwmPoarity5::Inverted)
13429            }
13430        }
13431        impl R {
13432            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
13433            #[inline(always)]
13434            pub fn pwm_poarity_5(&self) -> PwmPoarity5R {
13435                PwmPoarity5R::new((self.bits & 1) != 0)
13436            }
13437        }
13438        impl W {
13439            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
13440            #[inline(always)]
13441            pub fn pwm_poarity_5(&mut self) -> PwmPoarity5W<'_, PwmPortity5Spec> {
13442                PwmPoarity5W::new(self, 0)
13443            }
13444        }
13445        #[doc = "PWM5 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13446        pub struct PwmPortity5Spec;
13447        impl crate::RegisterSpec for PwmPortity5Spec {
13448            type Ux = u32;
13449        }
13450        #[doc = "`read()` method returns [`pwm_portity5::R`](R) reader structure"]
13451        impl crate::Readable for PwmPortity5Spec {}
13452        #[doc = "`write(|w| ..)` method takes [`pwm_portity5::W`](W) writer structure"]
13453        impl crate::Writable for PwmPortity5Spec {
13454            type Safety = crate::Unsafe;
13455        }
13456        #[doc = "`reset()` method sets PWM_PORTITY5 to value 0"]
13457        impl crate::Resettable for PwmPortity5Spec {}
13458    }
13459    #[doc = "PWM_OEN_CFG5 (rw) register accessor: PWM5 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg5`] module"]
13460    #[doc(alias = "PWM_OEN_CFG5")]
13461    pub type PwmOenCfg5 = crate::Reg<pwm_oen_cfg5::PwmOenCfg5Spec>;
13462    #[doc = "PWM5 high-impedance config"]
13463    pub mod pwm_oen_cfg5 {
13464        #[doc = "Register `PWM_OEN_CFG5` reader"]
13465        pub type R = crate::R<PwmOenCfg5Spec>;
13466        #[doc = "Register `PWM_OEN_CFG5` writer"]
13467        pub type W = crate::W<PwmOenCfg5Spec>;
13468        #[doc = "Field `pwm_oen_cfg_5` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
13469        pub type PwmOenCfg5R = crate::BitReader;
13470        #[doc = "Field `pwm_oen_cfg_5` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
13471        pub type PwmOenCfg5W<'a, REG> = crate::BitWriter<'a, REG>;
13472        impl R {
13473            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
13474            #[inline(always)]
13475            pub fn pwm_oen_cfg_5(&self) -> PwmOenCfg5R {
13476                PwmOenCfg5R::new((self.bits & 1) != 0)
13477            }
13478        }
13479        impl W {
13480            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
13481            #[inline(always)]
13482            pub fn pwm_oen_cfg_5(&mut self) -> PwmOenCfg5W<'_, PwmOenCfg5Spec> {
13483                PwmOenCfg5W::new(self, 0)
13484            }
13485        }
13486        #[doc = "PWM5 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13487        pub struct PwmOenCfg5Spec;
13488        impl crate::RegisterSpec for PwmOenCfg5Spec {
13489            type Ux = u32;
13490        }
13491        #[doc = "`read()` method returns [`pwm_oen_cfg5::R`](R) reader structure"]
13492        impl crate::Readable for PwmOenCfg5Spec {}
13493        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg5::W`](W) writer structure"]
13494        impl crate::Writable for PwmOenCfg5Spec {
13495            type Safety = crate::Unsafe;
13496        }
13497        #[doc = "`reset()` method sets PWM_OEN_CFG5 to value 0"]
13498        impl crate::Resettable for PwmOenCfg5Spec {}
13499    }
13500    #[doc = "PWM_OFFSET_L5 (rw) register accessor: PWM5 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l5`] module"]
13501    #[doc(alias = "PWM_OFFSET_L5")]
13502    pub type PwmOffsetL5 = crate::Reg<pwm_offset_l5::PwmOffsetL5Spec>;
13503    #[doc = "PWM5 phase offset low 16 bits"]
13504    pub mod pwm_offset_l5 {
13505        #[doc = "Register `PWM_OFFSET_L5` reader"]
13506        pub type R = crate::R<PwmOffsetL5Spec>;
13507        #[doc = "Register `PWM_OFFSET_L5` writer"]
13508        pub type W = crate::W<PwmOffsetL5Spec>;
13509        #[doc = "Field `pwm_offset_l_5` reader - PWM0 phase offset low 16 bits"]
13510        pub type PwmOffsetL5R = crate::FieldReader<u16>;
13511        #[doc = "Field `pwm_offset_l_5` writer - PWM0 phase offset low 16 bits"]
13512        pub type PwmOffsetL5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13513        impl R {
13514            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
13515            #[inline(always)]
13516            pub fn pwm_offset_l_5(&self) -> PwmOffsetL5R {
13517                PwmOffsetL5R::new((self.bits & 0xffff) as u16)
13518            }
13519        }
13520        impl W {
13521            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
13522            #[inline(always)]
13523            pub fn pwm_offset_l_5(&mut self) -> PwmOffsetL5W<'_, PwmOffsetL5Spec> {
13524                PwmOffsetL5W::new(self, 0)
13525            }
13526        }
13527        #[doc = "PWM5 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13528        pub struct PwmOffsetL5Spec;
13529        impl crate::RegisterSpec for PwmOffsetL5Spec {
13530            type Ux = u32;
13531        }
13532        #[doc = "`read()` method returns [`pwm_offset_l5::R`](R) reader structure"]
13533        impl crate::Readable for PwmOffsetL5Spec {}
13534        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l5::W`](W) writer structure"]
13535        impl crate::Writable for PwmOffsetL5Spec {
13536            type Safety = crate::Unsafe;
13537        }
13538        #[doc = "`reset()` method sets PWM_OFFSET_L5 to value 0"]
13539        impl crate::Resettable for PwmOffsetL5Spec {}
13540    }
13541    #[doc = "PWM_OFFSET_H5 (rw) register accessor: PWM5 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h5`] module"]
13542    #[doc(alias = "PWM_OFFSET_H5")]
13543    pub type PwmOffsetH5 = crate::Reg<pwm_offset_h5::PwmOffsetH5Spec>;
13544    #[doc = "PWM5 phase offset high 16 bits"]
13545    pub mod pwm_offset_h5 {
13546        #[doc = "Register `PWM_OFFSET_H5` reader"]
13547        pub type R = crate::R<PwmOffsetH5Spec>;
13548        #[doc = "Register `PWM_OFFSET_H5` writer"]
13549        pub type W = crate::W<PwmOffsetH5Spec>;
13550        #[doc = "Field `pwm_offset_h_5` reader - PWM0 phase offset high 16 bits"]
13551        pub type PwmOffsetH5R = crate::FieldReader<u16>;
13552        #[doc = "Field `pwm_offset_h_5` writer - PWM0 phase offset high 16 bits"]
13553        pub type PwmOffsetH5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13554        impl R {
13555            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
13556            #[inline(always)]
13557            pub fn pwm_offset_h_5(&self) -> PwmOffsetH5R {
13558                PwmOffsetH5R::new((self.bits & 0xffff) as u16)
13559            }
13560        }
13561        impl W {
13562            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
13563            #[inline(always)]
13564            pub fn pwm_offset_h_5(&mut self) -> PwmOffsetH5W<'_, PwmOffsetH5Spec> {
13565                PwmOffsetH5W::new(self, 0)
13566            }
13567        }
13568        #[doc = "PWM5 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13569        pub struct PwmOffsetH5Spec;
13570        impl crate::RegisterSpec for PwmOffsetH5Spec {
13571            type Ux = u32;
13572        }
13573        #[doc = "`read()` method returns [`pwm_offset_h5::R`](R) reader structure"]
13574        impl crate::Readable for PwmOffsetH5Spec {}
13575        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h5::W`](W) writer structure"]
13576        impl crate::Writable for PwmOffsetH5Spec {
13577            type Safety = crate::Unsafe;
13578        }
13579        #[doc = "`reset()` method sets PWM_OFFSET_H5 to value 0"]
13580        impl crate::Resettable for PwmOffsetH5Spec {}
13581    }
13582    #[doc = "PWM_FREQ_L5 (rw) register accessor: PWM5 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l5`] module"]
13583    #[doc(alias = "PWM_FREQ_L5")]
13584    pub type PwmFreqL5 = crate::Reg<pwm_freq_l5::PwmFreqL5Spec>;
13585    #[doc = "PWM5 frequency low 16 bits"]
13586    pub mod pwm_freq_l5 {
13587        #[doc = "Register `PWM_FREQ_L5` reader"]
13588        pub type R = crate::R<PwmFreqL5Spec>;
13589        #[doc = "Register `PWM_FREQ_L5` writer"]
13590        pub type W = crate::W<PwmFreqL5Spec>;
13591        #[doc = "Field `pwm_freq_l_5` reader - PWM0 clock divider low 16 bits"]
13592        pub type PwmFreqL5R = crate::FieldReader<u16>;
13593        #[doc = "Field `pwm_freq_l_5` writer - PWM0 clock divider low 16 bits"]
13594        pub type PwmFreqL5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13595        impl R {
13596            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
13597            #[inline(always)]
13598            pub fn pwm_freq_l_5(&self) -> PwmFreqL5R {
13599                PwmFreqL5R::new((self.bits & 0xffff) as u16)
13600            }
13601        }
13602        impl W {
13603            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
13604            #[inline(always)]
13605            pub fn pwm_freq_l_5(&mut self) -> PwmFreqL5W<'_, PwmFreqL5Spec> {
13606                PwmFreqL5W::new(self, 0)
13607            }
13608        }
13609        #[doc = "PWM5 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13610        pub struct PwmFreqL5Spec;
13611        impl crate::RegisterSpec for PwmFreqL5Spec {
13612            type Ux = u32;
13613        }
13614        #[doc = "`read()` method returns [`pwm_freq_l5::R`](R) reader structure"]
13615        impl crate::Readable for PwmFreqL5Spec {}
13616        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l5::W`](W) writer structure"]
13617        impl crate::Writable for PwmFreqL5Spec {
13618            type Safety = crate::Unsafe;
13619        }
13620        #[doc = "`reset()` method sets PWM_FREQ_L5 to value 0"]
13621        impl crate::Resettable for PwmFreqL5Spec {}
13622    }
13623    #[doc = "PWM_FREQ_H5 (rw) register accessor: PWM5 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h5`] module"]
13624    #[doc(alias = "PWM_FREQ_H5")]
13625    pub type PwmFreqH5 = crate::Reg<pwm_freq_h5::PwmFreqH5Spec>;
13626    #[doc = "PWM5 frequency high 16 bits"]
13627    pub mod pwm_freq_h5 {
13628        #[doc = "Register `PWM_FREQ_H5` reader"]
13629        pub type R = crate::R<PwmFreqH5Spec>;
13630        #[doc = "Register `PWM_FREQ_H5` writer"]
13631        pub type W = crate::W<PwmFreqH5Spec>;
13632        #[doc = "Field `pwm_freq_h_5` reader - PWM0 clock divider high 16 bits"]
13633        pub type PwmFreqH5R = crate::FieldReader<u16>;
13634        #[doc = "Field `pwm_freq_h_5` writer - PWM0 clock divider high 16 bits"]
13635        pub type PwmFreqH5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13636        impl R {
13637            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
13638            #[inline(always)]
13639            pub fn pwm_freq_h_5(&self) -> PwmFreqH5R {
13640                PwmFreqH5R::new((self.bits & 0xffff) as u16)
13641            }
13642        }
13643        impl W {
13644            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
13645            #[inline(always)]
13646            pub fn pwm_freq_h_5(&mut self) -> PwmFreqH5W<'_, PwmFreqH5Spec> {
13647                PwmFreqH5W::new(self, 0)
13648            }
13649        }
13650        #[doc = "PWM5 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13651        pub struct PwmFreqH5Spec;
13652        impl crate::RegisterSpec for PwmFreqH5Spec {
13653            type Ux = u32;
13654        }
13655        #[doc = "`read()` method returns [`pwm_freq_h5::R`](R) reader structure"]
13656        impl crate::Readable for PwmFreqH5Spec {}
13657        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h5::W`](W) writer structure"]
13658        impl crate::Writable for PwmFreqH5Spec {
13659            type Safety = crate::Unsafe;
13660        }
13661        #[doc = "`reset()` method sets PWM_FREQ_H5 to value 0"]
13662        impl crate::Resettable for PwmFreqH5Spec {}
13663    }
13664    #[doc = "PWM_DUTY_L5 (rw) register accessor: PWM5 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l5`] module"]
13665    #[doc(alias = "PWM_DUTY_L5")]
13666    pub type PwmDutyL5 = crate::Reg<pwm_duty_l5::PwmDutyL5Spec>;
13667    #[doc = "PWM5 duty cycle low 16 bits"]
13668    pub mod pwm_duty_l5 {
13669        #[doc = "Register `PWM_DUTY_L5` reader"]
13670        pub type R = crate::R<PwmDutyL5Spec>;
13671        #[doc = "Register `PWM_DUTY_L5` writer"]
13672        pub type W = crate::W<PwmDutyL5Spec>;
13673        #[doc = "Field `pwm_duty_l_5` reader - PWM0 duty cycle low 16 bits"]
13674        pub type PwmDutyL5R = crate::FieldReader<u16>;
13675        #[doc = "Field `pwm_duty_l_5` writer - PWM0 duty cycle low 16 bits"]
13676        pub type PwmDutyL5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13677        impl R {
13678            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
13679            #[inline(always)]
13680            pub fn pwm_duty_l_5(&self) -> PwmDutyL5R {
13681                PwmDutyL5R::new((self.bits & 0xffff) as u16)
13682            }
13683        }
13684        impl W {
13685            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
13686            #[inline(always)]
13687            pub fn pwm_duty_l_5(&mut self) -> PwmDutyL5W<'_, PwmDutyL5Spec> {
13688                PwmDutyL5W::new(self, 0)
13689            }
13690        }
13691        #[doc = "PWM5 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13692        pub struct PwmDutyL5Spec;
13693        impl crate::RegisterSpec for PwmDutyL5Spec {
13694            type Ux = u32;
13695        }
13696        #[doc = "`read()` method returns [`pwm_duty_l5::R`](R) reader structure"]
13697        impl crate::Readable for PwmDutyL5Spec {}
13698        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l5::W`](W) writer structure"]
13699        impl crate::Writable for PwmDutyL5Spec {
13700            type Safety = crate::Unsafe;
13701        }
13702        #[doc = "`reset()` method sets PWM_DUTY_L5 to value 0"]
13703        impl crate::Resettable for PwmDutyL5Spec {}
13704    }
13705    #[doc = "PWM_DUTY_H5 (rw) register accessor: PWM5 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h5`] module"]
13706    #[doc(alias = "PWM_DUTY_H5")]
13707    pub type PwmDutyH5 = crate::Reg<pwm_duty_h5::PwmDutyH5Spec>;
13708    #[doc = "PWM5 duty cycle high 16 bits"]
13709    pub mod pwm_duty_h5 {
13710        #[doc = "Register `PWM_DUTY_H5` reader"]
13711        pub type R = crate::R<PwmDutyH5Spec>;
13712        #[doc = "Register `PWM_DUTY_H5` writer"]
13713        pub type W = crate::W<PwmDutyH5Spec>;
13714        #[doc = "Field `pwm_duty_h_5` reader - PWM0 duty cycle high 16 bits"]
13715        pub type PwmDutyH5R = crate::FieldReader<u16>;
13716        #[doc = "Field `pwm_duty_h_5` writer - PWM0 duty cycle high 16 bits"]
13717        pub type PwmDutyH5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13718        impl R {
13719            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
13720            #[inline(always)]
13721            pub fn pwm_duty_h_5(&self) -> PwmDutyH5R {
13722                PwmDutyH5R::new((self.bits & 0xffff) as u16)
13723            }
13724        }
13725        impl W {
13726            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
13727            #[inline(always)]
13728            pub fn pwm_duty_h_5(&mut self) -> PwmDutyH5W<'_, PwmDutyH5Spec> {
13729                PwmDutyH5W::new(self, 0)
13730            }
13731        }
13732        #[doc = "PWM5 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13733        pub struct PwmDutyH5Spec;
13734        impl crate::RegisterSpec for PwmDutyH5Spec {
13735            type Ux = u32;
13736        }
13737        #[doc = "`read()` method returns [`pwm_duty_h5::R`](R) reader structure"]
13738        impl crate::Readable for PwmDutyH5Spec {}
13739        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h5::W`](W) writer structure"]
13740        impl crate::Writable for PwmDutyH5Spec {
13741            type Safety = crate::Unsafe;
13742        }
13743        #[doc = "`reset()` method sets PWM_DUTY_H5 to value 0"]
13744        impl crate::Resettable for PwmDutyH5Spec {}
13745    }
13746    #[doc = "PWM_PERIODLOAD_FLAG5 (rw) register accessor: PWM5 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag5`] module"]
13747    #[doc(alias = "PWM_PERIODLOAD_FLAG5")]
13748    pub type PwmPeriodloadFlag5 = crate::Reg<pwm_periodload_flag5::PwmPeriodloadFlag5Spec>;
13749    #[doc = "PWM5 period load flag"]
13750    pub mod pwm_periodload_flag5 {
13751        #[doc = "Register `PWM_PERIODLOAD_FLAG5` reader"]
13752        pub type R = crate::R<PwmPeriodloadFlag5Spec>;
13753        #[doc = "Register `PWM_PERIODLOAD_FLAG5` writer"]
13754        pub type W = crate::W<PwmPeriodloadFlag5Spec>;
13755        #[doc = "Field `pwm_periodload_flag_5` reader - Period load complete flag"]
13756        pub type PwmPeriodloadFlag5R = crate::BitReader;
13757        impl R {
13758            #[doc = "Bit 0 - Period load complete flag"]
13759            #[inline(always)]
13760            pub fn pwm_periodload_flag_5(&self) -> PwmPeriodloadFlag5R {
13761                PwmPeriodloadFlag5R::new((self.bits & 1) != 0)
13762            }
13763        }
13764        impl W {}
13765        #[doc = "PWM5 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13766        pub struct PwmPeriodloadFlag5Spec;
13767        impl crate::RegisterSpec for PwmPeriodloadFlag5Spec {
13768            type Ux = u32;
13769        }
13770        #[doc = "`read()` method returns [`pwm_periodload_flag5::R`](R) reader structure"]
13771        impl crate::Readable for PwmPeriodloadFlag5Spec {}
13772        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag5::W`](W) writer structure"]
13773        impl crate::Writable for PwmPeriodloadFlag5Spec {
13774            type Safety = crate::Unsafe;
13775        }
13776        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG5 to value 0"]
13777        impl crate::Resettable for PwmPeriodloadFlag5Spec {}
13778    }
13779    #[doc = "PWM_PERIOD_VAL5 (rw) register accessor: PWM5 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val5`] module"]
13780    #[doc(alias = "PWM_PERIOD_VAL5")]
13781    pub type PwmPeriodVal5 = crate::Reg<pwm_period_val5::PwmPeriodVal5Spec>;
13782    #[doc = "PWM5 pulse count value"]
13783    pub mod pwm_period_val5 {
13784        #[doc = "Register `PWM_PERIOD_VAL5` reader"]
13785        pub type R = crate::R<PwmPeriodVal5Spec>;
13786        #[doc = "Register `PWM_PERIOD_VAL5` writer"]
13787        pub type W = crate::W<PwmPeriodVal5Spec>;
13788        #[doc = "Field `pwm_period_val_5` reader - Pulse count for stepping mode"]
13789        pub type PwmPeriodVal5R = crate::FieldReader<u16>;
13790        #[doc = "Field `pwm_period_val_5` writer - Pulse count for stepping mode"]
13791        pub type PwmPeriodVal5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13792        impl R {
13793            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
13794            #[inline(always)]
13795            pub fn pwm_period_val_5(&self) -> PwmPeriodVal5R {
13796                PwmPeriodVal5R::new((self.bits & 0xffff) as u16)
13797            }
13798        }
13799        impl W {
13800            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
13801            #[inline(always)]
13802            pub fn pwm_period_val_5(&mut self) -> PwmPeriodVal5W<'_, PwmPeriodVal5Spec> {
13803                PwmPeriodVal5W::new(self, 0)
13804            }
13805        }
13806        #[doc = "PWM5 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13807        pub struct PwmPeriodVal5Spec;
13808        impl crate::RegisterSpec for PwmPeriodVal5Spec {
13809            type Ux = u32;
13810        }
13811        #[doc = "`read()` method returns [`pwm_period_val5::R`](R) reader structure"]
13812        impl crate::Readable for PwmPeriodVal5Spec {}
13813        #[doc = "`write(|w| ..)` method takes [`pwm_period_val5::W`](W) writer structure"]
13814        impl crate::Writable for PwmPeriodVal5Spec {
13815            type Safety = crate::Unsafe;
13816        }
13817        #[doc = "`reset()` method sets PWM_PERIOD_VAL5 to value 0"]
13818        impl crate::Resettable for PwmPeriodVal5Spec {}
13819    }
13820    #[doc = "PWM_PERIODCNT5 (rw) register accessor: PWM5 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt5`] module"]
13821    #[doc(alias = "PWM_PERIODCNT5")]
13822    pub type PwmPeriodcnt5 = crate::Reg<pwm_periodcnt5::PwmPeriodcnt5Spec>;
13823    #[doc = "PWM5 pulse count current value"]
13824    pub mod pwm_periodcnt5 {
13825        #[doc = "Register `PWM_PERIODCNT5` reader"]
13826        pub type R = crate::R<PwmPeriodcnt5Spec>;
13827        #[doc = "Register `PWM_PERIODCNT5` writer"]
13828        pub type W = crate::W<PwmPeriodcnt5Spec>;
13829        #[doc = "Field `pwm_periodcnt_5` reader - Current pulse count"]
13830        pub type PwmPeriodcnt5R = crate::FieldReader<u16>;
13831        impl R {
13832            #[doc = "Bits 0:15 - Current pulse count"]
13833            #[inline(always)]
13834            pub fn pwm_periodcnt_5(&self) -> PwmPeriodcnt5R {
13835                PwmPeriodcnt5R::new((self.bits & 0xffff) as u16)
13836            }
13837        }
13838        impl W {}
13839        #[doc = "PWM5 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13840        pub struct PwmPeriodcnt5Spec;
13841        impl crate::RegisterSpec for PwmPeriodcnt5Spec {
13842            type Ux = u32;
13843        }
13844        #[doc = "`read()` method returns [`pwm_periodcnt5::R`](R) reader structure"]
13845        impl crate::Readable for PwmPeriodcnt5Spec {}
13846        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt5::W`](W) writer structure"]
13847        impl crate::Writable for PwmPeriodcnt5Spec {
13848            type Safety = crate::Unsafe;
13849        }
13850        #[doc = "`reset()` method sets PWM_PERIODCNT5 to value 0"]
13851        impl crate::Resettable for PwmPeriodcnt5Spec {}
13852    }
13853    #[doc = "PWM_EN6 (rw) register accessor: PWM6 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en6`] module"]
13854    #[doc(alias = "PWM_EN6")]
13855    pub type PwmEn6 = crate::Reg<pwm_en6::PwmEn6Spec>;
13856    #[doc = "PWM6 enable"]
13857    pub mod pwm_en6 {
13858        #[doc = "Register `PWM_EN6` reader"]
13859        pub type R = crate::R<PwmEn6Spec>;
13860        #[doc = "Register `PWM_EN6` writer"]
13861        pub type W = crate::W<PwmEn6Spec>;
13862        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
13863        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
13864        pub enum PwmEn6 {
13865            #[doc = "0: PWM disabled, output low"]
13866            Off = 0,
13867            #[doc = "1: PWM enabled"]
13868            On = 1,
13869        }
13870        impl From<PwmEn6> for bool {
13871            #[inline(always)]
13872            fn from(variant: PwmEn6) -> Self {
13873                variant as u8 != 0
13874            }
13875        }
13876        #[doc = "Field `pwm_en_6` reader - PWM0 enable: 0=off; 1=on"]
13877        pub type PwmEn6R = crate::BitReader<PwmEn6>;
13878        impl PwmEn6R {
13879            #[doc = "Get enumerated values variant"]
13880            #[inline(always)]
13881            pub const fn variant(&self) -> PwmEn6 {
13882                match self.bits {
13883                    false => PwmEn6::Off,
13884                    true => PwmEn6::On,
13885                }
13886            }
13887            #[doc = "PWM disabled, output low"]
13888            #[inline(always)]
13889            pub fn is_off(&self) -> bool {
13890                *self == PwmEn6::Off
13891            }
13892            #[doc = "PWM enabled"]
13893            #[inline(always)]
13894            pub fn is_on(&self) -> bool {
13895                *self == PwmEn6::On
13896            }
13897        }
13898        #[doc = "Field `pwm_en_6` writer - PWM0 enable: 0=off; 1=on"]
13899        pub type PwmEn6W<'a, REG> = crate::BitWriter<'a, REG, PwmEn6>;
13900        impl<'a, REG> PwmEn6W<'a, REG>
13901        where
13902            REG: crate::Writable + crate::RegisterSpec,
13903        {
13904            #[doc = "PWM disabled, output low"]
13905            #[inline(always)]
13906            pub fn off(self) -> &'a mut crate::W<REG> {
13907                self.variant(PwmEn6::Off)
13908            }
13909            #[doc = "PWM enabled"]
13910            #[inline(always)]
13911            pub fn on(self) -> &'a mut crate::W<REG> {
13912                self.variant(PwmEn6::On)
13913            }
13914        }
13915        impl R {
13916            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
13917            #[inline(always)]
13918            pub fn pwm_en_6(&self) -> PwmEn6R {
13919                PwmEn6R::new((self.bits & 1) != 0)
13920            }
13921        }
13922        impl W {
13923            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
13924            #[inline(always)]
13925            pub fn pwm_en_6(&mut self) -> PwmEn6W<'_, PwmEn6Spec> {
13926                PwmEn6W::new(self, 0)
13927            }
13928        }
13929        #[doc = "PWM6 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13930        pub struct PwmEn6Spec;
13931        impl crate::RegisterSpec for PwmEn6Spec {
13932            type Ux = u32;
13933        }
13934        #[doc = "`read()` method returns [`pwm_en6::R`](R) reader structure"]
13935        impl crate::Readable for PwmEn6Spec {}
13936        #[doc = "`write(|w| ..)` method takes [`pwm_en6::W`](W) writer structure"]
13937        impl crate::Writable for PwmEn6Spec {
13938            type Safety = crate::Unsafe;
13939        }
13940        #[doc = "`reset()` method sets PWM_EN6 to value 0"]
13941        impl crate::Resettable for PwmEn6Spec {}
13942    }
13943    #[doc = "PWM_PORTITY6 (rw) register accessor: PWM6 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity6`] module"]
13944    #[doc(alias = "PWM_PORTITY6")]
13945    pub type PwmPortity6 = crate::Reg<pwm_portity6::PwmPortity6Spec>;
13946    #[doc = "PWM6 polarity"]
13947    pub mod pwm_portity6 {
13948        #[doc = "Register `PWM_PORTITY6` reader"]
13949        pub type R = crate::R<PwmPortity6Spec>;
13950        #[doc = "Register `PWM_PORTITY6` writer"]
13951        pub type W = crate::W<PwmPortity6Spec>;
13952        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
13953        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
13954        pub enum PwmPoarity6 {
13955            #[doc = "0: Normal polarity"]
13956            Normal = 0,
13957            #[doc = "1: Inverted polarity"]
13958            Inverted = 1,
13959        }
13960        impl From<PwmPoarity6> for bool {
13961            #[inline(always)]
13962            fn from(variant: PwmPoarity6) -> Self {
13963                variant as u8 != 0
13964            }
13965        }
13966        #[doc = "Field `pwm_poarity_6` reader - PWM0 polarity: 0=normal; 1=inverted"]
13967        pub type PwmPoarity6R = crate::BitReader<PwmPoarity6>;
13968        impl PwmPoarity6R {
13969            #[doc = "Get enumerated values variant"]
13970            #[inline(always)]
13971            pub const fn variant(&self) -> PwmPoarity6 {
13972                match self.bits {
13973                    false => PwmPoarity6::Normal,
13974                    true => PwmPoarity6::Inverted,
13975                }
13976            }
13977            #[doc = "Normal polarity"]
13978            #[inline(always)]
13979            pub fn is_normal(&self) -> bool {
13980                *self == PwmPoarity6::Normal
13981            }
13982            #[doc = "Inverted polarity"]
13983            #[inline(always)]
13984            pub fn is_inverted(&self) -> bool {
13985                *self == PwmPoarity6::Inverted
13986            }
13987        }
13988        #[doc = "Field `pwm_poarity_6` writer - PWM0 polarity: 0=normal; 1=inverted"]
13989        pub type PwmPoarity6W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity6>;
13990        impl<'a, REG> PwmPoarity6W<'a, REG>
13991        where
13992            REG: crate::Writable + crate::RegisterSpec,
13993        {
13994            #[doc = "Normal polarity"]
13995            #[inline(always)]
13996            pub fn normal(self) -> &'a mut crate::W<REG> {
13997                self.variant(PwmPoarity6::Normal)
13998            }
13999            #[doc = "Inverted polarity"]
14000            #[inline(always)]
14001            pub fn inverted(self) -> &'a mut crate::W<REG> {
14002                self.variant(PwmPoarity6::Inverted)
14003            }
14004        }
14005        impl R {
14006            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
14007            #[inline(always)]
14008            pub fn pwm_poarity_6(&self) -> PwmPoarity6R {
14009                PwmPoarity6R::new((self.bits & 1) != 0)
14010            }
14011        }
14012        impl W {
14013            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
14014            #[inline(always)]
14015            pub fn pwm_poarity_6(&mut self) -> PwmPoarity6W<'_, PwmPortity6Spec> {
14016                PwmPoarity6W::new(self, 0)
14017            }
14018        }
14019        #[doc = "PWM6 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14020        pub struct PwmPortity6Spec;
14021        impl crate::RegisterSpec for PwmPortity6Spec {
14022            type Ux = u32;
14023        }
14024        #[doc = "`read()` method returns [`pwm_portity6::R`](R) reader structure"]
14025        impl crate::Readable for PwmPortity6Spec {}
14026        #[doc = "`write(|w| ..)` method takes [`pwm_portity6::W`](W) writer structure"]
14027        impl crate::Writable for PwmPortity6Spec {
14028            type Safety = crate::Unsafe;
14029        }
14030        #[doc = "`reset()` method sets PWM_PORTITY6 to value 0"]
14031        impl crate::Resettable for PwmPortity6Spec {}
14032    }
14033    #[doc = "PWM_OEN_CFG6 (rw) register accessor: PWM6 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg6`] module"]
14034    #[doc(alias = "PWM_OEN_CFG6")]
14035    pub type PwmOenCfg6 = crate::Reg<pwm_oen_cfg6::PwmOenCfg6Spec>;
14036    #[doc = "PWM6 high-impedance config"]
14037    pub mod pwm_oen_cfg6 {
14038        #[doc = "Register `PWM_OEN_CFG6` reader"]
14039        pub type R = crate::R<PwmOenCfg6Spec>;
14040        #[doc = "Register `PWM_OEN_CFG6` writer"]
14041        pub type W = crate::W<PwmOenCfg6Spec>;
14042        #[doc = "Field `pwm_oen_cfg_6` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14043        pub type PwmOenCfg6R = crate::BitReader;
14044        #[doc = "Field `pwm_oen_cfg_6` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14045        pub type PwmOenCfg6W<'a, REG> = crate::BitWriter<'a, REG>;
14046        impl R {
14047            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14048            #[inline(always)]
14049            pub fn pwm_oen_cfg_6(&self) -> PwmOenCfg6R {
14050                PwmOenCfg6R::new((self.bits & 1) != 0)
14051            }
14052        }
14053        impl W {
14054            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14055            #[inline(always)]
14056            pub fn pwm_oen_cfg_6(&mut self) -> PwmOenCfg6W<'_, PwmOenCfg6Spec> {
14057                PwmOenCfg6W::new(self, 0)
14058            }
14059        }
14060        #[doc = "PWM6 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14061        pub struct PwmOenCfg6Spec;
14062        impl crate::RegisterSpec for PwmOenCfg6Spec {
14063            type Ux = u32;
14064        }
14065        #[doc = "`read()` method returns [`pwm_oen_cfg6::R`](R) reader structure"]
14066        impl crate::Readable for PwmOenCfg6Spec {}
14067        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg6::W`](W) writer structure"]
14068        impl crate::Writable for PwmOenCfg6Spec {
14069            type Safety = crate::Unsafe;
14070        }
14071        #[doc = "`reset()` method sets PWM_OEN_CFG6 to value 0"]
14072        impl crate::Resettable for PwmOenCfg6Spec {}
14073    }
14074    #[doc = "PWM_OFFSET_L6 (rw) register accessor: PWM6 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l6`] module"]
14075    #[doc(alias = "PWM_OFFSET_L6")]
14076    pub type PwmOffsetL6 = crate::Reg<pwm_offset_l6::PwmOffsetL6Spec>;
14077    #[doc = "PWM6 phase offset low 16 bits"]
14078    pub mod pwm_offset_l6 {
14079        #[doc = "Register `PWM_OFFSET_L6` reader"]
14080        pub type R = crate::R<PwmOffsetL6Spec>;
14081        #[doc = "Register `PWM_OFFSET_L6` writer"]
14082        pub type W = crate::W<PwmOffsetL6Spec>;
14083        #[doc = "Field `pwm_offset_l_6` reader - PWM0 phase offset low 16 bits"]
14084        pub type PwmOffsetL6R = crate::FieldReader<u16>;
14085        #[doc = "Field `pwm_offset_l_6` writer - PWM0 phase offset low 16 bits"]
14086        pub type PwmOffsetL6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14087        impl R {
14088            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
14089            #[inline(always)]
14090            pub fn pwm_offset_l_6(&self) -> PwmOffsetL6R {
14091                PwmOffsetL6R::new((self.bits & 0xffff) as u16)
14092            }
14093        }
14094        impl W {
14095            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
14096            #[inline(always)]
14097            pub fn pwm_offset_l_6(&mut self) -> PwmOffsetL6W<'_, PwmOffsetL6Spec> {
14098                PwmOffsetL6W::new(self, 0)
14099            }
14100        }
14101        #[doc = "PWM6 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14102        pub struct PwmOffsetL6Spec;
14103        impl crate::RegisterSpec for PwmOffsetL6Spec {
14104            type Ux = u32;
14105        }
14106        #[doc = "`read()` method returns [`pwm_offset_l6::R`](R) reader structure"]
14107        impl crate::Readable for PwmOffsetL6Spec {}
14108        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l6::W`](W) writer structure"]
14109        impl crate::Writable for PwmOffsetL6Spec {
14110            type Safety = crate::Unsafe;
14111        }
14112        #[doc = "`reset()` method sets PWM_OFFSET_L6 to value 0"]
14113        impl crate::Resettable for PwmOffsetL6Spec {}
14114    }
14115    #[doc = "PWM_OFFSET_H6 (rw) register accessor: PWM6 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h6`] module"]
14116    #[doc(alias = "PWM_OFFSET_H6")]
14117    pub type PwmOffsetH6 = crate::Reg<pwm_offset_h6::PwmOffsetH6Spec>;
14118    #[doc = "PWM6 phase offset high 16 bits"]
14119    pub mod pwm_offset_h6 {
14120        #[doc = "Register `PWM_OFFSET_H6` reader"]
14121        pub type R = crate::R<PwmOffsetH6Spec>;
14122        #[doc = "Register `PWM_OFFSET_H6` writer"]
14123        pub type W = crate::W<PwmOffsetH6Spec>;
14124        #[doc = "Field `pwm_offset_h_6` reader - PWM0 phase offset high 16 bits"]
14125        pub type PwmOffsetH6R = crate::FieldReader<u16>;
14126        #[doc = "Field `pwm_offset_h_6` writer - PWM0 phase offset high 16 bits"]
14127        pub type PwmOffsetH6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14128        impl R {
14129            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
14130            #[inline(always)]
14131            pub fn pwm_offset_h_6(&self) -> PwmOffsetH6R {
14132                PwmOffsetH6R::new((self.bits & 0xffff) as u16)
14133            }
14134        }
14135        impl W {
14136            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
14137            #[inline(always)]
14138            pub fn pwm_offset_h_6(&mut self) -> PwmOffsetH6W<'_, PwmOffsetH6Spec> {
14139                PwmOffsetH6W::new(self, 0)
14140            }
14141        }
14142        #[doc = "PWM6 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14143        pub struct PwmOffsetH6Spec;
14144        impl crate::RegisterSpec for PwmOffsetH6Spec {
14145            type Ux = u32;
14146        }
14147        #[doc = "`read()` method returns [`pwm_offset_h6::R`](R) reader structure"]
14148        impl crate::Readable for PwmOffsetH6Spec {}
14149        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h6::W`](W) writer structure"]
14150        impl crate::Writable for PwmOffsetH6Spec {
14151            type Safety = crate::Unsafe;
14152        }
14153        #[doc = "`reset()` method sets PWM_OFFSET_H6 to value 0"]
14154        impl crate::Resettable for PwmOffsetH6Spec {}
14155    }
14156    #[doc = "PWM_FREQ_L6 (rw) register accessor: PWM6 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l6`] module"]
14157    #[doc(alias = "PWM_FREQ_L6")]
14158    pub type PwmFreqL6 = crate::Reg<pwm_freq_l6::PwmFreqL6Spec>;
14159    #[doc = "PWM6 frequency low 16 bits"]
14160    pub mod pwm_freq_l6 {
14161        #[doc = "Register `PWM_FREQ_L6` reader"]
14162        pub type R = crate::R<PwmFreqL6Spec>;
14163        #[doc = "Register `PWM_FREQ_L6` writer"]
14164        pub type W = crate::W<PwmFreqL6Spec>;
14165        #[doc = "Field `pwm_freq_l_6` reader - PWM0 clock divider low 16 bits"]
14166        pub type PwmFreqL6R = crate::FieldReader<u16>;
14167        #[doc = "Field `pwm_freq_l_6` writer - PWM0 clock divider low 16 bits"]
14168        pub type PwmFreqL6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14169        impl R {
14170            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
14171            #[inline(always)]
14172            pub fn pwm_freq_l_6(&self) -> PwmFreqL6R {
14173                PwmFreqL6R::new((self.bits & 0xffff) as u16)
14174            }
14175        }
14176        impl W {
14177            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
14178            #[inline(always)]
14179            pub fn pwm_freq_l_6(&mut self) -> PwmFreqL6W<'_, PwmFreqL6Spec> {
14180                PwmFreqL6W::new(self, 0)
14181            }
14182        }
14183        #[doc = "PWM6 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14184        pub struct PwmFreqL6Spec;
14185        impl crate::RegisterSpec for PwmFreqL6Spec {
14186            type Ux = u32;
14187        }
14188        #[doc = "`read()` method returns [`pwm_freq_l6::R`](R) reader structure"]
14189        impl crate::Readable for PwmFreqL6Spec {}
14190        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l6::W`](W) writer structure"]
14191        impl crate::Writable for PwmFreqL6Spec {
14192            type Safety = crate::Unsafe;
14193        }
14194        #[doc = "`reset()` method sets PWM_FREQ_L6 to value 0"]
14195        impl crate::Resettable for PwmFreqL6Spec {}
14196    }
14197    #[doc = "PWM_FREQ_H6 (rw) register accessor: PWM6 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h6`] module"]
14198    #[doc(alias = "PWM_FREQ_H6")]
14199    pub type PwmFreqH6 = crate::Reg<pwm_freq_h6::PwmFreqH6Spec>;
14200    #[doc = "PWM6 frequency high 16 bits"]
14201    pub mod pwm_freq_h6 {
14202        #[doc = "Register `PWM_FREQ_H6` reader"]
14203        pub type R = crate::R<PwmFreqH6Spec>;
14204        #[doc = "Register `PWM_FREQ_H6` writer"]
14205        pub type W = crate::W<PwmFreqH6Spec>;
14206        #[doc = "Field `pwm_freq_h_6` reader - PWM0 clock divider high 16 bits"]
14207        pub type PwmFreqH6R = crate::FieldReader<u16>;
14208        #[doc = "Field `pwm_freq_h_6` writer - PWM0 clock divider high 16 bits"]
14209        pub type PwmFreqH6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14210        impl R {
14211            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
14212            #[inline(always)]
14213            pub fn pwm_freq_h_6(&self) -> PwmFreqH6R {
14214                PwmFreqH6R::new((self.bits & 0xffff) as u16)
14215            }
14216        }
14217        impl W {
14218            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
14219            #[inline(always)]
14220            pub fn pwm_freq_h_6(&mut self) -> PwmFreqH6W<'_, PwmFreqH6Spec> {
14221                PwmFreqH6W::new(self, 0)
14222            }
14223        }
14224        #[doc = "PWM6 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14225        pub struct PwmFreqH6Spec;
14226        impl crate::RegisterSpec for PwmFreqH6Spec {
14227            type Ux = u32;
14228        }
14229        #[doc = "`read()` method returns [`pwm_freq_h6::R`](R) reader structure"]
14230        impl crate::Readable for PwmFreqH6Spec {}
14231        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h6::W`](W) writer structure"]
14232        impl crate::Writable for PwmFreqH6Spec {
14233            type Safety = crate::Unsafe;
14234        }
14235        #[doc = "`reset()` method sets PWM_FREQ_H6 to value 0"]
14236        impl crate::Resettable for PwmFreqH6Spec {}
14237    }
14238    #[doc = "PWM_DUTY_L6 (rw) register accessor: PWM6 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l6`] module"]
14239    #[doc(alias = "PWM_DUTY_L6")]
14240    pub type PwmDutyL6 = crate::Reg<pwm_duty_l6::PwmDutyL6Spec>;
14241    #[doc = "PWM6 duty cycle low 16 bits"]
14242    pub mod pwm_duty_l6 {
14243        #[doc = "Register `PWM_DUTY_L6` reader"]
14244        pub type R = crate::R<PwmDutyL6Spec>;
14245        #[doc = "Register `PWM_DUTY_L6` writer"]
14246        pub type W = crate::W<PwmDutyL6Spec>;
14247        #[doc = "Field `pwm_duty_l_6` reader - PWM0 duty cycle low 16 bits"]
14248        pub type PwmDutyL6R = crate::FieldReader<u16>;
14249        #[doc = "Field `pwm_duty_l_6` writer - PWM0 duty cycle low 16 bits"]
14250        pub type PwmDutyL6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14251        impl R {
14252            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
14253            #[inline(always)]
14254            pub fn pwm_duty_l_6(&self) -> PwmDutyL6R {
14255                PwmDutyL6R::new((self.bits & 0xffff) as u16)
14256            }
14257        }
14258        impl W {
14259            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
14260            #[inline(always)]
14261            pub fn pwm_duty_l_6(&mut self) -> PwmDutyL6W<'_, PwmDutyL6Spec> {
14262                PwmDutyL6W::new(self, 0)
14263            }
14264        }
14265        #[doc = "PWM6 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14266        pub struct PwmDutyL6Spec;
14267        impl crate::RegisterSpec for PwmDutyL6Spec {
14268            type Ux = u32;
14269        }
14270        #[doc = "`read()` method returns [`pwm_duty_l6::R`](R) reader structure"]
14271        impl crate::Readable for PwmDutyL6Spec {}
14272        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l6::W`](W) writer structure"]
14273        impl crate::Writable for PwmDutyL6Spec {
14274            type Safety = crate::Unsafe;
14275        }
14276        #[doc = "`reset()` method sets PWM_DUTY_L6 to value 0"]
14277        impl crate::Resettable for PwmDutyL6Spec {}
14278    }
14279    #[doc = "PWM_DUTY_H6 (rw) register accessor: PWM6 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h6`] module"]
14280    #[doc(alias = "PWM_DUTY_H6")]
14281    pub type PwmDutyH6 = crate::Reg<pwm_duty_h6::PwmDutyH6Spec>;
14282    #[doc = "PWM6 duty cycle high 16 bits"]
14283    pub mod pwm_duty_h6 {
14284        #[doc = "Register `PWM_DUTY_H6` reader"]
14285        pub type R = crate::R<PwmDutyH6Spec>;
14286        #[doc = "Register `PWM_DUTY_H6` writer"]
14287        pub type W = crate::W<PwmDutyH6Spec>;
14288        #[doc = "Field `pwm_duty_h_6` reader - PWM0 duty cycle high 16 bits"]
14289        pub type PwmDutyH6R = crate::FieldReader<u16>;
14290        #[doc = "Field `pwm_duty_h_6` writer - PWM0 duty cycle high 16 bits"]
14291        pub type PwmDutyH6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14292        impl R {
14293            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
14294            #[inline(always)]
14295            pub fn pwm_duty_h_6(&self) -> PwmDutyH6R {
14296                PwmDutyH6R::new((self.bits & 0xffff) as u16)
14297            }
14298        }
14299        impl W {
14300            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
14301            #[inline(always)]
14302            pub fn pwm_duty_h_6(&mut self) -> PwmDutyH6W<'_, PwmDutyH6Spec> {
14303                PwmDutyH6W::new(self, 0)
14304            }
14305        }
14306        #[doc = "PWM6 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14307        pub struct PwmDutyH6Spec;
14308        impl crate::RegisterSpec for PwmDutyH6Spec {
14309            type Ux = u32;
14310        }
14311        #[doc = "`read()` method returns [`pwm_duty_h6::R`](R) reader structure"]
14312        impl crate::Readable for PwmDutyH6Spec {}
14313        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h6::W`](W) writer structure"]
14314        impl crate::Writable for PwmDutyH6Spec {
14315            type Safety = crate::Unsafe;
14316        }
14317        #[doc = "`reset()` method sets PWM_DUTY_H6 to value 0"]
14318        impl crate::Resettable for PwmDutyH6Spec {}
14319    }
14320    #[doc = "PWM_PERIODLOAD_FLAG6 (rw) register accessor: PWM6 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag6`] module"]
14321    #[doc(alias = "PWM_PERIODLOAD_FLAG6")]
14322    pub type PwmPeriodloadFlag6 = crate::Reg<pwm_periodload_flag6::PwmPeriodloadFlag6Spec>;
14323    #[doc = "PWM6 period load flag"]
14324    pub mod pwm_periodload_flag6 {
14325        #[doc = "Register `PWM_PERIODLOAD_FLAG6` reader"]
14326        pub type R = crate::R<PwmPeriodloadFlag6Spec>;
14327        #[doc = "Register `PWM_PERIODLOAD_FLAG6` writer"]
14328        pub type W = crate::W<PwmPeriodloadFlag6Spec>;
14329        #[doc = "Field `pwm_periodload_flag_6` reader - Period load complete flag"]
14330        pub type PwmPeriodloadFlag6R = crate::BitReader;
14331        impl R {
14332            #[doc = "Bit 0 - Period load complete flag"]
14333            #[inline(always)]
14334            pub fn pwm_periodload_flag_6(&self) -> PwmPeriodloadFlag6R {
14335                PwmPeriodloadFlag6R::new((self.bits & 1) != 0)
14336            }
14337        }
14338        impl W {}
14339        #[doc = "PWM6 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14340        pub struct PwmPeriodloadFlag6Spec;
14341        impl crate::RegisterSpec for PwmPeriodloadFlag6Spec {
14342            type Ux = u32;
14343        }
14344        #[doc = "`read()` method returns [`pwm_periodload_flag6::R`](R) reader structure"]
14345        impl crate::Readable for PwmPeriodloadFlag6Spec {}
14346        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag6::W`](W) writer structure"]
14347        impl crate::Writable for PwmPeriodloadFlag6Spec {
14348            type Safety = crate::Unsafe;
14349        }
14350        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG6 to value 0"]
14351        impl crate::Resettable for PwmPeriodloadFlag6Spec {}
14352    }
14353    #[doc = "PWM_PERIOD_VAL6 (rw) register accessor: PWM6 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val6`] module"]
14354    #[doc(alias = "PWM_PERIOD_VAL6")]
14355    pub type PwmPeriodVal6 = crate::Reg<pwm_period_val6::PwmPeriodVal6Spec>;
14356    #[doc = "PWM6 pulse count value"]
14357    pub mod pwm_period_val6 {
14358        #[doc = "Register `PWM_PERIOD_VAL6` reader"]
14359        pub type R = crate::R<PwmPeriodVal6Spec>;
14360        #[doc = "Register `PWM_PERIOD_VAL6` writer"]
14361        pub type W = crate::W<PwmPeriodVal6Spec>;
14362        #[doc = "Field `pwm_period_val_6` reader - Pulse count for stepping mode"]
14363        pub type PwmPeriodVal6R = crate::FieldReader<u16>;
14364        #[doc = "Field `pwm_period_val_6` writer - Pulse count for stepping mode"]
14365        pub type PwmPeriodVal6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14366        impl R {
14367            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
14368            #[inline(always)]
14369            pub fn pwm_period_val_6(&self) -> PwmPeriodVal6R {
14370                PwmPeriodVal6R::new((self.bits & 0xffff) as u16)
14371            }
14372        }
14373        impl W {
14374            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
14375            #[inline(always)]
14376            pub fn pwm_period_val_6(&mut self) -> PwmPeriodVal6W<'_, PwmPeriodVal6Spec> {
14377                PwmPeriodVal6W::new(self, 0)
14378            }
14379        }
14380        #[doc = "PWM6 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14381        pub struct PwmPeriodVal6Spec;
14382        impl crate::RegisterSpec for PwmPeriodVal6Spec {
14383            type Ux = u32;
14384        }
14385        #[doc = "`read()` method returns [`pwm_period_val6::R`](R) reader structure"]
14386        impl crate::Readable for PwmPeriodVal6Spec {}
14387        #[doc = "`write(|w| ..)` method takes [`pwm_period_val6::W`](W) writer structure"]
14388        impl crate::Writable for PwmPeriodVal6Spec {
14389            type Safety = crate::Unsafe;
14390        }
14391        #[doc = "`reset()` method sets PWM_PERIOD_VAL6 to value 0"]
14392        impl crate::Resettable for PwmPeriodVal6Spec {}
14393    }
14394    #[doc = "PWM_PERIODCNT6 (rw) register accessor: PWM6 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt6`] module"]
14395    #[doc(alias = "PWM_PERIODCNT6")]
14396    pub type PwmPeriodcnt6 = crate::Reg<pwm_periodcnt6::PwmPeriodcnt6Spec>;
14397    #[doc = "PWM6 pulse count current value"]
14398    pub mod pwm_periodcnt6 {
14399        #[doc = "Register `PWM_PERIODCNT6` reader"]
14400        pub type R = crate::R<PwmPeriodcnt6Spec>;
14401        #[doc = "Register `PWM_PERIODCNT6` writer"]
14402        pub type W = crate::W<PwmPeriodcnt6Spec>;
14403        #[doc = "Field `pwm_periodcnt_6` reader - Current pulse count"]
14404        pub type PwmPeriodcnt6R = crate::FieldReader<u16>;
14405        impl R {
14406            #[doc = "Bits 0:15 - Current pulse count"]
14407            #[inline(always)]
14408            pub fn pwm_periodcnt_6(&self) -> PwmPeriodcnt6R {
14409                PwmPeriodcnt6R::new((self.bits & 0xffff) as u16)
14410            }
14411        }
14412        impl W {}
14413        #[doc = "PWM6 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14414        pub struct PwmPeriodcnt6Spec;
14415        impl crate::RegisterSpec for PwmPeriodcnt6Spec {
14416            type Ux = u32;
14417        }
14418        #[doc = "`read()` method returns [`pwm_periodcnt6::R`](R) reader structure"]
14419        impl crate::Readable for PwmPeriodcnt6Spec {}
14420        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt6::W`](W) writer structure"]
14421        impl crate::Writable for PwmPeriodcnt6Spec {
14422            type Safety = crate::Unsafe;
14423        }
14424        #[doc = "`reset()` method sets PWM_PERIODCNT6 to value 0"]
14425        impl crate::Resettable for PwmPeriodcnt6Spec {}
14426    }
14427    #[doc = "PWM_EN7 (rw) register accessor: PWM7 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en7`] module"]
14428    #[doc(alias = "PWM_EN7")]
14429    pub type PwmEn7 = crate::Reg<pwm_en7::PwmEn7Spec>;
14430    #[doc = "PWM7 enable"]
14431    pub mod pwm_en7 {
14432        #[doc = "Register `PWM_EN7` reader"]
14433        pub type R = crate::R<PwmEn7Spec>;
14434        #[doc = "Register `PWM_EN7` writer"]
14435        pub type W = crate::W<PwmEn7Spec>;
14436        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
14437        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
14438        pub enum PwmEn7 {
14439            #[doc = "0: PWM disabled, output low"]
14440            Off = 0,
14441            #[doc = "1: PWM enabled"]
14442            On = 1,
14443        }
14444        impl From<PwmEn7> for bool {
14445            #[inline(always)]
14446            fn from(variant: PwmEn7) -> Self {
14447                variant as u8 != 0
14448            }
14449        }
14450        #[doc = "Field `pwm_en_7` reader - PWM0 enable: 0=off; 1=on"]
14451        pub type PwmEn7R = crate::BitReader<PwmEn7>;
14452        impl PwmEn7R {
14453            #[doc = "Get enumerated values variant"]
14454            #[inline(always)]
14455            pub const fn variant(&self) -> PwmEn7 {
14456                match self.bits {
14457                    false => PwmEn7::Off,
14458                    true => PwmEn7::On,
14459                }
14460            }
14461            #[doc = "PWM disabled, output low"]
14462            #[inline(always)]
14463            pub fn is_off(&self) -> bool {
14464                *self == PwmEn7::Off
14465            }
14466            #[doc = "PWM enabled"]
14467            #[inline(always)]
14468            pub fn is_on(&self) -> bool {
14469                *self == PwmEn7::On
14470            }
14471        }
14472        #[doc = "Field `pwm_en_7` writer - PWM0 enable: 0=off; 1=on"]
14473        pub type PwmEn7W<'a, REG> = crate::BitWriter<'a, REG, PwmEn7>;
14474        impl<'a, REG> PwmEn7W<'a, REG>
14475        where
14476            REG: crate::Writable + crate::RegisterSpec,
14477        {
14478            #[doc = "PWM disabled, output low"]
14479            #[inline(always)]
14480            pub fn off(self) -> &'a mut crate::W<REG> {
14481                self.variant(PwmEn7::Off)
14482            }
14483            #[doc = "PWM enabled"]
14484            #[inline(always)]
14485            pub fn on(self) -> &'a mut crate::W<REG> {
14486                self.variant(PwmEn7::On)
14487            }
14488        }
14489        impl R {
14490            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
14491            #[inline(always)]
14492            pub fn pwm_en_7(&self) -> PwmEn7R {
14493                PwmEn7R::new((self.bits & 1) != 0)
14494            }
14495        }
14496        impl W {
14497            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
14498            #[inline(always)]
14499            pub fn pwm_en_7(&mut self) -> PwmEn7W<'_, PwmEn7Spec> {
14500                PwmEn7W::new(self, 0)
14501            }
14502        }
14503        #[doc = "PWM7 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14504        pub struct PwmEn7Spec;
14505        impl crate::RegisterSpec for PwmEn7Spec {
14506            type Ux = u32;
14507        }
14508        #[doc = "`read()` method returns [`pwm_en7::R`](R) reader structure"]
14509        impl crate::Readable for PwmEn7Spec {}
14510        #[doc = "`write(|w| ..)` method takes [`pwm_en7::W`](W) writer structure"]
14511        impl crate::Writable for PwmEn7Spec {
14512            type Safety = crate::Unsafe;
14513        }
14514        #[doc = "`reset()` method sets PWM_EN7 to value 0"]
14515        impl crate::Resettable for PwmEn7Spec {}
14516    }
14517    #[doc = "PWM_PORTITY7 (rw) register accessor: PWM7 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity7`] module"]
14518    #[doc(alias = "PWM_PORTITY7")]
14519    pub type PwmPortity7 = crate::Reg<pwm_portity7::PwmPortity7Spec>;
14520    #[doc = "PWM7 polarity"]
14521    pub mod pwm_portity7 {
14522        #[doc = "Register `PWM_PORTITY7` reader"]
14523        pub type R = crate::R<PwmPortity7Spec>;
14524        #[doc = "Register `PWM_PORTITY7` writer"]
14525        pub type W = crate::W<PwmPortity7Spec>;
14526        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
14527        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
14528        pub enum PwmPoarity7 {
14529            #[doc = "0: Normal polarity"]
14530            Normal = 0,
14531            #[doc = "1: Inverted polarity"]
14532            Inverted = 1,
14533        }
14534        impl From<PwmPoarity7> for bool {
14535            #[inline(always)]
14536            fn from(variant: PwmPoarity7) -> Self {
14537                variant as u8 != 0
14538            }
14539        }
14540        #[doc = "Field `pwm_poarity_7` reader - PWM0 polarity: 0=normal; 1=inverted"]
14541        pub type PwmPoarity7R = crate::BitReader<PwmPoarity7>;
14542        impl PwmPoarity7R {
14543            #[doc = "Get enumerated values variant"]
14544            #[inline(always)]
14545            pub const fn variant(&self) -> PwmPoarity7 {
14546                match self.bits {
14547                    false => PwmPoarity7::Normal,
14548                    true => PwmPoarity7::Inverted,
14549                }
14550            }
14551            #[doc = "Normal polarity"]
14552            #[inline(always)]
14553            pub fn is_normal(&self) -> bool {
14554                *self == PwmPoarity7::Normal
14555            }
14556            #[doc = "Inverted polarity"]
14557            #[inline(always)]
14558            pub fn is_inverted(&self) -> bool {
14559                *self == PwmPoarity7::Inverted
14560            }
14561        }
14562        #[doc = "Field `pwm_poarity_7` writer - PWM0 polarity: 0=normal; 1=inverted"]
14563        pub type PwmPoarity7W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity7>;
14564        impl<'a, REG> PwmPoarity7W<'a, REG>
14565        where
14566            REG: crate::Writable + crate::RegisterSpec,
14567        {
14568            #[doc = "Normal polarity"]
14569            #[inline(always)]
14570            pub fn normal(self) -> &'a mut crate::W<REG> {
14571                self.variant(PwmPoarity7::Normal)
14572            }
14573            #[doc = "Inverted polarity"]
14574            #[inline(always)]
14575            pub fn inverted(self) -> &'a mut crate::W<REG> {
14576                self.variant(PwmPoarity7::Inverted)
14577            }
14578        }
14579        impl R {
14580            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
14581            #[inline(always)]
14582            pub fn pwm_poarity_7(&self) -> PwmPoarity7R {
14583                PwmPoarity7R::new((self.bits & 1) != 0)
14584            }
14585        }
14586        impl W {
14587            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
14588            #[inline(always)]
14589            pub fn pwm_poarity_7(&mut self) -> PwmPoarity7W<'_, PwmPortity7Spec> {
14590                PwmPoarity7W::new(self, 0)
14591            }
14592        }
14593        #[doc = "PWM7 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14594        pub struct PwmPortity7Spec;
14595        impl crate::RegisterSpec for PwmPortity7Spec {
14596            type Ux = u32;
14597        }
14598        #[doc = "`read()` method returns [`pwm_portity7::R`](R) reader structure"]
14599        impl crate::Readable for PwmPortity7Spec {}
14600        #[doc = "`write(|w| ..)` method takes [`pwm_portity7::W`](W) writer structure"]
14601        impl crate::Writable for PwmPortity7Spec {
14602            type Safety = crate::Unsafe;
14603        }
14604        #[doc = "`reset()` method sets PWM_PORTITY7 to value 0"]
14605        impl crate::Resettable for PwmPortity7Spec {}
14606    }
14607    #[doc = "PWM_OEN_CFG7 (rw) register accessor: PWM7 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg7`] module"]
14608    #[doc(alias = "PWM_OEN_CFG7")]
14609    pub type PwmOenCfg7 = crate::Reg<pwm_oen_cfg7::PwmOenCfg7Spec>;
14610    #[doc = "PWM7 high-impedance config"]
14611    pub mod pwm_oen_cfg7 {
14612        #[doc = "Register `PWM_OEN_CFG7` reader"]
14613        pub type R = crate::R<PwmOenCfg7Spec>;
14614        #[doc = "Register `PWM_OEN_CFG7` writer"]
14615        pub type W = crate::W<PwmOenCfg7Spec>;
14616        #[doc = "Field `pwm_oen_cfg_7` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14617        pub type PwmOenCfg7R = crate::BitReader;
14618        #[doc = "Field `pwm_oen_cfg_7` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14619        pub type PwmOenCfg7W<'a, REG> = crate::BitWriter<'a, REG>;
14620        impl R {
14621            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14622            #[inline(always)]
14623            pub fn pwm_oen_cfg_7(&self) -> PwmOenCfg7R {
14624                PwmOenCfg7R::new((self.bits & 1) != 0)
14625            }
14626        }
14627        impl W {
14628            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14629            #[inline(always)]
14630            pub fn pwm_oen_cfg_7(&mut self) -> PwmOenCfg7W<'_, PwmOenCfg7Spec> {
14631                PwmOenCfg7W::new(self, 0)
14632            }
14633        }
14634        #[doc = "PWM7 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14635        pub struct PwmOenCfg7Spec;
14636        impl crate::RegisterSpec for PwmOenCfg7Spec {
14637            type Ux = u32;
14638        }
14639        #[doc = "`read()` method returns [`pwm_oen_cfg7::R`](R) reader structure"]
14640        impl crate::Readable for PwmOenCfg7Spec {}
14641        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg7::W`](W) writer structure"]
14642        impl crate::Writable for PwmOenCfg7Spec {
14643            type Safety = crate::Unsafe;
14644        }
14645        #[doc = "`reset()` method sets PWM_OEN_CFG7 to value 0"]
14646        impl crate::Resettable for PwmOenCfg7Spec {}
14647    }
14648    #[doc = "PWM_OFFSET_L7 (rw) register accessor: PWM7 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l7`] module"]
14649    #[doc(alias = "PWM_OFFSET_L7")]
14650    pub type PwmOffsetL7 = crate::Reg<pwm_offset_l7::PwmOffsetL7Spec>;
14651    #[doc = "PWM7 phase offset low 16 bits"]
14652    pub mod pwm_offset_l7 {
14653        #[doc = "Register `PWM_OFFSET_L7` reader"]
14654        pub type R = crate::R<PwmOffsetL7Spec>;
14655        #[doc = "Register `PWM_OFFSET_L7` writer"]
14656        pub type W = crate::W<PwmOffsetL7Spec>;
14657        #[doc = "Field `pwm_offset_l_7` reader - PWM0 phase offset low 16 bits"]
14658        pub type PwmOffsetL7R = crate::FieldReader<u16>;
14659        #[doc = "Field `pwm_offset_l_7` writer - PWM0 phase offset low 16 bits"]
14660        pub type PwmOffsetL7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14661        impl R {
14662            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
14663            #[inline(always)]
14664            pub fn pwm_offset_l_7(&self) -> PwmOffsetL7R {
14665                PwmOffsetL7R::new((self.bits & 0xffff) as u16)
14666            }
14667        }
14668        impl W {
14669            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
14670            #[inline(always)]
14671            pub fn pwm_offset_l_7(&mut self) -> PwmOffsetL7W<'_, PwmOffsetL7Spec> {
14672                PwmOffsetL7W::new(self, 0)
14673            }
14674        }
14675        #[doc = "PWM7 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14676        pub struct PwmOffsetL7Spec;
14677        impl crate::RegisterSpec for PwmOffsetL7Spec {
14678            type Ux = u32;
14679        }
14680        #[doc = "`read()` method returns [`pwm_offset_l7::R`](R) reader structure"]
14681        impl crate::Readable for PwmOffsetL7Spec {}
14682        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l7::W`](W) writer structure"]
14683        impl crate::Writable for PwmOffsetL7Spec {
14684            type Safety = crate::Unsafe;
14685        }
14686        #[doc = "`reset()` method sets PWM_OFFSET_L7 to value 0"]
14687        impl crate::Resettable for PwmOffsetL7Spec {}
14688    }
14689    #[doc = "PWM_OFFSET_H7 (rw) register accessor: PWM7 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h7`] module"]
14690    #[doc(alias = "PWM_OFFSET_H7")]
14691    pub type PwmOffsetH7 = crate::Reg<pwm_offset_h7::PwmOffsetH7Spec>;
14692    #[doc = "PWM7 phase offset high 16 bits"]
14693    pub mod pwm_offset_h7 {
14694        #[doc = "Register `PWM_OFFSET_H7` reader"]
14695        pub type R = crate::R<PwmOffsetH7Spec>;
14696        #[doc = "Register `PWM_OFFSET_H7` writer"]
14697        pub type W = crate::W<PwmOffsetH7Spec>;
14698        #[doc = "Field `pwm_offset_h_7` reader - PWM0 phase offset high 16 bits"]
14699        pub type PwmOffsetH7R = crate::FieldReader<u16>;
14700        #[doc = "Field `pwm_offset_h_7` writer - PWM0 phase offset high 16 bits"]
14701        pub type PwmOffsetH7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14702        impl R {
14703            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
14704            #[inline(always)]
14705            pub fn pwm_offset_h_7(&self) -> PwmOffsetH7R {
14706                PwmOffsetH7R::new((self.bits & 0xffff) as u16)
14707            }
14708        }
14709        impl W {
14710            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
14711            #[inline(always)]
14712            pub fn pwm_offset_h_7(&mut self) -> PwmOffsetH7W<'_, PwmOffsetH7Spec> {
14713                PwmOffsetH7W::new(self, 0)
14714            }
14715        }
14716        #[doc = "PWM7 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14717        pub struct PwmOffsetH7Spec;
14718        impl crate::RegisterSpec for PwmOffsetH7Spec {
14719            type Ux = u32;
14720        }
14721        #[doc = "`read()` method returns [`pwm_offset_h7::R`](R) reader structure"]
14722        impl crate::Readable for PwmOffsetH7Spec {}
14723        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h7::W`](W) writer structure"]
14724        impl crate::Writable for PwmOffsetH7Spec {
14725            type Safety = crate::Unsafe;
14726        }
14727        #[doc = "`reset()` method sets PWM_OFFSET_H7 to value 0"]
14728        impl crate::Resettable for PwmOffsetH7Spec {}
14729    }
14730    #[doc = "PWM_FREQ_L7 (rw) register accessor: PWM7 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l7`] module"]
14731    #[doc(alias = "PWM_FREQ_L7")]
14732    pub type PwmFreqL7 = crate::Reg<pwm_freq_l7::PwmFreqL7Spec>;
14733    #[doc = "PWM7 frequency low 16 bits"]
14734    pub mod pwm_freq_l7 {
14735        #[doc = "Register `PWM_FREQ_L7` reader"]
14736        pub type R = crate::R<PwmFreqL7Spec>;
14737        #[doc = "Register `PWM_FREQ_L7` writer"]
14738        pub type W = crate::W<PwmFreqL7Spec>;
14739        #[doc = "Field `pwm_freq_l_7` reader - PWM0 clock divider low 16 bits"]
14740        pub type PwmFreqL7R = crate::FieldReader<u16>;
14741        #[doc = "Field `pwm_freq_l_7` writer - PWM0 clock divider low 16 bits"]
14742        pub type PwmFreqL7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14743        impl R {
14744            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
14745            #[inline(always)]
14746            pub fn pwm_freq_l_7(&self) -> PwmFreqL7R {
14747                PwmFreqL7R::new((self.bits & 0xffff) as u16)
14748            }
14749        }
14750        impl W {
14751            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
14752            #[inline(always)]
14753            pub fn pwm_freq_l_7(&mut self) -> PwmFreqL7W<'_, PwmFreqL7Spec> {
14754                PwmFreqL7W::new(self, 0)
14755            }
14756        }
14757        #[doc = "PWM7 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14758        pub struct PwmFreqL7Spec;
14759        impl crate::RegisterSpec for PwmFreqL7Spec {
14760            type Ux = u32;
14761        }
14762        #[doc = "`read()` method returns [`pwm_freq_l7::R`](R) reader structure"]
14763        impl crate::Readable for PwmFreqL7Spec {}
14764        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l7::W`](W) writer structure"]
14765        impl crate::Writable for PwmFreqL7Spec {
14766            type Safety = crate::Unsafe;
14767        }
14768        #[doc = "`reset()` method sets PWM_FREQ_L7 to value 0"]
14769        impl crate::Resettable for PwmFreqL7Spec {}
14770    }
14771    #[doc = "PWM_FREQ_H7 (rw) register accessor: PWM7 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h7`] module"]
14772    #[doc(alias = "PWM_FREQ_H7")]
14773    pub type PwmFreqH7 = crate::Reg<pwm_freq_h7::PwmFreqH7Spec>;
14774    #[doc = "PWM7 frequency high 16 bits"]
14775    pub mod pwm_freq_h7 {
14776        #[doc = "Register `PWM_FREQ_H7` reader"]
14777        pub type R = crate::R<PwmFreqH7Spec>;
14778        #[doc = "Register `PWM_FREQ_H7` writer"]
14779        pub type W = crate::W<PwmFreqH7Spec>;
14780        #[doc = "Field `pwm_freq_h_7` reader - PWM0 clock divider high 16 bits"]
14781        pub type PwmFreqH7R = crate::FieldReader<u16>;
14782        #[doc = "Field `pwm_freq_h_7` writer - PWM0 clock divider high 16 bits"]
14783        pub type PwmFreqH7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14784        impl R {
14785            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
14786            #[inline(always)]
14787            pub fn pwm_freq_h_7(&self) -> PwmFreqH7R {
14788                PwmFreqH7R::new((self.bits & 0xffff) as u16)
14789            }
14790        }
14791        impl W {
14792            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
14793            #[inline(always)]
14794            pub fn pwm_freq_h_7(&mut self) -> PwmFreqH7W<'_, PwmFreqH7Spec> {
14795                PwmFreqH7W::new(self, 0)
14796            }
14797        }
14798        #[doc = "PWM7 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14799        pub struct PwmFreqH7Spec;
14800        impl crate::RegisterSpec for PwmFreqH7Spec {
14801            type Ux = u32;
14802        }
14803        #[doc = "`read()` method returns [`pwm_freq_h7::R`](R) reader structure"]
14804        impl crate::Readable for PwmFreqH7Spec {}
14805        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h7::W`](W) writer structure"]
14806        impl crate::Writable for PwmFreqH7Spec {
14807            type Safety = crate::Unsafe;
14808        }
14809        #[doc = "`reset()` method sets PWM_FREQ_H7 to value 0"]
14810        impl crate::Resettable for PwmFreqH7Spec {}
14811    }
14812    #[doc = "PWM_DUTY_L7 (rw) register accessor: PWM7 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l7`] module"]
14813    #[doc(alias = "PWM_DUTY_L7")]
14814    pub type PwmDutyL7 = crate::Reg<pwm_duty_l7::PwmDutyL7Spec>;
14815    #[doc = "PWM7 duty cycle low 16 bits"]
14816    pub mod pwm_duty_l7 {
14817        #[doc = "Register `PWM_DUTY_L7` reader"]
14818        pub type R = crate::R<PwmDutyL7Spec>;
14819        #[doc = "Register `PWM_DUTY_L7` writer"]
14820        pub type W = crate::W<PwmDutyL7Spec>;
14821        #[doc = "Field `pwm_duty_l_7` reader - PWM0 duty cycle low 16 bits"]
14822        pub type PwmDutyL7R = crate::FieldReader<u16>;
14823        #[doc = "Field `pwm_duty_l_7` writer - PWM0 duty cycle low 16 bits"]
14824        pub type PwmDutyL7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14825        impl R {
14826            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
14827            #[inline(always)]
14828            pub fn pwm_duty_l_7(&self) -> PwmDutyL7R {
14829                PwmDutyL7R::new((self.bits & 0xffff) as u16)
14830            }
14831        }
14832        impl W {
14833            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
14834            #[inline(always)]
14835            pub fn pwm_duty_l_7(&mut self) -> PwmDutyL7W<'_, PwmDutyL7Spec> {
14836                PwmDutyL7W::new(self, 0)
14837            }
14838        }
14839        #[doc = "PWM7 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14840        pub struct PwmDutyL7Spec;
14841        impl crate::RegisterSpec for PwmDutyL7Spec {
14842            type Ux = u32;
14843        }
14844        #[doc = "`read()` method returns [`pwm_duty_l7::R`](R) reader structure"]
14845        impl crate::Readable for PwmDutyL7Spec {}
14846        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l7::W`](W) writer structure"]
14847        impl crate::Writable for PwmDutyL7Spec {
14848            type Safety = crate::Unsafe;
14849        }
14850        #[doc = "`reset()` method sets PWM_DUTY_L7 to value 0"]
14851        impl crate::Resettable for PwmDutyL7Spec {}
14852    }
14853    #[doc = "PWM_DUTY_H7 (rw) register accessor: PWM7 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h7`] module"]
14854    #[doc(alias = "PWM_DUTY_H7")]
14855    pub type PwmDutyH7 = crate::Reg<pwm_duty_h7::PwmDutyH7Spec>;
14856    #[doc = "PWM7 duty cycle high 16 bits"]
14857    pub mod pwm_duty_h7 {
14858        #[doc = "Register `PWM_DUTY_H7` reader"]
14859        pub type R = crate::R<PwmDutyH7Spec>;
14860        #[doc = "Register `PWM_DUTY_H7` writer"]
14861        pub type W = crate::W<PwmDutyH7Spec>;
14862        #[doc = "Field `pwm_duty_h_7` reader - PWM0 duty cycle high 16 bits"]
14863        pub type PwmDutyH7R = crate::FieldReader<u16>;
14864        #[doc = "Field `pwm_duty_h_7` writer - PWM0 duty cycle high 16 bits"]
14865        pub type PwmDutyH7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14866        impl R {
14867            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
14868            #[inline(always)]
14869            pub fn pwm_duty_h_7(&self) -> PwmDutyH7R {
14870                PwmDutyH7R::new((self.bits & 0xffff) as u16)
14871            }
14872        }
14873        impl W {
14874            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
14875            #[inline(always)]
14876            pub fn pwm_duty_h_7(&mut self) -> PwmDutyH7W<'_, PwmDutyH7Spec> {
14877                PwmDutyH7W::new(self, 0)
14878            }
14879        }
14880        #[doc = "PWM7 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14881        pub struct PwmDutyH7Spec;
14882        impl crate::RegisterSpec for PwmDutyH7Spec {
14883            type Ux = u32;
14884        }
14885        #[doc = "`read()` method returns [`pwm_duty_h7::R`](R) reader structure"]
14886        impl crate::Readable for PwmDutyH7Spec {}
14887        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h7::W`](W) writer structure"]
14888        impl crate::Writable for PwmDutyH7Spec {
14889            type Safety = crate::Unsafe;
14890        }
14891        #[doc = "`reset()` method sets PWM_DUTY_H7 to value 0"]
14892        impl crate::Resettable for PwmDutyH7Spec {}
14893    }
14894    #[doc = "PWM_PERIODLOAD_FLAG7 (rw) register accessor: PWM7 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag7`] module"]
14895    #[doc(alias = "PWM_PERIODLOAD_FLAG7")]
14896    pub type PwmPeriodloadFlag7 = crate::Reg<pwm_periodload_flag7::PwmPeriodloadFlag7Spec>;
14897    #[doc = "PWM7 period load flag"]
14898    pub mod pwm_periodload_flag7 {
14899        #[doc = "Register `PWM_PERIODLOAD_FLAG7` reader"]
14900        pub type R = crate::R<PwmPeriodloadFlag7Spec>;
14901        #[doc = "Register `PWM_PERIODLOAD_FLAG7` writer"]
14902        pub type W = crate::W<PwmPeriodloadFlag7Spec>;
14903        #[doc = "Field `pwm_periodload_flag_7` reader - Period load complete flag"]
14904        pub type PwmPeriodloadFlag7R = crate::BitReader;
14905        impl R {
14906            #[doc = "Bit 0 - Period load complete flag"]
14907            #[inline(always)]
14908            pub fn pwm_periodload_flag_7(&self) -> PwmPeriodloadFlag7R {
14909                PwmPeriodloadFlag7R::new((self.bits & 1) != 0)
14910            }
14911        }
14912        impl W {}
14913        #[doc = "PWM7 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14914        pub struct PwmPeriodloadFlag7Spec;
14915        impl crate::RegisterSpec for PwmPeriodloadFlag7Spec {
14916            type Ux = u32;
14917        }
14918        #[doc = "`read()` method returns [`pwm_periodload_flag7::R`](R) reader structure"]
14919        impl crate::Readable for PwmPeriodloadFlag7Spec {}
14920        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag7::W`](W) writer structure"]
14921        impl crate::Writable for PwmPeriodloadFlag7Spec {
14922            type Safety = crate::Unsafe;
14923        }
14924        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG7 to value 0"]
14925        impl crate::Resettable for PwmPeriodloadFlag7Spec {}
14926    }
14927    #[doc = "PWM_PERIOD_VAL7 (rw) register accessor: PWM7 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val7`] module"]
14928    #[doc(alias = "PWM_PERIOD_VAL7")]
14929    pub type PwmPeriodVal7 = crate::Reg<pwm_period_val7::PwmPeriodVal7Spec>;
14930    #[doc = "PWM7 pulse count value"]
14931    pub mod pwm_period_val7 {
14932        #[doc = "Register `PWM_PERIOD_VAL7` reader"]
14933        pub type R = crate::R<PwmPeriodVal7Spec>;
14934        #[doc = "Register `PWM_PERIOD_VAL7` writer"]
14935        pub type W = crate::W<PwmPeriodVal7Spec>;
14936        #[doc = "Field `pwm_period_val_7` reader - Pulse count for stepping mode"]
14937        pub type PwmPeriodVal7R = crate::FieldReader<u16>;
14938        #[doc = "Field `pwm_period_val_7` writer - Pulse count for stepping mode"]
14939        pub type PwmPeriodVal7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14940        impl R {
14941            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
14942            #[inline(always)]
14943            pub fn pwm_period_val_7(&self) -> PwmPeriodVal7R {
14944                PwmPeriodVal7R::new((self.bits & 0xffff) as u16)
14945            }
14946        }
14947        impl W {
14948            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
14949            #[inline(always)]
14950            pub fn pwm_period_val_7(&mut self) -> PwmPeriodVal7W<'_, PwmPeriodVal7Spec> {
14951                PwmPeriodVal7W::new(self, 0)
14952            }
14953        }
14954        #[doc = "PWM7 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14955        pub struct PwmPeriodVal7Spec;
14956        impl crate::RegisterSpec for PwmPeriodVal7Spec {
14957            type Ux = u32;
14958        }
14959        #[doc = "`read()` method returns [`pwm_period_val7::R`](R) reader structure"]
14960        impl crate::Readable for PwmPeriodVal7Spec {}
14961        #[doc = "`write(|w| ..)` method takes [`pwm_period_val7::W`](W) writer structure"]
14962        impl crate::Writable for PwmPeriodVal7Spec {
14963            type Safety = crate::Unsafe;
14964        }
14965        #[doc = "`reset()` method sets PWM_PERIOD_VAL7 to value 0"]
14966        impl crate::Resettable for PwmPeriodVal7Spec {}
14967    }
14968    #[doc = "PWM_PERIODCNT7 (rw) register accessor: PWM7 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt7`] module"]
14969    #[doc(alias = "PWM_PERIODCNT7")]
14970    pub type PwmPeriodcnt7 = crate::Reg<pwm_periodcnt7::PwmPeriodcnt7Spec>;
14971    #[doc = "PWM7 pulse count current value"]
14972    pub mod pwm_periodcnt7 {
14973        #[doc = "Register `PWM_PERIODCNT7` reader"]
14974        pub type R = crate::R<PwmPeriodcnt7Spec>;
14975        #[doc = "Register `PWM_PERIODCNT7` writer"]
14976        pub type W = crate::W<PwmPeriodcnt7Spec>;
14977        #[doc = "Field `pwm_periodcnt_7` reader - Current pulse count"]
14978        pub type PwmPeriodcnt7R = crate::FieldReader<u16>;
14979        impl R {
14980            #[doc = "Bits 0:15 - Current pulse count"]
14981            #[inline(always)]
14982            pub fn pwm_periodcnt_7(&self) -> PwmPeriodcnt7R {
14983                PwmPeriodcnt7R::new((self.bits & 0xffff) as u16)
14984            }
14985        }
14986        impl W {}
14987        #[doc = "PWM7 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14988        pub struct PwmPeriodcnt7Spec;
14989        impl crate::RegisterSpec for PwmPeriodcnt7Spec {
14990            type Ux = u32;
14991        }
14992        #[doc = "`read()` method returns [`pwm_periodcnt7::R`](R) reader structure"]
14993        impl crate::Readable for PwmPeriodcnt7Spec {}
14994        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt7::W`](W) writer structure"]
14995        impl crate::Writable for PwmPeriodcnt7Spec {
14996            type Safety = crate::Unsafe;
14997        }
14998        #[doc = "`reset()` method sets PWM_PERIODCNT7 to value 0"]
14999        impl crate::Resettable for PwmPeriodcnt7Spec {}
15000    }
15001}
15002#[doc = "DMA controller with 4 channels"]
15003pub type Dma = crate::Periph<dma::RegisterBlock, 0x4a00_0000>;
15004impl core::fmt::Debug for Dma {
15005    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15006        f.debug_struct("Dma").finish()
15007    }
15008}
15009#[doc = "DMA controller with 4 channels"]
15010pub mod dma {
15011    #[repr(C)]
15012    #[doc = "Register block"]
15013    pub struct RegisterBlock {
15014        _reserved0: [u8; 0x04],
15015        dmac_int_st: DmacIntSt,
15016        dmac_int_clr: DmacIntClr,
15017        dmac_ori_int_st: DmacOriIntSt,
15018        dmac_en_chns: DmacEnChns,
15019        dmac_burst_req: DmacBurstReq,
15020        dmac_single_req: DmacSingleReq,
15021        dmac_config: DmacConfig,
15022        dmac_sync: DmacSync,
15023        _reserved8: [u8; 0xdc],
15024        dmac_lli_0: (),
15025        _reserved9: [u8; 0x04],
15026        dmac_d_addr_0: (),
15027        _reserved10: [u8; 0x04],
15028        dmac_chn_config_0: (),
15029        _reserved11: [u8; 0x08],
15030        dmac_s_addr_0: (),
15031        _reserved12: [u8; 0x04],
15032        dmac_chn_control_0: (),
15033    }
15034    impl RegisterBlock {
15035        #[doc = "0x04 - Interrupt status register"]
15036        #[inline(always)]
15037        pub const fn dmac_int_st(&self) -> &DmacIntSt {
15038            &self.dmac_int_st
15039        }
15040        #[doc = "0x08 - Interrupt clear register"]
15041        #[inline(always)]
15042        pub const fn dmac_int_clr(&self) -> &DmacIntClr {
15043            &self.dmac_int_clr
15044        }
15045        #[doc = "0x0c - Raw interrupt status register"]
15046        #[inline(always)]
15047        pub const fn dmac_ori_int_st(&self) -> &DmacOriIntSt {
15048            &self.dmac_ori_int_st
15049        }
15050        #[doc = "0x10 - Channel enable query register"]
15051        #[inline(always)]
15052        pub const fn dmac_en_chns(&self) -> &DmacEnChns {
15053            &self.dmac_en_chns
15054        }
15055        #[doc = "0x14 - Burst software request register"]
15056        #[inline(always)]
15057        pub const fn dmac_burst_req(&self) -> &DmacBurstReq {
15058            &self.dmac_burst_req
15059        }
15060        #[doc = "0x18 - Single software request register"]
15061        #[inline(always)]
15062        pub const fn dmac_single_req(&self) -> &DmacSingleReq {
15063            &self.dmac_single_req
15064        }
15065        #[doc = "0x1c - DMA configuration register"]
15066        #[inline(always)]
15067        pub const fn dmac_config(&self) -> &DmacConfig {
15068            &self.dmac_config
15069        }
15070        #[doc = "0x20 - DMA sync register"]
15071        #[inline(always)]
15072        pub const fn dmac_sync(&self) -> &DmacSync {
15073            &self.dmac_sync
15074        }
15075        #[doc = "0x100..0x110 - Channel %s \\[dim=4\\] linked list register"]
15076        #[inline(always)]
15077        pub const fn dmac_lli_0(&self, n: usize) -> &DmacLli_ {
15078            #[allow(clippy::no_effect)]
15079            [(); 4][n];
15080            unsafe {
15081                &*core::ptr::from_ref(self)
15082                    .cast::<u8>()
15083                    .add(256)
15084                    .add(32 * n)
15085                    .cast()
15086            }
15087        }
15088        #[doc = "Iterator for array of:"]
15089        #[doc = "0x100..0x110 - Channel %s \\[dim=4\\] linked list register"]
15090        #[inline(always)]
15091        pub fn dmac_lli_0_iter(&self) -> impl Iterator<Item = &DmacLli_> {
15092            (0..4).map(move |n| unsafe {
15093                &*core::ptr::from_ref(self)
15094                    .cast::<u8>()
15095                    .add(256)
15096                    .add(32 * n)
15097                    .cast()
15098            })
15099        }
15100        #[doc = "0x104..0x114 - Channel %s \\[dim=4\\] destination address"]
15101        #[inline(always)]
15102        pub const fn dmac_d_addr_0(&self, n: usize) -> &DmacDAddr_ {
15103            #[allow(clippy::no_effect)]
15104            [(); 4][n];
15105            unsafe {
15106                &*core::ptr::from_ref(self)
15107                    .cast::<u8>()
15108                    .add(260)
15109                    .add(32 * n)
15110                    .cast()
15111            }
15112        }
15113        #[doc = "Iterator for array of:"]
15114        #[doc = "0x104..0x114 - Channel %s \\[dim=4\\] destination address"]
15115        #[inline(always)]
15116        pub fn dmac_d_addr_0_iter(&self) -> impl Iterator<Item = &DmacDAddr_> {
15117            (0..4).map(move |n| unsafe {
15118                &*core::ptr::from_ref(self)
15119                    .cast::<u8>()
15120                    .add(260)
15121                    .add(32 * n)
15122                    .cast()
15123            })
15124        }
15125        #[doc = "0x108..0x118 - Channel %s \\[dim=4\\] configuration register"]
15126        #[inline(always)]
15127        pub const fn dmac_chn_config_0(&self, n: usize) -> &DmacChnConfig_ {
15128            #[allow(clippy::no_effect)]
15129            [(); 4][n];
15130            unsafe {
15131                &*core::ptr::from_ref(self)
15132                    .cast::<u8>()
15133                    .add(264)
15134                    .add(32 * n)
15135                    .cast()
15136            }
15137        }
15138        #[doc = "Iterator for array of:"]
15139        #[doc = "0x108..0x118 - Channel %s \\[dim=4\\] configuration register"]
15140        #[inline(always)]
15141        pub fn dmac_chn_config_0_iter(&self) -> impl Iterator<Item = &DmacChnConfig_> {
15142            (0..4).map(move |n| unsafe {
15143                &*core::ptr::from_ref(self)
15144                    .cast::<u8>()
15145                    .add(264)
15146                    .add(32 * n)
15147                    .cast()
15148            })
15149        }
15150        #[doc = "0x110..0x120 - Channel %s \\[dim=4\\] source address"]
15151        #[inline(always)]
15152        pub const fn dmac_s_addr_0(&self, n: usize) -> &DmacSAddr_ {
15153            #[allow(clippy::no_effect)]
15154            [(); 4][n];
15155            unsafe {
15156                &*core::ptr::from_ref(self)
15157                    .cast::<u8>()
15158                    .add(272)
15159                    .add(32 * n)
15160                    .cast()
15161            }
15162        }
15163        #[doc = "Iterator for array of:"]
15164        #[doc = "0x110..0x120 - Channel %s \\[dim=4\\] source address"]
15165        #[inline(always)]
15166        pub fn dmac_s_addr_0_iter(&self) -> impl Iterator<Item = &DmacSAddr_> {
15167            (0..4).map(move |n| unsafe {
15168                &*core::ptr::from_ref(self)
15169                    .cast::<u8>()
15170                    .add(272)
15171                    .add(32 * n)
15172                    .cast()
15173            })
15174        }
15175        #[doc = "0x114..0x124 - Channel %s \\[dim=4\\] control register"]
15176        #[inline(always)]
15177        pub const fn dmac_chn_control_0(&self, n: usize) -> &DmacChnControl_ {
15178            #[allow(clippy::no_effect)]
15179            [(); 4][n];
15180            unsafe {
15181                &*core::ptr::from_ref(self)
15182                    .cast::<u8>()
15183                    .add(276)
15184                    .add(32 * n)
15185                    .cast()
15186            }
15187        }
15188        #[doc = "Iterator for array of:"]
15189        #[doc = "0x114..0x124 - Channel %s \\[dim=4\\] control register"]
15190        #[inline(always)]
15191        pub fn dmac_chn_control_0_iter(&self) -> impl Iterator<Item = &DmacChnControl_> {
15192            (0..4).map(move |n| unsafe {
15193                &*core::ptr::from_ref(self)
15194                    .cast::<u8>()
15195                    .add(276)
15196                    .add(32 * n)
15197                    .cast()
15198            })
15199        }
15200    }
15201    #[doc = "DMAC_INT_ST (rw) register accessor: Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_int_st`] module"]
15202    #[doc(alias = "DMAC_INT_ST")]
15203    pub type DmacIntSt = crate::Reg<dmac_int_st::DmacIntStSpec>;
15204    #[doc = "Interrupt status register"]
15205    pub mod dmac_int_st {
15206        #[doc = "Register `DMAC_INT_ST` reader"]
15207        pub type R = crate::R<DmacIntStSpec>;
15208        #[doc = "Register `DMAC_INT_ST` writer"]
15209        pub type W = crate::W<DmacIntStSpec>;
15210        #[doc = "Field `int_st` reader - Channel interrupt status (after mask)"]
15211        pub type IntStR = crate::FieldReader;
15212        #[doc = "Field `int_trans_st` reader - Channel transfer interrupt status (after mask)"]
15213        pub type IntTransStR = crate::FieldReader;
15214        #[doc = "Field `int_err_st` reader - Channel error interrupt status (after mask)"]
15215        pub type IntErrStR = crate::FieldReader;
15216        impl R {
15217            #[doc = "Bits 0:7 - Channel interrupt status (after mask)"]
15218            #[inline(always)]
15219            pub fn int_st(&self) -> IntStR {
15220                IntStR::new((self.bits & 0xff) as u8)
15221            }
15222            #[doc = "Bits 8:15 - Channel transfer interrupt status (after mask)"]
15223            #[inline(always)]
15224            pub fn int_trans_st(&self) -> IntTransStR {
15225                IntTransStR::new(((self.bits >> 8) & 0xff) as u8)
15226            }
15227            #[doc = "Bits 16:23 - Channel error interrupt status (after mask)"]
15228            #[inline(always)]
15229            pub fn int_err_st(&self) -> IntErrStR {
15230                IntErrStR::new(((self.bits >> 16) & 0xff) as u8)
15231            }
15232        }
15233        impl W {}
15234        #[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15235        pub struct DmacIntStSpec;
15236        impl crate::RegisterSpec for DmacIntStSpec {
15237            type Ux = u32;
15238        }
15239        #[doc = "`read()` method returns [`dmac_int_st::R`](R) reader structure"]
15240        impl crate::Readable for DmacIntStSpec {}
15241        #[doc = "`write(|w| ..)` method takes [`dmac_int_st::W`](W) writer structure"]
15242        impl crate::Writable for DmacIntStSpec {
15243            type Safety = crate::Unsafe;
15244        }
15245        #[doc = "`reset()` method sets DMAC_INT_ST to value 0"]
15246        impl crate::Resettable for DmacIntStSpec {}
15247    }
15248    #[doc = "DMAC_INT_CLR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_int_clr`] module"]
15249    #[doc(alias = "DMAC_INT_CLR")]
15250    pub type DmacIntClr = crate::Reg<dmac_int_clr::DmacIntClrSpec>;
15251    #[doc = "Interrupt clear register"]
15252    pub mod dmac_int_clr {
15253        #[doc = "Register `DMAC_INT_CLR` reader"]
15254        pub type R = crate::R<DmacIntClrSpec>;
15255        #[doc = "Register `DMAC_INT_CLR` writer"]
15256        pub type W = crate::W<DmacIntClrSpec>;
15257        #[doc = "Field `int_trans_clr` reader - Clear channel transfer interrupt"]
15258        pub type IntTransClrR = crate::FieldReader;
15259        #[doc = "Field `int_trans_clr` writer - Clear channel transfer interrupt"]
15260        pub type IntTransClrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
15261        #[doc = "Field `int_err_clr` reader - Clear channel error interrupt"]
15262        pub type IntErrClrR = crate::FieldReader;
15263        #[doc = "Field `int_err_clr` writer - Clear channel error interrupt"]
15264        pub type IntErrClrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
15265        impl R {
15266            #[doc = "Bits 0:7 - Clear channel transfer interrupt"]
15267            #[inline(always)]
15268            pub fn int_trans_clr(&self) -> IntTransClrR {
15269                IntTransClrR::new((self.bits & 0xff) as u8)
15270            }
15271            #[doc = "Bits 8:15 - Clear channel error interrupt"]
15272            #[inline(always)]
15273            pub fn int_err_clr(&self) -> IntErrClrR {
15274                IntErrClrR::new(((self.bits >> 8) & 0xff) as u8)
15275            }
15276        }
15277        impl W {
15278            #[doc = "Bits 0:7 - Clear channel transfer interrupt"]
15279            #[inline(always)]
15280            pub fn int_trans_clr(&mut self) -> IntTransClrW<'_, DmacIntClrSpec> {
15281                IntTransClrW::new(self, 0)
15282            }
15283            #[doc = "Bits 8:15 - Clear channel error interrupt"]
15284            #[inline(always)]
15285            pub fn int_err_clr(&mut self) -> IntErrClrW<'_, DmacIntClrSpec> {
15286                IntErrClrW::new(self, 8)
15287            }
15288        }
15289        #[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15290        pub struct DmacIntClrSpec;
15291        impl crate::RegisterSpec for DmacIntClrSpec {
15292            type Ux = u32;
15293        }
15294        #[doc = "`read()` method returns [`dmac_int_clr::R`](R) reader structure"]
15295        impl crate::Readable for DmacIntClrSpec {}
15296        #[doc = "`write(|w| ..)` method takes [`dmac_int_clr::W`](W) writer structure"]
15297        impl crate::Writable for DmacIntClrSpec {
15298            type Safety = crate::Unsafe;
15299        }
15300        #[doc = "`reset()` method sets DMAC_INT_CLR to value 0"]
15301        impl crate::Resettable for DmacIntClrSpec {}
15302    }
15303    #[doc = "DMAC_ORI_INT_ST (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_ori_int_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_ori_int_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_ori_int_st`] module"]
15304    #[doc(alias = "DMAC_ORI_INT_ST")]
15305    pub type DmacOriIntSt = crate::Reg<dmac_ori_int_st::DmacOriIntStSpec>;
15306    #[doc = "Raw interrupt status register"]
15307    pub mod dmac_ori_int_st {
15308        #[doc = "Register `DMAC_ORI_INT_ST` reader"]
15309        pub type R = crate::R<DmacOriIntStSpec>;
15310        #[doc = "Register `DMAC_ORI_INT_ST` writer"]
15311        pub type W = crate::W<DmacOriIntStSpec>;
15312        #[doc = "Field `ori_int_trans_st` reader - Raw transfer interrupt status (before mask)"]
15313        pub type OriIntTransStR = crate::FieldReader;
15314        #[doc = "Field `ori_int_err_st` reader - Raw error interrupt status (before mask)"]
15315        pub type OriIntErrStR = crate::FieldReader;
15316        impl R {
15317            #[doc = "Bits 0:7 - Raw transfer interrupt status (before mask)"]
15318            #[inline(always)]
15319            pub fn ori_int_trans_st(&self) -> OriIntTransStR {
15320                OriIntTransStR::new((self.bits & 0xff) as u8)
15321            }
15322            #[doc = "Bits 8:15 - Raw error interrupt status (before mask)"]
15323            #[inline(always)]
15324            pub fn ori_int_err_st(&self) -> OriIntErrStR {
15325                OriIntErrStR::new(((self.bits >> 8) & 0xff) as u8)
15326            }
15327        }
15328        impl W {}
15329        #[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_ori_int_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_ori_int_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15330        pub struct DmacOriIntStSpec;
15331        impl crate::RegisterSpec for DmacOriIntStSpec {
15332            type Ux = u32;
15333        }
15334        #[doc = "`read()` method returns [`dmac_ori_int_st::R`](R) reader structure"]
15335        impl crate::Readable for DmacOriIntStSpec {}
15336        #[doc = "`write(|w| ..)` method takes [`dmac_ori_int_st::W`](W) writer structure"]
15337        impl crate::Writable for DmacOriIntStSpec {
15338            type Safety = crate::Unsafe;
15339        }
15340        #[doc = "`reset()` method sets DMAC_ORI_INT_ST to value 0"]
15341        impl crate::Resettable for DmacOriIntStSpec {}
15342    }
15343    #[doc = "DMAC_EN_CHNS (rw) register accessor: Channel enable query register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_en_chns::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_en_chns::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_en_chns`] module"]
15344    #[doc(alias = "DMAC_EN_CHNS")]
15345    pub type DmacEnChns = crate::Reg<dmac_en_chns::DmacEnChnsSpec>;
15346    #[doc = "Channel enable query register"]
15347    pub mod dmac_en_chns {
15348        #[doc = "Register `DMAC_EN_CHNS` reader"]
15349        pub type R = crate::R<DmacEnChnsSpec>;
15350        #[doc = "Register `DMAC_EN_CHNS` writer"]
15351        pub type W = crate::W<DmacEnChnsSpec>;
15352        #[doc = "Field `en_chns` reader - Channel enable status: 0=disabled; 1=enabled"]
15353        pub type EnChnsR = crate::FieldReader;
15354        impl R {
15355            #[doc = "Bits 0:7 - Channel enable status: 0=disabled; 1=enabled"]
15356            #[inline(always)]
15357            pub fn en_chns(&self) -> EnChnsR {
15358                EnChnsR::new((self.bits & 0xff) as u8)
15359            }
15360        }
15361        impl W {}
15362        #[doc = "Channel enable query register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_en_chns::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_en_chns::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15363        pub struct DmacEnChnsSpec;
15364        impl crate::RegisterSpec for DmacEnChnsSpec {
15365            type Ux = u32;
15366        }
15367        #[doc = "`read()` method returns [`dmac_en_chns::R`](R) reader structure"]
15368        impl crate::Readable for DmacEnChnsSpec {}
15369        #[doc = "`write(|w| ..)` method takes [`dmac_en_chns::W`](W) writer structure"]
15370        impl crate::Writable for DmacEnChnsSpec {
15371            type Safety = crate::Unsafe;
15372        }
15373        #[doc = "`reset()` method sets DMAC_EN_CHNS to value 0"]
15374        impl crate::Resettable for DmacEnChnsSpec {}
15375    }
15376    #[doc = "DMAC_BURST_REQ (rw) register accessor: Burst software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_burst_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_burst_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_burst_req`] module"]
15377    #[doc(alias = "DMAC_BURST_REQ")]
15378    pub type DmacBurstReq = crate::Reg<dmac_burst_req::DmacBurstReqSpec>;
15379    #[doc = "Burst software request register"]
15380    pub mod dmac_burst_req {
15381        #[doc = "Register `DMAC_BURST_REQ` reader"]
15382        pub type R = crate::R<DmacBurstReqSpec>;
15383        #[doc = "Register `DMAC_BURST_REQ` writer"]
15384        pub type W = crate::W<DmacBurstReqSpec>;
15385        #[doc = "Field `last_burst_req` reader - Last burst request per peripheral"]
15386        pub type LastBurstReqR = crate::FieldReader<u16>;
15387        #[doc = "Field `last_burst_req` writer - Last burst request per peripheral"]
15388        pub type LastBurstReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15389        #[doc = "Field `burst_req` reader - Burst request per peripheral"]
15390        pub type BurstReqR = crate::FieldReader<u16>;
15391        #[doc = "Field `burst_req` writer - Burst request per peripheral"]
15392        pub type BurstReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15393        impl R {
15394            #[doc = "Bits 0:15 - Last burst request per peripheral"]
15395            #[inline(always)]
15396            pub fn last_burst_req(&self) -> LastBurstReqR {
15397                LastBurstReqR::new((self.bits & 0xffff) as u16)
15398            }
15399            #[doc = "Bits 16:31 - Burst request per peripheral"]
15400            #[inline(always)]
15401            pub fn burst_req(&self) -> BurstReqR {
15402                BurstReqR::new(((self.bits >> 16) & 0xffff) as u16)
15403            }
15404        }
15405        impl W {
15406            #[doc = "Bits 0:15 - Last burst request per peripheral"]
15407            #[inline(always)]
15408            pub fn last_burst_req(&mut self) -> LastBurstReqW<'_, DmacBurstReqSpec> {
15409                LastBurstReqW::new(self, 0)
15410            }
15411            #[doc = "Bits 16:31 - Burst request per peripheral"]
15412            #[inline(always)]
15413            pub fn burst_req(&mut self) -> BurstReqW<'_, DmacBurstReqSpec> {
15414                BurstReqW::new(self, 16)
15415            }
15416        }
15417        #[doc = "Burst software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_burst_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_burst_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15418        pub struct DmacBurstReqSpec;
15419        impl crate::RegisterSpec for DmacBurstReqSpec {
15420            type Ux = u32;
15421        }
15422        #[doc = "`read()` method returns [`dmac_burst_req::R`](R) reader structure"]
15423        impl crate::Readable for DmacBurstReqSpec {}
15424        #[doc = "`write(|w| ..)` method takes [`dmac_burst_req::W`](W) writer structure"]
15425        impl crate::Writable for DmacBurstReqSpec {
15426            type Safety = crate::Unsafe;
15427        }
15428        #[doc = "`reset()` method sets DMAC_BURST_REQ to value 0"]
15429        impl crate::Resettable for DmacBurstReqSpec {}
15430    }
15431    #[doc = "DMAC_SINGLE_REQ (rw) register accessor: Single software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_single_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_single_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_single_req`] module"]
15432    #[doc(alias = "DMAC_SINGLE_REQ")]
15433    pub type DmacSingleReq = crate::Reg<dmac_single_req::DmacSingleReqSpec>;
15434    #[doc = "Single software request register"]
15435    pub mod dmac_single_req {
15436        #[doc = "Register `DMAC_SINGLE_REQ` reader"]
15437        pub type R = crate::R<DmacSingleReqSpec>;
15438        #[doc = "Register `DMAC_SINGLE_REQ` writer"]
15439        pub type W = crate::W<DmacSingleReqSpec>;
15440        #[doc = "Field `last_single_req` reader - Last single request per peripheral"]
15441        pub type LastSingleReqR = crate::FieldReader<u16>;
15442        #[doc = "Field `last_single_req` writer - Last single request per peripheral"]
15443        pub type LastSingleReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15444        #[doc = "Field `single_req` reader - Single request per peripheral"]
15445        pub type SingleReqR = crate::FieldReader<u16>;
15446        #[doc = "Field `single_req` writer - Single request per peripheral"]
15447        pub type SingleReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15448        impl R {
15449            #[doc = "Bits 0:15 - Last single request per peripheral"]
15450            #[inline(always)]
15451            pub fn last_single_req(&self) -> LastSingleReqR {
15452                LastSingleReqR::new((self.bits & 0xffff) as u16)
15453            }
15454            #[doc = "Bits 16:31 - Single request per peripheral"]
15455            #[inline(always)]
15456            pub fn single_req(&self) -> SingleReqR {
15457                SingleReqR::new(((self.bits >> 16) & 0xffff) as u16)
15458            }
15459        }
15460        impl W {
15461            #[doc = "Bits 0:15 - Last single request per peripheral"]
15462            #[inline(always)]
15463            pub fn last_single_req(&mut self) -> LastSingleReqW<'_, DmacSingleReqSpec> {
15464                LastSingleReqW::new(self, 0)
15465            }
15466            #[doc = "Bits 16:31 - Single request per peripheral"]
15467            #[inline(always)]
15468            pub fn single_req(&mut self) -> SingleReqW<'_, DmacSingleReqSpec> {
15469                SingleReqW::new(self, 16)
15470            }
15471        }
15472        #[doc = "Single software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_single_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_single_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15473        pub struct DmacSingleReqSpec;
15474        impl crate::RegisterSpec for DmacSingleReqSpec {
15475            type Ux = u32;
15476        }
15477        #[doc = "`read()` method returns [`dmac_single_req::R`](R) reader structure"]
15478        impl crate::Readable for DmacSingleReqSpec {}
15479        #[doc = "`write(|w| ..)` method takes [`dmac_single_req::W`](W) writer structure"]
15480        impl crate::Writable for DmacSingleReqSpec {
15481            type Safety = crate::Unsafe;
15482        }
15483        #[doc = "`reset()` method sets DMAC_SINGLE_REQ to value 0"]
15484        impl crate::Resettable for DmacSingleReqSpec {}
15485    }
15486    #[doc = "DMAC_CONFIG (rw) register accessor: DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_config`] module"]
15487    #[doc(alias = "DMAC_CONFIG")]
15488    pub type DmacConfig = crate::Reg<dmac_config::DmacConfigSpec>;
15489    #[doc = "DMA configuration register"]
15490    pub mod dmac_config {
15491        #[doc = "Register `DMAC_CONFIG` reader"]
15492        pub type R = crate::R<DmacConfigSpec>;
15493        #[doc = "Register `DMAC_CONFIG` writer"]
15494        pub type W = crate::W<DmacConfigSpec>;
15495        #[doc = "Field `dmac_en` reader - DMAC enable: 0=disabled; 1=enabled"]
15496        pub type DmacEnR = crate::BitReader;
15497        #[doc = "Field `dmac_en` writer - DMAC enable: 0=disabled; 1=enabled"]
15498        pub type DmacEnW<'a, REG> = crate::BitWriter<'a, REG>;
15499        #[doc = "Field `dmac_m1` reader - Master 1 endianness: 0=little; 1=big"]
15500        pub type DmacM1R = crate::BitReader;
15501        #[doc = "Field `dmac_m1` writer - Master 1 endianness: 0=little; 1=big"]
15502        pub type DmacM1W<'a, REG> = crate::BitWriter<'a, REG>;
15503        #[doc = "Field `dmac_m2` reader - Master 2 endianness: 0=little; 1=big"]
15504        pub type DmacM2R = crate::BitReader;
15505        #[doc = "Field `dmac_m2` writer - Master 2 endianness: 0=little; 1=big"]
15506        pub type DmacM2W<'a, REG> = crate::BitWriter<'a, REG>;
15507        impl R {
15508            #[doc = "Bit 0 - DMAC enable: 0=disabled; 1=enabled"]
15509            #[inline(always)]
15510            pub fn dmac_en(&self) -> DmacEnR {
15511                DmacEnR::new((self.bits & 1) != 0)
15512            }
15513            #[doc = "Bit 1 - Master 1 endianness: 0=little; 1=big"]
15514            #[inline(always)]
15515            pub fn dmac_m1(&self) -> DmacM1R {
15516                DmacM1R::new(((self.bits >> 1) & 1) != 0)
15517            }
15518            #[doc = "Bit 2 - Master 2 endianness: 0=little; 1=big"]
15519            #[inline(always)]
15520            pub fn dmac_m2(&self) -> DmacM2R {
15521                DmacM2R::new(((self.bits >> 2) & 1) != 0)
15522            }
15523        }
15524        impl W {
15525            #[doc = "Bit 0 - DMAC enable: 0=disabled; 1=enabled"]
15526            #[inline(always)]
15527            pub fn dmac_en(&mut self) -> DmacEnW<'_, DmacConfigSpec> {
15528                DmacEnW::new(self, 0)
15529            }
15530            #[doc = "Bit 1 - Master 1 endianness: 0=little; 1=big"]
15531            #[inline(always)]
15532            pub fn dmac_m1(&mut self) -> DmacM1W<'_, DmacConfigSpec> {
15533                DmacM1W::new(self, 1)
15534            }
15535            #[doc = "Bit 2 - Master 2 endianness: 0=little; 1=big"]
15536            #[inline(always)]
15537            pub fn dmac_m2(&mut self) -> DmacM2W<'_, DmacConfigSpec> {
15538                DmacM2W::new(self, 2)
15539            }
15540        }
15541        #[doc = "DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15542        pub struct DmacConfigSpec;
15543        impl crate::RegisterSpec for DmacConfigSpec {
15544            type Ux = u32;
15545        }
15546        #[doc = "`read()` method returns [`dmac_config::R`](R) reader structure"]
15547        impl crate::Readable for DmacConfigSpec {}
15548        #[doc = "`write(|w| ..)` method takes [`dmac_config::W`](W) writer structure"]
15549        impl crate::Writable for DmacConfigSpec {
15550            type Safety = crate::Unsafe;
15551        }
15552        #[doc = "`reset()` method sets DMAC_CONFIG to value 0"]
15553        impl crate::Resettable for DmacConfigSpec {}
15554    }
15555    #[doc = "DMAC_SYNC (rw) register accessor: DMA sync register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_sync`] module"]
15556    #[doc(alias = "DMAC_SYNC")]
15557    pub type DmacSync = crate::Reg<dmac_sync::DmacSyncSpec>;
15558    #[doc = "DMA sync register"]
15559    pub mod dmac_sync {
15560        #[doc = "Register `DMAC_SYNC` reader"]
15561        pub type R = crate::R<DmacSyncSpec>;
15562        #[doc = "Register `DMAC_SYNC` writer"]
15563        pub type W = crate::W<DmacSyncSpec>;
15564        #[doc = "Field `damc_sync` reader - DMA request sync: 0=enable sync; 1=disable sync"]
15565        pub type DamcSyncR = crate::FieldReader<u16>;
15566        #[doc = "Field `damc_sync` writer - DMA request sync: 0=enable sync; 1=disable sync"]
15567        pub type DamcSyncW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15568        impl R {
15569            #[doc = "Bits 0:15 - DMA request sync: 0=enable sync; 1=disable sync"]
15570            #[inline(always)]
15571            pub fn damc_sync(&self) -> DamcSyncR {
15572                DamcSyncR::new((self.bits & 0xffff) as u16)
15573            }
15574        }
15575        impl W {
15576            #[doc = "Bits 0:15 - DMA request sync: 0=enable sync; 1=disable sync"]
15577            #[inline(always)]
15578            pub fn damc_sync(&mut self) -> DamcSyncW<'_, DmacSyncSpec> {
15579                DamcSyncW::new(self, 0)
15580            }
15581        }
15582        #[doc = "DMA sync register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_sync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_sync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15583        pub struct DmacSyncSpec;
15584        impl crate::RegisterSpec for DmacSyncSpec {
15585            type Ux = u32;
15586        }
15587        #[doc = "`read()` method returns [`dmac_sync::R`](R) reader structure"]
15588        impl crate::Readable for DmacSyncSpec {}
15589        #[doc = "`write(|w| ..)` method takes [`dmac_sync::W`](W) writer structure"]
15590        impl crate::Writable for DmacSyncSpec {
15591            type Safety = crate::Unsafe;
15592        }
15593        #[doc = "`reset()` method sets DMAC_SYNC to value 0"]
15594        impl crate::Resettable for DmacSyncSpec {}
15595    }
15596    #[doc = "DMAC_D_ADDR_ (rw) register accessor: Channel %s \\[dim=4\\] destination address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_d_addr_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_d_addr_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_d_addr_`] module"]
15597    #[doc(alias = "DMAC_D_ADDR_")]
15598    pub type DmacDAddr_ = crate::Reg<dmac_d_addr_::DmacDAddr_Spec>;
15599    #[doc = "Channel %s \\[dim=4\\] destination address"]
15600    pub mod dmac_d_addr_ {
15601        #[doc = "Register `DMAC_D_ADDR_%s` reader"]
15602        pub type R = crate::R<DmacDAddr_Spec>;
15603        #[doc = "Register `DMAC_D_ADDR_%s` writer"]
15604        pub type W = crate::W<DmacDAddr_Spec>;
15605        #[doc = "Field `dmac_d_addr_0` reader - Channel 0 destination address"]
15606        pub type DmacDAddr0R = crate::FieldReader<u32>;
15607        #[doc = "Field `dmac_d_addr_0` writer - Channel 0 destination address"]
15608        pub type DmacDAddr0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
15609        impl R {
15610            #[doc = "Bits 0:31 - Channel 0 destination address"]
15611            #[inline(always)]
15612            pub fn dmac_d_addr_0(&self) -> DmacDAddr0R {
15613                DmacDAddr0R::new(self.bits)
15614            }
15615        }
15616        impl W {
15617            #[doc = "Bits 0:31 - Channel 0 destination address"]
15618            #[inline(always)]
15619            pub fn dmac_d_addr_0(&mut self) -> DmacDAddr0W<'_, DmacDAddr_Spec> {
15620                DmacDAddr0W::new(self, 0)
15621            }
15622        }
15623        #[doc = "Channel %s \\[dim=4\\] destination address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_d_addr_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_d_addr_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15624        pub struct DmacDAddr_Spec;
15625        impl crate::RegisterSpec for DmacDAddr_Spec {
15626            type Ux = u32;
15627        }
15628        #[doc = "`read()` method returns [`dmac_d_addr_::R`](R) reader structure"]
15629        impl crate::Readable for DmacDAddr_Spec {}
15630        #[doc = "`write(|w| ..)` method takes [`dmac_d_addr_::W`](W) writer structure"]
15631        impl crate::Writable for DmacDAddr_Spec {
15632            type Safety = crate::Unsafe;
15633        }
15634        #[doc = "`reset()` method sets DMAC_D_ADDR_%s to value 0"]
15635        impl crate::Resettable for DmacDAddr_Spec {}
15636    }
15637    #[doc = "DMAC_LLI_ (rw) register accessor: Channel %s \\[dim=4\\] linked list register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_lli_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_lli_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_lli_`] module"]
15638    #[doc(alias = "DMAC_LLI_")]
15639    pub type DmacLli_ = crate::Reg<dmac_lli_::DmacLli_Spec>;
15640    #[doc = "Channel %s \\[dim=4\\] linked list register"]
15641    pub mod dmac_lli_ {
15642        #[doc = "Register `DMAC_LLI_%s` reader"]
15643        pub type R = crate::R<DmacLli_Spec>;
15644        #[doc = "Register `DMAC_LLI_%s` writer"]
15645        pub type W = crate::W<DmacLli_Spec>;
15646        #[doc = "Field `dmac_lm_0` reader - Master for next LLI node: 0=Master1; 1=Master2"]
15647        pub type DmacLm0R = crate::BitReader;
15648        #[doc = "Field `dmac_lm_0` writer - Master for next LLI node: 0=Master1; 1=Master2"]
15649        pub type DmacLm0W<'a, REG> = crate::BitWriter<'a, REG>;
15650        #[doc = "Field `dmac_lli_0` reader - Linked list address \\[31:2\\]"]
15651        pub type DmacLli0R = crate::FieldReader<u32>;
15652        #[doc = "Field `dmac_lli_0` writer - Linked list address \\[31:2\\]"]
15653        pub type DmacLli0W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
15654        impl R {
15655            #[doc = "Bit 0 - Master for next LLI node: 0=Master1; 1=Master2"]
15656            #[inline(always)]
15657            pub fn dmac_lm_0(&self) -> DmacLm0R {
15658                DmacLm0R::new((self.bits & 1) != 0)
15659            }
15660            #[doc = "Bits 2:31 - Linked list address \\[31:2\\]"]
15661            #[inline(always)]
15662            pub fn dmac_lli_0(&self) -> DmacLli0R {
15663                DmacLli0R::new((self.bits >> 2) & 0x3fff_ffff)
15664            }
15665        }
15666        impl W {
15667            #[doc = "Bit 0 - Master for next LLI node: 0=Master1; 1=Master2"]
15668            #[inline(always)]
15669            pub fn dmac_lm_0(&mut self) -> DmacLm0W<'_, DmacLli_Spec> {
15670                DmacLm0W::new(self, 0)
15671            }
15672            #[doc = "Bits 2:31 - Linked list address \\[31:2\\]"]
15673            #[inline(always)]
15674            pub fn dmac_lli_0(&mut self) -> DmacLli0W<'_, DmacLli_Spec> {
15675                DmacLli0W::new(self, 2)
15676            }
15677        }
15678        #[doc = "Channel %s \\[dim=4\\] linked list register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_lli_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_lli_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15679        pub struct DmacLli_Spec;
15680        impl crate::RegisterSpec for DmacLli_Spec {
15681            type Ux = u32;
15682        }
15683        #[doc = "`read()` method returns [`dmac_lli_::R`](R) reader structure"]
15684        impl crate::Readable for DmacLli_Spec {}
15685        #[doc = "`write(|w| ..)` method takes [`dmac_lli_::W`](W) writer structure"]
15686        impl crate::Writable for DmacLli_Spec {
15687            type Safety = crate::Unsafe;
15688        }
15689        #[doc = "`reset()` method sets DMAC_LLI_%s to value 0"]
15690        impl crate::Resettable for DmacLli_Spec {}
15691    }
15692    #[doc = "DMAC_S_ADDR_ (rw) register accessor: Channel %s \\[dim=4\\] source address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_s_addr_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_s_addr_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_s_addr_`] module"]
15693    #[doc(alias = "DMAC_S_ADDR_")]
15694    pub type DmacSAddr_ = crate::Reg<dmac_s_addr_::DmacSAddr_Spec>;
15695    #[doc = "Channel %s \\[dim=4\\] source address"]
15696    pub mod dmac_s_addr_ {
15697        #[doc = "Register `DMAC_S_ADDR_%s` reader"]
15698        pub type R = crate::R<DmacSAddr_Spec>;
15699        #[doc = "Register `DMAC_S_ADDR_%s` writer"]
15700        pub type W = crate::W<DmacSAddr_Spec>;
15701        #[doc = "Field `dmac_s_addr_0` reader - Channel 0 source address"]
15702        pub type DmacSAddr0R = crate::FieldReader<u32>;
15703        #[doc = "Field `dmac_s_addr_0` writer - Channel 0 source address"]
15704        pub type DmacSAddr0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
15705        impl R {
15706            #[doc = "Bits 0:31 - Channel 0 source address"]
15707            #[inline(always)]
15708            pub fn dmac_s_addr_0(&self) -> DmacSAddr0R {
15709                DmacSAddr0R::new(self.bits)
15710            }
15711        }
15712        impl W {
15713            #[doc = "Bits 0:31 - Channel 0 source address"]
15714            #[inline(always)]
15715            pub fn dmac_s_addr_0(&mut self) -> DmacSAddr0W<'_, DmacSAddr_Spec> {
15716                DmacSAddr0W::new(self, 0)
15717            }
15718        }
15719        #[doc = "Channel %s \\[dim=4\\] source address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_s_addr_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_s_addr_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15720        pub struct DmacSAddr_Spec;
15721        impl crate::RegisterSpec for DmacSAddr_Spec {
15722            type Ux = u32;
15723        }
15724        #[doc = "`read()` method returns [`dmac_s_addr_::R`](R) reader structure"]
15725        impl crate::Readable for DmacSAddr_Spec {}
15726        #[doc = "`write(|w| ..)` method takes [`dmac_s_addr_::W`](W) writer structure"]
15727        impl crate::Writable for DmacSAddr_Spec {
15728            type Safety = crate::Unsafe;
15729        }
15730        #[doc = "`reset()` method sets DMAC_S_ADDR_%s to value 0"]
15731        impl crate::Resettable for DmacSAddr_Spec {}
15732    }
15733    #[doc = "DMAC_CHN_CONTROL_ (rw) register accessor: Channel %s \\[dim=4\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_control_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_control_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_chn_control_`] module"]
15734    #[doc(alias = "DMAC_CHN_CONTROL_")]
15735    pub type DmacChnControl_ = crate::Reg<dmac_chn_control_::DmacChnControl_Spec>;
15736    #[doc = "Channel %s \\[dim=4\\] control register"]
15737    pub mod dmac_chn_control_ {
15738        #[doc = "Register `DMAC_CHN_CONTROL_%s` reader"]
15739        pub type R = crate::R<DmacChnControl_Spec>;
15740        #[doc = "Register `DMAC_CHN_CONTROL_%s` writer"]
15741        pub type W = crate::W<DmacChnControl_Spec>;
15742        #[doc = "Field `dmac_trans_size_0` reader - Transfer size"]
15743        pub type DmacTransSize0R = crate::FieldReader<u16>;
15744        #[doc = "Field `dmac_trans_size_0` writer - Transfer size"]
15745        pub type DmacTransSize0W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
15746        #[doc = "Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256\n\nValue on reset: 0"]
15747        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
15748        #[repr(u8)]
15749        pub enum DmacSBsize0 {
15750            #[doc = "0: Burst size 1"]
15751            Bs1 = 0,
15752            #[doc = "1: Burst size 4"]
15753            Bs4 = 1,
15754            #[doc = "2: Burst size 8"]
15755            Bs8 = 2,
15756            #[doc = "3: Burst size 16"]
15757            Bs16 = 3,
15758            #[doc = "4: Burst size 32"]
15759            Bs32 = 4,
15760            #[doc = "5: Burst size 64"]
15761            Bs64 = 5,
15762            #[doc = "6: Burst size 128"]
15763            Bs128 = 6,
15764            #[doc = "7: Burst size 256"]
15765            Bs256 = 7,
15766        }
15767        impl From<DmacSBsize0> for u8 {
15768            #[inline(always)]
15769            fn from(variant: DmacSBsize0) -> Self {
15770                variant as _
15771            }
15772        }
15773        impl crate::FieldSpec for DmacSBsize0 {
15774            type Ux = u8;
15775        }
15776        impl crate::IsEnum for DmacSBsize0 {}
15777        #[doc = "Field `dmac_s_bsize_0` reader - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
15778        pub type DmacSBsize0R = crate::FieldReader<DmacSBsize0>;
15779        impl DmacSBsize0R {
15780            #[doc = "Get enumerated values variant"]
15781            #[inline(always)]
15782            pub const fn variant(&self) -> DmacSBsize0 {
15783                match self.bits {
15784                    0 => DmacSBsize0::Bs1,
15785                    1 => DmacSBsize0::Bs4,
15786                    2 => DmacSBsize0::Bs8,
15787                    3 => DmacSBsize0::Bs16,
15788                    4 => DmacSBsize0::Bs32,
15789                    5 => DmacSBsize0::Bs64,
15790                    6 => DmacSBsize0::Bs128,
15791                    7 => DmacSBsize0::Bs256,
15792                    _ => unreachable!(),
15793                }
15794            }
15795            #[doc = "Burst size 1"]
15796            #[inline(always)]
15797            pub fn is_bs1(&self) -> bool {
15798                *self == DmacSBsize0::Bs1
15799            }
15800            #[doc = "Burst size 4"]
15801            #[inline(always)]
15802            pub fn is_bs4(&self) -> bool {
15803                *self == DmacSBsize0::Bs4
15804            }
15805            #[doc = "Burst size 8"]
15806            #[inline(always)]
15807            pub fn is_bs8(&self) -> bool {
15808                *self == DmacSBsize0::Bs8
15809            }
15810            #[doc = "Burst size 16"]
15811            #[inline(always)]
15812            pub fn is_bs16(&self) -> bool {
15813                *self == DmacSBsize0::Bs16
15814            }
15815            #[doc = "Burst size 32"]
15816            #[inline(always)]
15817            pub fn is_bs32(&self) -> bool {
15818                *self == DmacSBsize0::Bs32
15819            }
15820            #[doc = "Burst size 64"]
15821            #[inline(always)]
15822            pub fn is_bs64(&self) -> bool {
15823                *self == DmacSBsize0::Bs64
15824            }
15825            #[doc = "Burst size 128"]
15826            #[inline(always)]
15827            pub fn is_bs128(&self) -> bool {
15828                *self == DmacSBsize0::Bs128
15829            }
15830            #[doc = "Burst size 256"]
15831            #[inline(always)]
15832            pub fn is_bs256(&self) -> bool {
15833                *self == DmacSBsize0::Bs256
15834            }
15835        }
15836        #[doc = "Field `dmac_s_bsize_0` writer - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
15837        pub type DmacSBsize0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacSBsize0, crate::Safe>;
15838        impl<'a, REG> DmacSBsize0W<'a, REG>
15839        where
15840            REG: crate::Writable + crate::RegisterSpec,
15841            REG::Ux: From<u8>,
15842        {
15843            #[doc = "Burst size 1"]
15844            #[inline(always)]
15845            pub fn bs1(self) -> &'a mut crate::W<REG> {
15846                self.variant(DmacSBsize0::Bs1)
15847            }
15848            #[doc = "Burst size 4"]
15849            #[inline(always)]
15850            pub fn bs4(self) -> &'a mut crate::W<REG> {
15851                self.variant(DmacSBsize0::Bs4)
15852            }
15853            #[doc = "Burst size 8"]
15854            #[inline(always)]
15855            pub fn bs8(self) -> &'a mut crate::W<REG> {
15856                self.variant(DmacSBsize0::Bs8)
15857            }
15858            #[doc = "Burst size 16"]
15859            #[inline(always)]
15860            pub fn bs16(self) -> &'a mut crate::W<REG> {
15861                self.variant(DmacSBsize0::Bs16)
15862            }
15863            #[doc = "Burst size 32"]
15864            #[inline(always)]
15865            pub fn bs32(self) -> &'a mut crate::W<REG> {
15866                self.variant(DmacSBsize0::Bs32)
15867            }
15868            #[doc = "Burst size 64"]
15869            #[inline(always)]
15870            pub fn bs64(self) -> &'a mut crate::W<REG> {
15871                self.variant(DmacSBsize0::Bs64)
15872            }
15873            #[doc = "Burst size 128"]
15874            #[inline(always)]
15875            pub fn bs128(self) -> &'a mut crate::W<REG> {
15876                self.variant(DmacSBsize0::Bs128)
15877            }
15878            #[doc = "Burst size 256"]
15879            #[inline(always)]
15880            pub fn bs256(self) -> &'a mut crate::W<REG> {
15881                self.variant(DmacSBsize0::Bs256)
15882            }
15883        }
15884        #[doc = "Field `dmac_d_bsize_0` reader - Destination burst size"]
15885        pub type DmacDBsize0R = crate::FieldReader;
15886        #[doc = "Field `dmac_d_bsize_0` writer - Destination burst size"]
15887        pub type DmacDBsize0W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
15888        #[doc = "Source width: 000=8bit; 001=16bit; 010=32bit\n\nValue on reset: 0"]
15889        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
15890        #[repr(u8)]
15891        pub enum DmacSWidth0 {
15892            #[doc = "0: 8-bit"]
15893            Byte = 0,
15894            #[doc = "1: 16-bit"]
15895            Halfword = 1,
15896            #[doc = "2: 32-bit"]
15897            Word = 2,
15898        }
15899        impl From<DmacSWidth0> for u8 {
15900            #[inline(always)]
15901            fn from(variant: DmacSWidth0) -> Self {
15902                variant as _
15903            }
15904        }
15905        impl crate::FieldSpec for DmacSWidth0 {
15906            type Ux = u8;
15907        }
15908        impl crate::IsEnum for DmacSWidth0 {}
15909        #[doc = "Field `dmac_s_width_0` reader - Source width: 000=8bit; 001=16bit; 010=32bit"]
15910        pub type DmacSWidth0R = crate::FieldReader<DmacSWidth0>;
15911        impl DmacSWidth0R {
15912            #[doc = "Get enumerated values variant"]
15913            #[inline(always)]
15914            pub const fn variant(&self) -> Option<DmacSWidth0> {
15915                match self.bits {
15916                    0 => Some(DmacSWidth0::Byte),
15917                    1 => Some(DmacSWidth0::Halfword),
15918                    2 => Some(DmacSWidth0::Word),
15919                    _ => None,
15920                }
15921            }
15922            #[doc = "8-bit"]
15923            #[inline(always)]
15924            pub fn is_byte(&self) -> bool {
15925                *self == DmacSWidth0::Byte
15926            }
15927            #[doc = "16-bit"]
15928            #[inline(always)]
15929            pub fn is_halfword(&self) -> bool {
15930                *self == DmacSWidth0::Halfword
15931            }
15932            #[doc = "32-bit"]
15933            #[inline(always)]
15934            pub fn is_word(&self) -> bool {
15935                *self == DmacSWidth0::Word
15936            }
15937        }
15938        #[doc = "Field `dmac_s_width_0` writer - Source width: 000=8bit; 001=16bit; 010=32bit"]
15939        pub type DmacSWidth0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacSWidth0>;
15940        impl<'a, REG> DmacSWidth0W<'a, REG>
15941        where
15942            REG: crate::Writable + crate::RegisterSpec,
15943            REG::Ux: From<u8>,
15944        {
15945            #[doc = "8-bit"]
15946            #[inline(always)]
15947            pub fn byte(self) -> &'a mut crate::W<REG> {
15948                self.variant(DmacSWidth0::Byte)
15949            }
15950            #[doc = "16-bit"]
15951            #[inline(always)]
15952            pub fn halfword(self) -> &'a mut crate::W<REG> {
15953                self.variant(DmacSWidth0::Halfword)
15954            }
15955            #[doc = "32-bit"]
15956            #[inline(always)]
15957            pub fn word(self) -> &'a mut crate::W<REG> {
15958                self.variant(DmacSWidth0::Word)
15959            }
15960        }
15961        #[doc = "Destination width\n\nValue on reset: 0"]
15962        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
15963        #[repr(u8)]
15964        pub enum DmacDWidth0 {
15965            #[doc = "0: 8-bit"]
15966            Byte = 0,
15967            #[doc = "1: 16-bit"]
15968            Halfword = 1,
15969            #[doc = "2: 32-bit"]
15970            Word = 2,
15971        }
15972        impl From<DmacDWidth0> for u8 {
15973            #[inline(always)]
15974            fn from(variant: DmacDWidth0) -> Self {
15975                variant as _
15976            }
15977        }
15978        impl crate::FieldSpec for DmacDWidth0 {
15979            type Ux = u8;
15980        }
15981        impl crate::IsEnum for DmacDWidth0 {}
15982        #[doc = "Field `dmac_d_width_0` reader - Destination width"]
15983        pub type DmacDWidth0R = crate::FieldReader<DmacDWidth0>;
15984        impl DmacDWidth0R {
15985            #[doc = "Get enumerated values variant"]
15986            #[inline(always)]
15987            pub const fn variant(&self) -> Option<DmacDWidth0> {
15988                match self.bits {
15989                    0 => Some(DmacDWidth0::Byte),
15990                    1 => Some(DmacDWidth0::Halfword),
15991                    2 => Some(DmacDWidth0::Word),
15992                    _ => None,
15993                }
15994            }
15995            #[doc = "8-bit"]
15996            #[inline(always)]
15997            pub fn is_byte(&self) -> bool {
15998                *self == DmacDWidth0::Byte
15999            }
16000            #[doc = "16-bit"]
16001            #[inline(always)]
16002            pub fn is_halfword(&self) -> bool {
16003                *self == DmacDWidth0::Halfword
16004            }
16005            #[doc = "32-bit"]
16006            #[inline(always)]
16007            pub fn is_word(&self) -> bool {
16008                *self == DmacDWidth0::Word
16009            }
16010        }
16011        #[doc = "Field `dmac_d_width_0` writer - Destination width"]
16012        pub type DmacDWidth0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacDWidth0>;
16013        impl<'a, REG> DmacDWidth0W<'a, REG>
16014        where
16015            REG: crate::Writable + crate::RegisterSpec,
16016            REG::Ux: From<u8>,
16017        {
16018            #[doc = "8-bit"]
16019            #[inline(always)]
16020            pub fn byte(self) -> &'a mut crate::W<REG> {
16021                self.variant(DmacDWidth0::Byte)
16022            }
16023            #[doc = "16-bit"]
16024            #[inline(always)]
16025            pub fn halfword(self) -> &'a mut crate::W<REG> {
16026                self.variant(DmacDWidth0::Halfword)
16027            }
16028            #[doc = "32-bit"]
16029            #[inline(always)]
16030            pub fn word(self) -> &'a mut crate::W<REG> {
16031                self.variant(DmacDWidth0::Word)
16032            }
16033        }
16034        #[doc = "Field `dmac_s_master_0` reader - Source master: 0=Master1; 1=Master2"]
16035        pub type DmacSMaster0R = crate::BitReader;
16036        #[doc = "Field `dmac_s_master_0` writer - Source master: 0=Master1; 1=Master2"]
16037        pub type DmacSMaster0W<'a, REG> = crate::BitWriter<'a, REG>;
16038        #[doc = "Field `dmac_d_master_0` reader - Destination master"]
16039        pub type DmacDMaster0R = crate::BitReader;
16040        #[doc = "Field `dmac_d_master_0` writer - Destination master"]
16041        pub type DmacDMaster0W<'a, REG> = crate::BitWriter<'a, REG>;
16042        #[doc = "Field `dmac_s_inc_0` reader - Source address increment: 0=no; 1=yes"]
16043        pub type DmacSInc0R = crate::BitReader;
16044        #[doc = "Field `dmac_s_inc_0` writer - Source address increment: 0=no; 1=yes"]
16045        pub type DmacSInc0W<'a, REG> = crate::BitWriter<'a, REG>;
16046        #[doc = "Field `dmac_d_inc_0` reader - Destination address increment"]
16047        pub type DmacDInc0R = crate::BitReader;
16048        #[doc = "Field `dmac_d_inc_0` writer - Destination address increment"]
16049        pub type DmacDInc0W<'a, REG> = crate::BitWriter<'a, REG>;
16050        #[doc = "Field `dmac_prot_0` reader - Protection HPROT\\[2:0\\]"]
16051        pub type DmacProt0R = crate::FieldReader;
16052        #[doc = "Field `dmac_prot_0` writer - Protection HPROT\\[2:0\\]"]
16053        pub type DmacProt0W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
16054        #[doc = "Field `dmac_trans_int_0` reader - Transfer complete interrupt enable"]
16055        pub type DmacTransInt0R = crate::BitReader;
16056        #[doc = "Field `dmac_trans_int_0` writer - Transfer complete interrupt enable"]
16057        pub type DmacTransInt0W<'a, REG> = crate::BitWriter<'a, REG>;
16058        impl R {
16059            #[doc = "Bits 0:11 - Transfer size"]
16060            #[inline(always)]
16061            pub fn dmac_trans_size_0(&self) -> DmacTransSize0R {
16062                DmacTransSize0R::new((self.bits & 0x0fff) as u16)
16063            }
16064            #[doc = "Bits 12:14 - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
16065            #[inline(always)]
16066            pub fn dmac_s_bsize_0(&self) -> DmacSBsize0R {
16067                DmacSBsize0R::new(((self.bits >> 12) & 7) as u8)
16068            }
16069            #[doc = "Bits 15:17 - Destination burst size"]
16070            #[inline(always)]
16071            pub fn dmac_d_bsize_0(&self) -> DmacDBsize0R {
16072                DmacDBsize0R::new(((self.bits >> 15) & 7) as u8)
16073            }
16074            #[doc = "Bits 18:20 - Source width: 000=8bit; 001=16bit; 010=32bit"]
16075            #[inline(always)]
16076            pub fn dmac_s_width_0(&self) -> DmacSWidth0R {
16077                DmacSWidth0R::new(((self.bits >> 18) & 7) as u8)
16078            }
16079            #[doc = "Bits 21:23 - Destination width"]
16080            #[inline(always)]
16081            pub fn dmac_d_width_0(&self) -> DmacDWidth0R {
16082                DmacDWidth0R::new(((self.bits >> 21) & 7) as u8)
16083            }
16084            #[doc = "Bit 24 - Source master: 0=Master1; 1=Master2"]
16085            #[inline(always)]
16086            pub fn dmac_s_master_0(&self) -> DmacSMaster0R {
16087                DmacSMaster0R::new(((self.bits >> 24) & 1) != 0)
16088            }
16089            #[doc = "Bit 25 - Destination master"]
16090            #[inline(always)]
16091            pub fn dmac_d_master_0(&self) -> DmacDMaster0R {
16092                DmacDMaster0R::new(((self.bits >> 25) & 1) != 0)
16093            }
16094            #[doc = "Bit 26 - Source address increment: 0=no; 1=yes"]
16095            #[inline(always)]
16096            pub fn dmac_s_inc_0(&self) -> DmacSInc0R {
16097                DmacSInc0R::new(((self.bits >> 26) & 1) != 0)
16098            }
16099            #[doc = "Bit 27 - Destination address increment"]
16100            #[inline(always)]
16101            pub fn dmac_d_inc_0(&self) -> DmacDInc0R {
16102                DmacDInc0R::new(((self.bits >> 27) & 1) != 0)
16103            }
16104            #[doc = "Bits 28:30 - Protection HPROT\\[2:0\\]"]
16105            #[inline(always)]
16106            pub fn dmac_prot_0(&self) -> DmacProt0R {
16107                DmacProt0R::new(((self.bits >> 28) & 7) as u8)
16108            }
16109            #[doc = "Bit 31 - Transfer complete interrupt enable"]
16110            #[inline(always)]
16111            pub fn dmac_trans_int_0(&self) -> DmacTransInt0R {
16112                DmacTransInt0R::new(((self.bits >> 31) & 1) != 0)
16113            }
16114        }
16115        impl W {
16116            #[doc = "Bits 0:11 - Transfer size"]
16117            #[inline(always)]
16118            pub fn dmac_trans_size_0(&mut self) -> DmacTransSize0W<'_, DmacChnControl_Spec> {
16119                DmacTransSize0W::new(self, 0)
16120            }
16121            #[doc = "Bits 12:14 - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
16122            #[inline(always)]
16123            pub fn dmac_s_bsize_0(&mut self) -> DmacSBsize0W<'_, DmacChnControl_Spec> {
16124                DmacSBsize0W::new(self, 12)
16125            }
16126            #[doc = "Bits 15:17 - Destination burst size"]
16127            #[inline(always)]
16128            pub fn dmac_d_bsize_0(&mut self) -> DmacDBsize0W<'_, DmacChnControl_Spec> {
16129                DmacDBsize0W::new(self, 15)
16130            }
16131            #[doc = "Bits 18:20 - Source width: 000=8bit; 001=16bit; 010=32bit"]
16132            #[inline(always)]
16133            pub fn dmac_s_width_0(&mut self) -> DmacSWidth0W<'_, DmacChnControl_Spec> {
16134                DmacSWidth0W::new(self, 18)
16135            }
16136            #[doc = "Bits 21:23 - Destination width"]
16137            #[inline(always)]
16138            pub fn dmac_d_width_0(&mut self) -> DmacDWidth0W<'_, DmacChnControl_Spec> {
16139                DmacDWidth0W::new(self, 21)
16140            }
16141            #[doc = "Bit 24 - Source master: 0=Master1; 1=Master2"]
16142            #[inline(always)]
16143            pub fn dmac_s_master_0(&mut self) -> DmacSMaster0W<'_, DmacChnControl_Spec> {
16144                DmacSMaster0W::new(self, 24)
16145            }
16146            #[doc = "Bit 25 - Destination master"]
16147            #[inline(always)]
16148            pub fn dmac_d_master_0(&mut self) -> DmacDMaster0W<'_, DmacChnControl_Spec> {
16149                DmacDMaster0W::new(self, 25)
16150            }
16151            #[doc = "Bit 26 - Source address increment: 0=no; 1=yes"]
16152            #[inline(always)]
16153            pub fn dmac_s_inc_0(&mut self) -> DmacSInc0W<'_, DmacChnControl_Spec> {
16154                DmacSInc0W::new(self, 26)
16155            }
16156            #[doc = "Bit 27 - Destination address increment"]
16157            #[inline(always)]
16158            pub fn dmac_d_inc_0(&mut self) -> DmacDInc0W<'_, DmacChnControl_Spec> {
16159                DmacDInc0W::new(self, 27)
16160            }
16161            #[doc = "Bits 28:30 - Protection HPROT\\[2:0\\]"]
16162            #[inline(always)]
16163            pub fn dmac_prot_0(&mut self) -> DmacProt0W<'_, DmacChnControl_Spec> {
16164                DmacProt0W::new(self, 28)
16165            }
16166            #[doc = "Bit 31 - Transfer complete interrupt enable"]
16167            #[inline(always)]
16168            pub fn dmac_trans_int_0(&mut self) -> DmacTransInt0W<'_, DmacChnControl_Spec> {
16169                DmacTransInt0W::new(self, 31)
16170            }
16171        }
16172        #[doc = "Channel %s \\[dim=4\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_control_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_control_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16173        pub struct DmacChnControl_Spec;
16174        impl crate::RegisterSpec for DmacChnControl_Spec {
16175            type Ux = u32;
16176        }
16177        #[doc = "`read()` method returns [`dmac_chn_control_::R`](R) reader structure"]
16178        impl crate::Readable for DmacChnControl_Spec {}
16179        #[doc = "`write(|w| ..)` method takes [`dmac_chn_control_::W`](W) writer structure"]
16180        impl crate::Writable for DmacChnControl_Spec {
16181            type Safety = crate::Unsafe;
16182        }
16183        #[doc = "`reset()` method sets DMAC_CHN_CONTROL_%s to value 0"]
16184        impl crate::Resettable for DmacChnControl_Spec {}
16185    }
16186    #[doc = "DMAC_CHN_CONFIG_ (rw) register accessor: Channel %s \\[dim=4\\] configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_config_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_config_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_chn_config_`] module"]
16187    #[doc(alias = "DMAC_CHN_CONFIG_")]
16188    pub type DmacChnConfig_ = crate::Reg<dmac_chn_config_::DmacChnConfig_Spec>;
16189    #[doc = "Channel %s \\[dim=4\\] configuration register"]
16190    pub mod dmac_chn_config_ {
16191        #[doc = "Register `DMAC_CHN_CONFIG_%s` reader"]
16192        pub type R = crate::R<DmacChnConfig_Spec>;
16193        #[doc = "Register `DMAC_CHN_CONFIG_%s` writer"]
16194        pub type W = crate::W<DmacChnConfig_Spec>;
16195        #[doc = "Field `dmac_chn_en_0` reader - Channel enable: 0=disable; 1=enable"]
16196        pub type DmacChnEn0R = crate::BitReader;
16197        #[doc = "Field `dmac_chn_en_0` writer - Channel enable: 0=disable; 1=enable"]
16198        pub type DmacChnEn0W<'a, REG> = crate::BitWriter<'a, REG>;
16199        #[doc = "Field `dmac_s_peripheral_0` reader - Source peripheral select"]
16200        pub type DmacSPeripheral0R = crate::FieldReader;
16201        #[doc = "Field `dmac_s_peripheral_0` writer - Source peripheral select"]
16202        pub type DmacSPeripheral0W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
16203        #[doc = "Field `dmac_d_peripheral_0` reader - Destination peripheral select"]
16204        pub type DmacDPeripheral0R = crate::FieldReader;
16205        #[doc = "Field `dmac_d_peripheral_0` writer - Destination peripheral select"]
16206        pub type DmacDPeripheral0W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
16207        #[doc = "Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)\n\nValue on reset: 0"]
16208        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
16209        #[repr(u8)]
16210        pub enum DmacFlowCtl0 {
16211            #[doc = "0: Memory to Memory, DMAC flow control"]
16212            Mem2memDmac = 0,
16213            #[doc = "1: Memory to Peripheral, DMAC flow control"]
16214            Mem2perDmac = 1,
16215            #[doc = "2: Peripheral to Memory, DMAC flow control"]
16216            Per2memDmac = 2,
16217            #[doc = "3: Peripheral to Peripheral, DMAC flow control"]
16218            Per2perDmac = 3,
16219            #[doc = "4: Peripheral to Peripheral, Destination flow control"]
16220            Per2perDst = 4,
16221            #[doc = "5: Memory to Peripheral, Destination flow control"]
16222            Mem2perDst = 5,
16223            #[doc = "6: Peripheral to Memory, Source flow control"]
16224            Per2memSrc = 6,
16225            #[doc = "7: Peripheral to Peripheral, Source flow control"]
16226            Per2perSrc = 7,
16227        }
16228        impl From<DmacFlowCtl0> for u8 {
16229            #[inline(always)]
16230            fn from(variant: DmacFlowCtl0) -> Self {
16231                variant as _
16232            }
16233        }
16234        impl crate::FieldSpec for DmacFlowCtl0 {
16235            type Ux = u8;
16236        }
16237        impl crate::IsEnum for DmacFlowCtl0 {}
16238        #[doc = "Field `dmac_flow_ctl_0` reader - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
16239        pub type DmacFlowCtl0R = crate::FieldReader<DmacFlowCtl0>;
16240        impl DmacFlowCtl0R {
16241            #[doc = "Get enumerated values variant"]
16242            #[inline(always)]
16243            pub const fn variant(&self) -> DmacFlowCtl0 {
16244                match self.bits {
16245                    0 => DmacFlowCtl0::Mem2memDmac,
16246                    1 => DmacFlowCtl0::Mem2perDmac,
16247                    2 => DmacFlowCtl0::Per2memDmac,
16248                    3 => DmacFlowCtl0::Per2perDmac,
16249                    4 => DmacFlowCtl0::Per2perDst,
16250                    5 => DmacFlowCtl0::Mem2perDst,
16251                    6 => DmacFlowCtl0::Per2memSrc,
16252                    7 => DmacFlowCtl0::Per2perSrc,
16253                    _ => unreachable!(),
16254                }
16255            }
16256            #[doc = "Memory to Memory, DMAC flow control"]
16257            #[inline(always)]
16258            pub fn is_mem2mem_dmac(&self) -> bool {
16259                *self == DmacFlowCtl0::Mem2memDmac
16260            }
16261            #[doc = "Memory to Peripheral, DMAC flow control"]
16262            #[inline(always)]
16263            pub fn is_mem2per_dmac(&self) -> bool {
16264                *self == DmacFlowCtl0::Mem2perDmac
16265            }
16266            #[doc = "Peripheral to Memory, DMAC flow control"]
16267            #[inline(always)]
16268            pub fn is_per2mem_dmac(&self) -> bool {
16269                *self == DmacFlowCtl0::Per2memDmac
16270            }
16271            #[doc = "Peripheral to Peripheral, DMAC flow control"]
16272            #[inline(always)]
16273            pub fn is_per2per_dmac(&self) -> bool {
16274                *self == DmacFlowCtl0::Per2perDmac
16275            }
16276            #[doc = "Peripheral to Peripheral, Destination flow control"]
16277            #[inline(always)]
16278            pub fn is_per2per_dst(&self) -> bool {
16279                *self == DmacFlowCtl0::Per2perDst
16280            }
16281            #[doc = "Memory to Peripheral, Destination flow control"]
16282            #[inline(always)]
16283            pub fn is_mem2per_dst(&self) -> bool {
16284                *self == DmacFlowCtl0::Mem2perDst
16285            }
16286            #[doc = "Peripheral to Memory, Source flow control"]
16287            #[inline(always)]
16288            pub fn is_per2mem_src(&self) -> bool {
16289                *self == DmacFlowCtl0::Per2memSrc
16290            }
16291            #[doc = "Peripheral to Peripheral, Source flow control"]
16292            #[inline(always)]
16293            pub fn is_per2per_src(&self) -> bool {
16294                *self == DmacFlowCtl0::Per2perSrc
16295            }
16296        }
16297        #[doc = "Field `dmac_flow_ctl_0` writer - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
16298        pub type DmacFlowCtl0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacFlowCtl0, crate::Safe>;
16299        impl<'a, REG> DmacFlowCtl0W<'a, REG>
16300        where
16301            REG: crate::Writable + crate::RegisterSpec,
16302            REG::Ux: From<u8>,
16303        {
16304            #[doc = "Memory to Memory, DMAC flow control"]
16305            #[inline(always)]
16306            pub fn mem2mem_dmac(self) -> &'a mut crate::W<REG> {
16307                self.variant(DmacFlowCtl0::Mem2memDmac)
16308            }
16309            #[doc = "Memory to Peripheral, DMAC flow control"]
16310            #[inline(always)]
16311            pub fn mem2per_dmac(self) -> &'a mut crate::W<REG> {
16312                self.variant(DmacFlowCtl0::Mem2perDmac)
16313            }
16314            #[doc = "Peripheral to Memory, DMAC flow control"]
16315            #[inline(always)]
16316            pub fn per2mem_dmac(self) -> &'a mut crate::W<REG> {
16317                self.variant(DmacFlowCtl0::Per2memDmac)
16318            }
16319            #[doc = "Peripheral to Peripheral, DMAC flow control"]
16320            #[inline(always)]
16321            pub fn per2per_dmac(self) -> &'a mut crate::W<REG> {
16322                self.variant(DmacFlowCtl0::Per2perDmac)
16323            }
16324            #[doc = "Peripheral to Peripheral, Destination flow control"]
16325            #[inline(always)]
16326            pub fn per2per_dst(self) -> &'a mut crate::W<REG> {
16327                self.variant(DmacFlowCtl0::Per2perDst)
16328            }
16329            #[doc = "Memory to Peripheral, Destination flow control"]
16330            #[inline(always)]
16331            pub fn mem2per_dst(self) -> &'a mut crate::W<REG> {
16332                self.variant(DmacFlowCtl0::Mem2perDst)
16333            }
16334            #[doc = "Peripheral to Memory, Source flow control"]
16335            #[inline(always)]
16336            pub fn per2mem_src(self) -> &'a mut crate::W<REG> {
16337                self.variant(DmacFlowCtl0::Per2memSrc)
16338            }
16339            #[doc = "Peripheral to Peripheral, Source flow control"]
16340            #[inline(always)]
16341            pub fn per2per_src(self) -> &'a mut crate::W<REG> {
16342                self.variant(DmacFlowCtl0::Per2perSrc)
16343            }
16344        }
16345        #[doc = "Field `dmac_int_en_0` reader - Error interrupt mask: 0=masked; 1=unmasked"]
16346        pub type DmacIntEn0R = crate::BitReader;
16347        #[doc = "Field `dmac_int_en_0` writer - Error interrupt mask: 0=masked; 1=unmasked"]
16348        pub type DmacIntEn0W<'a, REG> = crate::BitWriter<'a, REG>;
16349        #[doc = "Field `dmac_int_tc_0` reader - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
16350        pub type DmacIntTc0R = crate::BitReader;
16351        #[doc = "Field `dmac_int_tc_0` writer - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
16352        pub type DmacIntTc0W<'a, REG> = crate::BitWriter<'a, REG>;
16353        #[doc = "Field `dmac_lock_0` reader - Bus lock: 0=disabled; 1=enabled"]
16354        pub type DmacLock0R = crate::BitReader;
16355        #[doc = "Field `dmac_lock_0` writer - Bus lock: 0=disabled; 1=enabled"]
16356        pub type DmacLock0W<'a, REG> = crate::BitWriter<'a, REG>;
16357        #[doc = "Field `dmac_active_0` reader - FIFO has data: 0=no; 1=yes"]
16358        pub type DmacActive0R = crate::BitReader;
16359        #[doc = "Field `dmac_halt_0` reader - Halt: 0=allow DMA; 1=ignore DMA requests"]
16360        pub type DmacHalt0R = crate::BitReader;
16361        #[doc = "Field `dmac_halt_0` writer - Halt: 0=allow DMA; 1=ignore DMA requests"]
16362        pub type DmacHalt0W<'a, REG> = crate::BitWriter<'a, REG>;
16363        impl R {
16364            #[doc = "Bit 0 - Channel enable: 0=disable; 1=enable"]
16365            #[inline(always)]
16366            pub fn dmac_chn_en_0(&self) -> DmacChnEn0R {
16367                DmacChnEn0R::new((self.bits & 1) != 0)
16368            }
16369            #[doc = "Bits 1:4 - Source peripheral select"]
16370            #[inline(always)]
16371            pub fn dmac_s_peripheral_0(&self) -> DmacSPeripheral0R {
16372                DmacSPeripheral0R::new(((self.bits >> 1) & 0x0f) as u8)
16373            }
16374            #[doc = "Bits 5:8 - Destination peripheral select"]
16375            #[inline(always)]
16376            pub fn dmac_d_peripheral_0(&self) -> DmacDPeripheral0R {
16377                DmacDPeripheral0R::new(((self.bits >> 5) & 0x0f) as u8)
16378            }
16379            #[doc = "Bits 9:11 - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
16380            #[inline(always)]
16381            pub fn dmac_flow_ctl_0(&self) -> DmacFlowCtl0R {
16382                DmacFlowCtl0R::new(((self.bits >> 9) & 7) as u8)
16383            }
16384            #[doc = "Bit 12 - Error interrupt mask: 0=masked; 1=unmasked"]
16385            #[inline(always)]
16386            pub fn dmac_int_en_0(&self) -> DmacIntEn0R {
16387                DmacIntEn0R::new(((self.bits >> 12) & 1) != 0)
16388            }
16389            #[doc = "Bit 13 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
16390            #[inline(always)]
16391            pub fn dmac_int_tc_0(&self) -> DmacIntTc0R {
16392                DmacIntTc0R::new(((self.bits >> 13) & 1) != 0)
16393            }
16394            #[doc = "Bit 14 - Bus lock: 0=disabled; 1=enabled"]
16395            #[inline(always)]
16396            pub fn dmac_lock_0(&self) -> DmacLock0R {
16397                DmacLock0R::new(((self.bits >> 14) & 1) != 0)
16398            }
16399            #[doc = "Bit 15 - FIFO has data: 0=no; 1=yes"]
16400            #[inline(always)]
16401            pub fn dmac_active_0(&self) -> DmacActive0R {
16402                DmacActive0R::new(((self.bits >> 15) & 1) != 0)
16403            }
16404            #[doc = "Bit 16 - Halt: 0=allow DMA; 1=ignore DMA requests"]
16405            #[inline(always)]
16406            pub fn dmac_halt_0(&self) -> DmacHalt0R {
16407                DmacHalt0R::new(((self.bits >> 16) & 1) != 0)
16408            }
16409        }
16410        impl W {
16411            #[doc = "Bit 0 - Channel enable: 0=disable; 1=enable"]
16412            #[inline(always)]
16413            pub fn dmac_chn_en_0(&mut self) -> DmacChnEn0W<'_, DmacChnConfig_Spec> {
16414                DmacChnEn0W::new(self, 0)
16415            }
16416            #[doc = "Bits 1:4 - Source peripheral select"]
16417            #[inline(always)]
16418            pub fn dmac_s_peripheral_0(&mut self) -> DmacSPeripheral0W<'_, DmacChnConfig_Spec> {
16419                DmacSPeripheral0W::new(self, 1)
16420            }
16421            #[doc = "Bits 5:8 - Destination peripheral select"]
16422            #[inline(always)]
16423            pub fn dmac_d_peripheral_0(&mut self) -> DmacDPeripheral0W<'_, DmacChnConfig_Spec> {
16424                DmacDPeripheral0W::new(self, 5)
16425            }
16426            #[doc = "Bits 9:11 - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
16427            #[inline(always)]
16428            pub fn dmac_flow_ctl_0(&mut self) -> DmacFlowCtl0W<'_, DmacChnConfig_Spec> {
16429                DmacFlowCtl0W::new(self, 9)
16430            }
16431            #[doc = "Bit 12 - Error interrupt mask: 0=masked; 1=unmasked"]
16432            #[inline(always)]
16433            pub fn dmac_int_en_0(&mut self) -> DmacIntEn0W<'_, DmacChnConfig_Spec> {
16434                DmacIntEn0W::new(self, 12)
16435            }
16436            #[doc = "Bit 13 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
16437            #[inline(always)]
16438            pub fn dmac_int_tc_0(&mut self) -> DmacIntTc0W<'_, DmacChnConfig_Spec> {
16439                DmacIntTc0W::new(self, 13)
16440            }
16441            #[doc = "Bit 14 - Bus lock: 0=disabled; 1=enabled"]
16442            #[inline(always)]
16443            pub fn dmac_lock_0(&mut self) -> DmacLock0W<'_, DmacChnConfig_Spec> {
16444                DmacLock0W::new(self, 14)
16445            }
16446            #[doc = "Bit 16 - Halt: 0=allow DMA; 1=ignore DMA requests"]
16447            #[inline(always)]
16448            pub fn dmac_halt_0(&mut self) -> DmacHalt0W<'_, DmacChnConfig_Spec> {
16449                DmacHalt0W::new(self, 16)
16450            }
16451        }
16452        #[doc = "Channel %s \\[dim=4\\] configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_config_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_config_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16453        pub struct DmacChnConfig_Spec;
16454        impl crate::RegisterSpec for DmacChnConfig_Spec {
16455            type Ux = u32;
16456        }
16457        #[doc = "`read()` method returns [`dmac_chn_config_::R`](R) reader structure"]
16458        impl crate::Readable for DmacChnConfig_Spec {}
16459        #[doc = "`write(|w| ..)` method takes [`dmac_chn_config_::W`](W) writer structure"]
16460        impl crate::Writable for DmacChnConfig_Spec {
16461            type Safety = crate::Unsafe;
16462        }
16463        #[doc = "`reset()` method sets DMAC_CHN_CONFIG_%s to value 0"]
16464        impl crate::Resettable for DmacChnConfig_Spec {}
16465    }
16466}
16467#[doc = "SPI Flash Controller configuration"]
16468pub type SfcCfg = crate::Periph<sfc_cfg::RegisterBlock, 0x4800_0000>;
16469impl core::fmt::Debug for SfcCfg {
16470    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
16471        f.debug_struct("SfcCfg").finish()
16472    }
16473}
16474#[doc = "SPI Flash Controller configuration"]
16475pub mod sfc_cfg {
16476    #[repr(C)]
16477    #[doc = "Register block"]
16478    pub struct RegisterBlock {
16479        _reserved0: [u8; 0x0100],
16480        global_config: GlobalConfig,
16481        _reserved1: [u8; 0x0c],
16482        timing: Timing,
16483        _reserved2: [u8; 0x0c],
16484        int_raw_status: IntRawStatus,
16485        int_status: IntStatus,
16486        int_mask: IntMask,
16487        int_clear: IntClear,
16488        soft_rst_mask: SoftRstMask,
16489        _reserved7: [u8; 0xcc],
16490        bus_config1: BusConfig1,
16491        bus_config2: BusConfig2,
16492        _reserved9: [u8; 0x38],
16493        bus_dma_ctrl: BusDmaCtrl,
16494        bus_dma_mem_saddr: BusDmaMemSaddr,
16495        bus_dma_flash_saddr: BusDmaFlashSaddr,
16496        bus_dma_len: BusDmaLen,
16497        bus_dma_ahb_ctrl: BusDmaAhbCtrl,
16498        _reserved14: [u8; 0xac],
16499        cmd_config: CmdConfig,
16500        _reserved15: [u8; 0x04],
16501        cmd_ins: CmdIns,
16502        cmd_addr: CmdAddr,
16503        _reserved17: [u8; 0xf0],
16504        cmd_databuf_0: CmdDatabuf0,
16505        cmd_databuf_1: CmdDatabuf1,
16506        cmd_databuf_2: CmdDatabuf2,
16507        cmd_databuf_3: CmdDatabuf3,
16508        cmd_databuf_4: CmdDatabuf4,
16509        cmd_databuf_5: CmdDatabuf5,
16510        cmd_databuf_6: CmdDatabuf6,
16511        cmd_databuf_7: CmdDatabuf7,
16512        cmd_databuf_8: CmdDatabuf8,
16513        cmd_databuf_9: CmdDatabuf9,
16514        cmd_databuf_10: CmdDatabuf10,
16515        cmd_databuf_11: CmdDatabuf11,
16516        cmd_databuf_12: CmdDatabuf12,
16517        cmd_databuf_13: CmdDatabuf13,
16518        cmd_databuf_14: CmdDatabuf14,
16519        cmd_databuf_15: CmdDatabuf15,
16520        _reserved33: [u8; 0x0ec0],
16521        lea_lp_en: LeaLpEn,
16522        lea_dfx_info: LeaDfxInfo,
16523        _reserved35: [u8; 0x02f8],
16524        lea_iv_vld: LeaIvVld,
16525    }
16526    impl RegisterBlock {
16527        #[doc = "0x100 - Global configuration register"]
16528        #[inline(always)]
16529        pub const fn global_config(&self) -> &GlobalConfig {
16530            &self.global_config
16531        }
16532        #[doc = "0x110 - Timing configuration register"]
16533        #[inline(always)]
16534        pub const fn timing(&self) -> &Timing {
16535            &self.timing
16536        }
16537        #[doc = "0x120 - Interrupt raw status register"]
16538        #[inline(always)]
16539        pub const fn int_raw_status(&self) -> &IntRawStatus {
16540            &self.int_raw_status
16541        }
16542        #[doc = "0x124 - Interrupt status register (masked)"]
16543        #[inline(always)]
16544        pub const fn int_status(&self) -> &IntStatus {
16545            &self.int_status
16546        }
16547        #[doc = "0x128 - Interrupt mask register"]
16548        #[inline(always)]
16549        pub const fn int_mask(&self) -> &IntMask {
16550            &self.int_mask
16551        }
16552        #[doc = "0x12c - Interrupt clear register"]
16553        #[inline(always)]
16554        pub const fn int_clear(&self) -> &IntClear {
16555            &self.int_clear
16556        }
16557        #[doc = "0x130 - Soft reset mask register"]
16558        #[inline(always)]
16559        pub const fn soft_rst_mask(&self) -> &SoftRstMask {
16560            &self.soft_rst_mask
16561        }
16562        #[doc = "0x200 - Bus operation config 1"]
16563        #[inline(always)]
16564        pub const fn bus_config1(&self) -> &BusConfig1 {
16565            &self.bus_config1
16566        }
16567        #[doc = "0x204 - Bus operation config 2"]
16568        #[inline(always)]
16569        pub const fn bus_config2(&self) -> &BusConfig2 {
16570            &self.bus_config2
16571        }
16572        #[doc = "0x240 - DMA operation control register"]
16573        #[inline(always)]
16574        pub const fn bus_dma_ctrl(&self) -> &BusDmaCtrl {
16575            &self.bus_dma_ctrl
16576        }
16577        #[doc = "0x244 - DMA memory start address"]
16578        #[inline(always)]
16579        pub const fn bus_dma_mem_saddr(&self) -> &BusDmaMemSaddr {
16580            &self.bus_dma_mem_saddr
16581        }
16582        #[doc = "0x248 - DMA Flash start address"]
16583        #[inline(always)]
16584        pub const fn bus_dma_flash_saddr(&self) -> &BusDmaFlashSaddr {
16585            &self.bus_dma_flash_saddr
16586        }
16587        #[doc = "0x24c - DMA transfer length"]
16588        #[inline(always)]
16589        pub const fn bus_dma_len(&self) -> &BusDmaLen {
16590            &self.bus_dma_len
16591        }
16592        #[doc = "0x250 - DMA AHB burst control"]
16593        #[inline(always)]
16594        pub const fn bus_dma_ahb_ctrl(&self) -> &BusDmaAhbCtrl {
16595            &self.bus_dma_ahb_ctrl
16596        }
16597        #[doc = "0x300 - Command operation config"]
16598        #[inline(always)]
16599        pub const fn cmd_config(&self) -> &CmdConfig {
16600            &self.cmd_config
16601        }
16602        #[doc = "0x308 - Command instruction register"]
16603        #[inline(always)]
16604        pub const fn cmd_ins(&self) -> &CmdIns {
16605            &self.cmd_ins
16606        }
16607        #[doc = "0x30c - Command address register"]
16608        #[inline(always)]
16609        pub const fn cmd_addr(&self) -> &CmdAddr {
16610            &self.cmd_addr
16611        }
16612        #[doc = "0x400 - Command data buffer 0"]
16613        #[inline(always)]
16614        pub const fn cmd_databuf_0(&self) -> &CmdDatabuf0 {
16615            &self.cmd_databuf_0
16616        }
16617        #[doc = "0x404 - Command data buffer 1"]
16618        #[inline(always)]
16619        pub const fn cmd_databuf_1(&self) -> &CmdDatabuf1 {
16620            &self.cmd_databuf_1
16621        }
16622        #[doc = "0x408 - Command data buffer 2"]
16623        #[inline(always)]
16624        pub const fn cmd_databuf_2(&self) -> &CmdDatabuf2 {
16625            &self.cmd_databuf_2
16626        }
16627        #[doc = "0x40c - Command data buffer 3"]
16628        #[inline(always)]
16629        pub const fn cmd_databuf_3(&self) -> &CmdDatabuf3 {
16630            &self.cmd_databuf_3
16631        }
16632        #[doc = "0x410 - Command data buffer 4"]
16633        #[inline(always)]
16634        pub const fn cmd_databuf_4(&self) -> &CmdDatabuf4 {
16635            &self.cmd_databuf_4
16636        }
16637        #[doc = "0x414 - Command data buffer 5"]
16638        #[inline(always)]
16639        pub const fn cmd_databuf_5(&self) -> &CmdDatabuf5 {
16640            &self.cmd_databuf_5
16641        }
16642        #[doc = "0x418 - Command data buffer 6"]
16643        #[inline(always)]
16644        pub const fn cmd_databuf_6(&self) -> &CmdDatabuf6 {
16645            &self.cmd_databuf_6
16646        }
16647        #[doc = "0x41c - Command data buffer 7"]
16648        #[inline(always)]
16649        pub const fn cmd_databuf_7(&self) -> &CmdDatabuf7 {
16650            &self.cmd_databuf_7
16651        }
16652        #[doc = "0x420 - Command data buffer 8"]
16653        #[inline(always)]
16654        pub const fn cmd_databuf_8(&self) -> &CmdDatabuf8 {
16655            &self.cmd_databuf_8
16656        }
16657        #[doc = "0x424 - Command data buffer 9"]
16658        #[inline(always)]
16659        pub const fn cmd_databuf_9(&self) -> &CmdDatabuf9 {
16660            &self.cmd_databuf_9
16661        }
16662        #[doc = "0x428 - Command data buffer 10"]
16663        #[inline(always)]
16664        pub const fn cmd_databuf_10(&self) -> &CmdDatabuf10 {
16665            &self.cmd_databuf_10
16666        }
16667        #[doc = "0x42c - Command data buffer 11"]
16668        #[inline(always)]
16669        pub const fn cmd_databuf_11(&self) -> &CmdDatabuf11 {
16670            &self.cmd_databuf_11
16671        }
16672        #[doc = "0x430 - Command data buffer 12"]
16673        #[inline(always)]
16674        pub const fn cmd_databuf_12(&self) -> &CmdDatabuf12 {
16675            &self.cmd_databuf_12
16676        }
16677        #[doc = "0x434 - Command data buffer 13"]
16678        #[inline(always)]
16679        pub const fn cmd_databuf_13(&self) -> &CmdDatabuf13 {
16680            &self.cmd_databuf_13
16681        }
16682        #[doc = "0x438 - Command data buffer 14"]
16683        #[inline(always)]
16684        pub const fn cmd_databuf_14(&self) -> &CmdDatabuf14 {
16685            &self.cmd_databuf_14
16686        }
16687        #[doc = "0x43c - Command data buffer 15"]
16688        #[inline(always)]
16689        pub const fn cmd_databuf_15(&self) -> &CmdDatabuf15 {
16690            &self.cmd_databuf_15
16691        }
16692        #[doc = "0x1300 - LEA control register"]
16693        #[inline(always)]
16694        pub const fn lea_lp_en(&self) -> &LeaLpEn {
16695            &self.lea_lp_en
16696        }
16697        #[doc = "0x1304 - LEA DFX register"]
16698        #[inline(always)]
16699        pub const fn lea_dfx_info(&self) -> &LeaDfxInfo {
16700            &self.lea_dfx_info
16701        }
16702        #[doc = "0x1600 - LEA IV valid register"]
16703        #[inline(always)]
16704        pub const fn lea_iv_vld(&self) -> &LeaIvVld {
16705            &self.lea_iv_vld
16706        }
16707    }
16708    #[doc = "GLOBAL_CONFIG (rw) register accessor: Global configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`global_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`global_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@global_config`] module"]
16709    #[doc(alias = "GLOBAL_CONFIG")]
16710    pub type GlobalConfig = crate::Reg<global_config::GlobalConfigSpec>;
16711    #[doc = "Global configuration register"]
16712    pub mod global_config {
16713        #[doc = "Register `GLOBAL_CONFIG` reader"]
16714        pub type R = crate::R<GlobalConfigSpec>;
16715        #[doc = "Register `GLOBAL_CONFIG` writer"]
16716        pub type W = crate::W<GlobalConfigSpec>;
16717        #[doc = "SPI mode: 0=Mode0; 1=Mode3\n\nValue on reset: 0"]
16718        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
16719        pub enum Mode {
16720            #[doc = "0: SPI Mode 0 (CPOL=0, CPHA=0)"]
16721            Mode0 = 0,
16722            #[doc = "1: SPI Mode 3 (CPOL=1, CPHA=1)"]
16723            Mode3 = 1,
16724        }
16725        impl From<Mode> for bool {
16726            #[inline(always)]
16727            fn from(variant: Mode) -> Self {
16728                variant as u8 != 0
16729            }
16730        }
16731        #[doc = "Field `mode` reader - SPI mode: 0=Mode0; 1=Mode3"]
16732        pub type ModeR = crate::BitReader<Mode>;
16733        impl ModeR {
16734            #[doc = "Get enumerated values variant"]
16735            #[inline(always)]
16736            pub const fn variant(&self) -> Mode {
16737                match self.bits {
16738                    false => Mode::Mode0,
16739                    true => Mode::Mode3,
16740                }
16741            }
16742            #[doc = "SPI Mode 0 (CPOL=0, CPHA=0)"]
16743            #[inline(always)]
16744            pub fn is_mode0(&self) -> bool {
16745                *self == Mode::Mode0
16746            }
16747            #[doc = "SPI Mode 3 (CPOL=1, CPHA=1)"]
16748            #[inline(always)]
16749            pub fn is_mode3(&self) -> bool {
16750                *self == Mode::Mode3
16751            }
16752        }
16753        #[doc = "Field `mode` writer - SPI mode: 0=Mode0; 1=Mode3"]
16754        pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>;
16755        impl<'a, REG> ModeW<'a, REG>
16756        where
16757            REG: crate::Writable + crate::RegisterSpec,
16758        {
16759            #[doc = "SPI Mode 0 (CPOL=0, CPHA=0)"]
16760            #[inline(always)]
16761            pub fn mode0(self) -> &'a mut crate::W<REG> {
16762                self.variant(Mode::Mode0)
16763            }
16764            #[doc = "SPI Mode 3 (CPOL=1, CPHA=1)"]
16765            #[inline(always)]
16766            pub fn mode3(self) -> &'a mut crate::W<REG> {
16767                self.variant(Mode::Mode3)
16768            }
16769        }
16770        #[doc = "Field `wp_en` reader - Hardware write protect: 0=disabled; 1=enabled"]
16771        pub type WpEnR = crate::BitReader;
16772        #[doc = "Field `wp_en` writer - Hardware write protect: 0=disabled; 1=enabled"]
16773        pub type WpEnW<'a, REG> = crate::BitWriter<'a, REG>;
16774        #[doc = "Address mode: 0=3byte; 1=4byte. NOTE: write has no effect when CMD_CONFIG\\[start\\]=1\n\nValue on reset: 0"]
16775        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
16776        pub enum FlashAddrMode {
16777            #[doc = "0: 3-byte addressing"]
16778            Addr3byte = 0,
16779            #[doc = "1: 4-byte addressing"]
16780            Addr4byte = 1,
16781        }
16782        impl From<FlashAddrMode> for bool {
16783            #[inline(always)]
16784            fn from(variant: FlashAddrMode) -> Self {
16785                variant as u8 != 0
16786            }
16787        }
16788        #[doc = "Field `flash_addr_mode` reader - Address mode: 0=3byte; 1=4byte. NOTE: write has no effect when CMD_CONFIG\\[start\\]=1"]
16789        pub type FlashAddrModeR = crate::BitReader<FlashAddrMode>;
16790        impl FlashAddrModeR {
16791            #[doc = "Get enumerated values variant"]
16792            #[inline(always)]
16793            pub const fn variant(&self) -> FlashAddrMode {
16794                match self.bits {
16795                    false => FlashAddrMode::Addr3byte,
16796                    true => FlashAddrMode::Addr4byte,
16797                }
16798            }
16799            #[doc = "3-byte addressing"]
16800            #[inline(always)]
16801            pub fn is_addr3byte(&self) -> bool {
16802                *self == FlashAddrMode::Addr3byte
16803            }
16804            #[doc = "4-byte addressing"]
16805            #[inline(always)]
16806            pub fn is_addr4byte(&self) -> bool {
16807                *self == FlashAddrMode::Addr4byte
16808            }
16809        }
16810        #[doc = "Field `flash_addr_mode` writer - Address mode: 0=3byte; 1=4byte. NOTE: write has no effect when CMD_CONFIG\\[start\\]=1"]
16811        pub type FlashAddrModeW<'a, REG> = crate::BitWriter<'a, REG, FlashAddrMode>;
16812        impl<'a, REG> FlashAddrModeW<'a, REG>
16813        where
16814            REG: crate::Writable + crate::RegisterSpec,
16815        {
16816            #[doc = "3-byte addressing"]
16817            #[inline(always)]
16818            pub fn addr3byte(self) -> &'a mut crate::W<REG> {
16819                self.variant(FlashAddrMode::Addr3byte)
16820            }
16821            #[doc = "4-byte addressing"]
16822            #[inline(always)]
16823            pub fn addr4byte(self) -> &'a mut crate::W<REG> {
16824                self.variant(FlashAddrMode::Addr4byte)
16825            }
16826        }
16827        #[doc = "Field `rd_delay` reader - SPI read data delay: 000=0.5~1clk; 001=1~1.5clk; etc."]
16828        pub type RdDelayR = crate::FieldReader;
16829        #[doc = "Field `rd_delay` writer - SPI read data delay: 000=0.5~1clk; 001=1~1.5clk; etc."]
16830        pub type RdDelayW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
16831        impl R {
16832            #[doc = "Bit 0 - SPI mode: 0=Mode0; 1=Mode3"]
16833            #[inline(always)]
16834            pub fn mode(&self) -> ModeR {
16835                ModeR::new((self.bits & 1) != 0)
16836            }
16837            #[doc = "Bit 1 - Hardware write protect: 0=disabled; 1=enabled"]
16838            #[inline(always)]
16839            pub fn wp_en(&self) -> WpEnR {
16840                WpEnR::new(((self.bits >> 1) & 1) != 0)
16841            }
16842            #[doc = "Bit 2 - Address mode: 0=3byte; 1=4byte. NOTE: write has no effect when CMD_CONFIG\\[start\\]=1"]
16843            #[inline(always)]
16844            pub fn flash_addr_mode(&self) -> FlashAddrModeR {
16845                FlashAddrModeR::new(((self.bits >> 2) & 1) != 0)
16846            }
16847            #[doc = "Bits 3:5 - SPI read data delay: 000=0.5~1clk; 001=1~1.5clk; etc."]
16848            #[inline(always)]
16849            pub fn rd_delay(&self) -> RdDelayR {
16850                RdDelayR::new(((self.bits >> 3) & 7) as u8)
16851            }
16852        }
16853        impl W {
16854            #[doc = "Bit 0 - SPI mode: 0=Mode0; 1=Mode3"]
16855            #[inline(always)]
16856            pub fn mode(&mut self) -> ModeW<'_, GlobalConfigSpec> {
16857                ModeW::new(self, 0)
16858            }
16859            #[doc = "Bit 1 - Hardware write protect: 0=disabled; 1=enabled"]
16860            #[inline(always)]
16861            pub fn wp_en(&mut self) -> WpEnW<'_, GlobalConfigSpec> {
16862                WpEnW::new(self, 1)
16863            }
16864            #[doc = "Bit 2 - Address mode: 0=3byte; 1=4byte. NOTE: write has no effect when CMD_CONFIG\\[start\\]=1"]
16865            #[inline(always)]
16866            pub fn flash_addr_mode(&mut self) -> FlashAddrModeW<'_, GlobalConfigSpec> {
16867                FlashAddrModeW::new(self, 2)
16868            }
16869            #[doc = "Bits 3:5 - SPI read data delay: 000=0.5~1clk; 001=1~1.5clk; etc."]
16870            #[inline(always)]
16871            pub fn rd_delay(&mut self) -> RdDelayW<'_, GlobalConfigSpec> {
16872                RdDelayW::new(self, 3)
16873            }
16874        }
16875        #[doc = "Global configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`global_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`global_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16876        pub struct GlobalConfigSpec;
16877        impl crate::RegisterSpec for GlobalConfigSpec {
16878            type Ux = u32;
16879        }
16880        #[doc = "`read()` method returns [`global_config::R`](R) reader structure"]
16881        impl crate::Readable for GlobalConfigSpec {}
16882        #[doc = "`write(|w| ..)` method takes [`global_config::W`](W) writer structure"]
16883        impl crate::Writable for GlobalConfigSpec {
16884            type Safety = crate::Unsafe;
16885        }
16886        #[doc = "`reset()` method sets GLOBAL_CONFIG to value 0"]
16887        impl crate::Resettable for GlobalConfigSpec {}
16888    }
16889    #[doc = "TIMING (rw) register accessor: Timing configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`timing::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timing::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timing`] module"]
16890    #[doc(alias = "TIMING")]
16891    pub type Timing = crate::Reg<timing::TimingSpec>;
16892    #[doc = "Timing configuration register"]
16893    pub mod timing {
16894        #[doc = "Register `TIMING` reader"]
16895        pub type R = crate::R<TimingSpec>;
16896        #[doc = "Register `TIMING` writer"]
16897        pub type W = crate::W<TimingSpec>;
16898        #[doc = "Field `tshsl` reader - Inter-operation delay: (n+2) clock cycles"]
16899        pub type TshslR = crate::FieldReader;
16900        #[doc = "Field `tshsl` writer - Inter-operation delay: (n+2) clock cycles"]
16901        pub type TshslW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
16902        #[doc = "Field `tcss` reader - CS setup time: (n+1) clock cycles"]
16903        pub type TcssR = crate::FieldReader;
16904        #[doc = "Field `tcss` writer - CS setup time: (n+1) clock cycles"]
16905        pub type TcssW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
16906        #[doc = "Field `tcsh` reader - CS hold time: (n+1) clock cycles"]
16907        pub type TcshR = crate::FieldReader;
16908        #[doc = "Field `tcsh` writer - CS hold time: (n+1) clock cycles"]
16909        pub type TcshW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
16910        impl R {
16911            #[doc = "Bits 0:3 - Inter-operation delay: (n+2) clock cycles"]
16912            #[inline(always)]
16913            pub fn tshsl(&self) -> TshslR {
16914                TshslR::new((self.bits & 0x0f) as u8)
16915            }
16916            #[doc = "Bits 8:10 - CS setup time: (n+1) clock cycles"]
16917            #[inline(always)]
16918            pub fn tcss(&self) -> TcssR {
16919                TcssR::new(((self.bits >> 8) & 7) as u8)
16920            }
16921            #[doc = "Bits 12:14 - CS hold time: (n+1) clock cycles"]
16922            #[inline(always)]
16923            pub fn tcsh(&self) -> TcshR {
16924                TcshR::new(((self.bits >> 12) & 7) as u8)
16925            }
16926        }
16927        impl W {
16928            #[doc = "Bits 0:3 - Inter-operation delay: (n+2) clock cycles"]
16929            #[inline(always)]
16930            pub fn tshsl(&mut self) -> TshslW<'_, TimingSpec> {
16931                TshslW::new(self, 0)
16932            }
16933            #[doc = "Bits 8:10 - CS setup time: (n+1) clock cycles"]
16934            #[inline(always)]
16935            pub fn tcss(&mut self) -> TcssW<'_, TimingSpec> {
16936                TcssW::new(self, 8)
16937            }
16938            #[doc = "Bits 12:14 - CS hold time: (n+1) clock cycles"]
16939            #[inline(always)]
16940            pub fn tcsh(&mut self) -> TcshW<'_, TimingSpec> {
16941                TcshW::new(self, 12)
16942            }
16943        }
16944        #[doc = "Timing configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`timing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16945        pub struct TimingSpec;
16946        impl crate::RegisterSpec for TimingSpec {
16947            type Ux = u32;
16948        }
16949        #[doc = "`read()` method returns [`timing::R`](R) reader structure"]
16950        impl crate::Readable for TimingSpec {}
16951        #[doc = "`write(|w| ..)` method takes [`timing::W`](W) writer structure"]
16952        impl crate::Writable for TimingSpec {
16953            type Safety = crate::Unsafe;
16954        }
16955        #[doc = "`reset()` method sets TIMING to value 0x660f"]
16956        impl crate::Resettable for TimingSpec {
16957            const RESET_VALUE: u32 = 0x660f;
16958        }
16959    }
16960    #[doc = "INT_RAW_STATUS (rw) register accessor: Interrupt raw status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw_status`] module"]
16961    #[doc(alias = "INT_RAW_STATUS")]
16962    pub type IntRawStatus = crate::Reg<int_raw_status::IntRawStatusSpec>;
16963    #[doc = "Interrupt raw status register"]
16964    pub mod int_raw_status {
16965        #[doc = "Register `INT_RAW_STATUS` reader"]
16966        pub type R = crate::R<IntRawStatusSpec>;
16967        #[doc = "Register `INT_RAW_STATUS` writer"]
16968        pub type W = crate::W<IntRawStatusSpec>;
16969        #[doc = "Field `cmd_op_end_raw_status` reader - Command operation end raw status"]
16970        pub type CmdOpEndRawStatusR = crate::BitReader;
16971        #[doc = "Field `dma_done_int_raw_status` reader - DMA done raw status"]
16972        pub type DmaDoneIntRawStatusR = crate::BitReader;
16973        impl R {
16974            #[doc = "Bit 0 - Command operation end raw status"]
16975            #[inline(always)]
16976            pub fn cmd_op_end_raw_status(&self) -> CmdOpEndRawStatusR {
16977                CmdOpEndRawStatusR::new((self.bits & 1) != 0)
16978            }
16979            #[doc = "Bit 1 - DMA done raw status"]
16980            #[inline(always)]
16981            pub fn dma_done_int_raw_status(&self) -> DmaDoneIntRawStatusR {
16982                DmaDoneIntRawStatusR::new(((self.bits >> 1) & 1) != 0)
16983            }
16984        }
16985        impl W {}
16986        #[doc = "Interrupt raw status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16987        pub struct IntRawStatusSpec;
16988        impl crate::RegisterSpec for IntRawStatusSpec {
16989            type Ux = u32;
16990        }
16991        #[doc = "`read()` method returns [`int_raw_status::R`](R) reader structure"]
16992        impl crate::Readable for IntRawStatusSpec {}
16993        #[doc = "`write(|w| ..)` method takes [`int_raw_status::W`](W) writer structure"]
16994        impl crate::Writable for IntRawStatusSpec {
16995            type Safety = crate::Unsafe;
16996        }
16997        #[doc = "`reset()` method sets INT_RAW_STATUS to value 0"]
16998        impl crate::Resettable for IntRawStatusSpec {}
16999    }
17000    #[doc = "INT_STATUS (rw) register accessor: Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`] module"]
17001    #[doc(alias = "INT_STATUS")]
17002    pub type IntStatus = crate::Reg<int_status::IntStatusSpec>;
17003    #[doc = "Interrupt status register (masked)"]
17004    pub mod int_status {
17005        #[doc = "Register `INT_STATUS` reader"]
17006        pub type R = crate::R<IntStatusSpec>;
17007        #[doc = "Register `INT_STATUS` writer"]
17008        pub type W = crate::W<IntStatusSpec>;
17009        #[doc = "Field `cmd_op_end_status` reader - Command operation end status"]
17010        pub type CmdOpEndStatusR = crate::BitReader;
17011        #[doc = "Field `dma_done_int_status` reader - DMA done status"]
17012        pub type DmaDoneIntStatusR = crate::BitReader;
17013        impl R {
17014            #[doc = "Bit 0 - Command operation end status"]
17015            #[inline(always)]
17016            pub fn cmd_op_end_status(&self) -> CmdOpEndStatusR {
17017                CmdOpEndStatusR::new((self.bits & 1) != 0)
17018            }
17019            #[doc = "Bit 1 - DMA done status"]
17020            #[inline(always)]
17021            pub fn dma_done_int_status(&self) -> DmaDoneIntStatusR {
17022                DmaDoneIntStatusR::new(((self.bits >> 1) & 1) != 0)
17023            }
17024        }
17025        impl W {}
17026        #[doc = "Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17027        pub struct IntStatusSpec;
17028        impl crate::RegisterSpec for IntStatusSpec {
17029            type Ux = u32;
17030        }
17031        #[doc = "`read()` method returns [`int_status::R`](R) reader structure"]
17032        impl crate::Readable for IntStatusSpec {}
17033        #[doc = "`write(|w| ..)` method takes [`int_status::W`](W) writer structure"]
17034        impl crate::Writable for IntStatusSpec {
17035            type Safety = crate::Unsafe;
17036        }
17037        #[doc = "`reset()` method sets INT_STATUS to value 0"]
17038        impl crate::Resettable for IntStatusSpec {}
17039    }
17040    #[doc = "INT_MASK (rw) register accessor: Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_mask`] module"]
17041    #[doc(alias = "INT_MASK")]
17042    pub type IntMask = crate::Reg<int_mask::IntMaskSpec>;
17043    #[doc = "Interrupt mask register"]
17044    pub mod int_mask {
17045        #[doc = "Register `INT_MASK` reader"]
17046        pub type R = crate::R<IntMaskSpec>;
17047        #[doc = "Register `INT_MASK` writer"]
17048        pub type W = crate::W<IntMaskSpec>;
17049        #[doc = "Field `cmd_op_end_int_mask` reader - Command end mask: 0=masked; 1=unmasked"]
17050        pub type CmdOpEndIntMaskR = crate::BitReader;
17051        #[doc = "Field `cmd_op_end_int_mask` writer - Command end mask: 0=masked; 1=unmasked"]
17052        pub type CmdOpEndIntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
17053        #[doc = "Field `dma_done_int_mask` reader - DMA done mask"]
17054        pub type DmaDoneIntMaskR = crate::BitReader;
17055        #[doc = "Field `dma_done_int_mask` writer - DMA done mask"]
17056        pub type DmaDoneIntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
17057        impl R {
17058            #[doc = "Bit 0 - Command end mask: 0=masked; 1=unmasked"]
17059            #[inline(always)]
17060            pub fn cmd_op_end_int_mask(&self) -> CmdOpEndIntMaskR {
17061                CmdOpEndIntMaskR::new((self.bits & 1) != 0)
17062            }
17063            #[doc = "Bit 1 - DMA done mask"]
17064            #[inline(always)]
17065            pub fn dma_done_int_mask(&self) -> DmaDoneIntMaskR {
17066                DmaDoneIntMaskR::new(((self.bits >> 1) & 1) != 0)
17067            }
17068        }
17069        impl W {
17070            #[doc = "Bit 0 - Command end mask: 0=masked; 1=unmasked"]
17071            #[inline(always)]
17072            pub fn cmd_op_end_int_mask(&mut self) -> CmdOpEndIntMaskW<'_, IntMaskSpec> {
17073                CmdOpEndIntMaskW::new(self, 0)
17074            }
17075            #[doc = "Bit 1 - DMA done mask"]
17076            #[inline(always)]
17077            pub fn dma_done_int_mask(&mut self) -> DmaDoneIntMaskW<'_, IntMaskSpec> {
17078                DmaDoneIntMaskW::new(self, 1)
17079            }
17080        }
17081        #[doc = "Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17082        pub struct IntMaskSpec;
17083        impl crate::RegisterSpec for IntMaskSpec {
17084            type Ux = u32;
17085        }
17086        #[doc = "`read()` method returns [`int_mask::R`](R) reader structure"]
17087        impl crate::Readable for IntMaskSpec {}
17088        #[doc = "`write(|w| ..)` method takes [`int_mask::W`](W) writer structure"]
17089        impl crate::Writable for IntMaskSpec {
17090            type Safety = crate::Unsafe;
17091        }
17092        #[doc = "`reset()` method sets INT_MASK to value 0"]
17093        impl crate::Resettable for IntMaskSpec {}
17094    }
17095    #[doc = "INT_CLEAR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clear`] module"]
17096    #[doc(alias = "INT_CLEAR")]
17097    pub type IntClear = crate::Reg<int_clear::IntClearSpec>;
17098    #[doc = "Interrupt clear register"]
17099    pub mod int_clear {
17100        #[doc = "Register `INT_CLEAR` reader"]
17101        pub type R = crate::R<IntClearSpec>;
17102        #[doc = "Register `INT_CLEAR` writer"]
17103        pub type W = crate::W<IntClearSpec>;
17104        #[doc = "Field `cmd_op_end_int_clr` writer - Command end interrupt clear (self-clearing)"]
17105        pub type CmdOpEndIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
17106        #[doc = "Field `dma_done_int_clr` writer - DMA done interrupt clear (self-clearing)"]
17107        pub type DmaDoneIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
17108        impl W {
17109            #[doc = "Bit 0 - Command end interrupt clear (self-clearing)"]
17110            #[inline(always)]
17111            pub fn cmd_op_end_int_clr(&mut self) -> CmdOpEndIntClrW<'_, IntClearSpec> {
17112                CmdOpEndIntClrW::new(self, 0)
17113            }
17114            #[doc = "Bit 1 - DMA done interrupt clear (self-clearing)"]
17115            #[inline(always)]
17116            pub fn dma_done_int_clr(&mut self) -> DmaDoneIntClrW<'_, IntClearSpec> {
17117                DmaDoneIntClrW::new(self, 1)
17118            }
17119        }
17120        #[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17121        pub struct IntClearSpec;
17122        impl crate::RegisterSpec for IntClearSpec {
17123            type Ux = u32;
17124        }
17125        #[doc = "`read()` method returns [`int_clear::R`](R) reader structure"]
17126        impl crate::Readable for IntClearSpec {}
17127        #[doc = "`write(|w| ..)` method takes [`int_clear::W`](W) writer structure"]
17128        impl crate::Writable for IntClearSpec {
17129            type Safety = crate::Unsafe;
17130        }
17131        #[doc = "`reset()` method sets INT_CLEAR to value 0"]
17132        impl crate::Resettable for IntClearSpec {}
17133    }
17134    #[doc = "SOFT_RST_MASK (rw) register accessor: Soft reset mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_rst_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_rst_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst_mask`] module"]
17135    #[doc(alias = "SOFT_RST_MASK")]
17136    pub type SoftRstMask = crate::Reg<soft_rst_mask::SoftRstMaskSpec>;
17137    #[doc = "Soft reset mask register"]
17138    pub mod soft_rst_mask {
17139        #[doc = "Register `SOFT_RST_MASK` reader"]
17140        pub type R = crate::R<SoftRstMaskSpec>;
17141        #[doc = "Register `SOFT_RST_MASK` writer"]
17142        pub type W = crate::W<SoftRstMaskSpec>;
17143        #[doc = "Field `sfc_bus_soft_rst_mask` reader - SFC bus soft reset mask: 0=reset active; 1=reset masked"]
17144        pub type SfcBusSoftRstMaskR = crate::BitReader;
17145        #[doc = "Field `sfc_bus_soft_rst_mask` writer - SFC bus soft reset mask: 0=reset active; 1=reset masked"]
17146        pub type SfcBusSoftRstMaskW<'a, REG> = crate::BitWriter<'a, REG>;
17147        impl R {
17148            #[doc = "Bit 0 - SFC bus soft reset mask: 0=reset active; 1=reset masked"]
17149            #[inline(always)]
17150            pub fn sfc_bus_soft_rst_mask(&self) -> SfcBusSoftRstMaskR {
17151                SfcBusSoftRstMaskR::new((self.bits & 1) != 0)
17152            }
17153        }
17154        impl W {
17155            #[doc = "Bit 0 - SFC bus soft reset mask: 0=reset active; 1=reset masked"]
17156            #[inline(always)]
17157            pub fn sfc_bus_soft_rst_mask(&mut self) -> SfcBusSoftRstMaskW<'_, SoftRstMaskSpec> {
17158                SfcBusSoftRstMaskW::new(self, 0)
17159            }
17160        }
17161        #[doc = "Soft reset mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_rst_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_rst_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17162        pub struct SoftRstMaskSpec;
17163        impl crate::RegisterSpec for SoftRstMaskSpec {
17164            type Ux = u32;
17165        }
17166        #[doc = "`read()` method returns [`soft_rst_mask::R`](R) reader structure"]
17167        impl crate::Readable for SoftRstMaskSpec {}
17168        #[doc = "`write(|w| ..)` method takes [`soft_rst_mask::W`](W) writer structure"]
17169        impl crate::Writable for SoftRstMaskSpec {
17170            type Safety = crate::Unsafe;
17171        }
17172        #[doc = "`reset()` method sets SOFT_RST_MASK to value 0x01"]
17173        impl crate::Resettable for SoftRstMaskSpec {
17174            const RESET_VALUE: u32 = 0x01;
17175        }
17176    }
17177    #[doc = "BUS_CONFIG1 (rw) register accessor: Bus operation config 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_config1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_config1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_config1`] module"]
17178    #[doc(alias = "BUS_CONFIG1")]
17179    pub type BusConfig1 = crate::Reg<bus_config1::BusConfig1Spec>;
17180    #[doc = "Bus operation config 1"]
17181    pub mod bus_config1 {
17182        #[doc = "Register `BUS_CONFIG1` reader"]
17183        pub type R = crate::R<BusConfig1Spec>;
17184        #[doc = "Register `BUS_CONFIG1` writer"]
17185        pub type W = crate::W<BusConfig1Spec>;
17186        #[doc = "Field `rd_mem_if_type` reader - Read SPI interface type: 000=Standard; 001=Dual I/O; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
17187        pub type RdMemIfTypeR = crate::FieldReader;
17188        #[doc = "Field `rd_mem_if_type` writer - Read SPI interface type: 000=Standard; 001=Dual I/O; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
17189        pub type RdMemIfTypeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17190        #[doc = "Field `rd_dummy_bytes` reader - Read dummy bytes: 000=0; 001=1; etc."]
17191        pub type RdDummyBytesR = crate::FieldReader;
17192        #[doc = "Field `rd_dummy_bytes` writer - Read dummy bytes: 000=0; 001=1; etc."]
17193        pub type RdDummyBytesW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17194        #[doc = "Field `rd_prefetch_cnt` reader - Read prefetch count: 00=none; 01=1clk; 10=2clk; 11=3clk"]
17195        pub type RdPrefetchCntR = crate::FieldReader;
17196        #[doc = "Field `rd_prefetch_cnt` writer - Read prefetch count: 00=none; 01=1clk; 10=2clk; 11=3clk"]
17197        pub type RdPrefetchCntW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17198        #[doc = "Field `rd_ins` reader - Read instruction code"]
17199        pub type RdInsR = crate::FieldReader;
17200        #[doc = "Field `rd_ins` writer - Read instruction code"]
17201        pub type RdInsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17202        #[doc = "Field `wr_mem_if_type` reader - Write SPI interface type"]
17203        pub type WrMemIfTypeR = crate::FieldReader;
17204        #[doc = "Field `wr_mem_if_type` writer - Write SPI interface type"]
17205        pub type WrMemIfTypeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17206        #[doc = "Field `wr_dummy_bytes` reader - Write dummy bytes"]
17207        pub type WrDummyBytesR = crate::FieldReader;
17208        #[doc = "Field `wr_dummy_bytes` writer - Write dummy bytes"]
17209        pub type WrDummyBytesW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17210        #[doc = "Field `wr_ins` reader - Write instruction code"]
17211        pub type WrInsR = crate::FieldReader;
17212        #[doc = "Field `wr_ins` writer - Write instruction code"]
17213        pub type WrInsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17214        #[doc = "Field `wr_enable` reader - Bus write enable"]
17215        pub type WrEnableR = crate::BitReader;
17216        #[doc = "Field `wr_enable` writer - Bus write enable"]
17217        pub type WrEnableW<'a, REG> = crate::BitWriter<'a, REG>;
17218        #[doc = "Field `rd_enable` reader - Bus read enable"]
17219        pub type RdEnableR = crate::BitReader;
17220        #[doc = "Field `rd_enable` writer - Bus read enable"]
17221        pub type RdEnableW<'a, REG> = crate::BitWriter<'a, REG>;
17222        impl R {
17223            #[doc = "Bits 0:2 - Read SPI interface type: 000=Standard; 001=Dual I/O; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
17224            #[inline(always)]
17225            pub fn rd_mem_if_type(&self) -> RdMemIfTypeR {
17226                RdMemIfTypeR::new((self.bits & 7) as u8)
17227            }
17228            #[doc = "Bits 3:5 - Read dummy bytes: 000=0; 001=1; etc."]
17229            #[inline(always)]
17230            pub fn rd_dummy_bytes(&self) -> RdDummyBytesR {
17231                RdDummyBytesR::new(((self.bits >> 3) & 7) as u8)
17232            }
17233            #[doc = "Bits 6:7 - Read prefetch count: 00=none; 01=1clk; 10=2clk; 11=3clk"]
17234            #[inline(always)]
17235            pub fn rd_prefetch_cnt(&self) -> RdPrefetchCntR {
17236                RdPrefetchCntR::new(((self.bits >> 6) & 3) as u8)
17237            }
17238            #[doc = "Bits 8:15 - Read instruction code"]
17239            #[inline(always)]
17240            pub fn rd_ins(&self) -> RdInsR {
17241                RdInsR::new(((self.bits >> 8) & 0xff) as u8)
17242            }
17243            #[doc = "Bits 16:18 - Write SPI interface type"]
17244            #[inline(always)]
17245            pub fn wr_mem_if_type(&self) -> WrMemIfTypeR {
17246                WrMemIfTypeR::new(((self.bits >> 16) & 7) as u8)
17247            }
17248            #[doc = "Bits 19:21 - Write dummy bytes"]
17249            #[inline(always)]
17250            pub fn wr_dummy_bytes(&self) -> WrDummyBytesR {
17251                WrDummyBytesR::new(((self.bits >> 19) & 7) as u8)
17252            }
17253            #[doc = "Bits 22:29 - Write instruction code"]
17254            #[inline(always)]
17255            pub fn wr_ins(&self) -> WrInsR {
17256                WrInsR::new(((self.bits >> 22) & 0xff) as u8)
17257            }
17258            #[doc = "Bit 30 - Bus write enable"]
17259            #[inline(always)]
17260            pub fn wr_enable(&self) -> WrEnableR {
17261                WrEnableR::new(((self.bits >> 30) & 1) != 0)
17262            }
17263            #[doc = "Bit 31 - Bus read enable"]
17264            #[inline(always)]
17265            pub fn rd_enable(&self) -> RdEnableR {
17266                RdEnableR::new(((self.bits >> 31) & 1) != 0)
17267            }
17268        }
17269        impl W {
17270            #[doc = "Bits 0:2 - Read SPI interface type: 000=Standard; 001=Dual I/O; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
17271            #[inline(always)]
17272            pub fn rd_mem_if_type(&mut self) -> RdMemIfTypeW<'_, BusConfig1Spec> {
17273                RdMemIfTypeW::new(self, 0)
17274            }
17275            #[doc = "Bits 3:5 - Read dummy bytes: 000=0; 001=1; etc."]
17276            #[inline(always)]
17277            pub fn rd_dummy_bytes(&mut self) -> RdDummyBytesW<'_, BusConfig1Spec> {
17278                RdDummyBytesW::new(self, 3)
17279            }
17280            #[doc = "Bits 6:7 - Read prefetch count: 00=none; 01=1clk; 10=2clk; 11=3clk"]
17281            #[inline(always)]
17282            pub fn rd_prefetch_cnt(&mut self) -> RdPrefetchCntW<'_, BusConfig1Spec> {
17283                RdPrefetchCntW::new(self, 6)
17284            }
17285            #[doc = "Bits 8:15 - Read instruction code"]
17286            #[inline(always)]
17287            pub fn rd_ins(&mut self) -> RdInsW<'_, BusConfig1Spec> {
17288                RdInsW::new(self, 8)
17289            }
17290            #[doc = "Bits 16:18 - Write SPI interface type"]
17291            #[inline(always)]
17292            pub fn wr_mem_if_type(&mut self) -> WrMemIfTypeW<'_, BusConfig1Spec> {
17293                WrMemIfTypeW::new(self, 16)
17294            }
17295            #[doc = "Bits 19:21 - Write dummy bytes"]
17296            #[inline(always)]
17297            pub fn wr_dummy_bytes(&mut self) -> WrDummyBytesW<'_, BusConfig1Spec> {
17298                WrDummyBytesW::new(self, 19)
17299            }
17300            #[doc = "Bits 22:29 - Write instruction code"]
17301            #[inline(always)]
17302            pub fn wr_ins(&mut self) -> WrInsW<'_, BusConfig1Spec> {
17303                WrInsW::new(self, 22)
17304            }
17305            #[doc = "Bit 30 - Bus write enable"]
17306            #[inline(always)]
17307            pub fn wr_enable(&mut self) -> WrEnableW<'_, BusConfig1Spec> {
17308                WrEnableW::new(self, 30)
17309            }
17310            #[doc = "Bit 31 - Bus read enable"]
17311            #[inline(always)]
17312            pub fn rd_enable(&mut self) -> RdEnableW<'_, BusConfig1Spec> {
17313                RdEnableW::new(self, 31)
17314            }
17315        }
17316        #[doc = "Bus operation config 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_config1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_config1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17317        pub struct BusConfig1Spec;
17318        impl crate::RegisterSpec for BusConfig1Spec {
17319            type Ux = u32;
17320        }
17321        #[doc = "`read()` method returns [`bus_config1::R`](R) reader structure"]
17322        impl crate::Readable for BusConfig1Spec {}
17323        #[doc = "`write(|w| ..)` method takes [`bus_config1::W`](W) writer structure"]
17324        impl crate::Writable for BusConfig1Spec {
17325            type Safety = crate::Unsafe;
17326        }
17327        #[doc = "`reset()` method sets BUS_CONFIG1 to value 0x8080_0300"]
17328        impl crate::Resettable for BusConfig1Spec {
17329            const RESET_VALUE: u32 = 0x8080_0300;
17330        }
17331    }
17332    #[doc = "BUS_CONFIG2 (rw) register accessor: Bus operation config 2\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_config2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_config2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_config2`] module"]
17333    #[doc(alias = "BUS_CONFIG2")]
17334    pub type BusConfig2 = crate::Reg<bus_config2::BusConfig2Spec>;
17335    #[doc = "Bus operation config 2"]
17336    pub mod bus_config2 {
17337        #[doc = "Register `BUS_CONFIG2` reader"]
17338        pub type R = crate::R<BusConfig2Spec>;
17339        #[doc = "Register `BUS_CONFIG2` writer"]
17340        pub type W = crate::W<BusConfig2Spec>;
17341        #[doc = "Field `wip_locate` reader - WIP bit position in Flash status register: 000=bit0; etc."]
17342        pub type WipLocateR = crate::FieldReader;
17343        #[doc = "Field `wip_locate` writer - WIP bit position in Flash status register: 000=bit0; etc."]
17344        pub type WipLocateW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17345        impl R {
17346            #[doc = "Bits 0:2 - WIP bit position in Flash status register: 000=bit0; etc."]
17347            #[inline(always)]
17348            pub fn wip_locate(&self) -> WipLocateR {
17349                WipLocateR::new((self.bits & 7) as u8)
17350            }
17351        }
17352        impl W {
17353            #[doc = "Bits 0:2 - WIP bit position in Flash status register: 000=bit0; etc."]
17354            #[inline(always)]
17355            pub fn wip_locate(&mut self) -> WipLocateW<'_, BusConfig2Spec> {
17356                WipLocateW::new(self, 0)
17357            }
17358        }
17359        #[doc = "Bus operation config 2\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_config2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_config2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17360        pub struct BusConfig2Spec;
17361        impl crate::RegisterSpec for BusConfig2Spec {
17362            type Ux = u32;
17363        }
17364        #[doc = "`read()` method returns [`bus_config2::R`](R) reader structure"]
17365        impl crate::Readable for BusConfig2Spec {}
17366        #[doc = "`write(|w| ..)` method takes [`bus_config2::W`](W) writer structure"]
17367        impl crate::Writable for BusConfig2Spec {
17368            type Safety = crate::Unsafe;
17369        }
17370        #[doc = "`reset()` method sets BUS_CONFIG2 to value 0"]
17371        impl crate::Resettable for BusConfig2Spec {}
17372    }
17373    #[doc = "BUS_DMA_CTRL (rw) register accessor: DMA operation control register\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_dma_ctrl`] module"]
17374    #[doc(alias = "BUS_DMA_CTRL")]
17375    pub type BusDmaCtrl = crate::Reg<bus_dma_ctrl::BusDmaCtrlSpec>;
17376    #[doc = "DMA operation control register"]
17377    pub mod bus_dma_ctrl {
17378        #[doc = "Register `BUS_DMA_CTRL` reader"]
17379        pub type R = crate::R<BusDmaCtrlSpec>;
17380        #[doc = "Register `BUS_DMA_CTRL` writer"]
17381        pub type W = crate::W<BusDmaCtrlSpec>;
17382        #[doc = "Field `dma_start` reader - DMA transfer enable (auto-clears)"]
17383        pub type DmaStartR = crate::BitReader;
17384        #[doc = "Field `dma_start` writer - DMA transfer enable (auto-clears)"]
17385        pub type DmaStartW<'a, REG> = crate::BitWriter<'a, REG>;
17386        #[doc = "Field `dma_rw` reader - DMA direction: 0=write; 1=read"]
17387        pub type DmaRwR = crate::BitReader;
17388        #[doc = "Field `dma_rw` writer - DMA direction: 0=write; 1=read"]
17389        pub type DmaRwW<'a, REG> = crate::BitWriter<'a, REG>;
17390        #[doc = "Field `dma_sel_cs` reader - DMA chip select: 0=CS0; 1=CS1"]
17391        pub type DmaSelCsR = crate::BitReader;
17392        #[doc = "Field `dma_sel_cs` writer - DMA chip select: 0=CS0; 1=CS1"]
17393        pub type DmaSelCsW<'a, REG> = crate::BitWriter<'a, REG>;
17394        impl R {
17395            #[doc = "Bit 0 - DMA transfer enable (auto-clears)"]
17396            #[inline(always)]
17397            pub fn dma_start(&self) -> DmaStartR {
17398                DmaStartR::new((self.bits & 1) != 0)
17399            }
17400            #[doc = "Bit 1 - DMA direction: 0=write; 1=read"]
17401            #[inline(always)]
17402            pub fn dma_rw(&self) -> DmaRwR {
17403                DmaRwR::new(((self.bits >> 1) & 1) != 0)
17404            }
17405            #[doc = "Bit 4 - DMA chip select: 0=CS0; 1=CS1"]
17406            #[inline(always)]
17407            pub fn dma_sel_cs(&self) -> DmaSelCsR {
17408                DmaSelCsR::new(((self.bits >> 4) & 1) != 0)
17409            }
17410        }
17411        impl W {
17412            #[doc = "Bit 0 - DMA transfer enable (auto-clears)"]
17413            #[inline(always)]
17414            pub fn dma_start(&mut self) -> DmaStartW<'_, BusDmaCtrlSpec> {
17415                DmaStartW::new(self, 0)
17416            }
17417            #[doc = "Bit 1 - DMA direction: 0=write; 1=read"]
17418            #[inline(always)]
17419            pub fn dma_rw(&mut self) -> DmaRwW<'_, BusDmaCtrlSpec> {
17420                DmaRwW::new(self, 1)
17421            }
17422            #[doc = "Bit 4 - DMA chip select: 0=CS0; 1=CS1"]
17423            #[inline(always)]
17424            pub fn dma_sel_cs(&mut self) -> DmaSelCsW<'_, BusDmaCtrlSpec> {
17425                DmaSelCsW::new(self, 4)
17426            }
17427        }
17428        #[doc = "DMA operation control register\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17429        pub struct BusDmaCtrlSpec;
17430        impl crate::RegisterSpec for BusDmaCtrlSpec {
17431            type Ux = u32;
17432        }
17433        #[doc = "`read()` method returns [`bus_dma_ctrl::R`](R) reader structure"]
17434        impl crate::Readable for BusDmaCtrlSpec {}
17435        #[doc = "`write(|w| ..)` method takes [`bus_dma_ctrl::W`](W) writer structure"]
17436        impl crate::Writable for BusDmaCtrlSpec {
17437            type Safety = crate::Unsafe;
17438        }
17439        #[doc = "`reset()` method sets BUS_DMA_CTRL to value 0"]
17440        impl crate::Resettable for BusDmaCtrlSpec {}
17441    }
17442    #[doc = "BUS_DMA_MEM_SADDR (rw) register accessor: DMA memory start address\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_mem_saddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_mem_saddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_dma_mem_saddr`] module"]
17443    #[doc(alias = "BUS_DMA_MEM_SADDR")]
17444    pub type BusDmaMemSaddr = crate::Reg<bus_dma_mem_saddr::BusDmaMemSaddrSpec>;
17445    #[doc = "DMA memory start address"]
17446    pub mod bus_dma_mem_saddr {
17447        #[doc = "Register `BUS_DMA_MEM_SADDR` reader"]
17448        pub type R = crate::R<BusDmaMemSaddrSpec>;
17449        #[doc = "Register `BUS_DMA_MEM_SADDR` writer"]
17450        pub type W = crate::W<BusDmaMemSaddrSpec>;
17451        #[doc = "Field `dma_mem_saddr` reader - DMA memory start address (0x00100000~0x00BFFFFF)"]
17452        pub type DmaMemSaddrR = crate::FieldReader<u32>;
17453        #[doc = "Field `dma_mem_saddr` writer - DMA memory start address (0x00100000~0x00BFFFFF)"]
17454        pub type DmaMemSaddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
17455        impl R {
17456            #[doc = "Bits 0:31 - DMA memory start address (0x00100000~0x00BFFFFF)"]
17457            #[inline(always)]
17458            pub fn dma_mem_saddr(&self) -> DmaMemSaddrR {
17459                DmaMemSaddrR::new(self.bits)
17460            }
17461        }
17462        impl W {
17463            #[doc = "Bits 0:31 - DMA memory start address (0x00100000~0x00BFFFFF)"]
17464            #[inline(always)]
17465            pub fn dma_mem_saddr(&mut self) -> DmaMemSaddrW<'_, BusDmaMemSaddrSpec> {
17466                DmaMemSaddrW::new(self, 0)
17467            }
17468        }
17469        #[doc = "DMA memory start address\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_mem_saddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_mem_saddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17470        pub struct BusDmaMemSaddrSpec;
17471        impl crate::RegisterSpec for BusDmaMemSaddrSpec {
17472            type Ux = u32;
17473        }
17474        #[doc = "`read()` method returns [`bus_dma_mem_saddr::R`](R) reader structure"]
17475        impl crate::Readable for BusDmaMemSaddrSpec {}
17476        #[doc = "`write(|w| ..)` method takes [`bus_dma_mem_saddr::W`](W) writer structure"]
17477        impl crate::Writable for BusDmaMemSaddrSpec {
17478            type Safety = crate::Unsafe;
17479        }
17480        #[doc = "`reset()` method sets BUS_DMA_MEM_SADDR to value 0"]
17481        impl crate::Resettable for BusDmaMemSaddrSpec {}
17482    }
17483    #[doc = "BUS_DMA_FLASH_SADDR (rw) register accessor: DMA Flash start address\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_flash_saddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_flash_saddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_dma_flash_saddr`] module"]
17484    #[doc(alias = "BUS_DMA_FLASH_SADDR")]
17485    pub type BusDmaFlashSaddr = crate::Reg<bus_dma_flash_saddr::BusDmaFlashSaddrSpec>;
17486    #[doc = "DMA Flash start address"]
17487    pub mod bus_dma_flash_saddr {
17488        #[doc = "Register `BUS_DMA_FLASH_SADDR` reader"]
17489        pub type R = crate::R<BusDmaFlashSaddrSpec>;
17490        #[doc = "Register `BUS_DMA_FLASH_SADDR` writer"]
17491        pub type W = crate::W<BusDmaFlashSaddrSpec>;
17492        #[doc = "Field `dma_flash_saddr` reader - DMA Flash start address"]
17493        pub type DmaFlashSaddrR = crate::FieldReader<u32>;
17494        #[doc = "Field `dma_flash_saddr` writer - DMA Flash start address"]
17495        pub type DmaFlashSaddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
17496        impl R {
17497            #[doc = "Bits 0:31 - DMA Flash start address"]
17498            #[inline(always)]
17499            pub fn dma_flash_saddr(&self) -> DmaFlashSaddrR {
17500                DmaFlashSaddrR::new(self.bits)
17501            }
17502        }
17503        impl W {
17504            #[doc = "Bits 0:31 - DMA Flash start address"]
17505            #[inline(always)]
17506            pub fn dma_flash_saddr(&mut self) -> DmaFlashSaddrW<'_, BusDmaFlashSaddrSpec> {
17507                DmaFlashSaddrW::new(self, 0)
17508            }
17509        }
17510        #[doc = "DMA Flash start address\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_flash_saddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_flash_saddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17511        pub struct BusDmaFlashSaddrSpec;
17512        impl crate::RegisterSpec for BusDmaFlashSaddrSpec {
17513            type Ux = u32;
17514        }
17515        #[doc = "`read()` method returns [`bus_dma_flash_saddr::R`](R) reader structure"]
17516        impl crate::Readable for BusDmaFlashSaddrSpec {}
17517        #[doc = "`write(|w| ..)` method takes [`bus_dma_flash_saddr::W`](W) writer structure"]
17518        impl crate::Writable for BusDmaFlashSaddrSpec {
17519            type Safety = crate::Unsafe;
17520        }
17521        #[doc = "`reset()` method sets BUS_DMA_FLASH_SADDR to value 0"]
17522        impl crate::Resettable for BusDmaFlashSaddrSpec {}
17523    }
17524    #[doc = "BUS_DMA_LEN (rw) register accessor: DMA transfer length\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_dma_len`] module"]
17525    #[doc(alias = "BUS_DMA_LEN")]
17526    pub type BusDmaLen = crate::Reg<bus_dma_len::BusDmaLenSpec>;
17527    #[doc = "DMA transfer length"]
17528    pub mod bus_dma_len {
17529        #[doc = "Register `BUS_DMA_LEN` reader"]
17530        pub type R = crate::R<BusDmaLenSpec>;
17531        #[doc = "Register `BUS_DMA_LEN` writer"]
17532        pub type W = crate::W<BusDmaLenSpec>;
17533        #[doc = "Field `dma_len` reader - DMA length (n+1 bytes)"]
17534        pub type DmaLenR = crate::FieldReader<u32>;
17535        #[doc = "Field `dma_len` writer - DMA length (n+1 bytes)"]
17536        pub type DmaLenW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
17537        impl R {
17538            #[doc = "Bits 0:29 - DMA length (n+1 bytes)"]
17539            #[inline(always)]
17540            pub fn dma_len(&self) -> DmaLenR {
17541                DmaLenR::new(self.bits & 0x3fff_ffff)
17542            }
17543        }
17544        impl W {
17545            #[doc = "Bits 0:29 - DMA length (n+1 bytes)"]
17546            #[inline(always)]
17547            pub fn dma_len(&mut self) -> DmaLenW<'_, BusDmaLenSpec> {
17548                DmaLenW::new(self, 0)
17549            }
17550        }
17551        #[doc = "DMA transfer length\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17552        pub struct BusDmaLenSpec;
17553        impl crate::RegisterSpec for BusDmaLenSpec {
17554            type Ux = u32;
17555        }
17556        #[doc = "`read()` method returns [`bus_dma_len::R`](R) reader structure"]
17557        impl crate::Readable for BusDmaLenSpec {}
17558        #[doc = "`write(|w| ..)` method takes [`bus_dma_len::W`](W) writer structure"]
17559        impl crate::Writable for BusDmaLenSpec {
17560            type Safety = crate::Unsafe;
17561        }
17562        #[doc = "`reset()` method sets BUS_DMA_LEN to value 0"]
17563        impl crate::Resettable for BusDmaLenSpec {}
17564    }
17565    #[doc = "BUS_DMA_AHB_CTRL (rw) register accessor: DMA AHB burst control\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_ahb_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_ahb_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_dma_ahb_ctrl`] module"]
17566    #[doc(alias = "BUS_DMA_AHB_CTRL")]
17567    pub type BusDmaAhbCtrl = crate::Reg<bus_dma_ahb_ctrl::BusDmaAhbCtrlSpec>;
17568    #[doc = "DMA AHB burst control"]
17569    pub mod bus_dma_ahb_ctrl {
17570        #[doc = "Register `BUS_DMA_AHB_CTRL` reader"]
17571        pub type R = crate::R<BusDmaAhbCtrlSpec>;
17572        #[doc = "Register `BUS_DMA_AHB_CTRL` writer"]
17573        pub type W = crate::W<BusDmaAhbCtrlSpec>;
17574        #[doc = "Field `incr4_en` reader - INCR4 burst enable"]
17575        pub type Incr4EnR = crate::BitReader;
17576        #[doc = "Field `incr4_en` writer - INCR4 burst enable"]
17577        pub type Incr4EnW<'a, REG> = crate::BitWriter<'a, REG>;
17578        #[doc = "Field `incr8_en` reader - INCR8 burst enable"]
17579        pub type Incr8EnR = crate::BitReader;
17580        #[doc = "Field `incr8_en` writer - INCR8 burst enable"]
17581        pub type Incr8EnW<'a, REG> = crate::BitWriter<'a, REG>;
17582        #[doc = "Field `incr16_en` reader - INCR16 burst enable"]
17583        pub type Incr16EnR = crate::BitReader;
17584        #[doc = "Field `incr16_en` writer - INCR16 burst enable"]
17585        pub type Incr16EnW<'a, REG> = crate::BitWriter<'a, REG>;
17586        impl R {
17587            #[doc = "Bit 0 - INCR4 burst enable"]
17588            #[inline(always)]
17589            pub fn incr4_en(&self) -> Incr4EnR {
17590                Incr4EnR::new((self.bits & 1) != 0)
17591            }
17592            #[doc = "Bit 1 - INCR8 burst enable"]
17593            #[inline(always)]
17594            pub fn incr8_en(&self) -> Incr8EnR {
17595                Incr8EnR::new(((self.bits >> 1) & 1) != 0)
17596            }
17597            #[doc = "Bit 2 - INCR16 burst enable"]
17598            #[inline(always)]
17599            pub fn incr16_en(&self) -> Incr16EnR {
17600                Incr16EnR::new(((self.bits >> 2) & 1) != 0)
17601            }
17602        }
17603        impl W {
17604            #[doc = "Bit 0 - INCR4 burst enable"]
17605            #[inline(always)]
17606            pub fn incr4_en(&mut self) -> Incr4EnW<'_, BusDmaAhbCtrlSpec> {
17607                Incr4EnW::new(self, 0)
17608            }
17609            #[doc = "Bit 1 - INCR8 burst enable"]
17610            #[inline(always)]
17611            pub fn incr8_en(&mut self) -> Incr8EnW<'_, BusDmaAhbCtrlSpec> {
17612                Incr8EnW::new(self, 1)
17613            }
17614            #[doc = "Bit 2 - INCR16 burst enable"]
17615            #[inline(always)]
17616            pub fn incr16_en(&mut self) -> Incr16EnW<'_, BusDmaAhbCtrlSpec> {
17617                Incr16EnW::new(self, 2)
17618            }
17619        }
17620        #[doc = "DMA AHB burst control\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_ahb_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_ahb_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17621        pub struct BusDmaAhbCtrlSpec;
17622        impl crate::RegisterSpec for BusDmaAhbCtrlSpec {
17623            type Ux = u32;
17624        }
17625        #[doc = "`read()` method returns [`bus_dma_ahb_ctrl::R`](R) reader structure"]
17626        impl crate::Readable for BusDmaAhbCtrlSpec {}
17627        #[doc = "`write(|w| ..)` method takes [`bus_dma_ahb_ctrl::W`](W) writer structure"]
17628        impl crate::Writable for BusDmaAhbCtrlSpec {
17629            type Safety = crate::Unsafe;
17630        }
17631        #[doc = "`reset()` method sets BUS_DMA_AHB_CTRL to value 0x07"]
17632        impl crate::Resettable for BusDmaAhbCtrlSpec {
17633            const RESET_VALUE: u32 = 0x07;
17634        }
17635    }
17636    #[doc = "CMD_CONFIG (rw) register accessor: Command operation config\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_config`] module"]
17637    #[doc(alias = "CMD_CONFIG")]
17638    pub type CmdConfig = crate::Reg<cmd_config::CmdConfigSpec>;
17639    #[doc = "Command operation config"]
17640    pub mod cmd_config {
17641        #[doc = "Register `CMD_CONFIG` reader"]
17642        pub type R = crate::R<CmdConfigSpec>;
17643        #[doc = "Register `CMD_CONFIG` writer"]
17644        pub type W = crate::W<CmdConfigSpec>;
17645        #[doc = "Field `start` reader - Command start (auto-clears)"]
17646        pub type StartR = crate::BitReader;
17647        #[doc = "Field `start` writer - Command start (auto-clears)"]
17648        pub type StartW<'a, REG> = crate::BitWriter<'a, REG>;
17649        #[doc = "Field `sel_cs` reader - Chip select: 0=CS0; 1=CS1"]
17650        pub type SelCsR = crate::BitReader;
17651        #[doc = "Field `sel_cs` writer - Chip select: 0=CS0; 1=CS1"]
17652        pub type SelCsW<'a, REG> = crate::BitWriter<'a, REG>;
17653        #[doc = "Field `addr_en` reader - Address present: 0=no; 1=yes"]
17654        pub type AddrEnR = crate::BitReader;
17655        #[doc = "Field `addr_en` writer - Address present: 0=no; 1=yes"]
17656        pub type AddrEnW<'a, REG> = crate::BitWriter<'a, REG>;
17657        #[doc = "Field `dummy_byte_cnt` reader - Dummy bytes: 000=0; 001=1; etc."]
17658        pub type DummyByteCntR = crate::FieldReader;
17659        #[doc = "Field `dummy_byte_cnt` writer - Dummy bytes: 000=0; 001=1; etc."]
17660        pub type DummyByteCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17661        #[doc = "Field `data_en` reader - Data present: 0=no; 1=yes"]
17662        pub type DataEnR = crate::BitReader;
17663        #[doc = "Field `data_en` writer - Data present: 0=no; 1=yes"]
17664        pub type DataEnW<'a, REG> = crate::BitWriter<'a, REG>;
17665        #[doc = "Field `rw` reader - Data direction: 0=write; 1=read"]
17666        pub type RwR = crate::BitReader;
17667        #[doc = "Field `rw` writer - Data direction: 0=write; 1=read"]
17668        pub type RwW<'a, REG> = crate::BitWriter<'a, REG>;
17669        #[doc = "Field `data_cnt` reader - Data length (n+1 bytes)"]
17670        pub type DataCntR = crate::FieldReader;
17671        #[doc = "Field `data_cnt` writer - Data length (n+1 bytes)"]
17672        pub type DataCntW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17673        #[doc = "Field `mem_if_type` reader - SPI interface type: 000=Standard; 001=Dual; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
17674        pub type MemIfTypeR = crate::FieldReader;
17675        #[doc = "Field `mem_if_type` writer - SPI interface type: 000=Standard; 001=Dual; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
17676        pub type MemIfTypeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17677        impl R {
17678            #[doc = "Bit 0 - Command start (auto-clears)"]
17679            #[inline(always)]
17680            pub fn start(&self) -> StartR {
17681                StartR::new((self.bits & 1) != 0)
17682            }
17683            #[doc = "Bit 1 - Chip select: 0=CS0; 1=CS1"]
17684            #[inline(always)]
17685            pub fn sel_cs(&self) -> SelCsR {
17686                SelCsR::new(((self.bits >> 1) & 1) != 0)
17687            }
17688            #[doc = "Bit 3 - Address present: 0=no; 1=yes"]
17689            #[inline(always)]
17690            pub fn addr_en(&self) -> AddrEnR {
17691                AddrEnR::new(((self.bits >> 3) & 1) != 0)
17692            }
17693            #[doc = "Bits 4:6 - Dummy bytes: 000=0; 001=1; etc."]
17694            #[inline(always)]
17695            pub fn dummy_byte_cnt(&self) -> DummyByteCntR {
17696                DummyByteCntR::new(((self.bits >> 4) & 7) as u8)
17697            }
17698            #[doc = "Bit 7 - Data present: 0=no; 1=yes"]
17699            #[inline(always)]
17700            pub fn data_en(&self) -> DataEnR {
17701                DataEnR::new(((self.bits >> 7) & 1) != 0)
17702            }
17703            #[doc = "Bit 8 - Data direction: 0=write; 1=read"]
17704            #[inline(always)]
17705            pub fn rw(&self) -> RwR {
17706                RwR::new(((self.bits >> 8) & 1) != 0)
17707            }
17708            #[doc = "Bits 9:14 - Data length (n+1 bytes)"]
17709            #[inline(always)]
17710            pub fn data_cnt(&self) -> DataCntR {
17711                DataCntR::new(((self.bits >> 9) & 0x3f) as u8)
17712            }
17713            #[doc = "Bits 17:19 - SPI interface type: 000=Standard; 001=Dual; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
17714            #[inline(always)]
17715            pub fn mem_if_type(&self) -> MemIfTypeR {
17716                MemIfTypeR::new(((self.bits >> 17) & 7) as u8)
17717            }
17718        }
17719        impl W {
17720            #[doc = "Bit 0 - Command start (auto-clears)"]
17721            #[inline(always)]
17722            pub fn start(&mut self) -> StartW<'_, CmdConfigSpec> {
17723                StartW::new(self, 0)
17724            }
17725            #[doc = "Bit 1 - Chip select: 0=CS0; 1=CS1"]
17726            #[inline(always)]
17727            pub fn sel_cs(&mut self) -> SelCsW<'_, CmdConfigSpec> {
17728                SelCsW::new(self, 1)
17729            }
17730            #[doc = "Bit 3 - Address present: 0=no; 1=yes"]
17731            #[inline(always)]
17732            pub fn addr_en(&mut self) -> AddrEnW<'_, CmdConfigSpec> {
17733                AddrEnW::new(self, 3)
17734            }
17735            #[doc = "Bits 4:6 - Dummy bytes: 000=0; 001=1; etc."]
17736            #[inline(always)]
17737            pub fn dummy_byte_cnt(&mut self) -> DummyByteCntW<'_, CmdConfigSpec> {
17738                DummyByteCntW::new(self, 4)
17739            }
17740            #[doc = "Bit 7 - Data present: 0=no; 1=yes"]
17741            #[inline(always)]
17742            pub fn data_en(&mut self) -> DataEnW<'_, CmdConfigSpec> {
17743                DataEnW::new(self, 7)
17744            }
17745            #[doc = "Bit 8 - Data direction: 0=write; 1=read"]
17746            #[inline(always)]
17747            pub fn rw(&mut self) -> RwW<'_, CmdConfigSpec> {
17748                RwW::new(self, 8)
17749            }
17750            #[doc = "Bits 9:14 - Data length (n+1 bytes)"]
17751            #[inline(always)]
17752            pub fn data_cnt(&mut self) -> DataCntW<'_, CmdConfigSpec> {
17753                DataCntW::new(self, 9)
17754            }
17755            #[doc = "Bits 17:19 - SPI interface type: 000=Standard; 001=Dual; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
17756            #[inline(always)]
17757            pub fn mem_if_type(&mut self) -> MemIfTypeW<'_, CmdConfigSpec> {
17758                MemIfTypeW::new(self, 17)
17759            }
17760        }
17761        #[doc = "Command operation config\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17762        pub struct CmdConfigSpec;
17763        impl crate::RegisterSpec for CmdConfigSpec {
17764            type Ux = u32;
17765        }
17766        #[doc = "`read()` method returns [`cmd_config::R`](R) reader structure"]
17767        impl crate::Readable for CmdConfigSpec {}
17768        #[doc = "`write(|w| ..)` method takes [`cmd_config::W`](W) writer structure"]
17769        impl crate::Writable for CmdConfigSpec {
17770            type Safety = crate::Unsafe;
17771        }
17772        #[doc = "`reset()` method sets CMD_CONFIG to value 0x7e00"]
17773        impl crate::Resettable for CmdConfigSpec {
17774            const RESET_VALUE: u32 = 0x7e00;
17775        }
17776    }
17777    #[doc = "CMD_INS (rw) register accessor: Command instruction register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_ins::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_ins::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_ins`] module"]
17778    #[doc(alias = "CMD_INS")]
17779    pub type CmdIns = crate::Reg<cmd_ins::CmdInsSpec>;
17780    #[doc = "Command instruction register"]
17781    pub mod cmd_ins {
17782        #[doc = "Register `CMD_INS` reader"]
17783        pub type R = crate::R<CmdInsSpec>;
17784        #[doc = "Register `CMD_INS` writer"]
17785        pub type W = crate::W<CmdInsSpec>;
17786        #[doc = "Field `reg_ins` reader - Instruction code"]
17787        pub type RegInsR = crate::FieldReader;
17788        #[doc = "Field `reg_ins` writer - Instruction code"]
17789        pub type RegInsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17790        impl R {
17791            #[doc = "Bits 0:7 - Instruction code"]
17792            #[inline(always)]
17793            pub fn reg_ins(&self) -> RegInsR {
17794                RegInsR::new((self.bits & 0xff) as u8)
17795            }
17796        }
17797        impl W {
17798            #[doc = "Bits 0:7 - Instruction code"]
17799            #[inline(always)]
17800            pub fn reg_ins(&mut self) -> RegInsW<'_, CmdInsSpec> {
17801                RegInsW::new(self, 0)
17802            }
17803        }
17804        #[doc = "Command instruction register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_ins::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_ins::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17805        pub struct CmdInsSpec;
17806        impl crate::RegisterSpec for CmdInsSpec {
17807            type Ux = u32;
17808        }
17809        #[doc = "`read()` method returns [`cmd_ins::R`](R) reader structure"]
17810        impl crate::Readable for CmdInsSpec {}
17811        #[doc = "`write(|w| ..)` method takes [`cmd_ins::W`](W) writer structure"]
17812        impl crate::Writable for CmdInsSpec {
17813            type Safety = crate::Unsafe;
17814        }
17815        #[doc = "`reset()` method sets CMD_INS to value 0"]
17816        impl crate::Resettable for CmdInsSpec {}
17817    }
17818    #[doc = "CMD_ADDR (rw) register accessor: Command address register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_addr`] module"]
17819    #[doc(alias = "CMD_ADDR")]
17820    pub type CmdAddr = crate::Reg<cmd_addr::CmdAddrSpec>;
17821    #[doc = "Command address register"]
17822    pub mod cmd_addr {
17823        #[doc = "Register `CMD_ADDR` reader"]
17824        pub type R = crate::R<CmdAddrSpec>;
17825        #[doc = "Register `CMD_ADDR` writer"]
17826        pub type W = crate::W<CmdAddrSpec>;
17827        #[doc = "Field `cmd_addr` reader - Operation address"]
17828        pub type CmdAddrR = crate::FieldReader<u32>;
17829        #[doc = "Field `cmd_addr` writer - Operation address"]
17830        pub type CmdAddrW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
17831        impl R {
17832            #[doc = "Bits 0:29 - Operation address"]
17833            #[inline(always)]
17834            pub fn cmd_addr(&self) -> CmdAddrR {
17835                CmdAddrR::new(self.bits & 0x3fff_ffff)
17836            }
17837        }
17838        impl W {
17839            #[doc = "Bits 0:29 - Operation address"]
17840            #[inline(always)]
17841            pub fn cmd_addr(&mut self) -> CmdAddrW<'_, CmdAddrSpec> {
17842                CmdAddrW::new(self, 0)
17843            }
17844        }
17845        #[doc = "Command address register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17846        pub struct CmdAddrSpec;
17847        impl crate::RegisterSpec for CmdAddrSpec {
17848            type Ux = u32;
17849        }
17850        #[doc = "`read()` method returns [`cmd_addr::R`](R) reader structure"]
17851        impl crate::Readable for CmdAddrSpec {}
17852        #[doc = "`write(|w| ..)` method takes [`cmd_addr::W`](W) writer structure"]
17853        impl crate::Writable for CmdAddrSpec {
17854            type Safety = crate::Unsafe;
17855        }
17856        #[doc = "`reset()` method sets CMD_ADDR to value 0"]
17857        impl crate::Resettable for CmdAddrSpec {}
17858    }
17859    #[doc = "CMD_DATABUF_0 (rw) register accessor: Command data buffer 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_0`] module"]
17860    #[doc(alias = "CMD_DATABUF_0")]
17861    pub type CmdDatabuf0 = crate::Reg<cmd_databuf_0::CmdDatabuf0Spec>;
17862    #[doc = "Command data buffer 0"]
17863    pub mod cmd_databuf_0 {
17864        #[doc = "Register `CMD_DATABUF_0` reader"]
17865        pub type R = crate::R<CmdDatabuf0Spec>;
17866        #[doc = "Register `CMD_DATABUF_0` writer"]
17867        pub type W = crate::W<CmdDatabuf0Spec>;
17868        #[doc = "Field `cmd_databuf_0` reader - Data buffer 0"]
17869        pub type CmdDatabuf0R = crate::FieldReader<u32>;
17870        #[doc = "Field `cmd_databuf_0` writer - Data buffer 0"]
17871        pub type CmdDatabuf0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
17872        impl R {
17873            #[doc = "Bits 0:31 - Data buffer 0"]
17874            #[inline(always)]
17875            pub fn cmd_databuf_0(&self) -> CmdDatabuf0R {
17876                CmdDatabuf0R::new(self.bits)
17877            }
17878        }
17879        impl W {
17880            #[doc = "Bits 0:31 - Data buffer 0"]
17881            #[inline(always)]
17882            pub fn cmd_databuf_0(&mut self) -> CmdDatabuf0W<'_, CmdDatabuf0Spec> {
17883                CmdDatabuf0W::new(self, 0)
17884            }
17885        }
17886        #[doc = "Command data buffer 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17887        pub struct CmdDatabuf0Spec;
17888        impl crate::RegisterSpec for CmdDatabuf0Spec {
17889            type Ux = u32;
17890        }
17891        #[doc = "`read()` method returns [`cmd_databuf_0::R`](R) reader structure"]
17892        impl crate::Readable for CmdDatabuf0Spec {}
17893        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_0::W`](W) writer structure"]
17894        impl crate::Writable for CmdDatabuf0Spec {
17895            type Safety = crate::Unsafe;
17896        }
17897        #[doc = "`reset()` method sets CMD_DATABUF_0 to value 0"]
17898        impl crate::Resettable for CmdDatabuf0Spec {}
17899    }
17900    #[doc = "LEA_LP_EN (rw) register accessor: LEA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_lp_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_lp_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lea_lp_en`] module"]
17901    #[doc(alias = "LEA_LP_EN")]
17902    pub type LeaLpEn = crate::Reg<lea_lp_en::LeaLpEnSpec>;
17903    #[doc = "LEA control register"]
17904    pub mod lea_lp_en {
17905        #[doc = "Register `LEA_LP_EN` reader"]
17906        pub type R = crate::R<LeaLpEnSpec>;
17907        #[doc = "Register `LEA_LP_EN` writer"]
17908        pub type W = crate::W<LeaLpEnSpec>;
17909        #[doc = "Field `lea_lp_en` reader - AES low power: 0=disabled; 1=enabled"]
17910        pub type LeaLpEnR = crate::BitReader;
17911        #[doc = "Field `lea_lp_en` writer - AES low power: 0=disabled; 1=enabled"]
17912        pub type LeaLpEnW<'a, REG> = crate::BitWriter<'a, REG>;
17913        impl R {
17914            #[doc = "Bit 0 - AES low power: 0=disabled; 1=enabled"]
17915            #[inline(always)]
17916            pub fn lea_lp_en(&self) -> LeaLpEnR {
17917                LeaLpEnR::new((self.bits & 1) != 0)
17918            }
17919        }
17920        impl W {
17921            #[doc = "Bit 0 - AES low power: 0=disabled; 1=enabled"]
17922            #[inline(always)]
17923            pub fn lea_lp_en(&mut self) -> LeaLpEnW<'_, LeaLpEnSpec> {
17924                LeaLpEnW::new(self, 0)
17925            }
17926        }
17927        #[doc = "LEA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_lp_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_lp_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17928        pub struct LeaLpEnSpec;
17929        impl crate::RegisterSpec for LeaLpEnSpec {
17930            type Ux = u32;
17931        }
17932        #[doc = "`read()` method returns [`lea_lp_en::R`](R) reader structure"]
17933        impl crate::Readable for LeaLpEnSpec {}
17934        #[doc = "`write(|w| ..)` method takes [`lea_lp_en::W`](W) writer structure"]
17935        impl crate::Writable for LeaLpEnSpec {
17936            type Safety = crate::Unsafe;
17937        }
17938        #[doc = "`reset()` method sets LEA_LP_EN to value 0x01"]
17939        impl crate::Resettable for LeaLpEnSpec {
17940            const RESET_VALUE: u32 = 0x01;
17941        }
17942    }
17943    #[doc = "LEA_DFX_INFO (rw) register accessor: LEA DFX register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_dfx_info::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_dfx_info::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lea_dfx_info`] module"]
17944    #[doc(alias = "LEA_DFX_INFO")]
17945    pub type LeaDfxInfo = crate::Reg<lea_dfx_info::LeaDfxInfoSpec>;
17946    #[doc = "LEA DFX register"]
17947    pub mod lea_dfx_info {
17948        #[doc = "Register `LEA_DFX_INFO` reader"]
17949        pub type R = crate::R<LeaDfxInfoSpec>;
17950        #[doc = "Register `LEA_DFX_INFO` writer"]
17951        pub type W = crate::W<LeaDfxInfoSpec>;
17952        #[doc = "Field `lea_dfx_info` reader - AES DFX observation"]
17953        pub type LeaDfxInfoR = crate::FieldReader<u32>;
17954        impl R {
17955            #[doc = "Bits 0:31 - AES DFX observation"]
17956            #[inline(always)]
17957            pub fn lea_dfx_info(&self) -> LeaDfxInfoR {
17958                LeaDfxInfoR::new(self.bits)
17959            }
17960        }
17961        impl W {}
17962        #[doc = "LEA DFX register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_dfx_info::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_dfx_info::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17963        pub struct LeaDfxInfoSpec;
17964        impl crate::RegisterSpec for LeaDfxInfoSpec {
17965            type Ux = u32;
17966        }
17967        #[doc = "`read()` method returns [`lea_dfx_info::R`](R) reader structure"]
17968        impl crate::Readable for LeaDfxInfoSpec {}
17969        #[doc = "`write(|w| ..)` method takes [`lea_dfx_info::W`](W) writer structure"]
17970        impl crate::Writable for LeaDfxInfoSpec {
17971            type Safety = crate::Unsafe;
17972        }
17973        #[doc = "`reset()` method sets LEA_DFX_INFO to value 0"]
17974        impl crate::Resettable for LeaDfxInfoSpec {}
17975    }
17976    #[doc = "LEA_IV_VLD (rw) register accessor: LEA IV valid register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_iv_vld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_iv_vld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lea_iv_vld`] module"]
17977    #[doc(alias = "LEA_IV_VLD")]
17978    pub type LeaIvVld = crate::Reg<lea_iv_vld::LeaIvVldSpec>;
17979    #[doc = "LEA IV valid register"]
17980    pub mod lea_iv_vld {
17981        #[doc = "Register `LEA_IV_VLD` reader"]
17982        pub type R = crate::R<LeaIvVldSpec>;
17983        #[doc = "Register `LEA_IV_VLD` writer"]
17984        pub type W = crate::W<LeaIvVldSpec>;
17985        #[doc = "Field `lea_iv_vld` reader - AES IV value valid (auto-clears after sync)"]
17986        pub type LeaIvVldR = crate::BitReader;
17987        #[doc = "Field `lea_iv_vld` writer - AES IV value valid (auto-clears after sync)"]
17988        pub type LeaIvVldW<'a, REG> = crate::BitWriter<'a, REG>;
17989        impl R {
17990            #[doc = "Bit 0 - AES IV value valid (auto-clears after sync)"]
17991            #[inline(always)]
17992            pub fn lea_iv_vld(&self) -> LeaIvVldR {
17993                LeaIvVldR::new((self.bits & 1) != 0)
17994            }
17995        }
17996        impl W {
17997            #[doc = "Bit 0 - AES IV value valid (auto-clears after sync)"]
17998            #[inline(always)]
17999            pub fn lea_iv_vld(&mut self) -> LeaIvVldW<'_, LeaIvVldSpec> {
18000                LeaIvVldW::new(self, 0)
18001            }
18002        }
18003        #[doc = "LEA IV valid register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_iv_vld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_iv_vld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18004        pub struct LeaIvVldSpec;
18005        impl crate::RegisterSpec for LeaIvVldSpec {
18006            type Ux = u32;
18007        }
18008        #[doc = "`read()` method returns [`lea_iv_vld::R`](R) reader structure"]
18009        impl crate::Readable for LeaIvVldSpec {}
18010        #[doc = "`write(|w| ..)` method takes [`lea_iv_vld::W`](W) writer structure"]
18011        impl crate::Writable for LeaIvVldSpec {
18012            type Safety = crate::Unsafe;
18013        }
18014        #[doc = "`reset()` method sets LEA_IV_VLD to value 0"]
18015        impl crate::Resettable for LeaIvVldSpec {}
18016    }
18017    #[doc = "CMD_DATABUF_1 (rw) register accessor: Command data buffer 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_1`] module"]
18018    #[doc(alias = "CMD_DATABUF_1")]
18019    pub type CmdDatabuf1 = crate::Reg<cmd_databuf_1::CmdDatabuf1Spec>;
18020    #[doc = "Command data buffer 1"]
18021    pub mod cmd_databuf_1 {
18022        #[doc = "Register `CMD_DATABUF_1` reader"]
18023        pub type R = crate::R<CmdDatabuf1Spec>;
18024        #[doc = "Register `CMD_DATABUF_1` writer"]
18025        pub type W = crate::W<CmdDatabuf1Spec>;
18026        #[doc = "Field `cmd_databuf_1` reader - Command data buffer 1"]
18027        pub type CmdDatabuf1R = crate::FieldReader<u32>;
18028        #[doc = "Field `cmd_databuf_1` writer - Command data buffer 1"]
18029        pub type CmdDatabuf1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18030        impl R {
18031            #[doc = "Bits 0:31 - Command data buffer 1"]
18032            #[inline(always)]
18033            pub fn cmd_databuf_1(&self) -> CmdDatabuf1R {
18034                CmdDatabuf1R::new(self.bits)
18035            }
18036        }
18037        impl W {
18038            #[doc = "Bits 0:31 - Command data buffer 1"]
18039            #[inline(always)]
18040            pub fn cmd_databuf_1(&mut self) -> CmdDatabuf1W<'_, CmdDatabuf1Spec> {
18041                CmdDatabuf1W::new(self, 0)
18042            }
18043        }
18044        #[doc = "Command data buffer 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18045        pub struct CmdDatabuf1Spec;
18046        impl crate::RegisterSpec for CmdDatabuf1Spec {
18047            type Ux = u32;
18048        }
18049        #[doc = "`read()` method returns [`cmd_databuf_1::R`](R) reader structure"]
18050        impl crate::Readable for CmdDatabuf1Spec {}
18051        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_1::W`](W) writer structure"]
18052        impl crate::Writable for CmdDatabuf1Spec {
18053            type Safety = crate::Unsafe;
18054        }
18055        #[doc = "`reset()` method sets CMD_DATABUF_1 to value 0"]
18056        impl crate::Resettable for CmdDatabuf1Spec {}
18057    }
18058    #[doc = "CMD_DATABUF_2 (rw) register accessor: Command data buffer 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_2`] module"]
18059    #[doc(alias = "CMD_DATABUF_2")]
18060    pub type CmdDatabuf2 = crate::Reg<cmd_databuf_2::CmdDatabuf2Spec>;
18061    #[doc = "Command data buffer 2"]
18062    pub mod cmd_databuf_2 {
18063        #[doc = "Register `CMD_DATABUF_2` reader"]
18064        pub type R = crate::R<CmdDatabuf2Spec>;
18065        #[doc = "Register `CMD_DATABUF_2` writer"]
18066        pub type W = crate::W<CmdDatabuf2Spec>;
18067        #[doc = "Field `cmd_databuf_2` reader - Command data buffer 2"]
18068        pub type CmdDatabuf2R = crate::FieldReader<u32>;
18069        #[doc = "Field `cmd_databuf_2` writer - Command data buffer 2"]
18070        pub type CmdDatabuf2W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18071        impl R {
18072            #[doc = "Bits 0:31 - Command data buffer 2"]
18073            #[inline(always)]
18074            pub fn cmd_databuf_2(&self) -> CmdDatabuf2R {
18075                CmdDatabuf2R::new(self.bits)
18076            }
18077        }
18078        impl W {
18079            #[doc = "Bits 0:31 - Command data buffer 2"]
18080            #[inline(always)]
18081            pub fn cmd_databuf_2(&mut self) -> CmdDatabuf2W<'_, CmdDatabuf2Spec> {
18082                CmdDatabuf2W::new(self, 0)
18083            }
18084        }
18085        #[doc = "Command data buffer 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18086        pub struct CmdDatabuf2Spec;
18087        impl crate::RegisterSpec for CmdDatabuf2Spec {
18088            type Ux = u32;
18089        }
18090        #[doc = "`read()` method returns [`cmd_databuf_2::R`](R) reader structure"]
18091        impl crate::Readable for CmdDatabuf2Spec {}
18092        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_2::W`](W) writer structure"]
18093        impl crate::Writable for CmdDatabuf2Spec {
18094            type Safety = crate::Unsafe;
18095        }
18096        #[doc = "`reset()` method sets CMD_DATABUF_2 to value 0"]
18097        impl crate::Resettable for CmdDatabuf2Spec {}
18098    }
18099    #[doc = "CMD_DATABUF_3 (rw) register accessor: Command data buffer 3\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_3`] module"]
18100    #[doc(alias = "CMD_DATABUF_3")]
18101    pub type CmdDatabuf3 = crate::Reg<cmd_databuf_3::CmdDatabuf3Spec>;
18102    #[doc = "Command data buffer 3"]
18103    pub mod cmd_databuf_3 {
18104        #[doc = "Register `CMD_DATABUF_3` reader"]
18105        pub type R = crate::R<CmdDatabuf3Spec>;
18106        #[doc = "Register `CMD_DATABUF_3` writer"]
18107        pub type W = crate::W<CmdDatabuf3Spec>;
18108        #[doc = "Field `cmd_databuf_3` reader - Command data buffer 3"]
18109        pub type CmdDatabuf3R = crate::FieldReader<u32>;
18110        #[doc = "Field `cmd_databuf_3` writer - Command data buffer 3"]
18111        pub type CmdDatabuf3W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18112        impl R {
18113            #[doc = "Bits 0:31 - Command data buffer 3"]
18114            #[inline(always)]
18115            pub fn cmd_databuf_3(&self) -> CmdDatabuf3R {
18116                CmdDatabuf3R::new(self.bits)
18117            }
18118        }
18119        impl W {
18120            #[doc = "Bits 0:31 - Command data buffer 3"]
18121            #[inline(always)]
18122            pub fn cmd_databuf_3(&mut self) -> CmdDatabuf3W<'_, CmdDatabuf3Spec> {
18123                CmdDatabuf3W::new(self, 0)
18124            }
18125        }
18126        #[doc = "Command data buffer 3\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18127        pub struct CmdDatabuf3Spec;
18128        impl crate::RegisterSpec for CmdDatabuf3Spec {
18129            type Ux = u32;
18130        }
18131        #[doc = "`read()` method returns [`cmd_databuf_3::R`](R) reader structure"]
18132        impl crate::Readable for CmdDatabuf3Spec {}
18133        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_3::W`](W) writer structure"]
18134        impl crate::Writable for CmdDatabuf3Spec {
18135            type Safety = crate::Unsafe;
18136        }
18137        #[doc = "`reset()` method sets CMD_DATABUF_3 to value 0"]
18138        impl crate::Resettable for CmdDatabuf3Spec {}
18139    }
18140    #[doc = "CMD_DATABUF_4 (rw) register accessor: Command data buffer 4\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_4`] module"]
18141    #[doc(alias = "CMD_DATABUF_4")]
18142    pub type CmdDatabuf4 = crate::Reg<cmd_databuf_4::CmdDatabuf4Spec>;
18143    #[doc = "Command data buffer 4"]
18144    pub mod cmd_databuf_4 {
18145        #[doc = "Register `CMD_DATABUF_4` reader"]
18146        pub type R = crate::R<CmdDatabuf4Spec>;
18147        #[doc = "Register `CMD_DATABUF_4` writer"]
18148        pub type W = crate::W<CmdDatabuf4Spec>;
18149        #[doc = "Field `cmd_databuf_4` reader - Command data buffer 4"]
18150        pub type CmdDatabuf4R = crate::FieldReader<u32>;
18151        #[doc = "Field `cmd_databuf_4` writer - Command data buffer 4"]
18152        pub type CmdDatabuf4W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18153        impl R {
18154            #[doc = "Bits 0:31 - Command data buffer 4"]
18155            #[inline(always)]
18156            pub fn cmd_databuf_4(&self) -> CmdDatabuf4R {
18157                CmdDatabuf4R::new(self.bits)
18158            }
18159        }
18160        impl W {
18161            #[doc = "Bits 0:31 - Command data buffer 4"]
18162            #[inline(always)]
18163            pub fn cmd_databuf_4(&mut self) -> CmdDatabuf4W<'_, CmdDatabuf4Spec> {
18164                CmdDatabuf4W::new(self, 0)
18165            }
18166        }
18167        #[doc = "Command data buffer 4\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18168        pub struct CmdDatabuf4Spec;
18169        impl crate::RegisterSpec for CmdDatabuf4Spec {
18170            type Ux = u32;
18171        }
18172        #[doc = "`read()` method returns [`cmd_databuf_4::R`](R) reader structure"]
18173        impl crate::Readable for CmdDatabuf4Spec {}
18174        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_4::W`](W) writer structure"]
18175        impl crate::Writable for CmdDatabuf4Spec {
18176            type Safety = crate::Unsafe;
18177        }
18178        #[doc = "`reset()` method sets CMD_DATABUF_4 to value 0"]
18179        impl crate::Resettable for CmdDatabuf4Spec {}
18180    }
18181    #[doc = "CMD_DATABUF_5 (rw) register accessor: Command data buffer 5\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_5`] module"]
18182    #[doc(alias = "CMD_DATABUF_5")]
18183    pub type CmdDatabuf5 = crate::Reg<cmd_databuf_5::CmdDatabuf5Spec>;
18184    #[doc = "Command data buffer 5"]
18185    pub mod cmd_databuf_5 {
18186        #[doc = "Register `CMD_DATABUF_5` reader"]
18187        pub type R = crate::R<CmdDatabuf5Spec>;
18188        #[doc = "Register `CMD_DATABUF_5` writer"]
18189        pub type W = crate::W<CmdDatabuf5Spec>;
18190        #[doc = "Field `cmd_databuf_5` reader - Command data buffer 5"]
18191        pub type CmdDatabuf5R = crate::FieldReader<u32>;
18192        #[doc = "Field `cmd_databuf_5` writer - Command data buffer 5"]
18193        pub type CmdDatabuf5W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18194        impl R {
18195            #[doc = "Bits 0:31 - Command data buffer 5"]
18196            #[inline(always)]
18197            pub fn cmd_databuf_5(&self) -> CmdDatabuf5R {
18198                CmdDatabuf5R::new(self.bits)
18199            }
18200        }
18201        impl W {
18202            #[doc = "Bits 0:31 - Command data buffer 5"]
18203            #[inline(always)]
18204            pub fn cmd_databuf_5(&mut self) -> CmdDatabuf5W<'_, CmdDatabuf5Spec> {
18205                CmdDatabuf5W::new(self, 0)
18206            }
18207        }
18208        #[doc = "Command data buffer 5\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18209        pub struct CmdDatabuf5Spec;
18210        impl crate::RegisterSpec for CmdDatabuf5Spec {
18211            type Ux = u32;
18212        }
18213        #[doc = "`read()` method returns [`cmd_databuf_5::R`](R) reader structure"]
18214        impl crate::Readable for CmdDatabuf5Spec {}
18215        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_5::W`](W) writer structure"]
18216        impl crate::Writable for CmdDatabuf5Spec {
18217            type Safety = crate::Unsafe;
18218        }
18219        #[doc = "`reset()` method sets CMD_DATABUF_5 to value 0"]
18220        impl crate::Resettable for CmdDatabuf5Spec {}
18221    }
18222    #[doc = "CMD_DATABUF_6 (rw) register accessor: Command data buffer 6\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_6`] module"]
18223    #[doc(alias = "CMD_DATABUF_6")]
18224    pub type CmdDatabuf6 = crate::Reg<cmd_databuf_6::CmdDatabuf6Spec>;
18225    #[doc = "Command data buffer 6"]
18226    pub mod cmd_databuf_6 {
18227        #[doc = "Register `CMD_DATABUF_6` reader"]
18228        pub type R = crate::R<CmdDatabuf6Spec>;
18229        #[doc = "Register `CMD_DATABUF_6` writer"]
18230        pub type W = crate::W<CmdDatabuf6Spec>;
18231        #[doc = "Field `cmd_databuf_6` reader - Command data buffer 6"]
18232        pub type CmdDatabuf6R = crate::FieldReader<u32>;
18233        #[doc = "Field `cmd_databuf_6` writer - Command data buffer 6"]
18234        pub type CmdDatabuf6W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18235        impl R {
18236            #[doc = "Bits 0:31 - Command data buffer 6"]
18237            #[inline(always)]
18238            pub fn cmd_databuf_6(&self) -> CmdDatabuf6R {
18239                CmdDatabuf6R::new(self.bits)
18240            }
18241        }
18242        impl W {
18243            #[doc = "Bits 0:31 - Command data buffer 6"]
18244            #[inline(always)]
18245            pub fn cmd_databuf_6(&mut self) -> CmdDatabuf6W<'_, CmdDatabuf6Spec> {
18246                CmdDatabuf6W::new(self, 0)
18247            }
18248        }
18249        #[doc = "Command data buffer 6\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18250        pub struct CmdDatabuf6Spec;
18251        impl crate::RegisterSpec for CmdDatabuf6Spec {
18252            type Ux = u32;
18253        }
18254        #[doc = "`read()` method returns [`cmd_databuf_6::R`](R) reader structure"]
18255        impl crate::Readable for CmdDatabuf6Spec {}
18256        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_6::W`](W) writer structure"]
18257        impl crate::Writable for CmdDatabuf6Spec {
18258            type Safety = crate::Unsafe;
18259        }
18260        #[doc = "`reset()` method sets CMD_DATABUF_6 to value 0"]
18261        impl crate::Resettable for CmdDatabuf6Spec {}
18262    }
18263    #[doc = "CMD_DATABUF_7 (rw) register accessor: Command data buffer 7\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_7`] module"]
18264    #[doc(alias = "CMD_DATABUF_7")]
18265    pub type CmdDatabuf7 = crate::Reg<cmd_databuf_7::CmdDatabuf7Spec>;
18266    #[doc = "Command data buffer 7"]
18267    pub mod cmd_databuf_7 {
18268        #[doc = "Register `CMD_DATABUF_7` reader"]
18269        pub type R = crate::R<CmdDatabuf7Spec>;
18270        #[doc = "Register `CMD_DATABUF_7` writer"]
18271        pub type W = crate::W<CmdDatabuf7Spec>;
18272        #[doc = "Field `cmd_databuf_7` reader - Command data buffer 7"]
18273        pub type CmdDatabuf7R = crate::FieldReader<u32>;
18274        #[doc = "Field `cmd_databuf_7` writer - Command data buffer 7"]
18275        pub type CmdDatabuf7W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18276        impl R {
18277            #[doc = "Bits 0:31 - Command data buffer 7"]
18278            #[inline(always)]
18279            pub fn cmd_databuf_7(&self) -> CmdDatabuf7R {
18280                CmdDatabuf7R::new(self.bits)
18281            }
18282        }
18283        impl W {
18284            #[doc = "Bits 0:31 - Command data buffer 7"]
18285            #[inline(always)]
18286            pub fn cmd_databuf_7(&mut self) -> CmdDatabuf7W<'_, CmdDatabuf7Spec> {
18287                CmdDatabuf7W::new(self, 0)
18288            }
18289        }
18290        #[doc = "Command data buffer 7\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18291        pub struct CmdDatabuf7Spec;
18292        impl crate::RegisterSpec for CmdDatabuf7Spec {
18293            type Ux = u32;
18294        }
18295        #[doc = "`read()` method returns [`cmd_databuf_7::R`](R) reader structure"]
18296        impl crate::Readable for CmdDatabuf7Spec {}
18297        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_7::W`](W) writer structure"]
18298        impl crate::Writable for CmdDatabuf7Spec {
18299            type Safety = crate::Unsafe;
18300        }
18301        #[doc = "`reset()` method sets CMD_DATABUF_7 to value 0"]
18302        impl crate::Resettable for CmdDatabuf7Spec {}
18303    }
18304    #[doc = "CMD_DATABUF_8 (rw) register accessor: Command data buffer 8\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_8`] module"]
18305    #[doc(alias = "CMD_DATABUF_8")]
18306    pub type CmdDatabuf8 = crate::Reg<cmd_databuf_8::CmdDatabuf8Spec>;
18307    #[doc = "Command data buffer 8"]
18308    pub mod cmd_databuf_8 {
18309        #[doc = "Register `CMD_DATABUF_8` reader"]
18310        pub type R = crate::R<CmdDatabuf8Spec>;
18311        #[doc = "Register `CMD_DATABUF_8` writer"]
18312        pub type W = crate::W<CmdDatabuf8Spec>;
18313        #[doc = "Field `cmd_databuf_8` reader - Command data buffer 8"]
18314        pub type CmdDatabuf8R = crate::FieldReader<u32>;
18315        #[doc = "Field `cmd_databuf_8` writer - Command data buffer 8"]
18316        pub type CmdDatabuf8W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18317        impl R {
18318            #[doc = "Bits 0:31 - Command data buffer 8"]
18319            #[inline(always)]
18320            pub fn cmd_databuf_8(&self) -> CmdDatabuf8R {
18321                CmdDatabuf8R::new(self.bits)
18322            }
18323        }
18324        impl W {
18325            #[doc = "Bits 0:31 - Command data buffer 8"]
18326            #[inline(always)]
18327            pub fn cmd_databuf_8(&mut self) -> CmdDatabuf8W<'_, CmdDatabuf8Spec> {
18328                CmdDatabuf8W::new(self, 0)
18329            }
18330        }
18331        #[doc = "Command data buffer 8\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18332        pub struct CmdDatabuf8Spec;
18333        impl crate::RegisterSpec for CmdDatabuf8Spec {
18334            type Ux = u32;
18335        }
18336        #[doc = "`read()` method returns [`cmd_databuf_8::R`](R) reader structure"]
18337        impl crate::Readable for CmdDatabuf8Spec {}
18338        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_8::W`](W) writer structure"]
18339        impl crate::Writable for CmdDatabuf8Spec {
18340            type Safety = crate::Unsafe;
18341        }
18342        #[doc = "`reset()` method sets CMD_DATABUF_8 to value 0"]
18343        impl crate::Resettable for CmdDatabuf8Spec {}
18344    }
18345    #[doc = "CMD_DATABUF_9 (rw) register accessor: Command data buffer 9\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_9`] module"]
18346    #[doc(alias = "CMD_DATABUF_9")]
18347    pub type CmdDatabuf9 = crate::Reg<cmd_databuf_9::CmdDatabuf9Spec>;
18348    #[doc = "Command data buffer 9"]
18349    pub mod cmd_databuf_9 {
18350        #[doc = "Register `CMD_DATABUF_9` reader"]
18351        pub type R = crate::R<CmdDatabuf9Spec>;
18352        #[doc = "Register `CMD_DATABUF_9` writer"]
18353        pub type W = crate::W<CmdDatabuf9Spec>;
18354        #[doc = "Field `cmd_databuf_9` reader - Command data buffer 9"]
18355        pub type CmdDatabuf9R = crate::FieldReader<u32>;
18356        #[doc = "Field `cmd_databuf_9` writer - Command data buffer 9"]
18357        pub type CmdDatabuf9W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18358        impl R {
18359            #[doc = "Bits 0:31 - Command data buffer 9"]
18360            #[inline(always)]
18361            pub fn cmd_databuf_9(&self) -> CmdDatabuf9R {
18362                CmdDatabuf9R::new(self.bits)
18363            }
18364        }
18365        impl W {
18366            #[doc = "Bits 0:31 - Command data buffer 9"]
18367            #[inline(always)]
18368            pub fn cmd_databuf_9(&mut self) -> CmdDatabuf9W<'_, CmdDatabuf9Spec> {
18369                CmdDatabuf9W::new(self, 0)
18370            }
18371        }
18372        #[doc = "Command data buffer 9\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18373        pub struct CmdDatabuf9Spec;
18374        impl crate::RegisterSpec for CmdDatabuf9Spec {
18375            type Ux = u32;
18376        }
18377        #[doc = "`read()` method returns [`cmd_databuf_9::R`](R) reader structure"]
18378        impl crate::Readable for CmdDatabuf9Spec {}
18379        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_9::W`](W) writer structure"]
18380        impl crate::Writable for CmdDatabuf9Spec {
18381            type Safety = crate::Unsafe;
18382        }
18383        #[doc = "`reset()` method sets CMD_DATABUF_9 to value 0"]
18384        impl crate::Resettable for CmdDatabuf9Spec {}
18385    }
18386    #[doc = "CMD_DATABUF_10 (rw) register accessor: Command data buffer 10\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_10`] module"]
18387    #[doc(alias = "CMD_DATABUF_10")]
18388    pub type CmdDatabuf10 = crate::Reg<cmd_databuf_10::CmdDatabuf10Spec>;
18389    #[doc = "Command data buffer 10"]
18390    pub mod cmd_databuf_10 {
18391        #[doc = "Register `CMD_DATABUF_10` reader"]
18392        pub type R = crate::R<CmdDatabuf10Spec>;
18393        #[doc = "Register `CMD_DATABUF_10` writer"]
18394        pub type W = crate::W<CmdDatabuf10Spec>;
18395        #[doc = "Field `cmd_databuf_10` reader - Command data buffer 10"]
18396        pub type CmdDatabuf10R = crate::FieldReader<u32>;
18397        #[doc = "Field `cmd_databuf_10` writer - Command data buffer 10"]
18398        pub type CmdDatabuf10W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18399        impl R {
18400            #[doc = "Bits 0:31 - Command data buffer 10"]
18401            #[inline(always)]
18402            pub fn cmd_databuf_10(&self) -> CmdDatabuf10R {
18403                CmdDatabuf10R::new(self.bits)
18404            }
18405        }
18406        impl W {
18407            #[doc = "Bits 0:31 - Command data buffer 10"]
18408            #[inline(always)]
18409            pub fn cmd_databuf_10(&mut self) -> CmdDatabuf10W<'_, CmdDatabuf10Spec> {
18410                CmdDatabuf10W::new(self, 0)
18411            }
18412        }
18413        #[doc = "Command data buffer 10\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18414        pub struct CmdDatabuf10Spec;
18415        impl crate::RegisterSpec for CmdDatabuf10Spec {
18416            type Ux = u32;
18417        }
18418        #[doc = "`read()` method returns [`cmd_databuf_10::R`](R) reader structure"]
18419        impl crate::Readable for CmdDatabuf10Spec {}
18420        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_10::W`](W) writer structure"]
18421        impl crate::Writable for CmdDatabuf10Spec {
18422            type Safety = crate::Unsafe;
18423        }
18424        #[doc = "`reset()` method sets CMD_DATABUF_10 to value 0"]
18425        impl crate::Resettable for CmdDatabuf10Spec {}
18426    }
18427    #[doc = "CMD_DATABUF_11 (rw) register accessor: Command data buffer 11\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_11`] module"]
18428    #[doc(alias = "CMD_DATABUF_11")]
18429    pub type CmdDatabuf11 = crate::Reg<cmd_databuf_11::CmdDatabuf11Spec>;
18430    #[doc = "Command data buffer 11"]
18431    pub mod cmd_databuf_11 {
18432        #[doc = "Register `CMD_DATABUF_11` reader"]
18433        pub type R = crate::R<CmdDatabuf11Spec>;
18434        #[doc = "Register `CMD_DATABUF_11` writer"]
18435        pub type W = crate::W<CmdDatabuf11Spec>;
18436        #[doc = "Field `cmd_databuf_11` reader - Command data buffer 11"]
18437        pub type CmdDatabuf11R = crate::FieldReader<u32>;
18438        #[doc = "Field `cmd_databuf_11` writer - Command data buffer 11"]
18439        pub type CmdDatabuf11W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18440        impl R {
18441            #[doc = "Bits 0:31 - Command data buffer 11"]
18442            #[inline(always)]
18443            pub fn cmd_databuf_11(&self) -> CmdDatabuf11R {
18444                CmdDatabuf11R::new(self.bits)
18445            }
18446        }
18447        impl W {
18448            #[doc = "Bits 0:31 - Command data buffer 11"]
18449            #[inline(always)]
18450            pub fn cmd_databuf_11(&mut self) -> CmdDatabuf11W<'_, CmdDatabuf11Spec> {
18451                CmdDatabuf11W::new(self, 0)
18452            }
18453        }
18454        #[doc = "Command data buffer 11\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18455        pub struct CmdDatabuf11Spec;
18456        impl crate::RegisterSpec for CmdDatabuf11Spec {
18457            type Ux = u32;
18458        }
18459        #[doc = "`read()` method returns [`cmd_databuf_11::R`](R) reader structure"]
18460        impl crate::Readable for CmdDatabuf11Spec {}
18461        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_11::W`](W) writer structure"]
18462        impl crate::Writable for CmdDatabuf11Spec {
18463            type Safety = crate::Unsafe;
18464        }
18465        #[doc = "`reset()` method sets CMD_DATABUF_11 to value 0"]
18466        impl crate::Resettable for CmdDatabuf11Spec {}
18467    }
18468    #[doc = "CMD_DATABUF_12 (rw) register accessor: Command data buffer 12\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_12`] module"]
18469    #[doc(alias = "CMD_DATABUF_12")]
18470    pub type CmdDatabuf12 = crate::Reg<cmd_databuf_12::CmdDatabuf12Spec>;
18471    #[doc = "Command data buffer 12"]
18472    pub mod cmd_databuf_12 {
18473        #[doc = "Register `CMD_DATABUF_12` reader"]
18474        pub type R = crate::R<CmdDatabuf12Spec>;
18475        #[doc = "Register `CMD_DATABUF_12` writer"]
18476        pub type W = crate::W<CmdDatabuf12Spec>;
18477        #[doc = "Field `cmd_databuf_12` reader - Command data buffer 12"]
18478        pub type CmdDatabuf12R = crate::FieldReader<u32>;
18479        #[doc = "Field `cmd_databuf_12` writer - Command data buffer 12"]
18480        pub type CmdDatabuf12W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18481        impl R {
18482            #[doc = "Bits 0:31 - Command data buffer 12"]
18483            #[inline(always)]
18484            pub fn cmd_databuf_12(&self) -> CmdDatabuf12R {
18485                CmdDatabuf12R::new(self.bits)
18486            }
18487        }
18488        impl W {
18489            #[doc = "Bits 0:31 - Command data buffer 12"]
18490            #[inline(always)]
18491            pub fn cmd_databuf_12(&mut self) -> CmdDatabuf12W<'_, CmdDatabuf12Spec> {
18492                CmdDatabuf12W::new(self, 0)
18493            }
18494        }
18495        #[doc = "Command data buffer 12\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18496        pub struct CmdDatabuf12Spec;
18497        impl crate::RegisterSpec for CmdDatabuf12Spec {
18498            type Ux = u32;
18499        }
18500        #[doc = "`read()` method returns [`cmd_databuf_12::R`](R) reader structure"]
18501        impl crate::Readable for CmdDatabuf12Spec {}
18502        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_12::W`](W) writer structure"]
18503        impl crate::Writable for CmdDatabuf12Spec {
18504            type Safety = crate::Unsafe;
18505        }
18506        #[doc = "`reset()` method sets CMD_DATABUF_12 to value 0"]
18507        impl crate::Resettable for CmdDatabuf12Spec {}
18508    }
18509    #[doc = "CMD_DATABUF_13 (rw) register accessor: Command data buffer 13\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_13`] module"]
18510    #[doc(alias = "CMD_DATABUF_13")]
18511    pub type CmdDatabuf13 = crate::Reg<cmd_databuf_13::CmdDatabuf13Spec>;
18512    #[doc = "Command data buffer 13"]
18513    pub mod cmd_databuf_13 {
18514        #[doc = "Register `CMD_DATABUF_13` reader"]
18515        pub type R = crate::R<CmdDatabuf13Spec>;
18516        #[doc = "Register `CMD_DATABUF_13` writer"]
18517        pub type W = crate::W<CmdDatabuf13Spec>;
18518        #[doc = "Field `cmd_databuf_13` reader - Command data buffer 13"]
18519        pub type CmdDatabuf13R = crate::FieldReader<u32>;
18520        #[doc = "Field `cmd_databuf_13` writer - Command data buffer 13"]
18521        pub type CmdDatabuf13W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18522        impl R {
18523            #[doc = "Bits 0:31 - Command data buffer 13"]
18524            #[inline(always)]
18525            pub fn cmd_databuf_13(&self) -> CmdDatabuf13R {
18526                CmdDatabuf13R::new(self.bits)
18527            }
18528        }
18529        impl W {
18530            #[doc = "Bits 0:31 - Command data buffer 13"]
18531            #[inline(always)]
18532            pub fn cmd_databuf_13(&mut self) -> CmdDatabuf13W<'_, CmdDatabuf13Spec> {
18533                CmdDatabuf13W::new(self, 0)
18534            }
18535        }
18536        #[doc = "Command data buffer 13\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18537        pub struct CmdDatabuf13Spec;
18538        impl crate::RegisterSpec for CmdDatabuf13Spec {
18539            type Ux = u32;
18540        }
18541        #[doc = "`read()` method returns [`cmd_databuf_13::R`](R) reader structure"]
18542        impl crate::Readable for CmdDatabuf13Spec {}
18543        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_13::W`](W) writer structure"]
18544        impl crate::Writable for CmdDatabuf13Spec {
18545            type Safety = crate::Unsafe;
18546        }
18547        #[doc = "`reset()` method sets CMD_DATABUF_13 to value 0"]
18548        impl crate::Resettable for CmdDatabuf13Spec {}
18549    }
18550    #[doc = "CMD_DATABUF_14 (rw) register accessor: Command data buffer 14\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_14`] module"]
18551    #[doc(alias = "CMD_DATABUF_14")]
18552    pub type CmdDatabuf14 = crate::Reg<cmd_databuf_14::CmdDatabuf14Spec>;
18553    #[doc = "Command data buffer 14"]
18554    pub mod cmd_databuf_14 {
18555        #[doc = "Register `CMD_DATABUF_14` reader"]
18556        pub type R = crate::R<CmdDatabuf14Spec>;
18557        #[doc = "Register `CMD_DATABUF_14` writer"]
18558        pub type W = crate::W<CmdDatabuf14Spec>;
18559        #[doc = "Field `cmd_databuf_14` reader - Command data buffer 14"]
18560        pub type CmdDatabuf14R = crate::FieldReader<u32>;
18561        #[doc = "Field `cmd_databuf_14` writer - Command data buffer 14"]
18562        pub type CmdDatabuf14W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18563        impl R {
18564            #[doc = "Bits 0:31 - Command data buffer 14"]
18565            #[inline(always)]
18566            pub fn cmd_databuf_14(&self) -> CmdDatabuf14R {
18567                CmdDatabuf14R::new(self.bits)
18568            }
18569        }
18570        impl W {
18571            #[doc = "Bits 0:31 - Command data buffer 14"]
18572            #[inline(always)]
18573            pub fn cmd_databuf_14(&mut self) -> CmdDatabuf14W<'_, CmdDatabuf14Spec> {
18574                CmdDatabuf14W::new(self, 0)
18575            }
18576        }
18577        #[doc = "Command data buffer 14\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18578        pub struct CmdDatabuf14Spec;
18579        impl crate::RegisterSpec for CmdDatabuf14Spec {
18580            type Ux = u32;
18581        }
18582        #[doc = "`read()` method returns [`cmd_databuf_14::R`](R) reader structure"]
18583        impl crate::Readable for CmdDatabuf14Spec {}
18584        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_14::W`](W) writer structure"]
18585        impl crate::Writable for CmdDatabuf14Spec {
18586            type Safety = crate::Unsafe;
18587        }
18588        #[doc = "`reset()` method sets CMD_DATABUF_14 to value 0"]
18589        impl crate::Resettable for CmdDatabuf14Spec {}
18590    }
18591    #[doc = "CMD_DATABUF_15 (rw) register accessor: Command data buffer 15\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_15`] module"]
18592    #[doc(alias = "CMD_DATABUF_15")]
18593    pub type CmdDatabuf15 = crate::Reg<cmd_databuf_15::CmdDatabuf15Spec>;
18594    #[doc = "Command data buffer 15"]
18595    pub mod cmd_databuf_15 {
18596        #[doc = "Register `CMD_DATABUF_15` reader"]
18597        pub type R = crate::R<CmdDatabuf15Spec>;
18598        #[doc = "Register `CMD_DATABUF_15` writer"]
18599        pub type W = crate::W<CmdDatabuf15Spec>;
18600        #[doc = "Field `cmd_databuf_15` reader - Command data buffer 15"]
18601        pub type CmdDatabuf15R = crate::FieldReader<u32>;
18602        #[doc = "Field `cmd_databuf_15` writer - Command data buffer 15"]
18603        pub type CmdDatabuf15W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
18604        impl R {
18605            #[doc = "Bits 0:31 - Command data buffer 15"]
18606            #[inline(always)]
18607            pub fn cmd_databuf_15(&self) -> CmdDatabuf15R {
18608                CmdDatabuf15R::new(self.bits)
18609            }
18610        }
18611        impl W {
18612            #[doc = "Bits 0:31 - Command data buffer 15"]
18613            #[inline(always)]
18614            pub fn cmd_databuf_15(&mut self) -> CmdDatabuf15W<'_, CmdDatabuf15Spec> {
18615                CmdDatabuf15W::new(self, 0)
18616            }
18617        }
18618        #[doc = "Command data buffer 15\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18619        pub struct CmdDatabuf15Spec;
18620        impl crate::RegisterSpec for CmdDatabuf15Spec {
18621            type Ux = u32;
18622        }
18623        #[doc = "`read()` method returns [`cmd_databuf_15::R`](R) reader structure"]
18624        impl crate::Readable for CmdDatabuf15Spec {}
18625        #[doc = "`write(|w| ..)` method takes [`cmd_databuf_15::W`](W) writer structure"]
18626        impl crate::Writable for CmdDatabuf15Spec {
18627            type Safety = crate::Unsafe;
18628        }
18629        #[doc = "`reset()` method sets CMD_DATABUF_15 to value 0"]
18630        impl crate::Resettable for CmdDatabuf15Spec {}
18631    }
18632}
18633#[doc = "SPI0 master/slave controller (SSI v151)"]
18634pub type Spi0 = crate::Periph<spi0::RegisterBlock, 0x4402_0000>;
18635impl core::fmt::Debug for Spi0 {
18636    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18637        f.debug_struct("Spi0").finish()
18638    }
18639}
18640#[doc = "SPI0 master/slave controller (SSI v151)"]
18641pub mod spi0 {
18642    #[repr(C)]
18643    #[doc = "Register block"]
18644    pub struct RegisterBlock {
18645        spi_er: SpiEr,
18646        spi_ctra: SpiCtra,
18647        spi_ctrb: SpiCtrb,
18648        spi_enhctl: SpiEnhctl,
18649        _reserved4: [u8; 0x04],
18650        spi_brs: SpiBrs,
18651        spi_dcr: SpiDcr,
18652        spi_drdl: SpiDrdl,
18653        spi_dtdl: SpiDtdl,
18654        _reserved8: [u8; 0x3c],
18655        spi_dr: SpiDr,
18656        _reserved9: [u8; 0x58],
18657        spi_rainsr: SpiRainsr,
18658        spi_insr: SpiInsr,
18659        spi_inmar: SpiInmar,
18660        spi_slenr: SpiSlenr,
18661        spi_twlr: SpiTwlr,
18662        spi_tlr: SpiTlr,
18663        _reserved15: [u8; 0x04],
18664        spi_rwlr: SpiRwlr,
18665        spi_rlr: SpiRlr,
18666        _reserved17: [u8; 0x04],
18667        spi_wsr: SpiWsr,
18668        _reserved18: [u8; 0x10],
18669        spi_icr: SpiIcr,
18670    }
18671    impl RegisterBlock {
18672        #[doc = "0x00 - SPI enable register"]
18673        #[inline(always)]
18674        pub const fn spi_er(&self) -> &SpiEr {
18675            &self.spi_er
18676        }
18677        #[doc = "0x04 - SPI control register 0"]
18678        #[inline(always)]
18679        pub const fn spi_ctra(&self) -> &SpiCtra {
18680            &self.spi_ctra
18681        }
18682        #[doc = "0x08 - SPI control register 1 (master only)"]
18683        #[inline(always)]
18684        pub const fn spi_ctrb(&self) -> &SpiCtrb {
18685            &self.spi_ctrb
18686        }
18687        #[doc = "0x0c - Enhanced control register (Dual/Quad/Octal)"]
18688        #[inline(always)]
18689        pub const fn spi_enhctl(&self) -> &SpiEnhctl {
18690            &self.spi_enhctl
18691        }
18692        #[doc = "0x14 - Baud rate select register"]
18693        #[inline(always)]
18694        pub const fn spi_brs(&self) -> &SpiBrs {
18695            &self.spi_brs
18696        }
18697        #[doc = "0x18 - DMA control register"]
18698        #[inline(always)]
18699        pub const fn spi_dcr(&self) -> &SpiDcr {
18700            &self.spi_dcr
18701        }
18702        #[doc = "0x1c - DMA RX data level"]
18703        #[inline(always)]
18704        pub const fn spi_drdl(&self) -> &SpiDrdl {
18705            &self.spi_drdl
18706        }
18707        #[doc = "0x20 - DMA TX data level"]
18708        #[inline(always)]
18709        pub const fn spi_dtdl(&self) -> &SpiDtdl {
18710            &self.spi_dtdl
18711        }
18712        #[doc = "0x60 - Data register (FIFO read/write)"]
18713        #[inline(always)]
18714        pub const fn spi_dr(&self) -> &SpiDr {
18715            &self.spi_dr
18716        }
18717        #[doc = "0xbc - Raw interrupt status register"]
18718        #[inline(always)]
18719        pub const fn spi_rainsr(&self) -> &SpiRainsr {
18720            &self.spi_rainsr
18721        }
18722        #[doc = "0xc0 - Interrupt status register (masked)"]
18723        #[inline(always)]
18724        pub const fn spi_insr(&self) -> &SpiInsr {
18725            &self.spi_insr
18726        }
18727        #[doc = "0xc4 - Interrupt mask register"]
18728        #[inline(always)]
18729        pub const fn spi_inmar(&self) -> &SpiInmar {
18730            &self.spi_inmar
18731        }
18732        #[doc = "0xc8 - Slave enable register (master only)"]
18733        #[inline(always)]
18734        pub const fn spi_slenr(&self) -> &SpiSlenr {
18735            &self.spi_slenr
18736        }
18737        #[doc = "0xcc - TX FIFO threshold level"]
18738        #[inline(always)]
18739        pub const fn spi_twlr(&self) -> &SpiTwlr {
18740            &self.spi_twlr
18741        }
18742        #[doc = "0xd0 - TX FIFO level register"]
18743        #[inline(always)]
18744        pub const fn spi_tlr(&self) -> &SpiTlr {
18745            &self.spi_tlr
18746        }
18747        #[doc = "0xd8 - RX FIFO threshold level"]
18748        #[inline(always)]
18749        pub const fn spi_rwlr(&self) -> &SpiRwlr {
18750            &self.spi_rwlr
18751        }
18752        #[doc = "0xdc - RX FIFO level register"]
18753        #[inline(always)]
18754        pub const fn spi_rlr(&self) -> &SpiRlr {
18755            &self.spi_rlr
18756        }
18757        #[doc = "0xe4 - Status register"]
18758        #[inline(always)]
18759        pub const fn spi_wsr(&self) -> &SpiWsr {
18760            &self.spi_wsr
18761        }
18762        #[doc = "0xf8 - Interrupt clear register"]
18763        #[inline(always)]
18764        pub const fn spi_icr(&self) -> &SpiIcr {
18765            &self.spi_icr
18766        }
18767    }
18768    #[doc = "SPI_ER (rw) register accessor: SPI enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_er::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_er::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_er`] module"]
18769    #[doc(alias = "SPI_ER")]
18770    pub type SpiEr = crate::Reg<spi_er::SpiErSpec>;
18771    #[doc = "SPI enable register"]
18772    pub mod spi_er {
18773        #[doc = "Register `SPI_ER` reader"]
18774        pub type R = crate::R<SpiErSpec>;
18775        #[doc = "Register `SPI_ER` writer"]
18776        pub type W = crate::W<SpiErSpec>;
18777        #[doc = "Field `spi_en` reader - SPI enable: 0=disabled; 1=enabled"]
18778        pub type SpiEnR = crate::BitReader;
18779        #[doc = "Field `spi_en` writer - SPI enable: 0=disabled; 1=enabled"]
18780        pub type SpiEnW<'a, REG> = crate::BitWriter<'a, REG>;
18781        impl R {
18782            #[doc = "Bit 0 - SPI enable: 0=disabled; 1=enabled"]
18783            #[inline(always)]
18784            pub fn spi_en(&self) -> SpiEnR {
18785                SpiEnR::new((self.bits & 1) != 0)
18786            }
18787        }
18788        impl W {
18789            #[doc = "Bit 0 - SPI enable: 0=disabled; 1=enabled"]
18790            #[inline(always)]
18791            pub fn spi_en(&mut self) -> SpiEnW<'_, SpiErSpec> {
18792                SpiEnW::new(self, 0)
18793            }
18794        }
18795        #[doc = "SPI enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_er::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_er::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18796        pub struct SpiErSpec;
18797        impl crate::RegisterSpec for SpiErSpec {
18798            type Ux = u32;
18799        }
18800        #[doc = "`read()` method returns [`spi_er::R`](R) reader structure"]
18801        impl crate::Readable for SpiErSpec {}
18802        #[doc = "`write(|w| ..)` method takes [`spi_er::W`](W) writer structure"]
18803        impl crate::Writable for SpiErSpec {
18804            type Safety = crate::Unsafe;
18805        }
18806        #[doc = "`reset()` method sets SPI_ER to value 0"]
18807        impl crate::Resettable for SpiErSpec {}
18808    }
18809    #[doc = "SPI_CTRA (rw) register accessor: SPI control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctra`] module"]
18810    #[doc(alias = "SPI_CTRA")]
18811    pub type SpiCtra = crate::Reg<spi_ctra::SpiCtraSpec>;
18812    #[doc = "SPI control register 0"]
18813    pub mod spi_ctra {
18814        #[doc = "Register `SPI_CTRA` reader"]
18815        pub type R = crate::R<SpiCtraSpec>;
18816        #[doc = "Register `SPI_CTRA` writer"]
18817        pub type W = crate::W<SpiCtraSpec>;
18818        #[doc = "Field `soe` reader - Shift register loop test: 0=normal; 1=loopback"]
18819        pub type SoeR = crate::BitReader;
18820        #[doc = "Field `soe` writer - Shift register loop test: 0=normal; 1=loopback"]
18821        pub type SoeW<'a, REG> = crate::BitWriter<'a, REG>;
18822        #[doc = "Clock phase: 0=first edge sample; 1=second edge sample\n\nValue on reset: 0"]
18823        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
18824        pub enum Scph {
18825            #[doc = "0: Sample on first clock edge"]
18826            FirstEdge = 0,
18827            #[doc = "1: Sample on second clock edge"]
18828            SecondEdge = 1,
18829        }
18830        impl From<Scph> for bool {
18831            #[inline(always)]
18832            fn from(variant: Scph) -> Self {
18833                variant as u8 != 0
18834            }
18835        }
18836        #[doc = "Field `scph` reader - Clock phase: 0=first edge sample; 1=second edge sample"]
18837        pub type ScphR = crate::BitReader<Scph>;
18838        impl ScphR {
18839            #[doc = "Get enumerated values variant"]
18840            #[inline(always)]
18841            pub const fn variant(&self) -> Scph {
18842                match self.bits {
18843                    false => Scph::FirstEdge,
18844                    true => Scph::SecondEdge,
18845                }
18846            }
18847            #[doc = "Sample on first clock edge"]
18848            #[inline(always)]
18849            pub fn is_first_edge(&self) -> bool {
18850                *self == Scph::FirstEdge
18851            }
18852            #[doc = "Sample on second clock edge"]
18853            #[inline(always)]
18854            pub fn is_second_edge(&self) -> bool {
18855                *self == Scph::SecondEdge
18856            }
18857        }
18858        #[doc = "Field `scph` writer - Clock phase: 0=first edge sample; 1=second edge sample"]
18859        pub type ScphW<'a, REG> = crate::BitWriter<'a, REG, Scph>;
18860        impl<'a, REG> ScphW<'a, REG>
18861        where
18862            REG: crate::Writable + crate::RegisterSpec,
18863        {
18864            #[doc = "Sample on first clock edge"]
18865            #[inline(always)]
18866            pub fn first_edge(self) -> &'a mut crate::W<REG> {
18867                self.variant(Scph::FirstEdge)
18868            }
18869            #[doc = "Sample on second clock edge"]
18870            #[inline(always)]
18871            pub fn second_edge(self) -> &'a mut crate::W<REG> {
18872                self.variant(Scph::SecondEdge)
18873            }
18874        }
18875        #[doc = "Clock polarity: 0=low idle; 1=high idle\n\nValue on reset: 0"]
18876        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
18877        pub enum Scpol {
18878            #[doc = "0: SCK idle low"]
18879            LowIdle = 0,
18880            #[doc = "1: SCK idle high"]
18881            HighIdle = 1,
18882        }
18883        impl From<Scpol> for bool {
18884            #[inline(always)]
18885            fn from(variant: Scpol) -> Self {
18886                variant as u8 != 0
18887            }
18888        }
18889        #[doc = "Field `scpol` reader - Clock polarity: 0=low idle; 1=high idle"]
18890        pub type ScpolR = crate::BitReader<Scpol>;
18891        impl ScpolR {
18892            #[doc = "Get enumerated values variant"]
18893            #[inline(always)]
18894            pub const fn variant(&self) -> Scpol {
18895                match self.bits {
18896                    false => Scpol::LowIdle,
18897                    true => Scpol::HighIdle,
18898                }
18899            }
18900            #[doc = "SCK idle low"]
18901            #[inline(always)]
18902            pub fn is_low_idle(&self) -> bool {
18903                *self == Scpol::LowIdle
18904            }
18905            #[doc = "SCK idle high"]
18906            #[inline(always)]
18907            pub fn is_high_idle(&self) -> bool {
18908                *self == Scpol::HighIdle
18909            }
18910        }
18911        #[doc = "Field `scpol` writer - Clock polarity: 0=low idle; 1=high idle"]
18912        pub type ScpolW<'a, REG> = crate::BitWriter<'a, REG, Scpol>;
18913        impl<'a, REG> ScpolW<'a, REG>
18914        where
18915            REG: crate::Writable + crate::RegisterSpec,
18916        {
18917            #[doc = "SCK idle low"]
18918            #[inline(always)]
18919            pub fn low_idle(self) -> &'a mut crate::W<REG> {
18920                self.variant(Scpol::LowIdle)
18921            }
18922            #[doc = "SCK idle high"]
18923            #[inline(always)]
18924            pub fn high_idle(self) -> &'a mut crate::W<REG> {
18925                self.variant(Scpol::HighIdle)
18926            }
18927        }
18928        #[doc = "Field `dfs32` reader - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
18929        pub type Dfs32R = crate::FieldReader;
18930        #[doc = "Field `dfs32` writer - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
18931        pub type Dfs32W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
18932        #[doc = "Transfer mode: 00=TX/RX; 01=TX only; 10=RX only\n\nValue on reset: 0"]
18933        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
18934        #[repr(u8)]
18935        pub enum Trsm {
18936            #[doc = "0: Transmit and Receive"]
18937            TxRx = 0,
18938            #[doc = "1: Transmit Only"]
18939            TxOnly = 1,
18940            #[doc = "2: Receive Only"]
18941            RxOnly = 2,
18942        }
18943        impl From<Trsm> for u8 {
18944            #[inline(always)]
18945            fn from(variant: Trsm) -> Self {
18946                variant as _
18947            }
18948        }
18949        impl crate::FieldSpec for Trsm {
18950            type Ux = u8;
18951        }
18952        impl crate::IsEnum for Trsm {}
18953        #[doc = "Field `trsm` reader - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
18954        pub type TrsmR = crate::FieldReader<Trsm>;
18955        impl TrsmR {
18956            #[doc = "Get enumerated values variant"]
18957            #[inline(always)]
18958            pub const fn variant(&self) -> Option<Trsm> {
18959                match self.bits {
18960                    0 => Some(Trsm::TxRx),
18961                    1 => Some(Trsm::TxOnly),
18962                    2 => Some(Trsm::RxOnly),
18963                    _ => None,
18964                }
18965            }
18966            #[doc = "Transmit and Receive"]
18967            #[inline(always)]
18968            pub fn is_tx_rx(&self) -> bool {
18969                *self == Trsm::TxRx
18970            }
18971            #[doc = "Transmit Only"]
18972            #[inline(always)]
18973            pub fn is_tx_only(&self) -> bool {
18974                *self == Trsm::TxOnly
18975            }
18976            #[doc = "Receive Only"]
18977            #[inline(always)]
18978            pub fn is_rx_only(&self) -> bool {
18979                *self == Trsm::RxOnly
18980            }
18981        }
18982        #[doc = "Field `trsm` writer - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
18983        pub type TrsmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trsm>;
18984        impl<'a, REG> TrsmW<'a, REG>
18985        where
18986            REG: crate::Writable + crate::RegisterSpec,
18987            REG::Ux: From<u8>,
18988        {
18989            #[doc = "Transmit and Receive"]
18990            #[inline(always)]
18991            pub fn tx_rx(self) -> &'a mut crate::W<REG> {
18992                self.variant(Trsm::TxRx)
18993            }
18994            #[doc = "Transmit Only"]
18995            #[inline(always)]
18996            pub fn tx_only(self) -> &'a mut crate::W<REG> {
18997                self.variant(Trsm::TxOnly)
18998            }
18999            #[doc = "Receive Only"]
19000            #[inline(always)]
19001            pub fn rx_only(self) -> &'a mut crate::W<REG> {
19002                self.variant(Trsm::RxOnly)
19003            }
19004        }
19005        impl R {
19006            #[doc = "Bit 0 - Shift register loop test: 0=normal; 1=loopback"]
19007            #[inline(always)]
19008            pub fn soe(&self) -> SoeR {
19009                SoeR::new((self.bits & 1) != 0)
19010            }
19011            #[doc = "Bit 3 - Clock phase: 0=first edge sample; 1=second edge sample"]
19012            #[inline(always)]
19013            pub fn scph(&self) -> ScphR {
19014                ScphR::new(((self.bits >> 3) & 1) != 0)
19015            }
19016            #[doc = "Bit 4 - Clock polarity: 0=low idle; 1=high idle"]
19017            #[inline(always)]
19018            pub fn scpol(&self) -> ScpolR {
19019                ScpolR::new(((self.bits >> 4) & 1) != 0)
19020            }
19021            #[doc = "Bits 13:17 - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
19022            #[inline(always)]
19023            pub fn dfs32(&self) -> Dfs32R {
19024                Dfs32R::new(((self.bits >> 13) & 0x1f) as u8)
19025            }
19026            #[doc = "Bits 18:19 - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
19027            #[inline(always)]
19028            pub fn trsm(&self) -> TrsmR {
19029                TrsmR::new(((self.bits >> 18) & 3) as u8)
19030            }
19031        }
19032        impl W {
19033            #[doc = "Bit 0 - Shift register loop test: 0=normal; 1=loopback"]
19034            #[inline(always)]
19035            pub fn soe(&mut self) -> SoeW<'_, SpiCtraSpec> {
19036                SoeW::new(self, 0)
19037            }
19038            #[doc = "Bit 3 - Clock phase: 0=first edge sample; 1=second edge sample"]
19039            #[inline(always)]
19040            pub fn scph(&mut self) -> ScphW<'_, SpiCtraSpec> {
19041                ScphW::new(self, 3)
19042            }
19043            #[doc = "Bit 4 - Clock polarity: 0=low idle; 1=high idle"]
19044            #[inline(always)]
19045            pub fn scpol(&mut self) -> ScpolW<'_, SpiCtraSpec> {
19046                ScpolW::new(self, 4)
19047            }
19048            #[doc = "Bits 13:17 - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
19049            #[inline(always)]
19050            pub fn dfs32(&mut self) -> Dfs32W<'_, SpiCtraSpec> {
19051                Dfs32W::new(self, 13)
19052            }
19053            #[doc = "Bits 18:19 - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
19054            #[inline(always)]
19055            pub fn trsm(&mut self) -> TrsmW<'_, SpiCtraSpec> {
19056                TrsmW::new(self, 18)
19057            }
19058        }
19059        #[doc = "SPI control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19060        pub struct SpiCtraSpec;
19061        impl crate::RegisterSpec for SpiCtraSpec {
19062            type Ux = u32;
19063        }
19064        #[doc = "`read()` method returns [`spi_ctra::R`](R) reader structure"]
19065        impl crate::Readable for SpiCtraSpec {}
19066        #[doc = "`write(|w| ..)` method takes [`spi_ctra::W`](W) writer structure"]
19067        impl crate::Writable for SpiCtraSpec {
19068            type Safety = crate::Unsafe;
19069        }
19070        #[doc = "`reset()` method sets SPI_CTRA to value 0"]
19071        impl crate::Resettable for SpiCtraSpec {}
19072    }
19073    #[doc = "SPI_CTRB (rw) register accessor: SPI control register 1 (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrb`] module"]
19074    #[doc(alias = "SPI_CTRB")]
19075    pub type SpiCtrb = crate::Reg<spi_ctrb::SpiCtrbSpec>;
19076    #[doc = "SPI control register 1 (master only)"]
19077    pub mod spi_ctrb {
19078        #[doc = "Register `SPI_CTRB` reader"]
19079        pub type R = crate::R<SpiCtrbSpec>;
19080        #[doc = "Register `SPI_CTRB` writer"]
19081        pub type W = crate::W<SpiCtrbSpec>;
19082        #[doc = "Field `ndf` reader - Number of data frames (master TX only mode)"]
19083        pub type NdfR = crate::FieldReader<u16>;
19084        #[doc = "Field `ndf` writer - Number of data frames (master TX only mode)"]
19085        pub type NdfW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
19086        #[doc = "Field `ssi_clk_stretch_en` reader - Clock stretch enable"]
19087        pub type SsiClkStretchEnR = crate::BitReader;
19088        #[doc = "Field `ssi_clk_stretch_en` writer - Clock stretch enable"]
19089        pub type SsiClkStretchEnW<'a, REG> = crate::BitWriter<'a, REG>;
19090        impl R {
19091            #[doc = "Bits 0:15 - Number of data frames (master TX only mode)"]
19092            #[inline(always)]
19093            pub fn ndf(&self) -> NdfR {
19094                NdfR::new((self.bits & 0xffff) as u16)
19095            }
19096            #[doc = "Bit 27 - Clock stretch enable"]
19097            #[inline(always)]
19098            pub fn ssi_clk_stretch_en(&self) -> SsiClkStretchEnR {
19099                SsiClkStretchEnR::new(((self.bits >> 27) & 1) != 0)
19100            }
19101        }
19102        impl W {
19103            #[doc = "Bits 0:15 - Number of data frames (master TX only mode)"]
19104            #[inline(always)]
19105            pub fn ndf(&mut self) -> NdfW<'_, SpiCtrbSpec> {
19106                NdfW::new(self, 0)
19107            }
19108            #[doc = "Bit 27 - Clock stretch enable"]
19109            #[inline(always)]
19110            pub fn ssi_clk_stretch_en(&mut self) -> SsiClkStretchEnW<'_, SpiCtrbSpec> {
19111                SsiClkStretchEnW::new(self, 27)
19112            }
19113        }
19114        #[doc = "SPI control register 1 (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19115        pub struct SpiCtrbSpec;
19116        impl crate::RegisterSpec for SpiCtrbSpec {
19117            type Ux = u32;
19118        }
19119        #[doc = "`read()` method returns [`spi_ctrb::R`](R) reader structure"]
19120        impl crate::Readable for SpiCtrbSpec {}
19121        #[doc = "`write(|w| ..)` method takes [`spi_ctrb::W`](W) writer structure"]
19122        impl crate::Writable for SpiCtrbSpec {
19123            type Safety = crate::Unsafe;
19124        }
19125        #[doc = "`reset()` method sets SPI_CTRB to value 0"]
19126        impl crate::Resettable for SpiCtrbSpec {}
19127    }
19128    #[doc = "SPI_ENHCTL (rw) register accessor: Enhanced control register (Dual/Quad/Octal)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_enhctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_enhctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_enhctl`] module"]
19129    #[doc(alias = "SPI_ENHCTL")]
19130    pub type SpiEnhctl = crate::Reg<spi_enhctl::SpiEnhctlSpec>;
19131    #[doc = "Enhanced control register (Dual/Quad/Octal)"]
19132    pub mod spi_enhctl {
19133        #[doc = "Register `SPI_ENHCTL` reader"]
19134        pub type R = crate::R<SpiEnhctlSpec>;
19135        #[doc = "Register `SPI_ENHCTL` writer"]
19136        pub type W = crate::W<SpiEnhctlSpec>;
19137        #[doc = "Field `spi_dual_en` reader - Dual SPI mode enable"]
19138        pub type SpiDualEnR = crate::BitReader;
19139        #[doc = "Field `spi_dual_en` writer - Dual SPI mode enable"]
19140        pub type SpiDualEnW<'a, REG> = crate::BitWriter<'a, REG>;
19141        #[doc = "Field `spi_quad_en` reader - Quad SPI mode enable"]
19142        pub type SpiQuadEnR = crate::BitReader;
19143        #[doc = "Field `spi_quad_en` writer - Quad SPI mode enable"]
19144        pub type SpiQuadEnW<'a, REG> = crate::BitWriter<'a, REG>;
19145        #[doc = "Field `spi_oct_en` reader - Octal SPI mode enable"]
19146        pub type SpiOctEnR = crate::BitReader;
19147        #[doc = "Field `spi_oct_en` writer - Octal SPI mode enable"]
19148        pub type SpiOctEnW<'a, REG> = crate::BitWriter<'a, REG>;
19149        impl R {
19150            #[doc = "Bit 0 - Dual SPI mode enable"]
19151            #[inline(always)]
19152            pub fn spi_dual_en(&self) -> SpiDualEnR {
19153                SpiDualEnR::new((self.bits & 1) != 0)
19154            }
19155            #[doc = "Bit 1 - Quad SPI mode enable"]
19156            #[inline(always)]
19157            pub fn spi_quad_en(&self) -> SpiQuadEnR {
19158                SpiQuadEnR::new(((self.bits >> 1) & 1) != 0)
19159            }
19160            #[doc = "Bit 2 - Octal SPI mode enable"]
19161            #[inline(always)]
19162            pub fn spi_oct_en(&self) -> SpiOctEnR {
19163                SpiOctEnR::new(((self.bits >> 2) & 1) != 0)
19164            }
19165        }
19166        impl W {
19167            #[doc = "Bit 0 - Dual SPI mode enable"]
19168            #[inline(always)]
19169            pub fn spi_dual_en(&mut self) -> SpiDualEnW<'_, SpiEnhctlSpec> {
19170                SpiDualEnW::new(self, 0)
19171            }
19172            #[doc = "Bit 1 - Quad SPI mode enable"]
19173            #[inline(always)]
19174            pub fn spi_quad_en(&mut self) -> SpiQuadEnW<'_, SpiEnhctlSpec> {
19175                SpiQuadEnW::new(self, 1)
19176            }
19177            #[doc = "Bit 2 - Octal SPI mode enable"]
19178            #[inline(always)]
19179            pub fn spi_oct_en(&mut self) -> SpiOctEnW<'_, SpiEnhctlSpec> {
19180                SpiOctEnW::new(self, 2)
19181            }
19182        }
19183        #[doc = "Enhanced control register (Dual/Quad/Octal)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_enhctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_enhctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19184        pub struct SpiEnhctlSpec;
19185        impl crate::RegisterSpec for SpiEnhctlSpec {
19186            type Ux = u32;
19187        }
19188        #[doc = "`read()` method returns [`spi_enhctl::R`](R) reader structure"]
19189        impl crate::Readable for SpiEnhctlSpec {}
19190        #[doc = "`write(|w| ..)` method takes [`spi_enhctl::W`](W) writer structure"]
19191        impl crate::Writable for SpiEnhctlSpec {
19192            type Safety = crate::Unsafe;
19193        }
19194        #[doc = "`reset()` method sets SPI_ENHCTL to value 0"]
19195        impl crate::Resettable for SpiEnhctlSpec {}
19196    }
19197    #[doc = "SPI_BRS (rw) register accessor: Baud rate select register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_brs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_brs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_brs`] module"]
19198    #[doc(alias = "SPI_BRS")]
19199    pub type SpiBrs = crate::Reg<spi_brs::SpiBrsSpec>;
19200    #[doc = "Baud rate select register"]
19201    pub mod spi_brs {
19202        #[doc = "Register `SPI_BRS` reader"]
19203        pub type R = crate::R<SpiBrsSpec>;
19204        #[doc = "Register `SPI_BRS` writer"]
19205        pub type W = crate::W<SpiBrsSpec>;
19206        #[doc = "Field `clk_div` reader - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
19207        pub type ClkDivR = crate::FieldReader<u16>;
19208        #[doc = "Field `clk_div` writer - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
19209        pub type ClkDivW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
19210        impl R {
19211            #[doc = "Bits 0:15 - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
19212            #[inline(always)]
19213            pub fn clk_div(&self) -> ClkDivR {
19214                ClkDivR::new((self.bits & 0xffff) as u16)
19215            }
19216        }
19217        impl W {
19218            #[doc = "Bits 0:15 - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
19219            #[inline(always)]
19220            pub fn clk_div(&mut self) -> ClkDivW<'_, SpiBrsSpec> {
19221                ClkDivW::new(self, 0)
19222            }
19223        }
19224        #[doc = "Baud rate select register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_brs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_brs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19225        pub struct SpiBrsSpec;
19226        impl crate::RegisterSpec for SpiBrsSpec {
19227            type Ux = u32;
19228        }
19229        #[doc = "`read()` method returns [`spi_brs::R`](R) reader structure"]
19230        impl crate::Readable for SpiBrsSpec {}
19231        #[doc = "`write(|w| ..)` method takes [`spi_brs::W`](W) writer structure"]
19232        impl crate::Writable for SpiBrsSpec {
19233            type Safety = crate::Unsafe;
19234        }
19235        #[doc = "`reset()` method sets SPI_BRS to value 0"]
19236        impl crate::Resettable for SpiBrsSpec {}
19237    }
19238    #[doc = "SPI_DCR (rw) register accessor: DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dcr`] module"]
19239    #[doc(alias = "SPI_DCR")]
19240    pub type SpiDcr = crate::Reg<spi_dcr::SpiDcrSpec>;
19241    #[doc = "DMA control register"]
19242    pub mod spi_dcr {
19243        #[doc = "Register `SPI_DCR` reader"]
19244        pub type R = crate::R<SpiDcrSpec>;
19245        #[doc = "Register `SPI_DCR` writer"]
19246        pub type W = crate::W<SpiDcrSpec>;
19247        #[doc = "Field `tdmae` reader - TX DMA enable"]
19248        pub type TdmaeR = crate::BitReader;
19249        #[doc = "Field `tdmae` writer - TX DMA enable"]
19250        pub type TdmaeW<'a, REG> = crate::BitWriter<'a, REG>;
19251        #[doc = "Field `rdmae` reader - RX DMA enable"]
19252        pub type RdmaeR = crate::BitReader;
19253        #[doc = "Field `rdmae` writer - RX DMA enable"]
19254        pub type RdmaeW<'a, REG> = crate::BitWriter<'a, REG>;
19255        impl R {
19256            #[doc = "Bit 0 - TX DMA enable"]
19257            #[inline(always)]
19258            pub fn tdmae(&self) -> TdmaeR {
19259                TdmaeR::new((self.bits & 1) != 0)
19260            }
19261            #[doc = "Bit 1 - RX DMA enable"]
19262            #[inline(always)]
19263            pub fn rdmae(&self) -> RdmaeR {
19264                RdmaeR::new(((self.bits >> 1) & 1) != 0)
19265            }
19266        }
19267        impl W {
19268            #[doc = "Bit 0 - TX DMA enable"]
19269            #[inline(always)]
19270            pub fn tdmae(&mut self) -> TdmaeW<'_, SpiDcrSpec> {
19271                TdmaeW::new(self, 0)
19272            }
19273            #[doc = "Bit 1 - RX DMA enable"]
19274            #[inline(always)]
19275            pub fn rdmae(&mut self) -> RdmaeW<'_, SpiDcrSpec> {
19276                RdmaeW::new(self, 1)
19277            }
19278        }
19279        #[doc = "DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19280        pub struct SpiDcrSpec;
19281        impl crate::RegisterSpec for SpiDcrSpec {
19282            type Ux = u32;
19283        }
19284        #[doc = "`read()` method returns [`spi_dcr::R`](R) reader structure"]
19285        impl crate::Readable for SpiDcrSpec {}
19286        #[doc = "`write(|w| ..)` method takes [`spi_dcr::W`](W) writer structure"]
19287        impl crate::Writable for SpiDcrSpec {
19288            type Safety = crate::Unsafe;
19289        }
19290        #[doc = "`reset()` method sets SPI_DCR to value 0"]
19291        impl crate::Resettable for SpiDcrSpec {}
19292    }
19293    #[doc = "SPI_DRDL (rw) register accessor: DMA RX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_drdl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_drdl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_drdl`] module"]
19294    #[doc(alias = "SPI_DRDL")]
19295    pub type SpiDrdl = crate::Reg<spi_drdl::SpiDrdlSpec>;
19296    #[doc = "DMA RX data level"]
19297    pub mod spi_drdl {
19298        #[doc = "Register `SPI_DRDL` reader"]
19299        pub type R = crate::R<SpiDrdlSpec>;
19300        #[doc = "Register `SPI_DRDL` writer"]
19301        pub type W = crate::W<SpiDrdlSpec>;
19302        #[doc = "Field `dma_rx_data_level` reader - DMA RX FIFO threshold"]
19303        pub type DmaRxDataLevelR = crate::FieldReader;
19304        #[doc = "Field `dma_rx_data_level` writer - DMA RX FIFO threshold"]
19305        pub type DmaRxDataLevelW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
19306        impl R {
19307            #[doc = "Bits 0:7 - DMA RX FIFO threshold"]
19308            #[inline(always)]
19309            pub fn dma_rx_data_level(&self) -> DmaRxDataLevelR {
19310                DmaRxDataLevelR::new((self.bits & 0xff) as u8)
19311            }
19312        }
19313        impl W {
19314            #[doc = "Bits 0:7 - DMA RX FIFO threshold"]
19315            #[inline(always)]
19316            pub fn dma_rx_data_level(&mut self) -> DmaRxDataLevelW<'_, SpiDrdlSpec> {
19317                DmaRxDataLevelW::new(self, 0)
19318            }
19319        }
19320        #[doc = "DMA RX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_drdl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_drdl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19321        pub struct SpiDrdlSpec;
19322        impl crate::RegisterSpec for SpiDrdlSpec {
19323            type Ux = u32;
19324        }
19325        #[doc = "`read()` method returns [`spi_drdl::R`](R) reader structure"]
19326        impl crate::Readable for SpiDrdlSpec {}
19327        #[doc = "`write(|w| ..)` method takes [`spi_drdl::W`](W) writer structure"]
19328        impl crate::Writable for SpiDrdlSpec {
19329            type Safety = crate::Unsafe;
19330        }
19331        #[doc = "`reset()` method sets SPI_DRDL to value 0"]
19332        impl crate::Resettable for SpiDrdlSpec {}
19333    }
19334    #[doc = "SPI_DTDL (rw) register accessor: DMA TX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dtdl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dtdl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dtdl`] module"]
19335    #[doc(alias = "SPI_DTDL")]
19336    pub type SpiDtdl = crate::Reg<spi_dtdl::SpiDtdlSpec>;
19337    #[doc = "DMA TX data level"]
19338    pub mod spi_dtdl {
19339        #[doc = "Register `SPI_DTDL` reader"]
19340        pub type R = crate::R<SpiDtdlSpec>;
19341        #[doc = "Register `SPI_DTDL` writer"]
19342        pub type W = crate::W<SpiDtdlSpec>;
19343        #[doc = "Field `dma_tx_data_level` reader - DMA TX FIFO threshold"]
19344        pub type DmaTxDataLevelR = crate::FieldReader;
19345        #[doc = "Field `dma_tx_data_level` writer - DMA TX FIFO threshold"]
19346        pub type DmaTxDataLevelW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
19347        impl R {
19348            #[doc = "Bits 0:7 - DMA TX FIFO threshold"]
19349            #[inline(always)]
19350            pub fn dma_tx_data_level(&self) -> DmaTxDataLevelR {
19351                DmaTxDataLevelR::new((self.bits & 0xff) as u8)
19352            }
19353        }
19354        impl W {
19355            #[doc = "Bits 0:7 - DMA TX FIFO threshold"]
19356            #[inline(always)]
19357            pub fn dma_tx_data_level(&mut self) -> DmaTxDataLevelW<'_, SpiDtdlSpec> {
19358                DmaTxDataLevelW::new(self, 0)
19359            }
19360        }
19361        #[doc = "DMA TX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dtdl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dtdl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19362        pub struct SpiDtdlSpec;
19363        impl crate::RegisterSpec for SpiDtdlSpec {
19364            type Ux = u32;
19365        }
19366        #[doc = "`read()` method returns [`spi_dtdl::R`](R) reader structure"]
19367        impl crate::Readable for SpiDtdlSpec {}
19368        #[doc = "`write(|w| ..)` method takes [`spi_dtdl::W`](W) writer structure"]
19369        impl crate::Writable for SpiDtdlSpec {
19370            type Safety = crate::Unsafe;
19371        }
19372        #[doc = "`reset()` method sets SPI_DTDL to value 0"]
19373        impl crate::Resettable for SpiDtdlSpec {}
19374    }
19375    #[doc = "SPI_DR (rw) register accessor: Data register (FIFO read/write)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dr`] module"]
19376    #[doc(alias = "SPI_DR")]
19377    pub type SpiDr = crate::Reg<spi_dr::SpiDrSpec>;
19378    #[doc = "Data register (FIFO read/write)"]
19379    pub mod spi_dr {
19380        #[doc = "Register `SPI_DR` reader"]
19381        pub type R = crate::R<SpiDrSpec>;
19382        #[doc = "Register `SPI_DR` writer"]
19383        pub type W = crate::W<SpiDrSpec>;
19384        #[doc = "Field `dr` reader - Write: push to TX FIFO; Read: pop from RX FIFO"]
19385        pub type DrR = crate::FieldReader<u32>;
19386        #[doc = "Field `dr` writer - Write: push to TX FIFO; Read: pop from RX FIFO"]
19387        pub type DrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
19388        impl R {
19389            #[doc = "Bits 0:31 - Write: push to TX FIFO; Read: pop from RX FIFO"]
19390            #[inline(always)]
19391            pub fn dr(&self) -> DrR {
19392                DrR::new(self.bits)
19393            }
19394        }
19395        impl W {
19396            #[doc = "Bits 0:31 - Write: push to TX FIFO; Read: pop from RX FIFO"]
19397            #[inline(always)]
19398            pub fn dr(&mut self) -> DrW<'_, SpiDrSpec> {
19399                DrW::new(self, 0)
19400            }
19401        }
19402        #[doc = "Data register (FIFO read/write)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19403        pub struct SpiDrSpec;
19404        impl crate::RegisterSpec for SpiDrSpec {
19405            type Ux = u32;
19406        }
19407        #[doc = "`read()` method returns [`spi_dr::R`](R) reader structure"]
19408        impl crate::Readable for SpiDrSpec {}
19409        #[doc = "`write(|w| ..)` method takes [`spi_dr::W`](W) writer structure"]
19410        impl crate::Writable for SpiDrSpec {
19411            type Safety = crate::Unsafe;
19412        }
19413        #[doc = "`reset()` method sets SPI_DR to value 0"]
19414        impl crate::Resettable for SpiDrSpec {}
19415    }
19416    #[doc = "SPI_RAINSR (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rainsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rainsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rainsr`] module"]
19417    #[doc(alias = "SPI_RAINSR")]
19418    pub type SpiRainsr = crate::Reg<spi_rainsr::SpiRainsrSpec>;
19419    #[doc = "Raw interrupt status register"]
19420    pub mod spi_rainsr {
19421        #[doc = "Register `SPI_RAINSR` reader"]
19422        pub type R = crate::R<SpiRainsrSpec>;
19423        #[doc = "Register `SPI_RAINSR` writer"]
19424        pub type W = crate::W<SpiRainsrSpec>;
19425        #[doc = "Field `txe_irq` reader - TX FIFO empty raw status"]
19426        pub type TxeIrqR = crate::BitReader;
19427        #[doc = "Field `txo_irq` reader - TX FIFO overflow raw status"]
19428        pub type TxoIrqR = crate::BitReader;
19429        #[doc = "Field `rxu_irq` reader - RX FIFO underflow raw status"]
19430        pub type RxuIrqR = crate::BitReader;
19431        #[doc = "Field `rxo_irq` reader - RX FIFO overflow raw status"]
19432        pub type RxoIrqR = crate::BitReader;
19433        #[doc = "Field `rxf_irq` reader - RX FIFO full raw status"]
19434        pub type RxfIrqR = crate::BitReader;
19435        #[doc = "Field `mst_irq` reader - Multi-master contention raw status"]
19436        pub type MstIrqR = crate::BitReader;
19437        impl R {
19438            #[doc = "Bit 0 - TX FIFO empty raw status"]
19439            #[inline(always)]
19440            pub fn txe_irq(&self) -> TxeIrqR {
19441                TxeIrqR::new((self.bits & 1) != 0)
19442            }
19443            #[doc = "Bit 1 - TX FIFO overflow raw status"]
19444            #[inline(always)]
19445            pub fn txo_irq(&self) -> TxoIrqR {
19446                TxoIrqR::new(((self.bits >> 1) & 1) != 0)
19447            }
19448            #[doc = "Bit 2 - RX FIFO underflow raw status"]
19449            #[inline(always)]
19450            pub fn rxu_irq(&self) -> RxuIrqR {
19451                RxuIrqR::new(((self.bits >> 2) & 1) != 0)
19452            }
19453            #[doc = "Bit 3 - RX FIFO overflow raw status"]
19454            #[inline(always)]
19455            pub fn rxo_irq(&self) -> RxoIrqR {
19456                RxoIrqR::new(((self.bits >> 3) & 1) != 0)
19457            }
19458            #[doc = "Bit 4 - RX FIFO full raw status"]
19459            #[inline(always)]
19460            pub fn rxf_irq(&self) -> RxfIrqR {
19461                RxfIrqR::new(((self.bits >> 4) & 1) != 0)
19462            }
19463            #[doc = "Bit 5 - Multi-master contention raw status"]
19464            #[inline(always)]
19465            pub fn mst_irq(&self) -> MstIrqR {
19466                MstIrqR::new(((self.bits >> 5) & 1) != 0)
19467            }
19468        }
19469        impl W {}
19470        #[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rainsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rainsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19471        pub struct SpiRainsrSpec;
19472        impl crate::RegisterSpec for SpiRainsrSpec {
19473            type Ux = u32;
19474        }
19475        #[doc = "`read()` method returns [`spi_rainsr::R`](R) reader structure"]
19476        impl crate::Readable for SpiRainsrSpec {}
19477        #[doc = "`write(|w| ..)` method takes [`spi_rainsr::W`](W) writer structure"]
19478        impl crate::Writable for SpiRainsrSpec {
19479            type Safety = crate::Unsafe;
19480        }
19481        #[doc = "`reset()` method sets SPI_RAINSR to value 0"]
19482        impl crate::Resettable for SpiRainsrSpec {}
19483    }
19484    #[doc = "SPI_INSR (rw) register accessor: Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_insr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_insr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_insr`] module"]
19485    #[doc(alias = "SPI_INSR")]
19486    pub type SpiInsr = crate::Reg<spi_insr::SpiInsrSpec>;
19487    #[doc = "Interrupt status register (masked)"]
19488    pub mod spi_insr {
19489        #[doc = "Register `SPI_INSR` reader"]
19490        pub type R = crate::R<SpiInsrSpec>;
19491        #[doc = "Register `SPI_INSR` writer"]
19492        pub type W = crate::W<SpiInsrSpec>;
19493        #[doc = "Field `txe_is` reader - TX empty interrupt status"]
19494        pub type TxeIsR = crate::BitReader;
19495        #[doc = "Field `txo_is` reader - TX overflow interrupt status"]
19496        pub type TxoIsR = crate::BitReader;
19497        #[doc = "Field `rxu_is` reader - RX underflow interrupt status"]
19498        pub type RxuIsR = crate::BitReader;
19499        #[doc = "Field `rxo_is` reader - RX overflow interrupt status"]
19500        pub type RxoIsR = crate::BitReader;
19501        #[doc = "Field `rxf_is` reader - RX full interrupt status"]
19502        pub type RxfIsR = crate::BitReader;
19503        #[doc = "Field `mst_is` reader - Multi-master interrupt status"]
19504        pub type MstIsR = crate::BitReader;
19505        impl R {
19506            #[doc = "Bit 0 - TX empty interrupt status"]
19507            #[inline(always)]
19508            pub fn txe_is(&self) -> TxeIsR {
19509                TxeIsR::new((self.bits & 1) != 0)
19510            }
19511            #[doc = "Bit 1 - TX overflow interrupt status"]
19512            #[inline(always)]
19513            pub fn txo_is(&self) -> TxoIsR {
19514                TxoIsR::new(((self.bits >> 1) & 1) != 0)
19515            }
19516            #[doc = "Bit 2 - RX underflow interrupt status"]
19517            #[inline(always)]
19518            pub fn rxu_is(&self) -> RxuIsR {
19519                RxuIsR::new(((self.bits >> 2) & 1) != 0)
19520            }
19521            #[doc = "Bit 3 - RX overflow interrupt status"]
19522            #[inline(always)]
19523            pub fn rxo_is(&self) -> RxoIsR {
19524                RxoIsR::new(((self.bits >> 3) & 1) != 0)
19525            }
19526            #[doc = "Bit 4 - RX full interrupt status"]
19527            #[inline(always)]
19528            pub fn rxf_is(&self) -> RxfIsR {
19529                RxfIsR::new(((self.bits >> 4) & 1) != 0)
19530            }
19531            #[doc = "Bit 5 - Multi-master interrupt status"]
19532            #[inline(always)]
19533            pub fn mst_is(&self) -> MstIsR {
19534                MstIsR::new(((self.bits >> 5) & 1) != 0)
19535            }
19536        }
19537        impl W {}
19538        #[doc = "Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_insr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_insr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19539        pub struct SpiInsrSpec;
19540        impl crate::RegisterSpec for SpiInsrSpec {
19541            type Ux = u32;
19542        }
19543        #[doc = "`read()` method returns [`spi_insr::R`](R) reader structure"]
19544        impl crate::Readable for SpiInsrSpec {}
19545        #[doc = "`write(|w| ..)` method takes [`spi_insr::W`](W) writer structure"]
19546        impl crate::Writable for SpiInsrSpec {
19547            type Safety = crate::Unsafe;
19548        }
19549        #[doc = "`reset()` method sets SPI_INSR to value 0"]
19550        impl crate::Resettable for SpiInsrSpec {}
19551    }
19552    #[doc = "SPI_INMAR (rw) register accessor: Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_inmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_inmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_inmar`] module"]
19553    #[doc(alias = "SPI_INMAR")]
19554    pub type SpiInmar = crate::Reg<spi_inmar::SpiInmarSpec>;
19555    #[doc = "Interrupt mask register"]
19556    pub mod spi_inmar {
19557        #[doc = "Register `SPI_INMAR` reader"]
19558        pub type R = crate::R<SpiInmarSpec>;
19559        #[doc = "Register `SPI_INMAR` writer"]
19560        pub type W = crate::W<SpiInmarSpec>;
19561        #[doc = "Field `txe_im` reader - TX empty interrupt mask"]
19562        pub type TxeImR = crate::BitReader;
19563        #[doc = "Field `txe_im` writer - TX empty interrupt mask"]
19564        pub type TxeImW<'a, REG> = crate::BitWriter<'a, REG>;
19565        #[doc = "Field `txo_im` reader - TX overflow interrupt mask"]
19566        pub type TxoImR = crate::BitReader;
19567        #[doc = "Field `txo_im` writer - TX overflow interrupt mask"]
19568        pub type TxoImW<'a, REG> = crate::BitWriter<'a, REG>;
19569        #[doc = "Field `rxu_im` reader - RX underflow interrupt mask"]
19570        pub type RxuImR = crate::BitReader;
19571        #[doc = "Field `rxu_im` writer - RX underflow interrupt mask"]
19572        pub type RxuImW<'a, REG> = crate::BitWriter<'a, REG>;
19573        #[doc = "Field `rxo_im` reader - RX overflow interrupt mask"]
19574        pub type RxoImR = crate::BitReader;
19575        #[doc = "Field `rxo_im` writer - RX overflow interrupt mask"]
19576        pub type RxoImW<'a, REG> = crate::BitWriter<'a, REG>;
19577        #[doc = "Field `rxf_im` reader - RX full interrupt mask"]
19578        pub type RxfImR = crate::BitReader;
19579        #[doc = "Field `rxf_im` writer - RX full interrupt mask"]
19580        pub type RxfImW<'a, REG> = crate::BitWriter<'a, REG>;
19581        #[doc = "Field `mst_im` reader - Multi-master interrupt mask"]
19582        pub type MstImR = crate::BitReader;
19583        #[doc = "Field `mst_im` writer - Multi-master interrupt mask"]
19584        pub type MstImW<'a, REG> = crate::BitWriter<'a, REG>;
19585        impl R {
19586            #[doc = "Bit 0 - TX empty interrupt mask"]
19587            #[inline(always)]
19588            pub fn txe_im(&self) -> TxeImR {
19589                TxeImR::new((self.bits & 1) != 0)
19590            }
19591            #[doc = "Bit 1 - TX overflow interrupt mask"]
19592            #[inline(always)]
19593            pub fn txo_im(&self) -> TxoImR {
19594                TxoImR::new(((self.bits >> 1) & 1) != 0)
19595            }
19596            #[doc = "Bit 2 - RX underflow interrupt mask"]
19597            #[inline(always)]
19598            pub fn rxu_im(&self) -> RxuImR {
19599                RxuImR::new(((self.bits >> 2) & 1) != 0)
19600            }
19601            #[doc = "Bit 3 - RX overflow interrupt mask"]
19602            #[inline(always)]
19603            pub fn rxo_im(&self) -> RxoImR {
19604                RxoImR::new(((self.bits >> 3) & 1) != 0)
19605            }
19606            #[doc = "Bit 4 - RX full interrupt mask"]
19607            #[inline(always)]
19608            pub fn rxf_im(&self) -> RxfImR {
19609                RxfImR::new(((self.bits >> 4) & 1) != 0)
19610            }
19611            #[doc = "Bit 5 - Multi-master interrupt mask"]
19612            #[inline(always)]
19613            pub fn mst_im(&self) -> MstImR {
19614                MstImR::new(((self.bits >> 5) & 1) != 0)
19615            }
19616        }
19617        impl W {
19618            #[doc = "Bit 0 - TX empty interrupt mask"]
19619            #[inline(always)]
19620            pub fn txe_im(&mut self) -> TxeImW<'_, SpiInmarSpec> {
19621                TxeImW::new(self, 0)
19622            }
19623            #[doc = "Bit 1 - TX overflow interrupt mask"]
19624            #[inline(always)]
19625            pub fn txo_im(&mut self) -> TxoImW<'_, SpiInmarSpec> {
19626                TxoImW::new(self, 1)
19627            }
19628            #[doc = "Bit 2 - RX underflow interrupt mask"]
19629            #[inline(always)]
19630            pub fn rxu_im(&mut self) -> RxuImW<'_, SpiInmarSpec> {
19631                RxuImW::new(self, 2)
19632            }
19633            #[doc = "Bit 3 - RX overflow interrupt mask"]
19634            #[inline(always)]
19635            pub fn rxo_im(&mut self) -> RxoImW<'_, SpiInmarSpec> {
19636                RxoImW::new(self, 3)
19637            }
19638            #[doc = "Bit 4 - RX full interrupt mask"]
19639            #[inline(always)]
19640            pub fn rxf_im(&mut self) -> RxfImW<'_, SpiInmarSpec> {
19641                RxfImW::new(self, 4)
19642            }
19643            #[doc = "Bit 5 - Multi-master interrupt mask"]
19644            #[inline(always)]
19645            pub fn mst_im(&mut self) -> MstImW<'_, SpiInmarSpec> {
19646                MstImW::new(self, 5)
19647            }
19648        }
19649        #[doc = "Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_inmar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_inmar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19650        pub struct SpiInmarSpec;
19651        impl crate::RegisterSpec for SpiInmarSpec {
19652            type Ux = u32;
19653        }
19654        #[doc = "`read()` method returns [`spi_inmar::R`](R) reader structure"]
19655        impl crate::Readable for SpiInmarSpec {}
19656        #[doc = "`write(|w| ..)` method takes [`spi_inmar::W`](W) writer structure"]
19657        impl crate::Writable for SpiInmarSpec {
19658            type Safety = crate::Unsafe;
19659        }
19660        #[doc = "`reset()` method sets SPI_INMAR to value 0"]
19661        impl crate::Resettable for SpiInmarSpec {}
19662    }
19663    #[doc = "SPI_SLENR (rw) register accessor: Slave enable register (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_slenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_slenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slenr`] module"]
19664    #[doc(alias = "SPI_SLENR")]
19665    pub type SpiSlenr = crate::Reg<spi_slenr::SpiSlenrSpec>;
19666    #[doc = "Slave enable register (master only)"]
19667    pub mod spi_slenr {
19668        #[doc = "Register `SPI_SLENR` reader"]
19669        pub type R = crate::R<SpiSlenrSpec>;
19670        #[doc = "Register `SPI_SLENR` writer"]
19671        pub type W = crate::W<SpiSlenrSpec>;
19672        #[doc = "Field `slave_enable` reader - Slave select enable"]
19673        pub type SlaveEnableR = crate::BitReader;
19674        #[doc = "Field `slave_enable` writer - Slave select enable"]
19675        pub type SlaveEnableW<'a, REG> = crate::BitWriter<'a, REG>;
19676        impl R {
19677            #[doc = "Bit 0 - Slave select enable"]
19678            #[inline(always)]
19679            pub fn slave_enable(&self) -> SlaveEnableR {
19680                SlaveEnableR::new((self.bits & 1) != 0)
19681            }
19682        }
19683        impl W {
19684            #[doc = "Bit 0 - Slave select enable"]
19685            #[inline(always)]
19686            pub fn slave_enable(&mut self) -> SlaveEnableW<'_, SpiSlenrSpec> {
19687                SlaveEnableW::new(self, 0)
19688            }
19689        }
19690        #[doc = "Slave enable register (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_slenr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_slenr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19691        pub struct SpiSlenrSpec;
19692        impl crate::RegisterSpec for SpiSlenrSpec {
19693            type Ux = u32;
19694        }
19695        #[doc = "`read()` method returns [`spi_slenr::R`](R) reader structure"]
19696        impl crate::Readable for SpiSlenrSpec {}
19697        #[doc = "`write(|w| ..)` method takes [`spi_slenr::W`](W) writer structure"]
19698        impl crate::Writable for SpiSlenrSpec {
19699            type Safety = crate::Unsafe;
19700        }
19701        #[doc = "`reset()` method sets SPI_SLENR to value 0"]
19702        impl crate::Resettable for SpiSlenrSpec {}
19703    }
19704    #[doc = "SPI_TWLR (rw) register accessor: TX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_twlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_twlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_twlr`] module"]
19705    #[doc(alias = "SPI_TWLR")]
19706    pub type SpiTwlr = crate::Reg<spi_twlr::SpiTwlrSpec>;
19707    #[doc = "TX FIFO threshold level"]
19708    pub mod spi_twlr {
19709        #[doc = "Register `SPI_TWLR` reader"]
19710        pub type R = crate::R<SpiTwlrSpec>;
19711        #[doc = "Register `SPI_TWLR` writer"]
19712        pub type W = crate::W<SpiTwlrSpec>;
19713        #[doc = "Field `tx_fifo_threshold` reader - TX FIFO threshold level"]
19714        pub type TxFifoThresholdR = crate::FieldReader;
19715        #[doc = "Field `tx_fifo_threshold` writer - TX FIFO threshold level"]
19716        pub type TxFifoThresholdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
19717        impl R {
19718            #[doc = "Bits 0:7 - TX FIFO threshold level"]
19719            #[inline(always)]
19720            pub fn tx_fifo_threshold(&self) -> TxFifoThresholdR {
19721                TxFifoThresholdR::new((self.bits & 0xff) as u8)
19722            }
19723        }
19724        impl W {
19725            #[doc = "Bits 0:7 - TX FIFO threshold level"]
19726            #[inline(always)]
19727            pub fn tx_fifo_threshold(&mut self) -> TxFifoThresholdW<'_, SpiTwlrSpec> {
19728                TxFifoThresholdW::new(self, 0)
19729            }
19730        }
19731        #[doc = "TX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_twlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_twlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19732        pub struct SpiTwlrSpec;
19733        impl crate::RegisterSpec for SpiTwlrSpec {
19734            type Ux = u32;
19735        }
19736        #[doc = "`read()` method returns [`spi_twlr::R`](R) reader structure"]
19737        impl crate::Readable for SpiTwlrSpec {}
19738        #[doc = "`write(|w| ..)` method takes [`spi_twlr::W`](W) writer structure"]
19739        impl crate::Writable for SpiTwlrSpec {
19740            type Safety = crate::Unsafe;
19741        }
19742        #[doc = "`reset()` method sets SPI_TWLR to value 0"]
19743        impl crate::Resettable for SpiTwlrSpec {}
19744    }
19745    #[doc = "SPI_TLR (rw) register accessor: TX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_tlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_tlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_tlr`] module"]
19746    #[doc(alias = "SPI_TLR")]
19747    pub type SpiTlr = crate::Reg<spi_tlr::SpiTlrSpec>;
19748    #[doc = "TX FIFO level register"]
19749    pub mod spi_tlr {
19750        #[doc = "Register `SPI_TLR` reader"]
19751        pub type R = crate::R<SpiTlrSpec>;
19752        #[doc = "Register `SPI_TLR` writer"]
19753        pub type W = crate::W<SpiTlrSpec>;
19754        #[doc = "Field `tx_fifo_level` reader - TX FIFO data level"]
19755        pub type TxFifoLevelR = crate::FieldReader;
19756        impl R {
19757            #[doc = "Bits 0:7 - TX FIFO data level"]
19758            #[inline(always)]
19759            pub fn tx_fifo_level(&self) -> TxFifoLevelR {
19760                TxFifoLevelR::new((self.bits & 0xff) as u8)
19761            }
19762        }
19763        impl W {}
19764        #[doc = "TX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_tlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_tlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19765        pub struct SpiTlrSpec;
19766        impl crate::RegisterSpec for SpiTlrSpec {
19767            type Ux = u32;
19768        }
19769        #[doc = "`read()` method returns [`spi_tlr::R`](R) reader structure"]
19770        impl crate::Readable for SpiTlrSpec {}
19771        #[doc = "`write(|w| ..)` method takes [`spi_tlr::W`](W) writer structure"]
19772        impl crate::Writable for SpiTlrSpec {
19773            type Safety = crate::Unsafe;
19774        }
19775        #[doc = "`reset()` method sets SPI_TLR to value 0"]
19776        impl crate::Resettable for SpiTlrSpec {}
19777    }
19778    #[doc = "SPI_RWLR (rw) register accessor: RX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rwlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rwlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rwlr`] module"]
19779    #[doc(alias = "SPI_RWLR")]
19780    pub type SpiRwlr = crate::Reg<spi_rwlr::SpiRwlrSpec>;
19781    #[doc = "RX FIFO threshold level"]
19782    pub mod spi_rwlr {
19783        #[doc = "Register `SPI_RWLR` reader"]
19784        pub type R = crate::R<SpiRwlrSpec>;
19785        #[doc = "Register `SPI_RWLR` writer"]
19786        pub type W = crate::W<SpiRwlrSpec>;
19787        #[doc = "Field `rx_fifo_threshold` reader - RX FIFO threshold level"]
19788        pub type RxFifoThresholdR = crate::FieldReader;
19789        #[doc = "Field `rx_fifo_threshold` writer - RX FIFO threshold level"]
19790        pub type RxFifoThresholdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
19791        impl R {
19792            #[doc = "Bits 0:7 - RX FIFO threshold level"]
19793            #[inline(always)]
19794            pub fn rx_fifo_threshold(&self) -> RxFifoThresholdR {
19795                RxFifoThresholdR::new((self.bits & 0xff) as u8)
19796            }
19797        }
19798        impl W {
19799            #[doc = "Bits 0:7 - RX FIFO threshold level"]
19800            #[inline(always)]
19801            pub fn rx_fifo_threshold(&mut self) -> RxFifoThresholdW<'_, SpiRwlrSpec> {
19802                RxFifoThresholdW::new(self, 0)
19803            }
19804        }
19805        #[doc = "RX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rwlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rwlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19806        pub struct SpiRwlrSpec;
19807        impl crate::RegisterSpec for SpiRwlrSpec {
19808            type Ux = u32;
19809        }
19810        #[doc = "`read()` method returns [`spi_rwlr::R`](R) reader structure"]
19811        impl crate::Readable for SpiRwlrSpec {}
19812        #[doc = "`write(|w| ..)` method takes [`spi_rwlr::W`](W) writer structure"]
19813        impl crate::Writable for SpiRwlrSpec {
19814            type Safety = crate::Unsafe;
19815        }
19816        #[doc = "`reset()` method sets SPI_RWLR to value 0"]
19817        impl crate::Resettable for SpiRwlrSpec {}
19818    }
19819    #[doc = "SPI_RLR (rw) register accessor: RX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rlr`] module"]
19820    #[doc(alias = "SPI_RLR")]
19821    pub type SpiRlr = crate::Reg<spi_rlr::SpiRlrSpec>;
19822    #[doc = "RX FIFO level register"]
19823    pub mod spi_rlr {
19824        #[doc = "Register `SPI_RLR` reader"]
19825        pub type R = crate::R<SpiRlrSpec>;
19826        #[doc = "Register `SPI_RLR` writer"]
19827        pub type W = crate::W<SpiRlrSpec>;
19828        #[doc = "Field `rx_fifo_level` reader - RX FIFO data level"]
19829        pub type RxFifoLevelR = crate::FieldReader;
19830        impl R {
19831            #[doc = "Bits 0:7 - RX FIFO data level"]
19832            #[inline(always)]
19833            pub fn rx_fifo_level(&self) -> RxFifoLevelR {
19834                RxFifoLevelR::new((self.bits & 0xff) as u8)
19835            }
19836        }
19837        impl W {}
19838        #[doc = "RX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19839        pub struct SpiRlrSpec;
19840        impl crate::RegisterSpec for SpiRlrSpec {
19841            type Ux = u32;
19842        }
19843        #[doc = "`read()` method returns [`spi_rlr::R`](R) reader structure"]
19844        impl crate::Readable for SpiRlrSpec {}
19845        #[doc = "`write(|w| ..)` method takes [`spi_rlr::W`](W) writer structure"]
19846        impl crate::Writable for SpiRlrSpec {
19847            type Safety = crate::Unsafe;
19848        }
19849        #[doc = "`reset()` method sets SPI_RLR to value 0"]
19850        impl crate::Resettable for SpiRlrSpec {}
19851    }
19852    #[doc = "SPI_WSR (rw) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_wsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_wsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_wsr`] module"]
19853    #[doc(alias = "SPI_WSR")]
19854    pub type SpiWsr = crate::Reg<spi_wsr::SpiWsrSpec>;
19855    #[doc = "Status register"]
19856    pub mod spi_wsr {
19857        #[doc = "Register `SPI_WSR` reader"]
19858        pub type R = crate::R<SpiWsrSpec>;
19859        #[doc = "Register `SPI_WSR` writer"]
19860        pub type W = crate::W<SpiWsrSpec>;
19861        #[doc = "Field `busy` reader - SPI busy flag"]
19862        pub type BusyR = crate::BitReader;
19863        #[doc = "Field `txfnf` reader - TX FIFO not full"]
19864        pub type TxfnfR = crate::BitReader;
19865        #[doc = "Field `txfe` reader - TX FIFO empty"]
19866        pub type TxfeR = crate::BitReader;
19867        #[doc = "Field `rxfne` reader - RX FIFO not empty"]
19868        pub type RxfneR = crate::BitReader;
19869        #[doc = "Field `rxfo` reader - RX FIFO overflow"]
19870        pub type RxfoR = crate::BitReader;
19871        #[doc = "Field `txfo` reader - TX FIFO overflow"]
19872        pub type TxfoR = crate::BitReader;
19873        #[doc = "Field `dcm` reader - Data conflict mask"]
19874        pub type DcmR = crate::BitReader;
19875        impl R {
19876            #[doc = "Bit 0 - SPI busy flag"]
19877            #[inline(always)]
19878            pub fn busy(&self) -> BusyR {
19879                BusyR::new((self.bits & 1) != 0)
19880            }
19881            #[doc = "Bit 1 - TX FIFO not full"]
19882            #[inline(always)]
19883            pub fn txfnf(&self) -> TxfnfR {
19884                TxfnfR::new(((self.bits >> 1) & 1) != 0)
19885            }
19886            #[doc = "Bit 2 - TX FIFO empty"]
19887            #[inline(always)]
19888            pub fn txfe(&self) -> TxfeR {
19889                TxfeR::new(((self.bits >> 2) & 1) != 0)
19890            }
19891            #[doc = "Bit 3 - RX FIFO not empty"]
19892            #[inline(always)]
19893            pub fn rxfne(&self) -> RxfneR {
19894                RxfneR::new(((self.bits >> 3) & 1) != 0)
19895            }
19896            #[doc = "Bit 4 - RX FIFO overflow"]
19897            #[inline(always)]
19898            pub fn rxfo(&self) -> RxfoR {
19899                RxfoR::new(((self.bits >> 4) & 1) != 0)
19900            }
19901            #[doc = "Bit 5 - TX FIFO overflow"]
19902            #[inline(always)]
19903            pub fn txfo(&self) -> TxfoR {
19904                TxfoR::new(((self.bits >> 5) & 1) != 0)
19905            }
19906            #[doc = "Bit 6 - Data conflict mask"]
19907            #[inline(always)]
19908            pub fn dcm(&self) -> DcmR {
19909                DcmR::new(((self.bits >> 6) & 1) != 0)
19910            }
19911        }
19912        impl W {}
19913        #[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_wsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_wsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19914        pub struct SpiWsrSpec;
19915        impl crate::RegisterSpec for SpiWsrSpec {
19916            type Ux = u32;
19917        }
19918        #[doc = "`read()` method returns [`spi_wsr::R`](R) reader structure"]
19919        impl crate::Readable for SpiWsrSpec {}
19920        #[doc = "`write(|w| ..)` method takes [`spi_wsr::W`](W) writer structure"]
19921        impl crate::Writable for SpiWsrSpec {
19922            type Safety = crate::Unsafe;
19923        }
19924        #[doc = "`reset()` method sets SPI_WSR to value 0x06"]
19925        impl crate::Resettable for SpiWsrSpec {
19926            const RESET_VALUE: u32 = 0x06;
19927        }
19928    }
19929    #[doc = "SPI_ICR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_icr`] module"]
19930    #[doc(alias = "SPI_ICR")]
19931    pub type SpiIcr = crate::Reg<spi_icr::SpiIcrSpec>;
19932    #[doc = "Interrupt clear register"]
19933    pub mod spi_icr {
19934        #[doc = "Register `SPI_ICR` reader"]
19935        pub type R = crate::R<SpiIcrSpec>;
19936        #[doc = "Register `SPI_ICR` writer"]
19937        pub type W = crate::W<SpiIcrSpec>;
19938        #[doc = "Field `txo_ic` writer - TX overflow interrupt clear"]
19939        pub type TxoIcW<'a, REG> = crate::BitWriter<'a, REG>;
19940        #[doc = "Field `rxu_ic` writer - RX underflow interrupt clear"]
19941        pub type RxuIcW<'a, REG> = crate::BitWriter<'a, REG>;
19942        #[doc = "Field `rxo_ic` writer - RX overflow interrupt clear"]
19943        pub type RxoIcW<'a, REG> = crate::BitWriter<'a, REG>;
19944        #[doc = "Field `mst_ic` writer - Multi-master interrupt clear"]
19945        pub type MstIcW<'a, REG> = crate::BitWriter<'a, REG>;
19946        impl W {
19947            #[doc = "Bit 0 - TX overflow interrupt clear"]
19948            #[inline(always)]
19949            pub fn txo_ic(&mut self) -> TxoIcW<'_, SpiIcrSpec> {
19950                TxoIcW::new(self, 0)
19951            }
19952            #[doc = "Bit 1 - RX underflow interrupt clear"]
19953            #[inline(always)]
19954            pub fn rxu_ic(&mut self) -> RxuIcW<'_, SpiIcrSpec> {
19955                RxuIcW::new(self, 1)
19956            }
19957            #[doc = "Bit 2 - RX overflow interrupt clear"]
19958            #[inline(always)]
19959            pub fn rxo_ic(&mut self) -> RxoIcW<'_, SpiIcrSpec> {
19960                RxoIcW::new(self, 2)
19961            }
19962            #[doc = "Bit 3 - Multi-master interrupt clear"]
19963            #[inline(always)]
19964            pub fn mst_ic(&mut self) -> MstIcW<'_, SpiIcrSpec> {
19965                MstIcW::new(self, 3)
19966            }
19967        }
19968        #[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19969        pub struct SpiIcrSpec;
19970        impl crate::RegisterSpec for SpiIcrSpec {
19971            type Ux = u32;
19972        }
19973        #[doc = "`read()` method returns [`spi_icr::R`](R) reader structure"]
19974        impl crate::Readable for SpiIcrSpec {}
19975        #[doc = "`write(|w| ..)` method takes [`spi_icr::W`](W) writer structure"]
19976        impl crate::Writable for SpiIcrSpec {
19977            type Safety = crate::Unsafe;
19978        }
19979        #[doc = "`reset()` method sets SPI_ICR to value 0"]
19980        impl crate::Resettable for SpiIcrSpec {}
19981    }
19982}
19983#[doc = "SPI1/QSPI controller (SSI v151)"]
19984pub type Spi1 = crate::Periph<spi0::RegisterBlock, 0x4402_1000>;
19985impl core::fmt::Debug for Spi1 {
19986    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19987        f.debug_struct("Spi1").finish()
19988    }
19989}
19990#[doc = "SPI1/QSPI controller (SSI v151)"]
19991pub use self::spi0 as spi1;
19992#[doc = "I2S/SIO synchronous audio interface (v151)"]
19993pub type I2s = crate::Periph<i2s::RegisterBlock, 0x4402_5000>;
19994impl core::fmt::Debug for I2s {
19995    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19996        f.debug_struct("I2s").finish()
19997    }
19998}
19999#[doc = "I2S/SIO synchronous audio interface (v151)"]
20000pub mod i2s {
20001    #[repr(C)]
20002    #[doc = "Register block"]
20003    pub struct RegisterBlock {
20004        _reserved0: [u8; 0x3c],
20005        version: Version,
20006        mode: Mode,
20007        intstatus: Intstatus,
20008        intclr: Intclr,
20009        left_tx: LeftTx,
20010        right_tx: RightTx,
20011        left_rx: LeftRx,
20012        right_rx: RightRx,
20013        ct_set: CtSet,
20014        ct_clr: CtClr,
20015        fifo_threshold: FifoThreshold,
20016        rx_sta: RxSta,
20017        tx_sta: TxSta,
20018        _reserved13: [u8; 0x08],
20019        data_width_set: DataWidthSet,
20020        _reserved14: [u8; 0x08],
20021        signed_ext: SignedExt,
20022        _reserved15: [u8; 0x04],
20023        intmask: Intmask,
20024        i2s_crg: I2sCrg,
20025        i2s_bclk_div_num: I2sBclkDivNum,
20026        i2s_fs_div_num: I2sFsDivNum,
20027        i2s_fs_div_ratio_num: I2sFsDivRatioNum,
20028    }
20029    impl RegisterBlock {
20030        #[doc = "0x3c - Version and loopback register"]
20031        #[inline(always)]
20032        pub const fn version(&self) -> &Version {
20033            &self.version
20034        }
20035        #[doc = "0x40 - I2S/PCM mode register"]
20036        #[inline(always)]
20037        pub const fn mode(&self) -> &Mode {
20038            &self.mode
20039        }
20040        #[doc = "0x44 - Interrupt status register"]
20041        #[inline(always)]
20042        pub const fn intstatus(&self) -> &Intstatus {
20043            &self.intstatus
20044        }
20045        #[doc = "0x48 - Interrupt clear register"]
20046        #[inline(always)]
20047        pub const fn intclr(&self) -> &Intclr {
20048            &self.intclr
20049        }
20050        #[doc = "0x4c - TX left channel data"]
20051        #[inline(always)]
20052        pub const fn left_tx(&self) -> &LeftTx {
20053            &self.left_tx
20054        }
20055        #[doc = "0x50 - TX right channel data"]
20056        #[inline(always)]
20057        pub const fn right_tx(&self) -> &RightTx {
20058            &self.right_tx
20059        }
20060        #[doc = "0x54 - RX left channel data"]
20061        #[inline(always)]
20062        pub const fn left_rx(&self) -> &LeftRx {
20063            &self.left_rx
20064        }
20065        #[doc = "0x58 - RX right channel data"]
20066        #[inline(always)]
20067        pub const fn right_rx(&self) -> &RightRx {
20068            &self.right_rx
20069        }
20070        #[doc = "0x5c - Control set register"]
20071        #[inline(always)]
20072        pub const fn ct_set(&self) -> &CtSet {
20073            &self.ct_set
20074        }
20075        #[doc = "0x60 - Control clear register"]
20076        #[inline(always)]
20077        pub const fn ct_clr(&self) -> &CtClr {
20078            &self.ct_clr
20079        }
20080        #[doc = "0x64 - FIFO threshold register"]
20081        #[inline(always)]
20082        pub const fn fifo_threshold(&self) -> &FifoThreshold {
20083            &self.fifo_threshold
20084        }
20085        #[doc = "0x68 - RX status register"]
20086        #[inline(always)]
20087        pub const fn rx_sta(&self) -> &RxSta {
20088            &self.rx_sta
20089        }
20090        #[doc = "0x6c - TX status register"]
20091        #[inline(always)]
20092        pub const fn tx_sta(&self) -> &TxSta {
20093            &self.tx_sta
20094        }
20095        #[doc = "0x78 - Data width register"]
20096        #[inline(always)]
20097        pub const fn data_width_set(&self) -> &DataWidthSet {
20098            &self.data_width_set
20099        }
20100        #[doc = "0x84 - Signed extension enable"]
20101        #[inline(always)]
20102        pub const fn signed_ext(&self) -> &SignedExt {
20103            &self.signed_ext
20104        }
20105        #[doc = "0x8c - Interrupt mask register"]
20106        #[inline(always)]
20107        pub const fn intmask(&self) -> &Intmask {
20108            &self.intmask
20109        }
20110        #[doc = "0x90 - I2S clock/reset generator"]
20111        #[inline(always)]
20112        pub const fn i2s_crg(&self) -> &I2sCrg {
20113            &self.i2s_crg
20114        }
20115        #[doc = "0x94 - BCLK divider number"]
20116        #[inline(always)]
20117        pub const fn i2s_bclk_div_num(&self) -> &I2sBclkDivNum {
20118            &self.i2s_bclk_div_num
20119        }
20120        #[doc = "0x98 - FS divider number"]
20121        #[inline(always)]
20122        pub const fn i2s_fs_div_num(&self) -> &I2sFsDivNum {
20123            &self.i2s_fs_div_num
20124        }
20125        #[doc = "0x9c - FS divider ratio number"]
20126        #[inline(always)]
20127        pub const fn i2s_fs_div_ratio_num(&self) -> &I2sFsDivRatioNum {
20128            &self.i2s_fs_div_ratio_num
20129        }
20130    }
20131    #[doc = "VERSION (rw) register accessor: Version and loopback register\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"]
20132    #[doc(alias = "VERSION")]
20133    pub type Version = crate::Reg<version::VersionSpec>;
20134    #[doc = "Version and loopback register"]
20135    pub mod version {
20136        #[doc = "Register `VERSION` reader"]
20137        pub type R = crate::R<VersionSpec>;
20138        #[doc = "Register `VERSION` writer"]
20139        pub type W = crate::W<VersionSpec>;
20140        #[doc = "Field `version` reader - IP version"]
20141        pub type VersionR = crate::FieldReader;
20142        #[doc = "Field `loopback_mode` reader - Loopback mode enable"]
20143        pub type LoopbackModeR = crate::BitReader;
20144        #[doc = "Field `loopback_mode` writer - Loopback mode enable"]
20145        pub type LoopbackModeW<'a, REG> = crate::BitWriter<'a, REG>;
20146        impl R {
20147            #[doc = "Bits 0:7 - IP version"]
20148            #[inline(always)]
20149            pub fn version(&self) -> VersionR {
20150                VersionR::new((self.bits & 0xff) as u8)
20151            }
20152            #[doc = "Bit 8 - Loopback mode enable"]
20153            #[inline(always)]
20154            pub fn loopback_mode(&self) -> LoopbackModeR {
20155                LoopbackModeR::new(((self.bits >> 8) & 1) != 0)
20156            }
20157        }
20158        impl W {
20159            #[doc = "Bit 8 - Loopback mode enable"]
20160            #[inline(always)]
20161            pub fn loopback_mode(&mut self) -> LoopbackModeW<'_, VersionSpec> {
20162                LoopbackModeW::new(self, 8)
20163            }
20164        }
20165        #[doc = "Version and loopback register\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20166        pub struct VersionSpec;
20167        impl crate::RegisterSpec for VersionSpec {
20168            type Ux = u32;
20169        }
20170        #[doc = "`read()` method returns [`version::R`](R) reader structure"]
20171        impl crate::Readable for VersionSpec {}
20172        #[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"]
20173        impl crate::Writable for VersionSpec {
20174            type Safety = crate::Unsafe;
20175        }
20176        #[doc = "`reset()` method sets VERSION to value 0"]
20177        impl crate::Resettable for VersionSpec {}
20178    }
20179    #[doc = "MODE (rw) register accessor: I2S/PCM mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"]
20180    #[doc(alias = "MODE")]
20181    pub type Mode = crate::Reg<mode::ModeSpec>;
20182    #[doc = "I2S/PCM mode register"]
20183    pub mod mode {
20184        #[doc = "Register `MODE` reader"]
20185        pub type R = crate::R<ModeSpec>;
20186        #[doc = "Register `MODE` writer"]
20187        pub type W = crate::W<ModeSpec>;
20188        #[doc = "Field `channels` reader - Number of channels: 0=2ch; 1=4ch; 2=6ch; 3=8ch"]
20189        pub type ChannelsR = crate::FieldReader;
20190        #[doc = "Field `channels` writer - Number of channels: 0=2ch; 1=4ch; 2=6ch; 3=8ch"]
20191        pub type ChannelsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
20192        #[doc = "Field `clk_edge` reader - Clock edge: 0=rising; 1=falling"]
20193        pub type ClkEdgeR = crate::BitReader;
20194        #[doc = "Field `clk_edge` writer - Clock edge: 0=rising; 1=falling"]
20195        pub type ClkEdgeW<'a, REG> = crate::BitWriter<'a, REG>;
20196        #[doc = "Field `master_slave` reader - Mode: 0=slave; 1=master"]
20197        pub type MasterSlaveR = crate::BitReader;
20198        #[doc = "Field `master_slave` writer - Mode: 0=slave; 1=master"]
20199        pub type MasterSlaveW<'a, REG> = crate::BitWriter<'a, REG>;
20200        #[doc = "Field `pcm_mode` reader - PCM mode: 0=I2S; 1=PCM"]
20201        pub type PcmModeR = crate::BitReader;
20202        #[doc = "Field `pcm_mode` writer - PCM mode: 0=I2S; 1=PCM"]
20203        pub type PcmModeW<'a, REG> = crate::BitWriter<'a, REG>;
20204        impl R {
20205            #[doc = "Bits 0:1 - Number of channels: 0=2ch; 1=4ch; 2=6ch; 3=8ch"]
20206            #[inline(always)]
20207            pub fn channels(&self) -> ChannelsR {
20208                ChannelsR::new((self.bits & 3) as u8)
20209            }
20210            #[doc = "Bit 2 - Clock edge: 0=rising; 1=falling"]
20211            #[inline(always)]
20212            pub fn clk_edge(&self) -> ClkEdgeR {
20213                ClkEdgeR::new(((self.bits >> 2) & 1) != 0)
20214            }
20215            #[doc = "Bit 3 - Mode: 0=slave; 1=master"]
20216            #[inline(always)]
20217            pub fn master_slave(&self) -> MasterSlaveR {
20218                MasterSlaveR::new(((self.bits >> 3) & 1) != 0)
20219            }
20220            #[doc = "Bit 4 - PCM mode: 0=I2S; 1=PCM"]
20221            #[inline(always)]
20222            pub fn pcm_mode(&self) -> PcmModeR {
20223                PcmModeR::new(((self.bits >> 4) & 1) != 0)
20224            }
20225        }
20226        impl W {
20227            #[doc = "Bits 0:1 - Number of channels: 0=2ch; 1=4ch; 2=6ch; 3=8ch"]
20228            #[inline(always)]
20229            pub fn channels(&mut self) -> ChannelsW<'_, ModeSpec> {
20230                ChannelsW::new(self, 0)
20231            }
20232            #[doc = "Bit 2 - Clock edge: 0=rising; 1=falling"]
20233            #[inline(always)]
20234            pub fn clk_edge(&mut self) -> ClkEdgeW<'_, ModeSpec> {
20235                ClkEdgeW::new(self, 2)
20236            }
20237            #[doc = "Bit 3 - Mode: 0=slave; 1=master"]
20238            #[inline(always)]
20239            pub fn master_slave(&mut self) -> MasterSlaveW<'_, ModeSpec> {
20240                MasterSlaveW::new(self, 3)
20241            }
20242            #[doc = "Bit 4 - PCM mode: 0=I2S; 1=PCM"]
20243            #[inline(always)]
20244            pub fn pcm_mode(&mut self) -> PcmModeW<'_, ModeSpec> {
20245                PcmModeW::new(self, 4)
20246            }
20247        }
20248        #[doc = "I2S/PCM mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20249        pub struct ModeSpec;
20250        impl crate::RegisterSpec for ModeSpec {
20251            type Ux = u32;
20252        }
20253        #[doc = "`read()` method returns [`mode::R`](R) reader structure"]
20254        impl crate::Readable for ModeSpec {}
20255        #[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"]
20256        impl crate::Writable for ModeSpec {
20257            type Safety = crate::Unsafe;
20258        }
20259        #[doc = "`reset()` method sets MODE to value 0"]
20260        impl crate::Resettable for ModeSpec {}
20261    }
20262    #[doc = "INTSTATUS (rw) register accessor: Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intstatus`] module"]
20263    #[doc(alias = "INTSTATUS")]
20264    pub type Intstatus = crate::Reg<intstatus::IntstatusSpec>;
20265    #[doc = "Interrupt status register"]
20266    pub mod intstatus {
20267        #[doc = "Register `INTSTATUS` reader"]
20268        pub type R = crate::R<IntstatusSpec>;
20269        #[doc = "Register `INTSTATUS` writer"]
20270        pub type W = crate::W<IntstatusSpec>;
20271        #[doc = "Field `rx_int` reader - RX interrupt status"]
20272        pub type RxIntR = crate::BitReader;
20273        #[doc = "Field `tx_int` reader - TX interrupt status"]
20274        pub type TxIntR = crate::BitReader;
20275        #[doc = "Field `rx_overflow` reader - RX overflow status"]
20276        pub type RxOverflowR = crate::BitReader;
20277        #[doc = "Field `tx_underflow` reader - TX underflow status"]
20278        pub type TxUnderflowR = crate::BitReader;
20279        impl R {
20280            #[doc = "Bit 0 - RX interrupt status"]
20281            #[inline(always)]
20282            pub fn rx_int(&self) -> RxIntR {
20283                RxIntR::new((self.bits & 1) != 0)
20284            }
20285            #[doc = "Bit 1 - TX interrupt status"]
20286            #[inline(always)]
20287            pub fn tx_int(&self) -> TxIntR {
20288                TxIntR::new(((self.bits >> 1) & 1) != 0)
20289            }
20290            #[doc = "Bit 2 - RX overflow status"]
20291            #[inline(always)]
20292            pub fn rx_overflow(&self) -> RxOverflowR {
20293                RxOverflowR::new(((self.bits >> 2) & 1) != 0)
20294            }
20295            #[doc = "Bit 3 - TX underflow status"]
20296            #[inline(always)]
20297            pub fn tx_underflow(&self) -> TxUnderflowR {
20298                TxUnderflowR::new(((self.bits >> 3) & 1) != 0)
20299            }
20300        }
20301        impl W {}
20302        #[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20303        pub struct IntstatusSpec;
20304        impl crate::RegisterSpec for IntstatusSpec {
20305            type Ux = u32;
20306        }
20307        #[doc = "`read()` method returns [`intstatus::R`](R) reader structure"]
20308        impl crate::Readable for IntstatusSpec {}
20309        #[doc = "`write(|w| ..)` method takes [`intstatus::W`](W) writer structure"]
20310        impl crate::Writable for IntstatusSpec {
20311            type Safety = crate::Unsafe;
20312        }
20313        #[doc = "`reset()` method sets INTSTATUS to value 0"]
20314        impl crate::Resettable for IntstatusSpec {}
20315    }
20316    #[doc = "INTCLR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intclr`] module"]
20317    #[doc(alias = "INTCLR")]
20318    pub type Intclr = crate::Reg<intclr::IntclrSpec>;
20319    #[doc = "Interrupt clear register"]
20320    pub mod intclr {
20321        #[doc = "Register `INTCLR` reader"]
20322        pub type R = crate::R<IntclrSpec>;
20323        #[doc = "Register `INTCLR` writer"]
20324        pub type W = crate::W<IntclrSpec>;
20325        #[doc = "Field `rx_int_clr` writer - Clear RX interrupt"]
20326        pub type RxIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
20327        #[doc = "Field `tx_int_clr` writer - Clear TX interrupt"]
20328        pub type TxIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
20329        #[doc = "Field `rx_overflow_clr` writer - Clear RX overflow"]
20330        pub type RxOverflowClrW<'a, REG> = crate::BitWriter<'a, REG>;
20331        #[doc = "Field `tx_underflow_clr` writer - Clear TX underflow"]
20332        pub type TxUnderflowClrW<'a, REG> = crate::BitWriter<'a, REG>;
20333        impl W {
20334            #[doc = "Bit 0 - Clear RX interrupt"]
20335            #[inline(always)]
20336            pub fn rx_int_clr(&mut self) -> RxIntClrW<'_, IntclrSpec> {
20337                RxIntClrW::new(self, 0)
20338            }
20339            #[doc = "Bit 1 - Clear TX interrupt"]
20340            #[inline(always)]
20341            pub fn tx_int_clr(&mut self) -> TxIntClrW<'_, IntclrSpec> {
20342                TxIntClrW::new(self, 1)
20343            }
20344            #[doc = "Bit 2 - Clear RX overflow"]
20345            #[inline(always)]
20346            pub fn rx_overflow_clr(&mut self) -> RxOverflowClrW<'_, IntclrSpec> {
20347                RxOverflowClrW::new(self, 2)
20348            }
20349            #[doc = "Bit 3 - Clear TX underflow"]
20350            #[inline(always)]
20351            pub fn tx_underflow_clr(&mut self) -> TxUnderflowClrW<'_, IntclrSpec> {
20352                TxUnderflowClrW::new(self, 3)
20353            }
20354        }
20355        #[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20356        pub struct IntclrSpec;
20357        impl crate::RegisterSpec for IntclrSpec {
20358            type Ux = u32;
20359        }
20360        #[doc = "`read()` method returns [`intclr::R`](R) reader structure"]
20361        impl crate::Readable for IntclrSpec {}
20362        #[doc = "`write(|w| ..)` method takes [`intclr::W`](W) writer structure"]
20363        impl crate::Writable for IntclrSpec {
20364            type Safety = crate::Unsafe;
20365        }
20366        #[doc = "`reset()` method sets INTCLR to value 0"]
20367        impl crate::Resettable for IntclrSpec {}
20368    }
20369    #[doc = "LEFT_TX (rw) register accessor: TX left channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`left_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`left_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@left_tx`] module"]
20370    #[doc(alias = "LEFT_TX")]
20371    pub type LeftTx = crate::Reg<left_tx::LeftTxSpec>;
20372    #[doc = "TX left channel data"]
20373    pub mod left_tx {
20374        #[doc = "Register `LEFT_TX` reader"]
20375        pub type R = crate::R<LeftTxSpec>;
20376        #[doc = "Register `LEFT_TX` writer"]
20377        pub type W = crate::W<LeftTxSpec>;
20378        #[doc = "Field `left_tx_data` reader - TX left channel data"]
20379        pub type LeftTxDataR = crate::FieldReader<u32>;
20380        #[doc = "Field `left_tx_data` writer - TX left channel data"]
20381        pub type LeftTxDataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
20382        impl R {
20383            #[doc = "Bits 0:31 - TX left channel data"]
20384            #[inline(always)]
20385            pub fn left_tx_data(&self) -> LeftTxDataR {
20386                LeftTxDataR::new(self.bits)
20387            }
20388        }
20389        impl W {
20390            #[doc = "Bits 0:31 - TX left channel data"]
20391            #[inline(always)]
20392            pub fn left_tx_data(&mut self) -> LeftTxDataW<'_, LeftTxSpec> {
20393                LeftTxDataW::new(self, 0)
20394            }
20395        }
20396        #[doc = "TX left channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`left_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`left_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20397        pub struct LeftTxSpec;
20398        impl crate::RegisterSpec for LeftTxSpec {
20399            type Ux = u32;
20400        }
20401        #[doc = "`read()` method returns [`left_tx::R`](R) reader structure"]
20402        impl crate::Readable for LeftTxSpec {}
20403        #[doc = "`write(|w| ..)` method takes [`left_tx::W`](W) writer structure"]
20404        impl crate::Writable for LeftTxSpec {
20405            type Safety = crate::Unsafe;
20406        }
20407        #[doc = "`reset()` method sets LEFT_TX to value 0"]
20408        impl crate::Resettable for LeftTxSpec {}
20409    }
20410    #[doc = "RIGHT_TX (rw) register accessor: TX right channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`right_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`right_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@right_tx`] module"]
20411    #[doc(alias = "RIGHT_TX")]
20412    pub type RightTx = crate::Reg<right_tx::RightTxSpec>;
20413    #[doc = "TX right channel data"]
20414    pub mod right_tx {
20415        #[doc = "Register `RIGHT_TX` reader"]
20416        pub type R = crate::R<RightTxSpec>;
20417        #[doc = "Register `RIGHT_TX` writer"]
20418        pub type W = crate::W<RightTxSpec>;
20419        #[doc = "Field `right_tx_data` reader - TX right channel data"]
20420        pub type RightTxDataR = crate::FieldReader<u32>;
20421        #[doc = "Field `right_tx_data` writer - TX right channel data"]
20422        pub type RightTxDataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
20423        impl R {
20424            #[doc = "Bits 0:31 - TX right channel data"]
20425            #[inline(always)]
20426            pub fn right_tx_data(&self) -> RightTxDataR {
20427                RightTxDataR::new(self.bits)
20428            }
20429        }
20430        impl W {
20431            #[doc = "Bits 0:31 - TX right channel data"]
20432            #[inline(always)]
20433            pub fn right_tx_data(&mut self) -> RightTxDataW<'_, RightTxSpec> {
20434                RightTxDataW::new(self, 0)
20435            }
20436        }
20437        #[doc = "TX right channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`right_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`right_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20438        pub struct RightTxSpec;
20439        impl crate::RegisterSpec for RightTxSpec {
20440            type Ux = u32;
20441        }
20442        #[doc = "`read()` method returns [`right_tx::R`](R) reader structure"]
20443        impl crate::Readable for RightTxSpec {}
20444        #[doc = "`write(|w| ..)` method takes [`right_tx::W`](W) writer structure"]
20445        impl crate::Writable for RightTxSpec {
20446            type Safety = crate::Unsafe;
20447        }
20448        #[doc = "`reset()` method sets RIGHT_TX to value 0"]
20449        impl crate::Resettable for RightTxSpec {}
20450    }
20451    #[doc = "LEFT_RX (rw) register accessor: RX left channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`left_rx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`left_rx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@left_rx`] module"]
20452    #[doc(alias = "LEFT_RX")]
20453    pub type LeftRx = crate::Reg<left_rx::LeftRxSpec>;
20454    #[doc = "RX left channel data"]
20455    pub mod left_rx {
20456        #[doc = "Register `LEFT_RX` reader"]
20457        pub type R = crate::R<LeftRxSpec>;
20458        #[doc = "Register `LEFT_RX` writer"]
20459        pub type W = crate::W<LeftRxSpec>;
20460        #[doc = "Field `left_rx_data` reader - RX left channel data"]
20461        pub type LeftRxDataR = crate::FieldReader<u32>;
20462        impl R {
20463            #[doc = "Bits 0:31 - RX left channel data"]
20464            #[inline(always)]
20465            pub fn left_rx_data(&self) -> LeftRxDataR {
20466                LeftRxDataR::new(self.bits)
20467            }
20468        }
20469        impl W {}
20470        #[doc = "RX left channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`left_rx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`left_rx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20471        pub struct LeftRxSpec;
20472        impl crate::RegisterSpec for LeftRxSpec {
20473            type Ux = u32;
20474        }
20475        #[doc = "`read()` method returns [`left_rx::R`](R) reader structure"]
20476        impl crate::Readable for LeftRxSpec {}
20477        #[doc = "`write(|w| ..)` method takes [`left_rx::W`](W) writer structure"]
20478        impl crate::Writable for LeftRxSpec {
20479            type Safety = crate::Unsafe;
20480        }
20481        #[doc = "`reset()` method sets LEFT_RX to value 0"]
20482        impl crate::Resettable for LeftRxSpec {}
20483    }
20484    #[doc = "RIGHT_RX (rw) register accessor: RX right channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`right_rx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`right_rx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@right_rx`] module"]
20485    #[doc(alias = "RIGHT_RX")]
20486    pub type RightRx = crate::Reg<right_rx::RightRxSpec>;
20487    #[doc = "RX right channel data"]
20488    pub mod right_rx {
20489        #[doc = "Register `RIGHT_RX` reader"]
20490        pub type R = crate::R<RightRxSpec>;
20491        #[doc = "Register `RIGHT_RX` writer"]
20492        pub type W = crate::W<RightRxSpec>;
20493        #[doc = "Field `right_rx_data` reader - RX right channel data"]
20494        pub type RightRxDataR = crate::FieldReader<u32>;
20495        impl R {
20496            #[doc = "Bits 0:31 - RX right channel data"]
20497            #[inline(always)]
20498            pub fn right_rx_data(&self) -> RightRxDataR {
20499                RightRxDataR::new(self.bits)
20500            }
20501        }
20502        impl W {}
20503        #[doc = "RX right channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`right_rx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`right_rx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20504        pub struct RightRxSpec;
20505        impl crate::RegisterSpec for RightRxSpec {
20506            type Ux = u32;
20507        }
20508        #[doc = "`read()` method returns [`right_rx::R`](R) reader structure"]
20509        impl crate::Readable for RightRxSpec {}
20510        #[doc = "`write(|w| ..)` method takes [`right_rx::W`](W) writer structure"]
20511        impl crate::Writable for RightRxSpec {
20512            type Safety = crate::Unsafe;
20513        }
20514        #[doc = "`reset()` method sets RIGHT_RX to value 0"]
20515        impl crate::Resettable for RightRxSpec {}
20516    }
20517    #[doc = "CT_SET (rw) register accessor: Control set register\n\nYou can [`read`](crate::Reg::read) this register and get [`ct_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ct_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ct_set`] module"]
20518    #[doc(alias = "CT_SET")]
20519    pub type CtSet = crate::Reg<ct_set::CtSetSpec>;
20520    #[doc = "Control set register"]
20521    pub mod ct_set {
20522        #[doc = "Register `CT_SET` reader"]
20523        pub type R = crate::R<CtSetSpec>;
20524        #[doc = "Register `CT_SET` writer"]
20525        pub type W = crate::W<CtSetSpec>;
20526        #[doc = "Field `tx_en` writer - TX enable set"]
20527        pub type TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
20528        #[doc = "Field `rx_en` writer - RX enable set"]
20529        pub type RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
20530        #[doc = "Field `tx_rst` writer - TX reset set"]
20531        pub type TxRstW<'a, REG> = crate::BitWriter<'a, REG>;
20532        #[doc = "Field `rx_rst` writer - RX reset set"]
20533        pub type RxRstW<'a, REG> = crate::BitWriter<'a, REG>;
20534        #[doc = "Field `tx_intr_en` writer - TX interrupt enable set"]
20535        pub type TxIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
20536        #[doc = "Field `rx_intr_en` writer - RX interrupt enable set"]
20537        pub type RxIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
20538        #[doc = "Field `merge_en` writer - Merge enable set"]
20539        pub type MergeEnW<'a, REG> = crate::BitWriter<'a, REG>;
20540        impl W {
20541            #[doc = "Bit 0 - TX enable set"]
20542            #[inline(always)]
20543            pub fn tx_en(&mut self) -> TxEnW<'_, CtSetSpec> {
20544                TxEnW::new(self, 0)
20545            }
20546            #[doc = "Bit 1 - RX enable set"]
20547            #[inline(always)]
20548            pub fn rx_en(&mut self) -> RxEnW<'_, CtSetSpec> {
20549                RxEnW::new(self, 1)
20550            }
20551            #[doc = "Bit 2 - TX reset set"]
20552            #[inline(always)]
20553            pub fn tx_rst(&mut self) -> TxRstW<'_, CtSetSpec> {
20554                TxRstW::new(self, 2)
20555            }
20556            #[doc = "Bit 3 - RX reset set"]
20557            #[inline(always)]
20558            pub fn rx_rst(&mut self) -> RxRstW<'_, CtSetSpec> {
20559                RxRstW::new(self, 3)
20560            }
20561            #[doc = "Bit 4 - TX interrupt enable set"]
20562            #[inline(always)]
20563            pub fn tx_intr_en(&mut self) -> TxIntrEnW<'_, CtSetSpec> {
20564                TxIntrEnW::new(self, 4)
20565            }
20566            #[doc = "Bit 5 - RX interrupt enable set"]
20567            #[inline(always)]
20568            pub fn rx_intr_en(&mut self) -> RxIntrEnW<'_, CtSetSpec> {
20569                RxIntrEnW::new(self, 5)
20570            }
20571            #[doc = "Bit 6 - Merge enable set"]
20572            #[inline(always)]
20573            pub fn merge_en(&mut self) -> MergeEnW<'_, CtSetSpec> {
20574                MergeEnW::new(self, 6)
20575            }
20576        }
20577        #[doc = "Control set register\n\nYou can [`read`](crate::Reg::read) this register and get [`ct_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ct_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20578        pub struct CtSetSpec;
20579        impl crate::RegisterSpec for CtSetSpec {
20580            type Ux = u32;
20581        }
20582        #[doc = "`read()` method returns [`ct_set::R`](R) reader structure"]
20583        impl crate::Readable for CtSetSpec {}
20584        #[doc = "`write(|w| ..)` method takes [`ct_set::W`](W) writer structure"]
20585        impl crate::Writable for CtSetSpec {
20586            type Safety = crate::Unsafe;
20587        }
20588        #[doc = "`reset()` method sets CT_SET to value 0"]
20589        impl crate::Resettable for CtSetSpec {}
20590    }
20591    #[doc = "CT_CLR (rw) register accessor: Control clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`ct_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ct_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ct_clr`] module"]
20592    #[doc(alias = "CT_CLR")]
20593    pub type CtClr = crate::Reg<ct_clr::CtClrSpec>;
20594    #[doc = "Control clear register"]
20595    pub mod ct_clr {
20596        #[doc = "Register `CT_CLR` reader"]
20597        pub type R = crate::R<CtClrSpec>;
20598        #[doc = "Register `CT_CLR` writer"]
20599        pub type W = crate::W<CtClrSpec>;
20600        #[doc = "Field `tx_en` writer - TX enable clear"]
20601        pub type TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
20602        #[doc = "Field `rx_en` writer - RX enable clear"]
20603        pub type RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
20604        #[doc = "Field `tx_intr_en` writer - TX interrupt disable"]
20605        pub type TxIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
20606        #[doc = "Field `rx_intr_en` writer - RX interrupt disable"]
20607        pub type RxIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
20608        #[doc = "Field `merge_en` writer - Merge disable"]
20609        pub type MergeEnW<'a, REG> = crate::BitWriter<'a, REG>;
20610        impl W {
20611            #[doc = "Bit 0 - TX enable clear"]
20612            #[inline(always)]
20613            pub fn tx_en(&mut self) -> TxEnW<'_, CtClrSpec> {
20614                TxEnW::new(self, 0)
20615            }
20616            #[doc = "Bit 1 - RX enable clear"]
20617            #[inline(always)]
20618            pub fn rx_en(&mut self) -> RxEnW<'_, CtClrSpec> {
20619                RxEnW::new(self, 1)
20620            }
20621            #[doc = "Bit 4 - TX interrupt disable"]
20622            #[inline(always)]
20623            pub fn tx_intr_en(&mut self) -> TxIntrEnW<'_, CtClrSpec> {
20624                TxIntrEnW::new(self, 4)
20625            }
20626            #[doc = "Bit 5 - RX interrupt disable"]
20627            #[inline(always)]
20628            pub fn rx_intr_en(&mut self) -> RxIntrEnW<'_, CtClrSpec> {
20629                RxIntrEnW::new(self, 5)
20630            }
20631            #[doc = "Bit 6 - Merge disable"]
20632            #[inline(always)]
20633            pub fn merge_en(&mut self) -> MergeEnW<'_, CtClrSpec> {
20634                MergeEnW::new(self, 6)
20635            }
20636        }
20637        #[doc = "Control clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`ct_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ct_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20638        pub struct CtClrSpec;
20639        impl crate::RegisterSpec for CtClrSpec {
20640            type Ux = u32;
20641        }
20642        #[doc = "`read()` method returns [`ct_clr::R`](R) reader structure"]
20643        impl crate::Readable for CtClrSpec {}
20644        #[doc = "`write(|w| ..)` method takes [`ct_clr::W`](W) writer structure"]
20645        impl crate::Writable for CtClrSpec {
20646            type Safety = crate::Unsafe;
20647        }
20648        #[doc = "`reset()` method sets CT_CLR to value 0"]
20649        impl crate::Resettable for CtClrSpec {}
20650    }
20651    #[doc = "FIFO_THRESHOLD (rw) register accessor: FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_threshold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_threshold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_threshold`] module"]
20652    #[doc(alias = "FIFO_THRESHOLD")]
20653    pub type FifoThreshold = crate::Reg<fifo_threshold::FifoThresholdSpec>;
20654    #[doc = "FIFO threshold register"]
20655    pub mod fifo_threshold {
20656        #[doc = "Register `FIFO_THRESHOLD` reader"]
20657        pub type R = crate::R<FifoThresholdSpec>;
20658        #[doc = "Register `FIFO_THRESHOLD` writer"]
20659        pub type W = crate::W<FifoThresholdSpec>;
20660        #[doc = "Field `tx_threshold` reader - TX FIFO threshold"]
20661        pub type TxThresholdR = crate::FieldReader;
20662        #[doc = "Field `tx_threshold` writer - TX FIFO threshold"]
20663        pub type TxThresholdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
20664        #[doc = "Field `rx_threshold` reader - RX FIFO threshold"]
20665        pub type RxThresholdR = crate::FieldReader;
20666        #[doc = "Field `rx_threshold` writer - RX FIFO threshold"]
20667        pub type RxThresholdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
20668        impl R {
20669            #[doc = "Bits 0:7 - TX FIFO threshold"]
20670            #[inline(always)]
20671            pub fn tx_threshold(&self) -> TxThresholdR {
20672                TxThresholdR::new((self.bits & 0xff) as u8)
20673            }
20674            #[doc = "Bits 8:15 - RX FIFO threshold"]
20675            #[inline(always)]
20676            pub fn rx_threshold(&self) -> RxThresholdR {
20677                RxThresholdR::new(((self.bits >> 8) & 0xff) as u8)
20678            }
20679        }
20680        impl W {
20681            #[doc = "Bits 0:7 - TX FIFO threshold"]
20682            #[inline(always)]
20683            pub fn tx_threshold(&mut self) -> TxThresholdW<'_, FifoThresholdSpec> {
20684                TxThresholdW::new(self, 0)
20685            }
20686            #[doc = "Bits 8:15 - RX FIFO threshold"]
20687            #[inline(always)]
20688            pub fn rx_threshold(&mut self) -> RxThresholdW<'_, FifoThresholdSpec> {
20689                RxThresholdW::new(self, 8)
20690            }
20691        }
20692        #[doc = "FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_threshold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_threshold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20693        pub struct FifoThresholdSpec;
20694        impl crate::RegisterSpec for FifoThresholdSpec {
20695            type Ux = u32;
20696        }
20697        #[doc = "`read()` method returns [`fifo_threshold::R`](R) reader structure"]
20698        impl crate::Readable for FifoThresholdSpec {}
20699        #[doc = "`write(|w| ..)` method takes [`fifo_threshold::W`](W) writer structure"]
20700        impl crate::Writable for FifoThresholdSpec {
20701            type Safety = crate::Unsafe;
20702        }
20703        #[doc = "`reset()` method sets FIFO_THRESHOLD to value 0"]
20704        impl crate::Resettable for FifoThresholdSpec {}
20705    }
20706    #[doc = "RX_STA (rw) register accessor: RX status register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_sta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_sta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_sta`] module"]
20707    #[doc(alias = "RX_STA")]
20708    pub type RxSta = crate::Reg<rx_sta::RxStaSpec>;
20709    #[doc = "RX status register"]
20710    pub mod rx_sta {
20711        #[doc = "Register `RX_STA` reader"]
20712        pub type R = crate::R<RxStaSpec>;
20713        #[doc = "Register `RX_STA` writer"]
20714        pub type W = crate::W<RxStaSpec>;
20715        #[doc = "Field `left_depth` reader - RX left FIFO depth"]
20716        pub type LeftDepthR = crate::FieldReader;
20717        #[doc = "Field `right_depth` reader - RX right FIFO depth"]
20718        pub type RightDepthR = crate::FieldReader;
20719        impl R {
20720            #[doc = "Bits 0:7 - RX left FIFO depth"]
20721            #[inline(always)]
20722            pub fn left_depth(&self) -> LeftDepthR {
20723                LeftDepthR::new((self.bits & 0xff) as u8)
20724            }
20725            #[doc = "Bits 8:15 - RX right FIFO depth"]
20726            #[inline(always)]
20727            pub fn right_depth(&self) -> RightDepthR {
20728                RightDepthR::new(((self.bits >> 8) & 0xff) as u8)
20729            }
20730        }
20731        impl W {}
20732        #[doc = "RX status register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_sta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_sta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20733        pub struct RxStaSpec;
20734        impl crate::RegisterSpec for RxStaSpec {
20735            type Ux = u32;
20736        }
20737        #[doc = "`read()` method returns [`rx_sta::R`](R) reader structure"]
20738        impl crate::Readable for RxStaSpec {}
20739        #[doc = "`write(|w| ..)` method takes [`rx_sta::W`](W) writer structure"]
20740        impl crate::Writable for RxStaSpec {
20741            type Safety = crate::Unsafe;
20742        }
20743        #[doc = "`reset()` method sets RX_STA to value 0"]
20744        impl crate::Resettable for RxStaSpec {}
20745    }
20746    #[doc = "TX_STA (rw) register accessor: TX status register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_sta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_sta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_sta`] module"]
20747    #[doc(alias = "TX_STA")]
20748    pub type TxSta = crate::Reg<tx_sta::TxStaSpec>;
20749    #[doc = "TX status register"]
20750    pub mod tx_sta {
20751        #[doc = "Register `TX_STA` reader"]
20752        pub type R = crate::R<TxStaSpec>;
20753        #[doc = "Register `TX_STA` writer"]
20754        pub type W = crate::W<TxStaSpec>;
20755        #[doc = "Field `left_depth` reader - TX left FIFO depth"]
20756        pub type LeftDepthR = crate::FieldReader;
20757        #[doc = "Field `right_depth` reader - TX right FIFO depth"]
20758        pub type RightDepthR = crate::FieldReader;
20759        impl R {
20760            #[doc = "Bits 0:7 - TX left FIFO depth"]
20761            #[inline(always)]
20762            pub fn left_depth(&self) -> LeftDepthR {
20763                LeftDepthR::new((self.bits & 0xff) as u8)
20764            }
20765            #[doc = "Bits 8:15 - TX right FIFO depth"]
20766            #[inline(always)]
20767            pub fn right_depth(&self) -> RightDepthR {
20768                RightDepthR::new(((self.bits >> 8) & 0xff) as u8)
20769            }
20770        }
20771        impl W {}
20772        #[doc = "TX status register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_sta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_sta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20773        pub struct TxStaSpec;
20774        impl crate::RegisterSpec for TxStaSpec {
20775            type Ux = u32;
20776        }
20777        #[doc = "`read()` method returns [`tx_sta::R`](R) reader structure"]
20778        impl crate::Readable for TxStaSpec {}
20779        #[doc = "`write(|w| ..)` method takes [`tx_sta::W`](W) writer structure"]
20780        impl crate::Writable for TxStaSpec {
20781            type Safety = crate::Unsafe;
20782        }
20783        #[doc = "`reset()` method sets TX_STA to value 0"]
20784        impl crate::Resettable for TxStaSpec {}
20785    }
20786    #[doc = "DATA_WIDTH_SET (rw) register accessor: Data width register\n\nYou can [`read`](crate::Reg::read) this register and get [`data_width_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_width_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_width_set`] module"]
20787    #[doc(alias = "DATA_WIDTH_SET")]
20788    pub type DataWidthSet = crate::Reg<data_width_set::DataWidthSetSpec>;
20789    #[doc = "Data width register"]
20790    pub mod data_width_set {
20791        #[doc = "Register `DATA_WIDTH_SET` reader"]
20792        pub type R = crate::R<DataWidthSetSpec>;
20793        #[doc = "Register `DATA_WIDTH_SET` writer"]
20794        pub type W = crate::W<DataWidthSetSpec>;
20795        #[doc = "Field `tx_mode` reader - TX data width mode"]
20796        pub type TxModeR = crate::FieldReader;
20797        #[doc = "Field `tx_mode` writer - TX data width mode"]
20798        pub type TxModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
20799        #[doc = "Field `rx_mode` reader - RX data width mode"]
20800        pub type RxModeR = crate::FieldReader;
20801        #[doc = "Field `rx_mode` writer - RX data width mode"]
20802        pub type RxModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
20803        impl R {
20804            #[doc = "Bits 0:2 - TX data width mode"]
20805            #[inline(always)]
20806            pub fn tx_mode(&self) -> TxModeR {
20807                TxModeR::new((self.bits & 7) as u8)
20808            }
20809            #[doc = "Bits 8:10 - RX data width mode"]
20810            #[inline(always)]
20811            pub fn rx_mode(&self) -> RxModeR {
20812                RxModeR::new(((self.bits >> 8) & 7) as u8)
20813            }
20814        }
20815        impl W {
20816            #[doc = "Bits 0:2 - TX data width mode"]
20817            #[inline(always)]
20818            pub fn tx_mode(&mut self) -> TxModeW<'_, DataWidthSetSpec> {
20819                TxModeW::new(self, 0)
20820            }
20821            #[doc = "Bits 8:10 - RX data width mode"]
20822            #[inline(always)]
20823            pub fn rx_mode(&mut self) -> RxModeW<'_, DataWidthSetSpec> {
20824                RxModeW::new(self, 8)
20825            }
20826        }
20827        #[doc = "Data width register\n\nYou can [`read`](crate::Reg::read) this register and get [`data_width_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_width_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20828        pub struct DataWidthSetSpec;
20829        impl crate::RegisterSpec for DataWidthSetSpec {
20830            type Ux = u32;
20831        }
20832        #[doc = "`read()` method returns [`data_width_set::R`](R) reader structure"]
20833        impl crate::Readable for DataWidthSetSpec {}
20834        #[doc = "`write(|w| ..)` method takes [`data_width_set::W`](W) writer structure"]
20835        impl crate::Writable for DataWidthSetSpec {
20836            type Safety = crate::Unsafe;
20837        }
20838        #[doc = "`reset()` method sets DATA_WIDTH_SET to value 0"]
20839        impl crate::Resettable for DataWidthSetSpec {}
20840    }
20841    #[doc = "SIGNED_EXT (rw) register accessor: Signed extension enable\n\nYou can [`read`](crate::Reg::read) this register and get [`signed_ext::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`signed_ext::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@signed_ext`] module"]
20842    #[doc(alias = "SIGNED_EXT")]
20843    pub type SignedExt = crate::Reg<signed_ext::SignedExtSpec>;
20844    #[doc = "Signed extension enable"]
20845    pub mod signed_ext {
20846        #[doc = "Register `SIGNED_EXT` reader"]
20847        pub type R = crate::R<SignedExtSpec>;
20848        #[doc = "Register `SIGNED_EXT` writer"]
20849        pub type W = crate::W<SignedExtSpec>;
20850        #[doc = "Field `signed_ext_en` reader - Signed extension enable"]
20851        pub type SignedExtEnR = crate::BitReader;
20852        #[doc = "Field `signed_ext_en` writer - Signed extension enable"]
20853        pub type SignedExtEnW<'a, REG> = crate::BitWriter<'a, REG>;
20854        impl R {
20855            #[doc = "Bit 0 - Signed extension enable"]
20856            #[inline(always)]
20857            pub fn signed_ext_en(&self) -> SignedExtEnR {
20858                SignedExtEnR::new((self.bits & 1) != 0)
20859            }
20860        }
20861        impl W {
20862            #[doc = "Bit 0 - Signed extension enable"]
20863            #[inline(always)]
20864            pub fn signed_ext_en(&mut self) -> SignedExtEnW<'_, SignedExtSpec> {
20865                SignedExtEnW::new(self, 0)
20866            }
20867        }
20868        #[doc = "Signed extension enable\n\nYou can [`read`](crate::Reg::read) this register and get [`signed_ext::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`signed_ext::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20869        pub struct SignedExtSpec;
20870        impl crate::RegisterSpec for SignedExtSpec {
20871            type Ux = u32;
20872        }
20873        #[doc = "`read()` method returns [`signed_ext::R`](R) reader structure"]
20874        impl crate::Readable for SignedExtSpec {}
20875        #[doc = "`write(|w| ..)` method takes [`signed_ext::W`](W) writer structure"]
20876        impl crate::Writable for SignedExtSpec {
20877            type Safety = crate::Unsafe;
20878        }
20879        #[doc = "`reset()` method sets SIGNED_EXT to value 0"]
20880        impl crate::Resettable for SignedExtSpec {}
20881    }
20882    #[doc = "INTMASK (rw) register accessor: Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`intmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intmask`] module"]
20883    #[doc(alias = "INTMASK")]
20884    pub type Intmask = crate::Reg<intmask::IntmaskSpec>;
20885    #[doc = "Interrupt mask register"]
20886    pub mod intmask {
20887        #[doc = "Register `INTMASK` reader"]
20888        pub type R = crate::R<IntmaskSpec>;
20889        #[doc = "Register `INTMASK` writer"]
20890        pub type W = crate::W<IntmaskSpec>;
20891        #[doc = "Field `rx_int_mask` reader - RX interrupt mask"]
20892        pub type RxIntMaskR = crate::BitReader;
20893        #[doc = "Field `rx_int_mask` writer - RX interrupt mask"]
20894        pub type RxIntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
20895        #[doc = "Field `tx_int_mask` reader - TX interrupt mask"]
20896        pub type TxIntMaskR = crate::BitReader;
20897        #[doc = "Field `tx_int_mask` writer - TX interrupt mask"]
20898        pub type TxIntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
20899        #[doc = "Field `rx_overflow_mask` reader - RX overflow mask"]
20900        pub type RxOverflowMaskR = crate::BitReader;
20901        #[doc = "Field `rx_overflow_mask` writer - RX overflow mask"]
20902        pub type RxOverflowMaskW<'a, REG> = crate::BitWriter<'a, REG>;
20903        #[doc = "Field `tx_underflow_mask` reader - TX underflow mask"]
20904        pub type TxUnderflowMaskR = crate::BitReader;
20905        #[doc = "Field `tx_underflow_mask` writer - TX underflow mask"]
20906        pub type TxUnderflowMaskW<'a, REG> = crate::BitWriter<'a, REG>;
20907        impl R {
20908            #[doc = "Bit 0 - RX interrupt mask"]
20909            #[inline(always)]
20910            pub fn rx_int_mask(&self) -> RxIntMaskR {
20911                RxIntMaskR::new((self.bits & 1) != 0)
20912            }
20913            #[doc = "Bit 1 - TX interrupt mask"]
20914            #[inline(always)]
20915            pub fn tx_int_mask(&self) -> TxIntMaskR {
20916                TxIntMaskR::new(((self.bits >> 1) & 1) != 0)
20917            }
20918            #[doc = "Bit 2 - RX overflow mask"]
20919            #[inline(always)]
20920            pub fn rx_overflow_mask(&self) -> RxOverflowMaskR {
20921                RxOverflowMaskR::new(((self.bits >> 2) & 1) != 0)
20922            }
20923            #[doc = "Bit 3 - TX underflow mask"]
20924            #[inline(always)]
20925            pub fn tx_underflow_mask(&self) -> TxUnderflowMaskR {
20926                TxUnderflowMaskR::new(((self.bits >> 3) & 1) != 0)
20927            }
20928        }
20929        impl W {
20930            #[doc = "Bit 0 - RX interrupt mask"]
20931            #[inline(always)]
20932            pub fn rx_int_mask(&mut self) -> RxIntMaskW<'_, IntmaskSpec> {
20933                RxIntMaskW::new(self, 0)
20934            }
20935            #[doc = "Bit 1 - TX interrupt mask"]
20936            #[inline(always)]
20937            pub fn tx_int_mask(&mut self) -> TxIntMaskW<'_, IntmaskSpec> {
20938                TxIntMaskW::new(self, 1)
20939            }
20940            #[doc = "Bit 2 - RX overflow mask"]
20941            #[inline(always)]
20942            pub fn rx_overflow_mask(&mut self) -> RxOverflowMaskW<'_, IntmaskSpec> {
20943                RxOverflowMaskW::new(self, 2)
20944            }
20945            #[doc = "Bit 3 - TX underflow mask"]
20946            #[inline(always)]
20947            pub fn tx_underflow_mask(&mut self) -> TxUnderflowMaskW<'_, IntmaskSpec> {
20948                TxUnderflowMaskW::new(self, 3)
20949            }
20950        }
20951        #[doc = "Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`intmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20952        pub struct IntmaskSpec;
20953        impl crate::RegisterSpec for IntmaskSpec {
20954            type Ux = u32;
20955        }
20956        #[doc = "`read()` method returns [`intmask::R`](R) reader structure"]
20957        impl crate::Readable for IntmaskSpec {}
20958        #[doc = "`write(|w| ..)` method takes [`intmask::W`](W) writer structure"]
20959        impl crate::Writable for IntmaskSpec {
20960            type Safety = crate::Unsafe;
20961        }
20962        #[doc = "`reset()` method sets INTMASK to value 0"]
20963        impl crate::Resettable for IntmaskSpec {}
20964    }
20965    #[doc = "I2S_CRG (rw) register accessor: I2S clock/reset generator\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_crg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_crg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_crg`] module"]
20966    #[doc(alias = "I2S_CRG")]
20967    pub type I2sCrg = crate::Reg<i2s_crg::I2sCrgSpec>;
20968    #[doc = "I2S clock/reset generator"]
20969    pub mod i2s_crg {
20970        #[doc = "Register `I2S_CRG` reader"]
20971        pub type R = crate::R<I2sCrgSpec>;
20972        #[doc = "Register `I2S_CRG` writer"]
20973        pub type W = crate::W<I2sCrgSpec>;
20974        #[doc = "Field `bclk_div` reader - BCLK divider"]
20975        pub type BclkDivR = crate::FieldReader;
20976        #[doc = "Field `bclk_div` writer - BCLK divider"]
20977        pub type BclkDivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
20978        #[doc = "Field `clk_en` reader - Clock enable"]
20979        pub type ClkEnR = crate::BitReader;
20980        #[doc = "Field `clk_en` writer - Clock enable"]
20981        pub type ClkEnW<'a, REG> = crate::BitWriter<'a, REG>;
20982        #[doc = "Field `clk_sel` reader - Clock source select"]
20983        pub type ClkSelR = crate::BitReader;
20984        #[doc = "Field `clk_sel` writer - Clock source select"]
20985        pub type ClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
20986        impl R {
20987            #[doc = "Bits 0:7 - BCLK divider"]
20988            #[inline(always)]
20989            pub fn bclk_div(&self) -> BclkDivR {
20990                BclkDivR::new((self.bits & 0xff) as u8)
20991            }
20992            #[doc = "Bit 8 - Clock enable"]
20993            #[inline(always)]
20994            pub fn clk_en(&self) -> ClkEnR {
20995                ClkEnR::new(((self.bits >> 8) & 1) != 0)
20996            }
20997            #[doc = "Bit 9 - Clock source select"]
20998            #[inline(always)]
20999            pub fn clk_sel(&self) -> ClkSelR {
21000                ClkSelR::new(((self.bits >> 9) & 1) != 0)
21001            }
21002        }
21003        impl W {
21004            #[doc = "Bits 0:7 - BCLK divider"]
21005            #[inline(always)]
21006            pub fn bclk_div(&mut self) -> BclkDivW<'_, I2sCrgSpec> {
21007                BclkDivW::new(self, 0)
21008            }
21009            #[doc = "Bit 8 - Clock enable"]
21010            #[inline(always)]
21011            pub fn clk_en(&mut self) -> ClkEnW<'_, I2sCrgSpec> {
21012                ClkEnW::new(self, 8)
21013            }
21014            #[doc = "Bit 9 - Clock source select"]
21015            #[inline(always)]
21016            pub fn clk_sel(&mut self) -> ClkSelW<'_, I2sCrgSpec> {
21017                ClkSelW::new(self, 9)
21018            }
21019        }
21020        #[doc = "I2S clock/reset generator\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_crg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_crg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21021        pub struct I2sCrgSpec;
21022        impl crate::RegisterSpec for I2sCrgSpec {
21023            type Ux = u32;
21024        }
21025        #[doc = "`read()` method returns [`i2s_crg::R`](R) reader structure"]
21026        impl crate::Readable for I2sCrgSpec {}
21027        #[doc = "`write(|w| ..)` method takes [`i2s_crg::W`](W) writer structure"]
21028        impl crate::Writable for I2sCrgSpec {
21029            type Safety = crate::Unsafe;
21030        }
21031        #[doc = "`reset()` method sets I2S_CRG to value 0"]
21032        impl crate::Resettable for I2sCrgSpec {}
21033    }
21034    #[doc = "I2S_BCLK_DIV_NUM (rw) register accessor: BCLK divider number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_bclk_div_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_bclk_div_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_bclk_div_num`] module"]
21035    #[doc(alias = "I2S_BCLK_DIV_NUM")]
21036    pub type I2sBclkDivNum = crate::Reg<i2s_bclk_div_num::I2sBclkDivNumSpec>;
21037    #[doc = "BCLK divider number"]
21038    pub mod i2s_bclk_div_num {
21039        #[doc = "Register `I2S_BCLK_DIV_NUM` reader"]
21040        pub type R = crate::R<I2sBclkDivNumSpec>;
21041        #[doc = "Register `I2S_BCLK_DIV_NUM` writer"]
21042        pub type W = crate::W<I2sBclkDivNumSpec>;
21043        #[doc = "Field `bclk_div_num` reader - BCLK divider number"]
21044        pub type BclkDivNumR = crate::FieldReader;
21045        #[doc = "Field `bclk_div_num` writer - BCLK divider number"]
21046        pub type BclkDivNumW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
21047        impl R {
21048            #[doc = "Bits 0:6 - BCLK divider number"]
21049            #[inline(always)]
21050            pub fn bclk_div_num(&self) -> BclkDivNumR {
21051                BclkDivNumR::new((self.bits & 0x7f) as u8)
21052            }
21053        }
21054        impl W {
21055            #[doc = "Bits 0:6 - BCLK divider number"]
21056            #[inline(always)]
21057            pub fn bclk_div_num(&mut self) -> BclkDivNumW<'_, I2sBclkDivNumSpec> {
21058                BclkDivNumW::new(self, 0)
21059            }
21060        }
21061        #[doc = "BCLK divider number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_bclk_div_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_bclk_div_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21062        pub struct I2sBclkDivNumSpec;
21063        impl crate::RegisterSpec for I2sBclkDivNumSpec {
21064            type Ux = u32;
21065        }
21066        #[doc = "`read()` method returns [`i2s_bclk_div_num::R`](R) reader structure"]
21067        impl crate::Readable for I2sBclkDivNumSpec {}
21068        #[doc = "`write(|w| ..)` method takes [`i2s_bclk_div_num::W`](W) writer structure"]
21069        impl crate::Writable for I2sBclkDivNumSpec {
21070            type Safety = crate::Unsafe;
21071        }
21072        #[doc = "`reset()` method sets I2S_BCLK_DIV_NUM to value 0"]
21073        impl crate::Resettable for I2sBclkDivNumSpec {}
21074    }
21075    #[doc = "I2S_FS_DIV_NUM (rw) register accessor: FS divider number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_fs_div_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_fs_div_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_fs_div_num`] module"]
21076    #[doc(alias = "I2S_FS_DIV_NUM")]
21077    pub type I2sFsDivNum = crate::Reg<i2s_fs_div_num::I2sFsDivNumSpec>;
21078    #[doc = "FS divider number"]
21079    pub mod i2s_fs_div_num {
21080        #[doc = "Register `I2S_FS_DIV_NUM` reader"]
21081        pub type R = crate::R<I2sFsDivNumSpec>;
21082        #[doc = "Register `I2S_FS_DIV_NUM` writer"]
21083        pub type W = crate::W<I2sFsDivNumSpec>;
21084        #[doc = "Field `fs_div_num` reader - FS divider number"]
21085        pub type FsDivNumR = crate::FieldReader<u16>;
21086        #[doc = "Field `fs_div_num` writer - FS divider number"]
21087        pub type FsDivNumW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
21088        impl R {
21089            #[doc = "Bits 0:9 - FS divider number"]
21090            #[inline(always)]
21091            pub fn fs_div_num(&self) -> FsDivNumR {
21092                FsDivNumR::new((self.bits & 0x03ff) as u16)
21093            }
21094        }
21095        impl W {
21096            #[doc = "Bits 0:9 - FS divider number"]
21097            #[inline(always)]
21098            pub fn fs_div_num(&mut self) -> FsDivNumW<'_, I2sFsDivNumSpec> {
21099                FsDivNumW::new(self, 0)
21100            }
21101        }
21102        #[doc = "FS divider number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_fs_div_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_fs_div_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21103        pub struct I2sFsDivNumSpec;
21104        impl crate::RegisterSpec for I2sFsDivNumSpec {
21105            type Ux = u32;
21106        }
21107        #[doc = "`read()` method returns [`i2s_fs_div_num::R`](R) reader structure"]
21108        impl crate::Readable for I2sFsDivNumSpec {}
21109        #[doc = "`write(|w| ..)` method takes [`i2s_fs_div_num::W`](W) writer structure"]
21110        impl crate::Writable for I2sFsDivNumSpec {
21111            type Safety = crate::Unsafe;
21112        }
21113        #[doc = "`reset()` method sets I2S_FS_DIV_NUM to value 0"]
21114        impl crate::Resettable for I2sFsDivNumSpec {}
21115    }
21116    #[doc = "I2S_FS_DIV_RATIO_NUM (rw) register accessor: FS divider ratio number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_fs_div_ratio_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_fs_div_ratio_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_fs_div_ratio_num`] module"]
21117    #[doc(alias = "I2S_FS_DIV_RATIO_NUM")]
21118    pub type I2sFsDivRatioNum = crate::Reg<i2s_fs_div_ratio_num::I2sFsDivRatioNumSpec>;
21119    #[doc = "FS divider ratio number"]
21120    pub mod i2s_fs_div_ratio_num {
21121        #[doc = "Register `I2S_FS_DIV_RATIO_NUM` reader"]
21122        pub type R = crate::R<I2sFsDivRatioNumSpec>;
21123        #[doc = "Register `I2S_FS_DIV_RATIO_NUM` writer"]
21124        pub type W = crate::W<I2sFsDivRatioNumSpec>;
21125        #[doc = "Field `fs_div_ratio_num` reader - FS divider ratio number"]
21126        pub type FsDivRatioNumR = crate::FieldReader<u16>;
21127        #[doc = "Field `fs_div_ratio_num` writer - FS divider ratio number"]
21128        pub type FsDivRatioNumW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
21129        impl R {
21130            #[doc = "Bits 0:10 - FS divider ratio number"]
21131            #[inline(always)]
21132            pub fn fs_div_ratio_num(&self) -> FsDivRatioNumR {
21133                FsDivRatioNumR::new((self.bits & 0x07ff) as u16)
21134            }
21135        }
21136        impl W {
21137            #[doc = "Bits 0:10 - FS divider ratio number"]
21138            #[inline(always)]
21139            pub fn fs_div_ratio_num(&mut self) -> FsDivRatioNumW<'_, I2sFsDivRatioNumSpec> {
21140                FsDivRatioNumW::new(self, 0)
21141            }
21142        }
21143        #[doc = "FS divider ratio number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_fs_div_ratio_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_fs_div_ratio_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21144        pub struct I2sFsDivRatioNumSpec;
21145        impl crate::RegisterSpec for I2sFsDivRatioNumSpec {
21146            type Ux = u32;
21147        }
21148        #[doc = "`read()` method returns [`i2s_fs_div_ratio_num::R`](R) reader structure"]
21149        impl crate::Readable for I2sFsDivRatioNumSpec {}
21150        #[doc = "`write(|w| ..)` method takes [`i2s_fs_div_ratio_num::W`](W) writer structure"]
21151        impl crate::Writable for I2sFsDivRatioNumSpec {
21152            type Safety = crate::Unsafe;
21153        }
21154        #[doc = "`reset()` method sets I2S_FS_DIV_RATIO_NUM to value 0"]
21155        impl crate::Resettable for I2sFsDivRatioNumSpec {}
21156    }
21157}
21158#[doc = "Low-speed ADC controller (12-bit SAR, 6 channels, v154)"]
21159pub type Lsadc = crate::Periph<lsadc::RegisterBlock, 0x4400_c000>;
21160impl core::fmt::Debug for Lsadc {
21161    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21162        f.debug_struct("Lsadc").finish()
21163    }
21164}
21165#[doc = "Low-speed ADC controller (12-bit SAR, 6 channels, v154)"]
21166pub mod lsadc {
21167    #[repr(C)]
21168    #[doc = "Register block"]
21169    pub struct RegisterBlock {
21170        lsadc_ctrl_0: LsadcCtrl0,
21171        lsadc_ctrl_1: LsadcCtrl1,
21172        lsadc_ctrl_2: LsadcCtrl2,
21173        lsadc_ctrl_3: LsadcCtrl3,
21174        lsadc_ctrl_4: LsadcCtrl4,
21175        lsadc_ctrl_6: LsadcCtrl6,
21176        lsadc_ctrl_7: LsadcCtrl7,
21177        lsadc_ctrl_8: LsadcCtrl8,
21178        lsadc_ctrl_9: LsadcCtrl9,
21179        lsadc_ctrl_11: LsadcCtrl11,
21180        lsadc_ctrl_12: LsadcCtrl12,
21181        _reserved11: [u8; 0xb0],
21182        cfg_data_sel: CfgDataSel,
21183        cfg_offset: CfgOffset,
21184        cfg_gain: CfgGain,
21185        cfg_cic_filter_en: CfgCicFilterEn,
21186        cfg_cic_osr: CfgCicOsr,
21187    }
21188    impl RegisterBlock {
21189        #[doc = "0x00 - Scan config (adc_ctrl_data): per-channel enable + sample timing. Set via hal_adc_auto_scan_mode_set."]
21190        #[inline(always)]
21191        pub const fn lsadc_ctrl_0(&self) -> &LsadcCtrl0 {
21192            &self.lsadc_ctrl_0
21193        }
21194        #[doc = "0x04 - FIFO status + interrupt waterline (adc_fifo_data)"]
21195        #[inline(always)]
21196        pub const fn lsadc_ctrl_1(&self) -> &LsadcCtrl1 {
21197            &self.lsadc_ctrl_1
21198        }
21199        #[doc = "0x08 - Interrupt mask/status (adc_irg_data)"]
21200        #[inline(always)]
21201        pub const fn lsadc_ctrl_2(&self) -> &LsadcCtrl2 {
21202            &self.lsadc_ctrl_2
21203        }
21204        #[doc = "0x0c - ADC control register 3 (analog, reserved)"]
21205        #[inline(always)]
21206        pub const fn lsadc_ctrl_3(&self) -> &LsadcCtrl3 {
21207            &self.lsadc_ctrl_3
21208        }
21209        #[doc = "0x10 - ADC control register 4 (analog, reserved)"]
21210        #[inline(always)]
21211        pub const fn lsadc_ctrl_4(&self) -> &LsadcCtrl4 {
21212            &self.lsadc_ctrl_4
21213        }
21214        #[doc = "0x14 - ADC control register 6 (analog, reserved)"]
21215        #[inline(always)]
21216        pub const fn lsadc_ctrl_6(&self) -> &LsadcCtrl6 {
21217            &self.lsadc_ctrl_6
21218        }
21219        #[doc = "0x18 - ADC control register 7 (analog, reserved)"]
21220        #[inline(always)]
21221        pub const fn lsadc_ctrl_7(&self) -> &LsadcCtrl7 {
21222            &self.lsadc_ctrl_7
21223        }
21224        #[doc = "0x1c - Scan start/stop (adc_scan_start_and_stop_data)"]
21225        #[inline(always)]
21226        pub const fn lsadc_ctrl_8(&self) -> &LsadcCtrl8 {
21227            &self.lsadc_ctrl_8
21228        }
21229        #[doc = "0x20 - FIFO read data (adc_fifo_read_data): 14-bit code + 3-bit channel"]
21230        #[inline(always)]
21231        pub const fn lsadc_ctrl_9(&self) -> &LsadcCtrl9 {
21232            &self.lsadc_ctrl_9
21233        }
21234        #[doc = "0x24 - Analog enable/reset (adc_enable_data)"]
21235        #[inline(always)]
21236        pub const fn lsadc_ctrl_11(&self) -> &LsadcCtrl11 {
21237            &self.lsadc_ctrl_11
21238        }
21239        #[doc = "0x28 - ADC control register 12 (analog, reserved)"]
21240        #[inline(always)]
21241        pub const fn lsadc_ctrl_12(&self) -> &LsadcCtrl12 {
21242            &self.lsadc_ctrl_12
21243        }
21244        #[doc = "0xdc - Data output select (base+0xDC)"]
21245        #[inline(always)]
21246        pub const fn cfg_data_sel(&self) -> &CfgDataSel {
21247            &self.cfg_data_sel
21248        }
21249        #[doc = "0xe0 - Offset correction (base+0xE0)"]
21250        #[inline(always)]
21251        pub const fn cfg_offset(&self) -> &CfgOffset {
21252            &self.cfg_offset
21253        }
21254        #[doc = "0xe4 - Gain correction (base+0xE4)"]
21255        #[inline(always)]
21256        pub const fn cfg_gain(&self) -> &CfgGain {
21257            &self.cfg_gain
21258        }
21259        #[doc = "0xe8 - CIC filter enable (base+0xE8)"]
21260        #[inline(always)]
21261        pub const fn cfg_cic_filter_en(&self) -> &CfgCicFilterEn {
21262            &self.cfg_cic_filter_en
21263        }
21264        #[doc = "0xec - CIC oversampling ratio (base+0xEC)"]
21265        #[inline(always)]
21266        pub const fn cfg_cic_osr(&self) -> &CfgCicOsr {
21267            &self.cfg_cic_osr
21268        }
21269    }
21270    #[doc = "LSADC_CTRL_0 (rw) register accessor: Scan config (adc_ctrl_data): per-channel enable + sample timing. Set via hal_adc_auto_scan_mode_set.\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_0`] module"]
21271    #[doc(alias = "LSADC_CTRL_0")]
21272    pub type LsadcCtrl0 = crate::Reg<lsadc_ctrl_0::LsadcCtrl0Spec>;
21273    #[doc = "Scan config (adc_ctrl_data): per-channel enable + sample timing. Set via hal_adc_auto_scan_mode_set."]
21274    pub mod lsadc_ctrl_0 {
21275        #[doc = "Register `LSADC_CTRL_0` reader"]
21276        pub type R = crate::R<LsadcCtrl0Spec>;
21277        #[doc = "Register `LSADC_CTRL_0` writer"]
21278        pub type W = crate::W<LsadcCtrl0Spec>;
21279        #[doc = "Field `channel` reader - Per-channel enable bitmask (bit n enables channel n, 0-5)"]
21280        pub type ChannelR = crate::FieldReader;
21281        #[doc = "Field `channel` writer - Per-channel enable bitmask (bit n enables channel n, 0-5)"]
21282        pub type ChannelW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
21283        #[doc = "Field `equ_model_sel` reader - Averaging mode: 0=1x, 1=2x, 2=4x, 3=8x samples"]
21284        pub type EquModelSelR = crate::FieldReader;
21285        #[doc = "Field `equ_model_sel` writer - Averaging mode: 0=1x, 1=2x, 2=4x, 3=8x samples"]
21286        pub type EquModelSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21287        #[doc = "Field `sample_cnt` reader - Sample count (5-bit)"]
21288        pub type SampleCntR = crate::FieldReader;
21289        #[doc = "Field `sample_cnt` writer - Sample count (5-bit)"]
21290        pub type SampleCntW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
21291        #[doc = "Field `start_cnt` reader - Start count (8-bit; SDK field name satrt_cnt)"]
21292        pub type StartCntR = crate::FieldReader;
21293        #[doc = "Field `start_cnt` writer - Start count (8-bit; SDK field name satrt_cnt)"]
21294        pub type StartCntW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
21295        #[doc = "Field `cast_cnt` reader - Cast count (7-bit)"]
21296        pub type CastCntR = crate::FieldReader;
21297        #[doc = "Field `cast_cnt` writer - Cast count (7-bit)"]
21298        pub type CastCntW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
21299        impl R {
21300            #[doc = "Bits 0:5 - Per-channel enable bitmask (bit n enables channel n, 0-5)"]
21301            #[inline(always)]
21302            pub fn channel(&self) -> ChannelR {
21303                ChannelR::new((self.bits & 0x3f) as u8)
21304            }
21305            #[doc = "Bits 6:7 - Averaging mode: 0=1x, 1=2x, 2=4x, 3=8x samples"]
21306            #[inline(always)]
21307            pub fn equ_model_sel(&self) -> EquModelSelR {
21308                EquModelSelR::new(((self.bits >> 6) & 3) as u8)
21309            }
21310            #[doc = "Bits 8:12 - Sample count (5-bit)"]
21311            #[inline(always)]
21312            pub fn sample_cnt(&self) -> SampleCntR {
21313                SampleCntR::new(((self.bits >> 8) & 0x1f) as u8)
21314            }
21315            #[doc = "Bits 13:20 - Start count (8-bit; SDK field name satrt_cnt)"]
21316            #[inline(always)]
21317            pub fn start_cnt(&self) -> StartCntR {
21318                StartCntR::new(((self.bits >> 13) & 0xff) as u8)
21319            }
21320            #[doc = "Bits 21:27 - Cast count (7-bit)"]
21321            #[inline(always)]
21322            pub fn cast_cnt(&self) -> CastCntR {
21323                CastCntR::new(((self.bits >> 21) & 0x7f) as u8)
21324            }
21325        }
21326        impl W {
21327            #[doc = "Bits 0:5 - Per-channel enable bitmask (bit n enables channel n, 0-5)"]
21328            #[inline(always)]
21329            pub fn channel(&mut self) -> ChannelW<'_, LsadcCtrl0Spec> {
21330                ChannelW::new(self, 0)
21331            }
21332            #[doc = "Bits 6:7 - Averaging mode: 0=1x, 1=2x, 2=4x, 3=8x samples"]
21333            #[inline(always)]
21334            pub fn equ_model_sel(&mut self) -> EquModelSelW<'_, LsadcCtrl0Spec> {
21335                EquModelSelW::new(self, 6)
21336            }
21337            #[doc = "Bits 8:12 - Sample count (5-bit)"]
21338            #[inline(always)]
21339            pub fn sample_cnt(&mut self) -> SampleCntW<'_, LsadcCtrl0Spec> {
21340                SampleCntW::new(self, 8)
21341            }
21342            #[doc = "Bits 13:20 - Start count (8-bit; SDK field name satrt_cnt)"]
21343            #[inline(always)]
21344            pub fn start_cnt(&mut self) -> StartCntW<'_, LsadcCtrl0Spec> {
21345                StartCntW::new(self, 13)
21346            }
21347            #[doc = "Bits 21:27 - Cast count (7-bit)"]
21348            #[inline(always)]
21349            pub fn cast_cnt(&mut self) -> CastCntW<'_, LsadcCtrl0Spec> {
21350                CastCntW::new(self, 21)
21351            }
21352        }
21353        #[doc = "Scan config (adc_ctrl_data): per-channel enable + sample timing. Set via hal_adc_auto_scan_mode_set.\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21354        pub struct LsadcCtrl0Spec;
21355        impl crate::RegisterSpec for LsadcCtrl0Spec {
21356            type Ux = u32;
21357        }
21358        #[doc = "`read()` method returns [`lsadc_ctrl_0::R`](R) reader structure"]
21359        impl crate::Readable for LsadcCtrl0Spec {}
21360        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_0::W`](W) writer structure"]
21361        impl crate::Writable for LsadcCtrl0Spec {
21362            type Safety = crate::Unsafe;
21363        }
21364        #[doc = "`reset()` method sets LSADC_CTRL_0 to value 0"]
21365        impl crate::Resettable for LsadcCtrl0Spec {}
21366    }
21367    #[doc = "LSADC_CTRL_1 (rw) register accessor: FIFO status + interrupt waterline (adc_fifo_data)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_1`] module"]
21368    #[doc(alias = "LSADC_CTRL_1")]
21369    pub type LsadcCtrl1 = crate::Reg<lsadc_ctrl_1::LsadcCtrl1Spec>;
21370    #[doc = "FIFO status + interrupt waterline (adc_fifo_data)"]
21371    pub mod lsadc_ctrl_1 {
21372        #[doc = "Register `LSADC_CTRL_1` reader"]
21373        pub type R = crate::R<LsadcCtrl1Spec>;
21374        #[doc = "Register `LSADC_CTRL_1` writer"]
21375        pub type W = crate::W<LsadcCtrl1Spec>;
21376        #[doc = "Field `rxintsize` reader - RX FIFO interrupt waterline (3-bit)"]
21377        pub type RxintsizeR = crate::FieldReader;
21378        #[doc = "Field `rxintsize` writer - RX FIFO interrupt waterline (3-bit)"]
21379        pub type RxintsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21380        #[doc = "Field `rne` reader - RX FIFO not empty"]
21381        pub type RneR = crate::BitReader;
21382        #[doc = "Field `rff` reader - RX FIFO full"]
21383        pub type RffR = crate::BitReader;
21384        #[doc = "Field `bsy` reader - ADC busy"]
21385        pub type BsyR = crate::BitReader;
21386        impl R {
21387            #[doc = "Bits 0:2 - RX FIFO interrupt waterline (3-bit)"]
21388            #[inline(always)]
21389            pub fn rxintsize(&self) -> RxintsizeR {
21390                RxintsizeR::new((self.bits & 7) as u8)
21391            }
21392            #[doc = "Bit 3 - RX FIFO not empty"]
21393            #[inline(always)]
21394            pub fn rne(&self) -> RneR {
21395                RneR::new(((self.bits >> 3) & 1) != 0)
21396            }
21397            #[doc = "Bit 4 - RX FIFO full"]
21398            #[inline(always)]
21399            pub fn rff(&self) -> RffR {
21400                RffR::new(((self.bits >> 4) & 1) != 0)
21401            }
21402            #[doc = "Bit 5 - ADC busy"]
21403            #[inline(always)]
21404            pub fn bsy(&self) -> BsyR {
21405                BsyR::new(((self.bits >> 5) & 1) != 0)
21406            }
21407        }
21408        impl W {
21409            #[doc = "Bits 0:2 - RX FIFO interrupt waterline (3-bit)"]
21410            #[inline(always)]
21411            pub fn rxintsize(&mut self) -> RxintsizeW<'_, LsadcCtrl1Spec> {
21412                RxintsizeW::new(self, 0)
21413            }
21414        }
21415        #[doc = "FIFO status + interrupt waterline (adc_fifo_data)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21416        pub struct LsadcCtrl1Spec;
21417        impl crate::RegisterSpec for LsadcCtrl1Spec {
21418            type Ux = u32;
21419        }
21420        #[doc = "`read()` method returns [`lsadc_ctrl_1::R`](R) reader structure"]
21421        impl crate::Readable for LsadcCtrl1Spec {}
21422        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_1::W`](W) writer structure"]
21423        impl crate::Writable for LsadcCtrl1Spec {
21424            type Safety = crate::Unsafe;
21425        }
21426        #[doc = "`reset()` method sets LSADC_CTRL_1 to value 0"]
21427        impl crate::Resettable for LsadcCtrl1Spec {}
21428    }
21429    #[doc = "LSADC_CTRL_2 (rw) register accessor: Interrupt mask/status (adc_irg_data)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_2`] module"]
21430    #[doc(alias = "LSADC_CTRL_2")]
21431    pub type LsadcCtrl2 = crate::Reg<lsadc_ctrl_2::LsadcCtrl2Spec>;
21432    #[doc = "Interrupt mask/status (adc_irg_data)"]
21433    pub mod lsadc_ctrl_2 {
21434        #[doc = "Register `LSADC_CTRL_2` reader"]
21435        pub type R = crate::R<LsadcCtrl2Spec>;
21436        #[doc = "Register `LSADC_CTRL_2` writer"]
21437        pub type W = crate::W<LsadcCtrl2Spec>;
21438        #[doc = "Field `rorim` reader - RX overflow interrupt mask"]
21439        pub type RorimR = crate::BitReader;
21440        #[doc = "Field `rorim` writer - RX overflow interrupt mask"]
21441        pub type RorimW<'a, REG> = crate::BitWriter<'a, REG>;
21442        #[doc = "Field `rxim` reader - RX FIFO interrupt mask"]
21443        pub type RximR = crate::BitReader;
21444        #[doc = "Field `rxim` writer - RX FIFO interrupt mask"]
21445        pub type RximW<'a, REG> = crate::BitWriter<'a, REG>;
21446        #[doc = "Field `rormis` reader - RX overflow masked interrupt status"]
21447        pub type RormisR = crate::BitReader;
21448        #[doc = "Field `rxmis` reader - RX FIFO masked interrupt status"]
21449        pub type RxmisR = crate::BitReader;
21450        #[doc = "Field `rorris` reader - RX overflow raw interrupt status"]
21451        pub type RorrisR = crate::BitReader;
21452        #[doc = "Field `rxris` reader - RX FIFO raw interrupt status"]
21453        pub type RxrisR = crate::BitReader;
21454        impl R {
21455            #[doc = "Bit 0 - RX overflow interrupt mask"]
21456            #[inline(always)]
21457            pub fn rorim(&self) -> RorimR {
21458                RorimR::new((self.bits & 1) != 0)
21459            }
21460            #[doc = "Bit 1 - RX FIFO interrupt mask"]
21461            #[inline(always)]
21462            pub fn rxim(&self) -> RximR {
21463                RximR::new(((self.bits >> 1) & 1) != 0)
21464            }
21465            #[doc = "Bit 2 - RX overflow masked interrupt status"]
21466            #[inline(always)]
21467            pub fn rormis(&self) -> RormisR {
21468                RormisR::new(((self.bits >> 2) & 1) != 0)
21469            }
21470            #[doc = "Bit 3 - RX FIFO masked interrupt status"]
21471            #[inline(always)]
21472            pub fn rxmis(&self) -> RxmisR {
21473                RxmisR::new(((self.bits >> 3) & 1) != 0)
21474            }
21475            #[doc = "Bit 4 - RX overflow raw interrupt status"]
21476            #[inline(always)]
21477            pub fn rorris(&self) -> RorrisR {
21478                RorrisR::new(((self.bits >> 4) & 1) != 0)
21479            }
21480            #[doc = "Bit 5 - RX FIFO raw interrupt status"]
21481            #[inline(always)]
21482            pub fn rxris(&self) -> RxrisR {
21483                RxrisR::new(((self.bits >> 5) & 1) != 0)
21484            }
21485        }
21486        impl W {
21487            #[doc = "Bit 0 - RX overflow interrupt mask"]
21488            #[inline(always)]
21489            pub fn rorim(&mut self) -> RorimW<'_, LsadcCtrl2Spec> {
21490                RorimW::new(self, 0)
21491            }
21492            #[doc = "Bit 1 - RX FIFO interrupt mask"]
21493            #[inline(always)]
21494            pub fn rxim(&mut self) -> RximW<'_, LsadcCtrl2Spec> {
21495                RximW::new(self, 1)
21496            }
21497        }
21498        #[doc = "Interrupt mask/status (adc_irg_data)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21499        pub struct LsadcCtrl2Spec;
21500        impl crate::RegisterSpec for LsadcCtrl2Spec {
21501            type Ux = u32;
21502        }
21503        #[doc = "`read()` method returns [`lsadc_ctrl_2::R`](R) reader structure"]
21504        impl crate::Readable for LsadcCtrl2Spec {}
21505        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_2::W`](W) writer structure"]
21506        impl crate::Writable for LsadcCtrl2Spec {
21507            type Safety = crate::Unsafe;
21508        }
21509        #[doc = "`reset()` method sets LSADC_CTRL_2 to value 0"]
21510        impl crate::Resettable for LsadcCtrl2Spec {}
21511    }
21512    #[doc = "LSADC_CTRL_3 (rw) register accessor: ADC control register 3 (analog, reserved)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_3`] module"]
21513    #[doc(alias = "LSADC_CTRL_3")]
21514    pub type LsadcCtrl3 = crate::Reg<lsadc_ctrl_3::LsadcCtrl3Spec>;
21515    #[doc = "ADC control register 3 (analog, reserved)"]
21516    pub mod lsadc_ctrl_3 {
21517        #[doc = "Register `LSADC_CTRL_3` reader"]
21518        pub type R = crate::R<LsadcCtrl3Spec>;
21519        #[doc = "Register `LSADC_CTRL_3` writer"]
21520        pub type W = crate::W<LsadcCtrl3Spec>;
21521        #[doc = "Field `val` reader - Raw register value"]
21522        pub type ValR = crate::FieldReader<u32>;
21523        #[doc = "Field `val` writer - Raw register value"]
21524        pub type ValW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
21525        impl R {
21526            #[doc = "Bits 0:31 - Raw register value"]
21527            #[inline(always)]
21528            pub fn val(&self) -> ValR {
21529                ValR::new(self.bits)
21530            }
21531        }
21532        impl W {
21533            #[doc = "Bits 0:31 - Raw register value"]
21534            #[inline(always)]
21535            pub fn val(&mut self) -> ValW<'_, LsadcCtrl3Spec> {
21536                ValW::new(self, 0)
21537            }
21538        }
21539        #[doc = "ADC control register 3 (analog, reserved)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21540        pub struct LsadcCtrl3Spec;
21541        impl crate::RegisterSpec for LsadcCtrl3Spec {
21542            type Ux = u32;
21543        }
21544        #[doc = "`read()` method returns [`lsadc_ctrl_3::R`](R) reader structure"]
21545        impl crate::Readable for LsadcCtrl3Spec {}
21546        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_3::W`](W) writer structure"]
21547        impl crate::Writable for LsadcCtrl3Spec {
21548            type Safety = crate::Unsafe;
21549        }
21550        #[doc = "`reset()` method sets LSADC_CTRL_3 to value 0"]
21551        impl crate::Resettable for LsadcCtrl3Spec {}
21552    }
21553    #[doc = "LSADC_CTRL_4 (rw) register accessor: ADC control register 4 (analog, reserved)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_4`] module"]
21554    #[doc(alias = "LSADC_CTRL_4")]
21555    pub type LsadcCtrl4 = crate::Reg<lsadc_ctrl_4::LsadcCtrl4Spec>;
21556    #[doc = "ADC control register 4 (analog, reserved)"]
21557    pub mod lsadc_ctrl_4 {
21558        #[doc = "Register `LSADC_CTRL_4` reader"]
21559        pub type R = crate::R<LsadcCtrl4Spec>;
21560        #[doc = "Register `LSADC_CTRL_4` writer"]
21561        pub type W = crate::W<LsadcCtrl4Spec>;
21562        #[doc = "Field `val` reader - Raw register value"]
21563        pub type ValR = crate::FieldReader<u32>;
21564        #[doc = "Field `val` writer - Raw register value"]
21565        pub type ValW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
21566        impl R {
21567            #[doc = "Bits 0:31 - Raw register value"]
21568            #[inline(always)]
21569            pub fn val(&self) -> ValR {
21570                ValR::new(self.bits)
21571            }
21572        }
21573        impl W {
21574            #[doc = "Bits 0:31 - Raw register value"]
21575            #[inline(always)]
21576            pub fn val(&mut self) -> ValW<'_, LsadcCtrl4Spec> {
21577                ValW::new(self, 0)
21578            }
21579        }
21580        #[doc = "ADC control register 4 (analog, reserved)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21581        pub struct LsadcCtrl4Spec;
21582        impl crate::RegisterSpec for LsadcCtrl4Spec {
21583            type Ux = u32;
21584        }
21585        #[doc = "`read()` method returns [`lsadc_ctrl_4::R`](R) reader structure"]
21586        impl crate::Readable for LsadcCtrl4Spec {}
21587        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_4::W`](W) writer structure"]
21588        impl crate::Writable for LsadcCtrl4Spec {
21589            type Safety = crate::Unsafe;
21590        }
21591        #[doc = "`reset()` method sets LSADC_CTRL_4 to value 0"]
21592        impl crate::Resettable for LsadcCtrl4Spec {}
21593    }
21594    #[doc = "LSADC_CTRL_6 (rw) register accessor: ADC control register 6 (analog, reserved)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_6`] module"]
21595    #[doc(alias = "LSADC_CTRL_6")]
21596    pub type LsadcCtrl6 = crate::Reg<lsadc_ctrl_6::LsadcCtrl6Spec>;
21597    #[doc = "ADC control register 6 (analog, reserved)"]
21598    pub mod lsadc_ctrl_6 {
21599        #[doc = "Register `LSADC_CTRL_6` reader"]
21600        pub type R = crate::R<LsadcCtrl6Spec>;
21601        #[doc = "Register `LSADC_CTRL_6` writer"]
21602        pub type W = crate::W<LsadcCtrl6Spec>;
21603        #[doc = "Field `val` reader - Raw register value"]
21604        pub type ValR = crate::FieldReader<u32>;
21605        #[doc = "Field `val` writer - Raw register value"]
21606        pub type ValW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
21607        impl R {
21608            #[doc = "Bits 0:31 - Raw register value"]
21609            #[inline(always)]
21610            pub fn val(&self) -> ValR {
21611                ValR::new(self.bits)
21612            }
21613        }
21614        impl W {
21615            #[doc = "Bits 0:31 - Raw register value"]
21616            #[inline(always)]
21617            pub fn val(&mut self) -> ValW<'_, LsadcCtrl6Spec> {
21618                ValW::new(self, 0)
21619            }
21620        }
21621        #[doc = "ADC control register 6 (analog, reserved)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21622        pub struct LsadcCtrl6Spec;
21623        impl crate::RegisterSpec for LsadcCtrl6Spec {
21624            type Ux = u32;
21625        }
21626        #[doc = "`read()` method returns [`lsadc_ctrl_6::R`](R) reader structure"]
21627        impl crate::Readable for LsadcCtrl6Spec {}
21628        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_6::W`](W) writer structure"]
21629        impl crate::Writable for LsadcCtrl6Spec {
21630            type Safety = crate::Unsafe;
21631        }
21632        #[doc = "`reset()` method sets LSADC_CTRL_6 to value 0"]
21633        impl crate::Resettable for LsadcCtrl6Spec {}
21634    }
21635    #[doc = "LSADC_CTRL_7 (rw) register accessor: ADC control register 7 (analog, reserved)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_7`] module"]
21636    #[doc(alias = "LSADC_CTRL_7")]
21637    pub type LsadcCtrl7 = crate::Reg<lsadc_ctrl_7::LsadcCtrl7Spec>;
21638    #[doc = "ADC control register 7 (analog, reserved)"]
21639    pub mod lsadc_ctrl_7 {
21640        #[doc = "Register `LSADC_CTRL_7` reader"]
21641        pub type R = crate::R<LsadcCtrl7Spec>;
21642        #[doc = "Register `LSADC_CTRL_7` writer"]
21643        pub type W = crate::W<LsadcCtrl7Spec>;
21644        #[doc = "Field `val` reader - Raw register value"]
21645        pub type ValR = crate::FieldReader<u32>;
21646        #[doc = "Field `val` writer - Raw register value"]
21647        pub type ValW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
21648        impl R {
21649            #[doc = "Bits 0:31 - Raw register value"]
21650            #[inline(always)]
21651            pub fn val(&self) -> ValR {
21652                ValR::new(self.bits)
21653            }
21654        }
21655        impl W {
21656            #[doc = "Bits 0:31 - Raw register value"]
21657            #[inline(always)]
21658            pub fn val(&mut self) -> ValW<'_, LsadcCtrl7Spec> {
21659                ValW::new(self, 0)
21660            }
21661        }
21662        #[doc = "ADC control register 7 (analog, reserved)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21663        pub struct LsadcCtrl7Spec;
21664        impl crate::RegisterSpec for LsadcCtrl7Spec {
21665            type Ux = u32;
21666        }
21667        #[doc = "`read()` method returns [`lsadc_ctrl_7::R`](R) reader structure"]
21668        impl crate::Readable for LsadcCtrl7Spec {}
21669        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_7::W`](W) writer structure"]
21670        impl crate::Writable for LsadcCtrl7Spec {
21671            type Safety = crate::Unsafe;
21672        }
21673        #[doc = "`reset()` method sets LSADC_CTRL_7 to value 0"]
21674        impl crate::Resettable for LsadcCtrl7Spec {}
21675    }
21676    #[doc = "LSADC_CTRL_8 (rw) register accessor: Scan start/stop (adc_scan_start_and_stop_data)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_8`] module"]
21677    #[doc(alias = "LSADC_CTRL_8")]
21678    pub type LsadcCtrl8 = crate::Reg<lsadc_ctrl_8::LsadcCtrl8Spec>;
21679    #[doc = "Scan start/stop (adc_scan_start_and_stop_data)"]
21680    pub mod lsadc_ctrl_8 {
21681        #[doc = "Register `LSADC_CTRL_8` reader"]
21682        pub type R = crate::R<LsadcCtrl8Spec>;
21683        #[doc = "Register `LSADC_CTRL_8` writer"]
21684        pub type W = crate::W<LsadcCtrl8Spec>;
21685        #[doc = "Field `lsadc_start` reader - Write 1 to start a scan"]
21686        pub type LsadcStartR = crate::BitReader;
21687        #[doc = "Field `lsadc_start` writer - Write 1 to start a scan"]
21688        pub type LsadcStartW<'a, REG> = crate::BitWriter<'a, REG>;
21689        #[doc = "Field `lsadc_stop` reader - Write 1 to stop a scan"]
21690        pub type LsadcStopR = crate::BitReader;
21691        #[doc = "Field `lsadc_stop` writer - Write 1 to stop a scan"]
21692        pub type LsadcStopW<'a, REG> = crate::BitWriter<'a, REG>;
21693        impl R {
21694            #[doc = "Bit 0 - Write 1 to start a scan"]
21695            #[inline(always)]
21696            pub fn lsadc_start(&self) -> LsadcStartR {
21697                LsadcStartR::new((self.bits & 1) != 0)
21698            }
21699            #[doc = "Bit 1 - Write 1 to stop a scan"]
21700            #[inline(always)]
21701            pub fn lsadc_stop(&self) -> LsadcStopR {
21702                LsadcStopR::new(((self.bits >> 1) & 1) != 0)
21703            }
21704        }
21705        impl W {
21706            #[doc = "Bit 0 - Write 1 to start a scan"]
21707            #[inline(always)]
21708            pub fn lsadc_start(&mut self) -> LsadcStartW<'_, LsadcCtrl8Spec> {
21709                LsadcStartW::new(self, 0)
21710            }
21711            #[doc = "Bit 1 - Write 1 to stop a scan"]
21712            #[inline(always)]
21713            pub fn lsadc_stop(&mut self) -> LsadcStopW<'_, LsadcCtrl8Spec> {
21714                LsadcStopW::new(self, 1)
21715            }
21716        }
21717        #[doc = "Scan start/stop (adc_scan_start_and_stop_data)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21718        pub struct LsadcCtrl8Spec;
21719        impl crate::RegisterSpec for LsadcCtrl8Spec {
21720            type Ux = u32;
21721        }
21722        #[doc = "`read()` method returns [`lsadc_ctrl_8::R`](R) reader structure"]
21723        impl crate::Readable for LsadcCtrl8Spec {}
21724        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_8::W`](W) writer structure"]
21725        impl crate::Writable for LsadcCtrl8Spec {
21726            type Safety = crate::Unsafe;
21727        }
21728        #[doc = "`reset()` method sets LSADC_CTRL_8 to value 0"]
21729        impl crate::Resettable for LsadcCtrl8Spec {}
21730    }
21731    #[doc = "LSADC_CTRL_9 (rw) register accessor: FIFO read data (adc_fifo_read_data): 14-bit code + 3-bit channel\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_9`] module"]
21732    #[doc(alias = "LSADC_CTRL_9")]
21733    pub type LsadcCtrl9 = crate::Reg<lsadc_ctrl_9::LsadcCtrl9Spec>;
21734    #[doc = "FIFO read data (adc_fifo_read_data): 14-bit code + 3-bit channel"]
21735    pub mod lsadc_ctrl_9 {
21736        #[doc = "Register `LSADC_CTRL_9` reader"]
21737        pub type R = crate::R<LsadcCtrl9Spec>;
21738        #[doc = "Register `LSADC_CTRL_9` writer"]
21739        pub type W = crate::W<LsadcCtrl9Spec>;
21740        #[doc = "Field `data` reader - 14-bit conversion code"]
21741        pub type DataR = crate::FieldReader<u16>;
21742        #[doc = "Field `channel` reader - Source channel (0-5)"]
21743        pub type ChannelR = crate::FieldReader;
21744        impl R {
21745            #[doc = "Bits 0:13 - 14-bit conversion code"]
21746            #[inline(always)]
21747            pub fn data(&self) -> DataR {
21748                DataR::new((self.bits & 0x3fff) as u16)
21749            }
21750            #[doc = "Bits 14:16 - Source channel (0-5)"]
21751            #[inline(always)]
21752            pub fn channel(&self) -> ChannelR {
21753                ChannelR::new(((self.bits >> 14) & 7) as u8)
21754            }
21755        }
21756        impl W {}
21757        #[doc = "FIFO read data (adc_fifo_read_data): 14-bit code + 3-bit channel\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21758        pub struct LsadcCtrl9Spec;
21759        impl crate::RegisterSpec for LsadcCtrl9Spec {
21760            type Ux = u32;
21761        }
21762        #[doc = "`read()` method returns [`lsadc_ctrl_9::R`](R) reader structure"]
21763        impl crate::Readable for LsadcCtrl9Spec {}
21764        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_9::W`](W) writer structure"]
21765        impl crate::Writable for LsadcCtrl9Spec {
21766            type Safety = crate::Unsafe;
21767        }
21768        #[doc = "`reset()` method sets LSADC_CTRL_9 to value 0"]
21769        impl crate::Resettable for LsadcCtrl9Spec {}
21770    }
21771    #[doc = "LSADC_CTRL_11 (rw) register accessor: Analog enable/reset (adc_enable_data)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_11`] module"]
21772    #[doc(alias = "LSADC_CTRL_11")]
21773    pub type LsadcCtrl11 = crate::Reg<lsadc_ctrl_11::LsadcCtrl11Spec>;
21774    #[doc = "Analog enable/reset (adc_enable_data)"]
21775    pub mod lsadc_ctrl_11 {
21776        #[doc = "Register `LSADC_CTRL_11` reader"]
21777        pub type R = crate::R<LsadcCtrl11Spec>;
21778        #[doc = "Register `LSADC_CTRL_11` writer"]
21779        pub type W = crate::W<LsadcCtrl11Spec>;
21780        #[doc = "Field `da_lsadc_en` reader - Analog block enable bits (16-bit; SDK ORs 0x7000/0xE7F/0x100/0x80 during power-up)"]
21781        pub type DaLsadcEnR = crate::FieldReader<u16>;
21782        #[doc = "Field `da_lsadc_en` writer - Analog block enable bits (16-bit; SDK ORs 0x7000/0xE7F/0x100/0x80 during power-up)"]
21783        pub type DaLsadcEnW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
21784        #[doc = "Field `da_lsadc_rstn` reader - Analog reset, active low: 1=release reset"]
21785        pub type DaLsadcRstnR = crate::BitReader;
21786        #[doc = "Field `da_lsadc_rstn` writer - Analog reset, active low: 1=release reset"]
21787        pub type DaLsadcRstnW<'a, REG> = crate::BitWriter<'a, REG>;
21788        impl R {
21789            #[doc = "Bits 0:15 - Analog block enable bits (16-bit; SDK ORs 0x7000/0xE7F/0x100/0x80 during power-up)"]
21790            #[inline(always)]
21791            pub fn da_lsadc_en(&self) -> DaLsadcEnR {
21792                DaLsadcEnR::new((self.bits & 0xffff) as u16)
21793            }
21794            #[doc = "Bit 16 - Analog reset, active low: 1=release reset"]
21795            #[inline(always)]
21796            pub fn da_lsadc_rstn(&self) -> DaLsadcRstnR {
21797                DaLsadcRstnR::new(((self.bits >> 16) & 1) != 0)
21798            }
21799        }
21800        impl W {
21801            #[doc = "Bits 0:15 - Analog block enable bits (16-bit; SDK ORs 0x7000/0xE7F/0x100/0x80 during power-up)"]
21802            #[inline(always)]
21803            pub fn da_lsadc_en(&mut self) -> DaLsadcEnW<'_, LsadcCtrl11Spec> {
21804                DaLsadcEnW::new(self, 0)
21805            }
21806            #[doc = "Bit 16 - Analog reset, active low: 1=release reset"]
21807            #[inline(always)]
21808            pub fn da_lsadc_rstn(&mut self) -> DaLsadcRstnW<'_, LsadcCtrl11Spec> {
21809                DaLsadcRstnW::new(self, 16)
21810            }
21811        }
21812        #[doc = "Analog enable/reset (adc_enable_data)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21813        pub struct LsadcCtrl11Spec;
21814        impl crate::RegisterSpec for LsadcCtrl11Spec {
21815            type Ux = u32;
21816        }
21817        #[doc = "`read()` method returns [`lsadc_ctrl_11::R`](R) reader structure"]
21818        impl crate::Readable for LsadcCtrl11Spec {}
21819        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_11::W`](W) writer structure"]
21820        impl crate::Writable for LsadcCtrl11Spec {
21821            type Safety = crate::Unsafe;
21822        }
21823        #[doc = "`reset()` method sets LSADC_CTRL_11 to value 0"]
21824        impl crate::Resettable for LsadcCtrl11Spec {}
21825    }
21826    #[doc = "LSADC_CTRL_12 (rw) register accessor: ADC control register 12 (analog, reserved)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_12`] module"]
21827    #[doc(alias = "LSADC_CTRL_12")]
21828    pub type LsadcCtrl12 = crate::Reg<lsadc_ctrl_12::LsadcCtrl12Spec>;
21829    #[doc = "ADC control register 12 (analog, reserved)"]
21830    pub mod lsadc_ctrl_12 {
21831        #[doc = "Register `LSADC_CTRL_12` reader"]
21832        pub type R = crate::R<LsadcCtrl12Spec>;
21833        #[doc = "Register `LSADC_CTRL_12` writer"]
21834        pub type W = crate::W<LsadcCtrl12Spec>;
21835        #[doc = "Field `val` reader - Raw register value"]
21836        pub type ValR = crate::FieldReader<u32>;
21837        #[doc = "Field `val` writer - Raw register value"]
21838        pub type ValW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
21839        impl R {
21840            #[doc = "Bits 0:31 - Raw register value"]
21841            #[inline(always)]
21842            pub fn val(&self) -> ValR {
21843                ValR::new(self.bits)
21844            }
21845        }
21846        impl W {
21847            #[doc = "Bits 0:31 - Raw register value"]
21848            #[inline(always)]
21849            pub fn val(&mut self) -> ValW<'_, LsadcCtrl12Spec> {
21850                ValW::new(self, 0)
21851            }
21852        }
21853        #[doc = "ADC control register 12 (analog, reserved)\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21854        pub struct LsadcCtrl12Spec;
21855        impl crate::RegisterSpec for LsadcCtrl12Spec {
21856            type Ux = u32;
21857        }
21858        #[doc = "`read()` method returns [`lsadc_ctrl_12::R`](R) reader structure"]
21859        impl crate::Readable for LsadcCtrl12Spec {}
21860        #[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_12::W`](W) writer structure"]
21861        impl crate::Writable for LsadcCtrl12Spec {
21862            type Safety = crate::Unsafe;
21863        }
21864        #[doc = "`reset()` method sets LSADC_CTRL_12 to value 0"]
21865        impl crate::Resettable for LsadcCtrl12Spec {}
21866    }
21867    #[doc = "CFG_DATA_SEL (rw) register accessor: Data output select (base+0xDC)\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_data_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_data_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_data_sel`] module"]
21868    #[doc(alias = "CFG_DATA_SEL")]
21869    pub type CfgDataSel = crate::Reg<cfg_data_sel::CfgDataSelSpec>;
21870    #[doc = "Data output select (base+0xDC)"]
21871    pub mod cfg_data_sel {
21872        #[doc = "Register `CFG_DATA_SEL` reader"]
21873        pub type R = crate::R<CfgDataSelSpec>;
21874        #[doc = "Register `CFG_DATA_SEL` writer"]
21875        pub type W = crate::W<CfgDataSelSpec>;
21876        #[doc = "Field `data_sel` reader - 0=raw ADC data, 1=post-processed"]
21877        pub type DataSelR = crate::BitReader;
21878        #[doc = "Field `data_sel` writer - 0=raw ADC data, 1=post-processed"]
21879        pub type DataSelW<'a, REG> = crate::BitWriter<'a, REG>;
21880        impl R {
21881            #[doc = "Bit 0 - 0=raw ADC data, 1=post-processed"]
21882            #[inline(always)]
21883            pub fn data_sel(&self) -> DataSelR {
21884                DataSelR::new((self.bits & 1) != 0)
21885            }
21886        }
21887        impl W {
21888            #[doc = "Bit 0 - 0=raw ADC data, 1=post-processed"]
21889            #[inline(always)]
21890            pub fn data_sel(&mut self) -> DataSelW<'_, CfgDataSelSpec> {
21891                DataSelW::new(self, 0)
21892            }
21893        }
21894        #[doc = "Data output select (base+0xDC)\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_data_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_data_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21895        pub struct CfgDataSelSpec;
21896        impl crate::RegisterSpec for CfgDataSelSpec {
21897            type Ux = u32;
21898        }
21899        #[doc = "`read()` method returns [`cfg_data_sel::R`](R) reader structure"]
21900        impl crate::Readable for CfgDataSelSpec {}
21901        #[doc = "`write(|w| ..)` method takes [`cfg_data_sel::W`](W) writer structure"]
21902        impl crate::Writable for CfgDataSelSpec {
21903            type Safety = crate::Unsafe;
21904        }
21905        #[doc = "`reset()` method sets CFG_DATA_SEL to value 0"]
21906        impl crate::Resettable for CfgDataSelSpec {}
21907    }
21908    #[doc = "CFG_OFFSET (rw) register accessor: Offset correction (base+0xE0)\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_offset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_offset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_offset`] module"]
21909    #[doc(alias = "CFG_OFFSET")]
21910    pub type CfgOffset = crate::Reg<cfg_offset::CfgOffsetSpec>;
21911    #[doc = "Offset correction (base+0xE0)"]
21912    pub mod cfg_offset {
21913        #[doc = "Register `CFG_OFFSET` reader"]
21914        pub type R = crate::R<CfgOffsetSpec>;
21915        #[doc = "Register `CFG_OFFSET` writer"]
21916        pub type W = crate::W<CfgOffsetSpec>;
21917        #[doc = "Field `offset` reader - ADC offset correction"]
21918        pub type OffsetR = crate::FieldReader<u16>;
21919        #[doc = "Field `offset` writer - ADC offset correction"]
21920        pub type OffsetW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
21921        impl R {
21922            #[doc = "Bits 0:15 - ADC offset correction"]
21923            #[inline(always)]
21924            pub fn offset(&self) -> OffsetR {
21925                OffsetR::new((self.bits & 0xffff) as u16)
21926            }
21927        }
21928        impl W {
21929            #[doc = "Bits 0:15 - ADC offset correction"]
21930            #[inline(always)]
21931            pub fn offset(&mut self) -> OffsetW<'_, CfgOffsetSpec> {
21932                OffsetW::new(self, 0)
21933            }
21934        }
21935        #[doc = "Offset correction (base+0xE0)\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_offset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_offset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21936        pub struct CfgOffsetSpec;
21937        impl crate::RegisterSpec for CfgOffsetSpec {
21938            type Ux = u32;
21939        }
21940        #[doc = "`read()` method returns [`cfg_offset::R`](R) reader structure"]
21941        impl crate::Readable for CfgOffsetSpec {}
21942        #[doc = "`write(|w| ..)` method takes [`cfg_offset::W`](W) writer structure"]
21943        impl crate::Writable for CfgOffsetSpec {
21944            type Safety = crate::Unsafe;
21945        }
21946        #[doc = "`reset()` method sets CFG_OFFSET to value 0"]
21947        impl crate::Resettable for CfgOffsetSpec {}
21948    }
21949    #[doc = "CFG_GAIN (rw) register accessor: Gain correction (base+0xE4)\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gain::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gain::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gain`] module"]
21950    #[doc(alias = "CFG_GAIN")]
21951    pub type CfgGain = crate::Reg<cfg_gain::CfgGainSpec>;
21952    #[doc = "Gain correction (base+0xE4)"]
21953    pub mod cfg_gain {
21954        #[doc = "Register `CFG_GAIN` reader"]
21955        pub type R = crate::R<CfgGainSpec>;
21956        #[doc = "Register `CFG_GAIN` writer"]
21957        pub type W = crate::W<CfgGainSpec>;
21958        #[doc = "Field `gain` reader - ADC gain correction"]
21959        pub type GainR = crate::FieldReader<u16>;
21960        #[doc = "Field `gain` writer - ADC gain correction"]
21961        pub type GainW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
21962        impl R {
21963            #[doc = "Bits 0:15 - ADC gain correction"]
21964            #[inline(always)]
21965            pub fn gain(&self) -> GainR {
21966                GainR::new((self.bits & 0xffff) as u16)
21967            }
21968        }
21969        impl W {
21970            #[doc = "Bits 0:15 - ADC gain correction"]
21971            #[inline(always)]
21972            pub fn gain(&mut self) -> GainW<'_, CfgGainSpec> {
21973                GainW::new(self, 0)
21974            }
21975        }
21976        #[doc = "Gain correction (base+0xE4)\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gain::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gain::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21977        pub struct CfgGainSpec;
21978        impl crate::RegisterSpec for CfgGainSpec {
21979            type Ux = u32;
21980        }
21981        #[doc = "`read()` method returns [`cfg_gain::R`](R) reader structure"]
21982        impl crate::Readable for CfgGainSpec {}
21983        #[doc = "`write(|w| ..)` method takes [`cfg_gain::W`](W) writer structure"]
21984        impl crate::Writable for CfgGainSpec {
21985            type Safety = crate::Unsafe;
21986        }
21987        #[doc = "`reset()` method sets CFG_GAIN to value 0"]
21988        impl crate::Resettable for CfgGainSpec {}
21989    }
21990    #[doc = "CFG_CIC_FILTER_EN (rw) register accessor: CIC filter enable (base+0xE8)\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cic_filter_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cic_filter_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cic_filter_en`] module"]
21991    #[doc(alias = "CFG_CIC_FILTER_EN")]
21992    pub type CfgCicFilterEn = crate::Reg<cfg_cic_filter_en::CfgCicFilterEnSpec>;
21993    #[doc = "CIC filter enable (base+0xE8)"]
21994    pub mod cfg_cic_filter_en {
21995        #[doc = "Register `CFG_CIC_FILTER_EN` reader"]
21996        pub type R = crate::R<CfgCicFilterEnSpec>;
21997        #[doc = "Register `CFG_CIC_FILTER_EN` writer"]
21998        pub type W = crate::W<CfgCicFilterEnSpec>;
21999        #[doc = "Field `cic_filter_en` reader - CIC filter enable"]
22000        pub type CicFilterEnR = crate::BitReader;
22001        #[doc = "Field `cic_filter_en` writer - CIC filter enable"]
22002        pub type CicFilterEnW<'a, REG> = crate::BitWriter<'a, REG>;
22003        impl R {
22004            #[doc = "Bit 0 - CIC filter enable"]
22005            #[inline(always)]
22006            pub fn cic_filter_en(&self) -> CicFilterEnR {
22007                CicFilterEnR::new((self.bits & 1) != 0)
22008            }
22009        }
22010        impl W {
22011            #[doc = "Bit 0 - CIC filter enable"]
22012            #[inline(always)]
22013            pub fn cic_filter_en(&mut self) -> CicFilterEnW<'_, CfgCicFilterEnSpec> {
22014                CicFilterEnW::new(self, 0)
22015            }
22016        }
22017        #[doc = "CIC filter enable (base+0xE8)\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cic_filter_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cic_filter_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22018        pub struct CfgCicFilterEnSpec;
22019        impl crate::RegisterSpec for CfgCicFilterEnSpec {
22020            type Ux = u32;
22021        }
22022        #[doc = "`read()` method returns [`cfg_cic_filter_en::R`](R) reader structure"]
22023        impl crate::Readable for CfgCicFilterEnSpec {}
22024        #[doc = "`write(|w| ..)` method takes [`cfg_cic_filter_en::W`](W) writer structure"]
22025        impl crate::Writable for CfgCicFilterEnSpec {
22026            type Safety = crate::Unsafe;
22027        }
22028        #[doc = "`reset()` method sets CFG_CIC_FILTER_EN to value 0"]
22029        impl crate::Resettable for CfgCicFilterEnSpec {}
22030    }
22031    #[doc = "CFG_CIC_OSR (rw) register accessor: CIC oversampling ratio (base+0xEC)\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cic_osr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cic_osr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cic_osr`] module"]
22032    #[doc(alias = "CFG_CIC_OSR")]
22033    pub type CfgCicOsr = crate::Reg<cfg_cic_osr::CfgCicOsrSpec>;
22034    #[doc = "CIC oversampling ratio (base+0xEC)"]
22035    pub mod cfg_cic_osr {
22036        #[doc = "Register `CFG_CIC_OSR` reader"]
22037        pub type R = crate::R<CfgCicOsrSpec>;
22038        #[doc = "Register `CFG_CIC_OSR` writer"]
22039        pub type W = crate::W<CfgCicOsrSpec>;
22040        #[doc = "Field `cic_osr` reader - CIC oversampling ratio"]
22041        pub type CicOsrR = crate::FieldReader;
22042        #[doc = "Field `cic_osr` writer - CIC oversampling ratio"]
22043        pub type CicOsrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
22044        impl R {
22045            #[doc = "Bits 0:7 - CIC oversampling ratio"]
22046            #[inline(always)]
22047            pub fn cic_osr(&self) -> CicOsrR {
22048                CicOsrR::new((self.bits & 0xff) as u8)
22049            }
22050        }
22051        impl W {
22052            #[doc = "Bits 0:7 - CIC oversampling ratio"]
22053            #[inline(always)]
22054            pub fn cic_osr(&mut self) -> CicOsrW<'_, CfgCicOsrSpec> {
22055                CicOsrW::new(self, 0)
22056            }
22057        }
22058        #[doc = "CIC oversampling ratio (base+0xEC)\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cic_osr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cic_osr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22059        pub struct CfgCicOsrSpec;
22060        impl crate::RegisterSpec for CfgCicOsrSpec {
22061            type Ux = u32;
22062        }
22063        #[doc = "`read()` method returns [`cfg_cic_osr::R`](R) reader structure"]
22064        impl crate::Readable for CfgCicOsrSpec {}
22065        #[doc = "`write(|w| ..)` method takes [`cfg_cic_osr::W`](W) writer structure"]
22066        impl crate::Writable for CfgCicOsrSpec {
22067            type Safety = crate::Unsafe;
22068        }
22069        #[doc = "`reset()` method sets CFG_CIC_OSR to value 0"]
22070        impl crate::Resettable for CfgCicOsrSpec {}
22071    }
22072}
22073#[doc = "Temperature sensor controller (v151)"]
22074pub type Tsensor = crate::Periph<tsensor::RegisterBlock, 0x4400_e000>;
22075impl core::fmt::Debug for Tsensor {
22076    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22077        f.debug_struct("Tsensor").finish()
22078    }
22079}
22080#[doc = "Temperature sensor controller (v151)"]
22081pub mod tsensor {
22082    #[repr(C)]
22083    #[doc = "Register block"]
22084    pub struct RegisterBlock {
22085        tsensor_ctl_id: TsensorCtlId,
22086        _reserved1: [u8; 0x0c],
22087        tsensor_reg0: TsensorReg0,
22088        tsensor_reg1: TsensorReg1,
22089        tsensor_reg2: TsensorReg2,
22090        tsensor_reg3: TsensorReg3,
22091        _reserved5: [u8; 0x02e0],
22092        tsensor_start: TsensorStart,
22093        tsensor_ctrl: TsensorCtrl,
22094        tsensor_sts: TsensorSts,
22095        _reserved8: [u8; 0x04],
22096        tsensor_ctrl1: TsensorCtrl1,
22097        tsensor_temp_high_limit: TsensorTempHighLimit,
22098        tsensor_temp_low_limit: TsensorTempLowLimit,
22099        tsensor_over_temp: TsensorOverTemp,
22100        tsensor_temp_int_en: TsensorTempIntEn,
22101        tsensor_temp_int_clr: TsensorTempIntClr,
22102        tsensor_temp_int_sts: TsensorTempIntSts,
22103        _reserved15: [u8; 0x04],
22104        tsensor_auto_refresh_period: TsensorAutoRefreshPeriod,
22105        tsensor_auto_refresh_cfg: TsensorAutoRefreshCfg,
22106    }
22107    impl RegisterBlock {
22108        #[doc = "0x00 - Temperature sensor control ID"]
22109        #[inline(always)]
22110        pub const fn tsensor_ctl_id(&self) -> &TsensorCtlId {
22111            &self.tsensor_ctl_id
22112        }
22113        #[doc = "0x10 - Common register 0"]
22114        #[inline(always)]
22115        pub const fn tsensor_reg0(&self) -> &TsensorReg0 {
22116            &self.tsensor_reg0
22117        }
22118        #[doc = "0x14 - Common register 1"]
22119        #[inline(always)]
22120        pub const fn tsensor_reg1(&self) -> &TsensorReg1 {
22121            &self.tsensor_reg1
22122        }
22123        #[doc = "0x18 - Common register 2"]
22124        #[inline(always)]
22125        pub const fn tsensor_reg2(&self) -> &TsensorReg2 {
22126            &self.tsensor_reg2
22127        }
22128        #[doc = "0x1c - Common register 3"]
22129        #[inline(always)]
22130        pub const fn tsensor_reg3(&self) -> &TsensorReg3 {
22131            &self.tsensor_reg3
22132        }
22133        #[doc = "0x300 - Temperature sensor start register"]
22134        #[inline(always)]
22135        pub const fn tsensor_start(&self) -> &TsensorStart {
22136            &self.tsensor_start
22137        }
22138        #[doc = "0x304 - Temperature sensor control register"]
22139        #[inline(always)]
22140        pub const fn tsensor_ctrl(&self) -> &TsensorCtrl {
22141            &self.tsensor_ctrl
22142        }
22143        #[doc = "0x308 - Temperature sensor status register"]
22144        #[inline(always)]
22145        pub const fn tsensor_sts(&self) -> &TsensorSts {
22146            &self.tsensor_sts
22147        }
22148        #[doc = "0x310 - Temperature sensor control 1"]
22149        #[inline(always)]
22150        pub const fn tsensor_ctrl1(&self) -> &TsensorCtrl1 {
22151            &self.tsensor_ctrl1
22152        }
22153        #[doc = "0x314 - High temperature limit"]
22154        #[inline(always)]
22155        pub const fn tsensor_temp_high_limit(&self) -> &TsensorTempHighLimit {
22156            &self.tsensor_temp_high_limit
22157        }
22158        #[doc = "0x318 - Low temperature limit"]
22159        #[inline(always)]
22160        pub const fn tsensor_temp_low_limit(&self) -> &TsensorTempLowLimit {
22161            &self.tsensor_temp_low_limit
22162        }
22163        #[doc = "0x31c - Over-temperature threshold"]
22164        #[inline(always)]
22165        pub const fn tsensor_over_temp(&self) -> &TsensorOverTemp {
22166            &self.tsensor_over_temp
22167        }
22168        #[doc = "0x320 - Temperature interrupt enable"]
22169        #[inline(always)]
22170        pub const fn tsensor_temp_int_en(&self) -> &TsensorTempIntEn {
22171            &self.tsensor_temp_int_en
22172        }
22173        #[doc = "0x324 - Temperature interrupt clear"]
22174        #[inline(always)]
22175        pub const fn tsensor_temp_int_clr(&self) -> &TsensorTempIntClr {
22176            &self.tsensor_temp_int_clr
22177        }
22178        #[doc = "0x328 - Temperature interrupt status"]
22179        #[inline(always)]
22180        pub const fn tsensor_temp_int_sts(&self) -> &TsensorTempIntSts {
22181            &self.tsensor_temp_int_sts
22182        }
22183        #[doc = "0x330 - Auto refresh period"]
22184        #[inline(always)]
22185        pub const fn tsensor_auto_refresh_period(&self) -> &TsensorAutoRefreshPeriod {
22186            &self.tsensor_auto_refresh_period
22187        }
22188        #[doc = "0x334 - Auto refresh configuration"]
22189        #[inline(always)]
22190        pub const fn tsensor_auto_refresh_cfg(&self) -> &TsensorAutoRefreshCfg {
22191            &self.tsensor_auto_refresh_cfg
22192        }
22193    }
22194    #[doc = "TSENSOR_CTL_ID (rw) register accessor: Temperature sensor control ID\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctl_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctl_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_ctl_id`] module"]
22195    #[doc(alias = "TSENSOR_CTL_ID")]
22196    pub type TsensorCtlId = crate::Reg<tsensor_ctl_id::TsensorCtlIdSpec>;
22197    #[doc = "Temperature sensor control ID"]
22198    pub mod tsensor_ctl_id {
22199        #[doc = "Register `TSENSOR_CTL_ID` reader"]
22200        pub type R = crate::R<TsensorCtlIdSpec>;
22201        #[doc = "Register `TSENSOR_CTL_ID` writer"]
22202        pub type W = crate::W<TsensorCtlIdSpec>;
22203        #[doc = "Field `tsensor_ctl_id` reader - Control ID"]
22204        pub type TsensorCtlIdR = crate::FieldReader<u16>;
22205        impl R {
22206            #[doc = "Bits 0:15 - Control ID"]
22207            #[inline(always)]
22208            pub fn tsensor_ctl_id(&self) -> TsensorCtlIdR {
22209                TsensorCtlIdR::new((self.bits & 0xffff) as u16)
22210            }
22211        }
22212        impl W {}
22213        #[doc = "Temperature sensor control ID\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctl_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctl_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22214        pub struct TsensorCtlIdSpec;
22215        impl crate::RegisterSpec for TsensorCtlIdSpec {
22216            type Ux = u32;
22217        }
22218        #[doc = "`read()` method returns [`tsensor_ctl_id::R`](R) reader structure"]
22219        impl crate::Readable for TsensorCtlIdSpec {}
22220        #[doc = "`write(|w| ..)` method takes [`tsensor_ctl_id::W`](W) writer structure"]
22221        impl crate::Writable for TsensorCtlIdSpec {
22222            type Safety = crate::Unsafe;
22223        }
22224        #[doc = "`reset()` method sets TSENSOR_CTL_ID to value 0"]
22225        impl crate::Resettable for TsensorCtlIdSpec {}
22226    }
22227    #[doc = "TSENSOR_REG0 (rw) register accessor: Common register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_reg0`] module"]
22228    #[doc(alias = "TSENSOR_REG0")]
22229    pub type TsensorReg0 = crate::Reg<tsensor_reg0::TsensorReg0Spec>;
22230    #[doc = "Common register 0"]
22231    pub mod tsensor_reg0 {
22232        #[doc = "Register `TSENSOR_REG0` reader"]
22233        pub type R = crate::R<TsensorReg0Spec>;
22234        #[doc = "Register `TSENSOR_REG0` writer"]
22235        pub type W = crate::W<TsensorReg0Spec>;
22236        #[doc = "Field `tsensor_reg0` reader - Common configuration register 0"]
22237        pub type TsensorReg0R = crate::FieldReader<u32>;
22238        #[doc = "Field `tsensor_reg0` writer - Common configuration register 0"]
22239        pub type TsensorReg0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
22240        impl R {
22241            #[doc = "Bits 0:31 - Common configuration register 0"]
22242            #[inline(always)]
22243            pub fn tsensor_reg0(&self) -> TsensorReg0R {
22244                TsensorReg0R::new(self.bits)
22245            }
22246        }
22247        impl W {
22248            #[doc = "Bits 0:31 - Common configuration register 0"]
22249            #[inline(always)]
22250            pub fn tsensor_reg0(&mut self) -> TsensorReg0W<'_, TsensorReg0Spec> {
22251                TsensorReg0W::new(self, 0)
22252            }
22253        }
22254        #[doc = "Common register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22255        pub struct TsensorReg0Spec;
22256        impl crate::RegisterSpec for TsensorReg0Spec {
22257            type Ux = u32;
22258        }
22259        #[doc = "`read()` method returns [`tsensor_reg0::R`](R) reader structure"]
22260        impl crate::Readable for TsensorReg0Spec {}
22261        #[doc = "`write(|w| ..)` method takes [`tsensor_reg0::W`](W) writer structure"]
22262        impl crate::Writable for TsensorReg0Spec {
22263            type Safety = crate::Unsafe;
22264        }
22265        #[doc = "`reset()` method sets TSENSOR_REG0 to value 0"]
22266        impl crate::Resettable for TsensorReg0Spec {}
22267    }
22268    #[doc = "TSENSOR_REG1 (rw) register accessor: Common register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_reg1`] module"]
22269    #[doc(alias = "TSENSOR_REG1")]
22270    pub type TsensorReg1 = crate::Reg<tsensor_reg1::TsensorReg1Spec>;
22271    #[doc = "Common register 1"]
22272    pub mod tsensor_reg1 {
22273        #[doc = "Register `TSENSOR_REG1` reader"]
22274        pub type R = crate::R<TsensorReg1Spec>;
22275        #[doc = "Register `TSENSOR_REG1` writer"]
22276        pub type W = crate::W<TsensorReg1Spec>;
22277        #[doc = "Field `tsensor_reg1` reader - Common configuration register 1"]
22278        pub type TsensorReg1R = crate::FieldReader<u32>;
22279        #[doc = "Field `tsensor_reg1` writer - Common configuration register 1"]
22280        pub type TsensorReg1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
22281        impl R {
22282            #[doc = "Bits 0:31 - Common configuration register 1"]
22283            #[inline(always)]
22284            pub fn tsensor_reg1(&self) -> TsensorReg1R {
22285                TsensorReg1R::new(self.bits)
22286            }
22287        }
22288        impl W {
22289            #[doc = "Bits 0:31 - Common configuration register 1"]
22290            #[inline(always)]
22291            pub fn tsensor_reg1(&mut self) -> TsensorReg1W<'_, TsensorReg1Spec> {
22292                TsensorReg1W::new(self, 0)
22293            }
22294        }
22295        #[doc = "Common register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22296        pub struct TsensorReg1Spec;
22297        impl crate::RegisterSpec for TsensorReg1Spec {
22298            type Ux = u32;
22299        }
22300        #[doc = "`read()` method returns [`tsensor_reg1::R`](R) reader structure"]
22301        impl crate::Readable for TsensorReg1Spec {}
22302        #[doc = "`write(|w| ..)` method takes [`tsensor_reg1::W`](W) writer structure"]
22303        impl crate::Writable for TsensorReg1Spec {
22304            type Safety = crate::Unsafe;
22305        }
22306        #[doc = "`reset()` method sets TSENSOR_REG1 to value 0"]
22307        impl crate::Resettable for TsensorReg1Spec {}
22308    }
22309    #[doc = "TSENSOR_REG2 (rw) register accessor: Common register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_reg2`] module"]
22310    #[doc(alias = "TSENSOR_REG2")]
22311    pub type TsensorReg2 = crate::Reg<tsensor_reg2::TsensorReg2Spec>;
22312    #[doc = "Common register 2"]
22313    pub mod tsensor_reg2 {
22314        #[doc = "Register `TSENSOR_REG2` reader"]
22315        pub type R = crate::R<TsensorReg2Spec>;
22316        #[doc = "Register `TSENSOR_REG2` writer"]
22317        pub type W = crate::W<TsensorReg2Spec>;
22318        #[doc = "Field `tsensor_reg2` reader - Common configuration register 2"]
22319        pub type TsensorReg2R = crate::FieldReader<u32>;
22320        #[doc = "Field `tsensor_reg2` writer - Common configuration register 2"]
22321        pub type TsensorReg2W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
22322        impl R {
22323            #[doc = "Bits 0:31 - Common configuration register 2"]
22324            #[inline(always)]
22325            pub fn tsensor_reg2(&self) -> TsensorReg2R {
22326                TsensorReg2R::new(self.bits)
22327            }
22328        }
22329        impl W {
22330            #[doc = "Bits 0:31 - Common configuration register 2"]
22331            #[inline(always)]
22332            pub fn tsensor_reg2(&mut self) -> TsensorReg2W<'_, TsensorReg2Spec> {
22333                TsensorReg2W::new(self, 0)
22334            }
22335        }
22336        #[doc = "Common register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22337        pub struct TsensorReg2Spec;
22338        impl crate::RegisterSpec for TsensorReg2Spec {
22339            type Ux = u32;
22340        }
22341        #[doc = "`read()` method returns [`tsensor_reg2::R`](R) reader structure"]
22342        impl crate::Readable for TsensorReg2Spec {}
22343        #[doc = "`write(|w| ..)` method takes [`tsensor_reg2::W`](W) writer structure"]
22344        impl crate::Writable for TsensorReg2Spec {
22345            type Safety = crate::Unsafe;
22346        }
22347        #[doc = "`reset()` method sets TSENSOR_REG2 to value 0"]
22348        impl crate::Resettable for TsensorReg2Spec {}
22349    }
22350    #[doc = "TSENSOR_REG3 (rw) register accessor: Common register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_reg3`] module"]
22351    #[doc(alias = "TSENSOR_REG3")]
22352    pub type TsensorReg3 = crate::Reg<tsensor_reg3::TsensorReg3Spec>;
22353    #[doc = "Common register 3"]
22354    pub mod tsensor_reg3 {
22355        #[doc = "Register `TSENSOR_REG3` reader"]
22356        pub type R = crate::R<TsensorReg3Spec>;
22357        #[doc = "Register `TSENSOR_REG3` writer"]
22358        pub type W = crate::W<TsensorReg3Spec>;
22359        #[doc = "Field `tsensor_reg3` reader - Common configuration register 3"]
22360        pub type TsensorReg3R = crate::FieldReader<u32>;
22361        #[doc = "Field `tsensor_reg3` writer - Common configuration register 3"]
22362        pub type TsensorReg3W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
22363        impl R {
22364            #[doc = "Bits 0:31 - Common configuration register 3"]
22365            #[inline(always)]
22366            pub fn tsensor_reg3(&self) -> TsensorReg3R {
22367                TsensorReg3R::new(self.bits)
22368            }
22369        }
22370        impl W {
22371            #[doc = "Bits 0:31 - Common configuration register 3"]
22372            #[inline(always)]
22373            pub fn tsensor_reg3(&mut self) -> TsensorReg3W<'_, TsensorReg3Spec> {
22374                TsensorReg3W::new(self, 0)
22375            }
22376        }
22377        #[doc = "Common register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22378        pub struct TsensorReg3Spec;
22379        impl crate::RegisterSpec for TsensorReg3Spec {
22380            type Ux = u32;
22381        }
22382        #[doc = "`read()` method returns [`tsensor_reg3::R`](R) reader structure"]
22383        impl crate::Readable for TsensorReg3Spec {}
22384        #[doc = "`write(|w| ..)` method takes [`tsensor_reg3::W`](W) writer structure"]
22385        impl crate::Writable for TsensorReg3Spec {
22386            type Safety = crate::Unsafe;
22387        }
22388        #[doc = "`reset()` method sets TSENSOR_REG3 to value 0"]
22389        impl crate::Resettable for TsensorReg3Spec {}
22390    }
22391    #[doc = "TSENSOR_START (rw) register accessor: Temperature sensor start register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_start`] module"]
22392    #[doc(alias = "TSENSOR_START")]
22393    pub type TsensorStart = crate::Reg<tsensor_start::TsensorStartSpec>;
22394    #[doc = "Temperature sensor start register"]
22395    pub mod tsensor_start {
22396        #[doc = "Register `TSENSOR_START` reader"]
22397        pub type R = crate::R<TsensorStartSpec>;
22398        #[doc = "Register `TSENSOR_START` writer"]
22399        pub type W = crate::W<TsensorStartSpec>;
22400        #[doc = "Field `tsensor_start` writer - Write 1 to refresh temperature reading"]
22401        pub type TsensorStartW<'a, REG> = crate::BitWriter<'a, REG>;
22402        impl W {
22403            #[doc = "Bit 0 - Write 1 to refresh temperature reading"]
22404            #[inline(always)]
22405            pub fn tsensor_start(&mut self) -> TsensorStartW<'_, TsensorStartSpec> {
22406                TsensorStartW::new(self, 0)
22407            }
22408        }
22409        #[doc = "Temperature sensor start register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22410        pub struct TsensorStartSpec;
22411        impl crate::RegisterSpec for TsensorStartSpec {
22412            type Ux = u32;
22413        }
22414        #[doc = "`read()` method returns [`tsensor_start::R`](R) reader structure"]
22415        impl crate::Readable for TsensorStartSpec {}
22416        #[doc = "`write(|w| ..)` method takes [`tsensor_start::W`](W) writer structure"]
22417        impl crate::Writable for TsensorStartSpec {
22418            type Safety = crate::Unsafe;
22419        }
22420        #[doc = "`reset()` method sets TSENSOR_START to value 0"]
22421        impl crate::Resettable for TsensorStartSpec {}
22422    }
22423    #[doc = "TSENSOR_CTRL (rw) register accessor: Temperature sensor control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_ctrl`] module"]
22424    #[doc(alias = "TSENSOR_CTRL")]
22425    pub type TsensorCtrl = crate::Reg<tsensor_ctrl::TsensorCtrlSpec>;
22426    #[doc = "Temperature sensor control register"]
22427    pub mod tsensor_ctrl {
22428        #[doc = "Register `TSENSOR_CTRL` reader"]
22429        pub type R = crate::R<TsensorCtrlSpec>;
22430        #[doc = "Register `TSENSOR_CTRL` writer"]
22431        pub type W = crate::W<TsensorCtrlSpec>;
22432        #[doc = "Field `tsensor_enable` reader - Temperature sensor enable"]
22433        pub type TsensorEnableR = crate::BitReader;
22434        #[doc = "Field `tsensor_enable` writer - Temperature sensor enable"]
22435        pub type TsensorEnableW<'a, REG> = crate::BitWriter<'a, REG>;
22436        #[doc = "Field `tsensor_mode` reader - Temperature sensor mode"]
22437        pub type TsensorModeR = crate::FieldReader;
22438        #[doc = "Field `tsensor_mode` writer - Temperature sensor mode"]
22439        pub type TsensorModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
22440        impl R {
22441            #[doc = "Bit 0 - Temperature sensor enable"]
22442            #[inline(always)]
22443            pub fn tsensor_enable(&self) -> TsensorEnableR {
22444                TsensorEnableR::new((self.bits & 1) != 0)
22445            }
22446            #[doc = "Bits 1:2 - Temperature sensor mode"]
22447            #[inline(always)]
22448            pub fn tsensor_mode(&self) -> TsensorModeR {
22449                TsensorModeR::new(((self.bits >> 1) & 3) as u8)
22450            }
22451        }
22452        impl W {
22453            #[doc = "Bit 0 - Temperature sensor enable"]
22454            #[inline(always)]
22455            pub fn tsensor_enable(&mut self) -> TsensorEnableW<'_, TsensorCtrlSpec> {
22456                TsensorEnableW::new(self, 0)
22457            }
22458            #[doc = "Bits 1:2 - Temperature sensor mode"]
22459            #[inline(always)]
22460            pub fn tsensor_mode(&mut self) -> TsensorModeW<'_, TsensorCtrlSpec> {
22461                TsensorModeW::new(self, 1)
22462            }
22463        }
22464        #[doc = "Temperature sensor control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22465        pub struct TsensorCtrlSpec;
22466        impl crate::RegisterSpec for TsensorCtrlSpec {
22467            type Ux = u32;
22468        }
22469        #[doc = "`read()` method returns [`tsensor_ctrl::R`](R) reader structure"]
22470        impl crate::Readable for TsensorCtrlSpec {}
22471        #[doc = "`write(|w| ..)` method takes [`tsensor_ctrl::W`](W) writer structure"]
22472        impl crate::Writable for TsensorCtrlSpec {
22473            type Safety = crate::Unsafe;
22474        }
22475        #[doc = "`reset()` method sets TSENSOR_CTRL to value 0"]
22476        impl crate::Resettable for TsensorCtrlSpec {}
22477    }
22478    #[doc = "TSENSOR_STS (rw) register accessor: Temperature sensor status register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_sts`] module"]
22479    #[doc(alias = "TSENSOR_STS")]
22480    pub type TsensorSts = crate::Reg<tsensor_sts::TsensorStsSpec>;
22481    #[doc = "Temperature sensor status register"]
22482    pub mod tsensor_sts {
22483        #[doc = "Register `TSENSOR_STS` reader"]
22484        pub type R = crate::R<TsensorStsSpec>;
22485        #[doc = "Register `TSENSOR_STS` writer"]
22486        pub type W = crate::W<TsensorStsSpec>;
22487        #[doc = "Field `clr` reader - Clear status"]
22488        pub type ClrR = crate::BitReader;
22489        #[doc = "Field `clr` writer - Clear status"]
22490        pub type ClrW<'a, REG> = crate::BitWriter<'a, REG>;
22491        #[doc = "Field `rdy` reader - Data ready flag"]
22492        pub type RdyR = crate::BitReader;
22493        #[doc = "Field `data` reader - Temperature code (10-bit, range 114-896 for -40C to 125C)"]
22494        pub type DataR = crate::FieldReader<u16>;
22495        impl R {
22496            #[doc = "Bit 0 - Clear status"]
22497            #[inline(always)]
22498            pub fn clr(&self) -> ClrR {
22499                ClrR::new((self.bits & 1) != 0)
22500            }
22501            #[doc = "Bit 1 - Data ready flag"]
22502            #[inline(always)]
22503            pub fn rdy(&self) -> RdyR {
22504                RdyR::new(((self.bits >> 1) & 1) != 0)
22505            }
22506            #[doc = "Bits 2:11 - Temperature code (10-bit, range 114-896 for -40C to 125C)"]
22507            #[inline(always)]
22508            pub fn data(&self) -> DataR {
22509                DataR::new(((self.bits >> 2) & 0x03ff) as u16)
22510            }
22511        }
22512        impl W {
22513            #[doc = "Bit 0 - Clear status"]
22514            #[inline(always)]
22515            pub fn clr(&mut self) -> ClrW<'_, TsensorStsSpec> {
22516                ClrW::new(self, 0)
22517            }
22518        }
22519        #[doc = "Temperature sensor status register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22520        pub struct TsensorStsSpec;
22521        impl crate::RegisterSpec for TsensorStsSpec {
22522            type Ux = u32;
22523        }
22524        #[doc = "`read()` method returns [`tsensor_sts::R`](R) reader structure"]
22525        impl crate::Readable for TsensorStsSpec {}
22526        #[doc = "`write(|w| ..)` method takes [`tsensor_sts::W`](W) writer structure"]
22527        impl crate::Writable for TsensorStsSpec {
22528            type Safety = crate::Unsafe;
22529        }
22530        #[doc = "`reset()` method sets TSENSOR_STS to value 0"]
22531        impl crate::Resettable for TsensorStsSpec {}
22532    }
22533    #[doc = "TSENSOR_CTRL1 (rw) register accessor: Temperature sensor control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_ctrl1`] module"]
22534    #[doc(alias = "TSENSOR_CTRL1")]
22535    pub type TsensorCtrl1 = crate::Reg<tsensor_ctrl1::TsensorCtrl1Spec>;
22536    #[doc = "Temperature sensor control 1"]
22537    pub mod tsensor_ctrl1 {
22538        #[doc = "Register `TSENSOR_CTRL1` reader"]
22539        pub type R = crate::R<TsensorCtrl1Spec>;
22540        #[doc = "Register `TSENSOR_CTRL1` writer"]
22541        pub type W = crate::W<TsensorCtrl1Spec>;
22542        #[doc = "Field `temp_calib` reader - Temperature calibration enable"]
22543        pub type TempCalibR = crate::BitReader;
22544        #[doc = "Field `temp_calib` writer - Temperature calibration enable"]
22545        pub type TempCalibW<'a, REG> = crate::BitWriter<'a, REG>;
22546        #[doc = "Field `temp_ct_sel` reader - Temperature CT select"]
22547        pub type TempCtSelR = crate::FieldReader;
22548        #[doc = "Field `temp_ct_sel` writer - Temperature CT select"]
22549        pub type TempCtSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
22550        #[doc = "Field `dft` reader - DFT mode enable"]
22551        pub type DftR = crate::BitReader;
22552        #[doc = "Field `dft` writer - DFT mode enable"]
22553        pub type DftW<'a, REG> = crate::BitWriter<'a, REG>;
22554        impl R {
22555            #[doc = "Bit 0 - Temperature calibration enable"]
22556            #[inline(always)]
22557            pub fn temp_calib(&self) -> TempCalibR {
22558                TempCalibR::new((self.bits & 1) != 0)
22559            }
22560            #[doc = "Bits 1:2 - Temperature CT select"]
22561            #[inline(always)]
22562            pub fn temp_ct_sel(&self) -> TempCtSelR {
22563                TempCtSelR::new(((self.bits >> 1) & 3) as u8)
22564            }
22565            #[doc = "Bit 4 - DFT mode enable"]
22566            #[inline(always)]
22567            pub fn dft(&self) -> DftR {
22568                DftR::new(((self.bits >> 4) & 1) != 0)
22569            }
22570        }
22571        impl W {
22572            #[doc = "Bit 0 - Temperature calibration enable"]
22573            #[inline(always)]
22574            pub fn temp_calib(&mut self) -> TempCalibW<'_, TsensorCtrl1Spec> {
22575                TempCalibW::new(self, 0)
22576            }
22577            #[doc = "Bits 1:2 - Temperature CT select"]
22578            #[inline(always)]
22579            pub fn temp_ct_sel(&mut self) -> TempCtSelW<'_, TsensorCtrl1Spec> {
22580                TempCtSelW::new(self, 1)
22581            }
22582            #[doc = "Bit 4 - DFT mode enable"]
22583            #[inline(always)]
22584            pub fn dft(&mut self) -> DftW<'_, TsensorCtrl1Spec> {
22585                DftW::new(self, 4)
22586            }
22587        }
22588        #[doc = "Temperature sensor control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22589        pub struct TsensorCtrl1Spec;
22590        impl crate::RegisterSpec for TsensorCtrl1Spec {
22591            type Ux = u32;
22592        }
22593        #[doc = "`read()` method returns [`tsensor_ctrl1::R`](R) reader structure"]
22594        impl crate::Readable for TsensorCtrl1Spec {}
22595        #[doc = "`write(|w| ..)` method takes [`tsensor_ctrl1::W`](W) writer structure"]
22596        impl crate::Writable for TsensorCtrl1Spec {
22597            type Safety = crate::Unsafe;
22598        }
22599        #[doc = "`reset()` method sets TSENSOR_CTRL1 to value 0"]
22600        impl crate::Resettable for TsensorCtrl1Spec {}
22601    }
22602    #[doc = "TSENSOR_TEMP_HIGH_LIMIT (rw) register accessor: High temperature limit\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_high_limit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_high_limit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_temp_high_limit`] module"]
22603    #[doc(alias = "TSENSOR_TEMP_HIGH_LIMIT")]
22604    pub type TsensorTempHighLimit = crate::Reg<tsensor_temp_high_limit::TsensorTempHighLimitSpec>;
22605    #[doc = "High temperature limit"]
22606    pub mod tsensor_temp_high_limit {
22607        #[doc = "Register `TSENSOR_TEMP_HIGH_LIMIT` reader"]
22608        pub type R = crate::R<TsensorTempHighLimitSpec>;
22609        #[doc = "Register `TSENSOR_TEMP_HIGH_LIMIT` writer"]
22610        pub type W = crate::W<TsensorTempHighLimitSpec>;
22611        #[doc = "Field `temp_high_limit` reader - High temperature threshold (10-bit code)"]
22612        pub type TempHighLimitR = crate::FieldReader<u16>;
22613        #[doc = "Field `temp_high_limit` writer - High temperature threshold (10-bit code)"]
22614        pub type TempHighLimitW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
22615        impl R {
22616            #[doc = "Bits 0:9 - High temperature threshold (10-bit code)"]
22617            #[inline(always)]
22618            pub fn temp_high_limit(&self) -> TempHighLimitR {
22619                TempHighLimitR::new((self.bits & 0x03ff) as u16)
22620            }
22621        }
22622        impl W {
22623            #[doc = "Bits 0:9 - High temperature threshold (10-bit code)"]
22624            #[inline(always)]
22625            pub fn temp_high_limit(&mut self) -> TempHighLimitW<'_, TsensorTempHighLimitSpec> {
22626                TempHighLimitW::new(self, 0)
22627            }
22628        }
22629        #[doc = "High temperature limit\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_high_limit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_high_limit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22630        pub struct TsensorTempHighLimitSpec;
22631        impl crate::RegisterSpec for TsensorTempHighLimitSpec {
22632            type Ux = u32;
22633        }
22634        #[doc = "`read()` method returns [`tsensor_temp_high_limit::R`](R) reader structure"]
22635        impl crate::Readable for TsensorTempHighLimitSpec {}
22636        #[doc = "`write(|w| ..)` method takes [`tsensor_temp_high_limit::W`](W) writer structure"]
22637        impl crate::Writable for TsensorTempHighLimitSpec {
22638            type Safety = crate::Unsafe;
22639        }
22640        #[doc = "`reset()` method sets TSENSOR_TEMP_HIGH_LIMIT to value 0"]
22641        impl crate::Resettable for TsensorTempHighLimitSpec {}
22642    }
22643    #[doc = "TSENSOR_TEMP_LOW_LIMIT (rw) register accessor: Low temperature limit\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_low_limit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_low_limit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_temp_low_limit`] module"]
22644    #[doc(alias = "TSENSOR_TEMP_LOW_LIMIT")]
22645    pub type TsensorTempLowLimit = crate::Reg<tsensor_temp_low_limit::TsensorTempLowLimitSpec>;
22646    #[doc = "Low temperature limit"]
22647    pub mod tsensor_temp_low_limit {
22648        #[doc = "Register `TSENSOR_TEMP_LOW_LIMIT` reader"]
22649        pub type R = crate::R<TsensorTempLowLimitSpec>;
22650        #[doc = "Register `TSENSOR_TEMP_LOW_LIMIT` writer"]
22651        pub type W = crate::W<TsensorTempLowLimitSpec>;
22652        #[doc = "Field `temp_low_limit` reader - Low temperature threshold (10-bit code)"]
22653        pub type TempLowLimitR = crate::FieldReader<u16>;
22654        #[doc = "Field `temp_low_limit` writer - Low temperature threshold (10-bit code)"]
22655        pub type TempLowLimitW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
22656        impl R {
22657            #[doc = "Bits 0:9 - Low temperature threshold (10-bit code)"]
22658            #[inline(always)]
22659            pub fn temp_low_limit(&self) -> TempLowLimitR {
22660                TempLowLimitR::new((self.bits & 0x03ff) as u16)
22661            }
22662        }
22663        impl W {
22664            #[doc = "Bits 0:9 - Low temperature threshold (10-bit code)"]
22665            #[inline(always)]
22666            pub fn temp_low_limit(&mut self) -> TempLowLimitW<'_, TsensorTempLowLimitSpec> {
22667                TempLowLimitW::new(self, 0)
22668            }
22669        }
22670        #[doc = "Low temperature limit\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_low_limit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_low_limit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22671        pub struct TsensorTempLowLimitSpec;
22672        impl crate::RegisterSpec for TsensorTempLowLimitSpec {
22673            type Ux = u32;
22674        }
22675        #[doc = "`read()` method returns [`tsensor_temp_low_limit::R`](R) reader structure"]
22676        impl crate::Readable for TsensorTempLowLimitSpec {}
22677        #[doc = "`write(|w| ..)` method takes [`tsensor_temp_low_limit::W`](W) writer structure"]
22678        impl crate::Writable for TsensorTempLowLimitSpec {
22679            type Safety = crate::Unsafe;
22680        }
22681        #[doc = "`reset()` method sets TSENSOR_TEMP_LOW_LIMIT to value 0"]
22682        impl crate::Resettable for TsensorTempLowLimitSpec {}
22683    }
22684    #[doc = "TSENSOR_OVER_TEMP (rw) register accessor: Over-temperature threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_over_temp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_over_temp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_over_temp`] module"]
22685    #[doc(alias = "TSENSOR_OVER_TEMP")]
22686    pub type TsensorOverTemp = crate::Reg<tsensor_over_temp::TsensorOverTempSpec>;
22687    #[doc = "Over-temperature threshold"]
22688    pub mod tsensor_over_temp {
22689        #[doc = "Register `TSENSOR_OVER_TEMP` reader"]
22690        pub type R = crate::R<TsensorOverTempSpec>;
22691        #[doc = "Register `TSENSOR_OVER_TEMP` writer"]
22692        pub type W = crate::W<TsensorOverTempSpec>;
22693        #[doc = "Field `over_temp` reader - Over-temperature threshold (10-bit code)"]
22694        pub type OverTempR = crate::FieldReader<u16>;
22695        #[doc = "Field `over_temp` writer - Over-temperature threshold (10-bit code)"]
22696        pub type OverTempW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
22697        #[doc = "Field `over_temp_en` reader - Over-temperature interrupt enable"]
22698        pub type OverTempEnR = crate::BitReader;
22699        #[doc = "Field `over_temp_en` writer - Over-temperature interrupt enable"]
22700        pub type OverTempEnW<'a, REG> = crate::BitWriter<'a, REG>;
22701        impl R {
22702            #[doc = "Bits 0:9 - Over-temperature threshold (10-bit code)"]
22703            #[inline(always)]
22704            pub fn over_temp(&self) -> OverTempR {
22705                OverTempR::new((self.bits & 0x03ff) as u16)
22706            }
22707            #[doc = "Bit 10 - Over-temperature interrupt enable"]
22708            #[inline(always)]
22709            pub fn over_temp_en(&self) -> OverTempEnR {
22710                OverTempEnR::new(((self.bits >> 10) & 1) != 0)
22711            }
22712        }
22713        impl W {
22714            #[doc = "Bits 0:9 - Over-temperature threshold (10-bit code)"]
22715            #[inline(always)]
22716            pub fn over_temp(&mut self) -> OverTempW<'_, TsensorOverTempSpec> {
22717                OverTempW::new(self, 0)
22718            }
22719            #[doc = "Bit 10 - Over-temperature interrupt enable"]
22720            #[inline(always)]
22721            pub fn over_temp_en(&mut self) -> OverTempEnW<'_, TsensorOverTempSpec> {
22722                OverTempEnW::new(self, 10)
22723            }
22724        }
22725        #[doc = "Over-temperature threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_over_temp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_over_temp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22726        pub struct TsensorOverTempSpec;
22727        impl crate::RegisterSpec for TsensorOverTempSpec {
22728            type Ux = u32;
22729        }
22730        #[doc = "`read()` method returns [`tsensor_over_temp::R`](R) reader structure"]
22731        impl crate::Readable for TsensorOverTempSpec {}
22732        #[doc = "`write(|w| ..)` method takes [`tsensor_over_temp::W`](W) writer structure"]
22733        impl crate::Writable for TsensorOverTempSpec {
22734            type Safety = crate::Unsafe;
22735        }
22736        #[doc = "`reset()` method sets TSENSOR_OVER_TEMP to value 0"]
22737        impl crate::Resettable for TsensorOverTempSpec {}
22738    }
22739    #[doc = "TSENSOR_TEMP_INT_EN (rw) register accessor: Temperature interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_temp_int_en`] module"]
22740    #[doc(alias = "TSENSOR_TEMP_INT_EN")]
22741    pub type TsensorTempIntEn = crate::Reg<tsensor_temp_int_en::TsensorTempIntEnSpec>;
22742    #[doc = "Temperature interrupt enable"]
22743    pub mod tsensor_temp_int_en {
22744        #[doc = "Register `TSENSOR_TEMP_INT_EN` reader"]
22745        pub type R = crate::R<TsensorTempIntEnSpec>;
22746        #[doc = "Register `TSENSOR_TEMP_INT_EN` writer"]
22747        pub type W = crate::W<TsensorTempIntEnSpec>;
22748        #[doc = "Field `done_int_en` reader - Conversion done interrupt enable"]
22749        pub type DoneIntEnR = crate::BitReader;
22750        #[doc = "Field `done_int_en` writer - Conversion done interrupt enable"]
22751        pub type DoneIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
22752        #[doc = "Field `out_thresh_int_en` reader - Out-of-threshold interrupt enable"]
22753        pub type OutThreshIntEnR = crate::BitReader;
22754        #[doc = "Field `out_thresh_int_en` writer - Out-of-threshold interrupt enable"]
22755        pub type OutThreshIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
22756        #[doc = "Field `overtemp_int_en` reader - Over-temperature interrupt enable"]
22757        pub type OvertempIntEnR = crate::BitReader;
22758        #[doc = "Field `overtemp_int_en` writer - Over-temperature interrupt enable"]
22759        pub type OvertempIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
22760        impl R {
22761            #[doc = "Bit 0 - Conversion done interrupt enable"]
22762            #[inline(always)]
22763            pub fn done_int_en(&self) -> DoneIntEnR {
22764                DoneIntEnR::new((self.bits & 1) != 0)
22765            }
22766            #[doc = "Bit 1 - Out-of-threshold interrupt enable"]
22767            #[inline(always)]
22768            pub fn out_thresh_int_en(&self) -> OutThreshIntEnR {
22769                OutThreshIntEnR::new(((self.bits >> 1) & 1) != 0)
22770            }
22771            #[doc = "Bit 2 - Over-temperature interrupt enable"]
22772            #[inline(always)]
22773            pub fn overtemp_int_en(&self) -> OvertempIntEnR {
22774                OvertempIntEnR::new(((self.bits >> 2) & 1) != 0)
22775            }
22776        }
22777        impl W {
22778            #[doc = "Bit 0 - Conversion done interrupt enable"]
22779            #[inline(always)]
22780            pub fn done_int_en(&mut self) -> DoneIntEnW<'_, TsensorTempIntEnSpec> {
22781                DoneIntEnW::new(self, 0)
22782            }
22783            #[doc = "Bit 1 - Out-of-threshold interrupt enable"]
22784            #[inline(always)]
22785            pub fn out_thresh_int_en(&mut self) -> OutThreshIntEnW<'_, TsensorTempIntEnSpec> {
22786                OutThreshIntEnW::new(self, 1)
22787            }
22788            #[doc = "Bit 2 - Over-temperature interrupt enable"]
22789            #[inline(always)]
22790            pub fn overtemp_int_en(&mut self) -> OvertempIntEnW<'_, TsensorTempIntEnSpec> {
22791                OvertempIntEnW::new(self, 2)
22792            }
22793        }
22794        #[doc = "Temperature interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22795        pub struct TsensorTempIntEnSpec;
22796        impl crate::RegisterSpec for TsensorTempIntEnSpec {
22797            type Ux = u32;
22798        }
22799        #[doc = "`read()` method returns [`tsensor_temp_int_en::R`](R) reader structure"]
22800        impl crate::Readable for TsensorTempIntEnSpec {}
22801        #[doc = "`write(|w| ..)` method takes [`tsensor_temp_int_en::W`](W) writer structure"]
22802        impl crate::Writable for TsensorTempIntEnSpec {
22803            type Safety = crate::Unsafe;
22804        }
22805        #[doc = "`reset()` method sets TSENSOR_TEMP_INT_EN to value 0"]
22806        impl crate::Resettable for TsensorTempIntEnSpec {}
22807    }
22808    #[doc = "TSENSOR_TEMP_INT_CLR (rw) register accessor: Temperature interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_temp_int_clr`] module"]
22809    #[doc(alias = "TSENSOR_TEMP_INT_CLR")]
22810    pub type TsensorTempIntClr = crate::Reg<tsensor_temp_int_clr::TsensorTempIntClrSpec>;
22811    #[doc = "Temperature interrupt clear"]
22812    pub mod tsensor_temp_int_clr {
22813        #[doc = "Register `TSENSOR_TEMP_INT_CLR` reader"]
22814        pub type R = crate::R<TsensorTempIntClrSpec>;
22815        #[doc = "Register `TSENSOR_TEMP_INT_CLR` writer"]
22816        pub type W = crate::W<TsensorTempIntClrSpec>;
22817        #[doc = "Field `done_int_clr` writer - Clear done interrupt"]
22818        pub type DoneIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
22819        #[doc = "Field `out_thresh_int_clr` writer - Clear out-of-threshold interrupt"]
22820        pub type OutThreshIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
22821        #[doc = "Field `overtemp_int_clr` writer - Clear over-temperature interrupt"]
22822        pub type OvertempIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
22823        impl W {
22824            #[doc = "Bit 0 - Clear done interrupt"]
22825            #[inline(always)]
22826            pub fn done_int_clr(&mut self) -> DoneIntClrW<'_, TsensorTempIntClrSpec> {
22827                DoneIntClrW::new(self, 0)
22828            }
22829            #[doc = "Bit 1 - Clear out-of-threshold interrupt"]
22830            #[inline(always)]
22831            pub fn out_thresh_int_clr(&mut self) -> OutThreshIntClrW<'_, TsensorTempIntClrSpec> {
22832                OutThreshIntClrW::new(self, 1)
22833            }
22834            #[doc = "Bit 2 - Clear over-temperature interrupt"]
22835            #[inline(always)]
22836            pub fn overtemp_int_clr(&mut self) -> OvertempIntClrW<'_, TsensorTempIntClrSpec> {
22837                OvertempIntClrW::new(self, 2)
22838            }
22839        }
22840        #[doc = "Temperature interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22841        pub struct TsensorTempIntClrSpec;
22842        impl crate::RegisterSpec for TsensorTempIntClrSpec {
22843            type Ux = u32;
22844        }
22845        #[doc = "`read()` method returns [`tsensor_temp_int_clr::R`](R) reader structure"]
22846        impl crate::Readable for TsensorTempIntClrSpec {}
22847        #[doc = "`write(|w| ..)` method takes [`tsensor_temp_int_clr::W`](W) writer structure"]
22848        impl crate::Writable for TsensorTempIntClrSpec {
22849            type Safety = crate::Unsafe;
22850        }
22851        #[doc = "`reset()` method sets TSENSOR_TEMP_INT_CLR to value 0"]
22852        impl crate::Resettable for TsensorTempIntClrSpec {}
22853    }
22854    #[doc = "TSENSOR_TEMP_INT_STS (rw) register accessor: Temperature interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_temp_int_sts`] module"]
22855    #[doc(alias = "TSENSOR_TEMP_INT_STS")]
22856    pub type TsensorTempIntSts = crate::Reg<tsensor_temp_int_sts::TsensorTempIntStsSpec>;
22857    #[doc = "Temperature interrupt status"]
22858    pub mod tsensor_temp_int_sts {
22859        #[doc = "Register `TSENSOR_TEMP_INT_STS` reader"]
22860        pub type R = crate::R<TsensorTempIntStsSpec>;
22861        #[doc = "Register `TSENSOR_TEMP_INT_STS` writer"]
22862        pub type W = crate::W<TsensorTempIntStsSpec>;
22863        #[doc = "Field `done_int_sts` reader - Conversion done interrupt status"]
22864        pub type DoneIntStsR = crate::BitReader;
22865        #[doc = "Field `out_thresh_int_sts` reader - Out-of-threshold interrupt status"]
22866        pub type OutThreshIntStsR = crate::BitReader;
22867        #[doc = "Field `overtemp_int_sts` reader - Over-temperature interrupt status"]
22868        pub type OvertempIntStsR = crate::BitReader;
22869        impl R {
22870            #[doc = "Bit 0 - Conversion done interrupt status"]
22871            #[inline(always)]
22872            pub fn done_int_sts(&self) -> DoneIntStsR {
22873                DoneIntStsR::new((self.bits & 1) != 0)
22874            }
22875            #[doc = "Bit 1 - Out-of-threshold interrupt status"]
22876            #[inline(always)]
22877            pub fn out_thresh_int_sts(&self) -> OutThreshIntStsR {
22878                OutThreshIntStsR::new(((self.bits >> 1) & 1) != 0)
22879            }
22880            #[doc = "Bit 2 - Over-temperature interrupt status"]
22881            #[inline(always)]
22882            pub fn overtemp_int_sts(&self) -> OvertempIntStsR {
22883                OvertempIntStsR::new(((self.bits >> 2) & 1) != 0)
22884            }
22885        }
22886        impl W {}
22887        #[doc = "Temperature interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22888        pub struct TsensorTempIntStsSpec;
22889        impl crate::RegisterSpec for TsensorTempIntStsSpec {
22890            type Ux = u32;
22891        }
22892        #[doc = "`read()` method returns [`tsensor_temp_int_sts::R`](R) reader structure"]
22893        impl crate::Readable for TsensorTempIntStsSpec {}
22894        #[doc = "`write(|w| ..)` method takes [`tsensor_temp_int_sts::W`](W) writer structure"]
22895        impl crate::Writable for TsensorTempIntStsSpec {
22896            type Safety = crate::Unsafe;
22897        }
22898        #[doc = "`reset()` method sets TSENSOR_TEMP_INT_STS to value 0"]
22899        impl crate::Resettable for TsensorTempIntStsSpec {}
22900    }
22901    #[doc = "TSENSOR_AUTO_REFRESH_PERIOD (rw) register accessor: Auto refresh period\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_auto_refresh_period::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_auto_refresh_period::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_auto_refresh_period`] module"]
22902    #[doc(alias = "TSENSOR_AUTO_REFRESH_PERIOD")]
22903    pub type TsensorAutoRefreshPeriod =
22904        crate::Reg<tsensor_auto_refresh_period::TsensorAutoRefreshPeriodSpec>;
22905    #[doc = "Auto refresh period"]
22906    pub mod tsensor_auto_refresh_period {
22907        #[doc = "Register `TSENSOR_AUTO_REFRESH_PERIOD` reader"]
22908        pub type R = crate::R<TsensorAutoRefreshPeriodSpec>;
22909        #[doc = "Register `TSENSOR_AUTO_REFRESH_PERIOD` writer"]
22910        pub type W = crate::W<TsensorAutoRefreshPeriodSpec>;
22911        #[doc = "Field `auto_refresh_period` reader - Auto refresh period in 32kHz clock cycles"]
22912        pub type AutoRefreshPeriodR = crate::FieldReader<u16>;
22913        #[doc = "Field `auto_refresh_period` writer - Auto refresh period in 32kHz clock cycles"]
22914        pub type AutoRefreshPeriodW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
22915        impl R {
22916            #[doc = "Bits 0:15 - Auto refresh period in 32kHz clock cycles"]
22917            #[inline(always)]
22918            pub fn auto_refresh_period(&self) -> AutoRefreshPeriodR {
22919                AutoRefreshPeriodR::new((self.bits & 0xffff) as u16)
22920            }
22921        }
22922        impl W {
22923            #[doc = "Bits 0:15 - Auto refresh period in 32kHz clock cycles"]
22924            #[inline(always)]
22925            pub fn auto_refresh_period(
22926                &mut self,
22927            ) -> AutoRefreshPeriodW<'_, TsensorAutoRefreshPeriodSpec> {
22928                AutoRefreshPeriodW::new(self, 0)
22929            }
22930        }
22931        #[doc = "Auto refresh period\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_auto_refresh_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_auto_refresh_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22932        pub struct TsensorAutoRefreshPeriodSpec;
22933        impl crate::RegisterSpec for TsensorAutoRefreshPeriodSpec {
22934            type Ux = u32;
22935        }
22936        #[doc = "`read()` method returns [`tsensor_auto_refresh_period::R`](R) reader structure"]
22937        impl crate::Readable for TsensorAutoRefreshPeriodSpec {}
22938        #[doc = "`write(|w| ..)` method takes [`tsensor_auto_refresh_period::W`](W) writer structure"]
22939        impl crate::Writable for TsensorAutoRefreshPeriodSpec {
22940            type Safety = crate::Unsafe;
22941        }
22942        #[doc = "`reset()` method sets TSENSOR_AUTO_REFRESH_PERIOD to value 0"]
22943        impl crate::Resettable for TsensorAutoRefreshPeriodSpec {}
22944    }
22945    #[doc = "TSENSOR_AUTO_REFRESH_CFG (rw) register accessor: Auto refresh configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_auto_refresh_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_auto_refresh_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_auto_refresh_cfg`] module"]
22946    #[doc(alias = "TSENSOR_AUTO_REFRESH_CFG")]
22947    pub type TsensorAutoRefreshCfg =
22948        crate::Reg<tsensor_auto_refresh_cfg::TsensorAutoRefreshCfgSpec>;
22949    #[doc = "Auto refresh configuration"]
22950    pub mod tsensor_auto_refresh_cfg {
22951        #[doc = "Register `TSENSOR_AUTO_REFRESH_CFG` reader"]
22952        pub type R = crate::R<TsensorAutoRefreshCfgSpec>;
22953        #[doc = "Register `TSENSOR_AUTO_REFRESH_CFG` writer"]
22954        pub type W = crate::W<TsensorAutoRefreshCfgSpec>;
22955        #[doc = "Field `auto_refresh_en` reader - Auto refresh enable"]
22956        pub type AutoRefreshEnR = crate::BitReader;
22957        #[doc = "Field `auto_refresh_en` writer - Auto refresh enable"]
22958        pub type AutoRefreshEnW<'a, REG> = crate::BitWriter<'a, REG>;
22959        impl R {
22960            #[doc = "Bit 0 - Auto refresh enable"]
22961            #[inline(always)]
22962            pub fn auto_refresh_en(&self) -> AutoRefreshEnR {
22963                AutoRefreshEnR::new((self.bits & 1) != 0)
22964            }
22965        }
22966        impl W {
22967            #[doc = "Bit 0 - Auto refresh enable"]
22968            #[inline(always)]
22969            pub fn auto_refresh_en(&mut self) -> AutoRefreshEnW<'_, TsensorAutoRefreshCfgSpec> {
22970                AutoRefreshEnW::new(self, 0)
22971            }
22972        }
22973        #[doc = "Auto refresh configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_auto_refresh_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_auto_refresh_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22974        pub struct TsensorAutoRefreshCfgSpec;
22975        impl crate::RegisterSpec for TsensorAutoRefreshCfgSpec {
22976            type Ux = u32;
22977        }
22978        #[doc = "`read()` method returns [`tsensor_auto_refresh_cfg::R`](R) reader structure"]
22979        impl crate::Readable for TsensorAutoRefreshCfgSpec {}
22980        #[doc = "`write(|w| ..)` method takes [`tsensor_auto_refresh_cfg::W`](W) writer structure"]
22981        impl crate::Writable for TsensorAutoRefreshCfgSpec {
22982            type Safety = crate::Unsafe;
22983        }
22984        #[doc = "`reset()` method sets TSENSOR_AUTO_REFRESH_CFG to value 0"]
22985        impl crate::Resettable for TsensorAutoRefreshCfgSpec {}
22986    }
22987}
22988#[doc = "Timer module with 3 independent 32-bit timers (v150)"]
22989pub type Timer = crate::Periph<timer::RegisterBlock, 0x4400_2000>;
22990impl core::fmt::Debug for Timer {
22991    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22992        f.debug_struct("Timer").finish()
22993    }
22994}
22995#[doc = "Timer module with 3 independent 32-bit timers (v150)"]
22996pub mod timer {
22997    #[repr(C)]
22998    #[doc = "Register block"]
22999    pub struct RegisterBlock {
23000        _reserved0: [u8; 0x60],
23001        abnor_intr_raw: AbnorIntrRaw,
23002        abnor_imsk: AbnorImsk,
23003        abnor_intr_stat: AbnorIntrStat,
23004        _reserved3: [u8; 0x0c],
23005        eoi_ren: EoiRen,
23006        raw_intr_stat: RawIntrStat,
23007        intr_stat: IntrStat,
23008        _reserved6: [u8; 0x7c],
23009        timer0_load_count: (),
23010        _reserved7: [u8; 0x08],
23011        timer0_current_value: (),
23012        _reserved8: [u8; 0x08],
23013        timer0_control: (),
23014        _reserved9: [u8; 0x04],
23015        timer0_eoi: (),
23016        _reserved10: [u8; 0x04],
23017        timer0_raw_intr: (),
23018    }
23019    impl RegisterBlock {
23020        #[doc = "0x60 - Abnormal interrupt raw status"]
23021        #[inline(always)]
23022        pub const fn abnor_intr_raw(&self) -> &AbnorIntrRaw {
23023            &self.abnor_intr_raw
23024        }
23025        #[doc = "0x64 - Abnormal interrupt mask"]
23026        #[inline(always)]
23027        pub const fn abnor_imsk(&self) -> &AbnorImsk {
23028            &self.abnor_imsk
23029        }
23030        #[doc = "0x68 - Abnormal interrupt status"]
23031        #[inline(always)]
23032        pub const fn abnor_intr_stat(&self) -> &AbnorIntrStat {
23033            &self.abnor_intr_stat
23034        }
23035        #[doc = "0x78 - End-of-interrupt register"]
23036        #[inline(always)]
23037        pub const fn eoi_ren(&self) -> &EoiRen {
23038            &self.eoi_ren
23039        }
23040        #[doc = "0x7c - Raw interrupt status"]
23041        #[inline(always)]
23042        pub const fn raw_intr_stat(&self) -> &RawIntrStat {
23043            &self.raw_intr_stat
23044        }
23045        #[doc = "0x80 - Interrupt status (masked)"]
23046        #[inline(always)]
23047        pub const fn intr_stat(&self) -> &IntrStat {
23048            &self.intr_stat
23049        }
23050        #[doc = "0x100..0x10c - Timer %s \\[dim=3\\] load count"]
23051        #[inline(always)]
23052        pub const fn timer0_load_count(&self, n: usize) -> &TimerLoadCount {
23053            #[allow(clippy::no_effect)]
23054            [(); 3][n];
23055            unsafe {
23056                &*core::ptr::from_ref(self)
23057                    .cast::<u8>()
23058                    .add(256)
23059                    .add(256 * n)
23060                    .cast()
23061            }
23062        }
23063        #[doc = "Iterator for array of:"]
23064        #[doc = "0x100..0x10c - Timer %s \\[dim=3\\] load count"]
23065        #[inline(always)]
23066        pub fn timer0_load_count_iter(&self) -> impl Iterator<Item = &TimerLoadCount> {
23067            (0..3).map(move |n| unsafe {
23068                &*core::ptr::from_ref(self)
23069                    .cast::<u8>()
23070                    .add(256)
23071                    .add(256 * n)
23072                    .cast()
23073            })
23074        }
23075        #[doc = "0x200 - Timer 1 \\[dim=3\\] load count"]
23076        #[inline(always)]
23077        pub const fn timer1_load_count(&self) -> &TimerLoadCount {
23078            self.timer0_load_count(1)
23079        }
23080        #[doc = "0x300 - Timer 2 \\[dim=3\\] load count"]
23081        #[inline(always)]
23082        pub const fn timer2_load_count(&self) -> &TimerLoadCount {
23083            self.timer0_load_count(2)
23084        }
23085        #[doc = "0x108..0x114 - Timer %s \\[dim=3\\] current value"]
23086        #[inline(always)]
23087        pub const fn timer0_current_value(&self, n: usize) -> &TimerCurrentValue {
23088            #[allow(clippy::no_effect)]
23089            [(); 3][n];
23090            unsafe {
23091                &*core::ptr::from_ref(self)
23092                    .cast::<u8>()
23093                    .add(264)
23094                    .add(256 * n)
23095                    .cast()
23096            }
23097        }
23098        #[doc = "Iterator for array of:"]
23099        #[doc = "0x108..0x114 - Timer %s \\[dim=3\\] current value"]
23100        #[inline(always)]
23101        pub fn timer0_current_value_iter(&self) -> impl Iterator<Item = &TimerCurrentValue> {
23102            (0..3).map(move |n| unsafe {
23103                &*core::ptr::from_ref(self)
23104                    .cast::<u8>()
23105                    .add(264)
23106                    .add(256 * n)
23107                    .cast()
23108            })
23109        }
23110        #[doc = "0x208 - Timer 1 \\[dim=3\\] current value"]
23111        #[inline(always)]
23112        pub const fn timer1_current_value(&self) -> &TimerCurrentValue {
23113            self.timer0_current_value(1)
23114        }
23115        #[doc = "0x308 - Timer 2 \\[dim=3\\] current value"]
23116        #[inline(always)]
23117        pub const fn timer2_current_value(&self) -> &TimerCurrentValue {
23118            self.timer0_current_value(2)
23119        }
23120        #[doc = "0x110..0x11c - Timer %s \\[dim=3\\] control register"]
23121        #[inline(always)]
23122        pub const fn timer0_control(&self, n: usize) -> &TimerControl {
23123            #[allow(clippy::no_effect)]
23124            [(); 3][n];
23125            unsafe {
23126                &*core::ptr::from_ref(self)
23127                    .cast::<u8>()
23128                    .add(272)
23129                    .add(256 * n)
23130                    .cast()
23131            }
23132        }
23133        #[doc = "Iterator for array of:"]
23134        #[doc = "0x110..0x11c - Timer %s \\[dim=3\\] control register"]
23135        #[inline(always)]
23136        pub fn timer0_control_iter(&self) -> impl Iterator<Item = &TimerControl> {
23137            (0..3).map(move |n| unsafe {
23138                &*core::ptr::from_ref(self)
23139                    .cast::<u8>()
23140                    .add(272)
23141                    .add(256 * n)
23142                    .cast()
23143            })
23144        }
23145        #[doc = "0x210 - Timer 1 \\[dim=3\\] control register"]
23146        #[inline(always)]
23147        pub const fn timer1_control(&self) -> &TimerControl {
23148            self.timer0_control(1)
23149        }
23150        #[doc = "0x310 - Timer 2 \\[dim=3\\] control register"]
23151        #[inline(always)]
23152        pub const fn timer2_control(&self) -> &TimerControl {
23153            self.timer0_control(2)
23154        }
23155        #[doc = "0x114..0x120 - Timer %s \\[dim=3\\] end-of-interrupt"]
23156        #[inline(always)]
23157        pub const fn timer0_eoi(&self, n: usize) -> &TimerEoi {
23158            #[allow(clippy::no_effect)]
23159            [(); 3][n];
23160            unsafe {
23161                &*core::ptr::from_ref(self)
23162                    .cast::<u8>()
23163                    .add(276)
23164                    .add(256 * n)
23165                    .cast()
23166            }
23167        }
23168        #[doc = "Iterator for array of:"]
23169        #[doc = "0x114..0x120 - Timer %s \\[dim=3\\] end-of-interrupt"]
23170        #[inline(always)]
23171        pub fn timer0_eoi_iter(&self) -> impl Iterator<Item = &TimerEoi> {
23172            (0..3).map(move |n| unsafe {
23173                &*core::ptr::from_ref(self)
23174                    .cast::<u8>()
23175                    .add(276)
23176                    .add(256 * n)
23177                    .cast()
23178            })
23179        }
23180        #[doc = "0x214 - Timer 1 \\[dim=3\\] end-of-interrupt"]
23181        #[inline(always)]
23182        pub const fn timer1_eoi(&self) -> &TimerEoi {
23183            self.timer0_eoi(1)
23184        }
23185        #[doc = "0x314 - Timer 2 \\[dim=3\\] end-of-interrupt"]
23186        #[inline(always)]
23187        pub const fn timer2_eoi(&self) -> &TimerEoi {
23188            self.timer0_eoi(2)
23189        }
23190        #[doc = "0x118..0x124 - Timer %s \\[dim=3\\] raw interrupt status"]
23191        #[inline(always)]
23192        pub const fn timer0_raw_intr(&self, n: usize) -> &TimerRawIntr {
23193            #[allow(clippy::no_effect)]
23194            [(); 3][n];
23195            unsafe {
23196                &*core::ptr::from_ref(self)
23197                    .cast::<u8>()
23198                    .add(280)
23199                    .add(256 * n)
23200                    .cast()
23201            }
23202        }
23203        #[doc = "Iterator for array of:"]
23204        #[doc = "0x118..0x124 - Timer %s \\[dim=3\\] raw interrupt status"]
23205        #[inline(always)]
23206        pub fn timer0_raw_intr_iter(&self) -> impl Iterator<Item = &TimerRawIntr> {
23207            (0..3).map(move |n| unsafe {
23208                &*core::ptr::from_ref(self)
23209                    .cast::<u8>()
23210                    .add(280)
23211                    .add(256 * n)
23212                    .cast()
23213            })
23214        }
23215        #[doc = "0x218 - Timer 1 \\[dim=3\\] raw interrupt status"]
23216        #[inline(always)]
23217        pub const fn timer1_raw_intr(&self) -> &TimerRawIntr {
23218            self.timer0_raw_intr(1)
23219        }
23220        #[doc = "0x318 - Timer 2 \\[dim=3\\] raw interrupt status"]
23221        #[inline(always)]
23222        pub const fn timer2_raw_intr(&self) -> &TimerRawIntr {
23223            self.timer0_raw_intr(2)
23224        }
23225    }
23226    #[doc = "ABNOR_INTR_RAW (rw) register accessor: Abnormal interrupt raw status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_intr_raw`] module"]
23227    #[doc(alias = "ABNOR_INTR_RAW")]
23228    pub type AbnorIntrRaw = crate::Reg<abnor_intr_raw::AbnorIntrRawSpec>;
23229    #[doc = "Abnormal interrupt raw status"]
23230    pub mod abnor_intr_raw {
23231        #[doc = "Register `ABNOR_INTR_RAW` reader"]
23232        pub type R = crate::R<AbnorIntrRawSpec>;
23233        #[doc = "Register `ABNOR_INTR_RAW` writer"]
23234        pub type W = crate::W<AbnorIntrRawSpec>;
23235        #[doc = "Field `abnor_intr_raw` reader - Abnormal interrupt raw status for all timers"]
23236        pub type AbnorIntrRawR = crate::FieldReader;
23237        impl R {
23238            #[doc = "Bits 0:2 - Abnormal interrupt raw status for all timers"]
23239            #[inline(always)]
23240            pub fn abnor_intr_raw(&self) -> AbnorIntrRawR {
23241                AbnorIntrRawR::new((self.bits & 7) as u8)
23242            }
23243        }
23244        impl W {}
23245        #[doc = "Abnormal interrupt raw status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23246        pub struct AbnorIntrRawSpec;
23247        impl crate::RegisterSpec for AbnorIntrRawSpec {
23248            type Ux = u32;
23249        }
23250        #[doc = "`read()` method returns [`abnor_intr_raw::R`](R) reader structure"]
23251        impl crate::Readable for AbnorIntrRawSpec {}
23252        #[doc = "`write(|w| ..)` method takes [`abnor_intr_raw::W`](W) writer structure"]
23253        impl crate::Writable for AbnorIntrRawSpec {
23254            type Safety = crate::Unsafe;
23255        }
23256        #[doc = "`reset()` method sets ABNOR_INTR_RAW to value 0"]
23257        impl crate::Resettable for AbnorIntrRawSpec {}
23258    }
23259    #[doc = "ABNOR_IMSK (rw) register accessor: Abnormal interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_imsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_imsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_imsk`] module"]
23260    #[doc(alias = "ABNOR_IMSK")]
23261    pub type AbnorImsk = crate::Reg<abnor_imsk::AbnorImskSpec>;
23262    #[doc = "Abnormal interrupt mask"]
23263    pub mod abnor_imsk {
23264        #[doc = "Register `ABNOR_IMSK` reader"]
23265        pub type R = crate::R<AbnorImskSpec>;
23266        #[doc = "Register `ABNOR_IMSK` writer"]
23267        pub type W = crate::W<AbnorImskSpec>;
23268        #[doc = "Field `abnor_imsk` reader - Abnormal interrupt mask for all timers"]
23269        pub type AbnorImskR = crate::FieldReader;
23270        #[doc = "Field `abnor_imsk` writer - Abnormal interrupt mask for all timers"]
23271        pub type AbnorImskW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
23272        impl R {
23273            #[doc = "Bits 0:2 - Abnormal interrupt mask for all timers"]
23274            #[inline(always)]
23275            pub fn abnor_imsk(&self) -> AbnorImskR {
23276                AbnorImskR::new((self.bits & 7) as u8)
23277            }
23278        }
23279        impl W {
23280            #[doc = "Bits 0:2 - Abnormal interrupt mask for all timers"]
23281            #[inline(always)]
23282            pub fn abnor_imsk(&mut self) -> AbnorImskW<'_, AbnorImskSpec> {
23283                AbnorImskW::new(self, 0)
23284            }
23285        }
23286        #[doc = "Abnormal interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_imsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_imsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23287        pub struct AbnorImskSpec;
23288        impl crate::RegisterSpec for AbnorImskSpec {
23289            type Ux = u32;
23290        }
23291        #[doc = "`read()` method returns [`abnor_imsk::R`](R) reader structure"]
23292        impl crate::Readable for AbnorImskSpec {}
23293        #[doc = "`write(|w| ..)` method takes [`abnor_imsk::W`](W) writer structure"]
23294        impl crate::Writable for AbnorImskSpec {
23295            type Safety = crate::Unsafe;
23296        }
23297        #[doc = "`reset()` method sets ABNOR_IMSK to value 0"]
23298        impl crate::Resettable for AbnorImskSpec {}
23299    }
23300    #[doc = "ABNOR_INTR_STAT (rw) register accessor: Abnormal interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_intr_stat`] module"]
23301    #[doc(alias = "ABNOR_INTR_STAT")]
23302    pub type AbnorIntrStat = crate::Reg<abnor_intr_stat::AbnorIntrStatSpec>;
23303    #[doc = "Abnormal interrupt status"]
23304    pub mod abnor_intr_stat {
23305        #[doc = "Register `ABNOR_INTR_STAT` reader"]
23306        pub type R = crate::R<AbnorIntrStatSpec>;
23307        #[doc = "Register `ABNOR_INTR_STAT` writer"]
23308        pub type W = crate::W<AbnorIntrStatSpec>;
23309        #[doc = "Field `abnor_intr_stat` reader - Abnormal interrupt status for all timers"]
23310        pub type AbnorIntrStatR = crate::FieldReader;
23311        impl R {
23312            #[doc = "Bits 0:2 - Abnormal interrupt status for all timers"]
23313            #[inline(always)]
23314            pub fn abnor_intr_stat(&self) -> AbnorIntrStatR {
23315                AbnorIntrStatR::new((self.bits & 7) as u8)
23316            }
23317        }
23318        impl W {}
23319        #[doc = "Abnormal interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23320        pub struct AbnorIntrStatSpec;
23321        impl crate::RegisterSpec for AbnorIntrStatSpec {
23322            type Ux = u32;
23323        }
23324        #[doc = "`read()` method returns [`abnor_intr_stat::R`](R) reader structure"]
23325        impl crate::Readable for AbnorIntrStatSpec {}
23326        #[doc = "`write(|w| ..)` method takes [`abnor_intr_stat::W`](W) writer structure"]
23327        impl crate::Writable for AbnorIntrStatSpec {
23328            type Safety = crate::Unsafe;
23329        }
23330        #[doc = "`reset()` method sets ABNOR_INTR_STAT to value 0"]
23331        impl crate::Resettable for AbnorIntrStatSpec {}
23332    }
23333    #[doc = "EOI_REN (rw) register accessor: End-of-interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi_ren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi_ren`] module"]
23334    #[doc(alias = "EOI_REN")]
23335    pub type EoiRen = crate::Reg<eoi_ren::EoiRenSpec>;
23336    #[doc = "End-of-interrupt register"]
23337    pub mod eoi_ren {
23338        #[doc = "Register `EOI_REN` reader"]
23339        pub type R = crate::R<EoiRenSpec>;
23340        #[doc = "Register `EOI_REN` writer"]
23341        pub type W = crate::W<EoiRenSpec>;
23342        #[doc = "Field `eoi` reader - Clear interrupts for all timers (read to clear)"]
23343        pub type EoiR = crate::FieldReader;
23344        impl R {
23345            #[doc = "Bits 0:2 - Clear interrupts for all timers (read to clear)"]
23346            #[inline(always)]
23347            pub fn eoi(&self) -> EoiR {
23348                EoiR::new((self.bits & 7) as u8)
23349            }
23350        }
23351        impl W {}
23352        #[doc = "End-of-interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi_ren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23353        pub struct EoiRenSpec;
23354        impl crate::RegisterSpec for EoiRenSpec {
23355            type Ux = u32;
23356        }
23357        #[doc = "`read()` method returns [`eoi_ren::R`](R) reader structure"]
23358        impl crate::Readable for EoiRenSpec {}
23359        #[doc = "`write(|w| ..)` method takes [`eoi_ren::W`](W) writer structure"]
23360        impl crate::Writable for EoiRenSpec {
23361            type Safety = crate::Unsafe;
23362        }
23363        #[doc = "`reset()` method sets EOI_REN to value 0"]
23364        impl crate::Resettable for EoiRenSpec {}
23365    }
23366    #[doc = "RAW_INTR_STAT (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"]
23367    #[doc(alias = "RAW_INTR_STAT")]
23368    pub type RawIntrStat = crate::Reg<raw_intr_stat::RawIntrStatSpec>;
23369    #[doc = "Raw interrupt status"]
23370    pub mod raw_intr_stat {
23371        #[doc = "Register `RAW_INTR_STAT` reader"]
23372        pub type R = crate::R<RawIntrStatSpec>;
23373        #[doc = "Register `RAW_INTR_STAT` writer"]
23374        pub type W = crate::W<RawIntrStatSpec>;
23375        #[doc = "Field `raw_intr` reader - Raw interrupt status for all timers"]
23376        pub type RawIntrR = crate::FieldReader;
23377        impl R {
23378            #[doc = "Bits 0:2 - Raw interrupt status for all timers"]
23379            #[inline(always)]
23380            pub fn raw_intr(&self) -> RawIntrR {
23381                RawIntrR::new((self.bits & 7) as u8)
23382            }
23383        }
23384        impl W {}
23385        #[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23386        pub struct RawIntrStatSpec;
23387        impl crate::RegisterSpec for RawIntrStatSpec {
23388            type Ux = u32;
23389        }
23390        #[doc = "`read()` method returns [`raw_intr_stat::R`](R) reader structure"]
23391        impl crate::Readable for RawIntrStatSpec {}
23392        #[doc = "`write(|w| ..)` method takes [`raw_intr_stat::W`](W) writer structure"]
23393        impl crate::Writable for RawIntrStatSpec {
23394            type Safety = crate::Unsafe;
23395        }
23396        #[doc = "`reset()` method sets RAW_INTR_STAT to value 0"]
23397        impl crate::Resettable for RawIntrStatSpec {}
23398    }
23399    #[doc = "INTR_STAT (rw) register accessor: Interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"]
23400    #[doc(alias = "INTR_STAT")]
23401    pub type IntrStat = crate::Reg<intr_stat::IntrStatSpec>;
23402    #[doc = "Interrupt status (masked)"]
23403    pub mod intr_stat {
23404        #[doc = "Register `INTR_STAT` reader"]
23405        pub type R = crate::R<IntrStatSpec>;
23406        #[doc = "Register `INTR_STAT` writer"]
23407        pub type W = crate::W<IntrStatSpec>;
23408        #[doc = "Field `intr_stat` reader - Interrupt status for all timers (after mask)"]
23409        pub type IntrStatR = crate::FieldReader;
23410        impl R {
23411            #[doc = "Bits 0:2 - Interrupt status for all timers (after mask)"]
23412            #[inline(always)]
23413            pub fn intr_stat(&self) -> IntrStatR {
23414                IntrStatR::new((self.bits & 7) as u8)
23415            }
23416        }
23417        impl W {}
23418        #[doc = "Interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23419        pub struct IntrStatSpec;
23420        impl crate::RegisterSpec for IntrStatSpec {
23421            type Ux = u32;
23422        }
23423        #[doc = "`read()` method returns [`intr_stat::R`](R) reader structure"]
23424        impl crate::Readable for IntrStatSpec {}
23425        #[doc = "`write(|w| ..)` method takes [`intr_stat::W`](W) writer structure"]
23426        impl crate::Writable for IntrStatSpec {
23427            type Safety = crate::Unsafe;
23428        }
23429        #[doc = "`reset()` method sets INTR_STAT to value 0"]
23430        impl crate::Resettable for IntrStatSpec {}
23431    }
23432    #[doc = "TIMER_LOAD_COUNT (rw) register accessor: Timer %s \\[dim=3\\] load count\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_load_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_load_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_load_count`] module"]
23433    #[doc(alias = "TIMER_LOAD_COUNT")]
23434    pub type TimerLoadCount = crate::Reg<timer_load_count::TimerLoadCountSpec>;
23435    #[doc = "Timer %s \\[dim=3\\] load count"]
23436    pub mod timer_load_count {
23437        #[doc = "Register `TIMER%s_LOAD_COUNT` reader"]
23438        pub type R = crate::R<TimerLoadCountSpec>;
23439        #[doc = "Register `TIMER%s_LOAD_COUNT` writer"]
23440        pub type W = crate::W<TimerLoadCountSpec>;
23441        #[doc = "Field `load_count` reader - Timer 0 load count value"]
23442        pub type LoadCountR = crate::FieldReader<u32>;
23443        #[doc = "Field `load_count` writer - Timer 0 load count value"]
23444        pub type LoadCountW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
23445        impl R {
23446            #[doc = "Bits 0:31 - Timer 0 load count value"]
23447            #[inline(always)]
23448            pub fn load_count(&self) -> LoadCountR {
23449                LoadCountR::new(self.bits)
23450            }
23451        }
23452        impl W {
23453            #[doc = "Bits 0:31 - Timer 0 load count value"]
23454            #[inline(always)]
23455            pub fn load_count(&mut self) -> LoadCountW<'_, TimerLoadCountSpec> {
23456                LoadCountW::new(self, 0)
23457            }
23458        }
23459        #[doc = "Timer %s \\[dim=3\\] load count\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_load_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_load_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23460        pub struct TimerLoadCountSpec;
23461        impl crate::RegisterSpec for TimerLoadCountSpec {
23462            type Ux = u32;
23463        }
23464        #[doc = "`read()` method returns [`timer_load_count::R`](R) reader structure"]
23465        impl crate::Readable for TimerLoadCountSpec {}
23466        #[doc = "`write(|w| ..)` method takes [`timer_load_count::W`](W) writer structure"]
23467        impl crate::Writable for TimerLoadCountSpec {
23468            type Safety = crate::Unsafe;
23469        }
23470        #[doc = "`reset()` method sets TIMER%s_LOAD_COUNT to value 0"]
23471        impl crate::Resettable for TimerLoadCountSpec {}
23472    }
23473    #[doc = "TIMER_CURRENT_VALUE (rw) register accessor: Timer %s \\[dim=3\\] current value\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_current_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_current_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_current_value`] module"]
23474    #[doc(alias = "TIMER_CURRENT_VALUE")]
23475    pub type TimerCurrentValue = crate::Reg<timer_current_value::TimerCurrentValueSpec>;
23476    #[doc = "Timer %s \\[dim=3\\] current value"]
23477    pub mod timer_current_value {
23478        #[doc = "Register `TIMER%s_CURRENT_VALUE` reader"]
23479        pub type R = crate::R<TimerCurrentValueSpec>;
23480        #[doc = "Register `TIMER%s_CURRENT_VALUE` writer"]
23481        pub type W = crate::W<TimerCurrentValueSpec>;
23482        #[doc = "Field `current_value` reader - Timer 0 current count value"]
23483        pub type CurrentValueR = crate::FieldReader<u32>;
23484        impl R {
23485            #[doc = "Bits 0:31 - Timer 0 current count value"]
23486            #[inline(always)]
23487            pub fn current_value(&self) -> CurrentValueR {
23488                CurrentValueR::new(self.bits)
23489            }
23490        }
23491        impl W {}
23492        #[doc = "Timer %s \\[dim=3\\] current value\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_current_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_current_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23493        pub struct TimerCurrentValueSpec;
23494        impl crate::RegisterSpec for TimerCurrentValueSpec {
23495            type Ux = u32;
23496        }
23497        #[doc = "`read()` method returns [`timer_current_value::R`](R) reader structure"]
23498        impl crate::Readable for TimerCurrentValueSpec {}
23499        #[doc = "`write(|w| ..)` method takes [`timer_current_value::W`](W) writer structure"]
23500        impl crate::Writable for TimerCurrentValueSpec {
23501            type Safety = crate::Unsafe;
23502        }
23503        #[doc = "`reset()` method sets TIMER%s_CURRENT_VALUE to value 0"]
23504        impl crate::Resettable for TimerCurrentValueSpec {}
23505    }
23506    #[doc = "TIMER_CONTROL (rw) register accessor: Timer %s \\[dim=3\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_control`] module"]
23507    #[doc(alias = "TIMER_CONTROL")]
23508    pub type TimerControl = crate::Reg<timer_control::TimerControlSpec>;
23509    #[doc = "Timer %s \\[dim=3\\] control register"]
23510    pub mod timer_control {
23511        #[doc = "Register `TIMER%s_CONTROL` reader"]
23512        pub type R = crate::R<TimerControlSpec>;
23513        #[doc = "Register `TIMER%s_CONTROL` writer"]
23514        pub type W = crate::W<TimerControlSpec>;
23515        #[doc = "Field `enable` reader - Timer enable: 0=disabled; 1=enabled"]
23516        pub type EnableR = crate::BitReader;
23517        #[doc = "Field `enable` writer - Timer enable: 0=disabled; 1=enabled"]
23518        pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
23519        #[doc = "Timer mode: 00=free running; 01=one-shot; 10=periodic\n\nValue on reset: 0"]
23520        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
23521        #[repr(u8)]
23522        pub enum Mode {
23523            #[doc = "0: Free-running mode"]
23524            FreeRunning = 0,
23525            #[doc = "1: One-shot mode"]
23526            OneShot = 1,
23527            #[doc = "2: Periodic mode"]
23528            Periodic = 2,
23529        }
23530        impl From<Mode> for u8 {
23531            #[inline(always)]
23532            fn from(variant: Mode) -> Self {
23533                variant as _
23534            }
23535        }
23536        impl crate::FieldSpec for Mode {
23537            type Ux = u8;
23538        }
23539        impl crate::IsEnum for Mode {}
23540        #[doc = "Field `mode` reader - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
23541        pub type ModeR = crate::FieldReader<Mode>;
23542        impl ModeR {
23543            #[doc = "Get enumerated values variant"]
23544            #[inline(always)]
23545            pub const fn variant(&self) -> Option<Mode> {
23546                match self.bits {
23547                    0 => Some(Mode::FreeRunning),
23548                    1 => Some(Mode::OneShot),
23549                    2 => Some(Mode::Periodic),
23550                    _ => None,
23551                }
23552            }
23553            #[doc = "Free-running mode"]
23554            #[inline(always)]
23555            pub fn is_free_running(&self) -> bool {
23556                *self == Mode::FreeRunning
23557            }
23558            #[doc = "One-shot mode"]
23559            #[inline(always)]
23560            pub fn is_one_shot(&self) -> bool {
23561                *self == Mode::OneShot
23562            }
23563            #[doc = "Periodic mode"]
23564            #[inline(always)]
23565            pub fn is_periodic(&self) -> bool {
23566                *self == Mode::Periodic
23567            }
23568        }
23569        #[doc = "Field `mode` writer - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
23570        pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mode>;
23571        impl<'a, REG> ModeW<'a, REG>
23572        where
23573            REG: crate::Writable + crate::RegisterSpec,
23574            REG::Ux: From<u8>,
23575        {
23576            #[doc = "Free-running mode"]
23577            #[inline(always)]
23578            pub fn free_running(self) -> &'a mut crate::W<REG> {
23579                self.variant(Mode::FreeRunning)
23580            }
23581            #[doc = "One-shot mode"]
23582            #[inline(always)]
23583            pub fn one_shot(self) -> &'a mut crate::W<REG> {
23584                self.variant(Mode::OneShot)
23585            }
23586            #[doc = "Periodic mode"]
23587            #[inline(always)]
23588            pub fn periodic(self) -> &'a mut crate::W<REG> {
23589                self.variant(Mode::Periodic)
23590            }
23591        }
23592        #[doc = "Field `int_mask` reader - Interrupt mask: 0=unmasked; 1=masked"]
23593        pub type IntMaskR = crate::BitReader;
23594        #[doc = "Field `int_mask` writer - Interrupt mask: 0=unmasked; 1=masked"]
23595        pub type IntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
23596        #[doc = "Field `rstfsm` writer - Reset FSM: 1=reset timer FSM"]
23597        pub type RstfsmW<'a, REG> = crate::BitWriter<'a, REG>;
23598        impl R {
23599            #[doc = "Bit 0 - Timer enable: 0=disabled; 1=enabled"]
23600            #[inline(always)]
23601            pub fn enable(&self) -> EnableR {
23602                EnableR::new((self.bits & 1) != 0)
23603            }
23604            #[doc = "Bits 1:2 - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
23605            #[inline(always)]
23606            pub fn mode(&self) -> ModeR {
23607                ModeR::new(((self.bits >> 1) & 3) as u8)
23608            }
23609            #[doc = "Bit 3 - Interrupt mask: 0=unmasked; 1=masked"]
23610            #[inline(always)]
23611            pub fn int_mask(&self) -> IntMaskR {
23612                IntMaskR::new(((self.bits >> 3) & 1) != 0)
23613            }
23614        }
23615        impl W {
23616            #[doc = "Bit 0 - Timer enable: 0=disabled; 1=enabled"]
23617            #[inline(always)]
23618            pub fn enable(&mut self) -> EnableW<'_, TimerControlSpec> {
23619                EnableW::new(self, 0)
23620            }
23621            #[doc = "Bits 1:2 - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
23622            #[inline(always)]
23623            pub fn mode(&mut self) -> ModeW<'_, TimerControlSpec> {
23624                ModeW::new(self, 1)
23625            }
23626            #[doc = "Bit 3 - Interrupt mask: 0=unmasked; 1=masked"]
23627            #[inline(always)]
23628            pub fn int_mask(&mut self) -> IntMaskW<'_, TimerControlSpec> {
23629                IntMaskW::new(self, 3)
23630            }
23631            #[doc = "Bit 4 - Reset FSM: 1=reset timer FSM"]
23632            #[inline(always)]
23633            pub fn rstfsm(&mut self) -> RstfsmW<'_, TimerControlSpec> {
23634                RstfsmW::new(self, 4)
23635            }
23636        }
23637        #[doc = "Timer %s \\[dim=3\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23638        pub struct TimerControlSpec;
23639        impl crate::RegisterSpec for TimerControlSpec {
23640            type Ux = u32;
23641        }
23642        #[doc = "`read()` method returns [`timer_control::R`](R) reader structure"]
23643        impl crate::Readable for TimerControlSpec {}
23644        #[doc = "`write(|w| ..)` method takes [`timer_control::W`](W) writer structure"]
23645        impl crate::Writable for TimerControlSpec {
23646            type Safety = crate::Unsafe;
23647        }
23648        #[doc = "`reset()` method sets TIMER%s_CONTROL to value 0"]
23649        impl crate::Resettable for TimerControlSpec {}
23650    }
23651    #[doc = "TIMER_EOI (rw) register accessor: Timer %s \\[dim=3\\] end-of-interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_eoi`] module"]
23652    #[doc(alias = "TIMER_EOI")]
23653    pub type TimerEoi = crate::Reg<timer_eoi::TimerEoiSpec>;
23654    #[doc = "Timer %s \\[dim=3\\] end-of-interrupt"]
23655    pub mod timer_eoi {
23656        #[doc = "Register `TIMER%s_EOI` reader"]
23657        pub type R = crate::R<TimerEoiSpec>;
23658        #[doc = "Register `TIMER%s_EOI` writer"]
23659        pub type W = crate::W<TimerEoiSpec>;
23660        #[doc = "Field `eoi` reader - Read to clear timer 0 interrupt"]
23661        pub type EoiR = crate::BitReader;
23662        impl R {
23663            #[doc = "Bit 0 - Read to clear timer 0 interrupt"]
23664            #[inline(always)]
23665            pub fn eoi(&self) -> EoiR {
23666                EoiR::new((self.bits & 1) != 0)
23667            }
23668        }
23669        impl W {}
23670        #[doc = "Timer %s \\[dim=3\\] end-of-interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23671        pub struct TimerEoiSpec;
23672        impl crate::RegisterSpec for TimerEoiSpec {
23673            type Ux = u32;
23674        }
23675        #[doc = "`read()` method returns [`timer_eoi::R`](R) reader structure"]
23676        impl crate::Readable for TimerEoiSpec {}
23677        #[doc = "`write(|w| ..)` method takes [`timer_eoi::W`](W) writer structure"]
23678        impl crate::Writable for TimerEoiSpec {
23679            type Safety = crate::Unsafe;
23680        }
23681        #[doc = "`reset()` method sets TIMER%s_EOI to value 0"]
23682        impl crate::Resettable for TimerEoiSpec {}
23683    }
23684    #[doc = "TIMER_RAW_INTR (rw) register accessor: Timer %s \\[dim=3\\] raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_raw_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_raw_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_raw_intr`] module"]
23685    #[doc(alias = "TIMER_RAW_INTR")]
23686    pub type TimerRawIntr = crate::Reg<timer_raw_intr::TimerRawIntrSpec>;
23687    #[doc = "Timer %s \\[dim=3\\] raw interrupt status"]
23688    pub mod timer_raw_intr {
23689        #[doc = "Register `TIMER%s_RAW_INTR` reader"]
23690        pub type R = crate::R<TimerRawIntrSpec>;
23691        #[doc = "Register `TIMER%s_RAW_INTR` writer"]
23692        pub type W = crate::W<TimerRawIntrSpec>;
23693        #[doc = "Field `raw_intr` reader - Raw interrupt status"]
23694        pub type RawIntrR = crate::BitReader;
23695        impl R {
23696            #[doc = "Bit 0 - Raw interrupt status"]
23697            #[inline(always)]
23698            pub fn raw_intr(&self) -> RawIntrR {
23699                RawIntrR::new((self.bits & 1) != 0)
23700            }
23701        }
23702        impl W {}
23703        #[doc = "Timer %s \\[dim=3\\] raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_raw_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_raw_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23704        pub struct TimerRawIntrSpec;
23705        impl crate::RegisterSpec for TimerRawIntrSpec {
23706            type Ux = u32;
23707        }
23708        #[doc = "`read()` method returns [`timer_raw_intr::R`](R) reader structure"]
23709        impl crate::Readable for TimerRawIntrSpec {}
23710        #[doc = "`write(|w| ..)` method takes [`timer_raw_intr::W`](W) writer structure"]
23711        impl crate::Writable for TimerRawIntrSpec {
23712            type Safety = crate::Unsafe;
23713        }
23714        #[doc = "`reset()` method sets TIMER%s_RAW_INTR to value 0"]
23715        impl crate::Resettable for TimerRawIntrSpec {}
23716    }
23717}
23718#[doc = "Watchdog timer (v151)"]
23719pub type Wdt = crate::Periph<wdt::RegisterBlock, 0x4000_6000>;
23720impl core::fmt::Debug for Wdt {
23721    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23722        f.debug_struct("Wdt").finish()
23723    }
23724}
23725#[doc = "Watchdog timer (v151)"]
23726pub mod wdt {
23727    #[repr(C)]
23728    #[doc = "Register block"]
23729    pub struct RegisterBlock {
23730        wdt_lock: WdtLock,
23731        wdt_load: WdtLoad,
23732        wdt_restart: WdtRestart,
23733        wdt_eoi: WdtEoi,
23734        wdt_cr: WdtCr,
23735        wdt_cnt: WdtCnt,
23736        wdt_raw_intr: WdtRawIntr,
23737        wdt_intr: WdtIntr,
23738        wdt_lpif_state: WdtLpifState,
23739        wdt_status: WdtStatus,
23740        wdt_ccvr_en: WdtCcvrEn,
23741    }
23742    impl RegisterBlock {
23743        #[doc = "0x00 - Watchdog lock register"]
23744        #[inline(always)]
23745        pub const fn wdt_lock(&self) -> &WdtLock {
23746            &self.wdt_lock
23747        }
23748        #[doc = "0x04 - Watchdog load value"]
23749        #[inline(always)]
23750        pub const fn wdt_load(&self) -> &WdtLoad {
23751            &self.wdt_load
23752        }
23753        #[doc = "0x08 - Watchdog restart register"]
23754        #[inline(always)]
23755        pub const fn wdt_restart(&self) -> &WdtRestart {
23756            &self.wdt_restart
23757        }
23758        #[doc = "0x0c - Watchdog interrupt clear (read to clear)"]
23759        #[inline(always)]
23760        pub const fn wdt_eoi(&self) -> &WdtEoi {
23761            &self.wdt_eoi
23762        }
23763        #[doc = "0x10 - Watchdog control register"]
23764        #[inline(always)]
23765        pub const fn wdt_cr(&self) -> &WdtCr {
23766            &self.wdt_cr
23767        }
23768        #[doc = "0x14 - Watchdog current counter value"]
23769        #[inline(always)]
23770        pub const fn wdt_cnt(&self) -> &WdtCnt {
23771            &self.wdt_cnt
23772        }
23773        #[doc = "0x18 - Watchdog raw interrupt status"]
23774        #[inline(always)]
23775        pub const fn wdt_raw_intr(&self) -> &WdtRawIntr {
23776            &self.wdt_raw_intr
23777        }
23778        #[doc = "0x1c - Watchdog interrupt status (masked)"]
23779        #[inline(always)]
23780        pub const fn wdt_intr(&self) -> &WdtIntr {
23781            &self.wdt_intr
23782        }
23783        #[doc = "0x20 - Watchdog low power state"]
23784        #[inline(always)]
23785        pub const fn wdt_lpif_state(&self) -> &WdtLpifState {
23786            &self.wdt_lpif_state
23787        }
23788        #[doc = "0x24 - Watchdog status"]
23789        #[inline(always)]
23790        pub const fn wdt_status(&self) -> &WdtStatus {
23791            &self.wdt_status
23792        }
23793        #[doc = "0x28 - Watchdog counter value request"]
23794        #[inline(always)]
23795        pub const fn wdt_ccvr_en(&self) -> &WdtCcvrEn {
23796            &self.wdt_ccvr_en
23797        }
23798    }
23799    #[doc = "WDT_LOCK (rw) register accessor: Watchdog lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_lock`] module"]
23800    #[doc(alias = "WDT_LOCK")]
23801    pub type WdtLock = crate::Reg<wdt_lock::WdtLockSpec>;
23802    #[doc = "Watchdog lock register"]
23803    pub mod wdt_lock {
23804        #[doc = "Register `WDT_LOCK` reader"]
23805        pub type R = crate::R<WdtLockSpec>;
23806        #[doc = "Register `WDT_LOCK` writer"]
23807        pub type W = crate::W<WdtLockSpec>;
23808        #[doc = "Field `wdt_lock` writer - Write 0x5A5A5A5A to unlock, other values lock"]
23809        pub type WdtLockW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
23810        impl W {
23811            #[doc = "Bits 0:31 - Write 0x5A5A5A5A to unlock, other values lock"]
23812            #[inline(always)]
23813            pub fn wdt_lock(&mut self) -> WdtLockW<'_, WdtLockSpec> {
23814                WdtLockW::new(self, 0)
23815            }
23816        }
23817        #[doc = "Watchdog lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23818        pub struct WdtLockSpec;
23819        impl crate::RegisterSpec for WdtLockSpec {
23820            type Ux = u32;
23821        }
23822        #[doc = "`read()` method returns [`wdt_lock::R`](R) reader structure"]
23823        impl crate::Readable for WdtLockSpec {}
23824        #[doc = "`write(|w| ..)` method takes [`wdt_lock::W`](W) writer structure"]
23825        impl crate::Writable for WdtLockSpec {
23826            type Safety = crate::Unsafe;
23827        }
23828        #[doc = "`reset()` method sets WDT_LOCK to value 0"]
23829        impl crate::Resettable for WdtLockSpec {}
23830    }
23831    #[doc = "WDT_LOAD (rw) register accessor: Watchdog load value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_load::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_load::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_load`] module"]
23832    #[doc(alias = "WDT_LOAD")]
23833    pub type WdtLoad = crate::Reg<wdt_load::WdtLoadSpec>;
23834    #[doc = "Watchdog load value"]
23835    pub mod wdt_load {
23836        #[doc = "Register `WDT_LOAD` reader"]
23837        pub type R = crate::R<WdtLoadSpec>;
23838        #[doc = "Register `WDT_LOAD` writer"]
23839        pub type W = crate::W<WdtLoadSpec>;
23840        #[doc = "Field `wdt_load` reader - Load count value (24-bit, low 8 bits reserved)"]
23841        pub type WdtLoadR = crate::FieldReader<u32>;
23842        #[doc = "Field `wdt_load` writer - Load count value (24-bit, low 8 bits reserved)"]
23843        pub type WdtLoadW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
23844        impl R {
23845            #[doc = "Bits 8:31 - Load count value (24-bit, low 8 bits reserved)"]
23846            #[inline(always)]
23847            pub fn wdt_load(&self) -> WdtLoadR {
23848                WdtLoadR::new((self.bits >> 8) & 0x00ff_ffff)
23849            }
23850        }
23851        impl W {
23852            #[doc = "Bits 8:31 - Load count value (24-bit, low 8 bits reserved)"]
23853            #[inline(always)]
23854            pub fn wdt_load(&mut self) -> WdtLoadW<'_, WdtLoadSpec> {
23855                WdtLoadW::new(self, 8)
23856            }
23857        }
23858        #[doc = "Watchdog load value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_load::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_load::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23859        pub struct WdtLoadSpec;
23860        impl crate::RegisterSpec for WdtLoadSpec {
23861            type Ux = u32;
23862        }
23863        #[doc = "`read()` method returns [`wdt_load::R`](R) reader structure"]
23864        impl crate::Readable for WdtLoadSpec {}
23865        #[doc = "`write(|w| ..)` method takes [`wdt_load::W`](W) writer structure"]
23866        impl crate::Writable for WdtLoadSpec {
23867            type Safety = crate::Unsafe;
23868        }
23869        #[doc = "`reset()` method sets WDT_LOAD to value 0"]
23870        impl crate::Resettable for WdtLoadSpec {}
23871    }
23872    #[doc = "WDT_RESTART (rw) register accessor: Watchdog restart register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_restart::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_restart::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_restart`] module"]
23873    #[doc(alias = "WDT_RESTART")]
23874    pub type WdtRestart = crate::Reg<wdt_restart::WdtRestartSpec>;
23875    #[doc = "Watchdog restart register"]
23876    pub mod wdt_restart {
23877        #[doc = "Register `WDT_RESTART` reader"]
23878        pub type R = crate::R<WdtRestartSpec>;
23879        #[doc = "Register `WDT_RESTART` writer"]
23880        pub type W = crate::W<WdtRestartSpec>;
23881        #[doc = "Field `wdt_restart` writer - Write anything except 0x5A5A5A5A to restart counter"]
23882        pub type WdtRestartW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
23883        impl W {
23884            #[doc = "Bits 0:31 - Write anything except 0x5A5A5A5A to restart counter"]
23885            #[inline(always)]
23886            pub fn wdt_restart(&mut self) -> WdtRestartW<'_, WdtRestartSpec> {
23887                WdtRestartW::new(self, 0)
23888            }
23889        }
23890        #[doc = "Watchdog restart register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_restart::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_restart::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23891        pub struct WdtRestartSpec;
23892        impl crate::RegisterSpec for WdtRestartSpec {
23893            type Ux = u32;
23894        }
23895        #[doc = "`read()` method returns [`wdt_restart::R`](R) reader structure"]
23896        impl crate::Readable for WdtRestartSpec {}
23897        #[doc = "`write(|w| ..)` method takes [`wdt_restart::W`](W) writer structure"]
23898        impl crate::Writable for WdtRestartSpec {
23899            type Safety = crate::Unsafe;
23900        }
23901        #[doc = "`reset()` method sets WDT_RESTART to value 0"]
23902        impl crate::Resettable for WdtRestartSpec {}
23903    }
23904    #[doc = "WDT_EOI (rw) register accessor: Watchdog interrupt clear (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_eoi`] module"]
23905    #[doc(alias = "WDT_EOI")]
23906    pub type WdtEoi = crate::Reg<wdt_eoi::WdtEoiSpec>;
23907    #[doc = "Watchdog interrupt clear (read to clear)"]
23908    pub mod wdt_eoi {
23909        #[doc = "Register `WDT_EOI` reader"]
23910        pub type R = crate::R<WdtEoiSpec>;
23911        #[doc = "Register `WDT_EOI` writer"]
23912        pub type W = crate::W<WdtEoiSpec>;
23913        #[doc = "Field `wdt_eoi` reader - Read to clear watchdog interrupt"]
23914        pub type WdtEoiR = crate::BitReader;
23915        impl R {
23916            #[doc = "Bit 0 - Read to clear watchdog interrupt"]
23917            #[inline(always)]
23918            pub fn wdt_eoi(&self) -> WdtEoiR {
23919                WdtEoiR::new((self.bits & 1) != 0)
23920            }
23921        }
23922        impl W {}
23923        #[doc = "Watchdog interrupt clear (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23924        pub struct WdtEoiSpec;
23925        impl crate::RegisterSpec for WdtEoiSpec {
23926            type Ux = u32;
23927        }
23928        #[doc = "`read()` method returns [`wdt_eoi::R`](R) reader structure"]
23929        impl crate::Readable for WdtEoiSpec {}
23930        #[doc = "`write(|w| ..)` method takes [`wdt_eoi::W`](W) writer structure"]
23931        impl crate::Writable for WdtEoiSpec {
23932            type Safety = crate::Unsafe;
23933        }
23934        #[doc = "`reset()` method sets WDT_EOI to value 0"]
23935        impl crate::Resettable for WdtEoiSpec {}
23936    }
23937    #[doc = "WDT_CR (rw) register accessor: Watchdog control register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cr`] module"]
23938    #[doc(alias = "WDT_CR")]
23939    pub type WdtCr = crate::Reg<wdt_cr::WdtCrSpec>;
23940    #[doc = "Watchdog control register"]
23941    pub mod wdt_cr {
23942        #[doc = "Register `WDT_CR` reader"]
23943        pub type R = crate::R<WdtCrSpec>;
23944        #[doc = "Register `WDT_CR` writer"]
23945        pub type W = crate::W<WdtCrSpec>;
23946        #[doc = "Field `wdt_en` reader - Watchdog enable: 0=disabled; 1=enabled"]
23947        pub type WdtEnR = crate::BitReader;
23948        #[doc = "Field `wdt_en` writer - Watchdog enable: 0=disabled; 1=enabled"]
23949        pub type WdtEnW<'a, REG> = crate::BitWriter<'a, REG>;
23950        #[doc = "Field `rst_en` reader - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
23951        pub type RstEnR = crate::BitReader;
23952        #[doc = "Field `rst_en` writer - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
23953        pub type RstEnW<'a, REG> = crate::BitWriter<'a, REG>;
23954        #[doc = "Field `rst_pl` reader - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
23955        pub type RstPlR = crate::FieldReader;
23956        #[doc = "Field `rst_pl` writer - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
23957        pub type RstPlW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
23958        #[doc = "Field `wdt_imsk` reader - Interrupt mask: 0=unmasked; 1=masked"]
23959        pub type WdtImskR = crate::BitReader;
23960        #[doc = "Field `wdt_imsk` writer - Interrupt mask: 0=unmasked; 1=masked"]
23961        pub type WdtImskW<'a, REG> = crate::BitWriter<'a, REG>;
23962        #[doc = "Mode: 0=one interrupt then reset; 1=two interrupts then reset\n\nValue on reset: 0"]
23963        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
23964        pub enum WdtMode {
23965            #[doc = "0: Single interrupt then reset"]
23966            Mode1 = 0,
23967            #[doc = "1: Two interrupts then reset"]
23968            Mode2 = 1,
23969        }
23970        impl From<WdtMode> for bool {
23971            #[inline(always)]
23972            fn from(variant: WdtMode) -> Self {
23973                variant as u8 != 0
23974            }
23975        }
23976        #[doc = "Field `wdt_mode` reader - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
23977        pub type WdtModeR = crate::BitReader<WdtMode>;
23978        impl WdtModeR {
23979            #[doc = "Get enumerated values variant"]
23980            #[inline(always)]
23981            pub const fn variant(&self) -> WdtMode {
23982                match self.bits {
23983                    false => WdtMode::Mode1,
23984                    true => WdtMode::Mode2,
23985                }
23986            }
23987            #[doc = "Single interrupt then reset"]
23988            #[inline(always)]
23989            pub fn is_mode1(&self) -> bool {
23990                *self == WdtMode::Mode1
23991            }
23992            #[doc = "Two interrupts then reset"]
23993            #[inline(always)]
23994            pub fn is_mode2(&self) -> bool {
23995                *self == WdtMode::Mode2
23996            }
23997        }
23998        #[doc = "Field `wdt_mode` writer - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
23999        pub type WdtModeW<'a, REG> = crate::BitWriter<'a, REG, WdtMode>;
24000        impl<'a, REG> WdtModeW<'a, REG>
24001        where
24002            REG: crate::Writable + crate::RegisterSpec,
24003        {
24004            #[doc = "Single interrupt then reset"]
24005            #[inline(always)]
24006            pub fn mode1(self) -> &'a mut crate::W<REG> {
24007                self.variant(WdtMode::Mode1)
24008            }
24009            #[doc = "Two interrupts then reset"]
24010            #[inline(always)]
24011            pub fn mode2(self) -> &'a mut crate::W<REG> {
24012                self.variant(WdtMode::Mode2)
24013            }
24014        }
24015        impl R {
24016            #[doc = "Bit 0 - Watchdog enable: 0=disabled; 1=enabled"]
24017            #[inline(always)]
24018            pub fn wdt_en(&self) -> WdtEnR {
24019                WdtEnR::new((self.bits & 1) != 0)
24020            }
24021            #[doc = "Bit 2 - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
24022            #[inline(always)]
24023            pub fn rst_en(&self) -> RstEnR {
24024                RstEnR::new(((self.bits >> 2) & 1) != 0)
24025            }
24026            #[doc = "Bits 3:5 - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
24027            #[inline(always)]
24028            pub fn rst_pl(&self) -> RstPlR {
24029                RstPlR::new(((self.bits >> 3) & 7) as u8)
24030            }
24031            #[doc = "Bit 6 - Interrupt mask: 0=unmasked; 1=masked"]
24032            #[inline(always)]
24033            pub fn wdt_imsk(&self) -> WdtImskR {
24034                WdtImskR::new(((self.bits >> 6) & 1) != 0)
24035            }
24036            #[doc = "Bit 7 - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
24037            #[inline(always)]
24038            pub fn wdt_mode(&self) -> WdtModeR {
24039                WdtModeR::new(((self.bits >> 7) & 1) != 0)
24040            }
24041        }
24042        impl W {
24043            #[doc = "Bit 0 - Watchdog enable: 0=disabled; 1=enabled"]
24044            #[inline(always)]
24045            pub fn wdt_en(&mut self) -> WdtEnW<'_, WdtCrSpec> {
24046                WdtEnW::new(self, 0)
24047            }
24048            #[doc = "Bit 2 - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
24049            #[inline(always)]
24050            pub fn rst_en(&mut self) -> RstEnW<'_, WdtCrSpec> {
24051                RstEnW::new(self, 2)
24052            }
24053            #[doc = "Bits 3:5 - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
24054            #[inline(always)]
24055            pub fn rst_pl(&mut self) -> RstPlW<'_, WdtCrSpec> {
24056                RstPlW::new(self, 3)
24057            }
24058            #[doc = "Bit 6 - Interrupt mask: 0=unmasked; 1=masked"]
24059            #[inline(always)]
24060            pub fn wdt_imsk(&mut self) -> WdtImskW<'_, WdtCrSpec> {
24061                WdtImskW::new(self, 6)
24062            }
24063            #[doc = "Bit 7 - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
24064            #[inline(always)]
24065            pub fn wdt_mode(&mut self) -> WdtModeW<'_, WdtCrSpec> {
24066                WdtModeW::new(self, 7)
24067            }
24068        }
24069        #[doc = "Watchdog control register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24070        pub struct WdtCrSpec;
24071        impl crate::RegisterSpec for WdtCrSpec {
24072            type Ux = u32;
24073        }
24074        #[doc = "`read()` method returns [`wdt_cr::R`](R) reader structure"]
24075        impl crate::Readable for WdtCrSpec {}
24076        #[doc = "`write(|w| ..)` method takes [`wdt_cr::W`](W) writer structure"]
24077        impl crate::Writable for WdtCrSpec {
24078            type Safety = crate::Unsafe;
24079        }
24080        #[doc = "`reset()` method sets WDT_CR to value 0"]
24081        impl crate::Resettable for WdtCrSpec {}
24082    }
24083    #[doc = "WDT_CNT (rw) register accessor: Watchdog current counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cnt`] module"]
24084    #[doc(alias = "WDT_CNT")]
24085    pub type WdtCnt = crate::Reg<wdt_cnt::WdtCntSpec>;
24086    #[doc = "Watchdog current counter value"]
24087    pub mod wdt_cnt {
24088        #[doc = "Register `WDT_CNT` reader"]
24089        pub type R = crate::R<WdtCntSpec>;
24090        #[doc = "Register `WDT_CNT` writer"]
24091        pub type W = crate::W<WdtCntSpec>;
24092        #[doc = "Field `wdt_cnt` reader - Current counter value"]
24093        pub type WdtCntR = crate::FieldReader<u32>;
24094        impl R {
24095            #[doc = "Bits 0:31 - Current counter value"]
24096            #[inline(always)]
24097            pub fn wdt_cnt(&self) -> WdtCntR {
24098                WdtCntR::new(self.bits)
24099            }
24100        }
24101        impl W {}
24102        #[doc = "Watchdog current counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24103        pub struct WdtCntSpec;
24104        impl crate::RegisterSpec for WdtCntSpec {
24105            type Ux = u32;
24106        }
24107        #[doc = "`read()` method returns [`wdt_cnt::R`](R) reader structure"]
24108        impl crate::Readable for WdtCntSpec {}
24109        #[doc = "`write(|w| ..)` method takes [`wdt_cnt::W`](W) writer structure"]
24110        impl crate::Writable for WdtCntSpec {
24111            type Safety = crate::Unsafe;
24112        }
24113        #[doc = "`reset()` method sets WDT_CNT to value 0"]
24114        impl crate::Resettable for WdtCntSpec {}
24115    }
24116    #[doc = "WDT_RAW_INTR (rw) register accessor: Watchdog raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_raw_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_raw_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_raw_intr`] module"]
24117    #[doc(alias = "WDT_RAW_INTR")]
24118    pub type WdtRawIntr = crate::Reg<wdt_raw_intr::WdtRawIntrSpec>;
24119    #[doc = "Watchdog raw interrupt status"]
24120    pub mod wdt_raw_intr {
24121        #[doc = "Register `WDT_RAW_INTR` reader"]
24122        pub type R = crate::R<WdtRawIntrSpec>;
24123        #[doc = "Register `WDT_RAW_INTR` writer"]
24124        pub type W = crate::W<WdtRawIntrSpec>;
24125        #[doc = "Field `wdt_raw_intr` reader - Raw interrupt status"]
24126        pub type WdtRawIntrR = crate::BitReader;
24127        impl R {
24128            #[doc = "Bit 0 - Raw interrupt status"]
24129            #[inline(always)]
24130            pub fn wdt_raw_intr(&self) -> WdtRawIntrR {
24131                WdtRawIntrR::new((self.bits & 1) != 0)
24132            }
24133        }
24134        impl W {}
24135        #[doc = "Watchdog raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_raw_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_raw_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24136        pub struct WdtRawIntrSpec;
24137        impl crate::RegisterSpec for WdtRawIntrSpec {
24138            type Ux = u32;
24139        }
24140        #[doc = "`read()` method returns [`wdt_raw_intr::R`](R) reader structure"]
24141        impl crate::Readable for WdtRawIntrSpec {}
24142        #[doc = "`write(|w| ..)` method takes [`wdt_raw_intr::W`](W) writer structure"]
24143        impl crate::Writable for WdtRawIntrSpec {
24144            type Safety = crate::Unsafe;
24145        }
24146        #[doc = "`reset()` method sets WDT_RAW_INTR to value 0"]
24147        impl crate::Resettable for WdtRawIntrSpec {}
24148    }
24149    #[doc = "WDT_INTR (rw) register accessor: Watchdog interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_intr`] module"]
24150    #[doc(alias = "WDT_INTR")]
24151    pub type WdtIntr = crate::Reg<wdt_intr::WdtIntrSpec>;
24152    #[doc = "Watchdog interrupt status (masked)"]
24153    pub mod wdt_intr {
24154        #[doc = "Register `WDT_INTR` reader"]
24155        pub type R = crate::R<WdtIntrSpec>;
24156        #[doc = "Register `WDT_INTR` writer"]
24157        pub type W = crate::W<WdtIntrSpec>;
24158        #[doc = "Field `wdt_intr` reader - Interrupt status after mask"]
24159        pub type WdtIntrR = crate::BitReader;
24160        impl R {
24161            #[doc = "Bit 0 - Interrupt status after mask"]
24162            #[inline(always)]
24163            pub fn wdt_intr(&self) -> WdtIntrR {
24164                WdtIntrR::new((self.bits & 1) != 0)
24165            }
24166        }
24167        impl W {}
24168        #[doc = "Watchdog interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24169        pub struct WdtIntrSpec;
24170        impl crate::RegisterSpec for WdtIntrSpec {
24171            type Ux = u32;
24172        }
24173        #[doc = "`read()` method returns [`wdt_intr::R`](R) reader structure"]
24174        impl crate::Readable for WdtIntrSpec {}
24175        #[doc = "`write(|w| ..)` method takes [`wdt_intr::W`](W) writer structure"]
24176        impl crate::Writable for WdtIntrSpec {
24177            type Safety = crate::Unsafe;
24178        }
24179        #[doc = "`reset()` method sets WDT_INTR to value 0"]
24180        impl crate::Resettable for WdtIntrSpec {}
24181    }
24182    #[doc = "WDT_LPIF_STATE (rw) register accessor: Watchdog low power state\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lpif_state::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lpif_state::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_lpif_state`] module"]
24183    #[doc(alias = "WDT_LPIF_STATE")]
24184    pub type WdtLpifState = crate::Reg<wdt_lpif_state::WdtLpifStateSpec>;
24185    #[doc = "Watchdog low power state"]
24186    pub mod wdt_lpif_state {
24187        #[doc = "Register `WDT_LPIF_STATE` reader"]
24188        pub type R = crate::R<WdtLpifStateSpec>;
24189        #[doc = "Register `WDT_LPIF_STATE` writer"]
24190        pub type W = crate::W<WdtLpifStateSpec>;
24191        #[doc = "Field `wdt_lpif_state` reader - Low power interface state"]
24192        pub type WdtLpifStateR = crate::FieldReader;
24193        impl R {
24194            #[doc = "Bits 0:2 - Low power interface state"]
24195            #[inline(always)]
24196            pub fn wdt_lpif_state(&self) -> WdtLpifStateR {
24197                WdtLpifStateR::new((self.bits & 7) as u8)
24198            }
24199        }
24200        impl W {}
24201        #[doc = "Watchdog low power state\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lpif_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lpif_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24202        pub struct WdtLpifStateSpec;
24203        impl crate::RegisterSpec for WdtLpifStateSpec {
24204            type Ux = u32;
24205        }
24206        #[doc = "`read()` method returns [`wdt_lpif_state::R`](R) reader structure"]
24207        impl crate::Readable for WdtLpifStateSpec {}
24208        #[doc = "`write(|w| ..)` method takes [`wdt_lpif_state::W`](W) writer structure"]
24209        impl crate::Writable for WdtLpifStateSpec {
24210            type Safety = crate::Unsafe;
24211        }
24212        #[doc = "`reset()` method sets WDT_LPIF_STATE to value 0"]
24213        impl crate::Resettable for WdtLpifStateSpec {}
24214    }
24215    #[doc = "WDT_STATUS (rw) register accessor: Watchdog status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_status`] module"]
24216    #[doc(alias = "WDT_STATUS")]
24217    pub type WdtStatus = crate::Reg<wdt_status::WdtStatusSpec>;
24218    #[doc = "Watchdog status"]
24219    pub mod wdt_status {
24220        #[doc = "Register `WDT_STATUS` reader"]
24221        pub type R = crate::R<WdtStatusSpec>;
24222        #[doc = "Register `WDT_STATUS` writer"]
24223        pub type W = crate::W<WdtStatusSpec>;
24224        #[doc = "Field `wdt_status` reader - Status: 0=busy; 1=free"]
24225        pub type WdtStatusR = crate::BitReader;
24226        impl R {
24227            #[doc = "Bit 0 - Status: 0=busy; 1=free"]
24228            #[inline(always)]
24229            pub fn wdt_status(&self) -> WdtStatusR {
24230                WdtStatusR::new((self.bits & 1) != 0)
24231            }
24232        }
24233        impl W {}
24234        #[doc = "Watchdog status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24235        pub struct WdtStatusSpec;
24236        impl crate::RegisterSpec for WdtStatusSpec {
24237            type Ux = u32;
24238        }
24239        #[doc = "`read()` method returns [`wdt_status::R`](R) reader structure"]
24240        impl crate::Readable for WdtStatusSpec {}
24241        #[doc = "`write(|w| ..)` method takes [`wdt_status::W`](W) writer structure"]
24242        impl crate::Writable for WdtStatusSpec {
24243            type Safety = crate::Unsafe;
24244        }
24245        #[doc = "`reset()` method sets WDT_STATUS to value 0"]
24246        impl crate::Resettable for WdtStatusSpec {}
24247    }
24248    #[doc = "WDT_CCVR_EN (rw) register accessor: Watchdog counter value request\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_ccvr_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_ccvr_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_ccvr_en`] module"]
24249    #[doc(alias = "WDT_CCVR_EN")]
24250    pub type WdtCcvrEn = crate::Reg<wdt_ccvr_en::WdtCcvrEnSpec>;
24251    #[doc = "Watchdog counter value request"]
24252    pub mod wdt_ccvr_en {
24253        #[doc = "Register `WDT_CCVR_EN` reader"]
24254        pub type R = crate::R<WdtCcvrEnSpec>;
24255        #[doc = "Register `WDT_CCVR_EN` writer"]
24256        pub type W = crate::W<WdtCcvrEnSpec>;
24257        #[doc = "Field `ccvr_req` writer - Write 1 to request current counter value"]
24258        pub type CcvrReqW<'a, REG> = crate::BitWriter<'a, REG>;
24259        #[doc = "Field `ccvr_ack` reader - Acknowledge: 1=counter value valid"]
24260        pub type CcvrAckR = crate::BitReader;
24261        impl R {
24262            #[doc = "Bit 1 - Acknowledge: 1=counter value valid"]
24263            #[inline(always)]
24264            pub fn ccvr_ack(&self) -> CcvrAckR {
24265                CcvrAckR::new(((self.bits >> 1) & 1) != 0)
24266            }
24267        }
24268        impl W {
24269            #[doc = "Bit 0 - Write 1 to request current counter value"]
24270            #[inline(always)]
24271            pub fn ccvr_req(&mut self) -> CcvrReqW<'_, WdtCcvrEnSpec> {
24272                CcvrReqW::new(self, 0)
24273            }
24274        }
24275        #[doc = "Watchdog counter value request\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_ccvr_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_ccvr_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24276        pub struct WdtCcvrEnSpec;
24277        impl crate::RegisterSpec for WdtCcvrEnSpec {
24278            type Ux = u32;
24279        }
24280        #[doc = "`read()` method returns [`wdt_ccvr_en::R`](R) reader structure"]
24281        impl crate::Readable for WdtCcvrEnSpec {}
24282        #[doc = "`write(|w| ..)` method takes [`wdt_ccvr_en::W`](W) writer structure"]
24283        impl crate::Writable for WdtCcvrEnSpec {
24284            type Safety = crate::Unsafe;
24285        }
24286        #[doc = "`reset()` method sets WDT_CCVR_EN to value 0"]
24287        impl crate::Resettable for WdtCcvrEnSpec {}
24288    }
24289}
24290#[doc = "Real-time clock (48-bit free-running counter, v100)"]
24291pub type Rtc = crate::Periph<rtc::RegisterBlock, 0x5702_4000>;
24292impl core::fmt::Debug for Rtc {
24293    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
24294        f.debug_struct("Rtc").finish()
24295    }
24296}
24297#[doc = "Real-time clock (48-bit free-running counter, v100)"]
24298pub mod rtc {
24299    #[repr(C)]
24300    #[doc = "Register block"]
24301    pub struct RegisterBlock {
24302        rtc_load_count: RtcLoadCount,
24303        rtc_current_value: RtcCurrentValue,
24304        rtc_control: RtcControl,
24305        rtc_eoi: RtcEoi,
24306        rtc_int_status: RtcIntStatus,
24307    }
24308    impl RegisterBlock {
24309        #[doc = "0x00 - RTC load count register"]
24310        #[inline(always)]
24311        pub const fn rtc_load_count(&self) -> &RtcLoadCount {
24312            &self.rtc_load_count
24313        }
24314        #[doc = "0x04 - RTC current count value"]
24315        #[inline(always)]
24316        pub const fn rtc_current_value(&self) -> &RtcCurrentValue {
24317            &self.rtc_current_value
24318        }
24319        #[doc = "0x08 - RTC control register"]
24320        #[inline(always)]
24321        pub const fn rtc_control(&self) -> &RtcControl {
24322            &self.rtc_control
24323        }
24324        #[doc = "0x0c - RTC end-of-interrupt (read to clear)"]
24325        #[inline(always)]
24326        pub const fn rtc_eoi(&self) -> &RtcEoi {
24327            &self.rtc_eoi
24328        }
24329        #[doc = "0x10 - RTC interrupt status"]
24330        #[inline(always)]
24331        pub const fn rtc_int_status(&self) -> &RtcIntStatus {
24332            &self.rtc_int_status
24333        }
24334    }
24335    #[doc = "RTC_LOAD_COUNT (rw) register accessor: RTC load count register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_load_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_load_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_load_count`] module"]
24336    #[doc(alias = "RTC_LOAD_COUNT")]
24337    pub type RtcLoadCount = crate::Reg<rtc_load_count::RtcLoadCountSpec>;
24338    #[doc = "RTC load count register"]
24339    pub mod rtc_load_count {
24340        #[doc = "Register `RTC_LOAD_COUNT` reader"]
24341        pub type R = crate::R<RtcLoadCountSpec>;
24342        #[doc = "Register `RTC_LOAD_COUNT` writer"]
24343        pub type W = crate::W<RtcLoadCountSpec>;
24344        #[doc = "Field `load_count` reader - Load count value (threshold for interrupt)"]
24345        pub type LoadCountR = crate::FieldReader<u32>;
24346        #[doc = "Field `load_count` writer - Load count value (threshold for interrupt)"]
24347        pub type LoadCountW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
24348        impl R {
24349            #[doc = "Bits 0:31 - Load count value (threshold for interrupt)"]
24350            #[inline(always)]
24351            pub fn load_count(&self) -> LoadCountR {
24352                LoadCountR::new(self.bits)
24353            }
24354        }
24355        impl W {
24356            #[doc = "Bits 0:31 - Load count value (threshold for interrupt)"]
24357            #[inline(always)]
24358            pub fn load_count(&mut self) -> LoadCountW<'_, RtcLoadCountSpec> {
24359                LoadCountW::new(self, 0)
24360            }
24361        }
24362        #[doc = "RTC load count register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_load_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_load_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24363        pub struct RtcLoadCountSpec;
24364        impl crate::RegisterSpec for RtcLoadCountSpec {
24365            type Ux = u32;
24366        }
24367        #[doc = "`read()` method returns [`rtc_load_count::R`](R) reader structure"]
24368        impl crate::Readable for RtcLoadCountSpec {}
24369        #[doc = "`write(|w| ..)` method takes [`rtc_load_count::W`](W) writer structure"]
24370        impl crate::Writable for RtcLoadCountSpec {
24371            type Safety = crate::Unsafe;
24372        }
24373        #[doc = "`reset()` method sets RTC_LOAD_COUNT to value 0"]
24374        impl crate::Resettable for RtcLoadCountSpec {}
24375    }
24376    #[doc = "RTC_CURRENT_VALUE (rw) register accessor: RTC current count value\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_current_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_current_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_current_value`] module"]
24377    #[doc(alias = "RTC_CURRENT_VALUE")]
24378    pub type RtcCurrentValue = crate::Reg<rtc_current_value::RtcCurrentValueSpec>;
24379    #[doc = "RTC current count value"]
24380    pub mod rtc_current_value {
24381        #[doc = "Register `RTC_CURRENT_VALUE` reader"]
24382        pub type R = crate::R<RtcCurrentValueSpec>;
24383        #[doc = "Register `RTC_CURRENT_VALUE` writer"]
24384        pub type W = crate::W<RtcCurrentValueSpec>;
24385        #[doc = "Field `current_value` reader - Current counter value"]
24386        pub type CurrentValueR = crate::FieldReader<u32>;
24387        impl R {
24388            #[doc = "Bits 0:31 - Current counter value"]
24389            #[inline(always)]
24390            pub fn current_value(&self) -> CurrentValueR {
24391                CurrentValueR::new(self.bits)
24392            }
24393        }
24394        impl W {}
24395        #[doc = "RTC current count value\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_current_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_current_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24396        pub struct RtcCurrentValueSpec;
24397        impl crate::RegisterSpec for RtcCurrentValueSpec {
24398            type Ux = u32;
24399        }
24400        #[doc = "`read()` method returns [`rtc_current_value::R`](R) reader structure"]
24401        impl crate::Readable for RtcCurrentValueSpec {}
24402        #[doc = "`write(|w| ..)` method takes [`rtc_current_value::W`](W) writer structure"]
24403        impl crate::Writable for RtcCurrentValueSpec {
24404            type Safety = crate::Unsafe;
24405        }
24406        #[doc = "`reset()` method sets RTC_CURRENT_VALUE to value 0"]
24407        impl crate::Resettable for RtcCurrentValueSpec {}
24408    }
24409    #[doc = "RTC_CONTROL (rw) register accessor: RTC control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_control`] module"]
24410    #[doc(alias = "RTC_CONTROL")]
24411    pub type RtcControl = crate::Reg<rtc_control::RtcControlSpec>;
24412    #[doc = "RTC control register"]
24413    pub mod rtc_control {
24414        #[doc = "Register `RTC_CONTROL` reader"]
24415        pub type R = crate::R<RtcControlSpec>;
24416        #[doc = "Register `RTC_CONTROL` writer"]
24417        pub type W = crate::W<RtcControlSpec>;
24418        #[doc = "Field `enable` reader - RTC enable"]
24419        pub type EnableR = crate::BitReader;
24420        #[doc = "Field `enable` writer - RTC enable"]
24421        pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
24422        #[doc = "Field `mode` reader - Mode: 0=free running; 1=periodic"]
24423        pub type ModeR = crate::BitReader;
24424        #[doc = "Field `mode` writer - Mode: 0=free running; 1=periodic"]
24425        pub type ModeW<'a, REG> = crate::BitWriter<'a, REG>;
24426        #[doc = "Field `int_mask` reader - Interrupt mask: 0=unmasked; 1=masked"]
24427        pub type IntMaskR = crate::BitReader;
24428        #[doc = "Field `int_mask` writer - Interrupt mask: 0=unmasked; 1=masked"]
24429        pub type IntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
24430        impl R {
24431            #[doc = "Bit 0 - RTC enable"]
24432            #[inline(always)]
24433            pub fn enable(&self) -> EnableR {
24434                EnableR::new((self.bits & 1) != 0)
24435            }
24436            #[doc = "Bit 1 - Mode: 0=free running; 1=periodic"]
24437            #[inline(always)]
24438            pub fn mode(&self) -> ModeR {
24439                ModeR::new(((self.bits >> 1) & 1) != 0)
24440            }
24441            #[doc = "Bit 2 - Interrupt mask: 0=unmasked; 1=masked"]
24442            #[inline(always)]
24443            pub fn int_mask(&self) -> IntMaskR {
24444                IntMaskR::new(((self.bits >> 2) & 1) != 0)
24445            }
24446        }
24447        impl W {
24448            #[doc = "Bit 0 - RTC enable"]
24449            #[inline(always)]
24450            pub fn enable(&mut self) -> EnableW<'_, RtcControlSpec> {
24451                EnableW::new(self, 0)
24452            }
24453            #[doc = "Bit 1 - Mode: 0=free running; 1=periodic"]
24454            #[inline(always)]
24455            pub fn mode(&mut self) -> ModeW<'_, RtcControlSpec> {
24456                ModeW::new(self, 1)
24457            }
24458            #[doc = "Bit 2 - Interrupt mask: 0=unmasked; 1=masked"]
24459            #[inline(always)]
24460            pub fn int_mask(&mut self) -> IntMaskW<'_, RtcControlSpec> {
24461                IntMaskW::new(self, 2)
24462            }
24463        }
24464        #[doc = "RTC control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24465        pub struct RtcControlSpec;
24466        impl crate::RegisterSpec for RtcControlSpec {
24467            type Ux = u32;
24468        }
24469        #[doc = "`read()` method returns [`rtc_control::R`](R) reader structure"]
24470        impl crate::Readable for RtcControlSpec {}
24471        #[doc = "`write(|w| ..)` method takes [`rtc_control::W`](W) writer structure"]
24472        impl crate::Writable for RtcControlSpec {
24473            type Safety = crate::Unsafe;
24474        }
24475        #[doc = "`reset()` method sets RTC_CONTROL to value 0"]
24476        impl crate::Resettable for RtcControlSpec {}
24477    }
24478    #[doc = "RTC_EOI (rw) register accessor: RTC end-of-interrupt (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_eoi`] module"]
24479    #[doc(alias = "RTC_EOI")]
24480    pub type RtcEoi = crate::Reg<rtc_eoi::RtcEoiSpec>;
24481    #[doc = "RTC end-of-interrupt (read to clear)"]
24482    pub mod rtc_eoi {
24483        #[doc = "Register `RTC_EOI` reader"]
24484        pub type R = crate::R<RtcEoiSpec>;
24485        #[doc = "Register `RTC_EOI` writer"]
24486        pub type W = crate::W<RtcEoiSpec>;
24487        #[doc = "Field `eoi` reader - Read to clear RTC interrupt"]
24488        pub type EoiR = crate::BitReader;
24489        impl R {
24490            #[doc = "Bit 0 - Read to clear RTC interrupt"]
24491            #[inline(always)]
24492            pub fn eoi(&self) -> EoiR {
24493                EoiR::new((self.bits & 1) != 0)
24494            }
24495        }
24496        impl W {}
24497        #[doc = "RTC end-of-interrupt (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24498        pub struct RtcEoiSpec;
24499        impl crate::RegisterSpec for RtcEoiSpec {
24500            type Ux = u32;
24501        }
24502        #[doc = "`read()` method returns [`rtc_eoi::R`](R) reader structure"]
24503        impl crate::Readable for RtcEoiSpec {}
24504        #[doc = "`write(|w| ..)` method takes [`rtc_eoi::W`](W) writer structure"]
24505        impl crate::Writable for RtcEoiSpec {
24506            type Safety = crate::Unsafe;
24507        }
24508        #[doc = "`reset()` method sets RTC_EOI to value 0"]
24509        impl crate::Resettable for RtcEoiSpec {}
24510    }
24511    #[doc = "RTC_INT_STATUS (rw) register accessor: RTC interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_int_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_int_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_int_status`] module"]
24512    #[doc(alias = "RTC_INT_STATUS")]
24513    pub type RtcIntStatus = crate::Reg<rtc_int_status::RtcIntStatusSpec>;
24514    #[doc = "RTC interrupt status"]
24515    pub mod rtc_int_status {
24516        #[doc = "Register `RTC_INT_STATUS` reader"]
24517        pub type R = crate::R<RtcIntStatusSpec>;
24518        #[doc = "Register `RTC_INT_STATUS` writer"]
24519        pub type W = crate::W<RtcIntStatusSpec>;
24520        #[doc = "Field `int_status` reader - Interrupt status"]
24521        pub type IntStatusR = crate::BitReader;
24522        impl R {
24523            #[doc = "Bit 0 - Interrupt status"]
24524            #[inline(always)]
24525            pub fn int_status(&self) -> IntStatusR {
24526                IntStatusR::new((self.bits & 1) != 0)
24527            }
24528        }
24529        impl W {}
24530        #[doc = "RTC interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_int_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_int_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24531        pub struct RtcIntStatusSpec;
24532        impl crate::RegisterSpec for RtcIntStatusSpec {
24533            type Ux = u32;
24534        }
24535        #[doc = "`read()` method returns [`rtc_int_status::R`](R) reader structure"]
24536        impl crate::Readable for RtcIntStatusSpec {}
24537        #[doc = "`write(|w| ..)` method takes [`rtc_int_status::W`](W) writer structure"]
24538        impl crate::Writable for RtcIntStatusSpec {
24539            type Safety = crate::Unsafe;
24540        }
24541        #[doc = "`reset()` method sets RTC_INT_STATUS to value 0"]
24542        impl crate::Resettable for RtcIntStatusSpec {}
24543    }
24544}
24545#[doc = "eFuse controller (OTP, v151)"]
24546pub type Efuse = crate::Periph<efuse::RegisterBlock, 0x4400_8000>;
24547impl core::fmt::Debug for Efuse {
24548    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
24549        f.debug_struct("Efuse").finish()
24550    }
24551}
24552#[doc = "eFuse controller (OTP, v151)"]
24553pub mod efuse {
24554    #[repr(C)]
24555    #[doc = "Register block"]
24556    pub struct RegisterBlock {
24557        _reserved0: [u8; 0x2c],
24558        efuse_sts: EfuseSts,
24559        efuse_ctl_data: EfuseCtlData,
24560        efuse_clk_period: EfuseClkPeriod,
24561        _reserved3: [u8; 0x04],
24562        efuse_avdd_ctl: EfuseAvddCtl,
24563        _reserved4: [u8; 0x07c0],
24564        efuse_data: [EfuseData; 128],
24565    }
24566    impl RegisterBlock {
24567        #[doc = "0x2c - eFuse boot-done status register (base+0x2C). Read-only."]
24568        #[inline(always)]
24569        pub const fn efuse_sts(&self) -> &EfuseSts {
24570            &self.efuse_sts
24571        }
24572        #[doc = "0x30 - eFuse mode-select register (base+0x30). Write the 16-bit magic to arm an access: 0xA5A5 = program (write) mode, 0x5A5A = read mode."]
24573        #[inline(always)]
24574        pub const fn efuse_ctl_data(&self) -> &EfuseCtlData {
24575            &self.efuse_ctl_data
24576        }
24577        #[doc = "0x34 - eFuse clock period register (base+0x34)"]
24578        #[inline(always)]
24579        pub const fn efuse_clk_period(&self) -> &EfuseClkPeriod {
24580            &self.efuse_clk_period
24581        }
24582        #[doc = "0x3c - eFuse AVDD program-voltage switch (base+0x3C)"]
24583        #[inline(always)]
24584        pub const fn efuse_avdd_ctl(&self) -> &EfuseAvddCtl {
24585            &self.efuse_avdd_ctl
24586        }
24587        #[doc = "0x800..0xa00 - eFuse read/write data window (base+0x800), 128 words covering 256 bytes. Each 32-bit word packs two eFuse bytes: even byte address in \\[7:0\\], odd in \\[15:8\\]. Word index = byte_addr/2."]
24588        #[inline(always)]
24589        pub const fn efuse_data(&self, n: usize) -> &EfuseData {
24590            &self.efuse_data[n]
24591        }
24592        #[doc = "Iterator for array of:"]
24593        #[doc = "0x800..0xa00 - eFuse read/write data window (base+0x800), 128 words covering 256 bytes. Each 32-bit word packs two eFuse bytes: even byte address in \\[7:0\\], odd in \\[15:8\\]. Word index = byte_addr/2."]
24594        #[inline(always)]
24595        pub fn efuse_data_iter(&self) -> impl Iterator<Item = &EfuseData> {
24596            self.efuse_data.iter()
24597        }
24598    }
24599    #[doc = "EFUSE_STS (rw) register accessor: eFuse boot-done status register (base+0x2C). Read-only.\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_sts`] module"]
24600    #[doc(alias = "EFUSE_STS")]
24601    pub type EfuseSts = crate::Reg<efuse_sts::EfuseStsSpec>;
24602    #[doc = "eFuse boot-done status register (base+0x2C). Read-only."]
24603    pub mod efuse_sts {
24604        #[doc = "Register `EFUSE_STS` reader"]
24605        pub type R = crate::R<EfuseStsSpec>;
24606        #[doc = "Register `EFUSE_STS` writer"]
24607        pub type W = crate::W<EfuseStsSpec>;
24608        #[doc = "Field `man_sts` reader - Manufacturing status"]
24609        pub type ManStsR = crate::FieldReader;
24610        #[doc = "Field `boot0_done` reader - Boot0 done flag"]
24611        pub type Boot0DoneR = crate::BitReader;
24612        #[doc = "Field `boot1_done` reader - Boot1 done flag"]
24613        pub type Boot1DoneR = crate::BitReader;
24614        #[doc = "Field `boot2_done` reader - Boot2 done flag"]
24615        pub type Boot2DoneR = crate::BitReader;
24616        impl R {
24617            #[doc = "Bits 0:1 - Manufacturing status"]
24618            #[inline(always)]
24619            pub fn man_sts(&self) -> ManStsR {
24620                ManStsR::new((self.bits & 3) as u8)
24621            }
24622            #[doc = "Bit 2 - Boot0 done flag"]
24623            #[inline(always)]
24624            pub fn boot0_done(&self) -> Boot0DoneR {
24625                Boot0DoneR::new(((self.bits >> 2) & 1) != 0)
24626            }
24627            #[doc = "Bit 3 - Boot1 done flag"]
24628            #[inline(always)]
24629            pub fn boot1_done(&self) -> Boot1DoneR {
24630                Boot1DoneR::new(((self.bits >> 3) & 1) != 0)
24631            }
24632            #[doc = "Bit 4 - Boot2 done flag"]
24633            #[inline(always)]
24634            pub fn boot2_done(&self) -> Boot2DoneR {
24635                Boot2DoneR::new(((self.bits >> 4) & 1) != 0)
24636            }
24637        }
24638        impl W {}
24639        #[doc = "eFuse boot-done status register (base+0x2C). Read-only.\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24640        pub struct EfuseStsSpec;
24641        impl crate::RegisterSpec for EfuseStsSpec {
24642            type Ux = u32;
24643        }
24644        #[doc = "`read()` method returns [`efuse_sts::R`](R) reader structure"]
24645        impl crate::Readable for EfuseStsSpec {}
24646        #[doc = "`write(|w| ..)` method takes [`efuse_sts::W`](W) writer structure"]
24647        impl crate::Writable for EfuseStsSpec {
24648            type Safety = crate::Unsafe;
24649        }
24650        #[doc = "`reset()` method sets EFUSE_STS to value 0"]
24651        impl crate::Resettable for EfuseStsSpec {}
24652    }
24653    #[doc = "EFUSE_CTL_DATA (rw) register accessor: eFuse mode-select register (base+0x30). Write the 16-bit magic to arm an access: 0xA5A5 = program (write) mode, 0x5A5A = read mode.\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_ctl_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_ctl_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_ctl_data`] module"]
24654    #[doc(alias = "EFUSE_CTL_DATA")]
24655    pub type EfuseCtlData = crate::Reg<efuse_ctl_data::EfuseCtlDataSpec>;
24656    #[doc = "eFuse mode-select register (base+0x30). Write the 16-bit magic to arm an access: 0xA5A5 = program (write) mode, 0x5A5A = read mode."]
24657    pub mod efuse_ctl_data {
24658        #[doc = "Register `EFUSE_CTL_DATA` reader"]
24659        pub type R = crate::R<EfuseCtlDataSpec>;
24660        #[doc = "Register `EFUSE_CTL_DATA` writer"]
24661        pub type W = crate::W<EfuseCtlDataSpec>;
24662        #[doc = "Field `efuse_wr_rd` reader - Mode-select magic word (0xA5A5=write, 0x5A5A=read)"]
24663        pub type EfuseWrRdR = crate::FieldReader<u16>;
24664        #[doc = "Field `efuse_wr_rd` writer - Mode-select magic word (0xA5A5=write, 0x5A5A=read)"]
24665        pub type EfuseWrRdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
24666        impl R {
24667            #[doc = "Bits 0:15 - Mode-select magic word (0xA5A5=write, 0x5A5A=read)"]
24668            #[inline(always)]
24669            pub fn efuse_wr_rd(&self) -> EfuseWrRdR {
24670                EfuseWrRdR::new((self.bits & 0xffff) as u16)
24671            }
24672        }
24673        impl W {
24674            #[doc = "Bits 0:15 - Mode-select magic word (0xA5A5=write, 0x5A5A=read)"]
24675            #[inline(always)]
24676            pub fn efuse_wr_rd(&mut self) -> EfuseWrRdW<'_, EfuseCtlDataSpec> {
24677                EfuseWrRdW::new(self, 0)
24678            }
24679        }
24680        #[doc = "eFuse mode-select register (base+0x30). Write the 16-bit magic to arm an access: 0xA5A5 = program (write) mode, 0x5A5A = read mode.\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_ctl_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_ctl_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24681        pub struct EfuseCtlDataSpec;
24682        impl crate::RegisterSpec for EfuseCtlDataSpec {
24683            type Ux = u32;
24684        }
24685        #[doc = "`read()` method returns [`efuse_ctl_data::R`](R) reader structure"]
24686        impl crate::Readable for EfuseCtlDataSpec {}
24687        #[doc = "`write(|w| ..)` method takes [`efuse_ctl_data::W`](W) writer structure"]
24688        impl crate::Writable for EfuseCtlDataSpec {
24689            type Safety = crate::Unsafe;
24690        }
24691        #[doc = "`reset()` method sets EFUSE_CTL_DATA to value 0"]
24692        impl crate::Resettable for EfuseCtlDataSpec {}
24693    }
24694    #[doc = "EFUSE_CLK_PERIOD (rw) register accessor: eFuse clock period register (base+0x34)\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_clk_period::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_clk_period::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_clk_period`] module"]
24695    #[doc(alias = "EFUSE_CLK_PERIOD")]
24696    pub type EfuseClkPeriod = crate::Reg<efuse_clk_period::EfuseClkPeriodSpec>;
24697    #[doc = "eFuse clock period register (base+0x34)"]
24698    pub mod efuse_clk_period {
24699        #[doc = "Register `EFUSE_CLK_PERIOD` reader"]
24700        pub type R = crate::R<EfuseClkPeriodSpec>;
24701        #[doc = "Register `EFUSE_CLK_PERIOD` writer"]
24702        pub type W = crate::W<EfuseClkPeriodSpec>;
24703        #[doc = "Field `clk_period` reader - Clock period in cycles (e.g. 0x29 @ 24MHz, 0x19 @ 40MHz)"]
24704        pub type ClkPeriodR = crate::FieldReader;
24705        #[doc = "Field `clk_period` writer - Clock period in cycles (e.g. 0x29 @ 24MHz, 0x19 @ 40MHz)"]
24706        pub type ClkPeriodW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
24707        impl R {
24708            #[doc = "Bits 0:7 - Clock period in cycles (e.g. 0x29 @ 24MHz, 0x19 @ 40MHz)"]
24709            #[inline(always)]
24710            pub fn clk_period(&self) -> ClkPeriodR {
24711                ClkPeriodR::new((self.bits & 0xff) as u8)
24712            }
24713        }
24714        impl W {
24715            #[doc = "Bits 0:7 - Clock period in cycles (e.g. 0x29 @ 24MHz, 0x19 @ 40MHz)"]
24716            #[inline(always)]
24717            pub fn clk_period(&mut self) -> ClkPeriodW<'_, EfuseClkPeriodSpec> {
24718                ClkPeriodW::new(self, 0)
24719            }
24720        }
24721        #[doc = "eFuse clock period register (base+0x34)\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_clk_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_clk_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24722        pub struct EfuseClkPeriodSpec;
24723        impl crate::RegisterSpec for EfuseClkPeriodSpec {
24724            type Ux = u32;
24725        }
24726        #[doc = "`read()` method returns [`efuse_clk_period::R`](R) reader structure"]
24727        impl crate::Readable for EfuseClkPeriodSpec {}
24728        #[doc = "`write(|w| ..)` method takes [`efuse_clk_period::W`](W) writer structure"]
24729        impl crate::Writable for EfuseClkPeriodSpec {
24730            type Safety = crate::Unsafe;
24731        }
24732        #[doc = "`reset()` method sets EFUSE_CLK_PERIOD to value 0"]
24733        impl crate::Resettable for EfuseClkPeriodSpec {}
24734    }
24735    #[doc = "EFUSE_AVDD_CTL (rw) register accessor: eFuse AVDD program-voltage switch (base+0x3C)\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_avdd_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_avdd_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_avdd_ctl`] module"]
24736    #[doc(alias = "EFUSE_AVDD_CTL")]
24737    pub type EfuseAvddCtl = crate::Reg<efuse_avdd_ctl::EfuseAvddCtlSpec>;
24738    #[doc = "eFuse AVDD program-voltage switch (base+0x3C)"]
24739    pub mod efuse_avdd_ctl {
24740        #[doc = "Register `EFUSE_AVDD_CTL` reader"]
24741        pub type R = crate::R<EfuseAvddCtlSpec>;
24742        #[doc = "Register `EFUSE_AVDD_CTL` writer"]
24743        pub type W = crate::W<EfuseAvddCtlSpec>;
24744        #[doc = "Field `avdd_sw` reader - AVDD switch: 1=enable program voltage, 0=disable"]
24745        pub type AvddSwR = crate::BitReader;
24746        #[doc = "Field `avdd_sw` writer - AVDD switch: 1=enable program voltage, 0=disable"]
24747        pub type AvddSwW<'a, REG> = crate::BitWriter<'a, REG>;
24748        impl R {
24749            #[doc = "Bit 0 - AVDD switch: 1=enable program voltage, 0=disable"]
24750            #[inline(always)]
24751            pub fn avdd_sw(&self) -> AvddSwR {
24752                AvddSwR::new((self.bits & 1) != 0)
24753            }
24754        }
24755        impl W {
24756            #[doc = "Bit 0 - AVDD switch: 1=enable program voltage, 0=disable"]
24757            #[inline(always)]
24758            pub fn avdd_sw(&mut self) -> AvddSwW<'_, EfuseAvddCtlSpec> {
24759                AvddSwW::new(self, 0)
24760            }
24761        }
24762        #[doc = "eFuse AVDD program-voltage switch (base+0x3C)\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_avdd_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_avdd_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24763        pub struct EfuseAvddCtlSpec;
24764        impl crate::RegisterSpec for EfuseAvddCtlSpec {
24765            type Ux = u32;
24766        }
24767        #[doc = "`read()` method returns [`efuse_avdd_ctl::R`](R) reader structure"]
24768        impl crate::Readable for EfuseAvddCtlSpec {}
24769        #[doc = "`write(|w| ..)` method takes [`efuse_avdd_ctl::W`](W) writer structure"]
24770        impl crate::Writable for EfuseAvddCtlSpec {
24771            type Safety = crate::Unsafe;
24772        }
24773        #[doc = "`reset()` method sets EFUSE_AVDD_CTL to value 0"]
24774        impl crate::Resettable for EfuseAvddCtlSpec {}
24775    }
24776    #[doc = "EFUSE_DATA (rw) register accessor: eFuse read/write data window (base+0x800), 128 words covering 256 bytes. Each 32-bit word packs two eFuse bytes: even byte address in \\[7:0\\], odd in \\[15:8\\]. Word index = byte_addr/2.\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_data`] module"]
24777    #[doc(alias = "EFUSE_DATA")]
24778    pub type EfuseData = crate::Reg<efuse_data::EfuseDataSpec>;
24779    #[doc = "eFuse read/write data window (base+0x800), 128 words covering 256 bytes. Each 32-bit word packs two eFuse bytes: even byte address in \\[7:0\\], odd in \\[15:8\\]. Word index = byte_addr/2."]
24780    pub mod efuse_data {
24781        #[doc = "Register `EFUSE_DATA[%s]` reader"]
24782        pub type R = crate::R<EfuseDataSpec>;
24783        #[doc = "Register `EFUSE_DATA[%s]` writer"]
24784        pub type W = crate::W<EfuseDataSpec>;
24785        #[doc = "Field `data` reader - Two packed eFuse bytes (low byte=\\[7:0\\], high byte=\\[15:8\\])"]
24786        pub type DataR = crate::FieldReader<u16>;
24787        #[doc = "Field `data` writer - Two packed eFuse bytes (low byte=\\[7:0\\], high byte=\\[15:8\\])"]
24788        pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
24789        impl R {
24790            #[doc = "Bits 0:15 - Two packed eFuse bytes (low byte=\\[7:0\\], high byte=\\[15:8\\])"]
24791            #[inline(always)]
24792            pub fn data(&self) -> DataR {
24793                DataR::new((self.bits & 0xffff) as u16)
24794            }
24795        }
24796        impl W {
24797            #[doc = "Bits 0:15 - Two packed eFuse bytes (low byte=\\[7:0\\], high byte=\\[15:8\\])"]
24798            #[inline(always)]
24799            pub fn data(&mut self) -> DataW<'_, EfuseDataSpec> {
24800                DataW::new(self, 0)
24801            }
24802        }
24803        #[doc = "eFuse read/write data window (base+0x800), 128 words covering 256 bytes. Each 32-bit word packs two eFuse bytes: even byte address in \\[7:0\\], odd in \\[15:8\\]. Word index = byte_addr/2.\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24804        pub struct EfuseDataSpec;
24805        impl crate::RegisterSpec for EfuseDataSpec {
24806            type Ux = u32;
24807        }
24808        #[doc = "`read()` method returns [`efuse_data::R`](R) reader structure"]
24809        impl crate::Readable for EfuseDataSpec {}
24810        #[doc = "`write(|w| ..)` method takes [`efuse_data::W`](W) writer structure"]
24811        impl crate::Writable for EfuseDataSpec {
24812            type Safety = crate::Unsafe;
24813        }
24814        #[doc = "`reset()` method sets EFUSE_DATA[%s] to value 0"]
24815        impl crate::Resettable for EfuseDataSpec {}
24816    }
24817}
24818#[doc = "System Control 0 - reset status, clock control, PLL config"]
24819pub type SysCtl0 = crate::Periph<sys_ctl0::RegisterBlock, 0x4000_0000>;
24820impl core::fmt::Debug for SysCtl0 {
24821    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
24822        f.debug_struct("SysCtl0").finish()
24823    }
24824}
24825#[doc = "System Control 0 - reset status, clock control, PLL config"]
24826pub mod sys_ctl0 {
24827    #[repr(C)]
24828    #[doc = "Register block"]
24829    pub struct RegisterBlock {
24830        _reserved0: [u8; 0x08],
24831        reset_count: ResetCount,
24832        _reserved1: [u8; 0x08],
24833        hw_ctl: HwCtl,
24834        _reserved2: [u8; 0x80],
24835        reg_sys_rst_record: RegSysRstRecord,
24836        _reserved3: [u8; 0x04],
24837        sys_rst_record_0: SysRstRecord0,
24838        sys_diag_clr_1: SysDiagClr1,
24839    }
24840    impl RegisterBlock {
24841        #[doc = "0x08 - Reset count register"]
24842        #[inline(always)]
24843        pub const fn reset_count(&self) -> &ResetCount {
24844            &self.reset_count
24845        }
24846        #[doc = "0x14 - Hardware control register"]
24847        #[inline(always)]
24848        pub const fn hw_ctl(&self) -> &HwCtl {
24849            &self.hw_ctl
24850        }
24851        #[doc = "0x98 - System reset record register"]
24852        #[inline(always)]
24853        pub const fn reg_sys_rst_record(&self) -> &RegSysRstRecord {
24854            &self.reg_sys_rst_record
24855        }
24856        #[doc = "0xa0 - System reset history record 0"]
24857        #[inline(always)]
24858        pub const fn sys_rst_record_0(&self) -> &SysRstRecord0 {
24859            &self.sys_rst_record_0
24860        }
24861        #[doc = "0xa4 - System diagnostic clear 1"]
24862        #[inline(always)]
24863        pub const fn sys_diag_clr_1(&self) -> &SysDiagClr1 {
24864            &self.sys_diag_clr_1
24865        }
24866    }
24867    #[doc = "RESET_COUNT (rw) register accessor: Reset count register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_count`] module"]
24868    #[doc(alias = "RESET_COUNT")]
24869    pub type ResetCount = crate::Reg<reset_count::ResetCountSpec>;
24870    #[doc = "Reset count register"]
24871    pub mod reset_count {
24872        #[doc = "Register `RESET_COUNT` reader"]
24873        pub type R = crate::R<ResetCountSpec>;
24874        #[doc = "Register `RESET_COUNT` writer"]
24875        pub type W = crate::W<ResetCountSpec>;
24876        #[doc = "Field `reset_count` reader - Reset count value"]
24877        pub type ResetCountR = crate::FieldReader<u32>;
24878        impl R {
24879            #[doc = "Bits 0:31 - Reset count value"]
24880            #[inline(always)]
24881            pub fn reset_count(&self) -> ResetCountR {
24882                ResetCountR::new(self.bits)
24883            }
24884        }
24885        impl W {}
24886        #[doc = "Reset count register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24887        pub struct ResetCountSpec;
24888        impl crate::RegisterSpec for ResetCountSpec {
24889            type Ux = u32;
24890        }
24891        #[doc = "`read()` method returns [`reset_count::R`](R) reader structure"]
24892        impl crate::Readable for ResetCountSpec {}
24893        #[doc = "`write(|w| ..)` method takes [`reset_count::W`](W) writer structure"]
24894        impl crate::Writable for ResetCountSpec {
24895            type Safety = crate::Unsafe;
24896        }
24897        #[doc = "`reset()` method sets RESET_COUNT to value 0"]
24898        impl crate::Resettable for ResetCountSpec {}
24899    }
24900    #[doc = "HW_CTL (rw) register accessor: Hardware control register\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_ctl`] module"]
24901    #[doc(alias = "HW_CTL")]
24902    pub type HwCtl = crate::Reg<hw_ctl::HwCtlSpec>;
24903    #[doc = "Hardware control register"]
24904    pub mod hw_ctl {
24905        #[doc = "Register `HW_CTL` reader"]
24906        pub type R = crate::R<HwCtlSpec>;
24907        #[doc = "Register `HW_CTL` writer"]
24908        pub type W = crate::W<HwCtlSpec>;
24909        #[doc = "Field `refclk_freq_status` reader - REFCLK frequency status: 0=40MHz; 1=24MHz"]
24910        pub type RefclkFreqStatusR = crate::BitReader;
24911        impl R {
24912            #[doc = "Bit 0 - REFCLK frequency status: 0=40MHz; 1=24MHz"]
24913            #[inline(always)]
24914            pub fn refclk_freq_status(&self) -> RefclkFreqStatusR {
24915                RefclkFreqStatusR::new((self.bits & 1) != 0)
24916            }
24917        }
24918        impl W {}
24919        #[doc = "Hardware control register\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24920        pub struct HwCtlSpec;
24921        impl crate::RegisterSpec for HwCtlSpec {
24922            type Ux = u32;
24923        }
24924        #[doc = "`read()` method returns [`hw_ctl::R`](R) reader structure"]
24925        impl crate::Readable for HwCtlSpec {}
24926        #[doc = "`write(|w| ..)` method takes [`hw_ctl::W`](W) writer structure"]
24927        impl crate::Writable for HwCtlSpec {
24928            type Safety = crate::Unsafe;
24929        }
24930        #[doc = "`reset()` method sets HW_CTL to value 0"]
24931        impl crate::Resettable for HwCtlSpec {}
24932    }
24933    #[doc = "REG_SYS_RST_RECORD (rw) register accessor: System reset record register\n\nYou can [`read`](crate::Reg::read) this register and get [`reg_sys_rst_record::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg_sys_rst_record::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_sys_rst_record`] module"]
24934    #[doc(alias = "REG_SYS_RST_RECORD")]
24935    pub type RegSysRstRecord = crate::Reg<reg_sys_rst_record::RegSysRstRecordSpec>;
24936    #[doc = "System reset record register"]
24937    pub mod reg_sys_rst_record {
24938        #[doc = "Register `REG_SYS_RST_RECORD` reader"]
24939        pub type R = crate::R<RegSysRstRecordSpec>;
24940        #[doc = "Register `REG_SYS_RST_RECORD` writer"]
24941        pub type W = crate::W<RegSysRstRecordSpec>;
24942        #[doc = "Field `wdt_rst` reader - Watchdog reset record"]
24943        pub type WdtRstR = crate::BitReader;
24944        #[doc = "Field `wdt_rst` writer - Watchdog reset record"]
24945        pub type WdtRstW<'a, REG> = crate::BitWriter<'a, REG>;
24946        #[doc = "Field `soft_rst` reader - Software reset record"]
24947        pub type SoftRstR = crate::BitReader;
24948        #[doc = "Field `soft_rst` writer - Software reset record"]
24949        pub type SoftRstW<'a, REG> = crate::BitWriter<'a, REG>;
24950        #[doc = "Field `hard_rst` reader - Hardware reset record"]
24951        pub type HardRstR = crate::BitReader;
24952        #[doc = "Field `hard_rst` writer - Hardware reset record"]
24953        pub type HardRstW<'a, REG> = crate::BitWriter<'a, REG>;
24954        impl R {
24955            #[doc = "Bit 0 - Watchdog reset record"]
24956            #[inline(always)]
24957            pub fn wdt_rst(&self) -> WdtRstR {
24958                WdtRstR::new((self.bits & 1) != 0)
24959            }
24960            #[doc = "Bit 1 - Software reset record"]
24961            #[inline(always)]
24962            pub fn soft_rst(&self) -> SoftRstR {
24963                SoftRstR::new(((self.bits >> 1) & 1) != 0)
24964            }
24965            #[doc = "Bit 2 - Hardware reset record"]
24966            #[inline(always)]
24967            pub fn hard_rst(&self) -> HardRstR {
24968                HardRstR::new(((self.bits >> 2) & 1) != 0)
24969            }
24970        }
24971        impl W {
24972            #[doc = "Bit 0 - Watchdog reset record"]
24973            #[inline(always)]
24974            pub fn wdt_rst(&mut self) -> WdtRstW<'_, RegSysRstRecordSpec> {
24975                WdtRstW::new(self, 0)
24976            }
24977            #[doc = "Bit 1 - Software reset record"]
24978            #[inline(always)]
24979            pub fn soft_rst(&mut self) -> SoftRstW<'_, RegSysRstRecordSpec> {
24980                SoftRstW::new(self, 1)
24981            }
24982            #[doc = "Bit 2 - Hardware reset record"]
24983            #[inline(always)]
24984            pub fn hard_rst(&mut self) -> HardRstW<'_, RegSysRstRecordSpec> {
24985                HardRstW::new(self, 2)
24986            }
24987        }
24988        #[doc = "System reset record register\n\nYou can [`read`](crate::Reg::read) this register and get [`reg_sys_rst_record::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg_sys_rst_record::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24989        pub struct RegSysRstRecordSpec;
24990        impl crate::RegisterSpec for RegSysRstRecordSpec {
24991            type Ux = u32;
24992        }
24993        #[doc = "`read()` method returns [`reg_sys_rst_record::R`](R) reader structure"]
24994        impl crate::Readable for RegSysRstRecordSpec {}
24995        #[doc = "`write(|w| ..)` method takes [`reg_sys_rst_record::W`](W) writer structure"]
24996        impl crate::Writable for RegSysRstRecordSpec {
24997            type Safety = crate::Unsafe;
24998        }
24999        #[doc = "`reset()` method sets REG_SYS_RST_RECORD to value 0"]
25000        impl crate::Resettable for RegSysRstRecordSpec {}
25001    }
25002    #[doc = "SYS_RST_RECORD_0 (rw) register accessor: System reset history record 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_rst_record_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_rst_record_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_rst_record_0`] module"]
25003    #[doc(alias = "SYS_RST_RECORD_0")]
25004    pub type SysRstRecord0 = crate::Reg<sys_rst_record_0::SysRstRecord0Spec>;
25005    #[doc = "System reset history record 0"]
25006    pub mod sys_rst_record_0 {
25007        #[doc = "Register `SYS_RST_RECORD_0` reader"]
25008        pub type R = crate::R<SysRstRecord0Spec>;
25009        #[doc = "Register `SYS_RST_RECORD_0` writer"]
25010        pub type W = crate::W<SysRstRecord0Spec>;
25011        #[doc = "Field `sys_wdt_rst_his` reader - WDT reset history"]
25012        pub type SysWdtRstHisR = crate::BitReader;
25013        #[doc = "Field `sys_soft_rst_his` reader - Software reset history"]
25014        pub type SysSoftRstHisR = crate::BitReader;
25015        #[doc = "Field `por_rst_filter_his` reader - POR reset filter history"]
25016        pub type PorRstFilterHisR = crate::BitReader;
25017        impl R {
25018            #[doc = "Bit 0 - WDT reset history"]
25019            #[inline(always)]
25020            pub fn sys_wdt_rst_his(&self) -> SysWdtRstHisR {
25021                SysWdtRstHisR::new((self.bits & 1) != 0)
25022            }
25023            #[doc = "Bit 1 - Software reset history"]
25024            #[inline(always)]
25025            pub fn sys_soft_rst_his(&self) -> SysSoftRstHisR {
25026                SysSoftRstHisR::new(((self.bits >> 1) & 1) != 0)
25027            }
25028            #[doc = "Bit 3 - POR reset filter history"]
25029            #[inline(always)]
25030            pub fn por_rst_filter_his(&self) -> PorRstFilterHisR {
25031                PorRstFilterHisR::new(((self.bits >> 3) & 1) != 0)
25032            }
25033        }
25034        impl W {}
25035        #[doc = "System reset history record 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_rst_record_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_rst_record_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25036        pub struct SysRstRecord0Spec;
25037        impl crate::RegisterSpec for SysRstRecord0Spec {
25038            type Ux = u32;
25039        }
25040        #[doc = "`read()` method returns [`sys_rst_record_0::R`](R) reader structure"]
25041        impl crate::Readable for SysRstRecord0Spec {}
25042        #[doc = "`write(|w| ..)` method takes [`sys_rst_record_0::W`](W) writer structure"]
25043        impl crate::Writable for SysRstRecord0Spec {
25044            type Safety = crate::Unsafe;
25045        }
25046        #[doc = "`reset()` method sets SYS_RST_RECORD_0 to value 0"]
25047        impl crate::Resettable for SysRstRecord0Spec {}
25048    }
25049    #[doc = "SYS_DIAG_CLR_1 (rw) register accessor: System diagnostic clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_diag_clr_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_diag_clr_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_diag_clr_1`] module"]
25050    #[doc(alias = "SYS_DIAG_CLR_1")]
25051    pub type SysDiagClr1 = crate::Reg<sys_diag_clr_1::SysDiagClr1Spec>;
25052    #[doc = "System diagnostic clear 1"]
25053    pub mod sys_diag_clr_1 {
25054        #[doc = "Register `SYS_DIAG_CLR_1` reader"]
25055        pub type R = crate::R<SysDiagClr1Spec>;
25056        #[doc = "Register `SYS_DIAG_CLR_1` writer"]
25057        pub type W = crate::W<SysDiagClr1Spec>;
25058        #[doc = "Field `sys_diag_clr` writer - Write to clear reset history bits"]
25059        pub type SysDiagClrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
25060        impl W {
25061            #[doc = "Bits 0:31 - Write to clear reset history bits"]
25062            #[inline(always)]
25063            pub fn sys_diag_clr(&mut self) -> SysDiagClrW<'_, SysDiagClr1Spec> {
25064                SysDiagClrW::new(self, 0)
25065            }
25066        }
25067        #[doc = "System diagnostic clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_diag_clr_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_diag_clr_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25068        pub struct SysDiagClr1Spec;
25069        impl crate::RegisterSpec for SysDiagClr1Spec {
25070            type Ux = u32;
25071        }
25072        #[doc = "`read()` method returns [`sys_diag_clr_1::R`](R) reader structure"]
25073        impl crate::Readable for SysDiagClr1Spec {}
25074        #[doc = "`write(|w| ..)` method takes [`sys_diag_clr_1::W`](W) writer structure"]
25075        impl crate::Writable for SysDiagClr1Spec {
25076            type Safety = crate::Unsafe;
25077        }
25078        #[doc = "`reset()` method sets SYS_DIAG_CLR_1 to value 0"]
25079        impl crate::Resettable for SysDiagClr1Spec {}
25080    }
25081}
25082#[doc = "Main core global control - BCPU/MCPU reset status, chip reset, AON CRG"]
25083pub type GlbCtlM = crate::Periph<glb_ctl_m::RegisterBlock, 0x4000_2000>;
25084impl core::fmt::Debug for GlbCtlM {
25085    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
25086        f.debug_struct("GlbCtlM").finish()
25087    }
25088}
25089#[doc = "Main core global control - BCPU/MCPU reset status, chip reset, AON CRG"]
25090pub mod glb_ctl_m {
25091    #[repr(C)]
25092    #[doc = "Register block"]
25093    pub struct RegisterBlock {
25094        _reserved0: [u8; 0x30],
25095        bcpu_reset_sts: BcpuResetSts,
25096        mcpu_reset_sts: McpuResetSts,
25097        _reserved2: [u8; 0x04],
25098        reset_sts_clear: ResetStsClear,
25099        _reserved3: [u8; 0xc0],
25100        aon_crg_cken_ctl: AonCrgCkenCtl,
25101        _reserved4: [u8; 0x0c],
25102        _reserved_4_chip_reset: [u8; 0x04],
25103    }
25104    impl RegisterBlock {
25105        #[doc = "0x30 - BCPU reset status register"]
25106        #[inline(always)]
25107        pub const fn bcpu_reset_sts(&self) -> &BcpuResetSts {
25108            &self.bcpu_reset_sts
25109        }
25110        #[doc = "0x34 - MCPU reset status register"]
25111        #[inline(always)]
25112        pub const fn mcpu_reset_sts(&self) -> &McpuResetSts {
25113            &self.mcpu_reset_sts
25114        }
25115        #[doc = "0x3c - Reset status clear register"]
25116        #[inline(always)]
25117        pub const fn reset_sts_clear(&self) -> &ResetStsClear {
25118            &self.reset_sts_clear
25119        }
25120        #[doc = "0x100 - AON CRG clock enable control"]
25121        #[inline(always)]
25122        pub const fn aon_crg_cken_ctl(&self) -> &AonCrgCkenCtl {
25123            &self.aon_crg_cken_ctl
25124        }
25125        #[doc = "0x110 - AON soft reset control"]
25126        #[inline(always)]
25127        pub const fn aon_soft_rst_ctl(&self) -> &AonSoftRstCtl {
25128            unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(272).cast() }
25129        }
25130        #[doc = "0x110 - Chip reset control register"]
25131        #[inline(always)]
25132        pub const fn chip_reset(&self) -> &ChipReset {
25133            unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(272).cast() }
25134        }
25135    }
25136    #[doc = "BCPU_RESET_STS (rw) register accessor: BCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`bcpu_reset_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcpu_reset_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bcpu_reset_sts`] module"]
25137    #[doc(alias = "BCPU_RESET_STS")]
25138    pub type BcpuResetSts = crate::Reg<bcpu_reset_sts::BcpuResetStsSpec>;
25139    #[doc = "BCPU reset status register"]
25140    pub mod bcpu_reset_sts {
25141        #[doc = "Register `BCPU_RESET_STS` reader"]
25142        pub type R = crate::R<BcpuResetStsSpec>;
25143        #[doc = "Register `BCPU_RESET_STS` writer"]
25144        pub type W = crate::W<BcpuResetStsSpec>;
25145        #[doc = "Field `bcpu_reset_sts` reader - BCPU reset status"]
25146        pub type BcpuResetStsR = crate::FieldReader<u32>;
25147        impl R {
25148            #[doc = "Bits 0:31 - BCPU reset status"]
25149            #[inline(always)]
25150            pub fn bcpu_reset_sts(&self) -> BcpuResetStsR {
25151                BcpuResetStsR::new(self.bits)
25152            }
25153        }
25154        impl W {}
25155        #[doc = "BCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`bcpu_reset_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcpu_reset_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25156        pub struct BcpuResetStsSpec;
25157        impl crate::RegisterSpec for BcpuResetStsSpec {
25158            type Ux = u32;
25159        }
25160        #[doc = "`read()` method returns [`bcpu_reset_sts::R`](R) reader structure"]
25161        impl crate::Readable for BcpuResetStsSpec {}
25162        #[doc = "`write(|w| ..)` method takes [`bcpu_reset_sts::W`](W) writer structure"]
25163        impl crate::Writable for BcpuResetStsSpec {
25164            type Safety = crate::Unsafe;
25165        }
25166        #[doc = "`reset()` method sets BCPU_RESET_STS to value 0"]
25167        impl crate::Resettable for BcpuResetStsSpec {}
25168    }
25169    #[doc = "MCPU_RESET_STS (rw) register accessor: MCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mcpu_reset_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcpu_reset_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcpu_reset_sts`] module"]
25170    #[doc(alias = "MCPU_RESET_STS")]
25171    pub type McpuResetSts = crate::Reg<mcpu_reset_sts::McpuResetStsSpec>;
25172    #[doc = "MCPU reset status register"]
25173    pub mod mcpu_reset_sts {
25174        #[doc = "Register `MCPU_RESET_STS` reader"]
25175        pub type R = crate::R<McpuResetStsSpec>;
25176        #[doc = "Register `MCPU_RESET_STS` writer"]
25177        pub type W = crate::W<McpuResetStsSpec>;
25178        #[doc = "Field `mcpu_reset_sts` reader - MCPU reset status"]
25179        pub type McpuResetStsR = crate::FieldReader<u32>;
25180        impl R {
25181            #[doc = "Bits 0:31 - MCPU reset status"]
25182            #[inline(always)]
25183            pub fn mcpu_reset_sts(&self) -> McpuResetStsR {
25184                McpuResetStsR::new(self.bits)
25185            }
25186        }
25187        impl W {}
25188        #[doc = "MCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mcpu_reset_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcpu_reset_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25189        pub struct McpuResetStsSpec;
25190        impl crate::RegisterSpec for McpuResetStsSpec {
25191            type Ux = u32;
25192        }
25193        #[doc = "`read()` method returns [`mcpu_reset_sts::R`](R) reader structure"]
25194        impl crate::Readable for McpuResetStsSpec {}
25195        #[doc = "`write(|w| ..)` method takes [`mcpu_reset_sts::W`](W) writer structure"]
25196        impl crate::Writable for McpuResetStsSpec {
25197            type Safety = crate::Unsafe;
25198        }
25199        #[doc = "`reset()` method sets MCPU_RESET_STS to value 0"]
25200        impl crate::Resettable for McpuResetStsSpec {}
25201    }
25202    #[doc = "RESET_STS_CLEAR (rw) register accessor: Reset status clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_sts_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_sts_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_sts_clear`] module"]
25203    #[doc(alias = "RESET_STS_CLEAR")]
25204    pub type ResetStsClear = crate::Reg<reset_sts_clear::ResetStsClearSpec>;
25205    #[doc = "Reset status clear register"]
25206    pub mod reset_sts_clear {
25207        #[doc = "Register `RESET_STS_CLEAR` reader"]
25208        pub type R = crate::R<ResetStsClearSpec>;
25209        #[doc = "Register `RESET_STS_CLEAR` writer"]
25210        pub type W = crate::W<ResetStsClearSpec>;
25211        #[doc = "Field `rst_sts_clear` writer - Write 0xFF to clear all reset status bits"]
25212        pub type RstStsClearW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
25213        impl W {
25214            #[doc = "Bits 0:31 - Write 0xFF to clear all reset status bits"]
25215            #[inline(always)]
25216            pub fn rst_sts_clear(&mut self) -> RstStsClearW<'_, ResetStsClearSpec> {
25217                RstStsClearW::new(self, 0)
25218            }
25219        }
25220        #[doc = "Reset status clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_sts_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_sts_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25221        pub struct ResetStsClearSpec;
25222        impl crate::RegisterSpec for ResetStsClearSpec {
25223            type Ux = u32;
25224        }
25225        #[doc = "`read()` method returns [`reset_sts_clear::R`](R) reader structure"]
25226        impl crate::Readable for ResetStsClearSpec {}
25227        #[doc = "`write(|w| ..)` method takes [`reset_sts_clear::W`](W) writer structure"]
25228        impl crate::Writable for ResetStsClearSpec {
25229            type Safety = crate::Unsafe;
25230        }
25231        #[doc = "`reset()` method sets RESET_STS_CLEAR to value 0"]
25232        impl crate::Resettable for ResetStsClearSpec {}
25233    }
25234    #[doc = "AON_CRG_CKEN_CTL (rw) register accessor: AON CRG clock enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_crg_cken_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_crg_cken_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_crg_cken_ctl`] module"]
25235    #[doc(alias = "AON_CRG_CKEN_CTL")]
25236    pub type AonCrgCkenCtl = crate::Reg<aon_crg_cken_ctl::AonCrgCkenCtlSpec>;
25237    #[doc = "AON CRG clock enable control"]
25238    pub mod aon_crg_cken_ctl {
25239        #[doc = "Register `AON_CRG_CKEN_CTL` reader"]
25240        pub type R = crate::R<AonCrgCkenCtlSpec>;
25241        #[doc = "Register `AON_CRG_CKEN_CTL` writer"]
25242        pub type W = crate::W<AonCrgCkenCtlSpec>;
25243        #[doc = "Field `wdt_gate` reader - WDT clock gate control at bit\\[4\\]"]
25244        pub type WdtGateR = crate::BitReader;
25245        #[doc = "Field `wdt_gate` writer - WDT clock gate control at bit\\[4\\]"]
25246        pub type WdtGateW<'a, REG> = crate::BitWriter<'a, REG>;
25247        impl R {
25248            #[doc = "Bit 4 - WDT clock gate control at bit\\[4\\]"]
25249            #[inline(always)]
25250            pub fn wdt_gate(&self) -> WdtGateR {
25251                WdtGateR::new(((self.bits >> 4) & 1) != 0)
25252            }
25253        }
25254        impl W {
25255            #[doc = "Bit 4 - WDT clock gate control at bit\\[4\\]"]
25256            #[inline(always)]
25257            pub fn wdt_gate(&mut self) -> WdtGateW<'_, AonCrgCkenCtlSpec> {
25258                WdtGateW::new(self, 4)
25259            }
25260        }
25261        #[doc = "AON CRG clock enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_crg_cken_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_crg_cken_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25262        pub struct AonCrgCkenCtlSpec;
25263        impl crate::RegisterSpec for AonCrgCkenCtlSpec {
25264            type Ux = u32;
25265        }
25266        #[doc = "`read()` method returns [`aon_crg_cken_ctl::R`](R) reader structure"]
25267        impl crate::Readable for AonCrgCkenCtlSpec {}
25268        #[doc = "`write(|w| ..)` method takes [`aon_crg_cken_ctl::W`](W) writer structure"]
25269        impl crate::Writable for AonCrgCkenCtlSpec {
25270            type Safety = crate::Unsafe;
25271        }
25272        #[doc = "`reset()` method sets AON_CRG_CKEN_CTL to value 0"]
25273        impl crate::Resettable for AonCrgCkenCtlSpec {}
25274    }
25275    #[doc = "CHIP_RESET (rw) register accessor: Chip reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`chip_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chip_reset`] module"]
25276    #[doc(alias = "CHIP_RESET")]
25277    pub type ChipReset = crate::Reg<chip_reset::ChipResetSpec>;
25278    #[doc = "Chip reset control register"]
25279    pub mod chip_reset {
25280        #[doc = "Register `CHIP_RESET` reader"]
25281        pub type R = crate::R<ChipResetSpec>;
25282        #[doc = "Register `CHIP_RESET` writer"]
25283        pub type W = crate::W<ChipResetSpec>;
25284        #[doc = "Field `chip_reset_en` reader - Chip reset enable: 1=assert chip reset"]
25285        pub type ChipResetEnR = crate::BitReader;
25286        #[doc = "Field `chip_reset_en` writer - Chip reset enable: 1=assert chip reset"]
25287        pub type ChipResetEnW<'a, REG> = crate::BitWriter<'a, REG>;
25288        impl R {
25289            #[doc = "Bit 2 - Chip reset enable: 1=assert chip reset"]
25290            #[inline(always)]
25291            pub fn chip_reset_en(&self) -> ChipResetEnR {
25292                ChipResetEnR::new(((self.bits >> 2) & 1) != 0)
25293            }
25294        }
25295        impl W {
25296            #[doc = "Bit 2 - Chip reset enable: 1=assert chip reset"]
25297            #[inline(always)]
25298            pub fn chip_reset_en(&mut self) -> ChipResetEnW<'_, ChipResetSpec> {
25299                ChipResetEnW::new(self, 2)
25300            }
25301        }
25302        #[doc = "Chip reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`chip_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25303        pub struct ChipResetSpec;
25304        impl crate::RegisterSpec for ChipResetSpec {
25305            type Ux = u32;
25306        }
25307        #[doc = "`read()` method returns [`chip_reset::R`](R) reader structure"]
25308        impl crate::Readable for ChipResetSpec {}
25309        #[doc = "`write(|w| ..)` method takes [`chip_reset::W`](W) writer structure"]
25310        impl crate::Writable for ChipResetSpec {
25311            type Safety = crate::Unsafe;
25312        }
25313        #[doc = "`reset()` method sets CHIP_RESET to value 0"]
25314        impl crate::Resettable for ChipResetSpec {}
25315    }
25316    #[doc = "AON_SOFT_RST_CTL (rw) register accessor: AON soft reset control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_soft_rst_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_soft_rst_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_soft_rst_ctl`] module"]
25317    #[doc(alias = "AON_SOFT_RST_CTL")]
25318    pub type AonSoftRstCtl = crate::Reg<aon_soft_rst_ctl::AonSoftRstCtlSpec>;
25319    #[doc = "AON soft reset control"]
25320    pub mod aon_soft_rst_ctl {
25321        #[doc = "Register `AON_SOFT_RST_CTL` reader"]
25322        pub type R = crate::R<AonSoftRstCtlSpec>;
25323        #[doc = "Register `AON_SOFT_RST_CTL` writer"]
25324        pub type W = crate::W<AonSoftRstCtlSpec>;
25325        #[doc = "Field `wdt_soft_rst` reader - WDT soft reset at bit\\[1\\]"]
25326        pub type WdtSoftRstR = crate::BitReader;
25327        #[doc = "Field `wdt_soft_rst` writer - WDT soft reset at bit\\[1\\]"]
25328        pub type WdtSoftRstW<'a, REG> = crate::BitWriter<'a, REG>;
25329        impl R {
25330            #[doc = "Bit 1 - WDT soft reset at bit\\[1\\]"]
25331            #[inline(always)]
25332            pub fn wdt_soft_rst(&self) -> WdtSoftRstR {
25333                WdtSoftRstR::new(((self.bits >> 1) & 1) != 0)
25334            }
25335        }
25336        impl W {
25337            #[doc = "Bit 1 - WDT soft reset at bit\\[1\\]"]
25338            #[inline(always)]
25339            pub fn wdt_soft_rst(&mut self) -> WdtSoftRstW<'_, AonSoftRstCtlSpec> {
25340                WdtSoftRstW::new(self, 1)
25341            }
25342        }
25343        #[doc = "AON soft reset control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_soft_rst_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_soft_rst_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25344        pub struct AonSoftRstCtlSpec;
25345        impl crate::RegisterSpec for AonSoftRstCtlSpec {
25346            type Ux = u32;
25347        }
25348        #[doc = "`read()` method returns [`aon_soft_rst_ctl::R`](R) reader structure"]
25349        impl crate::Readable for AonSoftRstCtlSpec {}
25350        #[doc = "`write(|w| ..)` method takes [`aon_soft_rst_ctl::W`](W) writer structure"]
25351        impl crate::Writable for AonSoftRstCtlSpec {
25352            type Safety = crate::Unsafe;
25353        }
25354        #[doc = "`reset()` method sets AON_SOFT_RST_CTL to value 0"]
25355        impl crate::Resettable for AonSoftRstCtlSpec {}
25356    }
25357}
25358#[doc = "Security accelerator - AES/SM4/LEA/TDES symmetric crypto, HASH/HMAC"]
25359pub type Spacc = crate::Periph<spacc::RegisterBlock, 0x4410_0000>;
25360impl core::fmt::Debug for Spacc {
25361    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
25362        f.debug_struct("Spacc").finish()
25363    }
25364}
25365#[doc = "Security accelerator - AES/SM4/LEA/TDES symmetric crypto, HASH/HMAC"]
25366pub mod spacc {
25367    #[repr(C)]
25368    #[doc = "Register block"]
25369    pub struct RegisterBlock {
25370        _reserved0: [u8; 0x04],
25371        spacc_ie: SpaccIe,
25372        spacc_int_raw_sym_clr_finish: SpaccIntRawSymClrFinish,
25373        _reserved2: [u8; 0x14],
25374        spacc_sym_chn_lock: SpaccSymChnLock,
25375        _reserved3: [u8; 0x1c],
25376        spacc_hash_chn_lock: SpaccHashChnLock,
25377        _reserved4: [u8; 0x1c],
25378        spacc_sym_chn_clear_req: SpaccSymChnClearReq,
25379        _reserved5: [u8; 0x04],
25380        spacc_hash_chn_clear_req: SpaccHashChnClearReq,
25381        _reserved6: [u8; 0x0194],
25382        spacc_bus_err: SpaccBusErr,
25383        _reserved7: [u8; 0x3dfc],
25384        in_sym_chn0_ctrl: InSymChn0Ctrl,
25385        in_sym_chn0_special_ctrl: InSymChn0SpecialCtrl,
25386        _reserved9: [u8; 0x08],
25387        in_sym_chn0_key_ctrl: InSymChn0KeyCtrl,
25388        _reserved10: [u8; 0x1c],
25389        in_sym_chn0_iv_data_ctrl: InSymChn0IvDataCtrl,
25390        _reserved11: [u8; 0x0c],
25391        in_sym_chn0_iv0: InSymChn0Iv0,
25392        in_sym_chn0_iv1: InSymChn0Iv1,
25393        in_sym_chn0_iv2: InSymChn0Iv2,
25394        in_sym_chn0_iv3: InSymChn0Iv3,
25395        in_sym_chn0_data0: InSymChn0Data0,
25396        _reserved16: [u8; 0x45bc],
25397        sym_chann_raw_int: SymChannRawInt,
25398    }
25399    impl RegisterBlock {
25400        #[doc = "0x04 - SPACC interrupt enable"]
25401        #[inline(always)]
25402        pub const fn spacc_ie(&self) -> &SpaccIe {
25403            &self.spacc_ie
25404        }
25405        #[doc = "0x08 - Sym clear finish raw interrupt"]
25406        #[inline(always)]
25407        pub const fn spacc_int_raw_sym_clr_finish(&self) -> &SpaccIntRawSymClrFinish {
25408            &self.spacc_int_raw_sym_clr_finish
25409        }
25410        #[doc = "0x20 - Sym channel lock register"]
25411        #[inline(always)]
25412        pub const fn spacc_sym_chn_lock(&self) -> &SpaccSymChnLock {
25413            &self.spacc_sym_chn_lock
25414        }
25415        #[doc = "0x40 - Hash channel lock register"]
25416        #[inline(always)]
25417        pub const fn spacc_hash_chn_lock(&self) -> &SpaccHashChnLock {
25418            &self.spacc_hash_chn_lock
25419        }
25420        #[doc = "0x60 - Sym channel clear request"]
25421        #[inline(always)]
25422        pub const fn spacc_sym_chn_clear_req(&self) -> &SpaccSymChnClearReq {
25423            &self.spacc_sym_chn_clear_req
25424        }
25425        #[doc = "0x68 - Hash channel clear request"]
25426        #[inline(always)]
25427        pub const fn spacc_hash_chn_clear_req(&self) -> &SpaccHashChnClearReq {
25428            &self.spacc_hash_chn_clear_req
25429        }
25430        #[doc = "0x200 - Bus error register"]
25431        #[inline(always)]
25432        pub const fn spacc_bus_err(&self) -> &SpaccBusErr {
25433            &self.spacc_bus_err
25434        }
25435        #[doc = "0x4000 - Sym channel 0 control register (no-DMA mode)"]
25436        #[inline(always)]
25437        pub const fn in_sym_chn0_ctrl(&self) -> &InSymChn0Ctrl {
25438            &self.in_sym_chn0_ctrl
25439        }
25440        #[doc = "0x4004 - Sym channel 0 special control"]
25441        #[inline(always)]
25442        pub const fn in_sym_chn0_special_ctrl(&self) -> &InSymChn0SpecialCtrl {
25443            &self.in_sym_chn0_special_ctrl
25444        }
25445        #[doc = "0x4010 - Sym channel 0 key control (no-DMA mode)"]
25446        #[inline(always)]
25447        pub const fn in_sym_chn0_key_ctrl(&self) -> &InSymChn0KeyCtrl {
25448            &self.in_sym_chn0_key_ctrl
25449        }
25450        #[doc = "0x4030 - Sym channel 0 IV/data control (register mode)"]
25451        #[inline(always)]
25452        pub const fn in_sym_chn0_iv_data_ctrl(&self) -> &InSymChn0IvDataCtrl {
25453            &self.in_sym_chn0_iv_data_ctrl
25454        }
25455        #[doc = "0x4040 - Sym channel 0 IV word 0 (register mode)"]
25456        #[inline(always)]
25457        pub const fn in_sym_chn0_iv0(&self) -> &InSymChn0Iv0 {
25458            &self.in_sym_chn0_iv0
25459        }
25460        #[doc = "0x4044 - Sym channel 0 IV word 1"]
25461        #[inline(always)]
25462        pub const fn in_sym_chn0_iv1(&self) -> &InSymChn0Iv1 {
25463            &self.in_sym_chn0_iv1
25464        }
25465        #[doc = "0x4048 - Sym channel 0 IV word 2"]
25466        #[inline(always)]
25467        pub const fn in_sym_chn0_iv2(&self) -> &InSymChn0Iv2 {
25468            &self.in_sym_chn0_iv2
25469        }
25470        #[doc = "0x404c - Sym channel 0 IV word 3"]
25471        #[inline(always)]
25472        pub const fn in_sym_chn0_iv3(&self) -> &InSymChn0Iv3 {
25473            &self.in_sym_chn0_iv3
25474        }
25475        #[doc = "0x4050 - Sym channel 0 data word 0 (register mode)"]
25476        #[inline(always)]
25477        pub const fn in_sym_chn0_data0(&self) -> &InSymChn0Data0 {
25478            &self.in_sym_chn0_data0
25479        }
25480        #[doc = "0x8610 - Sym channel raw interrupt status"]
25481        #[inline(always)]
25482        pub const fn sym_chann_raw_int(&self) -> &SymChannRawInt {
25483            &self.sym_chann_raw_int
25484        }
25485    }
25486    #[doc = "SPACC_IE (rw) register accessor: SPACC interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_ie`] module"]
25487    #[doc(alias = "SPACC_IE")]
25488    pub type SpaccIe = crate::Reg<spacc_ie::SpaccIeSpec>;
25489    #[doc = "SPACC interrupt enable"]
25490    pub mod spacc_ie {
25491        #[doc = "Register `SPACC_IE` reader"]
25492        pub type R = crate::R<SpaccIeSpec>;
25493        #[doc = "Register `SPACC_IE` writer"]
25494        pub type W = crate::W<SpaccIeSpec>;
25495        #[doc = "Field `spacc_ie_ree` reader - REE interrupt enable"]
25496        pub type SpaccIeReeR = crate::BitReader;
25497        #[doc = "Field `spacc_ie_ree` writer - REE interrupt enable"]
25498        pub type SpaccIeReeW<'a, REG> = crate::BitWriter<'a, REG>;
25499        #[doc = "Field `spacc_ie_tee` reader - TEE interrupt enable"]
25500        pub type SpaccIeTeeR = crate::BitReader;
25501        #[doc = "Field `spacc_ie_tee` writer - TEE interrupt enable"]
25502        pub type SpaccIeTeeW<'a, REG> = crate::BitWriter<'a, REG>;
25503        #[doc = "Field `spacc_ie_hpp` reader - HPP interrupt enable"]
25504        pub type SpaccIeHppR = crate::BitReader;
25505        #[doc = "Field `spacc_ie_hpp` writer - HPP interrupt enable"]
25506        pub type SpaccIeHppW<'a, REG> = crate::BitWriter<'a, REG>;
25507        impl R {
25508            #[doc = "Bit 0 - REE interrupt enable"]
25509            #[inline(always)]
25510            pub fn spacc_ie_ree(&self) -> SpaccIeReeR {
25511                SpaccIeReeR::new((self.bits & 1) != 0)
25512            }
25513            #[doc = "Bit 4 - TEE interrupt enable"]
25514            #[inline(always)]
25515            pub fn spacc_ie_tee(&self) -> SpaccIeTeeR {
25516                SpaccIeTeeR::new(((self.bits >> 4) & 1) != 0)
25517            }
25518            #[doc = "Bit 8 - HPP interrupt enable"]
25519            #[inline(always)]
25520            pub fn spacc_ie_hpp(&self) -> SpaccIeHppR {
25521                SpaccIeHppR::new(((self.bits >> 8) & 1) != 0)
25522            }
25523        }
25524        impl W {
25525            #[doc = "Bit 0 - REE interrupt enable"]
25526            #[inline(always)]
25527            pub fn spacc_ie_ree(&mut self) -> SpaccIeReeW<'_, SpaccIeSpec> {
25528                SpaccIeReeW::new(self, 0)
25529            }
25530            #[doc = "Bit 4 - TEE interrupt enable"]
25531            #[inline(always)]
25532            pub fn spacc_ie_tee(&mut self) -> SpaccIeTeeW<'_, SpaccIeSpec> {
25533                SpaccIeTeeW::new(self, 4)
25534            }
25535            #[doc = "Bit 8 - HPP interrupt enable"]
25536            #[inline(always)]
25537            pub fn spacc_ie_hpp(&mut self) -> SpaccIeHppW<'_, SpaccIeSpec> {
25538                SpaccIeHppW::new(self, 8)
25539            }
25540        }
25541        #[doc = "SPACC interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25542        pub struct SpaccIeSpec;
25543        impl crate::RegisterSpec for SpaccIeSpec {
25544            type Ux = u32;
25545        }
25546        #[doc = "`read()` method returns [`spacc_ie::R`](R) reader structure"]
25547        impl crate::Readable for SpaccIeSpec {}
25548        #[doc = "`write(|w| ..)` method takes [`spacc_ie::W`](W) writer structure"]
25549        impl crate::Writable for SpaccIeSpec {
25550            type Safety = crate::Unsafe;
25551        }
25552        #[doc = "`reset()` method sets SPACC_IE to value 0"]
25553        impl crate::Resettable for SpaccIeSpec {}
25554    }
25555    #[doc = "SPACC_INT_RAW_SYM_CLR_FINISH (rw) register accessor: Sym clear finish raw interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_int_raw_sym_clr_finish::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_int_raw_sym_clr_finish::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_int_raw_sym_clr_finish`] module"]
25556    #[doc(alias = "SPACC_INT_RAW_SYM_CLR_FINISH")]
25557    pub type SpaccIntRawSymClrFinish =
25558        crate::Reg<spacc_int_raw_sym_clr_finish::SpaccIntRawSymClrFinishSpec>;
25559    #[doc = "Sym clear finish raw interrupt"]
25560    pub mod spacc_int_raw_sym_clr_finish {
25561        #[doc = "Register `SPACC_INT_RAW_SYM_CLR_FINISH` reader"]
25562        pub type R = crate::R<SpaccIntRawSymClrFinishSpec>;
25563        #[doc = "Register `SPACC_INT_RAW_SYM_CLR_FINISH` writer"]
25564        pub type W = crate::W<SpaccIntRawSymClrFinishSpec>;
25565        #[doc = "Field `raw_sym_clr_finish_int` reader - Raw interrupt for sym clear finish"]
25566        pub type RawSymClrFinishIntR = crate::FieldReader<u16>;
25567        impl R {
25568            #[doc = "Bits 0:15 - Raw interrupt for sym clear finish"]
25569            #[inline(always)]
25570            pub fn raw_sym_clr_finish_int(&self) -> RawSymClrFinishIntR {
25571                RawSymClrFinishIntR::new((self.bits & 0xffff) as u16)
25572            }
25573        }
25574        impl W {}
25575        #[doc = "Sym clear finish raw interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_int_raw_sym_clr_finish::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_int_raw_sym_clr_finish::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25576        pub struct SpaccIntRawSymClrFinishSpec;
25577        impl crate::RegisterSpec for SpaccIntRawSymClrFinishSpec {
25578            type Ux = u32;
25579        }
25580        #[doc = "`read()` method returns [`spacc_int_raw_sym_clr_finish::R`](R) reader structure"]
25581        impl crate::Readable for SpaccIntRawSymClrFinishSpec {}
25582        #[doc = "`write(|w| ..)` method takes [`spacc_int_raw_sym_clr_finish::W`](W) writer structure"]
25583        impl crate::Writable for SpaccIntRawSymClrFinishSpec {
25584            type Safety = crate::Unsafe;
25585        }
25586        #[doc = "`reset()` method sets SPACC_INT_RAW_SYM_CLR_FINISH to value 0"]
25587        impl crate::Resettable for SpaccIntRawSymClrFinishSpec {}
25588    }
25589    #[doc = "SPACC_SYM_CHN_LOCK (rw) register accessor: Sym channel lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_sym_chn_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_sym_chn_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_sym_chn_lock`] module"]
25590    #[doc(alias = "SPACC_SYM_CHN_LOCK")]
25591    pub type SpaccSymChnLock = crate::Reg<spacc_sym_chn_lock::SpaccSymChnLockSpec>;
25592    #[doc = "Sym channel lock register"]
25593    pub mod spacc_sym_chn_lock {
25594        #[doc = "Register `SPACC_SYM_CHN_LOCK` reader"]
25595        pub type R = crate::R<SpaccSymChnLockSpec>;
25596        #[doc = "Register `SPACC_SYM_CHN_LOCK` writer"]
25597        pub type W = crate::W<SpaccSymChnLockSpec>;
25598        #[doc = "Field `sym_chn_lock` reader - Symmetric channel lock status"]
25599        pub type SymChnLockR = crate::FieldReader<u32>;
25600        #[doc = "Field `sym_chn_lock` writer - Symmetric channel lock status"]
25601        pub type SymChnLockW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
25602        impl R {
25603            #[doc = "Bits 0:31 - Symmetric channel lock status"]
25604            #[inline(always)]
25605            pub fn sym_chn_lock(&self) -> SymChnLockR {
25606                SymChnLockR::new(self.bits)
25607            }
25608        }
25609        impl W {
25610            #[doc = "Bits 0:31 - Symmetric channel lock status"]
25611            #[inline(always)]
25612            pub fn sym_chn_lock(&mut self) -> SymChnLockW<'_, SpaccSymChnLockSpec> {
25613                SymChnLockW::new(self, 0)
25614            }
25615        }
25616        #[doc = "Sym channel lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_sym_chn_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_sym_chn_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25617        pub struct SpaccSymChnLockSpec;
25618        impl crate::RegisterSpec for SpaccSymChnLockSpec {
25619            type Ux = u32;
25620        }
25621        #[doc = "`read()` method returns [`spacc_sym_chn_lock::R`](R) reader structure"]
25622        impl crate::Readable for SpaccSymChnLockSpec {}
25623        #[doc = "`write(|w| ..)` method takes [`spacc_sym_chn_lock::W`](W) writer structure"]
25624        impl crate::Writable for SpaccSymChnLockSpec {
25625            type Safety = crate::Unsafe;
25626        }
25627        #[doc = "`reset()` method sets SPACC_SYM_CHN_LOCK to value 0"]
25628        impl crate::Resettable for SpaccSymChnLockSpec {}
25629    }
25630    #[doc = "SPACC_HASH_CHN_LOCK (rw) register accessor: Hash channel lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_hash_chn_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_hash_chn_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_hash_chn_lock`] module"]
25631    #[doc(alias = "SPACC_HASH_CHN_LOCK")]
25632    pub type SpaccHashChnLock = crate::Reg<spacc_hash_chn_lock::SpaccHashChnLockSpec>;
25633    #[doc = "Hash channel lock register"]
25634    pub mod spacc_hash_chn_lock {
25635        #[doc = "Register `SPACC_HASH_CHN_LOCK` reader"]
25636        pub type R = crate::R<SpaccHashChnLockSpec>;
25637        #[doc = "Register `SPACC_HASH_CHN_LOCK` writer"]
25638        pub type W = crate::W<SpaccHashChnLockSpec>;
25639        #[doc = "Field `hash_chn_lock` reader - Hash channel lock status"]
25640        pub type HashChnLockR = crate::FieldReader<u32>;
25641        #[doc = "Field `hash_chn_lock` writer - Hash channel lock status"]
25642        pub type HashChnLockW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
25643        impl R {
25644            #[doc = "Bits 0:31 - Hash channel lock status"]
25645            #[inline(always)]
25646            pub fn hash_chn_lock(&self) -> HashChnLockR {
25647                HashChnLockR::new(self.bits)
25648            }
25649        }
25650        impl W {
25651            #[doc = "Bits 0:31 - Hash channel lock status"]
25652            #[inline(always)]
25653            pub fn hash_chn_lock(&mut self) -> HashChnLockW<'_, SpaccHashChnLockSpec> {
25654                HashChnLockW::new(self, 0)
25655            }
25656        }
25657        #[doc = "Hash channel lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_hash_chn_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_hash_chn_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25658        pub struct SpaccHashChnLockSpec;
25659        impl crate::RegisterSpec for SpaccHashChnLockSpec {
25660            type Ux = u32;
25661        }
25662        #[doc = "`read()` method returns [`spacc_hash_chn_lock::R`](R) reader structure"]
25663        impl crate::Readable for SpaccHashChnLockSpec {}
25664        #[doc = "`write(|w| ..)` method takes [`spacc_hash_chn_lock::W`](W) writer structure"]
25665        impl crate::Writable for SpaccHashChnLockSpec {
25666            type Safety = crate::Unsafe;
25667        }
25668        #[doc = "`reset()` method sets SPACC_HASH_CHN_LOCK to value 0"]
25669        impl crate::Resettable for SpaccHashChnLockSpec {}
25670    }
25671    #[doc = "SPACC_SYM_CHN_CLEAR_REQ (rw) register accessor: Sym channel clear request\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_sym_chn_clear_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_sym_chn_clear_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_sym_chn_clear_req`] module"]
25672    #[doc(alias = "SPACC_SYM_CHN_CLEAR_REQ")]
25673    pub type SpaccSymChnClearReq = crate::Reg<spacc_sym_chn_clear_req::SpaccSymChnClearReqSpec>;
25674    #[doc = "Sym channel clear request"]
25675    pub mod spacc_sym_chn_clear_req {
25676        #[doc = "Register `SPACC_SYM_CHN_CLEAR_REQ` reader"]
25677        pub type R = crate::R<SpaccSymChnClearReqSpec>;
25678        #[doc = "Register `SPACC_SYM_CHN_CLEAR_REQ` writer"]
25679        pub type W = crate::W<SpaccSymChnClearReqSpec>;
25680        #[doc = "Field `sym_chn_clear_req` writer - Clear request for symmetric channels"]
25681        pub type SymChnClearReqW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
25682        impl W {
25683            #[doc = "Bits 0:31 - Clear request for symmetric channels"]
25684            #[inline(always)]
25685            pub fn sym_chn_clear_req(&mut self) -> SymChnClearReqW<'_, SpaccSymChnClearReqSpec> {
25686                SymChnClearReqW::new(self, 0)
25687            }
25688        }
25689        #[doc = "Sym channel clear request\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_sym_chn_clear_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_sym_chn_clear_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25690        pub struct SpaccSymChnClearReqSpec;
25691        impl crate::RegisterSpec for SpaccSymChnClearReqSpec {
25692            type Ux = u32;
25693        }
25694        #[doc = "`read()` method returns [`spacc_sym_chn_clear_req::R`](R) reader structure"]
25695        impl crate::Readable for SpaccSymChnClearReqSpec {}
25696        #[doc = "`write(|w| ..)` method takes [`spacc_sym_chn_clear_req::W`](W) writer structure"]
25697        impl crate::Writable for SpaccSymChnClearReqSpec {
25698            type Safety = crate::Unsafe;
25699        }
25700        #[doc = "`reset()` method sets SPACC_SYM_CHN_CLEAR_REQ to value 0"]
25701        impl crate::Resettable for SpaccSymChnClearReqSpec {}
25702    }
25703    #[doc = "SPACC_HASH_CHN_CLEAR_REQ (rw) register accessor: Hash channel clear request\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_hash_chn_clear_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_hash_chn_clear_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_hash_chn_clear_req`] module"]
25704    #[doc(alias = "SPACC_HASH_CHN_CLEAR_REQ")]
25705    pub type SpaccHashChnClearReq = crate::Reg<spacc_hash_chn_clear_req::SpaccHashChnClearReqSpec>;
25706    #[doc = "Hash channel clear request"]
25707    pub mod spacc_hash_chn_clear_req {
25708        #[doc = "Register `SPACC_HASH_CHN_CLEAR_REQ` reader"]
25709        pub type R = crate::R<SpaccHashChnClearReqSpec>;
25710        #[doc = "Register `SPACC_HASH_CHN_CLEAR_REQ` writer"]
25711        pub type W = crate::W<SpaccHashChnClearReqSpec>;
25712        #[doc = "Field `hash_chn_clear_req` writer - Clear request for hash channels"]
25713        pub type HashChnClearReqW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
25714        impl W {
25715            #[doc = "Bits 0:31 - Clear request for hash channels"]
25716            #[inline(always)]
25717            pub fn hash_chn_clear_req(&mut self) -> HashChnClearReqW<'_, SpaccHashChnClearReqSpec> {
25718                HashChnClearReqW::new(self, 0)
25719            }
25720        }
25721        #[doc = "Hash channel clear request\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_hash_chn_clear_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_hash_chn_clear_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25722        pub struct SpaccHashChnClearReqSpec;
25723        impl crate::RegisterSpec for SpaccHashChnClearReqSpec {
25724            type Ux = u32;
25725        }
25726        #[doc = "`read()` method returns [`spacc_hash_chn_clear_req::R`](R) reader structure"]
25727        impl crate::Readable for SpaccHashChnClearReqSpec {}
25728        #[doc = "`write(|w| ..)` method takes [`spacc_hash_chn_clear_req::W`](W) writer structure"]
25729        impl crate::Writable for SpaccHashChnClearReqSpec {
25730            type Safety = crate::Unsafe;
25731        }
25732        #[doc = "`reset()` method sets SPACC_HASH_CHN_CLEAR_REQ to value 0"]
25733        impl crate::Resettable for SpaccHashChnClearReqSpec {}
25734    }
25735    #[doc = "SPACC_BUS_ERR (rw) register accessor: Bus error register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_bus_err::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_bus_err::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_bus_err`] module"]
25736    #[doc(alias = "SPACC_BUS_ERR")]
25737    pub type SpaccBusErr = crate::Reg<spacc_bus_err::SpaccBusErrSpec>;
25738    #[doc = "Bus error register"]
25739    pub mod spacc_bus_err {
25740        #[doc = "Register `SPACC_BUS_ERR` reader"]
25741        pub type R = crate::R<SpaccBusErrSpec>;
25742        #[doc = "Register `SPACC_BUS_ERR` writer"]
25743        pub type W = crate::W<SpaccBusErrSpec>;
25744        #[doc = "Field `bus_err` reader - Bus error status"]
25745        pub type BusErrR = crate::FieldReader<u32>;
25746        impl R {
25747            #[doc = "Bits 0:31 - Bus error status"]
25748            #[inline(always)]
25749            pub fn bus_err(&self) -> BusErrR {
25750                BusErrR::new(self.bits)
25751            }
25752        }
25753        impl W {}
25754        #[doc = "Bus error register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_bus_err::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_bus_err::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25755        pub struct SpaccBusErrSpec;
25756        impl crate::RegisterSpec for SpaccBusErrSpec {
25757            type Ux = u32;
25758        }
25759        #[doc = "`read()` method returns [`spacc_bus_err::R`](R) reader structure"]
25760        impl crate::Readable for SpaccBusErrSpec {}
25761        #[doc = "`write(|w| ..)` method takes [`spacc_bus_err::W`](W) writer structure"]
25762        impl crate::Writable for SpaccBusErrSpec {
25763            type Safety = crate::Unsafe;
25764        }
25765        #[doc = "`reset()` method sets SPACC_BUS_ERR to value 0"]
25766        impl crate::Resettable for SpaccBusErrSpec {}
25767    }
25768    #[doc = "IN_SYM_CHN0_CTRL (rw) register accessor: Sym channel 0 control register (no-DMA mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_ctrl`] module"]
25769    #[doc(alias = "IN_SYM_CHN0_CTRL")]
25770    pub type InSymChn0Ctrl = crate::Reg<in_sym_chn0_ctrl::InSymChn0CtrlSpec>;
25771    #[doc = "Sym channel 0 control register (no-DMA mode)"]
25772    pub mod in_sym_chn0_ctrl {
25773        #[doc = "Register `IN_SYM_CHN0_CTRL` reader"]
25774        pub type R = crate::R<InSymChn0CtrlSpec>;
25775        #[doc = "Register `IN_SYM_CHN0_CTRL` writer"]
25776        pub type W = crate::W<InSymChn0CtrlSpec>;
25777        #[doc = "Field `sym_chn0_req` writer - Channel 0 start request"]
25778        pub type SymChn0ReqW<'a, REG> = crate::BitWriter<'a, REG>;
25779        impl W {
25780            #[doc = "Bit 31 - Channel 0 start request"]
25781            #[inline(always)]
25782            pub fn sym_chn0_req(&mut self) -> SymChn0ReqW<'_, InSymChn0CtrlSpec> {
25783                SymChn0ReqW::new(self, 31)
25784            }
25785        }
25786        #[doc = "Sym channel 0 control register (no-DMA mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25787        pub struct InSymChn0CtrlSpec;
25788        impl crate::RegisterSpec for InSymChn0CtrlSpec {
25789            type Ux = u32;
25790        }
25791        #[doc = "`read()` method returns [`in_sym_chn0_ctrl::R`](R) reader structure"]
25792        impl crate::Readable for InSymChn0CtrlSpec {}
25793        #[doc = "`write(|w| ..)` method takes [`in_sym_chn0_ctrl::W`](W) writer structure"]
25794        impl crate::Writable for InSymChn0CtrlSpec {
25795            type Safety = crate::Unsafe;
25796        }
25797        #[doc = "`reset()` method sets IN_SYM_CHN0_CTRL to value 0"]
25798        impl crate::Resettable for InSymChn0CtrlSpec {}
25799    }
25800    #[doc = "IN_SYM_CHN0_KEY_CTRL (rw) register accessor: Sym channel 0 key control (no-DMA mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_key_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_key_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_key_ctrl`] module"]
25801    #[doc(alias = "IN_SYM_CHN0_KEY_CTRL")]
25802    pub type InSymChn0KeyCtrl = crate::Reg<in_sym_chn0_key_ctrl::InSymChn0KeyCtrlSpec>;
25803    #[doc = "Sym channel 0 key control (no-DMA mode)"]
25804    pub mod in_sym_chn0_key_ctrl {
25805        #[doc = "Register `IN_SYM_CHN0_KEY_CTRL` reader"]
25806        pub type R = crate::R<InSymChn0KeyCtrlSpec>;
25807        #[doc = "Register `IN_SYM_CHN0_KEY_CTRL` writer"]
25808        pub type W = crate::W<InSymChn0KeyCtrlSpec>;
25809        #[doc = "Field `key_chn_id` reader - Key channel ID"]
25810        pub type KeyChnIdR = crate::FieldReader<u16>;
25811        #[doc = "Field `key_chn_id` writer - Key channel ID"]
25812        pub type KeyChnIdW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
25813        #[doc = "Algorithm: 2=AES; 4=LEA; 5=SM4; 6=GHASH; 7=TDES\n\nValue on reset: 0"]
25814        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
25815        #[repr(u8)]
25816        pub enum AlgSel {
25817            #[doc = "2: AES algorithm"]
25818            Aes = 2,
25819            #[doc = "4: LEA (Lightweight Encryption Algorithm)"]
25820            Lea = 4,
25821            #[doc = "5: SM4 (Chinese national standard)"]
25822            Sm4 = 5,
25823            #[doc = "6: GHASH (GCM authentication)"]
25824            Ghash = 6,
25825            #[doc = "7: Triple DES"]
25826            Tdes = 7,
25827        }
25828        impl From<AlgSel> for u8 {
25829            #[inline(always)]
25830            fn from(variant: AlgSel) -> Self {
25831                variant as _
25832            }
25833        }
25834        impl crate::FieldSpec for AlgSel {
25835            type Ux = u8;
25836        }
25837        impl crate::IsEnum for AlgSel {}
25838        #[doc = "Field `alg_sel` reader - Algorithm: 2=AES; 4=LEA; 5=SM4; 6=GHASH; 7=TDES"]
25839        pub type AlgSelR = crate::FieldReader<AlgSel>;
25840        impl AlgSelR {
25841            #[doc = "Get enumerated values variant"]
25842            #[inline(always)]
25843            pub const fn variant(&self) -> Option<AlgSel> {
25844                match self.bits {
25845                    2 => Some(AlgSel::Aes),
25846                    4 => Some(AlgSel::Lea),
25847                    5 => Some(AlgSel::Sm4),
25848                    6 => Some(AlgSel::Ghash),
25849                    7 => Some(AlgSel::Tdes),
25850                    _ => None,
25851                }
25852            }
25853            #[doc = "AES algorithm"]
25854            #[inline(always)]
25855            pub fn is_aes(&self) -> bool {
25856                *self == AlgSel::Aes
25857            }
25858            #[doc = "LEA (Lightweight Encryption Algorithm)"]
25859            #[inline(always)]
25860            pub fn is_lea(&self) -> bool {
25861                *self == AlgSel::Lea
25862            }
25863            #[doc = "SM4 (Chinese national standard)"]
25864            #[inline(always)]
25865            pub fn is_sm4(&self) -> bool {
25866                *self == AlgSel::Sm4
25867            }
25868            #[doc = "GHASH (GCM authentication)"]
25869            #[inline(always)]
25870            pub fn is_ghash(&self) -> bool {
25871                *self == AlgSel::Ghash
25872            }
25873            #[doc = "Triple DES"]
25874            #[inline(always)]
25875            pub fn is_tdes(&self) -> bool {
25876                *self == AlgSel::Tdes
25877            }
25878        }
25879        #[doc = "Field `alg_sel` writer - Algorithm: 2=AES; 4=LEA; 5=SM4; 6=GHASH; 7=TDES"]
25880        pub type AlgSelW<'a, REG> = crate::FieldWriter<'a, REG, 4, AlgSel>;
25881        impl<'a, REG> AlgSelW<'a, REG>
25882        where
25883            REG: crate::Writable + crate::RegisterSpec,
25884            REG::Ux: From<u8>,
25885        {
25886            #[doc = "AES algorithm"]
25887            #[inline(always)]
25888            pub fn aes(self) -> &'a mut crate::W<REG> {
25889                self.variant(AlgSel::Aes)
25890            }
25891            #[doc = "LEA (Lightweight Encryption Algorithm)"]
25892            #[inline(always)]
25893            pub fn lea(self) -> &'a mut crate::W<REG> {
25894                self.variant(AlgSel::Lea)
25895            }
25896            #[doc = "SM4 (Chinese national standard)"]
25897            #[inline(always)]
25898            pub fn sm4(self) -> &'a mut crate::W<REG> {
25899                self.variant(AlgSel::Sm4)
25900            }
25901            #[doc = "GHASH (GCM authentication)"]
25902            #[inline(always)]
25903            pub fn ghash(self) -> &'a mut crate::W<REG> {
25904                self.variant(AlgSel::Ghash)
25905            }
25906            #[doc = "Triple DES"]
25907            #[inline(always)]
25908            pub fn tdes(self) -> &'a mut crate::W<REG> {
25909                self.variant(AlgSel::Tdes)
25910            }
25911        }
25912        #[doc = "Mode: 1=ECB; 3=CBC; 6=CTR; 0xA=GCM; 0xC=CMAC\n\nValue on reset: 0"]
25913        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
25914        #[repr(u8)]
25915        pub enum AlgMode {
25916            #[doc = "1: Electronic Codebook"]
25917            Ecb = 1,
25918            #[doc = "3: Cipher Block Chaining"]
25919            Cbc = 3,
25920            #[doc = "6: Counter mode"]
25921            Ctr = 6,
25922            #[doc = "7: Output Feedback"]
25923            Ofb = 7,
25924            #[doc = "8: Cipher Feedback"]
25925            Cfb = 8,
25926            #[doc = "9: CCM authenticated encryption"]
25927            Ccm = 9,
25928            #[doc = "10: Galois/Counter Mode"]
25929            Gcm = 10,
25930            #[doc = "11: GCM CTR only"]
25931            Gctr = 11,
25932            #[doc = "12: Cipher-based MAC"]
25933            Cmac = 12,
25934        }
25935        impl From<AlgMode> for u8 {
25936            #[inline(always)]
25937            fn from(variant: AlgMode) -> Self {
25938                variant as _
25939            }
25940        }
25941        impl crate::FieldSpec for AlgMode {
25942            type Ux = u8;
25943        }
25944        impl crate::IsEnum for AlgMode {}
25945        #[doc = "Field `alg_mode` reader - Mode: 1=ECB; 3=CBC; 6=CTR; 0xA=GCM; 0xC=CMAC"]
25946        pub type AlgModeR = crate::FieldReader<AlgMode>;
25947        impl AlgModeR {
25948            #[doc = "Get enumerated values variant"]
25949            #[inline(always)]
25950            pub const fn variant(&self) -> Option<AlgMode> {
25951                match self.bits {
25952                    1 => Some(AlgMode::Ecb),
25953                    3 => Some(AlgMode::Cbc),
25954                    6 => Some(AlgMode::Ctr),
25955                    7 => Some(AlgMode::Ofb),
25956                    8 => Some(AlgMode::Cfb),
25957                    9 => Some(AlgMode::Ccm),
25958                    10 => Some(AlgMode::Gcm),
25959                    11 => Some(AlgMode::Gctr),
25960                    12 => Some(AlgMode::Cmac),
25961                    _ => None,
25962                }
25963            }
25964            #[doc = "Electronic Codebook"]
25965            #[inline(always)]
25966            pub fn is_ecb(&self) -> bool {
25967                *self == AlgMode::Ecb
25968            }
25969            #[doc = "Cipher Block Chaining"]
25970            #[inline(always)]
25971            pub fn is_cbc(&self) -> bool {
25972                *self == AlgMode::Cbc
25973            }
25974            #[doc = "Counter mode"]
25975            #[inline(always)]
25976            pub fn is_ctr(&self) -> bool {
25977                *self == AlgMode::Ctr
25978            }
25979            #[doc = "Output Feedback"]
25980            #[inline(always)]
25981            pub fn is_ofb(&self) -> bool {
25982                *self == AlgMode::Ofb
25983            }
25984            #[doc = "Cipher Feedback"]
25985            #[inline(always)]
25986            pub fn is_cfb(&self) -> bool {
25987                *self == AlgMode::Cfb
25988            }
25989            #[doc = "CCM authenticated encryption"]
25990            #[inline(always)]
25991            pub fn is_ccm(&self) -> bool {
25992                *self == AlgMode::Ccm
25993            }
25994            #[doc = "Galois/Counter Mode"]
25995            #[inline(always)]
25996            pub fn is_gcm(&self) -> bool {
25997                *self == AlgMode::Gcm
25998            }
25999            #[doc = "GCM CTR only"]
26000            #[inline(always)]
26001            pub fn is_gctr(&self) -> bool {
26002                *self == AlgMode::Gctr
26003            }
26004            #[doc = "Cipher-based MAC"]
26005            #[inline(always)]
26006            pub fn is_cmac(&self) -> bool {
26007                *self == AlgMode::Cmac
26008            }
26009        }
26010        #[doc = "Field `alg_mode` writer - Mode: 1=ECB; 3=CBC; 6=CTR; 0xA=GCM; 0xC=CMAC"]
26011        pub type AlgModeW<'a, REG> = crate::FieldWriter<'a, REG, 4, AlgMode>;
26012        impl<'a, REG> AlgModeW<'a, REG>
26013        where
26014            REG: crate::Writable + crate::RegisterSpec,
26015            REG::Ux: From<u8>,
26016        {
26017            #[doc = "Electronic Codebook"]
26018            #[inline(always)]
26019            pub fn ecb(self) -> &'a mut crate::W<REG> {
26020                self.variant(AlgMode::Ecb)
26021            }
26022            #[doc = "Cipher Block Chaining"]
26023            #[inline(always)]
26024            pub fn cbc(self) -> &'a mut crate::W<REG> {
26025                self.variant(AlgMode::Cbc)
26026            }
26027            #[doc = "Counter mode"]
26028            #[inline(always)]
26029            pub fn ctr(self) -> &'a mut crate::W<REG> {
26030                self.variant(AlgMode::Ctr)
26031            }
26032            #[doc = "Output Feedback"]
26033            #[inline(always)]
26034            pub fn ofb(self) -> &'a mut crate::W<REG> {
26035                self.variant(AlgMode::Ofb)
26036            }
26037            #[doc = "Cipher Feedback"]
26038            #[inline(always)]
26039            pub fn cfb(self) -> &'a mut crate::W<REG> {
26040                self.variant(AlgMode::Cfb)
26041            }
26042            #[doc = "CCM authenticated encryption"]
26043            #[inline(always)]
26044            pub fn ccm(self) -> &'a mut crate::W<REG> {
26045                self.variant(AlgMode::Ccm)
26046            }
26047            #[doc = "Galois/Counter Mode"]
26048            #[inline(always)]
26049            pub fn gcm(self) -> &'a mut crate::W<REG> {
26050                self.variant(AlgMode::Gcm)
26051            }
26052            #[doc = "GCM CTR only"]
26053            #[inline(always)]
26054            pub fn gctr(self) -> &'a mut crate::W<REG> {
26055                self.variant(AlgMode::Gctr)
26056            }
26057            #[doc = "Cipher-based MAC"]
26058            #[inline(always)]
26059            pub fn cmac(self) -> &'a mut crate::W<REG> {
26060                self.variant(AlgMode::Cmac)
26061            }
26062        }
26063        #[doc = "Key length: 0=128bit; 1=192bit; 2=256bit\n\nValue on reset: 0"]
26064        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
26065        #[repr(u8)]
26066        pub enum KeyLen {
26067            #[doc = "0: 128-bit key"]
26068            Key128 = 0,
26069            #[doc = "1: 192-bit key"]
26070            Key192 = 1,
26071            #[doc = "2: 256-bit key"]
26072            Key256 = 2,
26073        }
26074        impl From<KeyLen> for u8 {
26075            #[inline(always)]
26076            fn from(variant: KeyLen) -> Self {
26077                variant as _
26078            }
26079        }
26080        impl crate::FieldSpec for KeyLen {
26081            type Ux = u8;
26082        }
26083        impl crate::IsEnum for KeyLen {}
26084        #[doc = "Field `key_len` reader - Key length: 0=128bit; 1=192bit; 2=256bit"]
26085        pub type KeyLenR = crate::FieldReader<KeyLen>;
26086        impl KeyLenR {
26087            #[doc = "Get enumerated values variant"]
26088            #[inline(always)]
26089            pub const fn variant(&self) -> Option<KeyLen> {
26090                match self.bits {
26091                    0 => Some(KeyLen::Key128),
26092                    1 => Some(KeyLen::Key192),
26093                    2 => Some(KeyLen::Key256),
26094                    _ => None,
26095                }
26096            }
26097            #[doc = "128-bit key"]
26098            #[inline(always)]
26099            pub fn is_key128(&self) -> bool {
26100                *self == KeyLen::Key128
26101            }
26102            #[doc = "192-bit key"]
26103            #[inline(always)]
26104            pub fn is_key192(&self) -> bool {
26105                *self == KeyLen::Key192
26106            }
26107            #[doc = "256-bit key"]
26108            #[inline(always)]
26109            pub fn is_key256(&self) -> bool {
26110                *self == KeyLen::Key256
26111            }
26112        }
26113        #[doc = "Field `key_len` writer - Key length: 0=128bit; 1=192bit; 2=256bit"]
26114        pub type KeyLenW<'a, REG> = crate::FieldWriter<'a, REG, 2, KeyLen>;
26115        impl<'a, REG> KeyLenW<'a, REG>
26116        where
26117            REG: crate::Writable + crate::RegisterSpec,
26118            REG::Ux: From<u8>,
26119        {
26120            #[doc = "128-bit key"]
26121            #[inline(always)]
26122            pub fn key128(self) -> &'a mut crate::W<REG> {
26123                self.variant(KeyLen::Key128)
26124            }
26125            #[doc = "192-bit key"]
26126            #[inline(always)]
26127            pub fn key192(self) -> &'a mut crate::W<REG> {
26128                self.variant(KeyLen::Key192)
26129            }
26130            #[doc = "256-bit key"]
26131            #[inline(always)]
26132            pub fn key256(self) -> &'a mut crate::W<REG> {
26133                self.variant(KeyLen::Key256)
26134            }
26135        }
26136        #[doc = "Data width: 0=128bit; 1=64bit; 2=32bit\n\nValue on reset: 0"]
26137        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
26138        #[repr(u8)]
26139        pub enum DataWidth {
26140            #[doc = "0: 128-bit data path"]
26141            Width128 = 0,
26142            #[doc = "1: 64-bit data path"]
26143            Width64 = 1,
26144            #[doc = "2: 32-bit data path"]
26145            Width32 = 2,
26146        }
26147        impl From<DataWidth> for u8 {
26148            #[inline(always)]
26149            fn from(variant: DataWidth) -> Self {
26150                variant as _
26151            }
26152        }
26153        impl crate::FieldSpec for DataWidth {
26154            type Ux = u8;
26155        }
26156        impl crate::IsEnum for DataWidth {}
26157        #[doc = "Field `data_width` reader - Data width: 0=128bit; 1=64bit; 2=32bit"]
26158        pub type DataWidthR = crate::FieldReader<DataWidth>;
26159        impl DataWidthR {
26160            #[doc = "Get enumerated values variant"]
26161            #[inline(always)]
26162            pub const fn variant(&self) -> Option<DataWidth> {
26163                match self.bits {
26164                    0 => Some(DataWidth::Width128),
26165                    1 => Some(DataWidth::Width64),
26166                    2 => Some(DataWidth::Width32),
26167                    _ => None,
26168                }
26169            }
26170            #[doc = "128-bit data path"]
26171            #[inline(always)]
26172            pub fn is_width128(&self) -> bool {
26173                *self == DataWidth::Width128
26174            }
26175            #[doc = "64-bit data path"]
26176            #[inline(always)]
26177            pub fn is_width64(&self) -> bool {
26178                *self == DataWidth::Width64
26179            }
26180            #[doc = "32-bit data path"]
26181            #[inline(always)]
26182            pub fn is_width32(&self) -> bool {
26183                *self == DataWidth::Width32
26184            }
26185        }
26186        #[doc = "Field `data_width` writer - Data width: 0=128bit; 1=64bit; 2=32bit"]
26187        pub type DataWidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, DataWidth>;
26188        impl<'a, REG> DataWidthW<'a, REG>
26189        where
26190            REG: crate::Writable + crate::RegisterSpec,
26191            REG::Ux: From<u8>,
26192        {
26193            #[doc = "128-bit data path"]
26194            #[inline(always)]
26195            pub fn width128(self) -> &'a mut crate::W<REG> {
26196                self.variant(DataWidth::Width128)
26197            }
26198            #[doc = "64-bit data path"]
26199            #[inline(always)]
26200            pub fn width64(self) -> &'a mut crate::W<REG> {
26201                self.variant(DataWidth::Width64)
26202            }
26203            #[doc = "32-bit data path"]
26204            #[inline(always)]
26205            pub fn width32(self) -> &'a mut crate::W<REG> {
26206                self.variant(DataWidth::Width32)
26207            }
26208        }
26209        #[doc = "Field `decrypt` reader - Decrypt: 0=encrypt; 1=decrypt"]
26210        pub type DecryptR = crate::BitReader;
26211        #[doc = "Field `decrypt` writer - Decrypt: 0=encrypt; 1=decrypt"]
26212        pub type DecryptW<'a, REG> = crate::BitWriter<'a, REG>;
26213        impl R {
26214            #[doc = "Bits 0:8 - Key channel ID"]
26215            #[inline(always)]
26216            pub fn key_chn_id(&self) -> KeyChnIdR {
26217                KeyChnIdR::new((self.bits & 0x01ff) as u16)
26218            }
26219            #[doc = "Bits 16:19 - Algorithm: 2=AES; 4=LEA; 5=SM4; 6=GHASH; 7=TDES"]
26220            #[inline(always)]
26221            pub fn alg_sel(&self) -> AlgSelR {
26222                AlgSelR::new(((self.bits >> 16) & 0x0f) as u8)
26223            }
26224            #[doc = "Bits 20:23 - Mode: 1=ECB; 3=CBC; 6=CTR; 0xA=GCM; 0xC=CMAC"]
26225            #[inline(always)]
26226            pub fn alg_mode(&self) -> AlgModeR {
26227                AlgModeR::new(((self.bits >> 20) & 0x0f) as u8)
26228            }
26229            #[doc = "Bits 24:25 - Key length: 0=128bit; 1=192bit; 2=256bit"]
26230            #[inline(always)]
26231            pub fn key_len(&self) -> KeyLenR {
26232                KeyLenR::new(((self.bits >> 24) & 3) as u8)
26233            }
26234            #[doc = "Bits 26:27 - Data width: 0=128bit; 1=64bit; 2=32bit"]
26235            #[inline(always)]
26236            pub fn data_width(&self) -> DataWidthR {
26237                DataWidthR::new(((self.bits >> 26) & 3) as u8)
26238            }
26239            #[doc = "Bit 28 - Decrypt: 0=encrypt; 1=decrypt"]
26240            #[inline(always)]
26241            pub fn decrypt(&self) -> DecryptR {
26242                DecryptR::new(((self.bits >> 28) & 1) != 0)
26243            }
26244        }
26245        impl W {
26246            #[doc = "Bits 0:8 - Key channel ID"]
26247            #[inline(always)]
26248            pub fn key_chn_id(&mut self) -> KeyChnIdW<'_, InSymChn0KeyCtrlSpec> {
26249                KeyChnIdW::new(self, 0)
26250            }
26251            #[doc = "Bits 16:19 - Algorithm: 2=AES; 4=LEA; 5=SM4; 6=GHASH; 7=TDES"]
26252            #[inline(always)]
26253            pub fn alg_sel(&mut self) -> AlgSelW<'_, InSymChn0KeyCtrlSpec> {
26254                AlgSelW::new(self, 16)
26255            }
26256            #[doc = "Bits 20:23 - Mode: 1=ECB; 3=CBC; 6=CTR; 0xA=GCM; 0xC=CMAC"]
26257            #[inline(always)]
26258            pub fn alg_mode(&mut self) -> AlgModeW<'_, InSymChn0KeyCtrlSpec> {
26259                AlgModeW::new(self, 20)
26260            }
26261            #[doc = "Bits 24:25 - Key length: 0=128bit; 1=192bit; 2=256bit"]
26262            #[inline(always)]
26263            pub fn key_len(&mut self) -> KeyLenW<'_, InSymChn0KeyCtrlSpec> {
26264                KeyLenW::new(self, 24)
26265            }
26266            #[doc = "Bits 26:27 - Data width: 0=128bit; 1=64bit; 2=32bit"]
26267            #[inline(always)]
26268            pub fn data_width(&mut self) -> DataWidthW<'_, InSymChn0KeyCtrlSpec> {
26269                DataWidthW::new(self, 26)
26270            }
26271            #[doc = "Bit 28 - Decrypt: 0=encrypt; 1=decrypt"]
26272            #[inline(always)]
26273            pub fn decrypt(&mut self) -> DecryptW<'_, InSymChn0KeyCtrlSpec> {
26274                DecryptW::new(self, 28)
26275            }
26276        }
26277        #[doc = "Sym channel 0 key control (no-DMA mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_key_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_key_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26278        pub struct InSymChn0KeyCtrlSpec;
26279        impl crate::RegisterSpec for InSymChn0KeyCtrlSpec {
26280            type Ux = u32;
26281        }
26282        #[doc = "`read()` method returns [`in_sym_chn0_key_ctrl::R`](R) reader structure"]
26283        impl crate::Readable for InSymChn0KeyCtrlSpec {}
26284        #[doc = "`write(|w| ..)` method takes [`in_sym_chn0_key_ctrl::W`](W) writer structure"]
26285        impl crate::Writable for InSymChn0KeyCtrlSpec {
26286            type Safety = crate::Unsafe;
26287        }
26288        #[doc = "`reset()` method sets IN_SYM_CHN0_KEY_CTRL to value 0"]
26289        impl crate::Resettable for InSymChn0KeyCtrlSpec {}
26290    }
26291    #[doc = "IN_SYM_CHN0_SPECIAL_CTRL (rw) register accessor: Sym channel 0 special control\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_special_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_special_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_special_ctrl`] module"]
26292    #[doc(alias = "IN_SYM_CHN0_SPECIAL_CTRL")]
26293    pub type InSymChn0SpecialCtrl = crate::Reg<in_sym_chn0_special_ctrl::InSymChn0SpecialCtrlSpec>;
26294    #[doc = "Sym channel 0 special control"]
26295    pub mod in_sym_chn0_special_ctrl {
26296        #[doc = "Register `IN_SYM_CHN0_SPECIAL_CTRL` reader"]
26297        pub type R = crate::R<InSymChn0SpecialCtrlSpec>;
26298        #[doc = "Register `IN_SYM_CHN0_SPECIAL_CTRL` writer"]
26299        pub type W = crate::W<InSymChn0SpecialCtrlSpec>;
26300        #[doc = "Field `sym_chn0_odd_even` reader - Odd/even control for TDES"]
26301        pub type SymChn0OddEvenR = crate::BitReader;
26302        #[doc = "Field `sym_chn0_odd_even` writer - Odd/even control for TDES"]
26303        pub type SymChn0OddEvenW<'a, REG> = crate::BitWriter<'a, REG>;
26304        impl R {
26305            #[doc = "Bit 0 - Odd/even control for TDES"]
26306            #[inline(always)]
26307            pub fn sym_chn0_odd_even(&self) -> SymChn0OddEvenR {
26308                SymChn0OddEvenR::new((self.bits & 1) != 0)
26309            }
26310        }
26311        impl W {
26312            #[doc = "Bit 0 - Odd/even control for TDES"]
26313            #[inline(always)]
26314            pub fn sym_chn0_odd_even(&mut self) -> SymChn0OddEvenW<'_, InSymChn0SpecialCtrlSpec> {
26315                SymChn0OddEvenW::new(self, 0)
26316            }
26317        }
26318        #[doc = "Sym channel 0 special control\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_special_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_special_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26319        pub struct InSymChn0SpecialCtrlSpec;
26320        impl crate::RegisterSpec for InSymChn0SpecialCtrlSpec {
26321            type Ux = u32;
26322        }
26323        #[doc = "`read()` method returns [`in_sym_chn0_special_ctrl::R`](R) reader structure"]
26324        impl crate::Readable for InSymChn0SpecialCtrlSpec {}
26325        #[doc = "`write(|w| ..)` method takes [`in_sym_chn0_special_ctrl::W`](W) writer structure"]
26326        impl crate::Writable for InSymChn0SpecialCtrlSpec {
26327            type Safety = crate::Unsafe;
26328        }
26329        #[doc = "`reset()` method sets IN_SYM_CHN0_SPECIAL_CTRL to value 0"]
26330        impl crate::Resettable for InSymChn0SpecialCtrlSpec {}
26331    }
26332    #[doc = "IN_SYM_CHN0_IV_DATA_CTRL (rw) register accessor: Sym channel 0 IV/data control (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv_data_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv_data_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_iv_data_ctrl`] module"]
26333    #[doc(alias = "IN_SYM_CHN0_IV_DATA_CTRL")]
26334    pub type InSymChn0IvDataCtrl = crate::Reg<in_sym_chn0_iv_data_ctrl::InSymChn0IvDataCtrlSpec>;
26335    #[doc = "Sym channel 0 IV/data control (register mode)"]
26336    pub mod in_sym_chn0_iv_data_ctrl {
26337        #[doc = "Register `IN_SYM_CHN0_IV_DATA_CTRL` reader"]
26338        pub type R = crate::R<InSymChn0IvDataCtrlSpec>;
26339        #[doc = "Register `IN_SYM_CHN0_IV_DATA_CTRL` writer"]
26340        pub type W = crate::W<InSymChn0IvDataCtrlSpec>;
26341        #[doc = "Field `first_block` reader - First block flag"]
26342        pub type FirstBlockR = crate::BitReader;
26343        #[doc = "Field `first_block` writer - First block flag"]
26344        pub type FirstBlockW<'a, REG> = crate::BitWriter<'a, REG>;
26345        #[doc = "Field `last_block` reader - Last block flag"]
26346        pub type LastBlockR = crate::BitReader;
26347        #[doc = "Field `last_block` writer - Last block flag"]
26348        pub type LastBlockW<'a, REG> = crate::BitWriter<'a, REG>;
26349        #[doc = "Field `block_len` reader - Block length (in bytes)"]
26350        pub type BlockLenR = crate::FieldReader;
26351        #[doc = "Field `block_len` writer - Block length (in bytes)"]
26352        pub type BlockLenW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
26353        impl R {
26354            #[doc = "Bit 0 - First block flag"]
26355            #[inline(always)]
26356            pub fn first_block(&self) -> FirstBlockR {
26357                FirstBlockR::new((self.bits & 1) != 0)
26358            }
26359            #[doc = "Bit 1 - Last block flag"]
26360            #[inline(always)]
26361            pub fn last_block(&self) -> LastBlockR {
26362                LastBlockR::new(((self.bits >> 1) & 1) != 0)
26363            }
26364            #[doc = "Bits 16:20 - Block length (in bytes)"]
26365            #[inline(always)]
26366            pub fn block_len(&self) -> BlockLenR {
26367                BlockLenR::new(((self.bits >> 16) & 0x1f) as u8)
26368            }
26369        }
26370        impl W {
26371            #[doc = "Bit 0 - First block flag"]
26372            #[inline(always)]
26373            pub fn first_block(&mut self) -> FirstBlockW<'_, InSymChn0IvDataCtrlSpec> {
26374                FirstBlockW::new(self, 0)
26375            }
26376            #[doc = "Bit 1 - Last block flag"]
26377            #[inline(always)]
26378            pub fn last_block(&mut self) -> LastBlockW<'_, InSymChn0IvDataCtrlSpec> {
26379                LastBlockW::new(self, 1)
26380            }
26381            #[doc = "Bits 16:20 - Block length (in bytes)"]
26382            #[inline(always)]
26383            pub fn block_len(&mut self) -> BlockLenW<'_, InSymChn0IvDataCtrlSpec> {
26384                BlockLenW::new(self, 16)
26385            }
26386        }
26387        #[doc = "Sym channel 0 IV/data control (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv_data_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv_data_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26388        pub struct InSymChn0IvDataCtrlSpec;
26389        impl crate::RegisterSpec for InSymChn0IvDataCtrlSpec {
26390            type Ux = u32;
26391        }
26392        #[doc = "`read()` method returns [`in_sym_chn0_iv_data_ctrl::R`](R) reader structure"]
26393        impl crate::Readable for InSymChn0IvDataCtrlSpec {}
26394        #[doc = "`write(|w| ..)` method takes [`in_sym_chn0_iv_data_ctrl::W`](W) writer structure"]
26395        impl crate::Writable for InSymChn0IvDataCtrlSpec {
26396            type Safety = crate::Unsafe;
26397        }
26398        #[doc = "`reset()` method sets IN_SYM_CHN0_IV_DATA_CTRL to value 0"]
26399        impl crate::Resettable for InSymChn0IvDataCtrlSpec {}
26400    }
26401    #[doc = "IN_SYM_CHN0_IV0 (rw) register accessor: Sym channel 0 IV word 0 (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_iv0`] module"]
26402    #[doc(alias = "IN_SYM_CHN0_IV0")]
26403    pub type InSymChn0Iv0 = crate::Reg<in_sym_chn0_iv0::InSymChn0Iv0Spec>;
26404    #[doc = "Sym channel 0 IV word 0 (register mode)"]
26405    pub mod in_sym_chn0_iv0 {
26406        #[doc = "Register `IN_SYM_CHN0_IV0` reader"]
26407        pub type R = crate::R<InSymChn0Iv0Spec>;
26408        #[doc = "Register `IN_SYM_CHN0_IV0` writer"]
26409        pub type W = crate::W<InSymChn0Iv0Spec>;
26410        #[doc = "Field `iv0` reader - IV\\[31:0\\]"]
26411        pub type Iv0R = crate::FieldReader<u32>;
26412        #[doc = "Field `iv0` writer - IV\\[31:0\\]"]
26413        pub type Iv0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
26414        impl R {
26415            #[doc = "Bits 0:31 - IV\\[31:0\\]"]
26416            #[inline(always)]
26417            pub fn iv0(&self) -> Iv0R {
26418                Iv0R::new(self.bits)
26419            }
26420        }
26421        impl W {
26422            #[doc = "Bits 0:31 - IV\\[31:0\\]"]
26423            #[inline(always)]
26424            pub fn iv0(&mut self) -> Iv0W<'_, InSymChn0Iv0Spec> {
26425                Iv0W::new(self, 0)
26426            }
26427        }
26428        #[doc = "Sym channel 0 IV word 0 (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26429        pub struct InSymChn0Iv0Spec;
26430        impl crate::RegisterSpec for InSymChn0Iv0Spec {
26431            type Ux = u32;
26432        }
26433        #[doc = "`read()` method returns [`in_sym_chn0_iv0::R`](R) reader structure"]
26434        impl crate::Readable for InSymChn0Iv0Spec {}
26435        #[doc = "`write(|w| ..)` method takes [`in_sym_chn0_iv0::W`](W) writer structure"]
26436        impl crate::Writable for InSymChn0Iv0Spec {
26437            type Safety = crate::Unsafe;
26438        }
26439        #[doc = "`reset()` method sets IN_SYM_CHN0_IV0 to value 0"]
26440        impl crate::Resettable for InSymChn0Iv0Spec {}
26441    }
26442    #[doc = "IN_SYM_CHN0_IV1 (rw) register accessor: Sym channel 0 IV word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_iv1`] module"]
26443    #[doc(alias = "IN_SYM_CHN0_IV1")]
26444    pub type InSymChn0Iv1 = crate::Reg<in_sym_chn0_iv1::InSymChn0Iv1Spec>;
26445    #[doc = "Sym channel 0 IV word 1"]
26446    pub mod in_sym_chn0_iv1 {
26447        #[doc = "Register `IN_SYM_CHN0_IV1` reader"]
26448        pub type R = crate::R<InSymChn0Iv1Spec>;
26449        #[doc = "Register `IN_SYM_CHN0_IV1` writer"]
26450        pub type W = crate::W<InSymChn0Iv1Spec>;
26451        #[doc = "Field `iv1` reader - IV\\[63:32\\]"]
26452        pub type Iv1R = crate::FieldReader<u32>;
26453        #[doc = "Field `iv1` writer - IV\\[63:32\\]"]
26454        pub type Iv1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
26455        impl R {
26456            #[doc = "Bits 0:31 - IV\\[63:32\\]"]
26457            #[inline(always)]
26458            pub fn iv1(&self) -> Iv1R {
26459                Iv1R::new(self.bits)
26460            }
26461        }
26462        impl W {
26463            #[doc = "Bits 0:31 - IV\\[63:32\\]"]
26464            #[inline(always)]
26465            pub fn iv1(&mut self) -> Iv1W<'_, InSymChn0Iv1Spec> {
26466                Iv1W::new(self, 0)
26467            }
26468        }
26469        #[doc = "Sym channel 0 IV word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26470        pub struct InSymChn0Iv1Spec;
26471        impl crate::RegisterSpec for InSymChn0Iv1Spec {
26472            type Ux = u32;
26473        }
26474        #[doc = "`read()` method returns [`in_sym_chn0_iv1::R`](R) reader structure"]
26475        impl crate::Readable for InSymChn0Iv1Spec {}
26476        #[doc = "`write(|w| ..)` method takes [`in_sym_chn0_iv1::W`](W) writer structure"]
26477        impl crate::Writable for InSymChn0Iv1Spec {
26478            type Safety = crate::Unsafe;
26479        }
26480        #[doc = "`reset()` method sets IN_SYM_CHN0_IV1 to value 0"]
26481        impl crate::Resettable for InSymChn0Iv1Spec {}
26482    }
26483    #[doc = "IN_SYM_CHN0_IV2 (rw) register accessor: Sym channel 0 IV word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_iv2`] module"]
26484    #[doc(alias = "IN_SYM_CHN0_IV2")]
26485    pub type InSymChn0Iv2 = crate::Reg<in_sym_chn0_iv2::InSymChn0Iv2Spec>;
26486    #[doc = "Sym channel 0 IV word 2"]
26487    pub mod in_sym_chn0_iv2 {
26488        #[doc = "Register `IN_SYM_CHN0_IV2` reader"]
26489        pub type R = crate::R<InSymChn0Iv2Spec>;
26490        #[doc = "Register `IN_SYM_CHN0_IV2` writer"]
26491        pub type W = crate::W<InSymChn0Iv2Spec>;
26492        #[doc = "Field `iv2` reader - IV\\[95:64\\]"]
26493        pub type Iv2R = crate::FieldReader<u32>;
26494        #[doc = "Field `iv2` writer - IV\\[95:64\\]"]
26495        pub type Iv2W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
26496        impl R {
26497            #[doc = "Bits 0:31 - IV\\[95:64\\]"]
26498            #[inline(always)]
26499            pub fn iv2(&self) -> Iv2R {
26500                Iv2R::new(self.bits)
26501            }
26502        }
26503        impl W {
26504            #[doc = "Bits 0:31 - IV\\[95:64\\]"]
26505            #[inline(always)]
26506            pub fn iv2(&mut self) -> Iv2W<'_, InSymChn0Iv2Spec> {
26507                Iv2W::new(self, 0)
26508            }
26509        }
26510        #[doc = "Sym channel 0 IV word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26511        pub struct InSymChn0Iv2Spec;
26512        impl crate::RegisterSpec for InSymChn0Iv2Spec {
26513            type Ux = u32;
26514        }
26515        #[doc = "`read()` method returns [`in_sym_chn0_iv2::R`](R) reader structure"]
26516        impl crate::Readable for InSymChn0Iv2Spec {}
26517        #[doc = "`write(|w| ..)` method takes [`in_sym_chn0_iv2::W`](W) writer structure"]
26518        impl crate::Writable for InSymChn0Iv2Spec {
26519            type Safety = crate::Unsafe;
26520        }
26521        #[doc = "`reset()` method sets IN_SYM_CHN0_IV2 to value 0"]
26522        impl crate::Resettable for InSymChn0Iv2Spec {}
26523    }
26524    #[doc = "IN_SYM_CHN0_IV3 (rw) register accessor: Sym channel 0 IV word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_iv3`] module"]
26525    #[doc(alias = "IN_SYM_CHN0_IV3")]
26526    pub type InSymChn0Iv3 = crate::Reg<in_sym_chn0_iv3::InSymChn0Iv3Spec>;
26527    #[doc = "Sym channel 0 IV word 3"]
26528    pub mod in_sym_chn0_iv3 {
26529        #[doc = "Register `IN_SYM_CHN0_IV3` reader"]
26530        pub type R = crate::R<InSymChn0Iv3Spec>;
26531        #[doc = "Register `IN_SYM_CHN0_IV3` writer"]
26532        pub type W = crate::W<InSymChn0Iv3Spec>;
26533        #[doc = "Field `iv3` reader - IV\\[127:96\\]"]
26534        pub type Iv3R = crate::FieldReader<u32>;
26535        #[doc = "Field `iv3` writer - IV\\[127:96\\]"]
26536        pub type Iv3W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
26537        impl R {
26538            #[doc = "Bits 0:31 - IV\\[127:96\\]"]
26539            #[inline(always)]
26540            pub fn iv3(&self) -> Iv3R {
26541                Iv3R::new(self.bits)
26542            }
26543        }
26544        impl W {
26545            #[doc = "Bits 0:31 - IV\\[127:96\\]"]
26546            #[inline(always)]
26547            pub fn iv3(&mut self) -> Iv3W<'_, InSymChn0Iv3Spec> {
26548                Iv3W::new(self, 0)
26549            }
26550        }
26551        #[doc = "Sym channel 0 IV word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26552        pub struct InSymChn0Iv3Spec;
26553        impl crate::RegisterSpec for InSymChn0Iv3Spec {
26554            type Ux = u32;
26555        }
26556        #[doc = "`read()` method returns [`in_sym_chn0_iv3::R`](R) reader structure"]
26557        impl crate::Readable for InSymChn0Iv3Spec {}
26558        #[doc = "`write(|w| ..)` method takes [`in_sym_chn0_iv3::W`](W) writer structure"]
26559        impl crate::Writable for InSymChn0Iv3Spec {
26560            type Safety = crate::Unsafe;
26561        }
26562        #[doc = "`reset()` method sets IN_SYM_CHN0_IV3 to value 0"]
26563        impl crate::Resettable for InSymChn0Iv3Spec {}
26564    }
26565    #[doc = "IN_SYM_CHN0_DATA0 (rw) register accessor: Sym channel 0 data word 0 (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_data0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_data0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_data0`] module"]
26566    #[doc(alias = "IN_SYM_CHN0_DATA0")]
26567    pub type InSymChn0Data0 = crate::Reg<in_sym_chn0_data0::InSymChn0Data0Spec>;
26568    #[doc = "Sym channel 0 data word 0 (register mode)"]
26569    pub mod in_sym_chn0_data0 {
26570        #[doc = "Register `IN_SYM_CHN0_DATA0` reader"]
26571        pub type R = crate::R<InSymChn0Data0Spec>;
26572        #[doc = "Register `IN_SYM_CHN0_DATA0` writer"]
26573        pub type W = crate::W<InSymChn0Data0Spec>;
26574        #[doc = "Field `data0` reader - Input data\\[31:0\\]"]
26575        pub type Data0R = crate::FieldReader<u32>;
26576        #[doc = "Field `data0` writer - Input data\\[31:0\\]"]
26577        pub type Data0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
26578        impl R {
26579            #[doc = "Bits 0:31 - Input data\\[31:0\\]"]
26580            #[inline(always)]
26581            pub fn data0(&self) -> Data0R {
26582                Data0R::new(self.bits)
26583            }
26584        }
26585        impl W {
26586            #[doc = "Bits 0:31 - Input data\\[31:0\\]"]
26587            #[inline(always)]
26588            pub fn data0(&mut self) -> Data0W<'_, InSymChn0Data0Spec> {
26589                Data0W::new(self, 0)
26590            }
26591        }
26592        #[doc = "Sym channel 0 data word 0 (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_data0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_data0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26593        pub struct InSymChn0Data0Spec;
26594        impl crate::RegisterSpec for InSymChn0Data0Spec {
26595            type Ux = u32;
26596        }
26597        #[doc = "`read()` method returns [`in_sym_chn0_data0::R`](R) reader structure"]
26598        impl crate::Readable for InSymChn0Data0Spec {}
26599        #[doc = "`write(|w| ..)` method takes [`in_sym_chn0_data0::W`](W) writer structure"]
26600        impl crate::Writable for InSymChn0Data0Spec {
26601            type Safety = crate::Unsafe;
26602        }
26603        #[doc = "`reset()` method sets IN_SYM_CHN0_DATA0 to value 0"]
26604        impl crate::Resettable for InSymChn0Data0Spec {}
26605    }
26606    #[doc = "SYM_CHANN_RAW_INT (rw) register accessor: Sym channel raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`sym_chann_raw_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sym_chann_raw_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sym_chann_raw_int`] module"]
26607    #[doc(alias = "SYM_CHANN_RAW_INT")]
26608    pub type SymChannRawInt = crate::Reg<sym_chann_raw_int::SymChannRawIntSpec>;
26609    #[doc = "Sym channel raw interrupt status"]
26610    pub mod sym_chann_raw_int {
26611        #[doc = "Register `SYM_CHANN_RAW_INT` reader"]
26612        pub type R = crate::R<SymChannRawIntSpec>;
26613        #[doc = "Register `SYM_CHANN_RAW_INT` writer"]
26614        pub type W = crate::W<SymChannRawIntSpec>;
26615        #[doc = "Field `sym_chann_raw_int` reader - Raw interrupt per channel \\[15:0\\]"]
26616        pub type SymChannRawIntR = crate::FieldReader<u16>;
26617        impl R {
26618            #[doc = "Bits 0:15 - Raw interrupt per channel \\[15:0\\]"]
26619            #[inline(always)]
26620            pub fn sym_chann_raw_int(&self) -> SymChannRawIntR {
26621                SymChannRawIntR::new((self.bits & 0xffff) as u16)
26622            }
26623        }
26624        impl W {}
26625        #[doc = "Sym channel raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`sym_chann_raw_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sym_chann_raw_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26626        pub struct SymChannRawIntSpec;
26627        impl crate::RegisterSpec for SymChannRawIntSpec {
26628            type Ux = u32;
26629        }
26630        #[doc = "`read()` method returns [`sym_chann_raw_int::R`](R) reader structure"]
26631        impl crate::Readable for SymChannRawIntSpec {}
26632        #[doc = "`write(|w| ..)` method takes [`sym_chann_raw_int::W`](W) writer structure"]
26633        impl crate::Writable for SymChannRawIntSpec {
26634            type Safety = crate::Unsafe;
26635        }
26636        #[doc = "`reset()` method sets SYM_CHANN_RAW_INT to value 0"]
26637        impl crate::Resettable for SymChannRawIntSpec {}
26638    }
26639}
26640#[doc = "Public Key Engine - modular arithmetic accelerator"]
26641pub type Pke = crate::Periph<pke::RegisterBlock, 0x4411_0000>;
26642impl core::fmt::Debug for Pke {
26643    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
26644        f.debug_struct("Pke").finish()
26645    }
26646}
26647#[doc = "Public Key Engine - modular arithmetic accelerator"]
26648pub mod pke {
26649    #[repr(C)]
26650    #[doc = "Register block"]
26651    pub struct RegisterBlock {
26652        pke_work_len: PkeWorkLen,
26653        pke_instr0: PkeInstr0,
26654        pke_instr1: PkeInstr1,
26655        pke_instr_addr_low: PkeInstrAddrLow,
26656        pke_instr_addr_hig: PkeInstrAddrHig,
26657        pke_instr_len: PkeInstrLen,
26658        pke_mask_rng_cfg: PkeMaskRngCfg,
26659        _reserved7: [u8; 0x04],
26660        pke_mont_para0: PkeMontPara0,
26661        pke_mont_para1: PkeMontPara1,
26662        _reserved9: [u8; 0x18],
26663        pke_start: PkeStart,
26664        pke_instr_rdy: PkeInstrRdy,
26665        pke_busy: PkeBusy,
26666        pke_noise_en: PkeNoiseEn,
26667        _reserved13: [u8; 0x30],
26668        pke_int_enable: PkeIntEnable,
26669        pke_int_nomask_status: PkeIntNomaskStatus,
26670        _reserved15: [u8; 0x04],
26671        pke_alarm_status: PkeAlarmStatus,
26672        pke_failure_flag: PkeFailureFlag,
26673        _reserved17: [u8; 0x2c],
26674        pke_dram_clr: PkeDramClr,
26675        _reserved18: [u8; 0x074c],
26676        pke_lock_ctrl: PkeLockCtrl,
26677        pke_lock_status: PkeLockStatus,
26678    }
26679    impl RegisterBlock {
26680        #[doc = "0x00 - PKE work length register"]
26681        #[inline(always)]
26682        pub const fn pke_work_len(&self) -> &PkeWorkLen {
26683            &self.pke_work_len
26684        }
26685        #[doc = "0x04 - PKE instruction register 0"]
26686        #[inline(always)]
26687        pub const fn pke_instr0(&self) -> &PkeInstr0 {
26688            &self.pke_instr0
26689        }
26690        #[doc = "0x08 - PKE instruction register 1"]
26691        #[inline(always)]
26692        pub const fn pke_instr1(&self) -> &PkeInstr1 {
26693            &self.pke_instr1
26694        }
26695        #[doc = "0x0c - PKE instruction start address low"]
26696        #[inline(always)]
26697        pub const fn pke_instr_addr_low(&self) -> &PkeInstrAddrLow {
26698            &self.pke_instr_addr_low
26699        }
26700        #[doc = "0x10 - PKE instruction start address high"]
26701        #[inline(always)]
26702        pub const fn pke_instr_addr_hig(&self) -> &PkeInstrAddrHig {
26703            &self.pke_instr_addr_hig
26704        }
26705        #[doc = "0x14 - PKE instruction length"]
26706        #[inline(always)]
26707        pub const fn pke_instr_len(&self) -> &PkeInstrLen {
26708            &self.pke_instr_len
26709        }
26710        #[doc = "0x18 - PKE mask RNG configuration"]
26711        #[inline(always)]
26712        pub const fn pke_mask_rng_cfg(&self) -> &PkeMaskRngCfg {
26713            &self.pke_mask_rng_cfg
26714        }
26715        #[doc = "0x20 - PKE Montgomery parameter 0"]
26716        #[inline(always)]
26717        pub const fn pke_mont_para0(&self) -> &PkeMontPara0 {
26718            &self.pke_mont_para0
26719        }
26720        #[doc = "0x24 - PKE Montgomery parameter 1"]
26721        #[inline(always)]
26722        pub const fn pke_mont_para1(&self) -> &PkeMontPara1 {
26723            &self.pke_mont_para1
26724        }
26725        #[doc = "0x40 - PKE start control register"]
26726        #[inline(always)]
26727        pub const fn pke_start(&self) -> &PkeStart {
26728            &self.pke_start
26729        }
26730        #[doc = "0x44 - PKE instruction ready status"]
26731        #[inline(always)]
26732        pub const fn pke_instr_rdy(&self) -> &PkeInstrRdy {
26733            &self.pke_instr_rdy
26734        }
26735        #[doc = "0x48 - PKE busy status register"]
26736        #[inline(always)]
26737        pub const fn pke_busy(&self) -> &PkeBusy {
26738            &self.pke_busy
26739        }
26740        #[doc = "0x4c - PKE noise enable register"]
26741        #[inline(always)]
26742        pub const fn pke_noise_en(&self) -> &PkeNoiseEn {
26743            &self.pke_noise_en
26744        }
26745        #[doc = "0x80 - PKE interrupt enable"]
26746        #[inline(always)]
26747        pub const fn pke_int_enable(&self) -> &PkeIntEnable {
26748            &self.pke_int_enable
26749        }
26750        #[doc = "0x84 - PKE unmasked interrupt status"]
26751        #[inline(always)]
26752        pub const fn pke_int_nomask_status(&self) -> &PkeIntNomaskStatus {
26753            &self.pke_int_nomask_status
26754        }
26755        #[doc = "0x8c - PKE alarm status register"]
26756        #[inline(always)]
26757        pub const fn pke_alarm_status(&self) -> &PkeAlarmStatus {
26758            &self.pke_alarm_status
26759        }
26760        #[doc = "0x90 - PKE failure flag register"]
26761        #[inline(always)]
26762        pub const fn pke_failure_flag(&self) -> &PkeFailureFlag {
26763            &self.pke_failure_flag
26764        }
26765        #[doc = "0xc0 - PKE DRAM clear register"]
26766        #[inline(always)]
26767        pub const fn pke_dram_clr(&self) -> &PkeDramClr {
26768            &self.pke_dram_clr
26769        }
26770        #[doc = "0x810 - PKE lock control register"]
26771        #[inline(always)]
26772        pub const fn pke_lock_ctrl(&self) -> &PkeLockCtrl {
26773            &self.pke_lock_ctrl
26774        }
26775        #[doc = "0x814 - PKE lock status register"]
26776        #[inline(always)]
26777        pub const fn pke_lock_status(&self) -> &PkeLockStatus {
26778            &self.pke_lock_status
26779        }
26780    }
26781    #[doc = "PKE_WORK_LEN (rw) register accessor: PKE work length register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_work_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_work_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_work_len`] module"]
26782    #[doc(alias = "PKE_WORK_LEN")]
26783    pub type PkeWorkLen = crate::Reg<pke_work_len::PkeWorkLenSpec>;
26784    #[doc = "PKE work length register"]
26785    pub mod pke_work_len {
26786        #[doc = "Register `PKE_WORK_LEN` reader"]
26787        pub type R = crate::R<PkeWorkLenSpec>;
26788        #[doc = "Register `PKE_WORK_LEN` writer"]
26789        pub type W = crate::W<PkeWorkLenSpec>;
26790        #[doc = "Field `work_len` reader - Operand bit length for modular arithmetic"]
26791        pub type WorkLenR = crate::FieldReader<u32>;
26792        #[doc = "Field `work_len` writer - Operand bit length for modular arithmetic"]
26793        pub type WorkLenW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
26794        impl R {
26795            #[doc = "Bits 0:31 - Operand bit length for modular arithmetic"]
26796            #[inline(always)]
26797            pub fn work_len(&self) -> WorkLenR {
26798                WorkLenR::new(self.bits)
26799            }
26800        }
26801        impl W {
26802            #[doc = "Bits 0:31 - Operand bit length for modular arithmetic"]
26803            #[inline(always)]
26804            pub fn work_len(&mut self) -> WorkLenW<'_, PkeWorkLenSpec> {
26805                WorkLenW::new(self, 0)
26806            }
26807        }
26808        #[doc = "PKE work length register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_work_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_work_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26809        pub struct PkeWorkLenSpec;
26810        impl crate::RegisterSpec for PkeWorkLenSpec {
26811            type Ux = u32;
26812        }
26813        #[doc = "`read()` method returns [`pke_work_len::R`](R) reader structure"]
26814        impl crate::Readable for PkeWorkLenSpec {}
26815        #[doc = "`write(|w| ..)` method takes [`pke_work_len::W`](W) writer structure"]
26816        impl crate::Writable for PkeWorkLenSpec {
26817            type Safety = crate::Unsafe;
26818        }
26819        #[doc = "`reset()` method sets PKE_WORK_LEN to value 0"]
26820        impl crate::Resettable for PkeWorkLenSpec {}
26821    }
26822    #[doc = "PKE_INSTR0 (rw) register accessor: PKE instruction register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr0`] module"]
26823    #[doc(alias = "PKE_INSTR0")]
26824    pub type PkeInstr0 = crate::Reg<pke_instr0::PkeInstr0Spec>;
26825    #[doc = "PKE instruction register 0"]
26826    pub mod pke_instr0 {
26827        #[doc = "Register `PKE_INSTR0` reader"]
26828        pub type R = crate::R<PkeInstr0Spec>;
26829        #[doc = "Register `PKE_INSTR0` writer"]
26830        pub type W = crate::W<PkeInstr0Spec>;
26831        #[doc = "Instruction code 0 (0=MUL_MOD, 1=ADD_MOD, 2=SUB_MOD)\n\nValue on reset: 0"]
26832        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
26833        #[repr(u32)]
26834        pub enum Instr0 {
26835            #[doc = "0: Modular multiplication"]
26836            MulMod = 0,
26837            #[doc = "1: Modular addition"]
26838            AddMod = 1,
26839            #[doc = "2: Modular subtraction"]
26840            SubMod = 2,
26841        }
26842        impl From<Instr0> for u32 {
26843            #[inline(always)]
26844            fn from(variant: Instr0) -> Self {
26845                variant as _
26846            }
26847        }
26848        impl crate::FieldSpec for Instr0 {
26849            type Ux = u32;
26850        }
26851        impl crate::IsEnum for Instr0 {}
26852        #[doc = "Field `instr0` reader - Instruction code 0 (0=MUL_MOD, 1=ADD_MOD, 2=SUB_MOD)"]
26853        pub type Instr0R = crate::FieldReader<Instr0>;
26854        impl Instr0R {
26855            #[doc = "Get enumerated values variant"]
26856            #[inline(always)]
26857            pub const fn variant(&self) -> Option<Instr0> {
26858                match self.bits {
26859                    0 => Some(Instr0::MulMod),
26860                    1 => Some(Instr0::AddMod),
26861                    2 => Some(Instr0::SubMod),
26862                    _ => None,
26863                }
26864            }
26865            #[doc = "Modular multiplication"]
26866            #[inline(always)]
26867            pub fn is_mul_mod(&self) -> bool {
26868                *self == Instr0::MulMod
26869            }
26870            #[doc = "Modular addition"]
26871            #[inline(always)]
26872            pub fn is_add_mod(&self) -> bool {
26873                *self == Instr0::AddMod
26874            }
26875            #[doc = "Modular subtraction"]
26876            #[inline(always)]
26877            pub fn is_sub_mod(&self) -> bool {
26878                *self == Instr0::SubMod
26879            }
26880        }
26881        #[doc = "Field `instr0` writer - Instruction code 0 (0=MUL_MOD, 1=ADD_MOD, 2=SUB_MOD)"]
26882        pub type Instr0W<'a, REG> = crate::FieldWriter<'a, REG, 32, Instr0>;
26883        impl<'a, REG> Instr0W<'a, REG>
26884        where
26885            REG: crate::Writable + crate::RegisterSpec,
26886            REG::Ux: From<u32>,
26887        {
26888            #[doc = "Modular multiplication"]
26889            #[inline(always)]
26890            pub fn mul_mod(self) -> &'a mut crate::W<REG> {
26891                self.variant(Instr0::MulMod)
26892            }
26893            #[doc = "Modular addition"]
26894            #[inline(always)]
26895            pub fn add_mod(self) -> &'a mut crate::W<REG> {
26896                self.variant(Instr0::AddMod)
26897            }
26898            #[doc = "Modular subtraction"]
26899            #[inline(always)]
26900            pub fn sub_mod(self) -> &'a mut crate::W<REG> {
26901                self.variant(Instr0::SubMod)
26902            }
26903        }
26904        impl R {
26905            #[doc = "Bits 0:31 - Instruction code 0 (0=MUL_MOD, 1=ADD_MOD, 2=SUB_MOD)"]
26906            #[inline(always)]
26907            pub fn instr0(&self) -> Instr0R {
26908                Instr0R::new(self.bits)
26909            }
26910        }
26911        impl W {
26912            #[doc = "Bits 0:31 - Instruction code 0 (0=MUL_MOD, 1=ADD_MOD, 2=SUB_MOD)"]
26913            #[inline(always)]
26914            pub fn instr0(&mut self) -> Instr0W<'_, PkeInstr0Spec> {
26915                Instr0W::new(self, 0)
26916            }
26917        }
26918        #[doc = "PKE instruction register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26919        pub struct PkeInstr0Spec;
26920        impl crate::RegisterSpec for PkeInstr0Spec {
26921            type Ux = u32;
26922        }
26923        #[doc = "`read()` method returns [`pke_instr0::R`](R) reader structure"]
26924        impl crate::Readable for PkeInstr0Spec {}
26925        #[doc = "`write(|w| ..)` method takes [`pke_instr0::W`](W) writer structure"]
26926        impl crate::Writable for PkeInstr0Spec {
26927            type Safety = crate::Unsafe;
26928        }
26929        #[doc = "`reset()` method sets PKE_INSTR0 to value 0"]
26930        impl crate::Resettable for PkeInstr0Spec {}
26931    }
26932    #[doc = "PKE_INSTR1 (rw) register accessor: PKE instruction register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr1`] module"]
26933    #[doc(alias = "PKE_INSTR1")]
26934    pub type PkeInstr1 = crate::Reg<pke_instr1::PkeInstr1Spec>;
26935    #[doc = "PKE instruction register 1"]
26936    pub mod pke_instr1 {
26937        #[doc = "Register `PKE_INSTR1` reader"]
26938        pub type R = crate::R<PkeInstr1Spec>;
26939        #[doc = "Register `PKE_INSTR1` writer"]
26940        pub type W = crate::W<PkeInstr1Spec>;
26941        #[doc = "Field `instr1` reader - Instruction code 1"]
26942        pub type Instr1R = crate::FieldReader<u32>;
26943        #[doc = "Field `instr1` writer - Instruction code 1"]
26944        pub type Instr1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
26945        impl R {
26946            #[doc = "Bits 0:31 - Instruction code 1"]
26947            #[inline(always)]
26948            pub fn instr1(&self) -> Instr1R {
26949                Instr1R::new(self.bits)
26950            }
26951        }
26952        impl W {
26953            #[doc = "Bits 0:31 - Instruction code 1"]
26954            #[inline(always)]
26955            pub fn instr1(&mut self) -> Instr1W<'_, PkeInstr1Spec> {
26956                Instr1W::new(self, 0)
26957            }
26958        }
26959        #[doc = "PKE instruction register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26960        pub struct PkeInstr1Spec;
26961        impl crate::RegisterSpec for PkeInstr1Spec {
26962            type Ux = u32;
26963        }
26964        #[doc = "`read()` method returns [`pke_instr1::R`](R) reader structure"]
26965        impl crate::Readable for PkeInstr1Spec {}
26966        #[doc = "`write(|w| ..)` method takes [`pke_instr1::W`](W) writer structure"]
26967        impl crate::Writable for PkeInstr1Spec {
26968            type Safety = crate::Unsafe;
26969        }
26970        #[doc = "`reset()` method sets PKE_INSTR1 to value 0"]
26971        impl crate::Resettable for PkeInstr1Spec {}
26972    }
26973    #[doc = "PKE_INSTR_ADDR_LOW (rw) register accessor: PKE instruction start address low\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_addr_low::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_addr_low::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr_addr_low`] module"]
26974    #[doc(alias = "PKE_INSTR_ADDR_LOW")]
26975    pub type PkeInstrAddrLow = crate::Reg<pke_instr_addr_low::PkeInstrAddrLowSpec>;
26976    #[doc = "PKE instruction start address low"]
26977    pub mod pke_instr_addr_low {
26978        #[doc = "Register `PKE_INSTR_ADDR_LOW` reader"]
26979        pub type R = crate::R<PkeInstrAddrLowSpec>;
26980        #[doc = "Register `PKE_INSTR_ADDR_LOW` writer"]
26981        pub type W = crate::W<PkeInstrAddrLowSpec>;
26982        #[doc = "Field `instr_addr_low` reader - Instruction start address \\[31:0\\]"]
26983        pub type InstrAddrLowR = crate::FieldReader<u32>;
26984        #[doc = "Field `instr_addr_low` writer - Instruction start address \\[31:0\\]"]
26985        pub type InstrAddrLowW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
26986        impl R {
26987            #[doc = "Bits 0:31 - Instruction start address \\[31:0\\]"]
26988            #[inline(always)]
26989            pub fn instr_addr_low(&self) -> InstrAddrLowR {
26990                InstrAddrLowR::new(self.bits)
26991            }
26992        }
26993        impl W {
26994            #[doc = "Bits 0:31 - Instruction start address \\[31:0\\]"]
26995            #[inline(always)]
26996            pub fn instr_addr_low(&mut self) -> InstrAddrLowW<'_, PkeInstrAddrLowSpec> {
26997                InstrAddrLowW::new(self, 0)
26998            }
26999        }
27000        #[doc = "PKE instruction start address low\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_addr_low::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_addr_low::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27001        pub struct PkeInstrAddrLowSpec;
27002        impl crate::RegisterSpec for PkeInstrAddrLowSpec {
27003            type Ux = u32;
27004        }
27005        #[doc = "`read()` method returns [`pke_instr_addr_low::R`](R) reader structure"]
27006        impl crate::Readable for PkeInstrAddrLowSpec {}
27007        #[doc = "`write(|w| ..)` method takes [`pke_instr_addr_low::W`](W) writer structure"]
27008        impl crate::Writable for PkeInstrAddrLowSpec {
27009            type Safety = crate::Unsafe;
27010        }
27011        #[doc = "`reset()` method sets PKE_INSTR_ADDR_LOW to value 0"]
27012        impl crate::Resettable for PkeInstrAddrLowSpec {}
27013    }
27014    #[doc = "PKE_INSTR_ADDR_HIG (rw) register accessor: PKE instruction start address high\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_addr_hig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_addr_hig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr_addr_hig`] module"]
27015    #[doc(alias = "PKE_INSTR_ADDR_HIG")]
27016    pub type PkeInstrAddrHig = crate::Reg<pke_instr_addr_hig::PkeInstrAddrHigSpec>;
27017    #[doc = "PKE instruction start address high"]
27018    pub mod pke_instr_addr_hig {
27019        #[doc = "Register `PKE_INSTR_ADDR_HIG` reader"]
27020        pub type R = crate::R<PkeInstrAddrHigSpec>;
27021        #[doc = "Register `PKE_INSTR_ADDR_HIG` writer"]
27022        pub type W = crate::W<PkeInstrAddrHigSpec>;
27023        #[doc = "Field `instr_addr_hig` reader - Instruction start address high bits"]
27024        pub type InstrAddrHigR = crate::FieldReader<u32>;
27025        #[doc = "Field `instr_addr_hig` writer - Instruction start address high bits"]
27026        pub type InstrAddrHigW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
27027        impl R {
27028            #[doc = "Bits 0:31 - Instruction start address high bits"]
27029            #[inline(always)]
27030            pub fn instr_addr_hig(&self) -> InstrAddrHigR {
27031                InstrAddrHigR::new(self.bits)
27032            }
27033        }
27034        impl W {
27035            #[doc = "Bits 0:31 - Instruction start address high bits"]
27036            #[inline(always)]
27037            pub fn instr_addr_hig(&mut self) -> InstrAddrHigW<'_, PkeInstrAddrHigSpec> {
27038                InstrAddrHigW::new(self, 0)
27039            }
27040        }
27041        #[doc = "PKE instruction start address high\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_addr_hig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_addr_hig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27042        pub struct PkeInstrAddrHigSpec;
27043        impl crate::RegisterSpec for PkeInstrAddrHigSpec {
27044            type Ux = u32;
27045        }
27046        #[doc = "`read()` method returns [`pke_instr_addr_hig::R`](R) reader structure"]
27047        impl crate::Readable for PkeInstrAddrHigSpec {}
27048        #[doc = "`write(|w| ..)` method takes [`pke_instr_addr_hig::W`](W) writer structure"]
27049        impl crate::Writable for PkeInstrAddrHigSpec {
27050            type Safety = crate::Unsafe;
27051        }
27052        #[doc = "`reset()` method sets PKE_INSTR_ADDR_HIG to value 0"]
27053        impl crate::Resettable for PkeInstrAddrHigSpec {}
27054    }
27055    #[doc = "PKE_INSTR_LEN (rw) register accessor: PKE instruction length\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr_len`] module"]
27056    #[doc(alias = "PKE_INSTR_LEN")]
27057    pub type PkeInstrLen = crate::Reg<pke_instr_len::PkeInstrLenSpec>;
27058    #[doc = "PKE instruction length"]
27059    pub mod pke_instr_len {
27060        #[doc = "Register `PKE_INSTR_LEN` reader"]
27061        pub type R = crate::R<PkeInstrLenSpec>;
27062        #[doc = "Register `PKE_INSTR_LEN` writer"]
27063        pub type W = crate::W<PkeInstrLenSpec>;
27064        #[doc = "Field `instr_len` reader - Total instruction length in bytes"]
27065        pub type InstrLenR = crate::FieldReader<u32>;
27066        #[doc = "Field `instr_len` writer - Total instruction length in bytes"]
27067        pub type InstrLenW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
27068        impl R {
27069            #[doc = "Bits 0:31 - Total instruction length in bytes"]
27070            #[inline(always)]
27071            pub fn instr_len(&self) -> InstrLenR {
27072                InstrLenR::new(self.bits)
27073            }
27074        }
27075        impl W {
27076            #[doc = "Bits 0:31 - Total instruction length in bytes"]
27077            #[inline(always)]
27078            pub fn instr_len(&mut self) -> InstrLenW<'_, PkeInstrLenSpec> {
27079                InstrLenW::new(self, 0)
27080            }
27081        }
27082        #[doc = "PKE instruction length\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27083        pub struct PkeInstrLenSpec;
27084        impl crate::RegisterSpec for PkeInstrLenSpec {
27085            type Ux = u32;
27086        }
27087        #[doc = "`read()` method returns [`pke_instr_len::R`](R) reader structure"]
27088        impl crate::Readable for PkeInstrLenSpec {}
27089        #[doc = "`write(|w| ..)` method takes [`pke_instr_len::W`](W) writer structure"]
27090        impl crate::Writable for PkeInstrLenSpec {
27091            type Safety = crate::Unsafe;
27092        }
27093        #[doc = "`reset()` method sets PKE_INSTR_LEN to value 0"]
27094        impl crate::Resettable for PkeInstrLenSpec {}
27095    }
27096    #[doc = "PKE_MASK_RNG_CFG (rw) register accessor: PKE mask RNG configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mask_rng_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mask_rng_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_mask_rng_cfg`] module"]
27097    #[doc(alias = "PKE_MASK_RNG_CFG")]
27098    pub type PkeMaskRngCfg = crate::Reg<pke_mask_rng_cfg::PkeMaskRngCfgSpec>;
27099    #[doc = "PKE mask RNG configuration"]
27100    pub mod pke_mask_rng_cfg {
27101        #[doc = "Register `PKE_MASK_RNG_CFG` reader"]
27102        pub type R = crate::R<PkeMaskRngCfgSpec>;
27103        #[doc = "Register `PKE_MASK_RNG_CFG` writer"]
27104        pub type W = crate::W<PkeMaskRngCfgSpec>;
27105        #[doc = "Field `mask_rng_cfg` reader - Mask RNG enable: 0=disabled; 1=enabled"]
27106        pub type MaskRngCfgR = crate::BitReader;
27107        #[doc = "Field `mask_rng_cfg` writer - Mask RNG enable: 0=disabled; 1=enabled"]
27108        pub type MaskRngCfgW<'a, REG> = crate::BitWriter<'a, REG>;
27109        impl R {
27110            #[doc = "Bit 0 - Mask RNG enable: 0=disabled; 1=enabled"]
27111            #[inline(always)]
27112            pub fn mask_rng_cfg(&self) -> MaskRngCfgR {
27113                MaskRngCfgR::new((self.bits & 1) != 0)
27114            }
27115        }
27116        impl W {
27117            #[doc = "Bit 0 - Mask RNG enable: 0=disabled; 1=enabled"]
27118            #[inline(always)]
27119            pub fn mask_rng_cfg(&mut self) -> MaskRngCfgW<'_, PkeMaskRngCfgSpec> {
27120                MaskRngCfgW::new(self, 0)
27121            }
27122        }
27123        #[doc = "PKE mask RNG configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mask_rng_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mask_rng_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27124        pub struct PkeMaskRngCfgSpec;
27125        impl crate::RegisterSpec for PkeMaskRngCfgSpec {
27126            type Ux = u32;
27127        }
27128        #[doc = "`read()` method returns [`pke_mask_rng_cfg::R`](R) reader structure"]
27129        impl crate::Readable for PkeMaskRngCfgSpec {}
27130        #[doc = "`write(|w| ..)` method takes [`pke_mask_rng_cfg::W`](W) writer structure"]
27131        impl crate::Writable for PkeMaskRngCfgSpec {
27132            type Safety = crate::Unsafe;
27133        }
27134        #[doc = "`reset()` method sets PKE_MASK_RNG_CFG to value 0"]
27135        impl crate::Resettable for PkeMaskRngCfgSpec {}
27136    }
27137    #[doc = "PKE_MONT_PARA0 (rw) register accessor: PKE Montgomery parameter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mont_para0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mont_para0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_mont_para0`] module"]
27138    #[doc(alias = "PKE_MONT_PARA0")]
27139    pub type PkeMontPara0 = crate::Reg<pke_mont_para0::PkeMontPara0Spec>;
27140    #[doc = "PKE Montgomery parameter 0"]
27141    pub mod pke_mont_para0 {
27142        #[doc = "Register `PKE_MONT_PARA0` reader"]
27143        pub type R = crate::R<PkeMontPara0Spec>;
27144        #[doc = "Register `PKE_MONT_PARA0` writer"]
27145        pub type W = crate::W<PkeMontPara0Spec>;
27146        #[doc = "Field `mont_para0` reader - Montgomery pre-computed parameter word 0"]
27147        pub type MontPara0R = crate::FieldReader<u32>;
27148        #[doc = "Field `mont_para0` writer - Montgomery pre-computed parameter word 0"]
27149        pub type MontPara0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
27150        impl R {
27151            #[doc = "Bits 0:31 - Montgomery pre-computed parameter word 0"]
27152            #[inline(always)]
27153            pub fn mont_para0(&self) -> MontPara0R {
27154                MontPara0R::new(self.bits)
27155            }
27156        }
27157        impl W {
27158            #[doc = "Bits 0:31 - Montgomery pre-computed parameter word 0"]
27159            #[inline(always)]
27160            pub fn mont_para0(&mut self) -> MontPara0W<'_, PkeMontPara0Spec> {
27161                MontPara0W::new(self, 0)
27162            }
27163        }
27164        #[doc = "PKE Montgomery parameter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mont_para0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mont_para0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27165        pub struct PkeMontPara0Spec;
27166        impl crate::RegisterSpec for PkeMontPara0Spec {
27167            type Ux = u32;
27168        }
27169        #[doc = "`read()` method returns [`pke_mont_para0::R`](R) reader structure"]
27170        impl crate::Readable for PkeMontPara0Spec {}
27171        #[doc = "`write(|w| ..)` method takes [`pke_mont_para0::W`](W) writer structure"]
27172        impl crate::Writable for PkeMontPara0Spec {
27173            type Safety = crate::Unsafe;
27174        }
27175        #[doc = "`reset()` method sets PKE_MONT_PARA0 to value 0"]
27176        impl crate::Resettable for PkeMontPara0Spec {}
27177    }
27178    #[doc = "PKE_MONT_PARA1 (rw) register accessor: PKE Montgomery parameter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mont_para1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mont_para1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_mont_para1`] module"]
27179    #[doc(alias = "PKE_MONT_PARA1")]
27180    pub type PkeMontPara1 = crate::Reg<pke_mont_para1::PkeMontPara1Spec>;
27181    #[doc = "PKE Montgomery parameter 1"]
27182    pub mod pke_mont_para1 {
27183        #[doc = "Register `PKE_MONT_PARA1` reader"]
27184        pub type R = crate::R<PkeMontPara1Spec>;
27185        #[doc = "Register `PKE_MONT_PARA1` writer"]
27186        pub type W = crate::W<PkeMontPara1Spec>;
27187        #[doc = "Field `mont_para1` reader - Montgomery pre-computed parameter word 1"]
27188        pub type MontPara1R = crate::FieldReader<u32>;
27189        #[doc = "Field `mont_para1` writer - Montgomery pre-computed parameter word 1"]
27190        pub type MontPara1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
27191        impl R {
27192            #[doc = "Bits 0:31 - Montgomery pre-computed parameter word 1"]
27193            #[inline(always)]
27194            pub fn mont_para1(&self) -> MontPara1R {
27195                MontPara1R::new(self.bits)
27196            }
27197        }
27198        impl W {
27199            #[doc = "Bits 0:31 - Montgomery pre-computed parameter word 1"]
27200            #[inline(always)]
27201            pub fn mont_para1(&mut self) -> MontPara1W<'_, PkeMontPara1Spec> {
27202                MontPara1W::new(self, 0)
27203            }
27204        }
27205        #[doc = "PKE Montgomery parameter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mont_para1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mont_para1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27206        pub struct PkeMontPara1Spec;
27207        impl crate::RegisterSpec for PkeMontPara1Spec {
27208            type Ux = u32;
27209        }
27210        #[doc = "`read()` method returns [`pke_mont_para1::R`](R) reader structure"]
27211        impl crate::Readable for PkeMontPara1Spec {}
27212        #[doc = "`write(|w| ..)` method takes [`pke_mont_para1::W`](W) writer structure"]
27213        impl crate::Writable for PkeMontPara1Spec {
27214            type Safety = crate::Unsafe;
27215        }
27216        #[doc = "`reset()` method sets PKE_MONT_PARA1 to value 0"]
27217        impl crate::Resettable for PkeMontPara1Spec {}
27218    }
27219    #[doc = "PKE_START (rw) register accessor: PKE start control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_start`] module"]
27220    #[doc(alias = "PKE_START")]
27221    pub type PkeStart = crate::Reg<pke_start::PkeStartSpec>;
27222    #[doc = "PKE start control register"]
27223    pub mod pke_start {
27224        #[doc = "Register `PKE_START` reader"]
27225        pub type R = crate::R<PkeStartSpec>;
27226        #[doc = "Register `PKE_START` writer"]
27227        pub type W = crate::W<PkeStartSpec>;
27228        #[doc = "Start code 0 (write 0x5 to start)\n\nValue on reset: 0"]
27229        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
27230        #[repr(u8)]
27231        pub enum PkeStart0 {
27232            #[doc = "5: Must write 0x5 to start PKE operation"]
27233            StartCode = 5,
27234        }
27235        impl From<PkeStart0> for u8 {
27236            #[inline(always)]
27237            fn from(variant: PkeStart0) -> Self {
27238                variant as _
27239            }
27240        }
27241        impl crate::FieldSpec for PkeStart0 {
27242            type Ux = u8;
27243        }
27244        impl crate::IsEnum for PkeStart0 {}
27245        #[doc = "Field `pke_start0` writer - Start code 0 (write 0x5 to start)"]
27246        pub type PkeStart0W<'a, REG> = crate::FieldWriter<'a, REG, 4, PkeStart0>;
27247        impl<'a, REG> PkeStart0W<'a, REG>
27248        where
27249            REG: crate::Writable + crate::RegisterSpec,
27250            REG::Ux: From<u8>,
27251        {
27252            #[doc = "Must write 0x5 to start PKE operation"]
27253            #[inline(always)]
27254            pub fn start_code(self) -> &'a mut crate::W<REG> {
27255                self.variant(PkeStart0::StartCode)
27256            }
27257        }
27258        #[doc = "Start code 1 (write 0xA)\n\nValue on reset: 0"]
27259        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
27260        #[repr(u8)]
27261        pub enum PkeStart1 {
27262            #[doc = "10: Must write 0xA to start PKE operation"]
27263            StartCode = 10,
27264        }
27265        impl From<PkeStart1> for u8 {
27266            #[inline(always)]
27267            fn from(variant: PkeStart1) -> Self {
27268                variant as _
27269            }
27270        }
27271        impl crate::FieldSpec for PkeStart1 {
27272            type Ux = u8;
27273        }
27274        impl crate::IsEnum for PkeStart1 {}
27275        #[doc = "Field `pke_start1` writer - Start code 1 (write 0xA)"]
27276        pub type PkeStart1W<'a, REG> = crate::FieldWriter<'a, REG, 4, PkeStart1>;
27277        impl<'a, REG> PkeStart1W<'a, REG>
27278        where
27279            REG: crate::Writable + crate::RegisterSpec,
27280            REG::Ux: From<u8>,
27281        {
27282            #[doc = "Must write 0xA to start PKE operation"]
27283            #[inline(always)]
27284            pub fn start_code(self) -> &'a mut crate::W<REG> {
27285                self.variant(PkeStart1::StartCode)
27286            }
27287        }
27288        #[doc = "Field `pke_batch_start` writer - Batch start code (write 0x5)"]
27289        pub type PkeBatchStartW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
27290        impl W {
27291            #[doc = "Bits 0:3 - Start code 0 (write 0x5 to start)"]
27292            #[inline(always)]
27293            pub fn pke_start0(&mut self) -> PkeStart0W<'_, PkeStartSpec> {
27294                PkeStart0W::new(self, 0)
27295            }
27296            #[doc = "Bits 4:7 - Start code 1 (write 0xA)"]
27297            #[inline(always)]
27298            pub fn pke_start1(&mut self) -> PkeStart1W<'_, PkeStartSpec> {
27299                PkeStart1W::new(self, 4)
27300            }
27301            #[doc = "Bits 8:11 - Batch start code (write 0x5)"]
27302            #[inline(always)]
27303            pub fn pke_batch_start(&mut self) -> PkeBatchStartW<'_, PkeStartSpec> {
27304                PkeBatchStartW::new(self, 8)
27305            }
27306        }
27307        #[doc = "PKE start control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27308        pub struct PkeStartSpec;
27309        impl crate::RegisterSpec for PkeStartSpec {
27310            type Ux = u32;
27311        }
27312        #[doc = "`read()` method returns [`pke_start::R`](R) reader structure"]
27313        impl crate::Readable for PkeStartSpec {}
27314        #[doc = "`write(|w| ..)` method takes [`pke_start::W`](W) writer structure"]
27315        impl crate::Writable for PkeStartSpec {
27316            type Safety = crate::Unsafe;
27317        }
27318        #[doc = "`reset()` method sets PKE_START to value 0"]
27319        impl crate::Resettable for PkeStartSpec {}
27320    }
27321    #[doc = "PKE_INSTR_RDY (rw) register accessor: PKE instruction ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_rdy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_rdy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr_rdy`] module"]
27322    #[doc(alias = "PKE_INSTR_RDY")]
27323    pub type PkeInstrRdy = crate::Reg<pke_instr_rdy::PkeInstrRdySpec>;
27324    #[doc = "PKE instruction ready status"]
27325    pub mod pke_instr_rdy {
27326        #[doc = "Register `PKE_INSTR_RDY` reader"]
27327        pub type R = crate::R<PkeInstrRdySpec>;
27328        #[doc = "Register `PKE_INSTR_RDY` writer"]
27329        pub type W = crate::W<PkeInstrRdySpec>;
27330        #[doc = "Field `instr0_rdy` reader - Instruction buffer 0 ready"]
27331        pub type Instr0RdyR = crate::BitReader;
27332        #[doc = "Field `instr1_rdy` reader - Instruction buffer 1 ready"]
27333        pub type Instr1RdyR = crate::BitReader;
27334        #[doc = "Field `batch_instr_rdy` reader - Batch instruction ready"]
27335        pub type BatchInstrRdyR = crate::BitReader;
27336        impl R {
27337            #[doc = "Bit 0 - Instruction buffer 0 ready"]
27338            #[inline(always)]
27339            pub fn instr0_rdy(&self) -> Instr0RdyR {
27340                Instr0RdyR::new((self.bits & 1) != 0)
27341            }
27342            #[doc = "Bit 1 - Instruction buffer 1 ready"]
27343            #[inline(always)]
27344            pub fn instr1_rdy(&self) -> Instr1RdyR {
27345                Instr1RdyR::new(((self.bits >> 1) & 1) != 0)
27346            }
27347            #[doc = "Bit 2 - Batch instruction ready"]
27348            #[inline(always)]
27349            pub fn batch_instr_rdy(&self) -> BatchInstrRdyR {
27350                BatchInstrRdyR::new(((self.bits >> 2) & 1) != 0)
27351            }
27352        }
27353        impl W {}
27354        #[doc = "PKE instruction ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_rdy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_rdy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27355        pub struct PkeInstrRdySpec;
27356        impl crate::RegisterSpec for PkeInstrRdySpec {
27357            type Ux = u32;
27358        }
27359        #[doc = "`read()` method returns [`pke_instr_rdy::R`](R) reader structure"]
27360        impl crate::Readable for PkeInstrRdySpec {}
27361        #[doc = "`write(|w| ..)` method takes [`pke_instr_rdy::W`](W) writer structure"]
27362        impl crate::Writable for PkeInstrRdySpec {
27363            type Safety = crate::Unsafe;
27364        }
27365        #[doc = "`reset()` method sets PKE_INSTR_RDY to value 0"]
27366        impl crate::Resettable for PkeInstrRdySpec {}
27367    }
27368    #[doc = "PKE_BUSY (rw) register accessor: PKE busy status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_busy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_busy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_busy`] module"]
27369    #[doc(alias = "PKE_BUSY")]
27370    pub type PkeBusy = crate::Reg<pke_busy::PkeBusySpec>;
27371    #[doc = "PKE busy status register"]
27372    pub mod pke_busy {
27373        #[doc = "Register `PKE_BUSY` reader"]
27374        pub type R = crate::R<PkeBusySpec>;
27375        #[doc = "Register `PKE_BUSY` writer"]
27376        pub type W = crate::W<PkeBusySpec>;
27377        #[doc = "Field `pke_busy` reader - PKE busy: 0=idle; 1=busy"]
27378        pub type PkeBusyR = crate::BitReader;
27379        impl R {
27380            #[doc = "Bit 0 - PKE busy: 0=idle; 1=busy"]
27381            #[inline(always)]
27382            pub fn pke_busy(&self) -> PkeBusyR {
27383                PkeBusyR::new((self.bits & 1) != 0)
27384            }
27385        }
27386        impl W {}
27387        #[doc = "PKE busy status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_busy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_busy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27388        pub struct PkeBusySpec;
27389        impl crate::RegisterSpec for PkeBusySpec {
27390            type Ux = u32;
27391        }
27392        #[doc = "`read()` method returns [`pke_busy::R`](R) reader structure"]
27393        impl crate::Readable for PkeBusySpec {}
27394        #[doc = "`write(|w| ..)` method takes [`pke_busy::W`](W) writer structure"]
27395        impl crate::Writable for PkeBusySpec {
27396            type Safety = crate::Unsafe;
27397        }
27398        #[doc = "`reset()` method sets PKE_BUSY to value 0"]
27399        impl crate::Resettable for PkeBusySpec {}
27400    }
27401    #[doc = "PKE_NOISE_EN (rw) register accessor: PKE noise enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_noise_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_noise_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_noise_en`] module"]
27402    #[doc(alias = "PKE_NOISE_EN")]
27403    pub type PkeNoiseEn = crate::Reg<pke_noise_en::PkeNoiseEnSpec>;
27404    #[doc = "PKE noise enable register"]
27405    pub mod pke_noise_en {
27406        #[doc = "Register `PKE_NOISE_EN` reader"]
27407        pub type R = crate::R<PkeNoiseEnSpec>;
27408        #[doc = "Register `PKE_NOISE_EN` writer"]
27409        pub type W = crate::W<PkeNoiseEnSpec>;
27410        #[doc = "Field `noise_en` reader - Side-channel noise enable"]
27411        pub type NoiseEnR = crate::BitReader;
27412        #[doc = "Field `noise_en` writer - Side-channel noise enable"]
27413        pub type NoiseEnW<'a, REG> = crate::BitWriter<'a, REG>;
27414        impl R {
27415            #[doc = "Bit 0 - Side-channel noise enable"]
27416            #[inline(always)]
27417            pub fn noise_en(&self) -> NoiseEnR {
27418                NoiseEnR::new((self.bits & 1) != 0)
27419            }
27420        }
27421        impl W {
27422            #[doc = "Bit 0 - Side-channel noise enable"]
27423            #[inline(always)]
27424            pub fn noise_en(&mut self) -> NoiseEnW<'_, PkeNoiseEnSpec> {
27425                NoiseEnW::new(self, 0)
27426            }
27427        }
27428        #[doc = "PKE noise enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_noise_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_noise_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27429        pub struct PkeNoiseEnSpec;
27430        impl crate::RegisterSpec for PkeNoiseEnSpec {
27431            type Ux = u32;
27432        }
27433        #[doc = "`read()` method returns [`pke_noise_en::R`](R) reader structure"]
27434        impl crate::Readable for PkeNoiseEnSpec {}
27435        #[doc = "`write(|w| ..)` method takes [`pke_noise_en::W`](W) writer structure"]
27436        impl crate::Writable for PkeNoiseEnSpec {
27437            type Safety = crate::Unsafe;
27438        }
27439        #[doc = "`reset()` method sets PKE_NOISE_EN to value 0"]
27440        impl crate::Resettable for PkeNoiseEnSpec {}
27441    }
27442    #[doc = "PKE_INT_ENABLE (rw) register accessor: PKE interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_int_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_int_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_int_enable`] module"]
27443    #[doc(alias = "PKE_INT_ENABLE")]
27444    pub type PkeIntEnable = crate::Reg<pke_int_enable::PkeIntEnableSpec>;
27445    #[doc = "PKE interrupt enable"]
27446    pub mod pke_int_enable {
27447        #[doc = "Register `PKE_INT_ENABLE` reader"]
27448        pub type R = crate::R<PkeIntEnableSpec>;
27449        #[doc = "Register `PKE_INT_ENABLE` writer"]
27450        pub type W = crate::W<PkeIntEnableSpec>;
27451        #[doc = "Field `finish_int_enable` reader - Operation finish interrupt enable"]
27452        pub type FinishIntEnableR = crate::BitReader;
27453        #[doc = "Field `finish_int_enable` writer - Operation finish interrupt enable"]
27454        pub type FinishIntEnableW<'a, REG> = crate::BitWriter<'a, REG>;
27455        impl R {
27456            #[doc = "Bit 0 - Operation finish interrupt enable"]
27457            #[inline(always)]
27458            pub fn finish_int_enable(&self) -> FinishIntEnableR {
27459                FinishIntEnableR::new((self.bits & 1) != 0)
27460            }
27461        }
27462        impl W {
27463            #[doc = "Bit 0 - Operation finish interrupt enable"]
27464            #[inline(always)]
27465            pub fn finish_int_enable(&mut self) -> FinishIntEnableW<'_, PkeIntEnableSpec> {
27466                FinishIntEnableW::new(self, 0)
27467            }
27468        }
27469        #[doc = "PKE interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_int_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_int_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27470        pub struct PkeIntEnableSpec;
27471        impl crate::RegisterSpec for PkeIntEnableSpec {
27472            type Ux = u32;
27473        }
27474        #[doc = "`read()` method returns [`pke_int_enable::R`](R) reader structure"]
27475        impl crate::Readable for PkeIntEnableSpec {}
27476        #[doc = "`write(|w| ..)` method takes [`pke_int_enable::W`](W) writer structure"]
27477        impl crate::Writable for PkeIntEnableSpec {
27478            type Safety = crate::Unsafe;
27479        }
27480        #[doc = "`reset()` method sets PKE_INT_ENABLE to value 0"]
27481        impl crate::Resettable for PkeIntEnableSpec {}
27482    }
27483    #[doc = "PKE_INT_NOMASK_STATUS (rw) register accessor: PKE unmasked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_int_nomask_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_int_nomask_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_int_nomask_status`] module"]
27484    #[doc(alias = "PKE_INT_NOMASK_STATUS")]
27485    pub type PkeIntNomaskStatus = crate::Reg<pke_int_nomask_status::PkeIntNomaskStatusSpec>;
27486    #[doc = "PKE unmasked interrupt status"]
27487    pub mod pke_int_nomask_status {
27488        #[doc = "Register `PKE_INT_NOMASK_STATUS` reader"]
27489        pub type R = crate::R<PkeIntNomaskStatusSpec>;
27490        #[doc = "Register `PKE_INT_NOMASK_STATUS` writer"]
27491        pub type W = crate::W<PkeIntNomaskStatusSpec>;
27492        #[doc = "Field `finish_int_nomask` reader - Finish interrupt status (expect 0x5 after completion)"]
27493        pub type FinishIntNomaskR = crate::FieldReader;
27494        impl R {
27495            #[doc = "Bits 0:3 - Finish interrupt status (expect 0x5 after completion)"]
27496            #[inline(always)]
27497            pub fn finish_int_nomask(&self) -> FinishIntNomaskR {
27498                FinishIntNomaskR::new((self.bits & 0x0f) as u8)
27499            }
27500        }
27501        impl W {}
27502        #[doc = "PKE unmasked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_int_nomask_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_int_nomask_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27503        pub struct PkeIntNomaskStatusSpec;
27504        impl crate::RegisterSpec for PkeIntNomaskStatusSpec {
27505            type Ux = u32;
27506        }
27507        #[doc = "`read()` method returns [`pke_int_nomask_status::R`](R) reader structure"]
27508        impl crate::Readable for PkeIntNomaskStatusSpec {}
27509        #[doc = "`write(|w| ..)` method takes [`pke_int_nomask_status::W`](W) writer structure"]
27510        impl crate::Writable for PkeIntNomaskStatusSpec {
27511            type Safety = crate::Unsafe;
27512        }
27513        #[doc = "`reset()` method sets PKE_INT_NOMASK_STATUS to value 0"]
27514        impl crate::Resettable for PkeIntNomaskStatusSpec {}
27515    }
27516    #[doc = "PKE_ALARM_STATUS (rw) register accessor: PKE alarm status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_alarm_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_alarm_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_alarm_status`] module"]
27517    #[doc(alias = "PKE_ALARM_STATUS")]
27518    pub type PkeAlarmStatus = crate::Reg<pke_alarm_status::PkeAlarmStatusSpec>;
27519    #[doc = "PKE alarm status register"]
27520    pub mod pke_alarm_status {
27521        #[doc = "Register `PKE_ALARM_STATUS` reader"]
27522        pub type R = crate::R<PkeAlarmStatusSpec>;
27523        #[doc = "Register `PKE_ALARM_STATUS` writer"]
27524        pub type W = crate::W<PkeAlarmStatusSpec>;
27525        #[doc = "Field `alarm_int` reader - Security alarm interrupt"]
27526        pub type AlarmIntR = crate::FieldReader;
27527        impl R {
27528            #[doc = "Bits 0:3 - Security alarm interrupt"]
27529            #[inline(always)]
27530            pub fn alarm_int(&self) -> AlarmIntR {
27531                AlarmIntR::new((self.bits & 0x0f) as u8)
27532            }
27533        }
27534        impl W {}
27535        #[doc = "PKE alarm status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_alarm_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_alarm_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27536        pub struct PkeAlarmStatusSpec;
27537        impl crate::RegisterSpec for PkeAlarmStatusSpec {
27538            type Ux = u32;
27539        }
27540        #[doc = "`read()` method returns [`pke_alarm_status::R`](R) reader structure"]
27541        impl crate::Readable for PkeAlarmStatusSpec {}
27542        #[doc = "`write(|w| ..)` method takes [`pke_alarm_status::W`](W) writer structure"]
27543        impl crate::Writable for PkeAlarmStatusSpec {
27544            type Safety = crate::Unsafe;
27545        }
27546        #[doc = "`reset()` method sets PKE_ALARM_STATUS to value 0"]
27547        impl crate::Resettable for PkeAlarmStatusSpec {}
27548    }
27549    #[doc = "PKE_FAILURE_FLAG (rw) register accessor: PKE failure flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_failure_flag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_failure_flag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_failure_flag`] module"]
27550    #[doc(alias = "PKE_FAILURE_FLAG")]
27551    pub type PkeFailureFlag = crate::Reg<pke_failure_flag::PkeFailureFlagSpec>;
27552    #[doc = "PKE failure flag register"]
27553    pub mod pke_failure_flag {
27554        #[doc = "Register `PKE_FAILURE_FLAG` reader"]
27555        pub type R = crate::R<PkeFailureFlagSpec>;
27556        #[doc = "Register `PKE_FAILURE_FLAG` writer"]
27557        pub type W = crate::W<PkeFailureFlagSpec>;
27558        #[doc = "Field `pke_failure_flag` reader - Operation failure status"]
27559        pub type PkeFailureFlagR = crate::FieldReader<u16>;
27560        impl R {
27561            #[doc = "Bits 0:10 - Operation failure status"]
27562            #[inline(always)]
27563            pub fn pke_failure_flag(&self) -> PkeFailureFlagR {
27564                PkeFailureFlagR::new((self.bits & 0x07ff) as u16)
27565            }
27566        }
27567        impl W {}
27568        #[doc = "PKE failure flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_failure_flag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_failure_flag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27569        pub struct PkeFailureFlagSpec;
27570        impl crate::RegisterSpec for PkeFailureFlagSpec {
27571            type Ux = u32;
27572        }
27573        #[doc = "`read()` method returns [`pke_failure_flag::R`](R) reader structure"]
27574        impl crate::Readable for PkeFailureFlagSpec {}
27575        #[doc = "`write(|w| ..)` method takes [`pke_failure_flag::W`](W) writer structure"]
27576        impl crate::Writable for PkeFailureFlagSpec {
27577            type Safety = crate::Unsafe;
27578        }
27579        #[doc = "`reset()` method sets PKE_FAILURE_FLAG to value 0"]
27580        impl crate::Resettable for PkeFailureFlagSpec {}
27581    }
27582    #[doc = "PKE_DRAM_CLR (rw) register accessor: PKE DRAM clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_dram_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_dram_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_dram_clr`] module"]
27583    #[doc(alias = "PKE_DRAM_CLR")]
27584    pub type PkeDramClr = crate::Reg<pke_dram_clr::PkeDramClrSpec>;
27585    #[doc = "PKE DRAM clear register"]
27586    pub mod pke_dram_clr {
27587        #[doc = "Register `PKE_DRAM_CLR` reader"]
27588        pub type R = crate::R<PkeDramClrSpec>;
27589        #[doc = "Register `PKE_DRAM_CLR` writer"]
27590        pub type W = crate::W<PkeDramClrSpec>;
27591        #[doc = "Field `dram_clr` writer - Clear PKE DRAM"]
27592        pub type DramClrW<'a, REG> = crate::BitWriter<'a, REG>;
27593        impl W {
27594            #[doc = "Bit 0 - Clear PKE DRAM"]
27595            #[inline(always)]
27596            pub fn dram_clr(&mut self) -> DramClrW<'_, PkeDramClrSpec> {
27597                DramClrW::new(self, 0)
27598            }
27599        }
27600        #[doc = "PKE DRAM clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_dram_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_dram_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27601        pub struct PkeDramClrSpec;
27602        impl crate::RegisterSpec for PkeDramClrSpec {
27603            type Ux = u32;
27604        }
27605        #[doc = "`read()` method returns [`pke_dram_clr::R`](R) reader structure"]
27606        impl crate::Readable for PkeDramClrSpec {}
27607        #[doc = "`write(|w| ..)` method takes [`pke_dram_clr::W`](W) writer structure"]
27608        impl crate::Writable for PkeDramClrSpec {
27609            type Safety = crate::Unsafe;
27610        }
27611        #[doc = "`reset()` method sets PKE_DRAM_CLR to value 0"]
27612        impl crate::Resettable for PkeDramClrSpec {}
27613    }
27614    #[doc = "PKE_LOCK_CTRL (rw) register accessor: PKE lock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_lock_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_lock_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_lock_ctrl`] module"]
27615    #[doc(alias = "PKE_LOCK_CTRL")]
27616    pub type PkeLockCtrl = crate::Reg<pke_lock_ctrl::PkeLockCtrlSpec>;
27617    #[doc = "PKE lock control register"]
27618    pub mod pke_lock_ctrl {
27619        #[doc = "Register `PKE_LOCK_CTRL` reader"]
27620        pub type R = crate::R<PkeLockCtrlSpec>;
27621        #[doc = "Register `PKE_LOCK_CTRL` writer"]
27622        pub type W = crate::W<PkeLockCtrlSpec>;
27623        #[doc = "Field `pke_lock` reader - Lock request"]
27624        pub type PkeLockR = crate::BitReader;
27625        #[doc = "Field `pke_lock` writer - Lock request"]
27626        pub type PkeLockW<'a, REG> = crate::BitWriter<'a, REG>;
27627        #[doc = "Field `pke_lock_type` reader - Lock type: 0=soft; 1=hard"]
27628        pub type PkeLockTypeR = crate::BitReader;
27629        #[doc = "Field `pke_lock_type` writer - Lock type: 0=soft; 1=hard"]
27630        pub type PkeLockTypeW<'a, REG> = crate::BitWriter<'a, REG>;
27631        impl R {
27632            #[doc = "Bit 0 - Lock request"]
27633            #[inline(always)]
27634            pub fn pke_lock(&self) -> PkeLockR {
27635                PkeLockR::new((self.bits & 1) != 0)
27636            }
27637            #[doc = "Bit 1 - Lock type: 0=soft; 1=hard"]
27638            #[inline(always)]
27639            pub fn pke_lock_type(&self) -> PkeLockTypeR {
27640                PkeLockTypeR::new(((self.bits >> 1) & 1) != 0)
27641            }
27642        }
27643        impl W {
27644            #[doc = "Bit 0 - Lock request"]
27645            #[inline(always)]
27646            pub fn pke_lock(&mut self) -> PkeLockW<'_, PkeLockCtrlSpec> {
27647                PkeLockW::new(self, 0)
27648            }
27649            #[doc = "Bit 1 - Lock type: 0=soft; 1=hard"]
27650            #[inline(always)]
27651            pub fn pke_lock_type(&mut self) -> PkeLockTypeW<'_, PkeLockCtrlSpec> {
27652                PkeLockTypeW::new(self, 1)
27653            }
27654        }
27655        #[doc = "PKE lock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_lock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_lock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27656        pub struct PkeLockCtrlSpec;
27657        impl crate::RegisterSpec for PkeLockCtrlSpec {
27658            type Ux = u32;
27659        }
27660        #[doc = "`read()` method returns [`pke_lock_ctrl::R`](R) reader structure"]
27661        impl crate::Readable for PkeLockCtrlSpec {}
27662        #[doc = "`write(|w| ..)` method takes [`pke_lock_ctrl::W`](W) writer structure"]
27663        impl crate::Writable for PkeLockCtrlSpec {
27664            type Safety = crate::Unsafe;
27665        }
27666        #[doc = "`reset()` method sets PKE_LOCK_CTRL to value 0"]
27667        impl crate::Resettable for PkeLockCtrlSpec {}
27668    }
27669    #[doc = "PKE_LOCK_STATUS (rw) register accessor: PKE lock status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_lock_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_lock_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_lock_status`] module"]
27670    #[doc(alias = "PKE_LOCK_STATUS")]
27671    pub type PkeLockStatus = crate::Reg<pke_lock_status::PkeLockStatusSpec>;
27672    #[doc = "PKE lock status register"]
27673    pub mod pke_lock_status {
27674        #[doc = "Register `PKE_LOCK_STATUS` reader"]
27675        pub type R = crate::R<PkeLockStatusSpec>;
27676        #[doc = "Register `PKE_LOCK_STATUS` writer"]
27677        pub type W = crate::W<PkeLockStatusSpec>;
27678        #[doc = "Field `pke_lock_busy` reader - Lock busy flag"]
27679        pub type PkeLockBusyR = crate::BitReader;
27680        #[doc = "Field `pke_unlock_fail` reader - Unlock failure flag"]
27681        pub type PkeUnlockFailR = crate::BitReader;
27682        #[doc = "Field `pke_lock_cnt` reader - Lock count"]
27683        pub type PkeLockCntR = crate::FieldReader;
27684        #[doc = "Field `pke_lock_stat` reader - Lock status: 0x6A=PCPU; 0x35=AIDSP; 0xA5=TEE; 0xAA=ACPU"]
27685        pub type PkeLockStatR = crate::FieldReader;
27686        impl R {
27687            #[doc = "Bit 0 - Lock busy flag"]
27688            #[inline(always)]
27689            pub fn pke_lock_busy(&self) -> PkeLockBusyR {
27690                PkeLockBusyR::new((self.bits & 1) != 0)
27691            }
27692            #[doc = "Bit 1 - Unlock failure flag"]
27693            #[inline(always)]
27694            pub fn pke_unlock_fail(&self) -> PkeUnlockFailR {
27695                PkeUnlockFailR::new(((self.bits >> 1) & 1) != 0)
27696            }
27697            #[doc = "Bits 4:6 - Lock count"]
27698            #[inline(always)]
27699            pub fn pke_lock_cnt(&self) -> PkeLockCntR {
27700                PkeLockCntR::new(((self.bits >> 4) & 7) as u8)
27701            }
27702            #[doc = "Bits 8:15 - Lock status: 0x6A=PCPU; 0x35=AIDSP; 0xA5=TEE; 0xAA=ACPU"]
27703            #[inline(always)]
27704            pub fn pke_lock_stat(&self) -> PkeLockStatR {
27705                PkeLockStatR::new(((self.bits >> 8) & 0xff) as u8)
27706            }
27707        }
27708        impl W {}
27709        #[doc = "PKE lock status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_lock_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_lock_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27710        pub struct PkeLockStatusSpec;
27711        impl crate::RegisterSpec for PkeLockStatusSpec {
27712            type Ux = u32;
27713        }
27714        #[doc = "`read()` method returns [`pke_lock_status::R`](R) reader structure"]
27715        impl crate::Readable for PkeLockStatusSpec {}
27716        #[doc = "`write(|w| ..)` method takes [`pke_lock_status::W`](W) writer structure"]
27717        impl crate::Writable for PkeLockStatusSpec {
27718            type Safety = crate::Unsafe;
27719        }
27720        #[doc = "`reset()` method sets PKE_LOCK_STATUS to value 0"]
27721        impl crate::Resettable for PkeLockStatusSpec {}
27722    }
27723}
27724#[doc = "Key Management - KLAD key derivation, keyslot locking, RKP root key protection"]
27725pub type Km = crate::Periph<km::RegisterBlock, 0x4411_2000>;
27726impl core::fmt::Debug for Km {
27727    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27728        f.debug_struct("Km").finish()
27729    }
27730}
27731#[doc = "Key Management - KLAD key derivation, keyslot locking, RKP root key protection"]
27732pub mod km {
27733    #[repr(C)]
27734    #[doc = "Register block"]
27735    pub struct RegisterBlock {
27736        _reserved0: [u8; 0x1000],
27737        kl_data_in_0: KlDataIn0,
27738        kl_data_in_1: KlDataIn1,
27739        kl_data_in_2: KlDataIn2,
27740        kl_data_in_3: KlDataIn3,
27741        kl_key_addr: KlKeyAddr,
27742        kl_key_cfg: KlKeyCfg,
27743        kl_key_sec_cfg: KlKeySecCfg,
27744        _reserved7: [u8; 0x14],
27745        kl_state: KlState,
27746        _reserved8: [u8; 0x04],
27747        kl_error: KlError,
27748        _reserved9: [u8; 0x04],
27749        kl_int_en: KlIntEn,
27750        _reserved10: [u8; 0x04],
27751        kl_int: KlInt,
27752        _reserved11: [u8; 0x28],
27753        kl_lock_ctrl: KlLockCtrl,
27754        _reserved12: [u8; 0x0c],
27755        kl_com_ctrl: KlComCtrl,
27756        kl_com_status: KlComStatus,
27757        _reserved14: [u8; 0x0574],
27758        kl_alarm_info: KlAlarmInfo,
27759        _reserved15: [u8; 0x04fc],
27760        kc_teecpu_lock_cmd: KcTeecpuLockCmd,
27761        kc_reecpu_lock_cmd: KcReecpuLockCmd,
27762        kc_pcpu_lock_cmd: KcPcpuLockCmd,
27763        kc_aidsp_lock_cmd: KcAidspLockCmd,
27764        _reserved19: [u8; 0x20],
27765        kc_rd_slot_num: KcRdSlotNum,
27766        kc_rd_lock_status: KcRdLockStatus,
27767    }
27768    impl RegisterBlock {
27769        #[doc = "0x1000 - Key data input word 0"]
27770        #[inline(always)]
27771        pub const fn kl_data_in_0(&self) -> &KlDataIn0 {
27772            &self.kl_data_in_0
27773        }
27774        #[doc = "0x1004 - Key data input word 1"]
27775        #[inline(always)]
27776        pub const fn kl_data_in_1(&self) -> &KlDataIn1 {
27777            &self.kl_data_in_1
27778        }
27779        #[doc = "0x1008 - Key data input word 2"]
27780        #[inline(always)]
27781        pub const fn kl_data_in_2(&self) -> &KlDataIn2 {
27782            &self.kl_data_in_2
27783        }
27784        #[doc = "0x100c - Key data input word 3"]
27785        #[inline(always)]
27786        pub const fn kl_data_in_3(&self) -> &KlDataIn3 {
27787            &self.kl_data_in_3
27788        }
27789        #[doc = "0x1010 - Key address register"]
27790        #[inline(always)]
27791        pub const fn kl_key_addr(&self) -> &KlKeyAddr {
27792            &self.kl_key_addr
27793        }
27794        #[doc = "0x1014 - Key configuration register"]
27795        #[inline(always)]
27796        pub const fn kl_key_cfg(&self) -> &KlKeyCfg {
27797            &self.kl_key_cfg
27798        }
27799        #[doc = "0x1018 - Key security configuration"]
27800        #[inline(always)]
27801        pub const fn kl_key_sec_cfg(&self) -> &KlKeySecCfg {
27802            &self.kl_key_sec_cfg
27803        }
27804        #[doc = "0x1030 - KLAD state register"]
27805        #[inline(always)]
27806        pub const fn kl_state(&self) -> &KlState {
27807            &self.kl_state
27808        }
27809        #[doc = "0x1038 - KLAD error register"]
27810        #[inline(always)]
27811        pub const fn kl_error(&self) -> &KlError {
27812            &self.kl_error
27813        }
27814        #[doc = "0x1040 - KLAD interrupt enable"]
27815        #[inline(always)]
27816        pub const fn kl_int_en(&self) -> &KlIntEn {
27817            &self.kl_int_en
27818        }
27819        #[doc = "0x1048 - KLAD interrupt status"]
27820        #[inline(always)]
27821        pub const fn kl_int(&self) -> &KlInt {
27822            &self.kl_int
27823        }
27824        #[doc = "0x1074 - KLAD lock control"]
27825        #[inline(always)]
27826        pub const fn kl_lock_ctrl(&self) -> &KlLockCtrl {
27827            &self.kl_lock_ctrl
27828        }
27829        #[doc = "0x1084 - KLAD common control"]
27830        #[inline(always)]
27831        pub const fn kl_com_ctrl(&self) -> &KlComCtrl {
27832            &self.kl_com_ctrl
27833        }
27834        #[doc = "0x1088 - KLAD common status"]
27835        #[inline(always)]
27836        pub const fn kl_com_status(&self) -> &KlComStatus {
27837            &self.kl_com_status
27838        }
27839        #[doc = "0x1600 - KLAD alarm info register"]
27840        #[inline(always)]
27841        pub const fn kl_alarm_info(&self) -> &KlAlarmInfo {
27842            &self.kl_alarm_info
27843        }
27844        #[doc = "0x1b00 - TEE CPU keyslot lock command"]
27845        #[inline(always)]
27846        pub const fn kc_teecpu_lock_cmd(&self) -> &KcTeecpuLockCmd {
27847            &self.kc_teecpu_lock_cmd
27848        }
27849        #[doc = "0x1b04 - REE CPU keyslot lock command"]
27850        #[inline(always)]
27851        pub const fn kc_reecpu_lock_cmd(&self) -> &KcReecpuLockCmd {
27852            &self.kc_reecpu_lock_cmd
27853        }
27854        #[doc = "0x1b08 - PCPU keyslot lock command"]
27855        #[inline(always)]
27856        pub const fn kc_pcpu_lock_cmd(&self) -> &KcPcpuLockCmd {
27857            &self.kc_pcpu_lock_cmd
27858        }
27859        #[doc = "0x1b0c - AIDSP keyslot lock command"]
27860        #[inline(always)]
27861        pub const fn kc_aidsp_lock_cmd(&self) -> &KcAidspLockCmd {
27862            &self.kc_aidsp_lock_cmd
27863        }
27864        #[doc = "0x1b30 - Keyslot query slot number selection"]
27865        #[inline(always)]
27866        pub const fn kc_rd_slot_num(&self) -> &KcRdSlotNum {
27867            &self.kc_rd_slot_num
27868        }
27869        #[doc = "0x1b34 - Keyslot lock status readback"]
27870        #[inline(always)]
27871        pub const fn kc_rd_lock_status(&self) -> &KcRdLockStatus {
27872            &self.kc_rd_lock_status
27873        }
27874    }
27875    #[doc = "KL_DATA_IN_0 (rw) register accessor: Key data input word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_data_in_0`] module"]
27876    #[doc(alias = "KL_DATA_IN_0")]
27877    pub type KlDataIn0 = crate::Reg<kl_data_in_0::KlDataIn0Spec>;
27878    #[doc = "Key data input word 0"]
27879    pub mod kl_data_in_0 {
27880        #[doc = "Register `KL_DATA_IN_0` reader"]
27881        pub type R = crate::R<KlDataIn0Spec>;
27882        #[doc = "Register `KL_DATA_IN_0` writer"]
27883        pub type W = crate::W<KlDataIn0Spec>;
27884        #[doc = "Field `data` reader - Key data\\[31:0\\]"]
27885        pub type DataR = crate::FieldReader<u32>;
27886        #[doc = "Field `data` writer - Key data\\[31:0\\]"]
27887        pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
27888        impl R {
27889            #[doc = "Bits 0:31 - Key data\\[31:0\\]"]
27890            #[inline(always)]
27891            pub fn data(&self) -> DataR {
27892                DataR::new(self.bits)
27893            }
27894        }
27895        impl W {
27896            #[doc = "Bits 0:31 - Key data\\[31:0\\]"]
27897            #[inline(always)]
27898            pub fn data(&mut self) -> DataW<'_, KlDataIn0Spec> {
27899                DataW::new(self, 0)
27900            }
27901        }
27902        #[doc = "Key data input word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27903        pub struct KlDataIn0Spec;
27904        impl crate::RegisterSpec for KlDataIn0Spec {
27905            type Ux = u32;
27906        }
27907        #[doc = "`read()` method returns [`kl_data_in_0::R`](R) reader structure"]
27908        impl crate::Readable for KlDataIn0Spec {}
27909        #[doc = "`write(|w| ..)` method takes [`kl_data_in_0::W`](W) writer structure"]
27910        impl crate::Writable for KlDataIn0Spec {
27911            type Safety = crate::Unsafe;
27912        }
27913        #[doc = "`reset()` method sets KL_DATA_IN_0 to value 0"]
27914        impl crate::Resettable for KlDataIn0Spec {}
27915    }
27916    #[doc = "KL_DATA_IN_1 (rw) register accessor: Key data input word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_data_in_1`] module"]
27917    #[doc(alias = "KL_DATA_IN_1")]
27918    pub type KlDataIn1 = crate::Reg<kl_data_in_1::KlDataIn1Spec>;
27919    #[doc = "Key data input word 1"]
27920    pub mod kl_data_in_1 {
27921        #[doc = "Register `KL_DATA_IN_1` reader"]
27922        pub type R = crate::R<KlDataIn1Spec>;
27923        #[doc = "Register `KL_DATA_IN_1` writer"]
27924        pub type W = crate::W<KlDataIn1Spec>;
27925        #[doc = "Field `data` reader - Key data\\[63:32\\]"]
27926        pub type DataR = crate::FieldReader<u32>;
27927        #[doc = "Field `data` writer - Key data\\[63:32\\]"]
27928        pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
27929        impl R {
27930            #[doc = "Bits 0:31 - Key data\\[63:32\\]"]
27931            #[inline(always)]
27932            pub fn data(&self) -> DataR {
27933                DataR::new(self.bits)
27934            }
27935        }
27936        impl W {
27937            #[doc = "Bits 0:31 - Key data\\[63:32\\]"]
27938            #[inline(always)]
27939            pub fn data(&mut self) -> DataW<'_, KlDataIn1Spec> {
27940                DataW::new(self, 0)
27941            }
27942        }
27943        #[doc = "Key data input word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27944        pub struct KlDataIn1Spec;
27945        impl crate::RegisterSpec for KlDataIn1Spec {
27946            type Ux = u32;
27947        }
27948        #[doc = "`read()` method returns [`kl_data_in_1::R`](R) reader structure"]
27949        impl crate::Readable for KlDataIn1Spec {}
27950        #[doc = "`write(|w| ..)` method takes [`kl_data_in_1::W`](W) writer structure"]
27951        impl crate::Writable for KlDataIn1Spec {
27952            type Safety = crate::Unsafe;
27953        }
27954        #[doc = "`reset()` method sets KL_DATA_IN_1 to value 0"]
27955        impl crate::Resettable for KlDataIn1Spec {}
27956    }
27957    #[doc = "KL_DATA_IN_2 (rw) register accessor: Key data input word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_data_in_2`] module"]
27958    #[doc(alias = "KL_DATA_IN_2")]
27959    pub type KlDataIn2 = crate::Reg<kl_data_in_2::KlDataIn2Spec>;
27960    #[doc = "Key data input word 2"]
27961    pub mod kl_data_in_2 {
27962        #[doc = "Register `KL_DATA_IN_2` reader"]
27963        pub type R = crate::R<KlDataIn2Spec>;
27964        #[doc = "Register `KL_DATA_IN_2` writer"]
27965        pub type W = crate::W<KlDataIn2Spec>;
27966        #[doc = "Field `data` reader - Key data\\[95:64\\]"]
27967        pub type DataR = crate::FieldReader<u32>;
27968        #[doc = "Field `data` writer - Key data\\[95:64\\]"]
27969        pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
27970        impl R {
27971            #[doc = "Bits 0:31 - Key data\\[95:64\\]"]
27972            #[inline(always)]
27973            pub fn data(&self) -> DataR {
27974                DataR::new(self.bits)
27975            }
27976        }
27977        impl W {
27978            #[doc = "Bits 0:31 - Key data\\[95:64\\]"]
27979            #[inline(always)]
27980            pub fn data(&mut self) -> DataW<'_, KlDataIn2Spec> {
27981                DataW::new(self, 0)
27982            }
27983        }
27984        #[doc = "Key data input word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27985        pub struct KlDataIn2Spec;
27986        impl crate::RegisterSpec for KlDataIn2Spec {
27987            type Ux = u32;
27988        }
27989        #[doc = "`read()` method returns [`kl_data_in_2::R`](R) reader structure"]
27990        impl crate::Readable for KlDataIn2Spec {}
27991        #[doc = "`write(|w| ..)` method takes [`kl_data_in_2::W`](W) writer structure"]
27992        impl crate::Writable for KlDataIn2Spec {
27993            type Safety = crate::Unsafe;
27994        }
27995        #[doc = "`reset()` method sets KL_DATA_IN_2 to value 0"]
27996        impl crate::Resettable for KlDataIn2Spec {}
27997    }
27998    #[doc = "KL_DATA_IN_3 (rw) register accessor: Key data input word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_data_in_3`] module"]
27999    #[doc(alias = "KL_DATA_IN_3")]
28000    pub type KlDataIn3 = crate::Reg<kl_data_in_3::KlDataIn3Spec>;
28001    #[doc = "Key data input word 3"]
28002    pub mod kl_data_in_3 {
28003        #[doc = "Register `KL_DATA_IN_3` reader"]
28004        pub type R = crate::R<KlDataIn3Spec>;
28005        #[doc = "Register `KL_DATA_IN_3` writer"]
28006        pub type W = crate::W<KlDataIn3Spec>;
28007        #[doc = "Field `data` reader - Key data\\[127:96\\]"]
28008        pub type DataR = crate::FieldReader<u32>;
28009        #[doc = "Field `data` writer - Key data\\[127:96\\]"]
28010        pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
28011        impl R {
28012            #[doc = "Bits 0:31 - Key data\\[127:96\\]"]
28013            #[inline(always)]
28014            pub fn data(&self) -> DataR {
28015                DataR::new(self.bits)
28016            }
28017        }
28018        impl W {
28019            #[doc = "Bits 0:31 - Key data\\[127:96\\]"]
28020            #[inline(always)]
28021            pub fn data(&mut self) -> DataW<'_, KlDataIn3Spec> {
28022                DataW::new(self, 0)
28023            }
28024        }
28025        #[doc = "Key data input word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28026        pub struct KlDataIn3Spec;
28027        impl crate::RegisterSpec for KlDataIn3Spec {
28028            type Ux = u32;
28029        }
28030        #[doc = "`read()` method returns [`kl_data_in_3::R`](R) reader structure"]
28031        impl crate::Readable for KlDataIn3Spec {}
28032        #[doc = "`write(|w| ..)` method takes [`kl_data_in_3::W`](W) writer structure"]
28033        impl crate::Writable for KlDataIn3Spec {
28034            type Safety = crate::Unsafe;
28035        }
28036        #[doc = "`reset()` method sets KL_DATA_IN_3 to value 0"]
28037        impl crate::Resettable for KlDataIn3Spec {}
28038    }
28039    #[doc = "KL_KEY_ADDR (rw) register accessor: Key address register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_key_addr`] module"]
28040    #[doc(alias = "KL_KEY_ADDR")]
28041    pub type KlKeyAddr = crate::Reg<kl_key_addr::KlKeyAddrSpec>;
28042    #[doc = "Key address register"]
28043    pub mod kl_key_addr {
28044        #[doc = "Register `KL_KEY_ADDR` reader"]
28045        pub type R = crate::R<KlKeyAddrSpec>;
28046        #[doc = "Register `KL_KEY_ADDR` writer"]
28047        pub type W = crate::W<KlKeyAddrSpec>;
28048        #[doc = "Field `key_addr` reader - Target key slot address"]
28049        pub type KeyAddrR = crate::FieldReader<u16>;
28050        #[doc = "Field `key_addr` writer - Target key slot address"]
28051        pub type KeyAddrW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
28052        impl R {
28053            #[doc = "Bits 0:9 - Target key slot address"]
28054            #[inline(always)]
28055            pub fn key_addr(&self) -> KeyAddrR {
28056                KeyAddrR::new((self.bits & 0x03ff) as u16)
28057            }
28058        }
28059        impl W {
28060            #[doc = "Bits 0:9 - Target key slot address"]
28061            #[inline(always)]
28062            pub fn key_addr(&mut self) -> KeyAddrW<'_, KlKeyAddrSpec> {
28063                KeyAddrW::new(self, 0)
28064            }
28065        }
28066        #[doc = "Key address register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28067        pub struct KlKeyAddrSpec;
28068        impl crate::RegisterSpec for KlKeyAddrSpec {
28069            type Ux = u32;
28070        }
28071        #[doc = "`read()` method returns [`kl_key_addr::R`](R) reader structure"]
28072        impl crate::Readable for KlKeyAddrSpec {}
28073        #[doc = "`write(|w| ..)` method takes [`kl_key_addr::W`](W) writer structure"]
28074        impl crate::Writable for KlKeyAddrSpec {
28075            type Safety = crate::Unsafe;
28076        }
28077        #[doc = "`reset()` method sets KL_KEY_ADDR to value 0"]
28078        impl crate::Resettable for KlKeyAddrSpec {}
28079    }
28080    #[doc = "KL_KEY_CFG (rw) register accessor: Key configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_key_cfg`] module"]
28081    #[doc(alias = "KL_KEY_CFG")]
28082    pub type KlKeyCfg = crate::Reg<kl_key_cfg::KlKeyCfgSpec>;
28083    #[doc = "Key configuration register"]
28084    pub mod kl_key_cfg {
28085        #[doc = "Register `KL_KEY_CFG` reader"]
28086        pub type R = crate::R<KlKeyCfgSpec>;
28087        #[doc = "Register `KL_KEY_CFG` writer"]
28088        pub type W = crate::W<KlKeyCfgSpec>;
28089        #[doc = "Field `port_sel` reader - Port select"]
28090        pub type PortSelR = crate::FieldReader;
28091        #[doc = "Field `port_sel` writer - Port select"]
28092        pub type PortSelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
28093        #[doc = "Field `dsc_code` reader - Descriptor code"]
28094        pub type DscCodeR = crate::FieldReader;
28095        #[doc = "Field `dsc_code` writer - Descriptor code"]
28096        pub type DscCodeW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
28097        #[doc = "Field `key_enc` reader - Key encrypt enable"]
28098        pub type KeyEncR = crate::BitReader;
28099        #[doc = "Field `key_enc` writer - Key encrypt enable"]
28100        pub type KeyEncW<'a, REG> = crate::BitWriter<'a, REG>;
28101        #[doc = "Field `key_dec` reader - Key decrypt enable"]
28102        pub type KeyDecR = crate::BitReader;
28103        #[doc = "Field `key_dec` writer - Key decrypt enable"]
28104        pub type KeyDecW<'a, REG> = crate::BitWriter<'a, REG>;
28105        #[doc = "Field `kl_flash_sel` reader - Flash key source select"]
28106        pub type KlFlashSelR = crate::FieldReader;
28107        #[doc = "Field `kl_flash_sel` writer - Flash key source select"]
28108        pub type KlFlashSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
28109        impl R {
28110            #[doc = "Bits 0:2 - Port select"]
28111            #[inline(always)]
28112            pub fn port_sel(&self) -> PortSelR {
28113                PortSelR::new((self.bits & 7) as u8)
28114            }
28115            #[doc = "Bits 4:11 - Descriptor code"]
28116            #[inline(always)]
28117            pub fn dsc_code(&self) -> DscCodeR {
28118                DscCodeR::new(((self.bits >> 4) & 0xff) as u8)
28119            }
28120            #[doc = "Bit 16 - Key encrypt enable"]
28121            #[inline(always)]
28122            pub fn key_enc(&self) -> KeyEncR {
28123                KeyEncR::new(((self.bits >> 16) & 1) != 0)
28124            }
28125            #[doc = "Bit 17 - Key decrypt enable"]
28126            #[inline(always)]
28127            pub fn key_dec(&self) -> KeyDecR {
28128                KeyDecR::new(((self.bits >> 17) & 1) != 0)
28129            }
28130            #[doc = "Bits 18:19 - Flash key source select"]
28131            #[inline(always)]
28132            pub fn kl_flash_sel(&self) -> KlFlashSelR {
28133                KlFlashSelR::new(((self.bits >> 18) & 3) as u8)
28134            }
28135        }
28136        impl W {
28137            #[doc = "Bits 0:2 - Port select"]
28138            #[inline(always)]
28139            pub fn port_sel(&mut self) -> PortSelW<'_, KlKeyCfgSpec> {
28140                PortSelW::new(self, 0)
28141            }
28142            #[doc = "Bits 4:11 - Descriptor code"]
28143            #[inline(always)]
28144            pub fn dsc_code(&mut self) -> DscCodeW<'_, KlKeyCfgSpec> {
28145                DscCodeW::new(self, 4)
28146            }
28147            #[doc = "Bit 16 - Key encrypt enable"]
28148            #[inline(always)]
28149            pub fn key_enc(&mut self) -> KeyEncW<'_, KlKeyCfgSpec> {
28150                KeyEncW::new(self, 16)
28151            }
28152            #[doc = "Bit 17 - Key decrypt enable"]
28153            #[inline(always)]
28154            pub fn key_dec(&mut self) -> KeyDecW<'_, KlKeyCfgSpec> {
28155                KeyDecW::new(self, 17)
28156            }
28157            #[doc = "Bits 18:19 - Flash key source select"]
28158            #[inline(always)]
28159            pub fn kl_flash_sel(&mut self) -> KlFlashSelW<'_, KlKeyCfgSpec> {
28160                KlFlashSelW::new(self, 18)
28161            }
28162        }
28163        #[doc = "Key configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28164        pub struct KlKeyCfgSpec;
28165        impl crate::RegisterSpec for KlKeyCfgSpec {
28166            type Ux = u32;
28167        }
28168        #[doc = "`read()` method returns [`kl_key_cfg::R`](R) reader structure"]
28169        impl crate::Readable for KlKeyCfgSpec {}
28170        #[doc = "`write(|w| ..)` method takes [`kl_key_cfg::W`](W) writer structure"]
28171        impl crate::Writable for KlKeyCfgSpec {
28172            type Safety = crate::Unsafe;
28173        }
28174        #[doc = "`reset()` method sets KL_KEY_CFG to value 0"]
28175        impl crate::Resettable for KlKeyCfgSpec {}
28176    }
28177    #[doc = "KL_KEY_SEC_CFG (rw) register accessor: Key security configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_sec_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_sec_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_key_sec_cfg`] module"]
28178    #[doc(alias = "KL_KEY_SEC_CFG")]
28179    pub type KlKeySecCfg = crate::Reg<kl_key_sec_cfg::KlKeySecCfgSpec>;
28180    #[doc = "Key security configuration"]
28181    pub mod kl_key_sec_cfg {
28182        #[doc = "Register `KL_KEY_SEC_CFG` reader"]
28183        pub type R = crate::R<KlKeySecCfgSpec>;
28184        #[doc = "Register `KL_KEY_SEC_CFG` writer"]
28185        pub type W = crate::W<KlKeySecCfgSpec>;
28186        #[doc = "Field `key_sec` reader - Key security: 0=NS; 1=Secure"]
28187        pub type KeySecR = crate::BitReader;
28188        #[doc = "Field `key_sec` writer - Key security: 0=NS; 1=Secure"]
28189        pub type KeySecW<'a, REG> = crate::BitWriter<'a, REG>;
28190        #[doc = "Field `src_nsec` reader - Source non-secure: 0=secure; 1=NS"]
28191        pub type SrcNsecR = crate::BitReader;
28192        #[doc = "Field `src_nsec` writer - Source non-secure: 0=secure; 1=NS"]
28193        pub type SrcNsecW<'a, REG> = crate::BitWriter<'a, REG>;
28194        #[doc = "Field `src_sec` reader - Source secure: 0=NS; 1=Secure"]
28195        pub type SrcSecR = crate::BitReader;
28196        #[doc = "Field `src_sec` writer - Source secure: 0=NS; 1=Secure"]
28197        pub type SrcSecW<'a, REG> = crate::BitWriter<'a, REG>;
28198        #[doc = "Field `dest_nsec` reader - Destination non-secure"]
28199        pub type DestNsecR = crate::BitReader;
28200        #[doc = "Field `dest_nsec` writer - Destination non-secure"]
28201        pub type DestNsecW<'a, REG> = crate::BitWriter<'a, REG>;
28202        #[doc = "Field `dest_sec` reader - Destination secure"]
28203        pub type DestSecR = crate::BitReader;
28204        #[doc = "Field `dest_sec` writer - Destination secure"]
28205        pub type DestSecW<'a, REG> = crate::BitWriter<'a, REG>;
28206        #[doc = "Field `master_only` reader - Master-only access"]
28207        pub type MasterOnlyR = crate::BitReader;
28208        #[doc = "Field `master_only` writer - Master-only access"]
28209        pub type MasterOnlyW<'a, REG> = crate::BitWriter<'a, REG>;
28210        impl R {
28211            #[doc = "Bit 0 - Key security: 0=NS; 1=Secure"]
28212            #[inline(always)]
28213            pub fn key_sec(&self) -> KeySecR {
28214                KeySecR::new((self.bits & 1) != 0)
28215            }
28216            #[doc = "Bit 1 - Source non-secure: 0=secure; 1=NS"]
28217            #[inline(always)]
28218            pub fn src_nsec(&self) -> SrcNsecR {
28219                SrcNsecR::new(((self.bits >> 1) & 1) != 0)
28220            }
28221            #[doc = "Bit 2 - Source secure: 0=NS; 1=Secure"]
28222            #[inline(always)]
28223            pub fn src_sec(&self) -> SrcSecR {
28224                SrcSecR::new(((self.bits >> 2) & 1) != 0)
28225            }
28226            #[doc = "Bit 3 - Destination non-secure"]
28227            #[inline(always)]
28228            pub fn dest_nsec(&self) -> DestNsecR {
28229                DestNsecR::new(((self.bits >> 3) & 1) != 0)
28230            }
28231            #[doc = "Bit 4 - Destination secure"]
28232            #[inline(always)]
28233            pub fn dest_sec(&self) -> DestSecR {
28234                DestSecR::new(((self.bits >> 4) & 1) != 0)
28235            }
28236            #[doc = "Bit 5 - Master-only access"]
28237            #[inline(always)]
28238            pub fn master_only(&self) -> MasterOnlyR {
28239                MasterOnlyR::new(((self.bits >> 5) & 1) != 0)
28240            }
28241        }
28242        impl W {
28243            #[doc = "Bit 0 - Key security: 0=NS; 1=Secure"]
28244            #[inline(always)]
28245            pub fn key_sec(&mut self) -> KeySecW<'_, KlKeySecCfgSpec> {
28246                KeySecW::new(self, 0)
28247            }
28248            #[doc = "Bit 1 - Source non-secure: 0=secure; 1=NS"]
28249            #[inline(always)]
28250            pub fn src_nsec(&mut self) -> SrcNsecW<'_, KlKeySecCfgSpec> {
28251                SrcNsecW::new(self, 1)
28252            }
28253            #[doc = "Bit 2 - Source secure: 0=NS; 1=Secure"]
28254            #[inline(always)]
28255            pub fn src_sec(&mut self) -> SrcSecW<'_, KlKeySecCfgSpec> {
28256                SrcSecW::new(self, 2)
28257            }
28258            #[doc = "Bit 3 - Destination non-secure"]
28259            #[inline(always)]
28260            pub fn dest_nsec(&mut self) -> DestNsecW<'_, KlKeySecCfgSpec> {
28261                DestNsecW::new(self, 3)
28262            }
28263            #[doc = "Bit 4 - Destination secure"]
28264            #[inline(always)]
28265            pub fn dest_sec(&mut self) -> DestSecW<'_, KlKeySecCfgSpec> {
28266                DestSecW::new(self, 4)
28267            }
28268            #[doc = "Bit 5 - Master-only access"]
28269            #[inline(always)]
28270            pub fn master_only(&mut self) -> MasterOnlyW<'_, KlKeySecCfgSpec> {
28271                MasterOnlyW::new(self, 5)
28272            }
28273        }
28274        #[doc = "Key security configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_sec_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_sec_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28275        pub struct KlKeySecCfgSpec;
28276        impl crate::RegisterSpec for KlKeySecCfgSpec {
28277            type Ux = u32;
28278        }
28279        #[doc = "`read()` method returns [`kl_key_sec_cfg::R`](R) reader structure"]
28280        impl crate::Readable for KlKeySecCfgSpec {}
28281        #[doc = "`write(|w| ..)` method takes [`kl_key_sec_cfg::W`](W) writer structure"]
28282        impl crate::Writable for KlKeySecCfgSpec {
28283            type Safety = crate::Unsafe;
28284        }
28285        #[doc = "`reset()` method sets KL_KEY_SEC_CFG to value 0"]
28286        impl crate::Resettable for KlKeySecCfgSpec {}
28287    }
28288    #[doc = "KL_STATE (rw) register accessor: KLAD state register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_state::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_state::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_state`] module"]
28289    #[doc(alias = "KL_STATE")]
28290    pub type KlState = crate::Reg<kl_state::KlStateSpec>;
28291    #[doc = "KLAD state register"]
28292    pub mod kl_state {
28293        #[doc = "Register `KL_STATE` reader"]
28294        pub type R = crate::R<KlStateSpec>;
28295        #[doc = "Register `KL_STATE` writer"]
28296        pub type W = crate::W<KlStateSpec>;
28297        #[doc = "Field `state` reader - KLAD processing state"]
28298        pub type StateR = crate::FieldReader<u32>;
28299        impl R {
28300            #[doc = "Bits 0:31 - KLAD processing state"]
28301            #[inline(always)]
28302            pub fn state(&self) -> StateR {
28303                StateR::new(self.bits)
28304            }
28305        }
28306        impl W {}
28307        #[doc = "KLAD state register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28308        pub struct KlStateSpec;
28309        impl crate::RegisterSpec for KlStateSpec {
28310            type Ux = u32;
28311        }
28312        #[doc = "`read()` method returns [`kl_state::R`](R) reader structure"]
28313        impl crate::Readable for KlStateSpec {}
28314        #[doc = "`write(|w| ..)` method takes [`kl_state::W`](W) writer structure"]
28315        impl crate::Writable for KlStateSpec {
28316            type Safety = crate::Unsafe;
28317        }
28318        #[doc = "`reset()` method sets KL_STATE to value 0"]
28319        impl crate::Resettable for KlStateSpec {}
28320    }
28321    #[doc = "KL_ERROR (rw) register accessor: KLAD error register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_error::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_error::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_error`] module"]
28322    #[doc(alias = "KL_ERROR")]
28323    pub type KlError = crate::Reg<kl_error::KlErrorSpec>;
28324    #[doc = "KLAD error register"]
28325    pub mod kl_error {
28326        #[doc = "Register `KL_ERROR` reader"]
28327        pub type R = crate::R<KlErrorSpec>;
28328        #[doc = "Register `KL_ERROR` writer"]
28329        pub type W = crate::W<KlErrorSpec>;
28330        #[doc = "Field `error` reader - KLAD error code"]
28331        pub type ErrorR = crate::FieldReader<u32>;
28332        impl R {
28333            #[doc = "Bits 0:31 - KLAD error code"]
28334            #[inline(always)]
28335            pub fn error(&self) -> ErrorR {
28336                ErrorR::new(self.bits)
28337            }
28338        }
28339        impl W {}
28340        #[doc = "KLAD error register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_error::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_error::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28341        pub struct KlErrorSpec;
28342        impl crate::RegisterSpec for KlErrorSpec {
28343            type Ux = u32;
28344        }
28345        #[doc = "`read()` method returns [`kl_error::R`](R) reader structure"]
28346        impl crate::Readable for KlErrorSpec {}
28347        #[doc = "`write(|w| ..)` method takes [`kl_error::W`](W) writer structure"]
28348        impl crate::Writable for KlErrorSpec {
28349            type Safety = crate::Unsafe;
28350        }
28351        #[doc = "`reset()` method sets KL_ERROR to value 0"]
28352        impl crate::Resettable for KlErrorSpec {}
28353    }
28354    #[doc = "KL_INT_EN (rw) register accessor: KLAD interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_int_en`] module"]
28355    #[doc(alias = "KL_INT_EN")]
28356    pub type KlIntEn = crate::Reg<kl_int_en::KlIntEnSpec>;
28357    #[doc = "KLAD interrupt enable"]
28358    pub mod kl_int_en {
28359        #[doc = "Register `KL_INT_EN` reader"]
28360        pub type R = crate::R<KlIntEnSpec>;
28361        #[doc = "Register `KL_INT_EN` writer"]
28362        pub type W = crate::W<KlIntEnSpec>;
28363        #[doc = "Field `kl_int_en` reader - KLAD interrupt enable"]
28364        pub type KlIntEnR = crate::BitReader;
28365        #[doc = "Field `kl_int_en` writer - KLAD interrupt enable"]
28366        pub type KlIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
28367        impl R {
28368            #[doc = "Bit 0 - KLAD interrupt enable"]
28369            #[inline(always)]
28370            pub fn kl_int_en(&self) -> KlIntEnR {
28371                KlIntEnR::new((self.bits & 1) != 0)
28372            }
28373        }
28374        impl W {
28375            #[doc = "Bit 0 - KLAD interrupt enable"]
28376            #[inline(always)]
28377            pub fn kl_int_en(&mut self) -> KlIntEnW<'_, KlIntEnSpec> {
28378                KlIntEnW::new(self, 0)
28379            }
28380        }
28381        #[doc = "KLAD interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28382        pub struct KlIntEnSpec;
28383        impl crate::RegisterSpec for KlIntEnSpec {
28384            type Ux = u32;
28385        }
28386        #[doc = "`read()` method returns [`kl_int_en::R`](R) reader structure"]
28387        impl crate::Readable for KlIntEnSpec {}
28388        #[doc = "`write(|w| ..)` method takes [`kl_int_en::W`](W) writer structure"]
28389        impl crate::Writable for KlIntEnSpec {
28390            type Safety = crate::Unsafe;
28391        }
28392        #[doc = "`reset()` method sets KL_INT_EN to value 0"]
28393        impl crate::Resettable for KlIntEnSpec {}
28394    }
28395    #[doc = "KL_INT (rw) register accessor: KLAD interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_int`] module"]
28396    #[doc(alias = "KL_INT")]
28397    pub type KlInt = crate::Reg<kl_int::KlIntSpec>;
28398    #[doc = "KLAD interrupt status"]
28399    pub mod kl_int {
28400        #[doc = "Register `KL_INT` reader"]
28401        pub type R = crate::R<KlIntSpec>;
28402        #[doc = "Register `KL_INT` writer"]
28403        pub type W = crate::W<KlIntSpec>;
28404        #[doc = "Field `kl_int` reader - KLAD interrupt flag"]
28405        pub type KlIntR = crate::BitReader;
28406        impl R {
28407            #[doc = "Bit 0 - KLAD interrupt flag"]
28408            #[inline(always)]
28409            pub fn kl_int(&self) -> KlIntR {
28410                KlIntR::new((self.bits & 1) != 0)
28411            }
28412        }
28413        impl W {}
28414        #[doc = "KLAD interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28415        pub struct KlIntSpec;
28416        impl crate::RegisterSpec for KlIntSpec {
28417            type Ux = u32;
28418        }
28419        #[doc = "`read()` method returns [`kl_int::R`](R) reader structure"]
28420        impl crate::Readable for KlIntSpec {}
28421        #[doc = "`write(|w| ..)` method takes [`kl_int::W`](W) writer structure"]
28422        impl crate::Writable for KlIntSpec {
28423            type Safety = crate::Unsafe;
28424        }
28425        #[doc = "`reset()` method sets KL_INT to value 0"]
28426        impl crate::Resettable for KlIntSpec {}
28427    }
28428    #[doc = "KL_COM_CTRL (rw) register accessor: KLAD common control\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_com_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_com_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_com_ctrl`] module"]
28429    #[doc(alias = "KL_COM_CTRL")]
28430    pub type KlComCtrl = crate::Reg<kl_com_ctrl::KlComCtrlSpec>;
28431    #[doc = "KLAD common control"]
28432    pub mod kl_com_ctrl {
28433        #[doc = "Register `KL_COM_CTRL` reader"]
28434        pub type R = crate::R<KlComCtrlSpec>;
28435        #[doc = "Register `KL_COM_CTRL` writer"]
28436        pub type W = crate::W<KlComCtrlSpec>;
28437        #[doc = "Field `kl_com_start` writer - Common KDF start"]
28438        pub type KlComStartW<'a, REG> = crate::BitWriter<'a, REG>;
28439        #[doc = "Field `kl_com_level_sel` reader - Level select"]
28440        pub type KlComLevelSelR = crate::FieldReader;
28441        #[doc = "Field `kl_com_level_sel` writer - Level select"]
28442        pub type KlComLevelSelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
28443        #[doc = "Field `kl_com_alg_sel` reader - Algorithm select"]
28444        pub type KlComAlgSelR = crate::FieldReader;
28445        #[doc = "Field `kl_com_alg_sel` writer - Algorithm select"]
28446        pub type KlComAlgSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
28447        #[doc = "Field `kl_com_key_size` reader - Key size select"]
28448        pub type KlComKeySizeR = crate::FieldReader;
28449        #[doc = "Field `kl_com_key_size` writer - Key size select"]
28450        pub type KlComKeySizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
28451        #[doc = "Field `rk_choose` reader - Root key select: 4=USD; 5=SBRK; 6=ABRK; 13=DRK; 18=PSK"]
28452        pub type RkChooseR = crate::FieldReader;
28453        #[doc = "Field `rk_choose` writer - Root key select: 4=USD; 5=SBRK; 6=ABRK; 13=DRK; 18=PSK"]
28454        pub type RkChooseW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
28455        impl R {
28456            #[doc = "Bits 1:3 - Level select"]
28457            #[inline(always)]
28458            pub fn kl_com_level_sel(&self) -> KlComLevelSelR {
28459                KlComLevelSelR::new(((self.bits >> 1) & 7) as u8)
28460            }
28461            #[doc = "Bits 4:5 - Algorithm select"]
28462            #[inline(always)]
28463            pub fn kl_com_alg_sel(&self) -> KlComAlgSelR {
28464                KlComAlgSelR::new(((self.bits >> 4) & 3) as u8)
28465            }
28466            #[doc = "Bits 6:7 - Key size select"]
28467            #[inline(always)]
28468            pub fn kl_com_key_size(&self) -> KlComKeySizeR {
28469                KlComKeySizeR::new(((self.bits >> 6) & 3) as u8)
28470            }
28471            #[doc = "Bits 8:12 - Root key select: 4=USD; 5=SBRK; 6=ABRK; 13=DRK; 18=PSK"]
28472            #[inline(always)]
28473            pub fn rk_choose(&self) -> RkChooseR {
28474                RkChooseR::new(((self.bits >> 8) & 0x1f) as u8)
28475            }
28476        }
28477        impl W {
28478            #[doc = "Bit 0 - Common KDF start"]
28479            #[inline(always)]
28480            pub fn kl_com_start(&mut self) -> KlComStartW<'_, KlComCtrlSpec> {
28481                KlComStartW::new(self, 0)
28482            }
28483            #[doc = "Bits 1:3 - Level select"]
28484            #[inline(always)]
28485            pub fn kl_com_level_sel(&mut self) -> KlComLevelSelW<'_, KlComCtrlSpec> {
28486                KlComLevelSelW::new(self, 1)
28487            }
28488            #[doc = "Bits 4:5 - Algorithm select"]
28489            #[inline(always)]
28490            pub fn kl_com_alg_sel(&mut self) -> KlComAlgSelW<'_, KlComCtrlSpec> {
28491                KlComAlgSelW::new(self, 4)
28492            }
28493            #[doc = "Bits 6:7 - Key size select"]
28494            #[inline(always)]
28495            pub fn kl_com_key_size(&mut self) -> KlComKeySizeW<'_, KlComCtrlSpec> {
28496                KlComKeySizeW::new(self, 6)
28497            }
28498            #[doc = "Bits 8:12 - Root key select: 4=USD; 5=SBRK; 6=ABRK; 13=DRK; 18=PSK"]
28499            #[inline(always)]
28500            pub fn rk_choose(&mut self) -> RkChooseW<'_, KlComCtrlSpec> {
28501                RkChooseW::new(self, 8)
28502            }
28503        }
28504        #[doc = "KLAD common control\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_com_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_com_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28505        pub struct KlComCtrlSpec;
28506        impl crate::RegisterSpec for KlComCtrlSpec {
28507            type Ux = u32;
28508        }
28509        #[doc = "`read()` method returns [`kl_com_ctrl::R`](R) reader structure"]
28510        impl crate::Readable for KlComCtrlSpec {}
28511        #[doc = "`write(|w| ..)` method takes [`kl_com_ctrl::W`](W) writer structure"]
28512        impl crate::Writable for KlComCtrlSpec {
28513            type Safety = crate::Unsafe;
28514        }
28515        #[doc = "`reset()` method sets KL_COM_CTRL to value 0"]
28516        impl crate::Resettable for KlComCtrlSpec {}
28517    }
28518    #[doc = "KL_COM_STATUS (rw) register accessor: KLAD common status\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_com_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_com_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_com_status`] module"]
28519    #[doc(alias = "KL_COM_STATUS")]
28520    pub type KlComStatus = crate::Reg<kl_com_status::KlComStatusSpec>;
28521    #[doc = "KLAD common status"]
28522    pub mod kl_com_status {
28523        #[doc = "Register `KL_COM_STATUS` reader"]
28524        pub type R = crate::R<KlComStatusSpec>;
28525        #[doc = "Register `KL_COM_STATUS` writer"]
28526        pub type W = crate::W<KlComStatusSpec>;
28527        #[doc = "Field `kl_com_rk_rdy` reader - Root key ready"]
28528        pub type KlComRkRdyR = crate::BitReader;
28529        #[doc = "Field `kl_com_lv1_rdy` reader - Level 1 key ready"]
28530        pub type KlComLv1RdyR = crate::BitReader;
28531        impl R {
28532            #[doc = "Bit 0 - Root key ready"]
28533            #[inline(always)]
28534            pub fn kl_com_rk_rdy(&self) -> KlComRkRdyR {
28535                KlComRkRdyR::new((self.bits & 1) != 0)
28536            }
28537            #[doc = "Bit 1 - Level 1 key ready"]
28538            #[inline(always)]
28539            pub fn kl_com_lv1_rdy(&self) -> KlComLv1RdyR {
28540                KlComLv1RdyR::new(((self.bits >> 1) & 1) != 0)
28541            }
28542        }
28543        impl W {}
28544        #[doc = "KLAD common status\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_com_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_com_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28545        pub struct KlComStatusSpec;
28546        impl crate::RegisterSpec for KlComStatusSpec {
28547            type Ux = u32;
28548        }
28549        #[doc = "`read()` method returns [`kl_com_status::R`](R) reader structure"]
28550        impl crate::Readable for KlComStatusSpec {}
28551        #[doc = "`write(|w| ..)` method takes [`kl_com_status::W`](W) writer structure"]
28552        impl crate::Writable for KlComStatusSpec {
28553            type Safety = crate::Unsafe;
28554        }
28555        #[doc = "`reset()` method sets KL_COM_STATUS to value 0"]
28556        impl crate::Resettable for KlComStatusSpec {}
28557    }
28558    #[doc = "KL_LOCK_CTRL (rw) register accessor: KLAD lock control\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_lock_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_lock_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_lock_ctrl`] module"]
28559    #[doc(alias = "KL_LOCK_CTRL")]
28560    pub type KlLockCtrl = crate::Reg<kl_lock_ctrl::KlLockCtrlSpec>;
28561    #[doc = "KLAD lock control"]
28562    pub mod kl_lock_ctrl {
28563        #[doc = "Register `KL_LOCK_CTRL` reader"]
28564        pub type R = crate::R<KlLockCtrlSpec>;
28565        #[doc = "Register `KL_LOCK_CTRL` writer"]
28566        pub type W = crate::W<KlLockCtrlSpec>;
28567        #[doc = "Field `kl_lock` writer - Lock request"]
28568        pub type KlLockW<'a, REG> = crate::BitWriter<'a, REG>;
28569        #[doc = "Field `kl_lock_num` reader - Lock sequence number"]
28570        pub type KlLockNumR = crate::FieldReader;
28571        #[doc = "Field `kl_lock_num` writer - Lock sequence number"]
28572        pub type KlLockNumW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
28573        impl R {
28574            #[doc = "Bits 4:6 - Lock sequence number"]
28575            #[inline(always)]
28576            pub fn kl_lock_num(&self) -> KlLockNumR {
28577                KlLockNumR::new(((self.bits >> 4) & 7) as u8)
28578            }
28579        }
28580        impl W {
28581            #[doc = "Bit 0 - Lock request"]
28582            #[inline(always)]
28583            pub fn kl_lock(&mut self) -> KlLockW<'_, KlLockCtrlSpec> {
28584                KlLockW::new(self, 0)
28585            }
28586            #[doc = "Bits 4:6 - Lock sequence number"]
28587            #[inline(always)]
28588            pub fn kl_lock_num(&mut self) -> KlLockNumW<'_, KlLockCtrlSpec> {
28589                KlLockNumW::new(self, 4)
28590            }
28591        }
28592        #[doc = "KLAD lock control\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_lock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_lock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28593        pub struct KlLockCtrlSpec;
28594        impl crate::RegisterSpec for KlLockCtrlSpec {
28595            type Ux = u32;
28596        }
28597        #[doc = "`read()` method returns [`kl_lock_ctrl::R`](R) reader structure"]
28598        impl crate::Readable for KlLockCtrlSpec {}
28599        #[doc = "`write(|w| ..)` method takes [`kl_lock_ctrl::W`](W) writer structure"]
28600        impl crate::Writable for KlLockCtrlSpec {
28601            type Safety = crate::Unsafe;
28602        }
28603        #[doc = "`reset()` method sets KL_LOCK_CTRL to value 0"]
28604        impl crate::Resettable for KlLockCtrlSpec {}
28605    }
28606    #[doc = "KL_ALARM_INFO (rw) register accessor: KLAD alarm info register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_alarm_info::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_alarm_info::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_alarm_info`] module"]
28607    #[doc(alias = "KL_ALARM_INFO")]
28608    pub type KlAlarmInfo = crate::Reg<kl_alarm_info::KlAlarmInfoSpec>;
28609    #[doc = "KLAD alarm info register"]
28610    pub mod kl_alarm_info {
28611        #[doc = "Register `KL_ALARM_INFO` reader"]
28612        pub type R = crate::R<KlAlarmInfoSpec>;
28613        #[doc = "Register `KL_ALARM_INFO` writer"]
28614        pub type W = crate::W<KlAlarmInfoSpec>;
28615        #[doc = "Field `kl_cfg_sig_alarm` reader - Config signature alarm"]
28616        pub type KlCfgSigAlarmR = crate::BitReader;
28617        #[doc = "Field `kl_com_crc16_alarm` reader - Common CRC16 alarm"]
28618        pub type KlComCrc16AlarmR = crate::BitReader;
28619        impl R {
28620            #[doc = "Bit 0 - Config signature alarm"]
28621            #[inline(always)]
28622            pub fn kl_cfg_sig_alarm(&self) -> KlCfgSigAlarmR {
28623                KlCfgSigAlarmR::new((self.bits & 1) != 0)
28624            }
28625            #[doc = "Bit 1 - Common CRC16 alarm"]
28626            #[inline(always)]
28627            pub fn kl_com_crc16_alarm(&self) -> KlComCrc16AlarmR {
28628                KlComCrc16AlarmR::new(((self.bits >> 1) & 1) != 0)
28629            }
28630        }
28631        impl W {}
28632        #[doc = "KLAD alarm info register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_alarm_info::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_alarm_info::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28633        pub struct KlAlarmInfoSpec;
28634        impl crate::RegisterSpec for KlAlarmInfoSpec {
28635            type Ux = u32;
28636        }
28637        #[doc = "`read()` method returns [`kl_alarm_info::R`](R) reader structure"]
28638        impl crate::Readable for KlAlarmInfoSpec {}
28639        #[doc = "`write(|w| ..)` method takes [`kl_alarm_info::W`](W) writer structure"]
28640        impl crate::Writable for KlAlarmInfoSpec {
28641            type Safety = crate::Unsafe;
28642        }
28643        #[doc = "`reset()` method sets KL_ALARM_INFO to value 0"]
28644        impl crate::Resettable for KlAlarmInfoSpec {}
28645    }
28646    #[doc = "KC_TEECPU_LOCK_CMD (rw) register accessor: TEE CPU keyslot lock command\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_teecpu_lock_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_teecpu_lock_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kc_teecpu_lock_cmd`] module"]
28647    #[doc(alias = "KC_TEECPU_LOCK_CMD")]
28648    pub type KcTeecpuLockCmd = crate::Reg<kc_teecpu_lock_cmd::KcTeecpuLockCmdSpec>;
28649    #[doc = "TEE CPU keyslot lock command"]
28650    pub mod kc_teecpu_lock_cmd {
28651        #[doc = "Register `KC_TEECPU_LOCK_CMD` reader"]
28652        pub type R = crate::R<KcTeecpuLockCmdSpec>;
28653        #[doc = "Register `KC_TEECPU_LOCK_CMD` writer"]
28654        pub type W = crate::W<KcTeecpuLockCmdSpec>;
28655        #[doc = "Field `key_slot_num` reader - Key slot number"]
28656        pub type KeySlotNumR = crate::FieldReader<u16>;
28657        #[doc = "Field `key_slot_num` writer - Key slot number"]
28658        pub type KeySlotNumW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
28659        #[doc = "Field `lock_cmd` writer - Lock command: 0x01=REE; 0x10=TEE; 0x100=PCPU; 0x110=AIDSP"]
28660        pub type LockCmdW<'a, REG> = crate::BitWriter<'a, REG>;
28661        impl R {
28662            #[doc = "Bits 0:9 - Key slot number"]
28663            #[inline(always)]
28664            pub fn key_slot_num(&self) -> KeySlotNumR {
28665                KeySlotNumR::new((self.bits & 0x03ff) as u16)
28666            }
28667        }
28668        impl W {
28669            #[doc = "Bits 0:9 - Key slot number"]
28670            #[inline(always)]
28671            pub fn key_slot_num(&mut self) -> KeySlotNumW<'_, KcTeecpuLockCmdSpec> {
28672                KeySlotNumW::new(self, 0)
28673            }
28674            #[doc = "Bit 20 - Lock command: 0x01=REE; 0x10=TEE; 0x100=PCPU; 0x110=AIDSP"]
28675            #[inline(always)]
28676            pub fn lock_cmd(&mut self) -> LockCmdW<'_, KcTeecpuLockCmdSpec> {
28677                LockCmdW::new(self, 20)
28678            }
28679        }
28680        #[doc = "TEE CPU keyslot lock command\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_teecpu_lock_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_teecpu_lock_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28681        pub struct KcTeecpuLockCmdSpec;
28682        impl crate::RegisterSpec for KcTeecpuLockCmdSpec {
28683            type Ux = u32;
28684        }
28685        #[doc = "`read()` method returns [`kc_teecpu_lock_cmd::R`](R) reader structure"]
28686        impl crate::Readable for KcTeecpuLockCmdSpec {}
28687        #[doc = "`write(|w| ..)` method takes [`kc_teecpu_lock_cmd::W`](W) writer structure"]
28688        impl crate::Writable for KcTeecpuLockCmdSpec {
28689            type Safety = crate::Unsafe;
28690        }
28691        #[doc = "`reset()` method sets KC_TEECPU_LOCK_CMD to value 0"]
28692        impl crate::Resettable for KcTeecpuLockCmdSpec {}
28693    }
28694    #[doc = "KC_REECPU_LOCK_CMD (rw) register accessor: REE CPU keyslot lock command\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_reecpu_lock_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_reecpu_lock_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kc_reecpu_lock_cmd`] module"]
28695    #[doc(alias = "KC_REECPU_LOCK_CMD")]
28696    pub type KcReecpuLockCmd = crate::Reg<kc_reecpu_lock_cmd::KcReecpuLockCmdSpec>;
28697    #[doc = "REE CPU keyslot lock command"]
28698    pub mod kc_reecpu_lock_cmd {
28699        #[doc = "Register `KC_REECPU_LOCK_CMD` reader"]
28700        pub type R = crate::R<KcReecpuLockCmdSpec>;
28701        #[doc = "Register `KC_REECPU_LOCK_CMD` writer"]
28702        pub type W = crate::W<KcReecpuLockCmdSpec>;
28703        #[doc = "Field `key_slot_num` reader - Key slot number"]
28704        pub type KeySlotNumR = crate::FieldReader<u16>;
28705        #[doc = "Field `key_slot_num` writer - Key slot number"]
28706        pub type KeySlotNumW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
28707        #[doc = "Field `flush_hmac_kslot_ind` reader - Keyslot type: 0=mcipher; 1=HMAC"]
28708        pub type FlushHmacKslotIndR = crate::BitReader;
28709        #[doc = "Field `flush_hmac_kslot_ind` writer - Keyslot type: 0=mcipher; 1=HMAC"]
28710        pub type FlushHmacKslotIndW<'a, REG> = crate::BitWriter<'a, REG>;
28711        #[doc = "Field `tscipher_ind` reader - TSCipher indicator"]
28712        pub type TscipherIndR = crate::BitReader;
28713        #[doc = "Field `tscipher_ind` writer - TSCipher indicator"]
28714        pub type TscipherIndW<'a, REG> = crate::BitWriter<'a, REG>;
28715        #[doc = "Field `lock_cmd` writer - Lock command: 1=lock; 0=unlock"]
28716        pub type LockCmdW<'a, REG> = crate::BitWriter<'a, REG>;
28717        impl R {
28718            #[doc = "Bits 0:9 - Key slot number"]
28719            #[inline(always)]
28720            pub fn key_slot_num(&self) -> KeySlotNumR {
28721                KeySlotNumR::new((self.bits & 0x03ff) as u16)
28722            }
28723            #[doc = "Bit 15 - Keyslot type: 0=mcipher; 1=HMAC"]
28724            #[inline(always)]
28725            pub fn flush_hmac_kslot_ind(&self) -> FlushHmacKslotIndR {
28726                FlushHmacKslotIndR::new(((self.bits >> 15) & 1) != 0)
28727            }
28728            #[doc = "Bit 16 - TSCipher indicator"]
28729            #[inline(always)]
28730            pub fn tscipher_ind(&self) -> TscipherIndR {
28731                TscipherIndR::new(((self.bits >> 16) & 1) != 0)
28732            }
28733        }
28734        impl W {
28735            #[doc = "Bits 0:9 - Key slot number"]
28736            #[inline(always)]
28737            pub fn key_slot_num(&mut self) -> KeySlotNumW<'_, KcReecpuLockCmdSpec> {
28738                KeySlotNumW::new(self, 0)
28739            }
28740            #[doc = "Bit 15 - Keyslot type: 0=mcipher; 1=HMAC"]
28741            #[inline(always)]
28742            pub fn flush_hmac_kslot_ind(&mut self) -> FlushHmacKslotIndW<'_, KcReecpuLockCmdSpec> {
28743                FlushHmacKslotIndW::new(self, 15)
28744            }
28745            #[doc = "Bit 16 - TSCipher indicator"]
28746            #[inline(always)]
28747            pub fn tscipher_ind(&mut self) -> TscipherIndW<'_, KcReecpuLockCmdSpec> {
28748                TscipherIndW::new(self, 16)
28749            }
28750            #[doc = "Bit 20 - Lock command: 1=lock; 0=unlock"]
28751            #[inline(always)]
28752            pub fn lock_cmd(&mut self) -> LockCmdW<'_, KcReecpuLockCmdSpec> {
28753                LockCmdW::new(self, 20)
28754            }
28755        }
28756        #[doc = "REE CPU keyslot lock command\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_reecpu_lock_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_reecpu_lock_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28757        pub struct KcReecpuLockCmdSpec;
28758        impl crate::RegisterSpec for KcReecpuLockCmdSpec {
28759            type Ux = u32;
28760        }
28761        #[doc = "`read()` method returns [`kc_reecpu_lock_cmd::R`](R) reader structure"]
28762        impl crate::Readable for KcReecpuLockCmdSpec {}
28763        #[doc = "`write(|w| ..)` method takes [`kc_reecpu_lock_cmd::W`](W) writer structure"]
28764        impl crate::Writable for KcReecpuLockCmdSpec {
28765            type Safety = crate::Unsafe;
28766        }
28767        #[doc = "`reset()` method sets KC_REECPU_LOCK_CMD to value 0"]
28768        impl crate::Resettable for KcReecpuLockCmdSpec {}
28769    }
28770    #[doc = "KC_PCPU_LOCK_CMD (rw) register accessor: PCPU keyslot lock command\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_pcpu_lock_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_pcpu_lock_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kc_pcpu_lock_cmd`] module"]
28771    #[doc(alias = "KC_PCPU_LOCK_CMD")]
28772    pub type KcPcpuLockCmd = crate::Reg<kc_pcpu_lock_cmd::KcPcpuLockCmdSpec>;
28773    #[doc = "PCPU keyslot lock command"]
28774    pub mod kc_pcpu_lock_cmd {
28775        #[doc = "Register `KC_PCPU_LOCK_CMD` reader"]
28776        pub type R = crate::R<KcPcpuLockCmdSpec>;
28777        #[doc = "Register `KC_PCPU_LOCK_CMD` writer"]
28778        pub type W = crate::W<KcPcpuLockCmdSpec>;
28779        #[doc = "Field `key_slot_num` reader - Key slot number"]
28780        pub type KeySlotNumR = crate::FieldReader<u16>;
28781        #[doc = "Field `key_slot_num` writer - Key slot number"]
28782        pub type KeySlotNumW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
28783        #[doc = "Field `flush_hmac_kslot_ind` reader - Keyslot type: 0=mcipher; 1=HMAC"]
28784        pub type FlushHmacKslotIndR = crate::BitReader;
28785        #[doc = "Field `flush_hmac_kslot_ind` writer - Keyslot type: 0=mcipher; 1=HMAC"]
28786        pub type FlushHmacKslotIndW<'a, REG> = crate::BitWriter<'a, REG>;
28787        #[doc = "Field `tscipher_ind` reader - TSCipher indicator"]
28788        pub type TscipherIndR = crate::BitReader;
28789        #[doc = "Field `tscipher_ind` writer - TSCipher indicator"]
28790        pub type TscipherIndW<'a, REG> = crate::BitWriter<'a, REG>;
28791        #[doc = "Field `lock_cmd` writer - Lock command: 1=lock; 0=unlock"]
28792        pub type LockCmdW<'a, REG> = crate::BitWriter<'a, REG>;
28793        impl R {
28794            #[doc = "Bits 0:9 - Key slot number"]
28795            #[inline(always)]
28796            pub fn key_slot_num(&self) -> KeySlotNumR {
28797                KeySlotNumR::new((self.bits & 0x03ff) as u16)
28798            }
28799            #[doc = "Bit 15 - Keyslot type: 0=mcipher; 1=HMAC"]
28800            #[inline(always)]
28801            pub fn flush_hmac_kslot_ind(&self) -> FlushHmacKslotIndR {
28802                FlushHmacKslotIndR::new(((self.bits >> 15) & 1) != 0)
28803            }
28804            #[doc = "Bit 16 - TSCipher indicator"]
28805            #[inline(always)]
28806            pub fn tscipher_ind(&self) -> TscipherIndR {
28807                TscipherIndR::new(((self.bits >> 16) & 1) != 0)
28808            }
28809        }
28810        impl W {
28811            #[doc = "Bits 0:9 - Key slot number"]
28812            #[inline(always)]
28813            pub fn key_slot_num(&mut self) -> KeySlotNumW<'_, KcPcpuLockCmdSpec> {
28814                KeySlotNumW::new(self, 0)
28815            }
28816            #[doc = "Bit 15 - Keyslot type: 0=mcipher; 1=HMAC"]
28817            #[inline(always)]
28818            pub fn flush_hmac_kslot_ind(&mut self) -> FlushHmacKslotIndW<'_, KcPcpuLockCmdSpec> {
28819                FlushHmacKslotIndW::new(self, 15)
28820            }
28821            #[doc = "Bit 16 - TSCipher indicator"]
28822            #[inline(always)]
28823            pub fn tscipher_ind(&mut self) -> TscipherIndW<'_, KcPcpuLockCmdSpec> {
28824                TscipherIndW::new(self, 16)
28825            }
28826            #[doc = "Bit 20 - Lock command: 1=lock; 0=unlock"]
28827            #[inline(always)]
28828            pub fn lock_cmd(&mut self) -> LockCmdW<'_, KcPcpuLockCmdSpec> {
28829                LockCmdW::new(self, 20)
28830            }
28831        }
28832        #[doc = "PCPU keyslot lock command\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_pcpu_lock_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_pcpu_lock_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28833        pub struct KcPcpuLockCmdSpec;
28834        impl crate::RegisterSpec for KcPcpuLockCmdSpec {
28835            type Ux = u32;
28836        }
28837        #[doc = "`read()` method returns [`kc_pcpu_lock_cmd::R`](R) reader structure"]
28838        impl crate::Readable for KcPcpuLockCmdSpec {}
28839        #[doc = "`write(|w| ..)` method takes [`kc_pcpu_lock_cmd::W`](W) writer structure"]
28840        impl crate::Writable for KcPcpuLockCmdSpec {
28841            type Safety = crate::Unsafe;
28842        }
28843        #[doc = "`reset()` method sets KC_PCPU_LOCK_CMD to value 0"]
28844        impl crate::Resettable for KcPcpuLockCmdSpec {}
28845    }
28846    #[doc = "KC_AIDSP_LOCK_CMD (rw) register accessor: AIDSP keyslot lock command\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_aidsp_lock_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_aidsp_lock_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kc_aidsp_lock_cmd`] module"]
28847    #[doc(alias = "KC_AIDSP_LOCK_CMD")]
28848    pub type KcAidspLockCmd = crate::Reg<kc_aidsp_lock_cmd::KcAidspLockCmdSpec>;
28849    #[doc = "AIDSP keyslot lock command"]
28850    pub mod kc_aidsp_lock_cmd {
28851        #[doc = "Register `KC_AIDSP_LOCK_CMD` reader"]
28852        pub type R = crate::R<KcAidspLockCmdSpec>;
28853        #[doc = "Register `KC_AIDSP_LOCK_CMD` writer"]
28854        pub type W = crate::W<KcAidspLockCmdSpec>;
28855        #[doc = "Field `key_slot_num` reader - Key slot number"]
28856        pub type KeySlotNumR = crate::FieldReader<u16>;
28857        #[doc = "Field `key_slot_num` writer - Key slot number"]
28858        pub type KeySlotNumW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
28859        #[doc = "Field `flush_hmac_kslot_ind` reader - Keyslot type: 0=mcipher; 1=HMAC"]
28860        pub type FlushHmacKslotIndR = crate::BitReader;
28861        #[doc = "Field `flush_hmac_kslot_ind` writer - Keyslot type: 0=mcipher; 1=HMAC"]
28862        pub type FlushHmacKslotIndW<'a, REG> = crate::BitWriter<'a, REG>;
28863        #[doc = "Field `tscipher_ind` reader - TSCipher indicator"]
28864        pub type TscipherIndR = crate::BitReader;
28865        #[doc = "Field `tscipher_ind` writer - TSCipher indicator"]
28866        pub type TscipherIndW<'a, REG> = crate::BitWriter<'a, REG>;
28867        #[doc = "Field `lock_cmd` writer - Lock command: 1=lock; 0=unlock"]
28868        pub type LockCmdW<'a, REG> = crate::BitWriter<'a, REG>;
28869        impl R {
28870            #[doc = "Bits 0:9 - Key slot number"]
28871            #[inline(always)]
28872            pub fn key_slot_num(&self) -> KeySlotNumR {
28873                KeySlotNumR::new((self.bits & 0x03ff) as u16)
28874            }
28875            #[doc = "Bit 15 - Keyslot type: 0=mcipher; 1=HMAC"]
28876            #[inline(always)]
28877            pub fn flush_hmac_kslot_ind(&self) -> FlushHmacKslotIndR {
28878                FlushHmacKslotIndR::new(((self.bits >> 15) & 1) != 0)
28879            }
28880            #[doc = "Bit 16 - TSCipher indicator"]
28881            #[inline(always)]
28882            pub fn tscipher_ind(&self) -> TscipherIndR {
28883                TscipherIndR::new(((self.bits >> 16) & 1) != 0)
28884            }
28885        }
28886        impl W {
28887            #[doc = "Bits 0:9 - Key slot number"]
28888            #[inline(always)]
28889            pub fn key_slot_num(&mut self) -> KeySlotNumW<'_, KcAidspLockCmdSpec> {
28890                KeySlotNumW::new(self, 0)
28891            }
28892            #[doc = "Bit 15 - Keyslot type: 0=mcipher; 1=HMAC"]
28893            #[inline(always)]
28894            pub fn flush_hmac_kslot_ind(&mut self) -> FlushHmacKslotIndW<'_, KcAidspLockCmdSpec> {
28895                FlushHmacKslotIndW::new(self, 15)
28896            }
28897            #[doc = "Bit 16 - TSCipher indicator"]
28898            #[inline(always)]
28899            pub fn tscipher_ind(&mut self) -> TscipherIndW<'_, KcAidspLockCmdSpec> {
28900                TscipherIndW::new(self, 16)
28901            }
28902            #[doc = "Bit 20 - Lock command: 1=lock; 0=unlock"]
28903            #[inline(always)]
28904            pub fn lock_cmd(&mut self) -> LockCmdW<'_, KcAidspLockCmdSpec> {
28905                LockCmdW::new(self, 20)
28906            }
28907        }
28908        #[doc = "AIDSP keyslot lock command\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_aidsp_lock_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_aidsp_lock_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28909        pub struct KcAidspLockCmdSpec;
28910        impl crate::RegisterSpec for KcAidspLockCmdSpec {
28911            type Ux = u32;
28912        }
28913        #[doc = "`read()` method returns [`kc_aidsp_lock_cmd::R`](R) reader structure"]
28914        impl crate::Readable for KcAidspLockCmdSpec {}
28915        #[doc = "`write(|w| ..)` method takes [`kc_aidsp_lock_cmd::W`](W) writer structure"]
28916        impl crate::Writable for KcAidspLockCmdSpec {
28917            type Safety = crate::Unsafe;
28918        }
28919        #[doc = "`reset()` method sets KC_AIDSP_LOCK_CMD to value 0"]
28920        impl crate::Resettable for KcAidspLockCmdSpec {}
28921    }
28922    #[doc = "KC_RD_SLOT_NUM (rw) register accessor: Keyslot query slot number selection\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_rd_slot_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_rd_slot_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kc_rd_slot_num`] module"]
28923    #[doc(alias = "KC_RD_SLOT_NUM")]
28924    pub type KcRdSlotNum = crate::Reg<kc_rd_slot_num::KcRdSlotNumSpec>;
28925    #[doc = "Keyslot query slot number selection"]
28926    pub mod kc_rd_slot_num {
28927        #[doc = "Register `KC_RD_SLOT_NUM` reader"]
28928        pub type R = crate::R<KcRdSlotNumSpec>;
28929        #[doc = "Register `KC_RD_SLOT_NUM` writer"]
28930        pub type W = crate::W<KcRdSlotNumSpec>;
28931        #[doc = "Field `slot_num_cfg` reader - Slot number to query (0-255)"]
28932        pub type SlotNumCfgR = crate::FieldReader<u16>;
28933        #[doc = "Field `slot_num_cfg` writer - Slot number to query (0-255)"]
28934        pub type SlotNumCfgW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
28935        #[doc = "Field `slot_cfg_type` reader - Keyslot type: 0=mcipher; 1=HMAC"]
28936        pub type SlotCfgTypeR = crate::BitReader;
28937        #[doc = "Field `slot_cfg_type` writer - Keyslot type: 0=mcipher; 1=HMAC"]
28938        pub type SlotCfgTypeW<'a, REG> = crate::BitWriter<'a, REG>;
28939        #[doc = "Field `tscipher_slot_ind` reader - TSCipher slot indicator"]
28940        pub type TscipherSlotIndR = crate::BitReader;
28941        #[doc = "Field `tscipher_slot_ind` writer - TSCipher slot indicator"]
28942        pub type TscipherSlotIndW<'a, REG> = crate::BitWriter<'a, REG>;
28943        impl R {
28944            #[doc = "Bits 0:9 - Slot number to query (0-255)"]
28945            #[inline(always)]
28946            pub fn slot_num_cfg(&self) -> SlotNumCfgR {
28947                SlotNumCfgR::new((self.bits & 0x03ff) as u16)
28948            }
28949            #[doc = "Bit 15 - Keyslot type: 0=mcipher; 1=HMAC"]
28950            #[inline(always)]
28951            pub fn slot_cfg_type(&self) -> SlotCfgTypeR {
28952                SlotCfgTypeR::new(((self.bits >> 15) & 1) != 0)
28953            }
28954            #[doc = "Bit 16 - TSCipher slot indicator"]
28955            #[inline(always)]
28956            pub fn tscipher_slot_ind(&self) -> TscipherSlotIndR {
28957                TscipherSlotIndR::new(((self.bits >> 16) & 1) != 0)
28958            }
28959        }
28960        impl W {
28961            #[doc = "Bits 0:9 - Slot number to query (0-255)"]
28962            #[inline(always)]
28963            pub fn slot_num_cfg(&mut self) -> SlotNumCfgW<'_, KcRdSlotNumSpec> {
28964                SlotNumCfgW::new(self, 0)
28965            }
28966            #[doc = "Bit 15 - Keyslot type: 0=mcipher; 1=HMAC"]
28967            #[inline(always)]
28968            pub fn slot_cfg_type(&mut self) -> SlotCfgTypeW<'_, KcRdSlotNumSpec> {
28969                SlotCfgTypeW::new(self, 15)
28970            }
28971            #[doc = "Bit 16 - TSCipher slot indicator"]
28972            #[inline(always)]
28973            pub fn tscipher_slot_ind(&mut self) -> TscipherSlotIndW<'_, KcRdSlotNumSpec> {
28974                TscipherSlotIndW::new(self, 16)
28975            }
28976        }
28977        #[doc = "Keyslot query slot number selection\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_rd_slot_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_rd_slot_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28978        pub struct KcRdSlotNumSpec;
28979        impl crate::RegisterSpec for KcRdSlotNumSpec {
28980            type Ux = u32;
28981        }
28982        #[doc = "`read()` method returns [`kc_rd_slot_num::R`](R) reader structure"]
28983        impl crate::Readable for KcRdSlotNumSpec {}
28984        #[doc = "`write(|w| ..)` method takes [`kc_rd_slot_num::W`](W) writer structure"]
28985        impl crate::Writable for KcRdSlotNumSpec {
28986            type Safety = crate::Unsafe;
28987        }
28988        #[doc = "`reset()` method sets KC_RD_SLOT_NUM to value 0"]
28989        impl crate::Resettable for KcRdSlotNumSpec {}
28990    }
28991    #[doc = "KC_RD_LOCK_STATUS (rw) register accessor: Keyslot lock status readback\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_rd_lock_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_rd_lock_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kc_rd_lock_status`] module"]
28992    #[doc(alias = "KC_RD_LOCK_STATUS")]
28993    pub type KcRdLockStatus = crate::Reg<kc_rd_lock_status::KcRdLockStatusSpec>;
28994    #[doc = "Keyslot lock status readback"]
28995    pub mod kc_rd_lock_status {
28996        #[doc = "Register `KC_RD_LOCK_STATUS` reader"]
28997        pub type R = crate::R<KcRdLockStatusSpec>;
28998        #[doc = "Register `KC_RD_LOCK_STATUS` writer"]
28999        pub type W = crate::W<KcRdLockStatusSpec>;
29000        #[doc = "Field `rd_lock_status` reader - Lock status: 0=unlock; 1=REE; 2=TEE; 4=PCPU; 6=AIDSP"]
29001        pub type RdLockStatusR = crate::FieldReader;
29002        impl R {
29003            #[doc = "Bits 0:2 - Lock status: 0=unlock; 1=REE; 2=TEE; 4=PCPU; 6=AIDSP"]
29004            #[inline(always)]
29005            pub fn rd_lock_status(&self) -> RdLockStatusR {
29006                RdLockStatusR::new((self.bits & 7) as u8)
29007            }
29008        }
29009        impl W {}
29010        #[doc = "Keyslot lock status readback\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_rd_lock_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_rd_lock_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29011        pub struct KcRdLockStatusSpec;
29012        impl crate::RegisterSpec for KcRdLockStatusSpec {
29013            type Ux = u32;
29014        }
29015        #[doc = "`read()` method returns [`kc_rd_lock_status::R`](R) reader structure"]
29016        impl crate::Readable for KcRdLockStatusSpec {}
29017        #[doc = "`write(|w| ..)` method takes [`kc_rd_lock_status::W`](W) writer structure"]
29018        impl crate::Writable for KcRdLockStatusSpec {
29019            type Safety = crate::Unsafe;
29020        }
29021        #[doc = "`reset()` method sets KC_RD_LOCK_STATUS to value 0"]
29022        impl crate::Resettable for KcRdLockStatusSpec {}
29023    }
29024}
29025#[doc = "True Random Number Generator"]
29026pub type Trng = crate::Periph<trng::RegisterBlock, 0x4411_4000>;
29027impl core::fmt::Debug for Trng {
29028    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
29029        f.debug_struct("Trng").finish()
29030    }
29031}
29032#[doc = "True Random Number Generator"]
29033pub mod trng {
29034    #[repr(C)]
29035    #[doc = "Register block"]
29036    pub struct RegisterBlock {
29037        _reserved0: [u8; 0x0100],
29038        trng_fifo_data: TrngFifoData,
29039        trng_fifo_ready: TrngFifoReady,
29040        trng_data_st: TrngDataSt,
29041        _reserved3: [u8; 0x68],
29042        trng_fro_sample_clk_sel: TrngFroSampleClkSel,
29043        trng_fro_div_cnt: TrngFroDivCnt,
29044    }
29045    impl RegisterBlock {
29046        #[doc = "0x100 - TRNG FIFO data output register"]
29047        #[inline(always)]
29048        pub const fn trng_fifo_data(&self) -> &TrngFifoData {
29049            &self.trng_fifo_data
29050        }
29051        #[doc = "0x104 - TRNG FIFO ready status"]
29052        #[inline(always)]
29053        pub const fn trng_fifo_ready(&self) -> &TrngFifoReady {
29054            &self.trng_fifo_ready
29055        }
29056        #[doc = "0x108 - TRNG data status register"]
29057        #[inline(always)]
29058        pub const fn trng_data_st(&self) -> &TrngDataSt {
29059            &self.trng_data_st
29060        }
29061        #[doc = "0x174 - TRNG FRO sample clock select"]
29062        #[inline(always)]
29063        pub const fn trng_fro_sample_clk_sel(&self) -> &TrngFroSampleClkSel {
29064            &self.trng_fro_sample_clk_sel
29065        }
29066        #[doc = "0x178 - TRNG FRO divider count"]
29067        #[inline(always)]
29068        pub const fn trng_fro_div_cnt(&self) -> &TrngFroDivCnt {
29069            &self.trng_fro_div_cnt
29070        }
29071    }
29072    #[doc = "TRNG_FIFO_DATA (rw) register accessor: TRNG FIFO data output register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fifo_data`] module"]
29073    #[doc(alias = "TRNG_FIFO_DATA")]
29074    pub type TrngFifoData = crate::Reg<trng_fifo_data::TrngFifoDataSpec>;
29075    #[doc = "TRNG FIFO data output register"]
29076    pub mod trng_fifo_data {
29077        #[doc = "Register `TRNG_FIFO_DATA` reader"]
29078        pub type R = crate::R<TrngFifoDataSpec>;
29079        #[doc = "Register `TRNG_FIFO_DATA` writer"]
29080        pub type W = crate::W<TrngFifoDataSpec>;
29081        #[doc = "Field `trng_data` reader - Random data (read to get random number)"]
29082        pub type TrngDataR = crate::FieldReader<u32>;
29083        impl R {
29084            #[doc = "Bits 0:31 - Random data (read to get random number)"]
29085            #[inline(always)]
29086            pub fn trng_data(&self) -> TrngDataR {
29087                TrngDataR::new(self.bits)
29088            }
29089        }
29090        impl W {}
29091        #[doc = "TRNG FIFO data output register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29092        pub struct TrngFifoDataSpec;
29093        impl crate::RegisterSpec for TrngFifoDataSpec {
29094            type Ux = u32;
29095        }
29096        #[doc = "`read()` method returns [`trng_fifo_data::R`](R) reader structure"]
29097        impl crate::Readable for TrngFifoDataSpec {}
29098        #[doc = "`write(|w| ..)` method takes [`trng_fifo_data::W`](W) writer structure"]
29099        impl crate::Writable for TrngFifoDataSpec {
29100            type Safety = crate::Unsafe;
29101        }
29102        #[doc = "`reset()` method sets TRNG_FIFO_DATA to value 0"]
29103        impl crate::Resettable for TrngFifoDataSpec {}
29104    }
29105    #[doc = "TRNG_FIFO_READY (rw) register accessor: TRNG FIFO ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_ready::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_ready::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fifo_ready`] module"]
29106    #[doc(alias = "TRNG_FIFO_READY")]
29107    pub type TrngFifoReady = crate::Reg<trng_fifo_ready::TrngFifoReadySpec>;
29108    #[doc = "TRNG FIFO ready status"]
29109    pub mod trng_fifo_ready {
29110        #[doc = "Register `TRNG_FIFO_READY` reader"]
29111        pub type R = crate::R<TrngFifoReadySpec>;
29112        #[doc = "Register `TRNG_FIFO_READY` writer"]
29113        pub type W = crate::W<TrngFifoReadySpec>;
29114        #[doc = "Field `trng_data_ready` reader - Data ready: 1=data available in FIFO"]
29115        pub type TrngDataReadyR = crate::BitReader;
29116        #[doc = "Field `trng_done` reader - TRNG generation done"]
29117        pub type TrngDoneR = crate::BitReader;
29118        impl R {
29119            #[doc = "Bit 0 - Data ready: 1=data available in FIFO"]
29120            #[inline(always)]
29121            pub fn trng_data_ready(&self) -> TrngDataReadyR {
29122                TrngDataReadyR::new((self.bits & 1) != 0)
29123            }
29124            #[doc = "Bit 1 - TRNG generation done"]
29125            #[inline(always)]
29126            pub fn trng_done(&self) -> TrngDoneR {
29127                TrngDoneR::new(((self.bits >> 1) & 1) != 0)
29128            }
29129        }
29130        impl W {}
29131        #[doc = "TRNG FIFO ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_ready::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_ready::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29132        pub struct TrngFifoReadySpec;
29133        impl crate::RegisterSpec for TrngFifoReadySpec {
29134            type Ux = u32;
29135        }
29136        #[doc = "`read()` method returns [`trng_fifo_ready::R`](R) reader structure"]
29137        impl crate::Readable for TrngFifoReadySpec {}
29138        #[doc = "`write(|w| ..)` method takes [`trng_fifo_ready::W`](W) writer structure"]
29139        impl crate::Writable for TrngFifoReadySpec {
29140            type Safety = crate::Unsafe;
29141        }
29142        #[doc = "`reset()` method sets TRNG_FIFO_READY to value 0"]
29143        impl crate::Resettable for TrngFifoReadySpec {}
29144    }
29145    #[doc = "TRNG_DATA_ST (rw) register accessor: TRNG data status register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_data_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_data_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_data_st`] module"]
29146    #[doc(alias = "TRNG_DATA_ST")]
29147    pub type TrngDataSt = crate::Reg<trng_data_st::TrngDataStSpec>;
29148    #[doc = "TRNG data status register"]
29149    pub mod trng_data_st {
29150        #[doc = "Register `TRNG_DATA_ST` reader"]
29151        pub type R = crate::R<TrngDataStSpec>;
29152        #[doc = "Register `TRNG_DATA_ST` writer"]
29153        pub type W = crate::W<TrngDataStSpec>;
29154        #[doc = "Field `data_st` reader - Data status"]
29155        pub type DataStR = crate::FieldReader<u32>;
29156        impl R {
29157            #[doc = "Bits 0:31 - Data status"]
29158            #[inline(always)]
29159            pub fn data_st(&self) -> DataStR {
29160                DataStR::new(self.bits)
29161            }
29162        }
29163        impl W {}
29164        #[doc = "TRNG data status register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_data_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_data_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29165        pub struct TrngDataStSpec;
29166        impl crate::RegisterSpec for TrngDataStSpec {
29167            type Ux = u32;
29168        }
29169        #[doc = "`read()` method returns [`trng_data_st::R`](R) reader structure"]
29170        impl crate::Readable for TrngDataStSpec {}
29171        #[doc = "`write(|w| ..)` method takes [`trng_data_st::W`](W) writer structure"]
29172        impl crate::Writable for TrngDataStSpec {
29173            type Safety = crate::Unsafe;
29174        }
29175        #[doc = "`reset()` method sets TRNG_DATA_ST to value 0"]
29176        impl crate::Resettable for TrngDataStSpec {}
29177    }
29178    #[doc = "TRNG_FRO_SAMPLE_CLK_SEL (rw) register accessor: TRNG FRO sample clock select\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_sample_clk_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_sample_clk_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fro_sample_clk_sel`] module"]
29179    #[doc(alias = "TRNG_FRO_SAMPLE_CLK_SEL")]
29180    pub type TrngFroSampleClkSel = crate::Reg<trng_fro_sample_clk_sel::TrngFroSampleClkSelSpec>;
29181    #[doc = "TRNG FRO sample clock select"]
29182    pub mod trng_fro_sample_clk_sel {
29183        #[doc = "Register `TRNG_FRO_SAMPLE_CLK_SEL` reader"]
29184        pub type R = crate::R<TrngFroSampleClkSelSpec>;
29185        #[doc = "Register `TRNG_FRO_SAMPLE_CLK_SEL` writer"]
29186        pub type W = crate::W<TrngFroSampleClkSelSpec>;
29187        #[doc = "Field `fro_sample_clk_sel` reader - FRO sample clock select: 0=inner; 1=external"]
29188        pub type FroSampleClkSelR = crate::BitReader;
29189        #[doc = "Field `fro_sample_clk_sel` writer - FRO sample clock select: 0=inner; 1=external"]
29190        pub type FroSampleClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
29191        impl R {
29192            #[doc = "Bit 0 - FRO sample clock select: 0=inner; 1=external"]
29193            #[inline(always)]
29194            pub fn fro_sample_clk_sel(&self) -> FroSampleClkSelR {
29195                FroSampleClkSelR::new((self.bits & 1) != 0)
29196            }
29197        }
29198        impl W {
29199            #[doc = "Bit 0 - FRO sample clock select: 0=inner; 1=external"]
29200            #[inline(always)]
29201            pub fn fro_sample_clk_sel(&mut self) -> FroSampleClkSelW<'_, TrngFroSampleClkSelSpec> {
29202                FroSampleClkSelW::new(self, 0)
29203            }
29204        }
29205        #[doc = "TRNG FRO sample clock select\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_sample_clk_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_sample_clk_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29206        pub struct TrngFroSampleClkSelSpec;
29207        impl crate::RegisterSpec for TrngFroSampleClkSelSpec {
29208            type Ux = u32;
29209        }
29210        #[doc = "`read()` method returns [`trng_fro_sample_clk_sel::R`](R) reader structure"]
29211        impl crate::Readable for TrngFroSampleClkSelSpec {}
29212        #[doc = "`write(|w| ..)` method takes [`trng_fro_sample_clk_sel::W`](W) writer structure"]
29213        impl crate::Writable for TrngFroSampleClkSelSpec {
29214            type Safety = crate::Unsafe;
29215        }
29216        #[doc = "`reset()` method sets TRNG_FRO_SAMPLE_CLK_SEL to value 0"]
29217        impl crate::Resettable for TrngFroSampleClkSelSpec {}
29218    }
29219    #[doc = "TRNG_FRO_DIV_CNT (rw) register accessor: TRNG FRO divider count\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_div_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_div_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fro_div_cnt`] module"]
29220    #[doc(alias = "TRNG_FRO_DIV_CNT")]
29221    pub type TrngFroDivCnt = crate::Reg<trng_fro_div_cnt::TrngFroDivCntSpec>;
29222    #[doc = "TRNG FRO divider count"]
29223    pub mod trng_fro_div_cnt {
29224        #[doc = "Register `TRNG_FRO_DIV_CNT` reader"]
29225        pub type R = crate::R<TrngFroDivCntSpec>;
29226        #[doc = "Register `TRNG_FRO_DIV_CNT` writer"]
29227        pub type W = crate::W<TrngFroDivCntSpec>;
29228        #[doc = "Field `fro_div_cnt` reader - FRO divider count (default 0x1b)"]
29229        pub type FroDivCntR = crate::FieldReader;
29230        #[doc = "Field `fro_div_cnt` writer - FRO divider count (default 0x1b)"]
29231        pub type FroDivCntW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
29232        impl R {
29233            #[doc = "Bits 0:7 - FRO divider count (default 0x1b)"]
29234            #[inline(always)]
29235            pub fn fro_div_cnt(&self) -> FroDivCntR {
29236                FroDivCntR::new((self.bits & 0xff) as u8)
29237            }
29238        }
29239        impl W {
29240            #[doc = "Bits 0:7 - FRO divider count (default 0x1b)"]
29241            #[inline(always)]
29242            pub fn fro_div_cnt(&mut self) -> FroDivCntW<'_, TrngFroDivCntSpec> {
29243                FroDivCntW::new(self, 0)
29244            }
29245        }
29246        #[doc = "TRNG FRO divider count\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_div_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_div_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29247        pub struct TrngFroDivCntSpec;
29248        impl crate::RegisterSpec for TrngFroDivCntSpec {
29249            type Ux = u32;
29250        }
29251        #[doc = "`read()` method returns [`trng_fro_div_cnt::R`](R) reader structure"]
29252        impl crate::Readable for TrngFroDivCntSpec {}
29253        #[doc = "`write(|w| ..)` method takes [`trng_fro_div_cnt::W`](W) writer structure"]
29254        impl crate::Writable for TrngFroDivCntSpec {
29255            type Safety = crate::Unsafe;
29256        }
29257        #[doc = "`reset()` method sets TRNG_FRO_DIV_CNT to value 0"]
29258        impl crate::Resettable for TrngFroDivCntSpec {}
29259    }
29260}
29261#[doc = "TCXO 64-bit free-running counter (v150)"]
29262pub type Tcxo = crate::Periph<tcxo::RegisterBlock, 0x4400_04c0>;
29263impl core::fmt::Debug for Tcxo {
29264    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
29265        f.debug_struct("Tcxo").finish()
29266    }
29267}
29268#[doc = "TCXO 64-bit free-running counter (v150)"]
29269pub mod tcxo {
29270    #[repr(C)]
29271    #[doc = "Register block"]
29272    pub struct RegisterBlock {
29273        tcxo_status: TcxoStatus,
29274        tcxo_count0: TcxoCount0,
29275        tcxo_count1: TcxoCount1,
29276        tcxo_count2: TcxoCount2,
29277        tcxo_count3: TcxoCount3,
29278    }
29279    impl RegisterBlock {
29280        #[doc = "0x00 - TCXO status and control register"]
29281        #[inline(always)]
29282        pub const fn tcxo_status(&self) -> &TcxoStatus {
29283            &self.tcxo_status
29284        }
29285        #[doc = "0x04 - TCXO count bits \\[15:0\\]"]
29286        #[inline(always)]
29287        pub const fn tcxo_count0(&self) -> &TcxoCount0 {
29288            &self.tcxo_count0
29289        }
29290        #[doc = "0x08 - TCXO count bits \\[31:16\\]"]
29291        #[inline(always)]
29292        pub const fn tcxo_count1(&self) -> &TcxoCount1 {
29293            &self.tcxo_count1
29294        }
29295        #[doc = "0x0c - TCXO count bits \\[47:32\\]"]
29296        #[inline(always)]
29297        pub const fn tcxo_count2(&self) -> &TcxoCount2 {
29298            &self.tcxo_count2
29299        }
29300        #[doc = "0x10 - TCXO count bits \\[63:48\\]"]
29301        #[inline(always)]
29302        pub const fn tcxo_count3(&self) -> &TcxoCount3 {
29303            &self.tcxo_count3
29304        }
29305    }
29306    #[doc = "TCXO_STATUS (rw) register accessor: TCXO status and control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_status`] module"]
29307    #[doc(alias = "TCXO_STATUS")]
29308    pub type TcxoStatus = crate::Reg<tcxo_status::TcxoStatusSpec>;
29309    #[doc = "TCXO status and control register"]
29310    pub mod tcxo_status {
29311        #[doc = "Register `TCXO_STATUS` reader"]
29312        pub type R = crate::R<TcxoStatusSpec>;
29313        #[doc = "Register `TCXO_STATUS` writer"]
29314        pub type W = crate::W<TcxoStatusSpec>;
29315        #[doc = "Field `refresh` reader - TCXO count refresh: 1=trigger count latch"]
29316        pub type RefreshR = crate::BitReader;
29317        #[doc = "Field `refresh` writer - TCXO count refresh: 1=trigger count latch"]
29318        pub type RefreshW<'a, REG> = crate::BitWriter<'a, REG>;
29319        #[doc = "Field `clear` reader - TCXO count clear: 1=clear counter"]
29320        pub type ClearR = crate::BitReader;
29321        #[doc = "Field `clear` writer - TCXO count clear: 1=clear counter"]
29322        pub type ClearW<'a, REG> = crate::BitWriter<'a, REG>;
29323        #[doc = "Field `enable` reader - TCXO count enable: 1=enable counting"]
29324        pub type EnableR = crate::BitReader;
29325        #[doc = "Field `enable` writer - TCXO count enable: 1=enable counting"]
29326        pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
29327        #[doc = "Field `valid` reader - TCXO count value valid flag"]
29328        pub type ValidR = crate::BitReader;
29329        impl R {
29330            #[doc = "Bit 0 - TCXO count refresh: 1=trigger count latch"]
29331            #[inline(always)]
29332            pub fn refresh(&self) -> RefreshR {
29333                RefreshR::new((self.bits & 1) != 0)
29334            }
29335            #[doc = "Bit 1 - TCXO count clear: 1=clear counter"]
29336            #[inline(always)]
29337            pub fn clear(&self) -> ClearR {
29338                ClearR::new(((self.bits >> 1) & 1) != 0)
29339            }
29340            #[doc = "Bit 2 - TCXO count enable: 1=enable counting"]
29341            #[inline(always)]
29342            pub fn enable(&self) -> EnableR {
29343                EnableR::new(((self.bits >> 2) & 1) != 0)
29344            }
29345            #[doc = "Bit 4 - TCXO count value valid flag"]
29346            #[inline(always)]
29347            pub fn valid(&self) -> ValidR {
29348                ValidR::new(((self.bits >> 4) & 1) != 0)
29349            }
29350        }
29351        impl W {
29352            #[doc = "Bit 0 - TCXO count refresh: 1=trigger count latch"]
29353            #[inline(always)]
29354            pub fn refresh(&mut self) -> RefreshW<'_, TcxoStatusSpec> {
29355                RefreshW::new(self, 0)
29356            }
29357            #[doc = "Bit 1 - TCXO count clear: 1=clear counter"]
29358            #[inline(always)]
29359            pub fn clear(&mut self) -> ClearW<'_, TcxoStatusSpec> {
29360                ClearW::new(self, 1)
29361            }
29362            #[doc = "Bit 2 - TCXO count enable: 1=enable counting"]
29363            #[inline(always)]
29364            pub fn enable(&mut self) -> EnableW<'_, TcxoStatusSpec> {
29365                EnableW::new(self, 2)
29366            }
29367        }
29368        #[doc = "TCXO status and control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29369        pub struct TcxoStatusSpec;
29370        impl crate::RegisterSpec for TcxoStatusSpec {
29371            type Ux = u32;
29372        }
29373        #[doc = "`read()` method returns [`tcxo_status::R`](R) reader structure"]
29374        impl crate::Readable for TcxoStatusSpec {}
29375        #[doc = "`write(|w| ..)` method takes [`tcxo_status::W`](W) writer structure"]
29376        impl crate::Writable for TcxoStatusSpec {
29377            type Safety = crate::Unsafe;
29378        }
29379        #[doc = "`reset()` method sets TCXO_STATUS to value 0"]
29380        impl crate::Resettable for TcxoStatusSpec {}
29381    }
29382    #[doc = "TCXO_COUNT0 (rw) register accessor: TCXO count bits \\[15:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count0`] module"]
29383    #[doc(alias = "TCXO_COUNT0")]
29384    pub type TcxoCount0 = crate::Reg<tcxo_count0::TcxoCount0Spec>;
29385    #[doc = "TCXO count bits \\[15:0\\]"]
29386    pub mod tcxo_count0 {
29387        #[doc = "Register `TCXO_COUNT0` reader"]
29388        pub type R = crate::R<TcxoCount0Spec>;
29389        #[doc = "Register `TCXO_COUNT0` writer"]
29390        pub type W = crate::W<TcxoCount0Spec>;
29391        #[doc = "Field `count0` reader - Counter value bits \\[15:0\\]"]
29392        pub type Count0R = crate::FieldReader<u16>;
29393        impl R {
29394            #[doc = "Bits 0:15 - Counter value bits \\[15:0\\]"]
29395            #[inline(always)]
29396            pub fn count0(&self) -> Count0R {
29397                Count0R::new((self.bits & 0xffff) as u16)
29398            }
29399        }
29400        impl W {}
29401        #[doc = "TCXO count bits \\[15:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29402        pub struct TcxoCount0Spec;
29403        impl crate::RegisterSpec for TcxoCount0Spec {
29404            type Ux = u32;
29405        }
29406        #[doc = "`read()` method returns [`tcxo_count0::R`](R) reader structure"]
29407        impl crate::Readable for TcxoCount0Spec {}
29408        #[doc = "`write(|w| ..)` method takes [`tcxo_count0::W`](W) writer structure"]
29409        impl crate::Writable for TcxoCount0Spec {
29410            type Safety = crate::Unsafe;
29411        }
29412        #[doc = "`reset()` method sets TCXO_COUNT0 to value 0"]
29413        impl crate::Resettable for TcxoCount0Spec {}
29414    }
29415    #[doc = "TCXO_COUNT1 (rw) register accessor: TCXO count bits \\[31:16\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count1`] module"]
29416    #[doc(alias = "TCXO_COUNT1")]
29417    pub type TcxoCount1 = crate::Reg<tcxo_count1::TcxoCount1Spec>;
29418    #[doc = "TCXO count bits \\[31:16\\]"]
29419    pub mod tcxo_count1 {
29420        #[doc = "Register `TCXO_COUNT1` reader"]
29421        pub type R = crate::R<TcxoCount1Spec>;
29422        #[doc = "Register `TCXO_COUNT1` writer"]
29423        pub type W = crate::W<TcxoCount1Spec>;
29424        #[doc = "Field `count1` reader - Counter value bits \\[31:16\\]"]
29425        pub type Count1R = crate::FieldReader<u16>;
29426        impl R {
29427            #[doc = "Bits 0:15 - Counter value bits \\[31:16\\]"]
29428            #[inline(always)]
29429            pub fn count1(&self) -> Count1R {
29430                Count1R::new((self.bits & 0xffff) as u16)
29431            }
29432        }
29433        impl W {}
29434        #[doc = "TCXO count bits \\[31:16\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29435        pub struct TcxoCount1Spec;
29436        impl crate::RegisterSpec for TcxoCount1Spec {
29437            type Ux = u32;
29438        }
29439        #[doc = "`read()` method returns [`tcxo_count1::R`](R) reader structure"]
29440        impl crate::Readable for TcxoCount1Spec {}
29441        #[doc = "`write(|w| ..)` method takes [`tcxo_count1::W`](W) writer structure"]
29442        impl crate::Writable for TcxoCount1Spec {
29443            type Safety = crate::Unsafe;
29444        }
29445        #[doc = "`reset()` method sets TCXO_COUNT1 to value 0"]
29446        impl crate::Resettable for TcxoCount1Spec {}
29447    }
29448    #[doc = "TCXO_COUNT2 (rw) register accessor: TCXO count bits \\[47:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count2`] module"]
29449    #[doc(alias = "TCXO_COUNT2")]
29450    pub type TcxoCount2 = crate::Reg<tcxo_count2::TcxoCount2Spec>;
29451    #[doc = "TCXO count bits \\[47:32\\]"]
29452    pub mod tcxo_count2 {
29453        #[doc = "Register `TCXO_COUNT2` reader"]
29454        pub type R = crate::R<TcxoCount2Spec>;
29455        #[doc = "Register `TCXO_COUNT2` writer"]
29456        pub type W = crate::W<TcxoCount2Spec>;
29457        #[doc = "Field `count2` reader - Counter value bits \\[47:32\\]"]
29458        pub type Count2R = crate::FieldReader<u16>;
29459        impl R {
29460            #[doc = "Bits 0:15 - Counter value bits \\[47:32\\]"]
29461            #[inline(always)]
29462            pub fn count2(&self) -> Count2R {
29463                Count2R::new((self.bits & 0xffff) as u16)
29464            }
29465        }
29466        impl W {}
29467        #[doc = "TCXO count bits \\[47:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29468        pub struct TcxoCount2Spec;
29469        impl crate::RegisterSpec for TcxoCount2Spec {
29470            type Ux = u32;
29471        }
29472        #[doc = "`read()` method returns [`tcxo_count2::R`](R) reader structure"]
29473        impl crate::Readable for TcxoCount2Spec {}
29474        #[doc = "`write(|w| ..)` method takes [`tcxo_count2::W`](W) writer structure"]
29475        impl crate::Writable for TcxoCount2Spec {
29476            type Safety = crate::Unsafe;
29477        }
29478        #[doc = "`reset()` method sets TCXO_COUNT2 to value 0"]
29479        impl crate::Resettable for TcxoCount2Spec {}
29480    }
29481    #[doc = "TCXO_COUNT3 (rw) register accessor: TCXO count bits \\[63:48\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count3`] module"]
29482    #[doc(alias = "TCXO_COUNT3")]
29483    pub type TcxoCount3 = crate::Reg<tcxo_count3::TcxoCount3Spec>;
29484    #[doc = "TCXO count bits \\[63:48\\]"]
29485    pub mod tcxo_count3 {
29486        #[doc = "Register `TCXO_COUNT3` reader"]
29487        pub type R = crate::R<TcxoCount3Spec>;
29488        #[doc = "Register `TCXO_COUNT3` writer"]
29489        pub type W = crate::W<TcxoCount3Spec>;
29490        #[doc = "Field `count3` reader - Counter value bits \\[63:48\\]"]
29491        pub type Count3R = crate::FieldReader<u16>;
29492        impl R {
29493            #[doc = "Bits 0:15 - Counter value bits \\[63:48\\]"]
29494            #[inline(always)]
29495            pub fn count3(&self) -> Count3R {
29496                Count3R::new((self.bits & 0xffff) as u16)
29497            }
29498        }
29499        impl W {}
29500        #[doc = "TCXO count bits \\[63:48\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29501        pub struct TcxoCount3Spec;
29502        impl crate::RegisterSpec for TcxoCount3Spec {
29503            type Ux = u32;
29504        }
29505        #[doc = "`read()` method returns [`tcxo_count3::R`](R) reader structure"]
29506        impl crate::Readable for TcxoCount3Spec {}
29507        #[doc = "`write(|w| ..)` method takes [`tcxo_count3::W`](W) writer structure"]
29508        impl crate::Writable for TcxoCount3Spec {
29509            type Safety = crate::Unsafe;
29510        }
29511        #[doc = "`reset()` method sets TCXO_COUNT3 to value 0"]
29512        impl crate::Resettable for TcxoCount3Spec {}
29513    }
29514}
29515#[doc = "CLDO Clock and Reset Generator - clock enables, dividers, clock selects, soft resets"]
29516pub type CldoCrg = crate::Periph<cldo_crg::RegisterBlock, 0x4400_1100>;
29517impl core::fmt::Debug for CldoCrg {
29518    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
29519        f.debug_struct("CldoCrg").finish()
29520    }
29521}
29522#[doc = "CLDO Clock and Reset Generator - clock enables, dividers, clock selects, soft resets"]
29523pub mod cldo_crg {
29524    #[repr(C)]
29525    #[doc = "Register block"]
29526    pub struct RegisterBlock {
29527        cken_ctl0: CkenCtl0,
29528        cken_ctl1: CkenCtl1,
29529        div_ctl0: DivCtl0,
29530        _reserved3: [u8; 0x08],
29531        div_ctl3: DivCtl3,
29532        div_ctl4: DivCtl4,
29533        div_ctl5: DivCtl5,
29534        _reserved6: [u8; 0x04],
29535        div_ctl7: DivCtl7,
29536        _reserved7: [u8; 0x04],
29537        div_ctl9: DivCtl9,
29538        div_ctl10: DivCtl10,
29539        clk_sel: ClkSel,
29540        rst_soft_cfg0: RstSoftCfg0,
29541        rst_soft_cfg1: RstSoftCfg1,
29542    }
29543    impl RegisterBlock {
29544        #[doc = "0x00 - Clock enable control register 0"]
29545        #[inline(always)]
29546        pub const fn cken_ctl0(&self) -> &CkenCtl0 {
29547            &self.cken_ctl0
29548        }
29549        #[doc = "0x04 - Clock enable control register 1"]
29550        #[inline(always)]
29551        pub const fn cken_ctl1(&self) -> &CkenCtl1 {
29552            &self.cken_ctl1
29553        }
29554        #[doc = "0x08 - Divider control register 0"]
29555        #[inline(always)]
29556        pub const fn div_ctl0(&self) -> &DivCtl0 {
29557            &self.div_ctl0
29558        }
29559        #[doc = "0x14 - Divider control 3 - PWM0, PWM1"]
29560        #[inline(always)]
29561        pub const fn div_ctl3(&self) -> &DivCtl3 {
29562            &self.div_ctl3
29563        }
29564        #[doc = "0x18 - Divider control 4 - PWM2, PWM3, PWM4"]
29565        #[inline(always)]
29566        pub const fn div_ctl4(&self) -> &DivCtl4 {
29567            &self.div_ctl4
29568        }
29569        #[doc = "0x1c - Divider control 5 - PWM5, PWM6, PWM7"]
29570        #[inline(always)]
29571        pub const fn div_ctl5(&self) -> &DivCtl5 {
29572            &self.div_ctl5
29573        }
29574        #[doc = "0x24 - Divider control 7 - tsensor, bus"]
29575        #[inline(always)]
29576        pub const fn div_ctl7(&self) -> &DivCtl7 {
29577            &self.div_ctl7
29578        }
29579        #[doc = "0x2c - Divider control 9 - TRNG"]
29580        #[inline(always)]
29581        pub const fn div_ctl9(&self) -> &DivCtl9 {
29582            &self.div_ctl9
29583        }
29584        #[doc = "0x30 - Divider control 10 - TCXO 120M, MAC main"]
29585        #[inline(always)]
29586        pub const fn div_ctl10(&self) -> &DivCtl10 {
29587            &self.div_ctl10
29588        }
29589        #[doc = "0x34 - Clock source select register"]
29590        #[inline(always)]
29591        pub const fn clk_sel(&self) -> &ClkSel {
29592            &self.clk_sel
29593        }
29594        #[doc = "0x38 - Soft reset configuration register 0"]
29595        #[inline(always)]
29596        pub const fn rst_soft_cfg0(&self) -> &RstSoftCfg0 {
29597            &self.rst_soft_cfg0
29598        }
29599        #[doc = "0x3c - Soft reset configuration register 1 (active low)"]
29600        #[inline(always)]
29601        pub const fn rst_soft_cfg1(&self) -> &RstSoftCfg1 {
29602            &self.rst_soft_cfg1
29603        }
29604    }
29605    #[doc = "CKEN_CTL0 (rw) register accessor: Clock enable control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cken_ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cken_ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cken_ctl0`] module"]
29606    #[doc(alias = "CKEN_CTL0")]
29607    pub type CkenCtl0 = crate::Reg<cken_ctl0::CkenCtl0Spec>;
29608    #[doc = "Clock enable control register 0"]
29609    pub mod cken_ctl0 {
29610        #[doc = "Register `CKEN_CTL0` reader"]
29611        pub type R = crate::R<CkenCtl0Spec>;
29612        #[doc = "Register `CKEN_CTL0` writer"]
29613        pub type W = crate::W<CkenCtl0Spec>;
29614        #[doc = "Field `pwm_cken` reader - PWM clock gates: bits \\[10:2\\], 9 channels"]
29615        pub type PwmCkenR = crate::FieldReader<u16>;
29616        #[doc = "Field `pwm_cken` writer - PWM clock gates: bits \\[10:2\\], 9 channels"]
29617        pub type PwmCkenW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
29618        #[doc = "Field `gen_cken` reader - General clock gates: bits \\[27:18\\], 10 channels"]
29619        pub type GenCkenR = crate::FieldReader<u16>;
29620        #[doc = "Field `gen_cken` writer - General clock gates: bits \\[27:18\\], 10 channels"]
29621        pub type GenCkenW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
29622        impl R {
29623            #[doc = "Bits 2:10 - PWM clock gates: bits \\[10:2\\], 9 channels"]
29624            #[inline(always)]
29625            pub fn pwm_cken(&self) -> PwmCkenR {
29626                PwmCkenR::new(((self.bits >> 2) & 0x01ff) as u16)
29627            }
29628            #[doc = "Bits 18:27 - General clock gates: bits \\[27:18\\], 10 channels"]
29629            #[inline(always)]
29630            pub fn gen_cken(&self) -> GenCkenR {
29631                GenCkenR::new(((self.bits >> 18) & 0x03ff) as u16)
29632            }
29633        }
29634        impl W {
29635            #[doc = "Bits 2:10 - PWM clock gates: bits \\[10:2\\], 9 channels"]
29636            #[inline(always)]
29637            pub fn pwm_cken(&mut self) -> PwmCkenW<'_, CkenCtl0Spec> {
29638                PwmCkenW::new(self, 2)
29639            }
29640            #[doc = "Bits 18:27 - General clock gates: bits \\[27:18\\], 10 channels"]
29641            #[inline(always)]
29642            pub fn gen_cken(&mut self) -> GenCkenW<'_, CkenCtl0Spec> {
29643                GenCkenW::new(self, 18)
29644            }
29645        }
29646        #[doc = "Clock enable control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cken_ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cken_ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29647        pub struct CkenCtl0Spec;
29648        impl crate::RegisterSpec for CkenCtl0Spec {
29649            type Ux = u32;
29650        }
29651        #[doc = "`read()` method returns [`cken_ctl0::R`](R) reader structure"]
29652        impl crate::Readable for CkenCtl0Spec {}
29653        #[doc = "`write(|w| ..)` method takes [`cken_ctl0::W`](W) writer structure"]
29654        impl crate::Writable for CkenCtl0Spec {
29655            type Safety = crate::Unsafe;
29656        }
29657        #[doc = "`reset()` method sets CKEN_CTL0 to value 0"]
29658        impl crate::Resettable for CkenCtl0Spec {}
29659    }
29660    #[doc = "CKEN_CTL1 (rw) register accessor: Clock enable control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cken_ctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cken_ctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cken_ctl1`] module"]
29661    #[doc(alias = "CKEN_CTL1")]
29662    pub type CkenCtl1 = crate::Reg<cken_ctl1::CkenCtl1Spec>;
29663    #[doc = "Clock enable control register 1"]
29664    pub mod cken_ctl1 {
29665        #[doc = "Register `CKEN_CTL1` reader"]
29666        pub type R = crate::R<CkenCtl1Spec>;
29667        #[doc = "Register `CKEN_CTL1` writer"]
29668        pub type W = crate::W<CkenCtl1Spec>;
29669        #[doc = "Field `bt_cken` reader - BT clock gates: bits \\[12:8\\], 5 channels"]
29670        pub type BtCkenR = crate::FieldReader;
29671        #[doc = "Field `bt_cken` writer - BT clock gates: bits \\[12:8\\], 5 channels"]
29672        pub type BtCkenW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
29673        #[doc = "Field `wifi_cken` reader - WIFI clock gates: bits \\[14:13\\], 2 channels"]
29674        pub type WifiCkenR = crate::FieldReader;
29675        #[doc = "Field `wifi_cken` writer - WIFI clock gates: bits \\[14:13\\], 2 channels"]
29676        pub type WifiCkenW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29677        #[doc = "Field `uart_cken` reader - UART clock gates: bits \\[20:18\\], 3 channels"]
29678        pub type UartCkenR = crate::FieldReader;
29679        #[doc = "Field `uart_cken` writer - UART clock gates: bits \\[20:18\\], 3 channels"]
29680        pub type UartCkenW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29681        #[doc = "Field `spi_cken` reader - SPI clock gate at bit 25"]
29682        pub type SpiCkenR = crate::BitReader;
29683        #[doc = "Field `spi_cken` writer - SPI clock gate at bit 25"]
29684        pub type SpiCkenW<'a, REG> = crate::BitWriter<'a, REG>;
29685        impl R {
29686            #[doc = "Bits 8:12 - BT clock gates: bits \\[12:8\\], 5 channels"]
29687            #[inline(always)]
29688            pub fn bt_cken(&self) -> BtCkenR {
29689                BtCkenR::new(((self.bits >> 8) & 0x1f) as u8)
29690            }
29691            #[doc = "Bits 13:14 - WIFI clock gates: bits \\[14:13\\], 2 channels"]
29692            #[inline(always)]
29693            pub fn wifi_cken(&self) -> WifiCkenR {
29694                WifiCkenR::new(((self.bits >> 13) & 3) as u8)
29695            }
29696            #[doc = "Bits 18:20 - UART clock gates: bits \\[20:18\\], 3 channels"]
29697            #[inline(always)]
29698            pub fn uart_cken(&self) -> UartCkenR {
29699                UartCkenR::new(((self.bits >> 18) & 7) as u8)
29700            }
29701            #[doc = "Bit 25 - SPI clock gate at bit 25"]
29702            #[inline(always)]
29703            pub fn spi_cken(&self) -> SpiCkenR {
29704                SpiCkenR::new(((self.bits >> 25) & 1) != 0)
29705            }
29706        }
29707        impl W {
29708            #[doc = "Bits 8:12 - BT clock gates: bits \\[12:8\\], 5 channels"]
29709            #[inline(always)]
29710            pub fn bt_cken(&mut self) -> BtCkenW<'_, CkenCtl1Spec> {
29711                BtCkenW::new(self, 8)
29712            }
29713            #[doc = "Bits 13:14 - WIFI clock gates: bits \\[14:13\\], 2 channels"]
29714            #[inline(always)]
29715            pub fn wifi_cken(&mut self) -> WifiCkenW<'_, CkenCtl1Spec> {
29716                WifiCkenW::new(self, 13)
29717            }
29718            #[doc = "Bits 18:20 - UART clock gates: bits \\[20:18\\], 3 channels"]
29719            #[inline(always)]
29720            pub fn uart_cken(&mut self) -> UartCkenW<'_, CkenCtl1Spec> {
29721                UartCkenW::new(self, 18)
29722            }
29723            #[doc = "Bit 25 - SPI clock gate at bit 25"]
29724            #[inline(always)]
29725            pub fn spi_cken(&mut self) -> SpiCkenW<'_, CkenCtl1Spec> {
29726                SpiCkenW::new(self, 25)
29727            }
29728        }
29729        #[doc = "Clock enable control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cken_ctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cken_ctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29730        pub struct CkenCtl1Spec;
29731        impl crate::RegisterSpec for CkenCtl1Spec {
29732            type Ux = u32;
29733        }
29734        #[doc = "`read()` method returns [`cken_ctl1::R`](R) reader structure"]
29735        impl crate::Readable for CkenCtl1Spec {}
29736        #[doc = "`write(|w| ..)` method takes [`cken_ctl1::W`](W) writer structure"]
29737        impl crate::Writable for CkenCtl1Spec {
29738            type Safety = crate::Unsafe;
29739        }
29740        #[doc = "`reset()` method sets CKEN_CTL1 to value 0"]
29741        impl crate::Resettable for CkenCtl1Spec {}
29742    }
29743    #[doc = "DIV_CTL0 (rw) register accessor: Divider control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl0`] module"]
29744    #[doc(alias = "DIV_CTL0")]
29745    pub type DivCtl0 = crate::Reg<div_ctl0::DivCtl0Spec>;
29746    #[doc = "Divider control register 0"]
29747    pub mod div_ctl0 {
29748        #[doc = "Register `DIV_CTL0` reader"]
29749        pub type R = crate::R<DivCtl0Spec>;
29750        #[doc = "Register `DIV_CTL0` writer"]
29751        pub type W = crate::W<DivCtl0Spec>;
29752        #[doc = "Field `div_ctl0` reader - Clock divider control 0"]
29753        pub type DivCtl0R = crate::FieldReader<u32>;
29754        #[doc = "Field `div_ctl0` writer - Clock divider control 0"]
29755        pub type DivCtl0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
29756        impl R {
29757            #[doc = "Bits 0:31 - Clock divider control 0"]
29758            #[inline(always)]
29759            pub fn div_ctl0(&self) -> DivCtl0R {
29760                DivCtl0R::new(self.bits)
29761            }
29762        }
29763        impl W {
29764            #[doc = "Bits 0:31 - Clock divider control 0"]
29765            #[inline(always)]
29766            pub fn div_ctl0(&mut self) -> DivCtl0W<'_, DivCtl0Spec> {
29767                DivCtl0W::new(self, 0)
29768            }
29769        }
29770        #[doc = "Divider control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29771        pub struct DivCtl0Spec;
29772        impl crate::RegisterSpec for DivCtl0Spec {
29773            type Ux = u32;
29774        }
29775        #[doc = "`read()` method returns [`div_ctl0::R`](R) reader structure"]
29776        impl crate::Readable for DivCtl0Spec {}
29777        #[doc = "`write(|w| ..)` method takes [`div_ctl0::W`](W) writer structure"]
29778        impl crate::Writable for DivCtl0Spec {
29779            type Safety = crate::Unsafe;
29780        }
29781        #[doc = "`reset()` method sets DIV_CTL0 to value 0"]
29782        impl crate::Resettable for DivCtl0Spec {}
29783    }
29784    #[doc = "DIV_CTL3 (rw) register accessor: Divider control 3 - PWM0, PWM1\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl3`] module"]
29785    #[doc(alias = "DIV_CTL3")]
29786    pub type DivCtl3 = crate::Reg<div_ctl3::DivCtl3Spec>;
29787    #[doc = "Divider control 3 - PWM0, PWM1"]
29788    pub mod div_ctl3 {
29789        #[doc = "Register `DIV_CTL3` reader"]
29790        pub type R = crate::R<DivCtl3Spec>;
29791        #[doc = "Register `DIV_CTL3` writer"]
29792        pub type W = crate::W<DivCtl3Spec>;
29793        #[doc = "Field `div_pwm01` reader - PWM0/PWM1 clock divider"]
29794        pub type DivPwm01R = crate::FieldReader<u32>;
29795        #[doc = "Field `div_pwm01` writer - PWM0/PWM1 clock divider"]
29796        pub type DivPwm01W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
29797        impl R {
29798            #[doc = "Bits 0:31 - PWM0/PWM1 clock divider"]
29799            #[inline(always)]
29800            pub fn div_pwm01(&self) -> DivPwm01R {
29801                DivPwm01R::new(self.bits)
29802            }
29803        }
29804        impl W {
29805            #[doc = "Bits 0:31 - PWM0/PWM1 clock divider"]
29806            #[inline(always)]
29807            pub fn div_pwm01(&mut self) -> DivPwm01W<'_, DivCtl3Spec> {
29808                DivPwm01W::new(self, 0)
29809            }
29810        }
29811        #[doc = "Divider control 3 - PWM0, PWM1\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29812        pub struct DivCtl3Spec;
29813        impl crate::RegisterSpec for DivCtl3Spec {
29814            type Ux = u32;
29815        }
29816        #[doc = "`read()` method returns [`div_ctl3::R`](R) reader structure"]
29817        impl crate::Readable for DivCtl3Spec {}
29818        #[doc = "`write(|w| ..)` method takes [`div_ctl3::W`](W) writer structure"]
29819        impl crate::Writable for DivCtl3Spec {
29820            type Safety = crate::Unsafe;
29821        }
29822        #[doc = "`reset()` method sets DIV_CTL3 to value 0"]
29823        impl crate::Resettable for DivCtl3Spec {}
29824    }
29825    #[doc = "DIV_CTL4 (rw) register accessor: Divider control 4 - PWM2, PWM3, PWM4\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl4`] module"]
29826    #[doc(alias = "DIV_CTL4")]
29827    pub type DivCtl4 = crate::Reg<div_ctl4::DivCtl4Spec>;
29828    #[doc = "Divider control 4 - PWM2, PWM3, PWM4"]
29829    pub mod div_ctl4 {
29830        #[doc = "Register `DIV_CTL4` reader"]
29831        pub type R = crate::R<DivCtl4Spec>;
29832        #[doc = "Register `DIV_CTL4` writer"]
29833        pub type W = crate::W<DivCtl4Spec>;
29834        #[doc = "Field `div_pwm234` reader - PWM2/PWM3/PWM4 clock divider"]
29835        pub type DivPwm234R = crate::FieldReader<u32>;
29836        #[doc = "Field `div_pwm234` writer - PWM2/PWM3/PWM4 clock divider"]
29837        pub type DivPwm234W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
29838        impl R {
29839            #[doc = "Bits 0:31 - PWM2/PWM3/PWM4 clock divider"]
29840            #[inline(always)]
29841            pub fn div_pwm234(&self) -> DivPwm234R {
29842                DivPwm234R::new(self.bits)
29843            }
29844        }
29845        impl W {
29846            #[doc = "Bits 0:31 - PWM2/PWM3/PWM4 clock divider"]
29847            #[inline(always)]
29848            pub fn div_pwm234(&mut self) -> DivPwm234W<'_, DivCtl4Spec> {
29849                DivPwm234W::new(self, 0)
29850            }
29851        }
29852        #[doc = "Divider control 4 - PWM2, PWM3, PWM4\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29853        pub struct DivCtl4Spec;
29854        impl crate::RegisterSpec for DivCtl4Spec {
29855            type Ux = u32;
29856        }
29857        #[doc = "`read()` method returns [`div_ctl4::R`](R) reader structure"]
29858        impl crate::Readable for DivCtl4Spec {}
29859        #[doc = "`write(|w| ..)` method takes [`div_ctl4::W`](W) writer structure"]
29860        impl crate::Writable for DivCtl4Spec {
29861            type Safety = crate::Unsafe;
29862        }
29863        #[doc = "`reset()` method sets DIV_CTL4 to value 0"]
29864        impl crate::Resettable for DivCtl4Spec {}
29865    }
29866    #[doc = "DIV_CTL5 (rw) register accessor: Divider control 5 - PWM5, PWM6, PWM7\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl5`] module"]
29867    #[doc(alias = "DIV_CTL5")]
29868    pub type DivCtl5 = crate::Reg<div_ctl5::DivCtl5Spec>;
29869    #[doc = "Divider control 5 - PWM5, PWM6, PWM7"]
29870    pub mod div_ctl5 {
29871        #[doc = "Register `DIV_CTL5` reader"]
29872        pub type R = crate::R<DivCtl5Spec>;
29873        #[doc = "Register `DIV_CTL5` writer"]
29874        pub type W = crate::W<DivCtl5Spec>;
29875        #[doc = "Field `div_pwm567` reader - PWM5/PWM6/PWM7 clock divider"]
29876        pub type DivPwm567R = crate::FieldReader<u32>;
29877        #[doc = "Field `div_pwm567` writer - PWM5/PWM6/PWM7 clock divider"]
29878        pub type DivPwm567W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
29879        impl R {
29880            #[doc = "Bits 0:31 - PWM5/PWM6/PWM7 clock divider"]
29881            #[inline(always)]
29882            pub fn div_pwm567(&self) -> DivPwm567R {
29883                DivPwm567R::new(self.bits)
29884            }
29885        }
29886        impl W {
29887            #[doc = "Bits 0:31 - PWM5/PWM6/PWM7 clock divider"]
29888            #[inline(always)]
29889            pub fn div_pwm567(&mut self) -> DivPwm567W<'_, DivCtl5Spec> {
29890                DivPwm567W::new(self, 0)
29891            }
29892        }
29893        #[doc = "Divider control 5 - PWM5, PWM6, PWM7\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29894        pub struct DivCtl5Spec;
29895        impl crate::RegisterSpec for DivCtl5Spec {
29896            type Ux = u32;
29897        }
29898        #[doc = "`read()` method returns [`div_ctl5::R`](R) reader structure"]
29899        impl crate::Readable for DivCtl5Spec {}
29900        #[doc = "`write(|w| ..)` method takes [`div_ctl5::W`](W) writer structure"]
29901        impl crate::Writable for DivCtl5Spec {
29902            type Safety = crate::Unsafe;
29903        }
29904        #[doc = "`reset()` method sets DIV_CTL5 to value 0"]
29905        impl crate::Resettable for DivCtl5Spec {}
29906    }
29907    #[doc = "DIV_CTL7 (rw) register accessor: Divider control 7 - tsensor, bus\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl7`] module"]
29908    #[doc(alias = "DIV_CTL7")]
29909    pub type DivCtl7 = crate::Reg<div_ctl7::DivCtl7Spec>;
29910    #[doc = "Divider control 7 - tsensor, bus"]
29911    pub mod div_ctl7 {
29912        #[doc = "Register `DIV_CTL7` reader"]
29913        pub type R = crate::R<DivCtl7Spec>;
29914        #[doc = "Register `DIV_CTL7` writer"]
29915        pub type W = crate::W<DivCtl7Spec>;
29916        #[doc = "Field `div_tsensor_bus` reader - TSENSOR and bus clock dividers"]
29917        pub type DivTsensorBusR = crate::FieldReader<u32>;
29918        #[doc = "Field `div_tsensor_bus` writer - TSENSOR and bus clock dividers"]
29919        pub type DivTsensorBusW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
29920        impl R {
29921            #[doc = "Bits 0:31 - TSENSOR and bus clock dividers"]
29922            #[inline(always)]
29923            pub fn div_tsensor_bus(&self) -> DivTsensorBusR {
29924                DivTsensorBusR::new(self.bits)
29925            }
29926        }
29927        impl W {
29928            #[doc = "Bits 0:31 - TSENSOR and bus clock dividers"]
29929            #[inline(always)]
29930            pub fn div_tsensor_bus(&mut self) -> DivTsensorBusW<'_, DivCtl7Spec> {
29931                DivTsensorBusW::new(self, 0)
29932            }
29933        }
29934        #[doc = "Divider control 7 - tsensor, bus\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29935        pub struct DivCtl7Spec;
29936        impl crate::RegisterSpec for DivCtl7Spec {
29937            type Ux = u32;
29938        }
29939        #[doc = "`read()` method returns [`div_ctl7::R`](R) reader structure"]
29940        impl crate::Readable for DivCtl7Spec {}
29941        #[doc = "`write(|w| ..)` method takes [`div_ctl7::W`](W) writer structure"]
29942        impl crate::Writable for DivCtl7Spec {
29943            type Safety = crate::Unsafe;
29944        }
29945        #[doc = "`reset()` method sets DIV_CTL7 to value 0"]
29946        impl crate::Resettable for DivCtl7Spec {}
29947    }
29948    #[doc = "DIV_CTL9 (rw) register accessor: Divider control 9 - TRNG\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl9`] module"]
29949    #[doc(alias = "DIV_CTL9")]
29950    pub type DivCtl9 = crate::Reg<div_ctl9::DivCtl9Spec>;
29951    #[doc = "Divider control 9 - TRNG"]
29952    pub mod div_ctl9 {
29953        #[doc = "Register `DIV_CTL9` reader"]
29954        pub type R = crate::R<DivCtl9Spec>;
29955        #[doc = "Register `DIV_CTL9` writer"]
29956        pub type W = crate::W<DivCtl9Spec>;
29957        #[doc = "Field `div_trng` reader - TRNG clock divider"]
29958        pub type DivTrngR = crate::FieldReader<u32>;
29959        #[doc = "Field `div_trng` writer - TRNG clock divider"]
29960        pub type DivTrngW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
29961        impl R {
29962            #[doc = "Bits 0:31 - TRNG clock divider"]
29963            #[inline(always)]
29964            pub fn div_trng(&self) -> DivTrngR {
29965                DivTrngR::new(self.bits)
29966            }
29967        }
29968        impl W {
29969            #[doc = "Bits 0:31 - TRNG clock divider"]
29970            #[inline(always)]
29971            pub fn div_trng(&mut self) -> DivTrngW<'_, DivCtl9Spec> {
29972                DivTrngW::new(self, 0)
29973            }
29974        }
29975        #[doc = "Divider control 9 - TRNG\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29976        pub struct DivCtl9Spec;
29977        impl crate::RegisterSpec for DivCtl9Spec {
29978            type Ux = u32;
29979        }
29980        #[doc = "`read()` method returns [`div_ctl9::R`](R) reader structure"]
29981        impl crate::Readable for DivCtl9Spec {}
29982        #[doc = "`write(|w| ..)` method takes [`div_ctl9::W`](W) writer structure"]
29983        impl crate::Writable for DivCtl9Spec {
29984            type Safety = crate::Unsafe;
29985        }
29986        #[doc = "`reset()` method sets DIV_CTL9 to value 0"]
29987        impl crate::Resettable for DivCtl9Spec {}
29988    }
29989    #[doc = "DIV_CTL10 (rw) register accessor: Divider control 10 - TCXO 120M, MAC main\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl10`] module"]
29990    #[doc(alias = "DIV_CTL10")]
29991    pub type DivCtl10 = crate::Reg<div_ctl10::DivCtl10Spec>;
29992    #[doc = "Divider control 10 - TCXO 120M, MAC main"]
29993    pub mod div_ctl10 {
29994        #[doc = "Register `DIV_CTL10` reader"]
29995        pub type R = crate::R<DivCtl10Spec>;
29996        #[doc = "Register `DIV_CTL10` writer"]
29997        pub type W = crate::W<DivCtl10Spec>;
29998        #[doc = "Field `tcxo_120m_div1_num` reader - TCXO 120M divider 1 value (3-bit)"]
29999        pub type Tcxo120mDiv1NumR = crate::FieldReader;
30000        #[doc = "Field `tcxo_120m_div1_num` writer - TCXO 120M divider 1 value (3-bit)"]
30001        pub type Tcxo120mDiv1NumW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
30002        #[doc = "Field `tcxo_120m_load_div_en` reader - TCXO 120M load divider enable"]
30003        pub type Tcxo120mLoadDivEnR = crate::BitReader;
30004        #[doc = "Field `tcxo_120m_load_div_en` writer - TCXO 120M load divider enable"]
30005        pub type Tcxo120mLoadDivEnW<'a, REG> = crate::BitWriter<'a, REG>;
30006        #[doc = "Field `tcxo_120m_div_en` reader - TCXO 120M divider enable"]
30007        pub type Tcxo120mDivEnR = crate::BitReader;
30008        #[doc = "Field `tcxo_120m_div_en` writer - TCXO 120M divider enable"]
30009        pub type Tcxo120mDivEnW<'a, REG> = crate::BitWriter<'a, REG>;
30010        #[doc = "Field `mac_main_div_num` reader - MAC main divider value (6-bit)"]
30011        pub type MacMainDivNumR = crate::FieldReader;
30012        #[doc = "Field `mac_main_div_num` writer - MAC main divider value (6-bit)"]
30013        pub type MacMainDivNumW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
30014        #[doc = "Field `wtop_div_en` reader - WTO divider enable"]
30015        pub type WtopDivEnR = crate::BitReader;
30016        #[doc = "Field `wtop_div_en` writer - WTO divider enable"]
30017        pub type WtopDivEnW<'a, REG> = crate::BitWriter<'a, REG>;
30018        #[doc = "Field `tcxo_120m_div2_num` reader - TCXO 120M divider 2 value (3-bit)"]
30019        pub type Tcxo120mDiv2NumR = crate::FieldReader;
30020        #[doc = "Field `tcxo_120m_div2_num` writer - TCXO 120M divider 2 value (3-bit)"]
30021        pub type Tcxo120mDiv2NumW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
30022        impl R {
30023            #[doc = "Bits 0:2 - TCXO 120M divider 1 value (3-bit)"]
30024            #[inline(always)]
30025            pub fn tcxo_120m_div1_num(&self) -> Tcxo120mDiv1NumR {
30026                Tcxo120mDiv1NumR::new((self.bits & 7) as u8)
30027            }
30028            #[doc = "Bit 3 - TCXO 120M load divider enable"]
30029            #[inline(always)]
30030            pub fn tcxo_120m_load_div_en(&self) -> Tcxo120mLoadDivEnR {
30031                Tcxo120mLoadDivEnR::new(((self.bits >> 3) & 1) != 0)
30032            }
30033            #[doc = "Bit 4 - TCXO 120M divider enable"]
30034            #[inline(always)]
30035            pub fn tcxo_120m_div_en(&self) -> Tcxo120mDivEnR {
30036                Tcxo120mDivEnR::new(((self.bits >> 4) & 1) != 0)
30037            }
30038            #[doc = "Bits 5:10 - MAC main divider value (6-bit)"]
30039            #[inline(always)]
30040            pub fn mac_main_div_num(&self) -> MacMainDivNumR {
30041                MacMainDivNumR::new(((self.bits >> 5) & 0x3f) as u8)
30042            }
30043            #[doc = "Bit 11 - WTO divider enable"]
30044            #[inline(always)]
30045            pub fn wtop_div_en(&self) -> WtopDivEnR {
30046                WtopDivEnR::new(((self.bits >> 11) & 1) != 0)
30047            }
30048            #[doc = "Bits 12:14 - TCXO 120M divider 2 value (3-bit)"]
30049            #[inline(always)]
30050            pub fn tcxo_120m_div2_num(&self) -> Tcxo120mDiv2NumR {
30051                Tcxo120mDiv2NumR::new(((self.bits >> 12) & 7) as u8)
30052            }
30053        }
30054        impl W {
30055            #[doc = "Bits 0:2 - TCXO 120M divider 1 value (3-bit)"]
30056            #[inline(always)]
30057            pub fn tcxo_120m_div1_num(&mut self) -> Tcxo120mDiv1NumW<'_, DivCtl10Spec> {
30058                Tcxo120mDiv1NumW::new(self, 0)
30059            }
30060            #[doc = "Bit 3 - TCXO 120M load divider enable"]
30061            #[inline(always)]
30062            pub fn tcxo_120m_load_div_en(&mut self) -> Tcxo120mLoadDivEnW<'_, DivCtl10Spec> {
30063                Tcxo120mLoadDivEnW::new(self, 3)
30064            }
30065            #[doc = "Bit 4 - TCXO 120M divider enable"]
30066            #[inline(always)]
30067            pub fn tcxo_120m_div_en(&mut self) -> Tcxo120mDivEnW<'_, DivCtl10Spec> {
30068                Tcxo120mDivEnW::new(self, 4)
30069            }
30070            #[doc = "Bits 5:10 - MAC main divider value (6-bit)"]
30071            #[inline(always)]
30072            pub fn mac_main_div_num(&mut self) -> MacMainDivNumW<'_, DivCtl10Spec> {
30073                MacMainDivNumW::new(self, 5)
30074            }
30075            #[doc = "Bit 11 - WTO divider enable"]
30076            #[inline(always)]
30077            pub fn wtop_div_en(&mut self) -> WtopDivEnW<'_, DivCtl10Spec> {
30078                WtopDivEnW::new(self, 11)
30079            }
30080            #[doc = "Bits 12:14 - TCXO 120M divider 2 value (3-bit)"]
30081            #[inline(always)]
30082            pub fn tcxo_120m_div2_num(&mut self) -> Tcxo120mDiv2NumW<'_, DivCtl10Spec> {
30083                Tcxo120mDiv2NumW::new(self, 12)
30084            }
30085        }
30086        #[doc = "Divider control 10 - TCXO 120M, MAC main\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30087        pub struct DivCtl10Spec;
30088        impl crate::RegisterSpec for DivCtl10Spec {
30089            type Ux = u32;
30090        }
30091        #[doc = "`read()` method returns [`div_ctl10::R`](R) reader structure"]
30092        impl crate::Readable for DivCtl10Spec {}
30093        #[doc = "`write(|w| ..)` method takes [`div_ctl10::W`](W) writer structure"]
30094        impl crate::Writable for DivCtl10Spec {
30095            type Safety = crate::Unsafe;
30096        }
30097        #[doc = "`reset()` method sets DIV_CTL10 to value 0"]
30098        impl crate::Resettable for DivCtl10Spec {}
30099    }
30100    #[doc = "CLK_SEL (rw) register accessor: Clock source select register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_sel`] module"]
30101    #[doc(alias = "CLK_SEL")]
30102    pub type ClkSel = crate::Reg<clk_sel::ClkSelSpec>;
30103    #[doc = "Clock source select register"]
30104    pub mod clk_sel {
30105        #[doc = "Register `CLK_SEL` reader"]
30106        pub type R = crate::R<ClkSelSpec>;
30107        #[doc = "Register `CLK_SEL` writer"]
30108        pub type W = crate::W<ClkSelSpec>;
30109        #[doc = "Field `rf_ctl_clk_sel` reader - RF_CTL clock: 0=TCXO; 1=PLL"]
30110        pub type RfCtlClkSelR = crate::BitReader;
30111        #[doc = "Field `rf_ctl_clk_sel` writer - RF_CTL clock: 0=TCXO; 1=PLL"]
30112        pub type RfCtlClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
30113        #[doc = "Field `uart0_clk_sel` reader - UART0 clock: 0=TCXO; 1=PLL"]
30114        pub type Uart0ClkSelR = crate::BitReader;
30115        #[doc = "Field `uart0_clk_sel` writer - UART0 clock: 0=TCXO; 1=PLL"]
30116        pub type Uart0ClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
30117        #[doc = "Field `uart1_clk_sel` reader - UART1 clock select"]
30118        pub type Uart1ClkSelR = crate::BitReader;
30119        #[doc = "Field `uart1_clk_sel` writer - UART1 clock select"]
30120        pub type Uart1ClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
30121        #[doc = "Field `uart2_clk_sel` reader - UART2 clock select"]
30122        pub type Uart2ClkSelR = crate::BitReader;
30123        #[doc = "Field `uart2_clk_sel` writer - UART2 clock select"]
30124        pub type Uart2ClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
30125        #[doc = "Field `spi_clk_sel` reader - SPI clock select"]
30126        pub type SpiClkSelR = crate::BitReader;
30127        #[doc = "Field `spi_clk_sel` writer - SPI clock select"]
30128        pub type SpiClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
30129        #[doc = "Field `pwm_clk_sel` reader - PWM clock: 0=TCXO; 1=PLL"]
30130        pub type PwmClkSelR = crate::BitReader;
30131        #[doc = "Field `pwm_clk_sel` writer - PWM clock: 0=TCXO; 1=PLL"]
30132        pub type PwmClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
30133        #[doc = "Field `bus_clk_sel` reader - Bus clock select"]
30134        pub type BusClkSelR = crate::BitReader;
30135        #[doc = "Field `bus_clk_sel` writer - Bus clock select"]
30136        pub type BusClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
30137        #[doc = "Field `flash_clk_sel` reader - Flash clock: 0=TCXO; 1=PLL"]
30138        pub type FlashClkSelR = crate::BitReader;
30139        #[doc = "Field `flash_clk_sel` writer - Flash clock: 0=TCXO; 1=PLL"]
30140        pub type FlashClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
30141        #[doc = "Field `wifi_phy_clk_sel` reader - WIFI_PHY clock select"]
30142        pub type WifiPhyClkSelR = crate::BitReader;
30143        #[doc = "Field `wifi_phy_clk_sel` writer - WIFI_PHY clock select"]
30144        pub type WifiPhyClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
30145        #[doc = "Field `wifi_mac_clk_sel` reader - WIFI_MAC clock select"]
30146        pub type WifiMacClkSelR = crate::BitReader;
30147        #[doc = "Field `wifi_mac_clk_sel` writer - WIFI_MAC clock select"]
30148        pub type WifiMacClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
30149        impl R {
30150            #[doc = "Bit 0 - RF_CTL clock: 0=TCXO; 1=PLL"]
30151            #[inline(always)]
30152            pub fn rf_ctl_clk_sel(&self) -> RfCtlClkSelR {
30153                RfCtlClkSelR::new((self.bits & 1) != 0)
30154            }
30155            #[doc = "Bit 1 - UART0 clock: 0=TCXO; 1=PLL"]
30156            #[inline(always)]
30157            pub fn uart0_clk_sel(&self) -> Uart0ClkSelR {
30158                Uart0ClkSelR::new(((self.bits >> 1) & 1) != 0)
30159            }
30160            #[doc = "Bit 2 - UART1 clock select"]
30161            #[inline(always)]
30162            pub fn uart1_clk_sel(&self) -> Uart1ClkSelR {
30163                Uart1ClkSelR::new(((self.bits >> 2) & 1) != 0)
30164            }
30165            #[doc = "Bit 3 - UART2 clock select"]
30166            #[inline(always)]
30167            pub fn uart2_clk_sel(&self) -> Uart2ClkSelR {
30168                Uart2ClkSelR::new(((self.bits >> 3) & 1) != 0)
30169            }
30170            #[doc = "Bit 6 - SPI clock select"]
30171            #[inline(always)]
30172            pub fn spi_clk_sel(&self) -> SpiClkSelR {
30173                SpiClkSelR::new(((self.bits >> 6) & 1) != 0)
30174            }
30175            #[doc = "Bit 7 - PWM clock: 0=TCXO; 1=PLL"]
30176            #[inline(always)]
30177            pub fn pwm_clk_sel(&self) -> PwmClkSelR {
30178                PwmClkSelR::new(((self.bits >> 7) & 1) != 0)
30179            }
30180            #[doc = "Bit 17 - Bus clock select"]
30181            #[inline(always)]
30182            pub fn bus_clk_sel(&self) -> BusClkSelR {
30183                BusClkSelR::new(((self.bits >> 17) & 1) != 0)
30184            }
30185            #[doc = "Bit 18 - Flash clock: 0=TCXO; 1=PLL"]
30186            #[inline(always)]
30187            pub fn flash_clk_sel(&self) -> FlashClkSelR {
30188                FlashClkSelR::new(((self.bits >> 18) & 1) != 0)
30189            }
30190            #[doc = "Bit 19 - WIFI_PHY clock select"]
30191            #[inline(always)]
30192            pub fn wifi_phy_clk_sel(&self) -> WifiPhyClkSelR {
30193                WifiPhyClkSelR::new(((self.bits >> 19) & 1) != 0)
30194            }
30195            #[doc = "Bit 20 - WIFI_MAC clock select"]
30196            #[inline(always)]
30197            pub fn wifi_mac_clk_sel(&self) -> WifiMacClkSelR {
30198                WifiMacClkSelR::new(((self.bits >> 20) & 1) != 0)
30199            }
30200        }
30201        impl W {
30202            #[doc = "Bit 0 - RF_CTL clock: 0=TCXO; 1=PLL"]
30203            #[inline(always)]
30204            pub fn rf_ctl_clk_sel(&mut self) -> RfCtlClkSelW<'_, ClkSelSpec> {
30205                RfCtlClkSelW::new(self, 0)
30206            }
30207            #[doc = "Bit 1 - UART0 clock: 0=TCXO; 1=PLL"]
30208            #[inline(always)]
30209            pub fn uart0_clk_sel(&mut self) -> Uart0ClkSelW<'_, ClkSelSpec> {
30210                Uart0ClkSelW::new(self, 1)
30211            }
30212            #[doc = "Bit 2 - UART1 clock select"]
30213            #[inline(always)]
30214            pub fn uart1_clk_sel(&mut self) -> Uart1ClkSelW<'_, ClkSelSpec> {
30215                Uart1ClkSelW::new(self, 2)
30216            }
30217            #[doc = "Bit 3 - UART2 clock select"]
30218            #[inline(always)]
30219            pub fn uart2_clk_sel(&mut self) -> Uart2ClkSelW<'_, ClkSelSpec> {
30220                Uart2ClkSelW::new(self, 3)
30221            }
30222            #[doc = "Bit 6 - SPI clock select"]
30223            #[inline(always)]
30224            pub fn spi_clk_sel(&mut self) -> SpiClkSelW<'_, ClkSelSpec> {
30225                SpiClkSelW::new(self, 6)
30226            }
30227            #[doc = "Bit 7 - PWM clock: 0=TCXO; 1=PLL"]
30228            #[inline(always)]
30229            pub fn pwm_clk_sel(&mut self) -> PwmClkSelW<'_, ClkSelSpec> {
30230                PwmClkSelW::new(self, 7)
30231            }
30232            #[doc = "Bit 17 - Bus clock select"]
30233            #[inline(always)]
30234            pub fn bus_clk_sel(&mut self) -> BusClkSelW<'_, ClkSelSpec> {
30235                BusClkSelW::new(self, 17)
30236            }
30237            #[doc = "Bit 18 - Flash clock: 0=TCXO; 1=PLL"]
30238            #[inline(always)]
30239            pub fn flash_clk_sel(&mut self) -> FlashClkSelW<'_, ClkSelSpec> {
30240                FlashClkSelW::new(self, 18)
30241            }
30242            #[doc = "Bit 19 - WIFI_PHY clock select"]
30243            #[inline(always)]
30244            pub fn wifi_phy_clk_sel(&mut self) -> WifiPhyClkSelW<'_, ClkSelSpec> {
30245                WifiPhyClkSelW::new(self, 19)
30246            }
30247            #[doc = "Bit 20 - WIFI_MAC clock select"]
30248            #[inline(always)]
30249            pub fn wifi_mac_clk_sel(&mut self) -> WifiMacClkSelW<'_, ClkSelSpec> {
30250                WifiMacClkSelW::new(self, 20)
30251            }
30252        }
30253        #[doc = "Clock source select register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30254        pub struct ClkSelSpec;
30255        impl crate::RegisterSpec for ClkSelSpec {
30256            type Ux = u32;
30257        }
30258        #[doc = "`read()` method returns [`clk_sel::R`](R) reader structure"]
30259        impl crate::Readable for ClkSelSpec {}
30260        #[doc = "`write(|w| ..)` method takes [`clk_sel::W`](W) writer structure"]
30261        impl crate::Writable for ClkSelSpec {
30262            type Safety = crate::Unsafe;
30263        }
30264        #[doc = "`reset()` method sets CLK_SEL to value 0"]
30265        impl crate::Resettable for ClkSelSpec {}
30266    }
30267    #[doc = "RST_SOFT_CFG0 (rw) register accessor: Soft reset configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_soft_cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_soft_cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_soft_cfg0`] module"]
30268    #[doc(alias = "RST_SOFT_CFG0")]
30269    pub type RstSoftCfg0 = crate::Reg<rst_soft_cfg0::RstSoftCfg0Spec>;
30270    #[doc = "Soft reset configuration register 0"]
30271    pub mod rst_soft_cfg0 {
30272        #[doc = "Register `RST_SOFT_CFG0` reader"]
30273        pub type R = crate::R<RstSoftCfg0Spec>;
30274        #[doc = "Register `RST_SOFT_CFG0` writer"]
30275        pub type W = crate::W<RstSoftCfg0Spec>;
30276        #[doc = "Field `cfg0_b3_b15` reader - 13-bit soft reset control (bits \\[15:3\\])"]
30277        pub type Cfg0B3B15R = crate::FieldReader<u16>;
30278        #[doc = "Field `cfg0_b3_b15` writer - 13-bit soft reset control (bits \\[15:3\\])"]
30279        pub type Cfg0B3B15W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
30280        #[doc = "Field `cfg0_b17_b24` reader - 8-bit soft reset control (bits \\[24:17\\])"]
30281        pub type Cfg0B17B24R = crate::FieldReader;
30282        #[doc = "Field `cfg0_b17_b24` writer - 8-bit soft reset control (bits \\[24:17\\])"]
30283        pub type Cfg0B17B24W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
30284        #[doc = "Field `cfg0_b27_b28` reader - 2-bit soft reset control (bits \\[28:27\\])"]
30285        pub type Cfg0B27B28R = crate::FieldReader;
30286        #[doc = "Field `cfg0_b27_b28` writer - 2-bit soft reset control (bits \\[28:27\\])"]
30287        pub type Cfg0B27B28W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
30288        #[doc = "Field `cfg0_b30` reader - Soft reset bit 30"]
30289        pub type Cfg0B30R = crate::BitReader;
30290        #[doc = "Field `cfg0_b30` writer - Soft reset bit 30"]
30291        pub type Cfg0B30W<'a, REG> = crate::BitWriter<'a, REG>;
30292        impl R {
30293            #[doc = "Bits 3:15 - 13-bit soft reset control (bits \\[15:3\\])"]
30294            #[inline(always)]
30295            pub fn cfg0_b3_b15(&self) -> Cfg0B3B15R {
30296                Cfg0B3B15R::new(((self.bits >> 3) & 0x1fff) as u16)
30297            }
30298            #[doc = "Bits 17:24 - 8-bit soft reset control (bits \\[24:17\\])"]
30299            #[inline(always)]
30300            pub fn cfg0_b17_b24(&self) -> Cfg0B17B24R {
30301                Cfg0B17B24R::new(((self.bits >> 17) & 0xff) as u8)
30302            }
30303            #[doc = "Bits 27:28 - 2-bit soft reset control (bits \\[28:27\\])"]
30304            #[inline(always)]
30305            pub fn cfg0_b27_b28(&self) -> Cfg0B27B28R {
30306                Cfg0B27B28R::new(((self.bits >> 27) & 3) as u8)
30307            }
30308            #[doc = "Bit 30 - Soft reset bit 30"]
30309            #[inline(always)]
30310            pub fn cfg0_b30(&self) -> Cfg0B30R {
30311                Cfg0B30R::new(((self.bits >> 30) & 1) != 0)
30312            }
30313        }
30314        impl W {
30315            #[doc = "Bits 3:15 - 13-bit soft reset control (bits \\[15:3\\])"]
30316            #[inline(always)]
30317            pub fn cfg0_b3_b15(&mut self) -> Cfg0B3B15W<'_, RstSoftCfg0Spec> {
30318                Cfg0B3B15W::new(self, 3)
30319            }
30320            #[doc = "Bits 17:24 - 8-bit soft reset control (bits \\[24:17\\])"]
30321            #[inline(always)]
30322            pub fn cfg0_b17_b24(&mut self) -> Cfg0B17B24W<'_, RstSoftCfg0Spec> {
30323                Cfg0B17B24W::new(self, 17)
30324            }
30325            #[doc = "Bits 27:28 - 2-bit soft reset control (bits \\[28:27\\])"]
30326            #[inline(always)]
30327            pub fn cfg0_b27_b28(&mut self) -> Cfg0B27B28W<'_, RstSoftCfg0Spec> {
30328                Cfg0B27B28W::new(self, 27)
30329            }
30330            #[doc = "Bit 30 - Soft reset bit 30"]
30331            #[inline(always)]
30332            pub fn cfg0_b30(&mut self) -> Cfg0B30W<'_, RstSoftCfg0Spec> {
30333                Cfg0B30W::new(self, 30)
30334            }
30335        }
30336        #[doc = "Soft reset configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_soft_cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_soft_cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30337        pub struct RstSoftCfg0Spec;
30338        impl crate::RegisterSpec for RstSoftCfg0Spec {
30339            type Ux = u32;
30340        }
30341        #[doc = "`read()` method returns [`rst_soft_cfg0::R`](R) reader structure"]
30342        impl crate::Readable for RstSoftCfg0Spec {}
30343        #[doc = "`write(|w| ..)` method takes [`rst_soft_cfg0::W`](W) writer structure"]
30344        impl crate::Writable for RstSoftCfg0Spec {
30345            type Safety = crate::Unsafe;
30346        }
30347        #[doc = "`reset()` method sets RST_SOFT_CFG0 to value 0"]
30348        impl crate::Resettable for RstSoftCfg0Spec {}
30349    }
30350    #[doc = "RST_SOFT_CFG1 (rw) register accessor: Soft reset configuration register 1 (active low)\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_soft_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_soft_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_soft_cfg1`] module"]
30351    #[doc(alias = "RST_SOFT_CFG1")]
30352    pub type RstSoftCfg1 = crate::Reg<rst_soft_cfg1::RstSoftCfg1Spec>;
30353    #[doc = "Soft reset configuration register 1 (active low)"]
30354    pub mod rst_soft_cfg1 {
30355        #[doc = "Register `RST_SOFT_CFG1` reader"]
30356        pub type R = crate::R<RstSoftCfg1Spec>;
30357        #[doc = "Register `RST_SOFT_CFG1` writer"]
30358        pub type W = crate::W<RstSoftCfg1Spec>;
30359        #[doc = "Field `soft_rst_gpio_n` reader - GPIO module reset: 0=reset; 1=released"]
30360        pub type SoftRstGpioNR = crate::BitReader;
30361        #[doc = "Field `soft_rst_gpio_n` writer - GPIO module reset: 0=reset; 1=released"]
30362        pub type SoftRstGpioNW<'a, REG> = crate::BitWriter<'a, REG>;
30363        #[doc = "Field `soft_rst_tglp_n` reader - TGLP (BT) reset: 0=reset; 1=released"]
30364        pub type SoftRstTglpNR = crate::BitReader;
30365        #[doc = "Field `soft_rst_tglp_n` writer - TGLP (BT) reset: 0=reset; 1=released"]
30366        pub type SoftRstTglpNW<'a, REG> = crate::BitWriter<'a, REG>;
30367        #[doc = "Field `soft_rst_bsub_n` reader - BSUB (BT) reset: 0=reset; 1=released"]
30368        pub type SoftRstBsubNR = crate::BitReader;
30369        #[doc = "Field `soft_rst_bsub_n` writer - BSUB (BT) reset: 0=reset; 1=released"]
30370        pub type SoftRstBsubNW<'a, REG> = crate::BitWriter<'a, REG>;
30371        #[doc = "Field `soft_rst_crg_bsub_n` reader - CRG BSUB (BT) reset: 0=reset; 1=released"]
30372        pub type SoftRstCrgBsubNR = crate::BitReader;
30373        #[doc = "Field `soft_rst_crg_bsub_n` writer - CRG BSUB (BT) reset: 0=reset; 1=released"]
30374        pub type SoftRstCrgBsubNW<'a, REG> = crate::BitWriter<'a, REG>;
30375        #[doc = "Field `soft_rst_wifi_n` reader - WIFI subsystem reset: 0=reset; 1=released"]
30376        pub type SoftRstWifiNR = crate::BitReader;
30377        #[doc = "Field `soft_rst_wifi_n` writer - WIFI subsystem reset: 0=reset; 1=released"]
30378        pub type SoftRstWifiNW<'a, REG> = crate::BitWriter<'a, REG>;
30379        #[doc = "Field `soft_rst_lsadc_n` reader - LSADC core reset: 0=reset; 1=released"]
30380        pub type SoftRstLsadcNR = crate::BitReader;
30381        #[doc = "Field `soft_rst_lsadc_n` writer - LSADC core reset: 0=reset; 1=released"]
30382        pub type SoftRstLsadcNW<'a, REG> = crate::BitWriter<'a, REG>;
30383        #[doc = "Field `soft_rst_tcxo_cnt_n` reader - TCXO counter reset: 0=reset; 1=released"]
30384        pub type SoftRstTcxoCntNR = crate::BitReader;
30385        #[doc = "Field `soft_rst_tcxo_cnt_n` writer - TCXO counter reset: 0=reset; 1=released"]
30386        pub type SoftRstTcxoCntNW<'a, REG> = crate::BitWriter<'a, REG>;
30387        #[doc = "Field `soft_rst_lsadc_bus_n` reader - LSADC bus interface reset: 0=reset; 1=released"]
30388        pub type SoftRstLsadcBusNR = crate::BitReader;
30389        #[doc = "Field `soft_rst_lsadc_bus_n` writer - LSADC bus interface reset: 0=reset; 1=released"]
30390        pub type SoftRstLsadcBusNW<'a, REG> = crate::BitWriter<'a, REG>;
30391        #[doc = "Field `soft_rst_wcpu_mem_ctl_n` reader - WCPU memory controller reset: 0=reset; 1=released"]
30392        pub type SoftRstWcpuMemCtlNR = crate::BitReader;
30393        #[doc = "Field `soft_rst_wcpu_mem_ctl_n` writer - WCPU memory controller reset: 0=reset; 1=released"]
30394        pub type SoftRstWcpuMemCtlNW<'a, REG> = crate::BitWriter<'a, REG>;
30395        impl R {
30396            #[doc = "Bit 0 - GPIO module reset: 0=reset; 1=released"]
30397            #[inline(always)]
30398            pub fn soft_rst_gpio_n(&self) -> SoftRstGpioNR {
30399                SoftRstGpioNR::new((self.bits & 1) != 0)
30400            }
30401            #[doc = "Bit 1 - TGLP (BT) reset: 0=reset; 1=released"]
30402            #[inline(always)]
30403            pub fn soft_rst_tglp_n(&self) -> SoftRstTglpNR {
30404                SoftRstTglpNR::new(((self.bits >> 1) & 1) != 0)
30405            }
30406            #[doc = "Bit 2 - BSUB (BT) reset: 0=reset; 1=released"]
30407            #[inline(always)]
30408            pub fn soft_rst_bsub_n(&self) -> SoftRstBsubNR {
30409                SoftRstBsubNR::new(((self.bits >> 2) & 1) != 0)
30410            }
30411            #[doc = "Bit 3 - CRG BSUB (BT) reset: 0=reset; 1=released"]
30412            #[inline(always)]
30413            pub fn soft_rst_crg_bsub_n(&self) -> SoftRstCrgBsubNR {
30414                SoftRstCrgBsubNR::new(((self.bits >> 3) & 1) != 0)
30415            }
30416            #[doc = "Bit 4 - WIFI subsystem reset: 0=reset; 1=released"]
30417            #[inline(always)]
30418            pub fn soft_rst_wifi_n(&self) -> SoftRstWifiNR {
30419                SoftRstWifiNR::new(((self.bits >> 4) & 1) != 0)
30420            }
30421            #[doc = "Bit 5 - LSADC core reset: 0=reset; 1=released"]
30422            #[inline(always)]
30423            pub fn soft_rst_lsadc_n(&self) -> SoftRstLsadcNR {
30424                SoftRstLsadcNR::new(((self.bits >> 5) & 1) != 0)
30425            }
30426            #[doc = "Bit 6 - TCXO counter reset: 0=reset; 1=released"]
30427            #[inline(always)]
30428            pub fn soft_rst_tcxo_cnt_n(&self) -> SoftRstTcxoCntNR {
30429                SoftRstTcxoCntNR::new(((self.bits >> 6) & 1) != 0)
30430            }
30431            #[doc = "Bit 7 - LSADC bus interface reset: 0=reset; 1=released"]
30432            #[inline(always)]
30433            pub fn soft_rst_lsadc_bus_n(&self) -> SoftRstLsadcBusNR {
30434                SoftRstLsadcBusNR::new(((self.bits >> 7) & 1) != 0)
30435            }
30436            #[doc = "Bit 8 - WCPU memory controller reset: 0=reset; 1=released"]
30437            #[inline(always)]
30438            pub fn soft_rst_wcpu_mem_ctl_n(&self) -> SoftRstWcpuMemCtlNR {
30439                SoftRstWcpuMemCtlNR::new(((self.bits >> 8) & 1) != 0)
30440            }
30441        }
30442        impl W {
30443            #[doc = "Bit 0 - GPIO module reset: 0=reset; 1=released"]
30444            #[inline(always)]
30445            pub fn soft_rst_gpio_n(&mut self) -> SoftRstGpioNW<'_, RstSoftCfg1Spec> {
30446                SoftRstGpioNW::new(self, 0)
30447            }
30448            #[doc = "Bit 1 - TGLP (BT) reset: 0=reset; 1=released"]
30449            #[inline(always)]
30450            pub fn soft_rst_tglp_n(&mut self) -> SoftRstTglpNW<'_, RstSoftCfg1Spec> {
30451                SoftRstTglpNW::new(self, 1)
30452            }
30453            #[doc = "Bit 2 - BSUB (BT) reset: 0=reset; 1=released"]
30454            #[inline(always)]
30455            pub fn soft_rst_bsub_n(&mut self) -> SoftRstBsubNW<'_, RstSoftCfg1Spec> {
30456                SoftRstBsubNW::new(self, 2)
30457            }
30458            #[doc = "Bit 3 - CRG BSUB (BT) reset: 0=reset; 1=released"]
30459            #[inline(always)]
30460            pub fn soft_rst_crg_bsub_n(&mut self) -> SoftRstCrgBsubNW<'_, RstSoftCfg1Spec> {
30461                SoftRstCrgBsubNW::new(self, 3)
30462            }
30463            #[doc = "Bit 4 - WIFI subsystem reset: 0=reset; 1=released"]
30464            #[inline(always)]
30465            pub fn soft_rst_wifi_n(&mut self) -> SoftRstWifiNW<'_, RstSoftCfg1Spec> {
30466                SoftRstWifiNW::new(self, 4)
30467            }
30468            #[doc = "Bit 5 - LSADC core reset: 0=reset; 1=released"]
30469            #[inline(always)]
30470            pub fn soft_rst_lsadc_n(&mut self) -> SoftRstLsadcNW<'_, RstSoftCfg1Spec> {
30471                SoftRstLsadcNW::new(self, 5)
30472            }
30473            #[doc = "Bit 6 - TCXO counter reset: 0=reset; 1=released"]
30474            #[inline(always)]
30475            pub fn soft_rst_tcxo_cnt_n(&mut self) -> SoftRstTcxoCntNW<'_, RstSoftCfg1Spec> {
30476                SoftRstTcxoCntNW::new(self, 6)
30477            }
30478            #[doc = "Bit 7 - LSADC bus interface reset: 0=reset; 1=released"]
30479            #[inline(always)]
30480            pub fn soft_rst_lsadc_bus_n(&mut self) -> SoftRstLsadcBusNW<'_, RstSoftCfg1Spec> {
30481                SoftRstLsadcBusNW::new(self, 7)
30482            }
30483            #[doc = "Bit 8 - WCPU memory controller reset: 0=reset; 1=released"]
30484            #[inline(always)]
30485            pub fn soft_rst_wcpu_mem_ctl_n(&mut self) -> SoftRstWcpuMemCtlNW<'_, RstSoftCfg1Spec> {
30486                SoftRstWcpuMemCtlNW::new(self, 8)
30487            }
30488        }
30489        #[doc = "Soft reset configuration register 1 (active low)\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_soft_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_soft_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30490        pub struct RstSoftCfg1Spec;
30491        impl crate::RegisterSpec for RstSoftCfg1Spec {
30492            type Ux = u32;
30493        }
30494        #[doc = "`read()` method returns [`rst_soft_cfg1::R`](R) reader structure"]
30495        impl crate::Readable for RstSoftCfg1Spec {}
30496        #[doc = "`write(|w| ..)` method takes [`rst_soft_cfg1::W`](W) writer structure"]
30497        impl crate::Writable for RstSoftCfg1Spec {
30498            type Safety = crate::Unsafe;
30499        }
30500        #[doc = "`reset()` method sets RST_SOFT_CFG1 to value 0xffff_ffff"]
30501        impl crate::Resettable for RstSoftCfg1Spec {
30502            const RESET_VALUE: u32 = 0xffff_ffff;
30503        }
30504    }
30505}
30506#[doc = "Secure DMA controller (4 channels, same layout as MDMA v151). Channels logically mapped as 8-11."]
30507pub type Sdma = crate::Periph<dma::RegisterBlock, 0x520a_0000>;
30508impl core::fmt::Debug for Sdma {
30509    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30510        f.debug_struct("Sdma").finish()
30511    }
30512}
30513#[doc = "Secure DMA controller (4 channels, same layout as MDMA v151). Channels logically mapped as 8-11."]
30514pub use self::dma as sdma;
30515#[doc = "Ultra-low-power GPIO controller (8 pins, GPIO\\[107:114\\]). Same register layout as GPIO0."]
30516pub type UlpGpio = crate::Periph<gpio0::RegisterBlock, 0x5703_0000>;
30517impl core::fmt::Debug for UlpGpio {
30518    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30519        f.debug_struct("UlpGpio").finish()
30520    }
30521}
30522#[doc = "Ultra-low-power GPIO controller (8 pins, GPIO\\[107:114\\]). Same register layout as GPIO0."]
30523pub use self::gpio0 as ulp_gpio;
30524#[doc = "SYS_CTL2 sub-block: RF Wideband Control Register Block - WL/BT RF analog interface control"]
30525pub type RfWbCtl = crate::Periph<rf_wb_ctl::RegisterBlock, 0x4400_4000>;
30526impl core::fmt::Debug for RfWbCtl {
30527    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30528        f.debug_struct("RfWbCtl").finish()
30529    }
30530}
30531#[doc = "SYS_CTL2 sub-block: RF Wideband Control Register Block - WL/BT RF analog interface control"]
30532pub mod rf_wb_ctl {
30533    #[repr(C)]
30534    #[doc = "Register block"]
30535    pub struct RegisterBlock {
30536        sys_ctl_id: SysCtlId,
30537        _reserved1: [u8; 0x0c],
30538        rf_wl_reg_clk_ctl: RfWlRegClkCtl,
30539        rf_wl_reg_soft_rstn: RfWlRegSoftRstn,
30540        rf_wl_reg_cmd_soft_rstn: RfWlRegCmdSoftRstn,
30541        rf_wl_reg_cmd_fifo_sts: RfWlRegCmdFifoSts,
30542        rf_wl_cbb_dis: RfWlCbbDis,
30543        rf_bt_cbb_dis: RfBtCbbDis,
30544        _reserved7: [u8; 0x08],
30545        abb_adc_ctrl: AbbAdcCtrl,
30546        abb_dac_ctrl: AbbDacCtrl,
30547        abb_en_ctrl: AbbEnCtrl,
30548        cfg_wl_adc_mux: CfgWlAdcMux,
30549        cfg_rf_man_en_ctrl: CfgRfManEnCtrl,
30550        cfg_trxen_ctrl: CfgTrxenCtrl,
30551        cfg_dcoc_iq_ctrl: CfgDcocIqCtrl,
30552        cfg_pa_idx_ctrl: CfgPaIdxCtrl,
30553        cfg_lpf_ctrl: CfgLpfCtrl,
30554        cfg_radar_ctrl: CfgRadarCtrl,
30555        cfg_ppa_code: CfgPpaCode,
30556        cfg_temp_lock_ctrl: CfgTempLockCtrl,
30557        cfg_temp_bank_sel_ctrl: CfgTempBankSelCtrl,
30558        cfg_rf_diag_mux: CfgRfDiagMux,
30559    }
30560    impl RegisterBlock {
30561        #[doc = "0x00 - System control ID register"]
30562        #[inline(always)]
30563        pub const fn sys_ctl_id(&self) -> &SysCtlId {
30564            &self.sys_ctl_id
30565        }
30566        #[doc = "0x10 - RF WL register clock control"]
30567        #[inline(always)]
30568        pub const fn rf_wl_reg_clk_ctl(&self) -> &RfWlRegClkCtl {
30569            &self.rf_wl_reg_clk_ctl
30570        }
30571        #[doc = "0x14 - RF WL register soft reset"]
30572        #[inline(always)]
30573        pub const fn rf_wl_reg_soft_rstn(&self) -> &RfWlRegSoftRstn {
30574            &self.rf_wl_reg_soft_rstn
30575        }
30576        #[doc = "0x18 - RF WL command soft reset"]
30577        #[inline(always)]
30578        pub const fn rf_wl_reg_cmd_soft_rstn(&self) -> &RfWlRegCmdSoftRstn {
30579            &self.rf_wl_reg_cmd_soft_rstn
30580        }
30581        #[doc = "0x1c - RF WL command FIFO status"]
30582        #[inline(always)]
30583        pub const fn rf_wl_reg_cmd_fifo_sts(&self) -> &RfWlRegCmdFifoSts {
30584            &self.rf_wl_reg_cmd_fifo_sts
30585        }
30586        #[doc = "0x20 - RF WL CBB disable"]
30587        #[inline(always)]
30588        pub const fn rf_wl_cbb_dis(&self) -> &RfWlCbbDis {
30589            &self.rf_wl_cbb_dis
30590        }
30591        #[doc = "0x24 - RF BT CBB disable"]
30592        #[inline(always)]
30593        pub const fn rf_bt_cbb_dis(&self) -> &RfBtCbbDis {
30594            &self.rf_bt_cbb_dis
30595        }
30596        #[doc = "0x30 - ABB ADC control"]
30597        #[inline(always)]
30598        pub const fn abb_adc_ctrl(&self) -> &AbbAdcCtrl {
30599            &self.abb_adc_ctrl
30600        }
30601        #[doc = "0x34 - ABB DAC control"]
30602        #[inline(always)]
30603        pub const fn abb_dac_ctrl(&self) -> &AbbDacCtrl {
30604            &self.abb_dac_ctrl
30605        }
30606        #[doc = "0x38 - ABB enable control"]
30607        #[inline(always)]
30608        pub const fn abb_en_ctrl(&self) -> &AbbEnCtrl {
30609            &self.abb_en_ctrl
30610        }
30611        #[doc = "0x3c - WL ADC mux configuration"]
30612        #[inline(always)]
30613        pub const fn cfg_wl_adc_mux(&self) -> &CfgWlAdcMux {
30614            &self.cfg_wl_adc_mux
30615        }
30616        #[doc = "0x40 - RF manual enable control"]
30617        #[inline(always)]
30618        pub const fn cfg_rf_man_en_ctrl(&self) -> &CfgRfManEnCtrl {
30619            &self.cfg_rf_man_en_ctrl
30620        }
30621        #[doc = "0x44 - TRX enable control"]
30622        #[inline(always)]
30623        pub const fn cfg_trxen_ctrl(&self) -> &CfgTrxenCtrl {
30624            &self.cfg_trxen_ctrl
30625        }
30626        #[doc = "0x48 - DCOC IQ control"]
30627        #[inline(always)]
30628        pub const fn cfg_dcoc_iq_ctrl(&self) -> &CfgDcocIqCtrl {
30629            &self.cfg_dcoc_iq_ctrl
30630        }
30631        #[doc = "0x4c - PA index control"]
30632        #[inline(always)]
30633        pub const fn cfg_pa_idx_ctrl(&self) -> &CfgPaIdxCtrl {
30634            &self.cfg_pa_idx_ctrl
30635        }
30636        #[doc = "0x50 - LPF control"]
30637        #[inline(always)]
30638        pub const fn cfg_lpf_ctrl(&self) -> &CfgLpfCtrl {
30639            &self.cfg_lpf_ctrl
30640        }
30641        #[doc = "0x54 - Radar control"]
30642        #[inline(always)]
30643        pub const fn cfg_radar_ctrl(&self) -> &CfgRadarCtrl {
30644            &self.cfg_radar_ctrl
30645        }
30646        #[doc = "0x58 - PPA code register"]
30647        #[inline(always)]
30648        pub const fn cfg_ppa_code(&self) -> &CfgPpaCode {
30649            &self.cfg_ppa_code
30650        }
30651        #[doc = "0x5c - Temperature lock control"]
30652        #[inline(always)]
30653        pub const fn cfg_temp_lock_ctrl(&self) -> &CfgTempLockCtrl {
30654            &self.cfg_temp_lock_ctrl
30655        }
30656        #[doc = "0x60 - Temperature bank select control"]
30657        #[inline(always)]
30658        pub const fn cfg_temp_bank_sel_ctrl(&self) -> &CfgTempBankSelCtrl {
30659            &self.cfg_temp_bank_sel_ctrl
30660        }
30661        #[doc = "0x64 - RF diagnostic mux"]
30662        #[inline(always)]
30663        pub const fn cfg_rf_diag_mux(&self) -> &CfgRfDiagMux {
30664            &self.cfg_rf_diag_mux
30665        }
30666    }
30667    #[doc = "SYS_CTL_ID (rw) register accessor: System control ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_ctl_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_ctl_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_ctl_id`] module"]
30668    #[doc(alias = "SYS_CTL_ID")]
30669    pub type SysCtlId = crate::Reg<sys_ctl_id::SysCtlIdSpec>;
30670    #[doc = "System control ID register"]
30671    pub mod sys_ctl_id {
30672        #[doc = "Register `SYS_CTL_ID` reader"]
30673        pub type R = crate::R<SysCtlIdSpec>;
30674        #[doc = "Register `SYS_CTL_ID` writer"]
30675        pub type W = crate::W<SysCtlIdSpec>;
30676        impl core::fmt::Debug for R {
30677            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30678                write!(f, "{}", self.bits())
30679            }
30680        }
30681        impl W {}
30682        #[doc = "System control ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_ctl_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_ctl_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30683        pub struct SysCtlIdSpec;
30684        impl crate::RegisterSpec for SysCtlIdSpec {
30685            type Ux = u32;
30686        }
30687        #[doc = "`read()` method returns [`sys_ctl_id::R`](R) reader structure"]
30688        impl crate::Readable for SysCtlIdSpec {}
30689        #[doc = "`write(|w| ..)` method takes [`sys_ctl_id::W`](W) writer structure"]
30690        impl crate::Writable for SysCtlIdSpec {
30691            type Safety = crate::Unsafe;
30692        }
30693        #[doc = "`reset()` method sets SYS_CTL_ID to value 0"]
30694        impl crate::Resettable for SysCtlIdSpec {}
30695    }
30696    #[doc = "RF_WL_REG_CLK_CTL (rw) register accessor: RF WL register clock control\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_clk_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_clk_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_wl_reg_clk_ctl`] module"]
30697    #[doc(alias = "RF_WL_REG_CLK_CTL")]
30698    pub type RfWlRegClkCtl = crate::Reg<rf_wl_reg_clk_ctl::RfWlRegClkCtlSpec>;
30699    #[doc = "RF WL register clock control"]
30700    pub mod rf_wl_reg_clk_ctl {
30701        #[doc = "Register `RF_WL_REG_CLK_CTL` reader"]
30702        pub type R = crate::R<RfWlRegClkCtlSpec>;
30703        #[doc = "Register `RF_WL_REG_CLK_CTL` writer"]
30704        pub type W = crate::W<RfWlRegClkCtlSpec>;
30705        impl core::fmt::Debug for R {
30706            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30707                write!(f, "{}", self.bits())
30708            }
30709        }
30710        impl W {}
30711        #[doc = "RF WL register clock control\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_clk_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_clk_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30712        pub struct RfWlRegClkCtlSpec;
30713        impl crate::RegisterSpec for RfWlRegClkCtlSpec {
30714            type Ux = u32;
30715        }
30716        #[doc = "`read()` method returns [`rf_wl_reg_clk_ctl::R`](R) reader structure"]
30717        impl crate::Readable for RfWlRegClkCtlSpec {}
30718        #[doc = "`write(|w| ..)` method takes [`rf_wl_reg_clk_ctl::W`](W) writer structure"]
30719        impl crate::Writable for RfWlRegClkCtlSpec {
30720            type Safety = crate::Unsafe;
30721        }
30722        #[doc = "`reset()` method sets RF_WL_REG_CLK_CTL to value 0"]
30723        impl crate::Resettable for RfWlRegClkCtlSpec {}
30724    }
30725    #[doc = "RF_WL_REG_SOFT_RSTN (rw) register accessor: RF WL register soft reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_soft_rstn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_soft_rstn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_wl_reg_soft_rstn`] module"]
30726    #[doc(alias = "RF_WL_REG_SOFT_RSTN")]
30727    pub type RfWlRegSoftRstn = crate::Reg<rf_wl_reg_soft_rstn::RfWlRegSoftRstnSpec>;
30728    #[doc = "RF WL register soft reset"]
30729    pub mod rf_wl_reg_soft_rstn {
30730        #[doc = "Register `RF_WL_REG_SOFT_RSTN` reader"]
30731        pub type R = crate::R<RfWlRegSoftRstnSpec>;
30732        #[doc = "Register `RF_WL_REG_SOFT_RSTN` writer"]
30733        pub type W = crate::W<RfWlRegSoftRstnSpec>;
30734        impl core::fmt::Debug for R {
30735            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30736                write!(f, "{}", self.bits())
30737            }
30738        }
30739        impl W {}
30740        #[doc = "RF WL register soft reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_soft_rstn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_soft_rstn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30741        pub struct RfWlRegSoftRstnSpec;
30742        impl crate::RegisterSpec for RfWlRegSoftRstnSpec {
30743            type Ux = u32;
30744        }
30745        #[doc = "`read()` method returns [`rf_wl_reg_soft_rstn::R`](R) reader structure"]
30746        impl crate::Readable for RfWlRegSoftRstnSpec {}
30747        #[doc = "`write(|w| ..)` method takes [`rf_wl_reg_soft_rstn::W`](W) writer structure"]
30748        impl crate::Writable for RfWlRegSoftRstnSpec {
30749            type Safety = crate::Unsafe;
30750        }
30751        #[doc = "`reset()` method sets RF_WL_REG_SOFT_RSTN to value 0"]
30752        impl crate::Resettable for RfWlRegSoftRstnSpec {}
30753    }
30754    #[doc = "RF_WL_REG_CMD_SOFT_RSTN (rw) register accessor: RF WL command soft reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_cmd_soft_rstn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_cmd_soft_rstn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_wl_reg_cmd_soft_rstn`] module"]
30755    #[doc(alias = "RF_WL_REG_CMD_SOFT_RSTN")]
30756    pub type RfWlRegCmdSoftRstn = crate::Reg<rf_wl_reg_cmd_soft_rstn::RfWlRegCmdSoftRstnSpec>;
30757    #[doc = "RF WL command soft reset"]
30758    pub mod rf_wl_reg_cmd_soft_rstn {
30759        #[doc = "Register `RF_WL_REG_CMD_SOFT_RSTN` reader"]
30760        pub type R = crate::R<RfWlRegCmdSoftRstnSpec>;
30761        #[doc = "Register `RF_WL_REG_CMD_SOFT_RSTN` writer"]
30762        pub type W = crate::W<RfWlRegCmdSoftRstnSpec>;
30763        impl core::fmt::Debug for R {
30764            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30765                write!(f, "{}", self.bits())
30766            }
30767        }
30768        impl W {}
30769        #[doc = "RF WL command soft reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_cmd_soft_rstn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_cmd_soft_rstn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30770        pub struct RfWlRegCmdSoftRstnSpec;
30771        impl crate::RegisterSpec for RfWlRegCmdSoftRstnSpec {
30772            type Ux = u32;
30773        }
30774        #[doc = "`read()` method returns [`rf_wl_reg_cmd_soft_rstn::R`](R) reader structure"]
30775        impl crate::Readable for RfWlRegCmdSoftRstnSpec {}
30776        #[doc = "`write(|w| ..)` method takes [`rf_wl_reg_cmd_soft_rstn::W`](W) writer structure"]
30777        impl crate::Writable for RfWlRegCmdSoftRstnSpec {
30778            type Safety = crate::Unsafe;
30779        }
30780        #[doc = "`reset()` method sets RF_WL_REG_CMD_SOFT_RSTN to value 0"]
30781        impl crate::Resettable for RfWlRegCmdSoftRstnSpec {}
30782    }
30783    #[doc = "RF_WL_REG_CMD_FIFO_STS (rw) register accessor: RF WL command FIFO status\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_cmd_fifo_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_cmd_fifo_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_wl_reg_cmd_fifo_sts`] module"]
30784    #[doc(alias = "RF_WL_REG_CMD_FIFO_STS")]
30785    pub type RfWlRegCmdFifoSts = crate::Reg<rf_wl_reg_cmd_fifo_sts::RfWlRegCmdFifoStsSpec>;
30786    #[doc = "RF WL command FIFO status"]
30787    pub mod rf_wl_reg_cmd_fifo_sts {
30788        #[doc = "Register `RF_WL_REG_CMD_FIFO_STS` reader"]
30789        pub type R = crate::R<RfWlRegCmdFifoStsSpec>;
30790        #[doc = "Register `RF_WL_REG_CMD_FIFO_STS` writer"]
30791        pub type W = crate::W<RfWlRegCmdFifoStsSpec>;
30792        impl core::fmt::Debug for R {
30793            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30794                write!(f, "{}", self.bits())
30795            }
30796        }
30797        impl W {}
30798        #[doc = "RF WL command FIFO status\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_cmd_fifo_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_cmd_fifo_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30799        pub struct RfWlRegCmdFifoStsSpec;
30800        impl crate::RegisterSpec for RfWlRegCmdFifoStsSpec {
30801            type Ux = u32;
30802        }
30803        #[doc = "`read()` method returns [`rf_wl_reg_cmd_fifo_sts::R`](R) reader structure"]
30804        impl crate::Readable for RfWlRegCmdFifoStsSpec {}
30805        #[doc = "`write(|w| ..)` method takes [`rf_wl_reg_cmd_fifo_sts::W`](W) writer structure"]
30806        impl crate::Writable for RfWlRegCmdFifoStsSpec {
30807            type Safety = crate::Unsafe;
30808        }
30809        #[doc = "`reset()` method sets RF_WL_REG_CMD_FIFO_STS to value 0"]
30810        impl crate::Resettable for RfWlRegCmdFifoStsSpec {}
30811    }
30812    #[doc = "RF_WL_CBB_DIS (rw) register accessor: RF WL CBB disable\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_cbb_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_cbb_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_wl_cbb_dis`] module"]
30813    #[doc(alias = "RF_WL_CBB_DIS")]
30814    pub type RfWlCbbDis = crate::Reg<rf_wl_cbb_dis::RfWlCbbDisSpec>;
30815    #[doc = "RF WL CBB disable"]
30816    pub mod rf_wl_cbb_dis {
30817        #[doc = "Register `RF_WL_CBB_DIS` reader"]
30818        pub type R = crate::R<RfWlCbbDisSpec>;
30819        #[doc = "Register `RF_WL_CBB_DIS` writer"]
30820        pub type W = crate::W<RfWlCbbDisSpec>;
30821        impl core::fmt::Debug for R {
30822            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30823                write!(f, "{}", self.bits())
30824            }
30825        }
30826        impl W {}
30827        #[doc = "RF WL CBB disable\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_cbb_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_cbb_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30828        pub struct RfWlCbbDisSpec;
30829        impl crate::RegisterSpec for RfWlCbbDisSpec {
30830            type Ux = u32;
30831        }
30832        #[doc = "`read()` method returns [`rf_wl_cbb_dis::R`](R) reader structure"]
30833        impl crate::Readable for RfWlCbbDisSpec {}
30834        #[doc = "`write(|w| ..)` method takes [`rf_wl_cbb_dis::W`](W) writer structure"]
30835        impl crate::Writable for RfWlCbbDisSpec {
30836            type Safety = crate::Unsafe;
30837        }
30838        #[doc = "`reset()` method sets RF_WL_CBB_DIS to value 0"]
30839        impl crate::Resettable for RfWlCbbDisSpec {}
30840    }
30841    #[doc = "RF_BT_CBB_DIS (rw) register accessor: RF BT CBB disable\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_bt_cbb_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_bt_cbb_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_bt_cbb_dis`] module"]
30842    #[doc(alias = "RF_BT_CBB_DIS")]
30843    pub type RfBtCbbDis = crate::Reg<rf_bt_cbb_dis::RfBtCbbDisSpec>;
30844    #[doc = "RF BT CBB disable"]
30845    pub mod rf_bt_cbb_dis {
30846        #[doc = "Register `RF_BT_CBB_DIS` reader"]
30847        pub type R = crate::R<RfBtCbbDisSpec>;
30848        #[doc = "Register `RF_BT_CBB_DIS` writer"]
30849        pub type W = crate::W<RfBtCbbDisSpec>;
30850        impl core::fmt::Debug for R {
30851            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30852                write!(f, "{}", self.bits())
30853            }
30854        }
30855        impl W {}
30856        #[doc = "RF BT CBB disable\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_bt_cbb_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_bt_cbb_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30857        pub struct RfBtCbbDisSpec;
30858        impl crate::RegisterSpec for RfBtCbbDisSpec {
30859            type Ux = u32;
30860        }
30861        #[doc = "`read()` method returns [`rf_bt_cbb_dis::R`](R) reader structure"]
30862        impl crate::Readable for RfBtCbbDisSpec {}
30863        #[doc = "`write(|w| ..)` method takes [`rf_bt_cbb_dis::W`](W) writer structure"]
30864        impl crate::Writable for RfBtCbbDisSpec {
30865            type Safety = crate::Unsafe;
30866        }
30867        #[doc = "`reset()` method sets RF_BT_CBB_DIS to value 0"]
30868        impl crate::Resettable for RfBtCbbDisSpec {}
30869    }
30870    #[doc = "ABB_ADC_CTRL (rw) register accessor: ABB ADC control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_adc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_adc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abb_adc_ctrl`] module"]
30871    #[doc(alias = "ABB_ADC_CTRL")]
30872    pub type AbbAdcCtrl = crate::Reg<abb_adc_ctrl::AbbAdcCtrlSpec>;
30873    #[doc = "ABB ADC control"]
30874    pub mod abb_adc_ctrl {
30875        #[doc = "Register `ABB_ADC_CTRL` reader"]
30876        pub type R = crate::R<AbbAdcCtrlSpec>;
30877        #[doc = "Register `ABB_ADC_CTRL` writer"]
30878        pub type W = crate::W<AbbAdcCtrlSpec>;
30879        impl core::fmt::Debug for R {
30880            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30881                write!(f, "{}", self.bits())
30882            }
30883        }
30884        impl W {}
30885        #[doc = "ABB ADC control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_adc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_adc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30886        pub struct AbbAdcCtrlSpec;
30887        impl crate::RegisterSpec for AbbAdcCtrlSpec {
30888            type Ux = u32;
30889        }
30890        #[doc = "`read()` method returns [`abb_adc_ctrl::R`](R) reader structure"]
30891        impl crate::Readable for AbbAdcCtrlSpec {}
30892        #[doc = "`write(|w| ..)` method takes [`abb_adc_ctrl::W`](W) writer structure"]
30893        impl crate::Writable for AbbAdcCtrlSpec {
30894            type Safety = crate::Unsafe;
30895        }
30896        #[doc = "`reset()` method sets ABB_ADC_CTRL to value 0"]
30897        impl crate::Resettable for AbbAdcCtrlSpec {}
30898    }
30899    #[doc = "ABB_DAC_CTRL (rw) register accessor: ABB DAC control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_dac_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_dac_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abb_dac_ctrl`] module"]
30900    #[doc(alias = "ABB_DAC_CTRL")]
30901    pub type AbbDacCtrl = crate::Reg<abb_dac_ctrl::AbbDacCtrlSpec>;
30902    #[doc = "ABB DAC control"]
30903    pub mod abb_dac_ctrl {
30904        #[doc = "Register `ABB_DAC_CTRL` reader"]
30905        pub type R = crate::R<AbbDacCtrlSpec>;
30906        #[doc = "Register `ABB_DAC_CTRL` writer"]
30907        pub type W = crate::W<AbbDacCtrlSpec>;
30908        impl core::fmt::Debug for R {
30909            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30910                write!(f, "{}", self.bits())
30911            }
30912        }
30913        impl W {}
30914        #[doc = "ABB DAC control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_dac_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_dac_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30915        pub struct AbbDacCtrlSpec;
30916        impl crate::RegisterSpec for AbbDacCtrlSpec {
30917            type Ux = u32;
30918        }
30919        #[doc = "`read()` method returns [`abb_dac_ctrl::R`](R) reader structure"]
30920        impl crate::Readable for AbbDacCtrlSpec {}
30921        #[doc = "`write(|w| ..)` method takes [`abb_dac_ctrl::W`](W) writer structure"]
30922        impl crate::Writable for AbbDacCtrlSpec {
30923            type Safety = crate::Unsafe;
30924        }
30925        #[doc = "`reset()` method sets ABB_DAC_CTRL to value 0"]
30926        impl crate::Resettable for AbbDacCtrlSpec {}
30927    }
30928    #[doc = "ABB_EN_CTRL (rw) register accessor: ABB enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_en_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_en_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abb_en_ctrl`] module"]
30929    #[doc(alias = "ABB_EN_CTRL")]
30930    pub type AbbEnCtrl = crate::Reg<abb_en_ctrl::AbbEnCtrlSpec>;
30931    #[doc = "ABB enable control"]
30932    pub mod abb_en_ctrl {
30933        #[doc = "Register `ABB_EN_CTRL` reader"]
30934        pub type R = crate::R<AbbEnCtrlSpec>;
30935        #[doc = "Register `ABB_EN_CTRL` writer"]
30936        pub type W = crate::W<AbbEnCtrlSpec>;
30937        impl core::fmt::Debug for R {
30938            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30939                write!(f, "{}", self.bits())
30940            }
30941        }
30942        impl W {}
30943        #[doc = "ABB enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_en_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_en_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30944        pub struct AbbEnCtrlSpec;
30945        impl crate::RegisterSpec for AbbEnCtrlSpec {
30946            type Ux = u32;
30947        }
30948        #[doc = "`read()` method returns [`abb_en_ctrl::R`](R) reader structure"]
30949        impl crate::Readable for AbbEnCtrlSpec {}
30950        #[doc = "`write(|w| ..)` method takes [`abb_en_ctrl::W`](W) writer structure"]
30951        impl crate::Writable for AbbEnCtrlSpec {
30952            type Safety = crate::Unsafe;
30953        }
30954        #[doc = "`reset()` method sets ABB_EN_CTRL to value 0"]
30955        impl crate::Resettable for AbbEnCtrlSpec {}
30956    }
30957    #[doc = "CFG_WL_ADC_MUX (rw) register accessor: WL ADC mux configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wl_adc_mux::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wl_adc_mux::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_wl_adc_mux`] module"]
30958    #[doc(alias = "CFG_WL_ADC_MUX")]
30959    pub type CfgWlAdcMux = crate::Reg<cfg_wl_adc_mux::CfgWlAdcMuxSpec>;
30960    #[doc = "WL ADC mux configuration"]
30961    pub mod cfg_wl_adc_mux {
30962        #[doc = "Register `CFG_WL_ADC_MUX` reader"]
30963        pub type R = crate::R<CfgWlAdcMuxSpec>;
30964        #[doc = "Register `CFG_WL_ADC_MUX` writer"]
30965        pub type W = crate::W<CfgWlAdcMuxSpec>;
30966        impl core::fmt::Debug for R {
30967            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30968                write!(f, "{}", self.bits())
30969            }
30970        }
30971        impl W {}
30972        #[doc = "WL ADC mux configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wl_adc_mux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wl_adc_mux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30973        pub struct CfgWlAdcMuxSpec;
30974        impl crate::RegisterSpec for CfgWlAdcMuxSpec {
30975            type Ux = u32;
30976        }
30977        #[doc = "`read()` method returns [`cfg_wl_adc_mux::R`](R) reader structure"]
30978        impl crate::Readable for CfgWlAdcMuxSpec {}
30979        #[doc = "`write(|w| ..)` method takes [`cfg_wl_adc_mux::W`](W) writer structure"]
30980        impl crate::Writable for CfgWlAdcMuxSpec {
30981            type Safety = crate::Unsafe;
30982        }
30983        #[doc = "`reset()` method sets CFG_WL_ADC_MUX to value 0"]
30984        impl crate::Resettable for CfgWlAdcMuxSpec {}
30985    }
30986    #[doc = "CFG_RF_MAN_EN_CTRL (rw) register accessor: RF manual enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rf_man_en_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rf_man_en_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rf_man_en_ctrl`] module"]
30987    #[doc(alias = "CFG_RF_MAN_EN_CTRL")]
30988    pub type CfgRfManEnCtrl = crate::Reg<cfg_rf_man_en_ctrl::CfgRfManEnCtrlSpec>;
30989    #[doc = "RF manual enable control"]
30990    pub mod cfg_rf_man_en_ctrl {
30991        #[doc = "Register `CFG_RF_MAN_EN_CTRL` reader"]
30992        pub type R = crate::R<CfgRfManEnCtrlSpec>;
30993        #[doc = "Register `CFG_RF_MAN_EN_CTRL` writer"]
30994        pub type W = crate::W<CfgRfManEnCtrlSpec>;
30995        impl core::fmt::Debug for R {
30996            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30997                write!(f, "{}", self.bits())
30998            }
30999        }
31000        impl W {}
31001        #[doc = "RF manual enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rf_man_en_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rf_man_en_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31002        pub struct CfgRfManEnCtrlSpec;
31003        impl crate::RegisterSpec for CfgRfManEnCtrlSpec {
31004            type Ux = u32;
31005        }
31006        #[doc = "`read()` method returns [`cfg_rf_man_en_ctrl::R`](R) reader structure"]
31007        impl crate::Readable for CfgRfManEnCtrlSpec {}
31008        #[doc = "`write(|w| ..)` method takes [`cfg_rf_man_en_ctrl::W`](W) writer structure"]
31009        impl crate::Writable for CfgRfManEnCtrlSpec {
31010            type Safety = crate::Unsafe;
31011        }
31012        #[doc = "`reset()` method sets CFG_RF_MAN_EN_CTRL to value 0"]
31013        impl crate::Resettable for CfgRfManEnCtrlSpec {}
31014    }
31015    #[doc = "CFG_TRXEN_CTRL (rw) register accessor: TRX enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_trxen_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_trxen_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_trxen_ctrl`] module"]
31016    #[doc(alias = "CFG_TRXEN_CTRL")]
31017    pub type CfgTrxenCtrl = crate::Reg<cfg_trxen_ctrl::CfgTrxenCtrlSpec>;
31018    #[doc = "TRX enable control"]
31019    pub mod cfg_trxen_ctrl {
31020        #[doc = "Register `CFG_TRXEN_CTRL` reader"]
31021        pub type R = crate::R<CfgTrxenCtrlSpec>;
31022        #[doc = "Register `CFG_TRXEN_CTRL` writer"]
31023        pub type W = crate::W<CfgTrxenCtrlSpec>;
31024        impl core::fmt::Debug for R {
31025            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31026                write!(f, "{}", self.bits())
31027            }
31028        }
31029        impl W {}
31030        #[doc = "TRX enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_trxen_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_trxen_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31031        pub struct CfgTrxenCtrlSpec;
31032        impl crate::RegisterSpec for CfgTrxenCtrlSpec {
31033            type Ux = u32;
31034        }
31035        #[doc = "`read()` method returns [`cfg_trxen_ctrl::R`](R) reader structure"]
31036        impl crate::Readable for CfgTrxenCtrlSpec {}
31037        #[doc = "`write(|w| ..)` method takes [`cfg_trxen_ctrl::W`](W) writer structure"]
31038        impl crate::Writable for CfgTrxenCtrlSpec {
31039            type Safety = crate::Unsafe;
31040        }
31041        #[doc = "`reset()` method sets CFG_TRXEN_CTRL to value 0"]
31042        impl crate::Resettable for CfgTrxenCtrlSpec {}
31043    }
31044    #[doc = "CFG_DCOC_IQ_CTRL (rw) register accessor: DCOC IQ control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_iq_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_iq_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_iq_ctrl`] module"]
31045    #[doc(alias = "CFG_DCOC_IQ_CTRL")]
31046    pub type CfgDcocIqCtrl = crate::Reg<cfg_dcoc_iq_ctrl::CfgDcocIqCtrlSpec>;
31047    #[doc = "DCOC IQ control"]
31048    pub mod cfg_dcoc_iq_ctrl {
31049        #[doc = "Register `CFG_DCOC_IQ_CTRL` reader"]
31050        pub type R = crate::R<CfgDcocIqCtrlSpec>;
31051        #[doc = "Register `CFG_DCOC_IQ_CTRL` writer"]
31052        pub type W = crate::W<CfgDcocIqCtrlSpec>;
31053        impl core::fmt::Debug for R {
31054            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31055                write!(f, "{}", self.bits())
31056            }
31057        }
31058        impl W {}
31059        #[doc = "DCOC IQ control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_iq_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_iq_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31060        pub struct CfgDcocIqCtrlSpec;
31061        impl crate::RegisterSpec for CfgDcocIqCtrlSpec {
31062            type Ux = u32;
31063        }
31064        #[doc = "`read()` method returns [`cfg_dcoc_iq_ctrl::R`](R) reader structure"]
31065        impl crate::Readable for CfgDcocIqCtrlSpec {}
31066        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_iq_ctrl::W`](W) writer structure"]
31067        impl crate::Writable for CfgDcocIqCtrlSpec {
31068            type Safety = crate::Unsafe;
31069        }
31070        #[doc = "`reset()` method sets CFG_DCOC_IQ_CTRL to value 0"]
31071        impl crate::Resettable for CfgDcocIqCtrlSpec {}
31072    }
31073    #[doc = "CFG_PA_IDX_CTRL (rw) register accessor: PA index control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_pa_idx_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_pa_idx_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_pa_idx_ctrl`] module"]
31074    #[doc(alias = "CFG_PA_IDX_CTRL")]
31075    pub type CfgPaIdxCtrl = crate::Reg<cfg_pa_idx_ctrl::CfgPaIdxCtrlSpec>;
31076    #[doc = "PA index control"]
31077    pub mod cfg_pa_idx_ctrl {
31078        #[doc = "Register `CFG_PA_IDX_CTRL` reader"]
31079        pub type R = crate::R<CfgPaIdxCtrlSpec>;
31080        #[doc = "Register `CFG_PA_IDX_CTRL` writer"]
31081        pub type W = crate::W<CfgPaIdxCtrlSpec>;
31082        impl core::fmt::Debug for R {
31083            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31084                write!(f, "{}", self.bits())
31085            }
31086        }
31087        impl W {}
31088        #[doc = "PA index control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_pa_idx_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_pa_idx_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31089        pub struct CfgPaIdxCtrlSpec;
31090        impl crate::RegisterSpec for CfgPaIdxCtrlSpec {
31091            type Ux = u32;
31092        }
31093        #[doc = "`read()` method returns [`cfg_pa_idx_ctrl::R`](R) reader structure"]
31094        impl crate::Readable for CfgPaIdxCtrlSpec {}
31095        #[doc = "`write(|w| ..)` method takes [`cfg_pa_idx_ctrl::W`](W) writer structure"]
31096        impl crate::Writable for CfgPaIdxCtrlSpec {
31097            type Safety = crate::Unsafe;
31098        }
31099        #[doc = "`reset()` method sets CFG_PA_IDX_CTRL to value 0"]
31100        impl crate::Resettable for CfgPaIdxCtrlSpec {}
31101    }
31102    #[doc = "CFG_LPF_CTRL (rw) register accessor: LPF control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_lpf_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_lpf_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_lpf_ctrl`] module"]
31103    #[doc(alias = "CFG_LPF_CTRL")]
31104    pub type CfgLpfCtrl = crate::Reg<cfg_lpf_ctrl::CfgLpfCtrlSpec>;
31105    #[doc = "LPF control"]
31106    pub mod cfg_lpf_ctrl {
31107        #[doc = "Register `CFG_LPF_CTRL` reader"]
31108        pub type R = crate::R<CfgLpfCtrlSpec>;
31109        #[doc = "Register `CFG_LPF_CTRL` writer"]
31110        pub type W = crate::W<CfgLpfCtrlSpec>;
31111        impl core::fmt::Debug for R {
31112            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31113                write!(f, "{}", self.bits())
31114            }
31115        }
31116        impl W {}
31117        #[doc = "LPF control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_lpf_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_lpf_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31118        pub struct CfgLpfCtrlSpec;
31119        impl crate::RegisterSpec for CfgLpfCtrlSpec {
31120            type Ux = u32;
31121        }
31122        #[doc = "`read()` method returns [`cfg_lpf_ctrl::R`](R) reader structure"]
31123        impl crate::Readable for CfgLpfCtrlSpec {}
31124        #[doc = "`write(|w| ..)` method takes [`cfg_lpf_ctrl::W`](W) writer structure"]
31125        impl crate::Writable for CfgLpfCtrlSpec {
31126            type Safety = crate::Unsafe;
31127        }
31128        #[doc = "`reset()` method sets CFG_LPF_CTRL to value 0"]
31129        impl crate::Resettable for CfgLpfCtrlSpec {}
31130    }
31131    #[doc = "CFG_RADAR_CTRL (rw) register accessor: Radar control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_radar_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_radar_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_radar_ctrl`] module"]
31132    #[doc(alias = "CFG_RADAR_CTRL")]
31133    pub type CfgRadarCtrl = crate::Reg<cfg_radar_ctrl::CfgRadarCtrlSpec>;
31134    #[doc = "Radar control"]
31135    pub mod cfg_radar_ctrl {
31136        #[doc = "Register `CFG_RADAR_CTRL` reader"]
31137        pub type R = crate::R<CfgRadarCtrlSpec>;
31138        #[doc = "Register `CFG_RADAR_CTRL` writer"]
31139        pub type W = crate::W<CfgRadarCtrlSpec>;
31140        impl core::fmt::Debug for R {
31141            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31142                write!(f, "{}", self.bits())
31143            }
31144        }
31145        impl W {}
31146        #[doc = "Radar control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_radar_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_radar_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31147        pub struct CfgRadarCtrlSpec;
31148        impl crate::RegisterSpec for CfgRadarCtrlSpec {
31149            type Ux = u32;
31150        }
31151        #[doc = "`read()` method returns [`cfg_radar_ctrl::R`](R) reader structure"]
31152        impl crate::Readable for CfgRadarCtrlSpec {}
31153        #[doc = "`write(|w| ..)` method takes [`cfg_radar_ctrl::W`](W) writer structure"]
31154        impl crate::Writable for CfgRadarCtrlSpec {
31155            type Safety = crate::Unsafe;
31156        }
31157        #[doc = "`reset()` method sets CFG_RADAR_CTRL to value 0"]
31158        impl crate::Resettable for CfgRadarCtrlSpec {}
31159    }
31160    #[doc = "CFG_PPA_CODE (rw) register accessor: PPA code register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ppa_code::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ppa_code::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_ppa_code`] module"]
31161    #[doc(alias = "CFG_PPA_CODE")]
31162    pub type CfgPpaCode = crate::Reg<cfg_ppa_code::CfgPpaCodeSpec>;
31163    #[doc = "PPA code register"]
31164    pub mod cfg_ppa_code {
31165        #[doc = "Register `CFG_PPA_CODE` reader"]
31166        pub type R = crate::R<CfgPpaCodeSpec>;
31167        #[doc = "Register `CFG_PPA_CODE` writer"]
31168        pub type W = crate::W<CfgPpaCodeSpec>;
31169        impl core::fmt::Debug for R {
31170            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31171                write!(f, "{}", self.bits())
31172            }
31173        }
31174        impl W {}
31175        #[doc = "PPA code register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ppa_code::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ppa_code::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31176        pub struct CfgPpaCodeSpec;
31177        impl crate::RegisterSpec for CfgPpaCodeSpec {
31178            type Ux = u32;
31179        }
31180        #[doc = "`read()` method returns [`cfg_ppa_code::R`](R) reader structure"]
31181        impl crate::Readable for CfgPpaCodeSpec {}
31182        #[doc = "`write(|w| ..)` method takes [`cfg_ppa_code::W`](W) writer structure"]
31183        impl crate::Writable for CfgPpaCodeSpec {
31184            type Safety = crate::Unsafe;
31185        }
31186        #[doc = "`reset()` method sets CFG_PPA_CODE to value 0"]
31187        impl crate::Resettable for CfgPpaCodeSpec {}
31188    }
31189    #[doc = "CFG_TEMP_LOCK_CTRL (rw) register accessor: Temperature lock control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_temp_lock_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_temp_lock_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_temp_lock_ctrl`] module"]
31190    #[doc(alias = "CFG_TEMP_LOCK_CTRL")]
31191    pub type CfgTempLockCtrl = crate::Reg<cfg_temp_lock_ctrl::CfgTempLockCtrlSpec>;
31192    #[doc = "Temperature lock control"]
31193    pub mod cfg_temp_lock_ctrl {
31194        #[doc = "Register `CFG_TEMP_LOCK_CTRL` reader"]
31195        pub type R = crate::R<CfgTempLockCtrlSpec>;
31196        #[doc = "Register `CFG_TEMP_LOCK_CTRL` writer"]
31197        pub type W = crate::W<CfgTempLockCtrlSpec>;
31198        impl core::fmt::Debug for R {
31199            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31200                write!(f, "{}", self.bits())
31201            }
31202        }
31203        impl W {}
31204        #[doc = "Temperature lock control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_temp_lock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_temp_lock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31205        pub struct CfgTempLockCtrlSpec;
31206        impl crate::RegisterSpec for CfgTempLockCtrlSpec {
31207            type Ux = u32;
31208        }
31209        #[doc = "`read()` method returns [`cfg_temp_lock_ctrl::R`](R) reader structure"]
31210        impl crate::Readable for CfgTempLockCtrlSpec {}
31211        #[doc = "`write(|w| ..)` method takes [`cfg_temp_lock_ctrl::W`](W) writer structure"]
31212        impl crate::Writable for CfgTempLockCtrlSpec {
31213            type Safety = crate::Unsafe;
31214        }
31215        #[doc = "`reset()` method sets CFG_TEMP_LOCK_CTRL to value 0"]
31216        impl crate::Resettable for CfgTempLockCtrlSpec {}
31217    }
31218    #[doc = "CFG_TEMP_BANK_SEL_CTRL (rw) register accessor: Temperature bank select control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_temp_bank_sel_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_temp_bank_sel_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_temp_bank_sel_ctrl`] module"]
31219    #[doc(alias = "CFG_TEMP_BANK_SEL_CTRL")]
31220    pub type CfgTempBankSelCtrl = crate::Reg<cfg_temp_bank_sel_ctrl::CfgTempBankSelCtrlSpec>;
31221    #[doc = "Temperature bank select control"]
31222    pub mod cfg_temp_bank_sel_ctrl {
31223        #[doc = "Register `CFG_TEMP_BANK_SEL_CTRL` reader"]
31224        pub type R = crate::R<CfgTempBankSelCtrlSpec>;
31225        #[doc = "Register `CFG_TEMP_BANK_SEL_CTRL` writer"]
31226        pub type W = crate::W<CfgTempBankSelCtrlSpec>;
31227        impl core::fmt::Debug for R {
31228            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31229                write!(f, "{}", self.bits())
31230            }
31231        }
31232        impl W {}
31233        #[doc = "Temperature bank select control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_temp_bank_sel_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_temp_bank_sel_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31234        pub struct CfgTempBankSelCtrlSpec;
31235        impl crate::RegisterSpec for CfgTempBankSelCtrlSpec {
31236            type Ux = u32;
31237        }
31238        #[doc = "`read()` method returns [`cfg_temp_bank_sel_ctrl::R`](R) reader structure"]
31239        impl crate::Readable for CfgTempBankSelCtrlSpec {}
31240        #[doc = "`write(|w| ..)` method takes [`cfg_temp_bank_sel_ctrl::W`](W) writer structure"]
31241        impl crate::Writable for CfgTempBankSelCtrlSpec {
31242            type Safety = crate::Unsafe;
31243        }
31244        #[doc = "`reset()` method sets CFG_TEMP_BANK_SEL_CTRL to value 0"]
31245        impl crate::Resettable for CfgTempBankSelCtrlSpec {}
31246    }
31247    #[doc = "CFG_RF_DIAG_MUX (rw) register accessor: RF diagnostic mux\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rf_diag_mux::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rf_diag_mux::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rf_diag_mux`] module"]
31248    #[doc(alias = "CFG_RF_DIAG_MUX")]
31249    pub type CfgRfDiagMux = crate::Reg<cfg_rf_diag_mux::CfgRfDiagMuxSpec>;
31250    #[doc = "RF diagnostic mux"]
31251    pub mod cfg_rf_diag_mux {
31252        #[doc = "Register `CFG_RF_DIAG_MUX` reader"]
31253        pub type R = crate::R<CfgRfDiagMuxSpec>;
31254        #[doc = "Register `CFG_RF_DIAG_MUX` writer"]
31255        pub type W = crate::W<CfgRfDiagMuxSpec>;
31256        impl core::fmt::Debug for R {
31257            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31258                write!(f, "{}", self.bits())
31259            }
31260        }
31261        impl W {}
31262        #[doc = "RF diagnostic mux\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rf_diag_mux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rf_diag_mux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31263        pub struct CfgRfDiagMuxSpec;
31264        impl crate::RegisterSpec for CfgRfDiagMuxSpec {
31265            type Ux = u32;
31266        }
31267        #[doc = "`read()` method returns [`cfg_rf_diag_mux::R`](R) reader structure"]
31268        impl crate::Readable for CfgRfDiagMuxSpec {}
31269        #[doc = "`write(|w| ..)` method takes [`cfg_rf_diag_mux::W`](W) writer structure"]
31270        impl crate::Writable for CfgRfDiagMuxSpec {
31271            type Safety = crate::Unsafe;
31272        }
31273        #[doc = "`reset()` method sets CFG_RF_DIAG_MUX to value 0"]
31274        impl crate::Resettable for CfgRfDiagMuxSpec {}
31275    }
31276}
31277#[doc = "SYS_CTL2 sub-block: Shared Memory Control - RAM config, RX/TX DMA descriptor rings for WiFi PHY↔Packet buffer"]
31278pub type ShareMemCtl = crate::Periph<share_mem_ctl::RegisterBlock, 0x4400_6c00>;
31279impl core::fmt::Debug for ShareMemCtl {
31280    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31281        f.debug_struct("ShareMemCtl").finish()
31282    }
31283}
31284#[doc = "SYS_CTL2 sub-block: Shared Memory Control - RAM config, RX/TX DMA descriptor rings for WiFi PHY↔Packet buffer"]
31285pub mod share_mem_ctl {
31286    #[repr(C)]
31287    #[doc = "Register block"]
31288    pub struct RegisterBlock {
31289        _reserved0: [u8; 0x04],
31290        cfg_ram_cken: CfgRamCken,
31291        cfg_ram_sel: CfgRamSel,
31292        ram_sw_conflict_clr: RamSwConflictClr,
31293        ram_sw_conflict_st: RamSwConflictSt,
31294        ramx_sw_conflict_base_addr: RamxSwConflictBaseAddr,
31295        _reserved5: [u8; 0x38],
31296        cfg_freq_busdmac: CfgFreqBusdmac,
31297        _reserved6: [u8; 0x04],
31298        cfg_rx_en: CfgRxEn,
31299        cfg_rx_start_addr: CfgRxStartAddr,
31300        cfg_rx_end_addr: CfgRxEndAddr,
31301        cfg_rx_done_sts: CfgRxDoneSts,
31302        cfg_rx_done_addr: CfgRxDoneAddr,
31303        cfg_wlphy2pkt_rx_ram_sts: CfgWlphy2pktRxRamSts,
31304        cfg_tx_en: CfgTxEn,
31305        cfg_tx_start_addr: CfgTxStartAddr,
31306        cfg_tx_end_addr: CfgTxEndAddr,
31307        cfg_tx_done_sts: CfgTxDoneSts,
31308        cfg_tx_done_addr: CfgTxDoneAddr,
31309        cfg_wlphy2pkt_tx_ram_sts: CfgWlphy2pktTxRamSts,
31310    }
31311    impl RegisterBlock {
31312        #[doc = "0x04 - RAM clock enable"]
31313        #[inline(always)]
31314        pub const fn cfg_ram_cken(&self) -> &CfgRamCken {
31315            &self.cfg_ram_cken
31316        }
31317        #[doc = "0x08 - Share RAM control and RAM select"]
31318        #[inline(always)]
31319        pub const fn cfg_ram_sel(&self) -> &CfgRamSel {
31320            &self.cfg_ram_sel
31321        }
31322        #[doc = "0x0c - RAM software conflict clear"]
31323        #[inline(always)]
31324        pub const fn ram_sw_conflict_clr(&self) -> &RamSwConflictClr {
31325            &self.ram_sw_conflict_clr
31326        }
31327        #[doc = "0x10 - RAM software conflict status"]
31328        #[inline(always)]
31329        pub const fn ram_sw_conflict_st(&self) -> &RamSwConflictSt {
31330            &self.ram_sw_conflict_st
31331        }
31332        #[doc = "0x14 - RAMX software conflict base address"]
31333        #[inline(always)]
31334        pub const fn ramx_sw_conflict_base_addr(&self) -> &RamxSwConflictBaseAddr {
31335            &self.ramx_sw_conflict_base_addr
31336        }
31337        #[doc = "0x50 - Bus DMAC frequency configuration"]
31338        #[inline(always)]
31339        pub const fn cfg_freq_busdmac(&self) -> &CfgFreqBusdmac {
31340            &self.cfg_freq_busdmac
31341        }
31342        #[doc = "0x58 - RX enable"]
31343        #[inline(always)]
31344        pub const fn cfg_rx_en(&self) -> &CfgRxEn {
31345            &self.cfg_rx_en
31346        }
31347        #[doc = "0x5c - RX start address"]
31348        #[inline(always)]
31349        pub const fn cfg_rx_start_addr(&self) -> &CfgRxStartAddr {
31350            &self.cfg_rx_start_addr
31351        }
31352        #[doc = "0x60 - RX end address"]
31353        #[inline(always)]
31354        pub const fn cfg_rx_end_addr(&self) -> &CfgRxEndAddr {
31355            &self.cfg_rx_end_addr
31356        }
31357        #[doc = "0x64 - RX done status"]
31358        #[inline(always)]
31359        pub const fn cfg_rx_done_sts(&self) -> &CfgRxDoneSts {
31360            &self.cfg_rx_done_sts
31361        }
31362        #[doc = "0x68 - RX done address"]
31363        #[inline(always)]
31364        pub const fn cfg_rx_done_addr(&self) -> &CfgRxDoneAddr {
31365            &self.cfg_rx_done_addr
31366        }
31367        #[doc = "0x6c - WL PHY-to-packet RX RAM status"]
31368        #[inline(always)]
31369        pub const fn cfg_wlphy2pkt_rx_ram_sts(&self) -> &CfgWlphy2pktRxRamSts {
31370            &self.cfg_wlphy2pkt_rx_ram_sts
31371        }
31372        #[doc = "0x70 - TX enable"]
31373        #[inline(always)]
31374        pub const fn cfg_tx_en(&self) -> &CfgTxEn {
31375            &self.cfg_tx_en
31376        }
31377        #[doc = "0x74 - TX start address"]
31378        #[inline(always)]
31379        pub const fn cfg_tx_start_addr(&self) -> &CfgTxStartAddr {
31380            &self.cfg_tx_start_addr
31381        }
31382        #[doc = "0x78 - TX end address"]
31383        #[inline(always)]
31384        pub const fn cfg_tx_end_addr(&self) -> &CfgTxEndAddr {
31385            &self.cfg_tx_end_addr
31386        }
31387        #[doc = "0x7c - TX done status"]
31388        #[inline(always)]
31389        pub const fn cfg_tx_done_sts(&self) -> &CfgTxDoneSts {
31390            &self.cfg_tx_done_sts
31391        }
31392        #[doc = "0x80 - TX done address"]
31393        #[inline(always)]
31394        pub const fn cfg_tx_done_addr(&self) -> &CfgTxDoneAddr {
31395            &self.cfg_tx_done_addr
31396        }
31397        #[doc = "0x84 - WL PHY-to-packet TX RAM status"]
31398        #[inline(always)]
31399        pub const fn cfg_wlphy2pkt_tx_ram_sts(&self) -> &CfgWlphy2pktTxRamSts {
31400            &self.cfg_wlphy2pkt_tx_ram_sts
31401        }
31402    }
31403    #[doc = "CFG_RAM_CKEN (rw) register accessor: RAM clock enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ram_cken::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ram_cken::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_ram_cken`] module"]
31404    #[doc(alias = "CFG_RAM_CKEN")]
31405    pub type CfgRamCken = crate::Reg<cfg_ram_cken::CfgRamCkenSpec>;
31406    #[doc = "RAM clock enable"]
31407    pub mod cfg_ram_cken {
31408        #[doc = "Register `CFG_RAM_CKEN` reader"]
31409        pub type R = crate::R<CfgRamCkenSpec>;
31410        #[doc = "Register `CFG_RAM_CKEN` writer"]
31411        pub type W = crate::W<CfgRamCkenSpec>;
31412        impl core::fmt::Debug for R {
31413            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31414                write!(f, "{}", self.bits())
31415            }
31416        }
31417        impl W {}
31418        #[doc = "RAM clock enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ram_cken::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ram_cken::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31419        pub struct CfgRamCkenSpec;
31420        impl crate::RegisterSpec for CfgRamCkenSpec {
31421            type Ux = u32;
31422        }
31423        #[doc = "`read()` method returns [`cfg_ram_cken::R`](R) reader structure"]
31424        impl crate::Readable for CfgRamCkenSpec {}
31425        #[doc = "`write(|w| ..)` method takes [`cfg_ram_cken::W`](W) writer structure"]
31426        impl crate::Writable for CfgRamCkenSpec {
31427            type Safety = crate::Unsafe;
31428        }
31429        #[doc = "`reset()` method sets CFG_RAM_CKEN to value 0"]
31430        impl crate::Resettable for CfgRamCkenSpec {}
31431    }
31432    #[doc = "CFG_RAM_SEL (rw) register accessor: Share RAM control and RAM select\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ram_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ram_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_ram_sel`] module"]
31433    #[doc(alias = "CFG_RAM_SEL")]
31434    pub type CfgRamSel = crate::Reg<cfg_ram_sel::CfgRamSelSpec>;
31435    #[doc = "Share RAM control and RAM select"]
31436    pub mod cfg_ram_sel {
31437        #[doc = "Register `CFG_RAM_SEL` reader"]
31438        pub type R = crate::R<CfgRamSelSpec>;
31439        #[doc = "Register `CFG_RAM_SEL` writer"]
31440        pub type W = crate::W<CfgRamSelSpec>;
31441        impl core::fmt::Debug for R {
31442            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31443                write!(f, "{}", self.bits())
31444            }
31445        }
31446        impl W {}
31447        #[doc = "Share RAM control and RAM select\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ram_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ram_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31448        pub struct CfgRamSelSpec;
31449        impl crate::RegisterSpec for CfgRamSelSpec {
31450            type Ux = u32;
31451        }
31452        #[doc = "`read()` method returns [`cfg_ram_sel::R`](R) reader structure"]
31453        impl crate::Readable for CfgRamSelSpec {}
31454        #[doc = "`write(|w| ..)` method takes [`cfg_ram_sel::W`](W) writer structure"]
31455        impl crate::Writable for CfgRamSelSpec {
31456            type Safety = crate::Unsafe;
31457        }
31458        #[doc = "`reset()` method sets CFG_RAM_SEL to value 0"]
31459        impl crate::Resettable for CfgRamSelSpec {}
31460    }
31461    #[doc = "RAM_SW_CONFLICT_CLR (rw) register accessor: RAM software conflict clear\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sw_conflict_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sw_conflict_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sw_conflict_clr`] module"]
31462    #[doc(alias = "RAM_SW_CONFLICT_CLR")]
31463    pub type RamSwConflictClr = crate::Reg<ram_sw_conflict_clr::RamSwConflictClrSpec>;
31464    #[doc = "RAM software conflict clear"]
31465    pub mod ram_sw_conflict_clr {
31466        #[doc = "Register `RAM_SW_CONFLICT_CLR` reader"]
31467        pub type R = crate::R<RamSwConflictClrSpec>;
31468        #[doc = "Register `RAM_SW_CONFLICT_CLR` writer"]
31469        pub type W = crate::W<RamSwConflictClrSpec>;
31470        impl core::fmt::Debug for R {
31471            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31472                write!(f, "{}", self.bits())
31473            }
31474        }
31475        impl W {}
31476        #[doc = "RAM software conflict clear\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sw_conflict_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sw_conflict_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31477        pub struct RamSwConflictClrSpec;
31478        impl crate::RegisterSpec for RamSwConflictClrSpec {
31479            type Ux = u32;
31480        }
31481        #[doc = "`read()` method returns [`ram_sw_conflict_clr::R`](R) reader structure"]
31482        impl crate::Readable for RamSwConflictClrSpec {}
31483        #[doc = "`write(|w| ..)` method takes [`ram_sw_conflict_clr::W`](W) writer structure"]
31484        impl crate::Writable for RamSwConflictClrSpec {
31485            type Safety = crate::Unsafe;
31486        }
31487        #[doc = "`reset()` method sets RAM_SW_CONFLICT_CLR to value 0"]
31488        impl crate::Resettable for RamSwConflictClrSpec {}
31489    }
31490    #[doc = "RAM_SW_CONFLICT_ST (rw) register accessor: RAM software conflict status\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sw_conflict_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sw_conflict_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sw_conflict_st`] module"]
31491    #[doc(alias = "RAM_SW_CONFLICT_ST")]
31492    pub type RamSwConflictSt = crate::Reg<ram_sw_conflict_st::RamSwConflictStSpec>;
31493    #[doc = "RAM software conflict status"]
31494    pub mod ram_sw_conflict_st {
31495        #[doc = "Register `RAM_SW_CONFLICT_ST` reader"]
31496        pub type R = crate::R<RamSwConflictStSpec>;
31497        #[doc = "Register `RAM_SW_CONFLICT_ST` writer"]
31498        pub type W = crate::W<RamSwConflictStSpec>;
31499        impl core::fmt::Debug for R {
31500            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31501                write!(f, "{}", self.bits())
31502            }
31503        }
31504        impl W {}
31505        #[doc = "RAM software conflict status\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sw_conflict_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sw_conflict_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31506        pub struct RamSwConflictStSpec;
31507        impl crate::RegisterSpec for RamSwConflictStSpec {
31508            type Ux = u32;
31509        }
31510        #[doc = "`read()` method returns [`ram_sw_conflict_st::R`](R) reader structure"]
31511        impl crate::Readable for RamSwConflictStSpec {}
31512        #[doc = "`write(|w| ..)` method takes [`ram_sw_conflict_st::W`](W) writer structure"]
31513        impl crate::Writable for RamSwConflictStSpec {
31514            type Safety = crate::Unsafe;
31515        }
31516        #[doc = "`reset()` method sets RAM_SW_CONFLICT_ST to value 0"]
31517        impl crate::Resettable for RamSwConflictStSpec {}
31518    }
31519    #[doc = "RAMX_SW_CONFLICT_BASE_ADDR (rw) register accessor: RAMX software conflict base address\n\nYou can [`read`](crate::Reg::read) this register and get [`ramx_sw_conflict_base_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ramx_sw_conflict_base_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ramx_sw_conflict_base_addr`] module"]
31520    #[doc(alias = "RAMX_SW_CONFLICT_BASE_ADDR")]
31521    pub type RamxSwConflictBaseAddr =
31522        crate::Reg<ramx_sw_conflict_base_addr::RamxSwConflictBaseAddrSpec>;
31523    #[doc = "RAMX software conflict base address"]
31524    pub mod ramx_sw_conflict_base_addr {
31525        #[doc = "Register `RAMX_SW_CONFLICT_BASE_ADDR` reader"]
31526        pub type R = crate::R<RamxSwConflictBaseAddrSpec>;
31527        #[doc = "Register `RAMX_SW_CONFLICT_BASE_ADDR` writer"]
31528        pub type W = crate::W<RamxSwConflictBaseAddrSpec>;
31529        impl core::fmt::Debug for R {
31530            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31531                write!(f, "{}", self.bits())
31532            }
31533        }
31534        impl W {}
31535        #[doc = "RAMX software conflict base address\n\nYou can [`read`](crate::Reg::read) this register and get [`ramx_sw_conflict_base_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ramx_sw_conflict_base_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31536        pub struct RamxSwConflictBaseAddrSpec;
31537        impl crate::RegisterSpec for RamxSwConflictBaseAddrSpec {
31538            type Ux = u32;
31539        }
31540        #[doc = "`read()` method returns [`ramx_sw_conflict_base_addr::R`](R) reader structure"]
31541        impl crate::Readable for RamxSwConflictBaseAddrSpec {}
31542        #[doc = "`write(|w| ..)` method takes [`ramx_sw_conflict_base_addr::W`](W) writer structure"]
31543        impl crate::Writable for RamxSwConflictBaseAddrSpec {
31544            type Safety = crate::Unsafe;
31545        }
31546        #[doc = "`reset()` method sets RAMX_SW_CONFLICT_BASE_ADDR to value 0"]
31547        impl crate::Resettable for RamxSwConflictBaseAddrSpec {}
31548    }
31549    #[doc = "CFG_FREQ_BUSDMAC (rw) register accessor: Bus DMAC frequency configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_freq_busdmac::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_freq_busdmac::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_freq_busdmac`] module"]
31550    #[doc(alias = "CFG_FREQ_BUSDMAC")]
31551    pub type CfgFreqBusdmac = crate::Reg<cfg_freq_busdmac::CfgFreqBusdmacSpec>;
31552    #[doc = "Bus DMAC frequency configuration"]
31553    pub mod cfg_freq_busdmac {
31554        #[doc = "Register `CFG_FREQ_BUSDMAC` reader"]
31555        pub type R = crate::R<CfgFreqBusdmacSpec>;
31556        #[doc = "Register `CFG_FREQ_BUSDMAC` writer"]
31557        pub type W = crate::W<CfgFreqBusdmacSpec>;
31558        impl core::fmt::Debug for R {
31559            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31560                write!(f, "{}", self.bits())
31561            }
31562        }
31563        impl W {}
31564        #[doc = "Bus DMAC frequency configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_freq_busdmac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_freq_busdmac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31565        pub struct CfgFreqBusdmacSpec;
31566        impl crate::RegisterSpec for CfgFreqBusdmacSpec {
31567            type Ux = u32;
31568        }
31569        #[doc = "`read()` method returns [`cfg_freq_busdmac::R`](R) reader structure"]
31570        impl crate::Readable for CfgFreqBusdmacSpec {}
31571        #[doc = "`write(|w| ..)` method takes [`cfg_freq_busdmac::W`](W) writer structure"]
31572        impl crate::Writable for CfgFreqBusdmacSpec {
31573            type Safety = crate::Unsafe;
31574        }
31575        #[doc = "`reset()` method sets CFG_FREQ_BUSDMAC to value 0"]
31576        impl crate::Resettable for CfgFreqBusdmacSpec {}
31577    }
31578    #[doc = "CFG_RX_EN (rw) register accessor: RX enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rx_en`] module"]
31579    #[doc(alias = "CFG_RX_EN")]
31580    pub type CfgRxEn = crate::Reg<cfg_rx_en::CfgRxEnSpec>;
31581    #[doc = "RX enable"]
31582    pub mod cfg_rx_en {
31583        #[doc = "Register `CFG_RX_EN` reader"]
31584        pub type R = crate::R<CfgRxEnSpec>;
31585        #[doc = "Register `CFG_RX_EN` writer"]
31586        pub type W = crate::W<CfgRxEnSpec>;
31587        impl core::fmt::Debug for R {
31588            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31589                write!(f, "{}", self.bits())
31590            }
31591        }
31592        impl W {}
31593        #[doc = "RX enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31594        pub struct CfgRxEnSpec;
31595        impl crate::RegisterSpec for CfgRxEnSpec {
31596            type Ux = u32;
31597        }
31598        #[doc = "`read()` method returns [`cfg_rx_en::R`](R) reader structure"]
31599        impl crate::Readable for CfgRxEnSpec {}
31600        #[doc = "`write(|w| ..)` method takes [`cfg_rx_en::W`](W) writer structure"]
31601        impl crate::Writable for CfgRxEnSpec {
31602            type Safety = crate::Unsafe;
31603        }
31604        #[doc = "`reset()` method sets CFG_RX_EN to value 0"]
31605        impl crate::Resettable for CfgRxEnSpec {}
31606    }
31607    #[doc = "CFG_RX_START_ADDR (rw) register accessor: RX start address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_start_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_start_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rx_start_addr`] module"]
31608    #[doc(alias = "CFG_RX_START_ADDR")]
31609    pub type CfgRxStartAddr = crate::Reg<cfg_rx_start_addr::CfgRxStartAddrSpec>;
31610    #[doc = "RX start address"]
31611    pub mod cfg_rx_start_addr {
31612        #[doc = "Register `CFG_RX_START_ADDR` reader"]
31613        pub type R = crate::R<CfgRxStartAddrSpec>;
31614        #[doc = "Register `CFG_RX_START_ADDR` writer"]
31615        pub type W = crate::W<CfgRxStartAddrSpec>;
31616        impl core::fmt::Debug for R {
31617            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31618                write!(f, "{}", self.bits())
31619            }
31620        }
31621        impl W {}
31622        #[doc = "RX start address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_start_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_start_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31623        pub struct CfgRxStartAddrSpec;
31624        impl crate::RegisterSpec for CfgRxStartAddrSpec {
31625            type Ux = u32;
31626        }
31627        #[doc = "`read()` method returns [`cfg_rx_start_addr::R`](R) reader structure"]
31628        impl crate::Readable for CfgRxStartAddrSpec {}
31629        #[doc = "`write(|w| ..)` method takes [`cfg_rx_start_addr::W`](W) writer structure"]
31630        impl crate::Writable for CfgRxStartAddrSpec {
31631            type Safety = crate::Unsafe;
31632        }
31633        #[doc = "`reset()` method sets CFG_RX_START_ADDR to value 0"]
31634        impl crate::Resettable for CfgRxStartAddrSpec {}
31635    }
31636    #[doc = "CFG_RX_END_ADDR (rw) register accessor: RX end address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_end_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_end_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rx_end_addr`] module"]
31637    #[doc(alias = "CFG_RX_END_ADDR")]
31638    pub type CfgRxEndAddr = crate::Reg<cfg_rx_end_addr::CfgRxEndAddrSpec>;
31639    #[doc = "RX end address"]
31640    pub mod cfg_rx_end_addr {
31641        #[doc = "Register `CFG_RX_END_ADDR` reader"]
31642        pub type R = crate::R<CfgRxEndAddrSpec>;
31643        #[doc = "Register `CFG_RX_END_ADDR` writer"]
31644        pub type W = crate::W<CfgRxEndAddrSpec>;
31645        impl core::fmt::Debug for R {
31646            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31647                write!(f, "{}", self.bits())
31648            }
31649        }
31650        impl W {}
31651        #[doc = "RX end address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_end_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_end_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31652        pub struct CfgRxEndAddrSpec;
31653        impl crate::RegisterSpec for CfgRxEndAddrSpec {
31654            type Ux = u32;
31655        }
31656        #[doc = "`read()` method returns [`cfg_rx_end_addr::R`](R) reader structure"]
31657        impl crate::Readable for CfgRxEndAddrSpec {}
31658        #[doc = "`write(|w| ..)` method takes [`cfg_rx_end_addr::W`](W) writer structure"]
31659        impl crate::Writable for CfgRxEndAddrSpec {
31660            type Safety = crate::Unsafe;
31661        }
31662        #[doc = "`reset()` method sets CFG_RX_END_ADDR to value 0"]
31663        impl crate::Resettable for CfgRxEndAddrSpec {}
31664    }
31665    #[doc = "CFG_RX_DONE_STS (rw) register accessor: RX done status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_done_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_done_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rx_done_sts`] module"]
31666    #[doc(alias = "CFG_RX_DONE_STS")]
31667    pub type CfgRxDoneSts = crate::Reg<cfg_rx_done_sts::CfgRxDoneStsSpec>;
31668    #[doc = "RX done status"]
31669    pub mod cfg_rx_done_sts {
31670        #[doc = "Register `CFG_RX_DONE_STS` reader"]
31671        pub type R = crate::R<CfgRxDoneStsSpec>;
31672        #[doc = "Register `CFG_RX_DONE_STS` writer"]
31673        pub type W = crate::W<CfgRxDoneStsSpec>;
31674        impl core::fmt::Debug for R {
31675            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31676                write!(f, "{}", self.bits())
31677            }
31678        }
31679        impl W {}
31680        #[doc = "RX done status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_done_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_done_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31681        pub struct CfgRxDoneStsSpec;
31682        impl crate::RegisterSpec for CfgRxDoneStsSpec {
31683            type Ux = u32;
31684        }
31685        #[doc = "`read()` method returns [`cfg_rx_done_sts::R`](R) reader structure"]
31686        impl crate::Readable for CfgRxDoneStsSpec {}
31687        #[doc = "`write(|w| ..)` method takes [`cfg_rx_done_sts::W`](W) writer structure"]
31688        impl crate::Writable for CfgRxDoneStsSpec {
31689            type Safety = crate::Unsafe;
31690        }
31691        #[doc = "`reset()` method sets CFG_RX_DONE_STS to value 0"]
31692        impl crate::Resettable for CfgRxDoneStsSpec {}
31693    }
31694    #[doc = "CFG_RX_DONE_ADDR (rw) register accessor: RX done address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_done_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_done_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rx_done_addr`] module"]
31695    #[doc(alias = "CFG_RX_DONE_ADDR")]
31696    pub type CfgRxDoneAddr = crate::Reg<cfg_rx_done_addr::CfgRxDoneAddrSpec>;
31697    #[doc = "RX done address"]
31698    pub mod cfg_rx_done_addr {
31699        #[doc = "Register `CFG_RX_DONE_ADDR` reader"]
31700        pub type R = crate::R<CfgRxDoneAddrSpec>;
31701        #[doc = "Register `CFG_RX_DONE_ADDR` writer"]
31702        pub type W = crate::W<CfgRxDoneAddrSpec>;
31703        impl core::fmt::Debug for R {
31704            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31705                write!(f, "{}", self.bits())
31706            }
31707        }
31708        impl W {}
31709        #[doc = "RX done address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_done_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_done_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31710        pub struct CfgRxDoneAddrSpec;
31711        impl crate::RegisterSpec for CfgRxDoneAddrSpec {
31712            type Ux = u32;
31713        }
31714        #[doc = "`read()` method returns [`cfg_rx_done_addr::R`](R) reader structure"]
31715        impl crate::Readable for CfgRxDoneAddrSpec {}
31716        #[doc = "`write(|w| ..)` method takes [`cfg_rx_done_addr::W`](W) writer structure"]
31717        impl crate::Writable for CfgRxDoneAddrSpec {
31718            type Safety = crate::Unsafe;
31719        }
31720        #[doc = "`reset()` method sets CFG_RX_DONE_ADDR to value 0"]
31721        impl crate::Resettable for CfgRxDoneAddrSpec {}
31722    }
31723    #[doc = "CFG_WLPHY2PKT_RX_RAM_STS (rw) register accessor: WL PHY-to-packet RX RAM status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wlphy2pkt_rx_ram_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wlphy2pkt_rx_ram_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_wlphy2pkt_rx_ram_sts`] module"]
31724    #[doc(alias = "CFG_WLPHY2PKT_RX_RAM_STS")]
31725    pub type CfgWlphy2pktRxRamSts = crate::Reg<cfg_wlphy2pkt_rx_ram_sts::CfgWlphy2pktRxRamStsSpec>;
31726    #[doc = "WL PHY-to-packet RX RAM status"]
31727    pub mod cfg_wlphy2pkt_rx_ram_sts {
31728        #[doc = "Register `CFG_WLPHY2PKT_RX_RAM_STS` reader"]
31729        pub type R = crate::R<CfgWlphy2pktRxRamStsSpec>;
31730        #[doc = "Register `CFG_WLPHY2PKT_RX_RAM_STS` writer"]
31731        pub type W = crate::W<CfgWlphy2pktRxRamStsSpec>;
31732        impl core::fmt::Debug for R {
31733            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31734                write!(f, "{}", self.bits())
31735            }
31736        }
31737        impl W {}
31738        #[doc = "WL PHY-to-packet RX RAM status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wlphy2pkt_rx_ram_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wlphy2pkt_rx_ram_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31739        pub struct CfgWlphy2pktRxRamStsSpec;
31740        impl crate::RegisterSpec for CfgWlphy2pktRxRamStsSpec {
31741            type Ux = u32;
31742        }
31743        #[doc = "`read()` method returns [`cfg_wlphy2pkt_rx_ram_sts::R`](R) reader structure"]
31744        impl crate::Readable for CfgWlphy2pktRxRamStsSpec {}
31745        #[doc = "`write(|w| ..)` method takes [`cfg_wlphy2pkt_rx_ram_sts::W`](W) writer structure"]
31746        impl crate::Writable for CfgWlphy2pktRxRamStsSpec {
31747            type Safety = crate::Unsafe;
31748        }
31749        #[doc = "`reset()` method sets CFG_WLPHY2PKT_RX_RAM_STS to value 0"]
31750        impl crate::Resettable for CfgWlphy2pktRxRamStsSpec {}
31751    }
31752    #[doc = "CFG_TX_EN (rw) register accessor: TX enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tx_en`] module"]
31753    #[doc(alias = "CFG_TX_EN")]
31754    pub type CfgTxEn = crate::Reg<cfg_tx_en::CfgTxEnSpec>;
31755    #[doc = "TX enable"]
31756    pub mod cfg_tx_en {
31757        #[doc = "Register `CFG_TX_EN` reader"]
31758        pub type R = crate::R<CfgTxEnSpec>;
31759        #[doc = "Register `CFG_TX_EN` writer"]
31760        pub type W = crate::W<CfgTxEnSpec>;
31761        impl core::fmt::Debug for R {
31762            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31763                write!(f, "{}", self.bits())
31764            }
31765        }
31766        impl W {}
31767        #[doc = "TX enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31768        pub struct CfgTxEnSpec;
31769        impl crate::RegisterSpec for CfgTxEnSpec {
31770            type Ux = u32;
31771        }
31772        #[doc = "`read()` method returns [`cfg_tx_en::R`](R) reader structure"]
31773        impl crate::Readable for CfgTxEnSpec {}
31774        #[doc = "`write(|w| ..)` method takes [`cfg_tx_en::W`](W) writer structure"]
31775        impl crate::Writable for CfgTxEnSpec {
31776            type Safety = crate::Unsafe;
31777        }
31778        #[doc = "`reset()` method sets CFG_TX_EN to value 0"]
31779        impl crate::Resettable for CfgTxEnSpec {}
31780    }
31781    #[doc = "CFG_TX_START_ADDR (rw) register accessor: TX start address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_start_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_start_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tx_start_addr`] module"]
31782    #[doc(alias = "CFG_TX_START_ADDR")]
31783    pub type CfgTxStartAddr = crate::Reg<cfg_tx_start_addr::CfgTxStartAddrSpec>;
31784    #[doc = "TX start address"]
31785    pub mod cfg_tx_start_addr {
31786        #[doc = "Register `CFG_TX_START_ADDR` reader"]
31787        pub type R = crate::R<CfgTxStartAddrSpec>;
31788        #[doc = "Register `CFG_TX_START_ADDR` writer"]
31789        pub type W = crate::W<CfgTxStartAddrSpec>;
31790        impl core::fmt::Debug for R {
31791            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31792                write!(f, "{}", self.bits())
31793            }
31794        }
31795        impl W {}
31796        #[doc = "TX start address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_start_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_start_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31797        pub struct CfgTxStartAddrSpec;
31798        impl crate::RegisterSpec for CfgTxStartAddrSpec {
31799            type Ux = u32;
31800        }
31801        #[doc = "`read()` method returns [`cfg_tx_start_addr::R`](R) reader structure"]
31802        impl crate::Readable for CfgTxStartAddrSpec {}
31803        #[doc = "`write(|w| ..)` method takes [`cfg_tx_start_addr::W`](W) writer structure"]
31804        impl crate::Writable for CfgTxStartAddrSpec {
31805            type Safety = crate::Unsafe;
31806        }
31807        #[doc = "`reset()` method sets CFG_TX_START_ADDR to value 0"]
31808        impl crate::Resettable for CfgTxStartAddrSpec {}
31809    }
31810    #[doc = "CFG_TX_END_ADDR (rw) register accessor: TX end address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_end_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_end_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tx_end_addr`] module"]
31811    #[doc(alias = "CFG_TX_END_ADDR")]
31812    pub type CfgTxEndAddr = crate::Reg<cfg_tx_end_addr::CfgTxEndAddrSpec>;
31813    #[doc = "TX end address"]
31814    pub mod cfg_tx_end_addr {
31815        #[doc = "Register `CFG_TX_END_ADDR` reader"]
31816        pub type R = crate::R<CfgTxEndAddrSpec>;
31817        #[doc = "Register `CFG_TX_END_ADDR` writer"]
31818        pub type W = crate::W<CfgTxEndAddrSpec>;
31819        impl core::fmt::Debug for R {
31820            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31821                write!(f, "{}", self.bits())
31822            }
31823        }
31824        impl W {}
31825        #[doc = "TX end address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_end_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_end_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31826        pub struct CfgTxEndAddrSpec;
31827        impl crate::RegisterSpec for CfgTxEndAddrSpec {
31828            type Ux = u32;
31829        }
31830        #[doc = "`read()` method returns [`cfg_tx_end_addr::R`](R) reader structure"]
31831        impl crate::Readable for CfgTxEndAddrSpec {}
31832        #[doc = "`write(|w| ..)` method takes [`cfg_tx_end_addr::W`](W) writer structure"]
31833        impl crate::Writable for CfgTxEndAddrSpec {
31834            type Safety = crate::Unsafe;
31835        }
31836        #[doc = "`reset()` method sets CFG_TX_END_ADDR to value 0"]
31837        impl crate::Resettable for CfgTxEndAddrSpec {}
31838    }
31839    #[doc = "CFG_TX_DONE_STS (rw) register accessor: TX done status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_done_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_done_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tx_done_sts`] module"]
31840    #[doc(alias = "CFG_TX_DONE_STS")]
31841    pub type CfgTxDoneSts = crate::Reg<cfg_tx_done_sts::CfgTxDoneStsSpec>;
31842    #[doc = "TX done status"]
31843    pub mod cfg_tx_done_sts {
31844        #[doc = "Register `CFG_TX_DONE_STS` reader"]
31845        pub type R = crate::R<CfgTxDoneStsSpec>;
31846        #[doc = "Register `CFG_TX_DONE_STS` writer"]
31847        pub type W = crate::W<CfgTxDoneStsSpec>;
31848        impl core::fmt::Debug for R {
31849            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31850                write!(f, "{}", self.bits())
31851            }
31852        }
31853        impl W {}
31854        #[doc = "TX done status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_done_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_done_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31855        pub struct CfgTxDoneStsSpec;
31856        impl crate::RegisterSpec for CfgTxDoneStsSpec {
31857            type Ux = u32;
31858        }
31859        #[doc = "`read()` method returns [`cfg_tx_done_sts::R`](R) reader structure"]
31860        impl crate::Readable for CfgTxDoneStsSpec {}
31861        #[doc = "`write(|w| ..)` method takes [`cfg_tx_done_sts::W`](W) writer structure"]
31862        impl crate::Writable for CfgTxDoneStsSpec {
31863            type Safety = crate::Unsafe;
31864        }
31865        #[doc = "`reset()` method sets CFG_TX_DONE_STS to value 0"]
31866        impl crate::Resettable for CfgTxDoneStsSpec {}
31867    }
31868    #[doc = "CFG_TX_DONE_ADDR (rw) register accessor: TX done address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_done_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_done_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tx_done_addr`] module"]
31869    #[doc(alias = "CFG_TX_DONE_ADDR")]
31870    pub type CfgTxDoneAddr = crate::Reg<cfg_tx_done_addr::CfgTxDoneAddrSpec>;
31871    #[doc = "TX done address"]
31872    pub mod cfg_tx_done_addr {
31873        #[doc = "Register `CFG_TX_DONE_ADDR` reader"]
31874        pub type R = crate::R<CfgTxDoneAddrSpec>;
31875        #[doc = "Register `CFG_TX_DONE_ADDR` writer"]
31876        pub type W = crate::W<CfgTxDoneAddrSpec>;
31877        impl core::fmt::Debug for R {
31878            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31879                write!(f, "{}", self.bits())
31880            }
31881        }
31882        impl W {}
31883        #[doc = "TX done address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_done_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_done_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31884        pub struct CfgTxDoneAddrSpec;
31885        impl crate::RegisterSpec for CfgTxDoneAddrSpec {
31886            type Ux = u32;
31887        }
31888        #[doc = "`read()` method returns [`cfg_tx_done_addr::R`](R) reader structure"]
31889        impl crate::Readable for CfgTxDoneAddrSpec {}
31890        #[doc = "`write(|w| ..)` method takes [`cfg_tx_done_addr::W`](W) writer structure"]
31891        impl crate::Writable for CfgTxDoneAddrSpec {
31892            type Safety = crate::Unsafe;
31893        }
31894        #[doc = "`reset()` method sets CFG_TX_DONE_ADDR to value 0"]
31895        impl crate::Resettable for CfgTxDoneAddrSpec {}
31896    }
31897    #[doc = "CFG_WLPHY2PKT_TX_RAM_STS (rw) register accessor: WL PHY-to-packet TX RAM status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wlphy2pkt_tx_ram_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wlphy2pkt_tx_ram_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_wlphy2pkt_tx_ram_sts`] module"]
31898    #[doc(alias = "CFG_WLPHY2PKT_TX_RAM_STS")]
31899    pub type CfgWlphy2pktTxRamSts = crate::Reg<cfg_wlphy2pkt_tx_ram_sts::CfgWlphy2pktTxRamStsSpec>;
31900    #[doc = "WL PHY-to-packet TX RAM status"]
31901    pub mod cfg_wlphy2pkt_tx_ram_sts {
31902        #[doc = "Register `CFG_WLPHY2PKT_TX_RAM_STS` reader"]
31903        pub type R = crate::R<CfgWlphy2pktTxRamStsSpec>;
31904        #[doc = "Register `CFG_WLPHY2PKT_TX_RAM_STS` writer"]
31905        pub type W = crate::W<CfgWlphy2pktTxRamStsSpec>;
31906        impl core::fmt::Debug for R {
31907            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31908                write!(f, "{}", self.bits())
31909            }
31910        }
31911        impl W {}
31912        #[doc = "WL PHY-to-packet TX RAM status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wlphy2pkt_tx_ram_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wlphy2pkt_tx_ram_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31913        pub struct CfgWlphy2pktTxRamStsSpec;
31914        impl crate::RegisterSpec for CfgWlphy2pktTxRamStsSpec {
31915            type Ux = u32;
31916        }
31917        #[doc = "`read()` method returns [`cfg_wlphy2pkt_tx_ram_sts::R`](R) reader structure"]
31918        impl crate::Readable for CfgWlphy2pktTxRamStsSpec {}
31919        #[doc = "`write(|w| ..)` method takes [`cfg_wlphy2pkt_tx_ram_sts::W`](W) writer structure"]
31920        impl crate::Writable for CfgWlphy2pktTxRamStsSpec {
31921            type Safety = crate::Unsafe;
31922        }
31923        #[doc = "`reset()` method sets CFG_WLPHY2PKT_TX_RAM_STS to value 0"]
31924        impl crate::Resettable for CfgWlphy2pktTxRamStsSpec {}
31925    }
31926}
31927#[doc = "SYS_CTL2 sub-block: Flash Address Map Remap - up to 12 regions for boot-time address redirection"]
31928pub type FamaRemap = crate::Periph<fama_remap::RegisterBlock, 0x4400_7800>;
31929impl core::fmt::Debug for FamaRemap {
31930    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31931        f.debug_struct("FamaRemap").finish()
31932    }
31933}
31934#[doc = "SYS_CTL2 sub-block: Flash Address Map Remap - up to 12 regions for boot-time address redirection"]
31935pub mod fama_remap {
31936    #[repr(C)]
31937    #[doc = "Register block"]
31938    pub struct RegisterBlock {
31939        remap_src_base: RemapSrcBase,
31940        _reserved1: [u8; 0x1c],
31941        remap_len: RemapLen,
31942        _reserved2: [u8; 0x1c],
31943        remap_dst_base: RemapDstBase,
31944    }
31945    impl RegisterBlock {
31946        #[doc = "0x00 - Remap source base address (address >> 12). Up to 12 regions, offset 0x0 + 0x4*n"]
31947        #[inline(always)]
31948        pub const fn remap_src_base(&self) -> &RemapSrcBase {
31949            &self.remap_src_base
31950        }
31951        #[doc = "0x20 - Remap region length (end address >> 12). offset 0x20 + 0x4*n"]
31952        #[inline(always)]
31953        pub const fn remap_len(&self) -> &RemapLen {
31954            &self.remap_len
31955        }
31956        #[doc = "0x40 - Remap destination base offset (dest - src). offset 0x40 + 0x4*n"]
31957        #[inline(always)]
31958        pub const fn remap_dst_base(&self) -> &RemapDstBase {
31959            &self.remap_dst_base
31960        }
31961    }
31962    #[doc = "REMAP_SRC_BASE (rw) register accessor: Remap source base address (address >> 12). Up to 12 regions, offset 0x0 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_src_base::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_src_base::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap_src_base`] module"]
31963    #[doc(alias = "REMAP_SRC_BASE")]
31964    pub type RemapSrcBase = crate::Reg<remap_src_base::RemapSrcBaseSpec>;
31965    #[doc = "Remap source base address (address >> 12). Up to 12 regions, offset 0x0 + 0x4*n"]
31966    pub mod remap_src_base {
31967        #[doc = "Register `REMAP_SRC_BASE` reader"]
31968        pub type R = crate::R<RemapSrcBaseSpec>;
31969        #[doc = "Register `REMAP_SRC_BASE` writer"]
31970        pub type W = crate::W<RemapSrcBaseSpec>;
31971        impl core::fmt::Debug for R {
31972            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31973                write!(f, "{}", self.bits())
31974            }
31975        }
31976        impl W {}
31977        #[doc = "Remap source base address (address >> 12). Up to 12 regions, offset 0x0 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_src_base::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_src_base::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31978        pub struct RemapSrcBaseSpec;
31979        impl crate::RegisterSpec for RemapSrcBaseSpec {
31980            type Ux = u32;
31981        }
31982        #[doc = "`read()` method returns [`remap_src_base::R`](R) reader structure"]
31983        impl crate::Readable for RemapSrcBaseSpec {}
31984        #[doc = "`write(|w| ..)` method takes [`remap_src_base::W`](W) writer structure"]
31985        impl crate::Writable for RemapSrcBaseSpec {
31986            type Safety = crate::Unsafe;
31987        }
31988        #[doc = "`reset()` method sets REMAP_SRC_BASE to value 0"]
31989        impl crate::Resettable for RemapSrcBaseSpec {}
31990    }
31991    #[doc = "REMAP_LEN (rw) register accessor: Remap region length (end address >> 12). offset 0x20 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap_len`] module"]
31992    #[doc(alias = "REMAP_LEN")]
31993    pub type RemapLen = crate::Reg<remap_len::RemapLenSpec>;
31994    #[doc = "Remap region length (end address >> 12). offset 0x20 + 0x4*n"]
31995    pub mod remap_len {
31996        #[doc = "Register `REMAP_LEN` reader"]
31997        pub type R = crate::R<RemapLenSpec>;
31998        #[doc = "Register `REMAP_LEN` writer"]
31999        pub type W = crate::W<RemapLenSpec>;
32000        impl core::fmt::Debug for R {
32001            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
32002                write!(f, "{}", self.bits())
32003            }
32004        }
32005        impl W {}
32006        #[doc = "Remap region length (end address >> 12). offset 0x20 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32007        pub struct RemapLenSpec;
32008        impl crate::RegisterSpec for RemapLenSpec {
32009            type Ux = u32;
32010        }
32011        #[doc = "`read()` method returns [`remap_len::R`](R) reader structure"]
32012        impl crate::Readable for RemapLenSpec {}
32013        #[doc = "`write(|w| ..)` method takes [`remap_len::W`](W) writer structure"]
32014        impl crate::Writable for RemapLenSpec {
32015            type Safety = crate::Unsafe;
32016        }
32017        #[doc = "`reset()` method sets REMAP_LEN to value 0"]
32018        impl crate::Resettable for RemapLenSpec {}
32019    }
32020    #[doc = "REMAP_DST_BASE (rw) register accessor: Remap destination base offset (dest - src). offset 0x40 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_dst_base::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_dst_base::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap_dst_base`] module"]
32021    #[doc(alias = "REMAP_DST_BASE")]
32022    pub type RemapDstBase = crate::Reg<remap_dst_base::RemapDstBaseSpec>;
32023    #[doc = "Remap destination base offset (dest - src). offset 0x40 + 0x4*n"]
32024    pub mod remap_dst_base {
32025        #[doc = "Register `REMAP_DST_BASE` reader"]
32026        pub type R = crate::R<RemapDstBaseSpec>;
32027        #[doc = "Register `REMAP_DST_BASE` writer"]
32028        pub type W = crate::W<RemapDstBaseSpec>;
32029        impl core::fmt::Debug for R {
32030            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
32031                write!(f, "{}", self.bits())
32032            }
32033        }
32034        impl W {}
32035        #[doc = "Remap destination base offset (dest - src). offset 0x40 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_dst_base::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_dst_base::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32036        pub struct RemapDstBaseSpec;
32037        impl crate::RegisterSpec for RemapDstBaseSpec {
32038            type Ux = u32;
32039        }
32040        #[doc = "`read()` method returns [`remap_dst_base::R`](R) reader structure"]
32041        impl crate::Readable for RemapDstBaseSpec {}
32042        #[doc = "`write(|w| ..)` method takes [`remap_dst_base::W`](W) writer structure"]
32043        impl crate::Writable for RemapDstBaseSpec {
32044            type Safety = crate::Unsafe;
32045        }
32046        #[doc = "`reset()` method sets REMAP_DST_BASE to value 0"]
32047        impl crate::Resettable for RemapDstBaseSpec {}
32048    }
32049}
32050#[unsafe(no_mangle)]
32051static mut DEVICE_PERIPHERALS: bool = false;
32052#[doc = r" All the peripherals."]
32053#[allow(non_snake_case)]
32054pub struct Peripherals {
32055    #[doc = "SYS_CTL1"]
32056    pub sys_ctl1: SysCtl1,
32057    #[doc = "IO_CONFIG"]
32058    pub io_config: IoConfig,
32059    #[doc = "GPIO0"]
32060    pub gpio0: Gpio0,
32061    #[doc = "GPIO1"]
32062    pub gpio1: Gpio1,
32063    #[doc = "GPIO2"]
32064    pub gpio2: Gpio2,
32065    #[doc = "UART0"]
32066    pub uart0: Uart0,
32067    #[doc = "UART1"]
32068    pub uart1: Uart1,
32069    #[doc = "UART2"]
32070    pub uart2: Uart2,
32071    #[doc = "I2C0"]
32072    pub i2c0: I2c0,
32073    #[doc = "I2C1"]
32074    pub i2c1: I2c1,
32075    #[doc = "PWM"]
32076    pub pwm: Pwm,
32077    #[doc = "DMA"]
32078    pub dma: Dma,
32079    #[doc = "SFC_CFG"]
32080    pub sfc_cfg: SfcCfg,
32081    #[doc = "SPI0"]
32082    pub spi0: Spi0,
32083    #[doc = "SPI1"]
32084    pub spi1: Spi1,
32085    #[doc = "I2S"]
32086    pub i2s: I2s,
32087    #[doc = "LSADC"]
32088    pub lsadc: Lsadc,
32089    #[doc = "TSENSOR"]
32090    pub tsensor: Tsensor,
32091    #[doc = "TIMER"]
32092    pub timer: Timer,
32093    #[doc = "WDT"]
32094    pub wdt: Wdt,
32095    #[doc = "RTC"]
32096    pub rtc: Rtc,
32097    #[doc = "EFUSE"]
32098    pub efuse: Efuse,
32099    #[doc = "SYS_CTL0"]
32100    pub sys_ctl0: SysCtl0,
32101    #[doc = "GLB_CTL_M"]
32102    pub glb_ctl_m: GlbCtlM,
32103    #[doc = "SPACC"]
32104    pub spacc: Spacc,
32105    #[doc = "PKE"]
32106    pub pke: Pke,
32107    #[doc = "KM"]
32108    pub km: Km,
32109    #[doc = "TRNG"]
32110    pub trng: Trng,
32111    #[doc = "TCXO"]
32112    pub tcxo: Tcxo,
32113    #[doc = "CLDO_CRG"]
32114    pub cldo_crg: CldoCrg,
32115    #[doc = "SDMA"]
32116    pub sdma: Sdma,
32117    #[doc = "ULP_GPIO"]
32118    pub ulp_gpio: UlpGpio,
32119    #[doc = "RF_WB_CTL"]
32120    pub rf_wb_ctl: RfWbCtl,
32121    #[doc = "SHARE_MEM_CTL"]
32122    pub share_mem_ctl: ShareMemCtl,
32123    #[doc = "FAMA_REMAP"]
32124    pub fama_remap: FamaRemap,
32125}
32126impl Peripherals {
32127    #[doc = r" Returns all the peripherals *once*."]
32128    #[cfg(feature = "critical-section")]
32129    #[inline]
32130    pub fn take() -> Option<Self> {
32131        critical_section::with(|_| {
32132            if unsafe { DEVICE_PERIPHERALS } {
32133                return None;
32134            }
32135            Some(unsafe { Peripherals::steal() })
32136        })
32137    }
32138    #[doc = r" Unchecked version of `Peripherals::take`."]
32139    #[doc = r""]
32140    #[doc = r" # Safety"]
32141    #[doc = r""]
32142    #[doc = r" Each of the returned peripherals must be used at most once."]
32143    #[inline]
32144    pub unsafe fn steal() -> Self {
32145        unsafe {
32146            DEVICE_PERIPHERALS = true;
32147            Peripherals {
32148                sys_ctl1: SysCtl1::steal(),
32149                io_config: IoConfig::steal(),
32150                gpio0: Gpio0::steal(),
32151                gpio1: Gpio1::steal(),
32152                gpio2: Gpio2::steal(),
32153                uart0: Uart0::steal(),
32154                uart1: Uart1::steal(),
32155                uart2: Uart2::steal(),
32156                i2c0: I2c0::steal(),
32157                i2c1: I2c1::steal(),
32158                pwm: Pwm::steal(),
32159                dma: Dma::steal(),
32160                sfc_cfg: SfcCfg::steal(),
32161                spi0: Spi0::steal(),
32162                spi1: Spi1::steal(),
32163                i2s: I2s::steal(),
32164                lsadc: Lsadc::steal(),
32165                tsensor: Tsensor::steal(),
32166                timer: Timer::steal(),
32167                wdt: Wdt::steal(),
32168                rtc: Rtc::steal(),
32169                efuse: Efuse::steal(),
32170                sys_ctl0: SysCtl0::steal(),
32171                glb_ctl_m: GlbCtlM::steal(),
32172                spacc: Spacc::steal(),
32173                pke: Pke::steal(),
32174                km: Km::steal(),
32175                trng: Trng::steal(),
32176                tcxo: Tcxo::steal(),
32177                cldo_crg: CldoCrg::steal(),
32178                sdma: Sdma::steal(),
32179                ulp_gpio: UlpGpio::steal(),
32180                rf_wb_ctl: RfWbCtl::steal(),
32181                share_mem_ctl: ShareMemCtl::steal(),
32182                fama_remap: FamaRemap::steal(),
32183            }
32184        }
32185    }
32186}