ws63-pac 0.1.0

# ! [doc = "Peripheral access API for WS63 microcontrollers (generated using svd2rust v0.37.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] # ! [allow (non_camel_case_types)] # ! [allow (non_snake_case)] # ! [no_std] # ! [cfg_attr (docsrs , feature (doc_cfg))]
#[doc = r"Number available in the NVIC for configuring priority"] pub const NVIC_PRIO_BITS : u8 = 3 ;
#[allow (unused_imports)] use generic :: * ;
#[doc = r"Common register and bit access and modify traits"] pub mod generic { use core :: marker ;
#[doc = " Generic peripheral accessor"] pub struct Periph < RB , const A : usize > { _marker : marker :: PhantomData < RB > , } unsafe impl < RB , const A : usize > Send for Periph < RB , A > { } impl < RB , const A : usize > Periph < RB , A > {
#[doc = "Pointer to the register block"] pub const PTR : * const RB = A as * const _ ;
#[doc = "Return the pointer to the register block"]
#[inline (always)] pub const fn ptr () -> * const RB { Self :: PTR }
#[doc = " Steal an instance of this peripheral"]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = " that may race with any existing instances, for example by only"]
#[doc = " accessing read-only or write-only registers, or by consuming the"]
#[doc = " original peripheral and using critical sections to coordinate"]
#[doc = " access between multiple new instances."]
#[doc = ""]
#[doc = " Additionally, other software such as HALs may rely on only one"]
#[doc = " peripheral instance existing to ensure memory safety; ensure"]
#[doc = " no stolen instances are passed to such software."] pub unsafe fn steal () -> Self { Self { _marker : marker :: PhantomData , } } } impl < RB , const A : usize > core :: ops :: Deref for Periph < RB , A > { type Target = RB ;
#[inline (always)] fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } }
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] pub trait RawReg : Copy + From < bool > + core :: ops :: BitOr < Output = Self > + core :: ops :: BitAnd < Output = Self > + core :: ops :: BitOrAssign + core :: ops :: BitAndAssign + core :: ops :: Not < Output = Self > + core :: ops :: Shl < u8 , Output = Self > {
#[doc = " Mask for bits of width `WI`"] fn mask < const WI : u8 > () -> Self ;
#[doc = " `0`"] const ZERO : Self ;
#[doc = " `1`"] const ONE : Self ; } macro_rules ! raw_reg { ($ U : ty , $ size : literal , $ mask : ident) => { impl RawReg for $ U {
#[inline (always)] fn mask < const WI : u8 > () -> Self { $ mask ::< WI > () } const ZERO : Self = 0 ; const ONE : Self = 1 ; } const fn $ mask < const WI : u8 > () -> $ U { <$ U >:: MAX >> ($ size - WI) } impl FieldSpec for $ U { type Ux = $ U ; } } ; } raw_reg ! (u8 , 8 , mask_u8) ; raw_reg ! (u16 , 16 , mask_u16) ; raw_reg ! (u32 , 32 , mask_u32) ; raw_reg ! (u64 , 64 , mask_u64) ;
#[doc = " Raw register type"] pub trait RegisterSpec {
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] type Ux : RawReg ; }
#[doc = " Raw field type"] pub trait FieldSpec : Sized {
#[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] type Ux : Copy + core :: fmt :: Debug + PartialEq + From < Self > ; }
#[doc = " Marker for fields with fixed values"] pub trait IsEnum : FieldSpec { }
#[doc = " Trait implemented by readable registers to enable the `read` method."]
#[doc = ""]
#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] pub trait Readable : RegisterSpec { }
#[doc = " Trait implemented by writeable registers."]
#[doc = ""]
#[doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
#[doc = ""]
#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] pub trait Writable : RegisterSpec {
#[doc = " Is it safe to write any bits to register"] type Safety ;
#[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = Self :: Ux :: ZERO ;
#[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = Self :: Ux :: ZERO ; }
#[doc = " Reset value of the register."]
#[doc = ""]
#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
#[doc = " register by using the `reset` method."] pub trait Resettable : RegisterSpec {
#[doc = " Reset value of the register."] const RESET_VALUE : Self :: Ux = Self :: Ux :: ZERO ;
#[doc = " Reset value of the register."]
#[inline (always)] fn reset_value () -> Self :: Ux { Self :: RESET_VALUE } }
#[doc (hidden)] pub mod raw { use super :: { marker , BitM , FieldSpec , RegisterSpec , Unsafe , Writable } ; pub struct R < REG : RegisterSpec > { pub (crate) bits : REG :: Ux , pub (super) _reg : marker :: PhantomData < REG > , } pub struct W < REG : RegisterSpec > {
#[doc = "Writable bits"] pub (crate) bits : REG :: Ux , pub (super) _reg : marker :: PhantomData < REG > , } pub struct FieldReader < FI = u8 > where FI : FieldSpec , { pub (crate) bits : FI :: Ux , _reg : marker :: PhantomData < FI > , } impl < FI : FieldSpec > FieldReader < FI > {
#[doc = " Creates a new instance of the reader."]
#[allow (unused)]
#[inline (always)] pub (crate) const fn new (bits : FI :: Ux) -> Self { Self { bits , _reg : marker :: PhantomData , } } } pub struct BitReader < FI = bool > { pub (crate) bits : bool , _reg : marker :: PhantomData < FI > , } impl < FI > BitReader < FI > {
#[doc = " Creates a new instance of the reader."]
#[allow (unused)]
#[inline (always)] pub (crate) const fn new (bits : bool) -> Self { Self { bits , _reg : marker :: PhantomData , } } }
#[must_use = "after creating `FieldWriter` you need to call field value setting method"] pub struct FieldWriter < 'a , REG , const WI : u8 , FI = u8 , Safety = Unsafe > where REG : Writable + RegisterSpec , FI : FieldSpec , { pub (crate) w : & 'a mut W < REG > , pub (crate) o : u8 , _field : marker :: PhantomData < (FI , Safety) > , } impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , {
#[doc = " Creates a new instance of the writer"]
#[allow (unused)]
#[inline (always)] pub (crate) fn new (w : & 'a mut W < REG > , o : u8) -> Self { Self { w , o , _field : marker :: PhantomData , } } }
#[must_use = "after creating `BitWriter` you need to call bit setting method"] pub struct BitWriter < 'a , REG , FI = bool , M = BitM > where REG : Writable + RegisterSpec , bool : From < FI > , { pub (crate) w : & 'a mut W < REG > , pub (crate) o : u8 , _field : marker :: PhantomData < (FI , M) > , } impl < 'a , REG , FI , M > BitWriter < 'a , REG , FI , M > where REG : Writable + RegisterSpec , bool : From < FI > , {
#[doc = " Creates a new instance of the writer"]
#[allow (unused)]
#[inline (always)] pub (crate) fn new (w : & 'a mut W < REG > , o : u8) -> Self { Self { w , o , _field : marker :: PhantomData , } } } }
#[doc = " Register reader."]
#[doc = ""]
#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
#[doc = " method."] pub type R < REG > = raw :: R < REG > ; impl < REG : RegisterSpec > R < REG > {
#[doc = " Reads raw bits from register."]
#[inline (always)] pub const fn bits (& self) -> REG :: Ux { self . bits } } impl < REG : RegisterSpec , FI > PartialEq < FI > for R < REG > where REG :: Ux : PartialEq , FI : Copy , REG :: Ux : From < FI > , {
#[inline (always)] fn eq (& self , other : & FI) -> bool { self . bits . eq (& REG :: Ux :: from (* other)) } }
#[doc = " Register writer."]
#[doc = ""]
#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] pub type W < REG > = raw :: W < REG > ; impl < REG : Writable > W < REG > {
#[doc = " Writes raw bits to the register."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline (always)] pub unsafe fn bits (& mut self , bits : REG :: Ux) -> & mut Self { self . bits = bits ; self } } impl < REG > W < REG > where REG : Writable < Safety = Safe > , {
#[doc = " Writes raw bits to the register."]
#[inline (always)] pub fn set (& mut self , bits : REG :: Ux) -> & mut Self { self . bits = bits ; self } }
#[doc = " Field reader."]
#[doc = ""]
#[doc = " Result of the `read` methods of fields."] pub type FieldReader < FI = u8 > = raw :: FieldReader < FI > ;
#[doc = " Bit-wise field reader"] pub type BitReader < FI = bool > = raw :: BitReader < FI > ; impl < FI : FieldSpec > FieldReader < FI > {
#[doc = " Reads raw bits from field."]
#[inline (always)] pub const fn bits (& self) -> FI :: Ux { self . bits } } impl < FI : FieldSpec > core :: fmt :: Debug for FieldReader < FI > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . bits , f) } } impl < FI > PartialEq < FI > for FieldReader < FI > where FI : FieldSpec + Copy , {
#[inline (always)] fn eq (& self , other : & FI) -> bool { self . bits . eq (& FI :: Ux :: from (* other)) } } impl < FI > PartialEq < FI > for BitReader < FI > where FI : Copy , bool : From < FI > , {
#[inline (always)] fn eq (& self , other : & FI) -> bool { self . bits . eq (& bool :: from (* other)) } } impl < FI > BitReader < FI > {
#[doc = " Value of the field as raw bits."]
#[inline (always)] pub const fn bit (& self) -> bool { self . bits }
#[doc = " Returns `true` if the bit is clear (0)."]
#[inline (always)] pub const fn bit_is_clear (& self) -> bool { ! self . bit () }
#[doc = " Returns `true` if the bit is set (1)."]
#[inline (always)] pub const fn bit_is_set (& self) -> bool { self . bit () } } impl < FI > core :: fmt :: Debug for BitReader < FI > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . bits , f) } }
#[doc = " Marker for register/field writers which can take any value of specified width"] pub struct Safe ;
#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] pub struct Unsafe ;
#[doc = " Marker for field writers are safe to write in specified inclusive range"] pub struct Range < const MIN : u64 , const MAX : u64 > ;
#[doc = " Marker for field writers are safe to write in specified inclusive range"] pub struct RangeFrom < const MIN : u64 > ;
#[doc = " Marker for field writers are safe to write in specified inclusive range"] pub struct RangeTo < const MAX : u64 > ;
#[doc = " Write field Proxy"] pub type FieldWriter < 'a , REG , const WI : u8 , FI = u8 , Safety = Unsafe > = raw :: FieldWriter < 'a , REG , WI , FI , Safety > ; impl < REG , const WI : u8 , FI , Safety > FieldWriter < '_ , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , {
#[doc = " Field width"] pub const WIDTH : u8 = WI ;
#[doc = " Field width"]
#[inline (always)] pub const fn width (& self) -> u8 { WI }
#[doc = " Field offset"]
#[inline (always)] pub const fn offset (& self) -> u8 { self . o } } impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , {
#[doc = " Writes raw bits to the field"]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline (always)] pub unsafe fn bits (self , value : FI :: Ux) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: mask :: < WI > () << self . o) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: mask :: < WI > ()) << self . o ; self . w } } impl < 'a , REG , const WI : u8 , FI > FieldWriter < 'a , REG , WI , FI , Safe > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , {
#[doc = " Writes raw bits to the field"]
#[inline (always)] pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , const MIN : u64 , const MAX : u64 > FieldWriter < 'a , REG , WI , FI , Range < MIN , MAX > > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , u64 : From < FI :: Ux > , {
#[doc = " Writes raw bits to the field"]
#[inline (always)] pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { { let value = u64 :: from (value) ; assert ! (value >= MIN && value <= MAX) ; } unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , const MIN : u64 > FieldWriter < 'a , REG , WI , FI , RangeFrom < MIN > > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , u64 : From < FI :: Ux > , {
#[doc = " Writes raw bits to the field"]
#[inline (always)] pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { { let value = u64 :: from (value) ; assert ! (value >= MIN) ; } unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , const MAX : u64 > FieldWriter < 'a , REG , WI , FI , RangeTo < MAX > > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , u64 : From < FI :: Ux > , {
#[doc = " Writes raw bits to the field"]
#[inline (always)] pub fn set (self , value : FI :: Ux) -> & 'a mut W < REG > { { let value = u64 :: from (value) ; assert ! (value <= MAX) ; } unsafe { self . bits (value) } } } impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : IsEnum , REG :: Ux : From < FI :: Ux > , {
#[doc = " Writes `variant` to the field"]
#[inline (always)] pub fn variant (self , variant : FI) -> & 'a mut W < REG > { unsafe { self . bits (FI :: Ux :: from (variant)) } } } macro_rules ! bit_proxy { ($ writer : ident , $ mwv : ident) => {
#[doc (hidden)] pub struct $ mwv ;
#[doc = " Bit-wise write field proxy"] pub type $ writer <'a , REG , FI = bool > = raw :: BitWriter <'a , REG , FI , $ mwv >; impl <'a , REG , FI > $ writer <'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI >, {
#[doc = " Field width"] pub const WIDTH : u8 = 1 ;
#[doc = " Field width"]
#[inline (always)] pub const fn width (& self) -> u8 { Self :: WIDTH }
#[doc = " Field offset"]
#[inline (always)] pub const fn offset (& self) -> u8 { self . o }
#[doc = " Writes bit to the field"]
#[inline (always)] pub fn bit (self , value : bool) -> &'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: ONE << self . o) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: ONE) << self . o ; self . w }
#[doc = " Writes `variant` to the field"]
#[inline (always)] pub fn variant (self , variant : FI) -> &'a mut W < REG > { self . bit (bool :: from (variant)) } } } ; } bit_proxy ! (BitWriter , BitM) ; bit_proxy ! (BitWriter1S , Bit1S) ; bit_proxy ! (BitWriter0C , Bit0C) ; bit_proxy ! (BitWriter1C , Bit1C) ; bit_proxy ! (BitWriter0S , Bit0S) ; bit_proxy ! (BitWriter1T , Bit1T) ; bit_proxy ! (BitWriter0T , Bit0T) ; impl < 'a , REG , FI > BitWriter < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , {
#[doc = " Sets the field bit"]
#[inline (always)] pub fn set_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: ONE << self . o ; self . w }
#[doc = " Clears the field bit"]
#[inline (always)] pub fn clear_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: ONE << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1S < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , {
#[doc = " Sets the field bit"]
#[inline (always)] pub fn set_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: ONE << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0C < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , {
#[doc = " Clears the field bit"]
#[inline (always)] pub fn clear_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: ONE << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1C < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , {
#[doc = "Clears the field bit by passing one"]
#[inline (always)] pub fn clear_bit_by_one (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: ONE << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0S < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , {
#[doc = "Sets the field bit by passing zero"]
#[inline (always)] pub fn set_bit_by_zero (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: ONE << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1T < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , {
#[doc = "Toggle the field bit by passing one"]
#[inline (always)] pub fn toggle_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: ONE << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0T < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , {
#[doc = "Toggle the field bit by passing zero"]
#[inline (always)] pub fn toggle_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: ONE << self . o) ; self . w } }
#[doc = " This structure provides volatile access to registers."]
#[repr (transparent)] pub struct Reg < REG : RegisterSpec > { register : vcell :: VolatileCell < REG :: Ux > , _marker : marker :: PhantomData < REG > , } unsafe impl < REG : RegisterSpec > Send for Reg < REG > where REG :: Ux : Send { } impl < REG : RegisterSpec > Reg < REG > {
#[doc = " Returns the underlying memory address of register."]
#[doc = ""]
#[doc = " ```ignore"]
#[doc = " let reg_ptr = periph.reg.as_ptr();"]
#[doc = " ```"]
#[inline (always)] pub fn as_ptr (& self) -> * mut REG :: Ux { self . register . as_ptr () } } impl < REG : Readable > Reg < REG > {
#[doc = " Reads the contents of a `Readable` register."]
#[doc = ""]
#[doc = " You can read the raw contents of a register by using `bits`:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.read().bits();"]
#[doc = " ```"]
#[doc = " or get the content of a particular field of a register:"]
#[doc = " ```ignore"]
#[doc = " let reader = periph.reg.read();"]
#[doc = " let bits = reader.field1().bits();"]
#[doc = " let flag = reader.field2().bit_is_set();"]
#[doc = " ```"]
#[inline (always)] pub fn read (& self) -> R < REG > { R { bits : self . register . get () , _reg : marker :: PhantomData , } } } impl < REG : Resettable + Writable > Reg < REG > {
#[doc = " Writes the reset value to `Writable` register."]
#[doc = ""]
#[doc = " Resets the register to its initial state."]
#[inline (always)] pub fn reset (& self) { self . register . set (REG :: RESET_VALUE) }
#[doc = " Writes bits to a `Writable` register."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| w"]
#[doc = "     .field1().bits(newfield1bits)"]
#[doc = "     .field2().set_bit()"]
#[doc = "     .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| {"]
#[doc = "     w.field1().bits(newfield1bits);"]
#[doc = "     w.field2().set_bit();"]
#[doc = "     w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[inline (always)] pub fn write < F > (& self , f : F) -> REG :: Ux where F : FnOnce (& mut W < REG >) -> & mut W < REG > , { let value = f (& mut W { bits : REG :: RESET_VALUE & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , }) . bits ; self . register . set (value) ; value }
#[doc = " Writes bits to a `Writable` register and produce a value."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| {"]
#[doc = "     w.field1().bits(newfield1bits)"]
#[doc = "         .field2().set_bit()"]
#[doc = "         .field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| {"]
#[doc = "     w.field1().bits(newfield1bits);"]
#[doc = "     w.field2().set_bit();"]
#[doc = "     w.field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[doc = ""]
#[doc = " Values can be returned from the closure:"]
#[doc = " ```ignore"]
#[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
#[doc = " ```"]
#[inline (always)] pub fn from_write < F , T > (& self , f : F) -> T where F : FnOnce (& mut W < REG >) -> T , { let mut writer = W { bits : REG :: RESET_VALUE & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , } ; let result = f (& mut writer) ; self . register . set (writer . bits) ; result } } impl < REG : Writable > Reg < REG > {
#[doc = " Writes 0 to a `Writable` register."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline (always)] pub unsafe fn write_with_zero < F > (& self , f : F) -> REG :: Ux where F : FnOnce (& mut W < REG >) -> & mut W < REG > , { let value = f (& mut W { bits : REG :: Ux :: ZERO , _reg : marker :: PhantomData , }) . bits ; self . register . set (value) ; value }
#[doc = " Writes 0 to a `Writable` register and produces a value."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline (always)] pub unsafe fn from_write_with_zero < F , T > (& self , f : F) -> T where F : FnOnce (& mut W < REG >) -> T , { let mut writer = W { bits : REG :: Ux :: ZERO , _reg : marker :: PhantomData , } ; let result = f (& mut writer) ; self . register . set (writer . bits) ; result } } impl < REG : Readable + Writable > Reg < REG > {
#[doc = " Modifies the contents of the register by reading and then writing it."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
#[doc = "    r.bits() | 3"]
#[doc = " ) });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| w"]
#[doc = "     .field1().bits(newfield1bits)"]
#[doc = "     .field2().set_bit()"]
#[doc = "     .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = "     w.field1().bits(newfield1bits);"]
#[doc = "     w.field2().set_bit();"]
#[doc = "     w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline (always)] pub fn modify < F > (& self , f : F) -> REG :: Ux where for < 'w > F : FnOnce (& R < REG > , & 'w mut W < REG >) -> & 'w mut W < REG > , { let bits = self . register . get () ; let value = f (& R { bits , _reg : marker :: PhantomData , } , & mut W { bits : bits & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , } ,) . bits ; self . register . set (value) ; value }
#[doc = " Modifies the contents of the register by reading and then writing it"]
#[doc = " and produces a value."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.modify(|r, w| {"]
#[doc = "     let new_bits = r.bits() | 3;"]
#[doc = "     unsafe {"]
#[doc = "         w.bits(new_bits);"]
#[doc = "     }"]
#[doc = ""]
#[doc = "     new_bits"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = "     w.field1().bits(newfield1bits)"]
#[doc = "         .field2().set_bit()"]
#[doc = "         .field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = "     w.field1().bits(newfield1bits);"]
#[doc = "     w.field2().set_bit();"]
#[doc = "     w.field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline (always)] pub fn from_modify < F , T > (& self , f : F) -> T where for < 'w > F : FnOnce (& R < REG > , & 'w mut W < REG >) -> T , { let bits = self . register . get () ; let mut writer = W { bits : bits & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , } ; let result = f (& R { bits , _reg : marker :: PhantomData , } , & mut writer ,) ; self . register . set (writer . bits) ; result } } impl < REG : Readable > core :: fmt :: Debug for crate :: generic :: Reg < REG > where R < REG > : core :: fmt :: Debug , { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } }
#[doc = r" Interrupt numbers, priority levels, and HART IDs."] pub mod interrupt { pub use riscv :: interrupt :: Interrupt as CoreInterrupt ; pub use riscv :: interrupt :: Exception ; pub use riscv :: { InterruptNumber , ExceptionNumber , PriorityNumber , HartIdNumber , interrupt :: { enable , disable , free , nested } } ; pub type Trap = riscv :: interrupt :: Trap < CoreInterrupt , Exception > ;
#[doc = r" Retrieves the cause of a trap in the current hart."]
#[doc = r""]
#[doc = r" If the raw cause is not a valid interrupt or exception for the target, it returns an error."]
#[inline] pub fn try_cause () -> riscv :: result :: Result < Trap > { riscv :: interrupt :: try_cause () }
#[doc = r" Retrieves the cause of a trap in the current hart (machine mode)."]
#[doc = r""]
#[doc = r" If the raw cause is not a valid interrupt or exception for the target, it panics."]
#[inline] pub fn cause () -> Trap { try_cause () . unwrap () }
#[doc = r" External interrupts. These interrupts are handled by the external peripherals."]
#[riscv :: pac_enum (unsafe ExternalInterruptNumber)]
#[derive (Debug , Clone , Copy , PartialEq , Eq)] pub enum ExternalInterrupt {
#[doc = "26 - TIMER_INT0"] TIMER_INT0 = 26 ,
#[doc = "27 - TIMER_INT1"] TIMER_INT1 = 27 ,
#[doc = "28 - TIMER_INT2"] TIMER_INT2 = 28 ,
#[doc = "29 - RTC_IRQ"] RTC_IRQ = 29 ,
#[doc = "31 - I2C0_INT"] I2C0_INT = 31 ,
#[doc = "32 - I2C1_INT"] I2C1_INT = 32 ,
#[doc = "33 - GPIO_INT0"] GPIO_INT0 = 33 ,
#[doc = "34 - GPIO_INT1"] GPIO_INT1 = 34 ,
#[doc = "35 - GPIO_INT2"] GPIO_INT2 = 35 ,
#[doc = "40 - COEX_WL_INT"] COEX_WL_INT = 40 ,
#[doc = "41 - COEX_BT_INT"] COEX_BT_INT = 41 ,
#[doc = "42 - COEX_WIFI_RESUME_INT"] COEX_WIFI_RESUME_INT = 42 ,
#[doc = "43 - SPI_INT"] SPI_INT = 43 ,
#[doc = "44 - WLPHY_INT"] WLPHY_INT = 44 ,
#[doc = "45 - WLMAC_INT"] WLMAC_INT = 45 ,
#[doc = "46 - BLE_INT"] BLE_INT = 46 ,
#[doc = "47 - SLE_INT"] SLE_INT = 47 ,
#[doc = "48 - TSENSOR_INT"] TSENSOR_INT = 48 ,
#[doc = "49 - PMU_CMU_ERR_INT"] PMU_CMU_ERR_INT = 49 ,
#[doc = "50 - DIAG_INT"] DIAG_INT = 50 ,
#[doc = "51 - I2S_INT"] I2S_INT = 51 ,
#[doc = "52 - QSPI_INT"] QSPI_INT = 52 ,
#[doc = "53 - UART0_INT"] UART0_INT = 53 ,
#[doc = "54 - UART1_INT"] UART1_INT = 54 ,
#[doc = "55 - UART2_INT"] UART2_INT = 55 ,
#[doc = "56 - PWM_ABNOR_INT"] PWM_ABNOR_INT = 56 ,
#[doc = "57 - PWM_CFG_INT"] PWM_CFG_INT = 57 ,
#[doc = "58 - SFC_INT"] SFC_INT = 58 ,
#[doc = "59 - DMA_INT"] DMA_INT = 59 ,
#[doc = "60 - TIMER_ABNOR_INT"] TIMER_ABNOR_INT = 60 ,
#[doc = "61 - I2S_TX_INT"] I2S_TX_INT = 61 ,
#[doc = "62 - I2S_RX_INT"] I2S_RX_INT = 62 ,
#[doc = "63 - PKE_REE_INT"] PKE_REE_INT = 63 ,
#[doc = "64 - SPACC_REE_INT"] SPACC_REE_INT = 64 ,
#[doc = "65 - RKP_REE_INT"] RKP_REE_INT = 65 ,
#[doc = "66 - KLAD_REE_INT"] KLAD_REE_INT = 66 ,
#[doc = "69 - MAC_MONITOR_INT"] MAC_MONITOR_INT = 69 ,
#[doc = "70 - MEM_MONITOR_INT"] MEM_MONITOR_INT = 70 ,
#[doc = "71 - TCM_MONITOR_INT"] TCM_MONITOR_INT = 71 ,
#[doc = "72 - LSADC_INTR"] LSADC_INTR = 72 , } }
#[doc = "System Control 1 - Interrupt Controller"] pub type SysCtl1 = crate :: Periph < sys_ctl1 :: RegisterBlock , 0x4400_0000 > ; impl core :: fmt :: Debug for SysCtl1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("SysCtl1") . finish () } }
#[doc = "System Control 1 - Interrupt Controller"] pub mod sys_ctl1 {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x40] , nmi_int : NmiInt , _reserved1 : [u8 ; 0x010c] , soft_int_en : SoftIntEn , soft_int_set : SoftIntSet , soft_int_clr : SoftIntClr , soft_int_sts : SoftIntSts , } impl RegisterBlock {
#[doc = "0x40 - WDT interrupt query and NMI interrupt configuration register"]
#[inline (always)] pub const fn nmi_int (& self) -> & NmiInt { & self . nmi_int }
#[doc = "0x150 - CPU soft interrupt enable register"]
#[inline (always)] pub const fn soft_int_en (& self) -> & SoftIntEn { & self . soft_int_en }
#[doc = "0x154 - CPU soft interrupt set register (self-clearing)"]
#[inline (always)] pub const fn soft_int_set (& self) -> & SoftIntSet { & self . soft_int_set }
#[doc = "0x158 - CPU soft interrupt clear register (self-clearing)"]
#[inline (always)] pub const fn soft_int_clr (& self) -> & SoftIntClr { & self . soft_int_clr }
#[doc = "0x15c - CPU soft interrupt status register"]
#[inline (always)] pub const fn soft_int_sts (& self) -> & SoftIntSts { & self . soft_int_sts } }
#[doc = "NMI_INT (rw) register accessor: WDT interrupt query and NMI interrupt configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmi_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi_int`] module"]
#[doc (alias = "NMI_INT")] pub type NmiInt = crate :: Reg < nmi_int :: NmiIntSpec > ;
#[doc = "WDT interrupt query and NMI interrupt configuration register"] pub mod nmi_int {
#[doc = "Register `NMI_INT` reader"] pub type R = crate :: R < NmiIntSpec > ;
#[doc = "Register `NMI_INT` writer"] pub type W = crate :: W < NmiIntSpec > ;
#[doc = "Field `tee_nmi_int` reader - Software NMI interrupt configuration. 0: pull low CPU NMI soft interrupt; 1: pull high CPU NMI soft interrupt"] pub type TeeNmiIntR = crate :: BitReader ;
#[doc = "Field `tee_nmi_int` writer - Software NMI interrupt configuration. 0: pull low CPU NMI soft interrupt; 1: pull high CPU NMI soft interrupt"] pub type TeeNmiIntW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `wdt_int` reader - Watchdog interrupt query. 0: WDT interrupt invalid; 1: WDT interrupt valid"] pub type WdtIntR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Software NMI interrupt configuration. 0: pull low CPU NMI soft interrupt; 1: pull high CPU NMI soft interrupt"]
#[inline (always)] pub fn tee_nmi_int (& self) -> TeeNmiIntR { TeeNmiIntR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Watchdog interrupt query. 0: WDT interrupt invalid; 1: WDT interrupt valid"]
#[inline (always)] pub fn wdt_int (& self) -> WdtIntR { WdtIntR :: new (((self . bits >> 1) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Software NMI interrupt configuration. 0: pull low CPU NMI soft interrupt; 1: pull high CPU NMI soft interrupt"]
#[inline (always)] pub fn tee_nmi_int (& mut self) -> TeeNmiIntW < '_ , NmiIntSpec > { TeeNmiIntW :: new (self , 0) } }
#[doc = "WDT interrupt query and NMI interrupt configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmi_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NmiIntSpec ; impl crate :: RegisterSpec for NmiIntSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`nmi_int::R`](R) reader structure"] impl crate :: Readable for NmiIntSpec { }
#[doc = "`write(|w| ..)` method takes [`nmi_int::W`](W) writer structure"] impl crate :: Writable for NmiIntSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets NMI_INT to value 0"] impl crate :: Resettable for NmiIntSpec { } }
#[doc = "SOFT_INT_EN (rw) register accessor: CPU soft interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_int_en`] module"]
#[doc (alias = "SOFT_INT_EN")] pub type SoftIntEn = crate :: Reg < soft_int_en :: SoftIntEnSpec > ;
#[doc = "CPU soft interrupt enable register"] pub mod soft_int_en {
#[doc = "Register `SOFT_INT_EN` reader"] pub type R = crate :: R < SoftIntEnSpec > ;
#[doc = "Register `SOFT_INT_EN` writer"] pub type W = crate :: W < SoftIntEnSpec > ;
#[doc = "Field `soft_int0_en` reader - CPU soft interrupt 0 enable. 0: disabled; 1: enabled"] pub type SoftInt0EnR = crate :: BitReader ;
#[doc = "Field `soft_int0_en` writer - CPU soft interrupt 0 enable. 0: disabled; 1: enabled"] pub type SoftInt0EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_int1_en` reader - CPU soft interrupt 1 enable. 0: disabled; 1: enabled"] pub type SoftInt1EnR = crate :: BitReader ;
#[doc = "Field `soft_int1_en` writer - CPU soft interrupt 1 enable. 0: disabled; 1: enabled"] pub type SoftInt1EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_int2_en` reader - CPU soft interrupt 2 enable. 0: disabled; 1: enabled"] pub type SoftInt2EnR = crate :: BitReader ;
#[doc = "Field `soft_int2_en` writer - CPU soft interrupt 2 enable. 0: disabled; 1: enabled"] pub type SoftInt2EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_int3_en` reader - CPU soft interrupt 3 enable. 0: disabled; 1: enabled"] pub type SoftInt3EnR = crate :: BitReader ;
#[doc = "Field `soft_int3_en` writer - CPU soft interrupt 3 enable. 0: disabled; 1: enabled"] pub type SoftInt3EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - CPU soft interrupt 0 enable. 0: disabled; 1: enabled"]
#[inline (always)] pub fn soft_int0_en (& self) -> SoftInt0EnR { SoftInt0EnR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - CPU soft interrupt 1 enable. 0: disabled; 1: enabled"]
#[inline (always)] pub fn soft_int1_en (& self) -> SoftInt1EnR { SoftInt1EnR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - CPU soft interrupt 2 enable. 0: disabled; 1: enabled"]
#[inline (always)] pub fn soft_int2_en (& self) -> SoftInt2EnR { SoftInt2EnR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - CPU soft interrupt 3 enable. 0: disabled; 1: enabled"]
#[inline (always)] pub fn soft_int3_en (& self) -> SoftInt3EnR { SoftInt3EnR :: new (((self . bits >> 3) & 1) != 0) } } impl W {
#[doc = "Bit 0 - CPU soft interrupt 0 enable. 0: disabled; 1: enabled"]
#[inline (always)] pub fn soft_int0_en (& mut self) -> SoftInt0EnW < '_ , SoftIntEnSpec > { SoftInt0EnW :: new (self , 0) }
#[doc = "Bit 1 - CPU soft interrupt 1 enable. 0: disabled; 1: enabled"]
#[inline (always)] pub fn soft_int1_en (& mut self) -> SoftInt1EnW < '_ , SoftIntEnSpec > { SoftInt1EnW :: new (self , 1) }
#[doc = "Bit 2 - CPU soft interrupt 2 enable. 0: disabled; 1: enabled"]
#[inline (always)] pub fn soft_int2_en (& mut self) -> SoftInt2EnW < '_ , SoftIntEnSpec > { SoftInt2EnW :: new (self , 2) }
#[doc = "Bit 3 - CPU soft interrupt 3 enable. 0: disabled; 1: enabled"]
#[inline (always)] pub fn soft_int3_en (& mut self) -> SoftInt3EnW < '_ , SoftIntEnSpec > { SoftInt3EnW :: new (self , 3) } }
#[doc = "CPU soft interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SoftIntEnSpec ; impl crate :: RegisterSpec for SoftIntEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`soft_int_en::R`](R) reader structure"] impl crate :: Readable for SoftIntEnSpec { }
#[doc = "`write(|w| ..)` method takes [`soft_int_en::W`](W) writer structure"] impl crate :: Writable for SoftIntEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SOFT_INT_EN to value 0"] impl crate :: Resettable for SoftIntEnSpec { } }
#[doc = "SOFT_INT_SET (rw) register accessor: CPU soft interrupt set register (self-clearing)\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_int_set`] module"]
#[doc (alias = "SOFT_INT_SET")] pub type SoftIntSet = crate :: Reg < soft_int_set :: SoftIntSetSpec > ;
#[doc = "CPU soft interrupt set register (self-clearing)"] pub mod soft_int_set {
#[doc = "Register `SOFT_INT_SET` reader"] pub type R = crate :: R < SoftIntSetSpec > ;
#[doc = "Register `SOFT_INT_SET` writer"] pub type W = crate :: W < SoftIntSetSpec > ;
#[doc = "Field `soft_int0_set` writer - CPU soft interrupt 0 set. 0: no effect; 1: set effective"] pub type SoftInt0SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_int1_set` writer - CPU soft interrupt 1 set. 0: no effect; 1: set effective"] pub type SoftInt1SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_int2_set` writer - CPU soft interrupt 2 set. 0: no effect; 1: set effective"] pub type SoftInt2SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_int3_set` writer - CPU soft interrupt 3 set. 0: no effect; 1: set effective"] pub type SoftInt3SetW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - CPU soft interrupt 0 set. 0: no effect; 1: set effective"]
#[inline (always)] pub fn soft_int0_set (& mut self) -> SoftInt0SetW < '_ , SoftIntSetSpec > { SoftInt0SetW :: new (self , 0) }
#[doc = "Bit 1 - CPU soft interrupt 1 set. 0: no effect; 1: set effective"]
#[inline (always)] pub fn soft_int1_set (& mut self) -> SoftInt1SetW < '_ , SoftIntSetSpec > { SoftInt1SetW :: new (self , 1) }
#[doc = "Bit 2 - CPU soft interrupt 2 set. 0: no effect; 1: set effective"]
#[inline (always)] pub fn soft_int2_set (& mut self) -> SoftInt2SetW < '_ , SoftIntSetSpec > { SoftInt2SetW :: new (self , 2) }
#[doc = "Bit 3 - CPU soft interrupt 3 set. 0: no effect; 1: set effective"]
#[inline (always)] pub fn soft_int3_set (& mut self) -> SoftInt3SetW < '_ , SoftIntSetSpec > { SoftInt3SetW :: new (self , 3) } }
#[doc = "CPU soft interrupt set register (self-clearing)\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SoftIntSetSpec ; impl crate :: RegisterSpec for SoftIntSetSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`soft_int_set::R`](R) reader structure"] impl crate :: Readable for SoftIntSetSpec { }
#[doc = "`write(|w| ..)` method takes [`soft_int_set::W`](W) writer structure"] impl crate :: Writable for SoftIntSetSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SOFT_INT_SET to value 0"] impl crate :: Resettable for SoftIntSetSpec { } }
#[doc = "SOFT_INT_CLR (rw) register accessor: CPU soft interrupt clear register (self-clearing)\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_int_clr`] module"]
#[doc (alias = "SOFT_INT_CLR")] pub type SoftIntClr = crate :: Reg < soft_int_clr :: SoftIntClrSpec > ;
#[doc = "CPU soft interrupt clear register (self-clearing)"] pub mod soft_int_clr {
#[doc = "Register `SOFT_INT_CLR` reader"] pub type R = crate :: R < SoftIntClrSpec > ;
#[doc = "Register `SOFT_INT_CLR` writer"] pub type W = crate :: W < SoftIntClrSpec > ;
#[doc = "Field `soft_int0_clr` writer - CPU soft interrupt 0 clear. 0: no effect; 1: clear effective"] pub type SoftInt0ClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_int1_clr` writer - CPU soft interrupt 1 clear. 0: no effect; 1: clear effective"] pub type SoftInt1ClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_int2_clr` writer - CPU soft interrupt 2 clear. 0: no effect; 1: clear effective"] pub type SoftInt2ClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_int3_clr` writer - CPU soft interrupt 3 clear. 0: no effect; 1: clear effective"] pub type SoftInt3ClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - CPU soft interrupt 0 clear. 0: no effect; 1: clear effective"]
#[inline (always)] pub fn soft_int0_clr (& mut self) -> SoftInt0ClrW < '_ , SoftIntClrSpec > { SoftInt0ClrW :: new (self , 0) }
#[doc = "Bit 1 - CPU soft interrupt 1 clear. 0: no effect; 1: clear effective"]
#[inline (always)] pub fn soft_int1_clr (& mut self) -> SoftInt1ClrW < '_ , SoftIntClrSpec > { SoftInt1ClrW :: new (self , 1) }
#[doc = "Bit 2 - CPU soft interrupt 2 clear. 0: no effect; 1: clear effective"]
#[inline (always)] pub fn soft_int2_clr (& mut self) -> SoftInt2ClrW < '_ , SoftIntClrSpec > { SoftInt2ClrW :: new (self , 2) }
#[doc = "Bit 3 - CPU soft interrupt 3 clear. 0: no effect; 1: clear effective"]
#[inline (always)] pub fn soft_int3_clr (& mut self) -> SoftInt3ClrW < '_ , SoftIntClrSpec > { SoftInt3ClrW :: new (self , 3) } }
#[doc = "CPU soft interrupt clear register (self-clearing)\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SoftIntClrSpec ; impl crate :: RegisterSpec for SoftIntClrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`soft_int_clr::R`](R) reader structure"] impl crate :: Readable for SoftIntClrSpec { }
#[doc = "`write(|w| ..)` method takes [`soft_int_clr::W`](W) writer structure"] impl crate :: Writable for SoftIntClrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SOFT_INT_CLR to value 0"] impl crate :: Resettable for SoftIntClrSpec { } }
#[doc = "SOFT_INT_STS (rw) register accessor: CPU soft interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_int_sts`] module"]
#[doc (alias = "SOFT_INT_STS")] pub type SoftIntSts = crate :: Reg < soft_int_sts :: SoftIntStsSpec > ;
#[doc = "CPU soft interrupt status register"] pub mod soft_int_sts {
#[doc = "Register `SOFT_INT_STS` reader"] pub type R = crate :: R < SoftIntStsSpec > ;
#[doc = "Register `SOFT_INT_STS` writer"] pub type W = crate :: W < SoftIntStsSpec > ;
#[doc = "Field `soft_int0_sts` reader - CPU soft interrupt 0 status. 0: no interrupt; 1: interrupt active"] pub type SoftInt0StsR = crate :: BitReader ;
#[doc = "Field `soft_int1_sts` reader - CPU soft interrupt 1 status. 0: no interrupt; 1: interrupt active"] pub type SoftInt1StsR = crate :: BitReader ;
#[doc = "Field `soft_int2_sts` reader - CPU soft interrupt 2 status. 0: no interrupt; 1: interrupt active"] pub type SoftInt2StsR = crate :: BitReader ;
#[doc = "Field `soft_int3_sts` reader - CPU soft interrupt 3 status. 0: no interrupt; 1: interrupt active"] pub type SoftInt3StsR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - CPU soft interrupt 0 status. 0: no interrupt; 1: interrupt active"]
#[inline (always)] pub fn soft_int0_sts (& self) -> SoftInt0StsR { SoftInt0StsR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - CPU soft interrupt 1 status. 0: no interrupt; 1: interrupt active"]
#[inline (always)] pub fn soft_int1_sts (& self) -> SoftInt1StsR { SoftInt1StsR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - CPU soft interrupt 2 status. 0: no interrupt; 1: interrupt active"]
#[inline (always)] pub fn soft_int2_sts (& self) -> SoftInt2StsR { SoftInt2StsR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - CPU soft interrupt 3 status. 0: no interrupt; 1: interrupt active"]
#[inline (always)] pub fn soft_int3_sts (& self) -> SoftInt3StsR { SoftInt3StsR :: new (((self . bits >> 3) & 1) != 0) } } impl W { }
#[doc = "CPU soft interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_int_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_int_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SoftIntStsSpec ; impl crate :: RegisterSpec for SoftIntStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`soft_int_sts::R`](R) reader structure"] impl crate :: Readable for SoftIntStsSpec { }
#[doc = "`write(|w| ..)` method takes [`soft_int_sts::W`](W) writer structure"] impl crate :: Writable for SoftIntStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SOFT_INT_STS to value 0"] impl crate :: Resettable for SoftIntStsSpec { } } }
#[doc = "IO multiplexing and pad control"] pub type IoConfig = crate :: Periph < io_config :: RegisterBlock , 0x4400_d000 > ; impl core :: fmt :: Debug for IoConfig { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("IoConfig") . finish () } }
#[doc = "IO multiplexing and pad control"] pub mod io_config {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { gpio_00_sel : Gpio00Sel , gpio_01_sel : Gpio01Sel , gpio_02_sel : Gpio02Sel , gpio_03_sel : Gpio03Sel , gpio_04_sel : Gpio04Sel , gpio_05_sel : Gpio05Sel , gpio_06_sel : Gpio06Sel , gpio_07_sel : Gpio07Sel , gpio_08_sel : Gpio08Sel , gpio_09_sel : Gpio09Sel , gpio_10_sel : Gpio10Sel , gpio_11_sel : Gpio11Sel , gpio_12_sel : Gpio12Sel , gpio_13_sel : Gpio13Sel , gpio_14_sel : Gpio14Sel , uart1_txd_sel : Uart1TxdSel , uart1_rxd_sel : Uart1RxdSel , uart0_txd_sel : Uart0TxdSel , uart0_rxd_sel : Uart0RxdSel , _reserved19 : [u8 ; 0x07b4] , pad_gpio_00_ctrl : PadGpio00Ctrl , pad_gpio_01_ctrl : PadGpio01Ctrl , pad_gpio_02_ctrl : PadGpio02Ctrl , pad_gpio_03_ctrl : PadGpio03Ctrl , pad_gpio_04_ctrl : PadGpio04Ctrl , pad_gpio_05_ctrl : PadGpio05Ctrl , pad_gpio_06_ctrl : PadGpio06Ctrl , pad_gpio_07_ctrl : PadGpio07Ctrl , pad_gpio_08_ctrl : PadGpio08Ctrl , pad_gpio_09_ctrl : PadGpio09Ctrl , pad_gpio_10_ctrl : PadGpio10Ctrl , pad_gpio_11_ctrl : PadGpio11Ctrl , pad_gpio_12_ctrl : PadGpio12Ctrl , pad_gpio_13_ctrl : PadGpio13Ctrl , pad_gpio_14_ctrl : PadGpio14Ctrl , pad_uart1_txd_ctrl : PadUart1TxdCtrl , pad_uart1_rxd_ctrl : PadUart1RxdCtrl , pad_uart0_txd_ctrl : PadUart0TxdCtrl , pad_uart0_rxd_ctrl : PadUart0RxdCtrl , _reserved38 : [u8 ; 0x1c] , pad_sfc_clk_ctrl : PadSfcClkCtrl , pad_sfc_csn_ctrl : PadSfcCsnCtrl , pad_sfc_io0_ctrl : PadSfcIo0Ctrl , pad_sfc_io1_ctrl : PadSfcIo1Ctrl , pad_sfc_io2_ctrl : PadSfcIo2Ctrl , pad_sfc_io3_ctrl : PadSfcIo3Ctrl , } impl RegisterBlock {
#[doc = "0x00 - GPIO_00 pin mux select"]
#[inline (always)] pub const fn gpio_00_sel (& self) -> & Gpio00Sel { & self . gpio_00_sel }
#[doc = "0x04 - GPIO_01 pin mux select"]
#[inline (always)] pub const fn gpio_01_sel (& self) -> & Gpio01Sel { & self . gpio_01_sel }
#[doc = "0x08 - GPIO_02 pin mux select"]
#[inline (always)] pub const fn gpio_02_sel (& self) -> & Gpio02Sel { & self . gpio_02_sel }
#[doc = "0x0c - GPIO_03 pin mux select"]
#[inline (always)] pub const fn gpio_03_sel (& self) -> & Gpio03Sel { & self . gpio_03_sel }
#[doc = "0x10 - GPIO_04 pin mux select"]
#[inline (always)] pub const fn gpio_04_sel (& self) -> & Gpio04Sel { & self . gpio_04_sel }
#[doc = "0x14 - GPIO_05 pin mux select"]
#[inline (always)] pub const fn gpio_05_sel (& self) -> & Gpio05Sel { & self . gpio_05_sel }
#[doc = "0x18 - GPIO_06 pin mux select"]
#[inline (always)] pub const fn gpio_06_sel (& self) -> & Gpio06Sel { & self . gpio_06_sel }
#[doc = "0x1c - GPIO_07 pin mux select"]
#[inline (always)] pub const fn gpio_07_sel (& self) -> & Gpio07Sel { & self . gpio_07_sel }
#[doc = "0x20 - GPIO_08 pin mux select"]
#[inline (always)] pub const fn gpio_08_sel (& self) -> & Gpio08Sel { & self . gpio_08_sel }
#[doc = "0x24 - GPIO_09 pin mux select"]
#[inline (always)] pub const fn gpio_09_sel (& self) -> & Gpio09Sel { & self . gpio_09_sel }
#[doc = "0x28 - GPIO_10 pin mux select"]
#[inline (always)] pub const fn gpio_10_sel (& self) -> & Gpio10Sel { & self . gpio_10_sel }
#[doc = "0x2c - GPIO_11 pin mux select"]
#[inline (always)] pub const fn gpio_11_sel (& self) -> & Gpio11Sel { & self . gpio_11_sel }
#[doc = "0x30 - GPIO_12 pin mux select"]
#[inline (always)] pub const fn gpio_12_sel (& self) -> & Gpio12Sel { & self . gpio_12_sel }
#[doc = "0x34 - GPIO_13 pin mux select"]
#[inline (always)] pub const fn gpio_13_sel (& self) -> & Gpio13Sel { & self . gpio_13_sel }
#[doc = "0x38 - GPIO_14 pin mux select"]
#[inline (always)] pub const fn gpio_14_sel (& self) -> & Gpio14Sel { & self . gpio_14_sel }
#[doc = "0x3c - UART1_TXD pin mux select"]
#[inline (always)] pub const fn uart1_txd_sel (& self) -> & Uart1TxdSel { & self . uart1_txd_sel }
#[doc = "0x40 - UART1_RXD pin mux select"]
#[inline (always)] pub const fn uart1_rxd_sel (& self) -> & Uart1RxdSel { & self . uart1_rxd_sel }
#[doc = "0x44 - UART0_TXD pin mux select"]
#[inline (always)] pub const fn uart0_txd_sel (& self) -> & Uart0TxdSel { & self . uart0_txd_sel }
#[doc = "0x48 - UART0_RXD pin mux select"]
#[inline (always)] pub const fn uart0_rxd_sel (& self) -> & Uart0RxdSel { & self . uart0_rxd_sel }
#[doc = "0x800 - GPIO_00 pad control register"]
#[inline (always)] pub const fn pad_gpio_00_ctrl (& self) -> & PadGpio00Ctrl { & self . pad_gpio_00_ctrl }
#[doc = "0x804 - GPIO_01 pad control register"]
#[inline (always)] pub const fn pad_gpio_01_ctrl (& self) -> & PadGpio01Ctrl { & self . pad_gpio_01_ctrl }
#[doc = "0x808 - GPIO_02 pad control register"]
#[inline (always)] pub const fn pad_gpio_02_ctrl (& self) -> & PadGpio02Ctrl { & self . pad_gpio_02_ctrl }
#[doc = "0x80c - GPIO_03 pad control register"]
#[inline (always)] pub const fn pad_gpio_03_ctrl (& self) -> & PadGpio03Ctrl { & self . pad_gpio_03_ctrl }
#[doc = "0x810 - GPIO_04 pad control register"]
#[inline (always)] pub const fn pad_gpio_04_ctrl (& self) -> & PadGpio04Ctrl { & self . pad_gpio_04_ctrl }
#[doc = "0x814 - GPIO_05 pad control register"]
#[inline (always)] pub const fn pad_gpio_05_ctrl (& self) -> & PadGpio05Ctrl { & self . pad_gpio_05_ctrl }
#[doc = "0x818 - GPIO_06 pad control register"]
#[inline (always)] pub const fn pad_gpio_06_ctrl (& self) -> & PadGpio06Ctrl { & self . pad_gpio_06_ctrl }
#[doc = "0x81c - GPIO_07 pad control register"]
#[inline (always)] pub const fn pad_gpio_07_ctrl (& self) -> & PadGpio07Ctrl { & self . pad_gpio_07_ctrl }
#[doc = "0x820 - GPIO_08 pad control register"]
#[inline (always)] pub const fn pad_gpio_08_ctrl (& self) -> & PadGpio08Ctrl { & self . pad_gpio_08_ctrl }
#[doc = "0x824 - GPIO_09 pad control register"]
#[inline (always)] pub const fn pad_gpio_09_ctrl (& self) -> & PadGpio09Ctrl { & self . pad_gpio_09_ctrl }
#[doc = "0x828 - GPIO_10 pad control register"]
#[inline (always)] pub const fn pad_gpio_10_ctrl (& self) -> & PadGpio10Ctrl { & self . pad_gpio_10_ctrl }
#[doc = "0x82c - GPIO_11 pad control register"]
#[inline (always)] pub const fn pad_gpio_11_ctrl (& self) -> & PadGpio11Ctrl { & self . pad_gpio_11_ctrl }
#[doc = "0x830 - GPIO_12 pad control register"]
#[inline (always)] pub const fn pad_gpio_12_ctrl (& self) -> & PadGpio12Ctrl { & self . pad_gpio_12_ctrl }
#[doc = "0x834 - GPIO_13 pad control register"]
#[inline (always)] pub const fn pad_gpio_13_ctrl (& self) -> & PadGpio13Ctrl { & self . pad_gpio_13_ctrl }
#[doc = "0x838 - GPIO_14 pad control register"]
#[inline (always)] pub const fn pad_gpio_14_ctrl (& self) -> & PadGpio14Ctrl { & self . pad_gpio_14_ctrl }
#[doc = "0x83c - UART1_TXD pad control register"]
#[inline (always)] pub const fn pad_uart1_txd_ctrl (& self) -> & PadUart1TxdCtrl { & self . pad_uart1_txd_ctrl }
#[doc = "0x840 - UART1_RXD pad control register"]
#[inline (always)] pub const fn pad_uart1_rxd_ctrl (& self) -> & PadUart1RxdCtrl { & self . pad_uart1_rxd_ctrl }
#[doc = "0x844 - UART0_TXD pad control register"]
#[inline (always)] pub const fn pad_uart0_txd_ctrl (& self) -> & PadUart0TxdCtrl { & self . pad_uart0_txd_ctrl }
#[doc = "0x848 - UART0_RXD pad control register"]
#[inline (always)] pub const fn pad_uart0_rxd_ctrl (& self) -> & PadUart0RxdCtrl { & self . pad_uart0_rxd_ctrl }
#[doc = "0x868 - SFC_CLK pad control register"]
#[inline (always)] pub const fn pad_sfc_clk_ctrl (& self) -> & PadSfcClkCtrl { & self . pad_sfc_clk_ctrl }
#[doc = "0x86c - SFC_CSN pad control register"]
#[inline (always)] pub const fn pad_sfc_csn_ctrl (& self) -> & PadSfcCsnCtrl { & self . pad_sfc_csn_ctrl }
#[doc = "0x870 - SFC_IO0 pad control register"]
#[inline (always)] pub const fn pad_sfc_io0_ctrl (& self) -> & PadSfcIo0Ctrl { & self . pad_sfc_io0_ctrl }
#[doc = "0x874 - SFC_IO1 pad control register"]
#[inline (always)] pub const fn pad_sfc_io1_ctrl (& self) -> & PadSfcIo1Ctrl { & self . pad_sfc_io1_ctrl }
#[doc = "0x878 - SFC_IO2 pad control register"]
#[inline (always)] pub const fn pad_sfc_io2_ctrl (& self) -> & PadSfcIo2Ctrl { & self . pad_sfc_io2_ctrl }
#[doc = "0x87c - SFC_IO3 pad control register"]
#[inline (always)] pub const fn pad_sfc_io3_ctrl (& self) -> & PadSfcIo3Ctrl { & self . pad_sfc_io3_ctrl } }
#[doc = "GPIO_00_SEL (rw) register accessor: GPIO_00 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_00_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_00_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_00_sel`] module"]
#[doc (alias = "GPIO_00_SEL")] pub type Gpio00Sel = crate :: Reg < gpio_00_sel :: Gpio00SelSpec > ;
#[doc = "GPIO_00 pin mux select"] pub mod gpio_00_sel {
#[doc = "Register `GPIO_00_SEL` reader"] pub type R = crate :: R < Gpio00SelSpec > ;
#[doc = "Register `GPIO_00_SEL` writer"] pub type W = crate :: W < Gpio00SelSpec > ;
#[doc = "Field `gpio_00_sel` reader - GPIO_00 pin mux: 0:GPIO_00; 1:PWM0; 2:DIAG\\[0\\]; 3:SPI1_CSN; 4:JTAG_TDI"] pub type Gpio00SelR = crate :: FieldReader ;
#[doc = "Field `gpio_00_sel` writer - GPIO_00 pin mux: 0:GPIO_00; 1:PWM0; 2:DIAG\\[0\\]; 3:SPI1_CSN; 4:JTAG_TDI"] pub type Gpio00SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_00 pin mux: 0:GPIO_00; 1:PWM0; 2:DIAG\\[0\\]; 3:SPI1_CSN; 4:JTAG_TDI"]
#[inline (always)] pub fn gpio_00_sel (& self) -> Gpio00SelR { Gpio00SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_00 pin mux: 0:GPIO_00; 1:PWM0; 2:DIAG\\[0\\]; 3:SPI1_CSN; 4:JTAG_TDI"]
#[inline (always)] pub fn gpio_00_sel (& mut self) -> Gpio00SelW < '_ , Gpio00SelSpec > { Gpio00SelW :: new (self , 0) } }
#[doc = "GPIO_00 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_00_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_00_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio00SelSpec ; impl crate :: RegisterSpec for Gpio00SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_00_sel::R`](R) reader structure"] impl crate :: Readable for Gpio00SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_00_sel::W`](W) writer structure"] impl crate :: Writable for Gpio00SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_00_SEL to value 0"] impl crate :: Resettable for Gpio00SelSpec { } }
#[doc = "GPIO_01_SEL (rw) register accessor: GPIO_01 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_01_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_01_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_01_sel`] module"]
#[doc (alias = "GPIO_01_SEL")] pub type Gpio01Sel = crate :: Reg < gpio_01_sel :: Gpio01SelSpec > ;
#[doc = "GPIO_01 pin mux select"] pub mod gpio_01_sel {
#[doc = "Register `GPIO_01_SEL` reader"] pub type R = crate :: R < Gpio01SelSpec > ;
#[doc = "Register `GPIO_01_SEL` writer"] pub type W = crate :: W < Gpio01SelSpec > ;
#[doc = "Field `gpio_01_sel` reader - GPIO_01 pin mux: 0:GPIO_01; 1:PWM1; 2:DIAG\\[1\\]; 3:SPI1_IO0; 4:JTAG_MODE; 5:BT_SAMPLE"] pub type Gpio01SelR = crate :: FieldReader ;
#[doc = "Field `gpio_01_sel` writer - GPIO_01 pin mux: 0:GPIO_01; 1:PWM1; 2:DIAG\\[1\\]; 3:SPI1_IO0; 4:JTAG_MODE; 5:BT_SAMPLE"] pub type Gpio01SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_01 pin mux: 0:GPIO_01; 1:PWM1; 2:DIAG\\[1\\]; 3:SPI1_IO0; 4:JTAG_MODE; 5:BT_SAMPLE"]
#[inline (always)] pub fn gpio_01_sel (& self) -> Gpio01SelR { Gpio01SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_01 pin mux: 0:GPIO_01; 1:PWM1; 2:DIAG\\[1\\]; 3:SPI1_IO0; 4:JTAG_MODE; 5:BT_SAMPLE"]
#[inline (always)] pub fn gpio_01_sel (& mut self) -> Gpio01SelW < '_ , Gpio01SelSpec > { Gpio01SelW :: new (self , 0) } }
#[doc = "GPIO_01 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_01_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_01_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio01SelSpec ; impl crate :: RegisterSpec for Gpio01SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_01_sel::R`](R) reader structure"] impl crate :: Readable for Gpio01SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_01_sel::W`](W) writer structure"] impl crate :: Writable for Gpio01SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_01_SEL to value 0"] impl crate :: Resettable for Gpio01SelSpec { } }
#[doc = "GPIO_02_SEL (rw) register accessor: GPIO_02 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_02_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_02_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_02_sel`] module"]
#[doc (alias = "GPIO_02_SEL")] pub type Gpio02Sel = crate :: Reg < gpio_02_sel :: Gpio02SelSpec > ;
#[doc = "GPIO_02 pin mux select"] pub mod gpio_02_sel {
#[doc = "Register `GPIO_02_SEL` reader"] pub type R = crate :: R < Gpio02SelSpec > ;
#[doc = "Register `GPIO_02_SEL` writer"] pub type W = crate :: W < Gpio02SelSpec > ;
#[doc = "Field `gpio_02_sel` reader - GPIO_02 pin mux: 0:GPIO_02; 1:PWM2; 2:DIAG\\[2\\]; 3:SPI1_IO3; 4:WIFI_TSF_SYNC; 5:WL_GLP_SYNC_PULSE; 6:BSLE_GLP_SYNC_PULSE"] pub type Gpio02SelR = crate :: FieldReader ;
#[doc = "Field `gpio_02_sel` writer - GPIO_02 pin mux: 0:GPIO_02; 1:PWM2; 2:DIAG\\[2\\]; 3:SPI1_IO3; 4:WIFI_TSF_SYNC; 5:WL_GLP_SYNC_PULSE; 6:BSLE_GLP_SYNC_PULSE"] pub type Gpio02SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_02 pin mux: 0:GPIO_02; 1:PWM2; 2:DIAG\\[2\\]; 3:SPI1_IO3; 4:WIFI_TSF_SYNC; 5:WL_GLP_SYNC_PULSE; 6:BSLE_GLP_SYNC_PULSE"]
#[inline (always)] pub fn gpio_02_sel (& self) -> Gpio02SelR { Gpio02SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_02 pin mux: 0:GPIO_02; 1:PWM2; 2:DIAG\\[2\\]; 3:SPI1_IO3; 4:WIFI_TSF_SYNC; 5:WL_GLP_SYNC_PULSE; 6:BSLE_GLP_SYNC_PULSE"]
#[inline (always)] pub fn gpio_02_sel (& mut self) -> Gpio02SelW < '_ , Gpio02SelSpec > { Gpio02SelW :: new (self , 0) } }
#[doc = "GPIO_02 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_02_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_02_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio02SelSpec ; impl crate :: RegisterSpec for Gpio02SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_02_sel::R`](R) reader structure"] impl crate :: Readable for Gpio02SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_02_sel::W`](W) writer structure"] impl crate :: Writable for Gpio02SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_02_SEL to value 0"] impl crate :: Resettable for Gpio02SelSpec { } }
#[doc = "GPIO_03_SEL (rw) register accessor: GPIO_03 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_03_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_03_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_03_sel`] module"]
#[doc (alias = "GPIO_03_SEL")] pub type Gpio03Sel = crate :: Reg < gpio_03_sel :: Gpio03SelSpec > ;
#[doc = "GPIO_03 pin mux select"] pub mod gpio_03_sel {
#[doc = "Register `GPIO_03_SEL` reader"] pub type R = crate :: R < Gpio03SelSpec > ;
#[doc = "Register `GPIO_03_SEL` writer"] pub type W = crate :: W < Gpio03SelSpec > ;
#[doc = "Field `gpio_03_sel` reader - GPIO_03 pin mux: 0:GPIO_03; 1:PWM3; 2:PMU_32K_TEST; 3:SPI1_IO1; 4:HW_ID\\[0\\]; 5:DIAG\\[3\\]"] pub type Gpio03SelR = crate :: FieldReader ;
#[doc = "Field `gpio_03_sel` writer - GPIO_03 pin mux: 0:GPIO_03; 1:PWM3; 2:PMU_32K_TEST; 3:SPI1_IO1; 4:HW_ID\\[0\\]; 5:DIAG\\[3\\]"] pub type Gpio03SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_03 pin mux: 0:GPIO_03; 1:PWM3; 2:PMU_32K_TEST; 3:SPI1_IO1; 4:HW_ID\\[0\\]; 5:DIAG\\[3\\]"]
#[inline (always)] pub fn gpio_03_sel (& self) -> Gpio03SelR { Gpio03SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_03 pin mux: 0:GPIO_03; 1:PWM3; 2:PMU_32K_TEST; 3:SPI1_IO1; 4:HW_ID\\[0\\]; 5:DIAG\\[3\\]"]
#[inline (always)] pub fn gpio_03_sel (& mut self) -> Gpio03SelW < '_ , Gpio03SelSpec > { Gpio03SelW :: new (self , 0) } }
#[doc = "GPIO_03 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_03_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_03_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio03SelSpec ; impl crate :: RegisterSpec for Gpio03SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_03_sel::R`](R) reader structure"] impl crate :: Readable for Gpio03SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_03_sel::W`](W) writer structure"] impl crate :: Writable for Gpio03SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_03_SEL to value 0"] impl crate :: Resettable for Gpio03SelSpec { } }
#[doc = "GPIO_04_SEL (rw) register accessor: GPIO_04 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_04_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_04_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_04_sel`] module"]
#[doc (alias = "GPIO_04_SEL")] pub type Gpio04Sel = crate :: Reg < gpio_04_sel :: Gpio04SelSpec > ;
#[doc = "GPIO_04 pin mux select"] pub mod gpio_04_sel {
#[doc = "Register `GPIO_04_SEL` reader"] pub type R = crate :: R < Gpio04SelSpec > ;
#[doc = "Register `GPIO_04_SEL` writer"] pub type W = crate :: W < Gpio04SelSpec > ;
#[doc = "Field `gpio_04_sel` reader - GPIO_04 pin mux: 0:SSI_CLK; 1:PWM4; 2:GPIO_04; 3:SPI1_IO1; 4:JTAG_ENABLE; 5:DFT_JTAG_TMS"] pub type Gpio04SelR = crate :: FieldReader ;
#[doc = "Field `gpio_04_sel` writer - GPIO_04 pin mux: 0:SSI_CLK; 1:PWM4; 2:GPIO_04; 3:SPI1_IO1; 4:JTAG_ENABLE; 5:DFT_JTAG_TMS"] pub type Gpio04SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_04 pin mux: 0:SSI_CLK; 1:PWM4; 2:GPIO_04; 3:SPI1_IO1; 4:JTAG_ENABLE; 5:DFT_JTAG_TMS"]
#[inline (always)] pub fn gpio_04_sel (& self) -> Gpio04SelR { Gpio04SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_04 pin mux: 0:SSI_CLK; 1:PWM4; 2:GPIO_04; 3:SPI1_IO1; 4:JTAG_ENABLE; 5:DFT_JTAG_TMS"]
#[inline (always)] pub fn gpio_04_sel (& mut self) -> Gpio04SelW < '_ , Gpio04SelSpec > { Gpio04SelW :: new (self , 0) } }
#[doc = "GPIO_04 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_04_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_04_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio04SelSpec ; impl crate :: RegisterSpec for Gpio04SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_04_sel::R`](R) reader structure"] impl crate :: Readable for Gpio04SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_04_sel::W`](W) writer structure"] impl crate :: Writable for Gpio04SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_04_SEL to value 0"] impl crate :: Resettable for Gpio04SelSpec { } }
#[doc = "GPIO_05_SEL (rw) register accessor: GPIO_05 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_05_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_05_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_05_sel`] module"]
#[doc (alias = "GPIO_05_SEL")] pub type Gpio05Sel = crate :: Reg < gpio_05_sel :: Gpio05SelSpec > ;
#[doc = "GPIO_05 pin mux select"] pub mod gpio_05_sel {
#[doc = "Register `GPIO_05_SEL` reader"] pub type R = crate :: R < Gpio05SelSpec > ;
#[doc = "Register `GPIO_05_SEL` writer"] pub type W = crate :: W < Gpio05SelSpec > ;
#[doc = "Field `gpio_05_sel` reader - GPIO_05 pin mux: 0:SSI_DATA; 1:PWM5; 2:UART2_CTS; 3:SPI1_IO2; 4:GPIO_05; 5:SPI0_IN; 6:DFT_JTAG_TCK"] pub type Gpio05SelR = crate :: FieldReader ;
#[doc = "Field `gpio_05_sel` writer - GPIO_05 pin mux: 0:SSI_DATA; 1:PWM5; 2:UART2_CTS; 3:SPI1_IO2; 4:GPIO_05; 5:SPI0_IN; 6:DFT_JTAG_TCK"] pub type Gpio05SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_05 pin mux: 0:SSI_DATA; 1:PWM5; 2:UART2_CTS; 3:SPI1_IO2; 4:GPIO_05; 5:SPI0_IN; 6:DFT_JTAG_TCK"]
#[inline (always)] pub fn gpio_05_sel (& self) -> Gpio05SelR { Gpio05SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_05 pin mux: 0:SSI_DATA; 1:PWM5; 2:UART2_CTS; 3:SPI1_IO2; 4:GPIO_05; 5:SPI0_IN; 6:DFT_JTAG_TCK"]
#[inline (always)] pub fn gpio_05_sel (& mut self) -> Gpio05SelW < '_ , Gpio05SelSpec > { Gpio05SelW :: new (self , 0) } }
#[doc = "GPIO_05 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_05_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_05_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio05SelSpec ; impl crate :: RegisterSpec for Gpio05SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_05_sel::R`](R) reader structure"] impl crate :: Readable for Gpio05SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_05_sel::W`](W) writer structure"] impl crate :: Writable for Gpio05SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_05_SEL to value 0"] impl crate :: Resettable for Gpio05SelSpec { } }
#[doc = "GPIO_06_SEL (rw) register accessor: GPIO_06 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_06_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_06_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_06_sel`] module"]
#[doc (alias = "GPIO_06_SEL")] pub type Gpio06Sel = crate :: Reg < gpio_06_sel :: Gpio06SelSpec > ;
#[doc = "GPIO_06 pin mux select"] pub mod gpio_06_sel {
#[doc = "Register `GPIO_06_SEL` reader"] pub type R = crate :: R < Gpio06SelSpec > ;
#[doc = "Register `GPIO_06_SEL` writer"] pub type W = crate :: W < Gpio06SelSpec > ;
#[doc = "Field `gpio_06_sel` reader - GPIO_06 pin mux: 0:GPIO_06; 1:PWM6; 2:UART2_RTS; 3:SPI1_SCK; 4:REFCLK_FREQ_STATUS; 5:DIAG\\[4\\]; 6:SPI0_OUT; 7:DFT_JTAG_TDI"] pub type Gpio06SelR = crate :: FieldReader ;
#[doc = "Field `gpio_06_sel` writer - GPIO_06 pin mux: 0:GPIO_06; 1:PWM6; 2:UART2_RTS; 3:SPI1_SCK; 4:REFCLK_FREQ_STATUS; 5:DIAG\\[4\\]; 6:SPI0_OUT; 7:DFT_JTAG_TDI"] pub type Gpio06SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_06 pin mux: 0:GPIO_06; 1:PWM6; 2:UART2_RTS; 3:SPI1_SCK; 4:REFCLK_FREQ_STATUS; 5:DIAG\\[4\\]; 6:SPI0_OUT; 7:DFT_JTAG_TDI"]
#[inline (always)] pub fn gpio_06_sel (& self) -> Gpio06SelR { Gpio06SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_06 pin mux: 0:GPIO_06; 1:PWM6; 2:UART2_RTS; 3:SPI1_SCK; 4:REFCLK_FREQ_STATUS; 5:DIAG\\[4\\]; 6:SPI0_OUT; 7:DFT_JTAG_TDI"]
#[inline (always)] pub fn gpio_06_sel (& mut self) -> Gpio06SelW < '_ , Gpio06SelSpec > { Gpio06SelW :: new (self , 0) } }
#[doc = "GPIO_06 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_06_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_06_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio06SelSpec ; impl crate :: RegisterSpec for Gpio06SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_06_sel::R`](R) reader structure"] impl crate :: Readable for Gpio06SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_06_sel::W`](W) writer structure"] impl crate :: Writable for Gpio06SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_06_SEL to value 0"] impl crate :: Resettable for Gpio06SelSpec { } }
#[doc = "GPIO_07_SEL (rw) register accessor: GPIO_07 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_07_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_07_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_07_sel`] module"]
#[doc (alias = "GPIO_07_SEL")] pub type Gpio07Sel = crate :: Reg < gpio_07_sel :: Gpio07SelSpec > ;
#[doc = "GPIO_07 pin mux select"] pub mod gpio_07_sel {
#[doc = "Register `GPIO_07_SEL` reader"] pub type R = crate :: R < Gpio07SelSpec > ;
#[doc = "Register `GPIO_07_SEL` writer"] pub type W = crate :: W < Gpio07SelSpec > ;
#[doc = "Field `gpio_07_sel` reader - GPIO_07 pin mux: 0:GPIO_07; 1:PWM7; 2:UART2_RXD; 3:SPI0_SCK; 4:I2S_MCLK; 5:DIAG\\[5\\]"] pub type Gpio07SelR = crate :: FieldReader ;
#[doc = "Field `gpio_07_sel` writer - GPIO_07 pin mux: 0:GPIO_07; 1:PWM7; 2:UART2_RXD; 3:SPI0_SCK; 4:I2S_MCLK; 5:DIAG\\[5\\]"] pub type Gpio07SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_07 pin mux: 0:GPIO_07; 1:PWM7; 2:UART2_RXD; 3:SPI0_SCK; 4:I2S_MCLK; 5:DIAG\\[5\\]"]
#[inline (always)] pub fn gpio_07_sel (& self) -> Gpio07SelR { Gpio07SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_07 pin mux: 0:GPIO_07; 1:PWM7; 2:UART2_RXD; 3:SPI0_SCK; 4:I2S_MCLK; 5:DIAG\\[5\\]"]
#[inline (always)] pub fn gpio_07_sel (& mut self) -> Gpio07SelW < '_ , Gpio07SelSpec > { Gpio07SelW :: new (self , 0) } }
#[doc = "GPIO_07 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_07_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_07_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio07SelSpec ; impl crate :: RegisterSpec for Gpio07SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_07_sel::R`](R) reader structure"] impl crate :: Readable for Gpio07SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_07_sel::W`](W) writer structure"] impl crate :: Writable for Gpio07SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_07_SEL to value 0"] impl crate :: Resettable for Gpio07SelSpec { } }
#[doc = "GPIO_08_SEL (rw) register accessor: GPIO_08 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_08_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_08_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_08_sel`] module"]
#[doc (alias = "GPIO_08_SEL")] pub type Gpio08Sel = crate :: Reg < gpio_08_sel :: Gpio08SelSpec > ;
#[doc = "GPIO_08 pin mux select"] pub mod gpio_08_sel {
#[doc = "Register `GPIO_08_SEL` reader"] pub type R = crate :: R < Gpio08SelSpec > ;
#[doc = "Register `GPIO_08_SEL` writer"] pub type W = crate :: W < Gpio08SelSpec > ;
#[doc = "Field `gpio_08_sel` reader - GPIO_08 pin mux: 0:GPIO_08; 1:PWM0; 2:UART2_TXD; 3:SPI0_CS1_N; 4:DIAG\\[6\\]"] pub type Gpio08SelR = crate :: FieldReader ;
#[doc = "Field `gpio_08_sel` writer - GPIO_08 pin mux: 0:GPIO_08; 1:PWM0; 2:UART2_TXD; 3:SPI0_CS1_N; 4:DIAG\\[6\\]"] pub type Gpio08SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_08 pin mux: 0:GPIO_08; 1:PWM0; 2:UART2_TXD; 3:SPI0_CS1_N; 4:DIAG\\[6\\]"]
#[inline (always)] pub fn gpio_08_sel (& self) -> Gpio08SelR { Gpio08SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_08 pin mux: 0:GPIO_08; 1:PWM0; 2:UART2_TXD; 3:SPI0_CS1_N; 4:DIAG\\[6\\]"]
#[inline (always)] pub fn gpio_08_sel (& mut self) -> Gpio08SelW < '_ , Gpio08SelSpec > { Gpio08SelW :: new (self , 0) } }
#[doc = "GPIO_08 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_08_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_08_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio08SelSpec ; impl crate :: RegisterSpec for Gpio08SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_08_sel::R`](R) reader structure"] impl crate :: Readable for Gpio08SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_08_sel::W`](W) writer structure"] impl crate :: Writable for Gpio08SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_08_SEL to value 0"] impl crate :: Resettable for Gpio08SelSpec { } }
#[doc = "GPIO_09_SEL (rw) register accessor: GPIO_09 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_09_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_09_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_09_sel`] module"]
#[doc (alias = "GPIO_09_SEL")] pub type Gpio09Sel = crate :: Reg < gpio_09_sel :: Gpio09SelSpec > ;
#[doc = "GPIO_09 pin mux select"] pub mod gpio_09_sel {
#[doc = "Register `GPIO_09_SEL` reader"] pub type R = crate :: R < Gpio09SelSpec > ;
#[doc = "Register `GPIO_09_SEL` writer"] pub type W = crate :: W < Gpio09SelSpec > ;
#[doc = "Field `gpio_09_sel` reader - GPIO_09 pin mux: 0:GPIO_09; 1:PWM1; 2:RADAR_ANT0_SW; 3:SPI0_OUT; 4:I2S_DO; 5:HW_ID\\[1\\]; 6:DIAG\\[7\\]; 7:JTAG_TDO"] pub type Gpio09SelR = crate :: FieldReader ;
#[doc = "Field `gpio_09_sel` writer - GPIO_09 pin mux: 0:GPIO_09; 1:PWM1; 2:RADAR_ANT0_SW; 3:SPI0_OUT; 4:I2S_DO; 5:HW_ID\\[1\\]; 6:DIAG\\[7\\]; 7:JTAG_TDO"] pub type Gpio09SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_09 pin mux: 0:GPIO_09; 1:PWM1; 2:RADAR_ANT0_SW; 3:SPI0_OUT; 4:I2S_DO; 5:HW_ID\\[1\\]; 6:DIAG\\[7\\]; 7:JTAG_TDO"]
#[inline (always)] pub fn gpio_09_sel (& self) -> Gpio09SelR { Gpio09SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_09 pin mux: 0:GPIO_09; 1:PWM1; 2:RADAR_ANT0_SW; 3:SPI0_OUT; 4:I2S_DO; 5:HW_ID\\[1\\]; 6:DIAG\\[7\\]; 7:JTAG_TDO"]
#[inline (always)] pub fn gpio_09_sel (& mut self) -> Gpio09SelW < '_ , Gpio09SelSpec > { Gpio09SelW :: new (self , 0) } }
#[doc = "GPIO_09 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_09_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_09_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio09SelSpec ; impl crate :: RegisterSpec for Gpio09SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_09_sel::R`](R) reader structure"] impl crate :: Readable for Gpio09SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_09_sel::W`](W) writer structure"] impl crate :: Writable for Gpio09SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_09_SEL to value 0"] impl crate :: Resettable for Gpio09SelSpec { } }
#[doc = "GPIO_10_SEL (rw) register accessor: GPIO_10 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_10_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_10_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_10_sel`] module"]
#[doc (alias = "GPIO_10_SEL")] pub type Gpio10Sel = crate :: Reg < gpio_10_sel :: Gpio10SelSpec > ;
#[doc = "GPIO_10 pin mux select"] pub mod gpio_10_sel {
#[doc = "Register `GPIO_10_SEL` reader"] pub type R = crate :: R < Gpio10SelSpec > ;
#[doc = "Register `GPIO_10_SEL` writer"] pub type W = crate :: W < Gpio10SelSpec > ;
#[doc = "Field `gpio_10_sel` reader - GPIO_10 pin mux: 0:GPIO_10; 1:PWM2; 2:ANT0_SW; 3:SPI0_CS0_N; 4:I2S_SCLK; 5:DIAG\\[0\\]"] pub type Gpio10SelR = crate :: FieldReader ;
#[doc = "Field `gpio_10_sel` writer - GPIO_10 pin mux: 0:GPIO_10; 1:PWM2; 2:ANT0_SW; 3:SPI0_CS0_N; 4:I2S_SCLK; 5:DIAG\\[0\\]"] pub type Gpio10SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_10 pin mux: 0:GPIO_10; 1:PWM2; 2:ANT0_SW; 3:SPI0_CS0_N; 4:I2S_SCLK; 5:DIAG\\[0\\]"]
#[inline (always)] pub fn gpio_10_sel (& self) -> Gpio10SelR { Gpio10SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_10 pin mux: 0:GPIO_10; 1:PWM2; 2:ANT0_SW; 3:SPI0_CS0_N; 4:I2S_SCLK; 5:DIAG\\[0\\]"]
#[inline (always)] pub fn gpio_10_sel (& mut self) -> Gpio10SelW < '_ , Gpio10SelSpec > { Gpio10SelW :: new (self , 0) } }
#[doc = "GPIO_10 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_10_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_10_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio10SelSpec ; impl crate :: RegisterSpec for Gpio10SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_10_sel::R`](R) reader structure"] impl crate :: Readable for Gpio10SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_10_sel::W`](W) writer structure"] impl crate :: Writable for Gpio10SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_10_SEL to value 0"] impl crate :: Resettable for Gpio10SelSpec { } }
#[doc = "GPIO_11_SEL (rw) register accessor: GPIO_11 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_11_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_11_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_11_sel`] module"]
#[doc (alias = "GPIO_11_SEL")] pub type Gpio11Sel = crate :: Reg < gpio_11_sel :: Gpio11SelSpec > ;
#[doc = "GPIO_11 pin mux select"] pub mod gpio_11_sel {
#[doc = "Register `GPIO_11_SEL` reader"] pub type R = crate :: R < Gpio11SelSpec > ;
#[doc = "Register `GPIO_11_SEL` writer"] pub type W = crate :: W < Gpio11SelSpec > ;
#[doc = "Field `gpio_11_sel` reader - GPIO_11 pin mux: 0:GPIO_11; 1:PWM3; 2:RADAR_ANT1_SW; 3:SPI0_IN; 4:I2S_LRCLK; 5:DIAG\\[1\\]; 6:HW_ID\\[2\\]"] pub type Gpio11SelR = crate :: FieldReader ;
#[doc = "Field `gpio_11_sel` writer - GPIO_11 pin mux: 0:GPIO_11; 1:PWM3; 2:RADAR_ANT1_SW; 3:SPI0_IN; 4:I2S_LRCLK; 5:DIAG\\[1\\]; 6:HW_ID\\[2\\]"] pub type Gpio11SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_11 pin mux: 0:GPIO_11; 1:PWM3; 2:RADAR_ANT1_SW; 3:SPI0_IN; 4:I2S_LRCLK; 5:DIAG\\[1\\]; 6:HW_ID\\[2\\]"]
#[inline (always)] pub fn gpio_11_sel (& self) -> Gpio11SelR { Gpio11SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_11 pin mux: 0:GPIO_11; 1:PWM3; 2:RADAR_ANT1_SW; 3:SPI0_IN; 4:I2S_LRCLK; 5:DIAG\\[1\\]; 6:HW_ID\\[2\\]"]
#[inline (always)] pub fn gpio_11_sel (& mut self) -> Gpio11SelW < '_ , Gpio11SelSpec > { Gpio11SelW :: new (self , 0) } }
#[doc = "GPIO_11 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_11_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_11_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio11SelSpec ; impl crate :: RegisterSpec for Gpio11SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_11_sel::R`](R) reader structure"] impl crate :: Readable for Gpio11SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_11_sel::W`](W) writer structure"] impl crate :: Writable for Gpio11SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_11_SEL to value 0"] impl crate :: Resettable for Gpio11SelSpec { } }
#[doc = "GPIO_12_SEL (rw) register accessor: GPIO_12 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_12_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_12_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_12_sel`] module"]
#[doc (alias = "GPIO_12_SEL")] pub type Gpio12Sel = crate :: Reg < gpio_12_sel :: Gpio12SelSpec > ;
#[doc = "GPIO_12 pin mux select"] pub mod gpio_12_sel {
#[doc = "Register `GPIO_12_SEL` reader"] pub type R = crate :: R < Gpio12SelSpec > ;
#[doc = "Register `GPIO_12_SEL` writer"] pub type W = crate :: W < Gpio12SelSpec > ;
#[doc = "Field `gpio_12_sel` reader - GPIO_12 pin mux: 0:GPIO_12; 1:PWM4; 2:ANT1_SW; 4:I2S_DI; 6:HW_ID\\[3\\]"] pub type Gpio12SelR = crate :: FieldReader ;
#[doc = "Field `gpio_12_sel` writer - GPIO_12 pin mux: 0:GPIO_12; 1:PWM4; 2:ANT1_SW; 4:I2S_DI; 6:HW_ID\\[3\\]"] pub type Gpio12SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_12 pin mux: 0:GPIO_12; 1:PWM4; 2:ANT1_SW; 4:I2S_DI; 6:HW_ID\\[3\\]"]
#[inline (always)] pub fn gpio_12_sel (& self) -> Gpio12SelR { Gpio12SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_12 pin mux: 0:GPIO_12; 1:PWM4; 2:ANT1_SW; 4:I2S_DI; 6:HW_ID\\[3\\]"]
#[inline (always)] pub fn gpio_12_sel (& mut self) -> Gpio12SelW < '_ , Gpio12SelSpec > { Gpio12SelW :: new (self , 0) } }
#[doc = "GPIO_12 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_12_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_12_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio12SelSpec ; impl crate :: RegisterSpec for Gpio12SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_12_sel::R`](R) reader structure"] impl crate :: Readable for Gpio12SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_12_sel::W`](W) writer structure"] impl crate :: Writable for Gpio12SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_12_SEL to value 0"] impl crate :: Resettable for Gpio12SelSpec { } }
#[doc = "GPIO_13_SEL (rw) register accessor: GPIO_13 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_13_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_13_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_13_sel`] module"]
#[doc (alias = "GPIO_13_SEL")] pub type Gpio13Sel = crate :: Reg < gpio_13_sel :: Gpio13SelSpec > ;
#[doc = "GPIO_13 pin mux select"] pub mod gpio_13_sel {
#[doc = "Register `GPIO_13_SEL` reader"] pub type R = crate :: R < Gpio13SelSpec > ;
#[doc = "Register `GPIO_13_SEL` writer"] pub type W = crate :: W < Gpio13SelSpec > ;
#[doc = "Field `gpio_13_sel` reader - GPIO_13 pin mux: 0:GPIO_13; 1:UART1_CTS; 2:RADAR_ANT0_SW; 3:DFT_JTAG_TDO; 4:JTAG_TMS"] pub type Gpio13SelR = crate :: FieldReader ;
#[doc = "Field `gpio_13_sel` writer - GPIO_13 pin mux: 0:GPIO_13; 1:UART1_CTS; 2:RADAR_ANT0_SW; 3:DFT_JTAG_TDO; 4:JTAG_TMS"] pub type Gpio13SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_13 pin mux: 0:GPIO_13; 1:UART1_CTS; 2:RADAR_ANT0_SW; 3:DFT_JTAG_TDO; 4:JTAG_TMS"]
#[inline (always)] pub fn gpio_13_sel (& self) -> Gpio13SelR { Gpio13SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_13 pin mux: 0:GPIO_13; 1:UART1_CTS; 2:RADAR_ANT0_SW; 3:DFT_JTAG_TDO; 4:JTAG_TMS"]
#[inline (always)] pub fn gpio_13_sel (& mut self) -> Gpio13SelW < '_ , Gpio13SelSpec > { Gpio13SelW :: new (self , 0) } }
#[doc = "GPIO_13 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_13_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_13_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio13SelSpec ; impl crate :: RegisterSpec for Gpio13SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_13_sel::R`](R) reader structure"] impl crate :: Readable for Gpio13SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_13_sel::W`](W) writer structure"] impl crate :: Writable for Gpio13SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_13_SEL to value 0"] impl crate :: Resettable for Gpio13SelSpec { } }
#[doc = "GPIO_14_SEL (rw) register accessor: GPIO_14 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_14_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_14_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_14_sel`] module"]
#[doc (alias = "GPIO_14_SEL")] pub type Gpio14Sel = crate :: Reg < gpio_14_sel :: Gpio14SelSpec > ;
#[doc = "GPIO_14 pin mux select"] pub mod gpio_14_sel {
#[doc = "Register `GPIO_14_SEL` reader"] pub type R = crate :: R < Gpio14SelSpec > ;
#[doc = "Register `GPIO_14_SEL` writer"] pub type W = crate :: W < Gpio14SelSpec > ;
#[doc = "Field `gpio_14_sel` reader - GPIO_14 pin mux: 0:GPIO_14; 1:UART1_RTS; 2:RADAR_ANT1_SW; 3:DFT_JTAG_TRSTN; 4:JTAG_TCK"] pub type Gpio14SelR = crate :: FieldReader ;
#[doc = "Field `gpio_14_sel` writer - GPIO_14 pin mux: 0:GPIO_14; 1:UART1_RTS; 2:RADAR_ANT1_SW; 3:DFT_JTAG_TRSTN; 4:JTAG_TCK"] pub type Gpio14SelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - GPIO_14 pin mux: 0:GPIO_14; 1:UART1_RTS; 2:RADAR_ANT1_SW; 3:DFT_JTAG_TRSTN; 4:JTAG_TCK"]
#[inline (always)] pub fn gpio_14_sel (& self) -> Gpio14SelR { Gpio14SelR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - GPIO_14 pin mux: 0:GPIO_14; 1:UART1_RTS; 2:RADAR_ANT1_SW; 3:DFT_JTAG_TRSTN; 4:JTAG_TCK"]
#[inline (always)] pub fn gpio_14_sel (& mut self) -> Gpio14SelW < '_ , Gpio14SelSpec > { Gpio14SelW :: new (self , 0) } }
#[doc = "GPIO_14 pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_14_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_14_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Gpio14SelSpec ; impl crate :: RegisterSpec for Gpio14SelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_14_sel::R`](R) reader structure"] impl crate :: Readable for Gpio14SelSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_14_sel::W`](W) writer structure"] impl crate :: Writable for Gpio14SelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_14_SEL to value 0"] impl crate :: Resettable for Gpio14SelSpec { } }
#[doc = "UART1_TXD_SEL (rw) register accessor: UART1_TXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_txd_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_txd_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_txd_sel`] module"]
#[doc (alias = "UART1_TXD_SEL")] pub type Uart1TxdSel = crate :: Reg < uart1_txd_sel :: Uart1TxdSelSpec > ;
#[doc = "UART1_TXD pin mux select"] pub mod uart1_txd_sel {
#[doc = "Register `UART1_TXD_SEL` reader"] pub type R = crate :: R < Uart1TxdSelSpec > ;
#[doc = "Register `UART1_TXD_SEL` writer"] pub type W = crate :: W < Uart1TxdSelSpec > ;
#[doc = "Field `uart1_txd_sel` reader - UART1_TXD pin mux: 0:GPIO_15; 1:UART1_TXD; 2:I2C1_SDA"] pub type Uart1TxdSelR = crate :: FieldReader ;
#[doc = "Field `uart1_txd_sel` writer - UART1_TXD pin mux: 0:GPIO_15; 1:UART1_TXD; 2:I2C1_SDA"] pub type Uart1TxdSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R {
#[doc = "Bits 0:1 - UART1_TXD pin mux: 0:GPIO_15; 1:UART1_TXD; 2:I2C1_SDA"]
#[inline (always)] pub fn uart1_txd_sel (& self) -> Uart1TxdSelR { Uart1TxdSelR :: new ((self . bits & 3) as u8) } } impl W {
#[doc = "Bits 0:1 - UART1_TXD pin mux: 0:GPIO_15; 1:UART1_TXD; 2:I2C1_SDA"]
#[inline (always)] pub fn uart1_txd_sel (& mut self) -> Uart1TxdSelW < '_ , Uart1TxdSelSpec > { Uart1TxdSelW :: new (self , 0) } }
#[doc = "UART1_TXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_txd_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_txd_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Uart1TxdSelSpec ; impl crate :: RegisterSpec for Uart1TxdSelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`uart1_txd_sel::R`](R) reader structure"] impl crate :: Readable for Uart1TxdSelSpec { }
#[doc = "`write(|w| ..)` method takes [`uart1_txd_sel::W`](W) writer structure"] impl crate :: Writable for Uart1TxdSelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets UART1_TXD_SEL to value 0"] impl crate :: Resettable for Uart1TxdSelSpec { } }
#[doc = "UART1_RXD_SEL (rw) register accessor: UART1_RXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_rxd_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_rxd_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_rxd_sel`] module"]
#[doc (alias = "UART1_RXD_SEL")] pub type Uart1RxdSel = crate :: Reg < uart1_rxd_sel :: Uart1RxdSelSpec > ;
#[doc = "UART1_RXD pin mux select"] pub mod uart1_rxd_sel {
#[doc = "Register `UART1_RXD_SEL` reader"] pub type R = crate :: R < Uart1RxdSelSpec > ;
#[doc = "Register `UART1_RXD_SEL` writer"] pub type W = crate :: W < Uart1RxdSelSpec > ;
#[doc = "Field `uart1_rxd_sel` reader - UART1_RXD pin mux: 0:GPIO_16; 1:UART1_RXD; 2:I2C1_SCL"] pub type Uart1RxdSelR = crate :: FieldReader ;
#[doc = "Field `uart1_rxd_sel` writer - UART1_RXD pin mux: 0:GPIO_16; 1:UART1_RXD; 2:I2C1_SCL"] pub type Uart1RxdSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R {
#[doc = "Bits 0:1 - UART1_RXD pin mux: 0:GPIO_16; 1:UART1_RXD; 2:I2C1_SCL"]
#[inline (always)] pub fn uart1_rxd_sel (& self) -> Uart1RxdSelR { Uart1RxdSelR :: new ((self . bits & 3) as u8) } } impl W {
#[doc = "Bits 0:1 - UART1_RXD pin mux: 0:GPIO_16; 1:UART1_RXD; 2:I2C1_SCL"]
#[inline (always)] pub fn uart1_rxd_sel (& mut self) -> Uart1RxdSelW < '_ , Uart1RxdSelSpec > { Uart1RxdSelW :: new (self , 0) } }
#[doc = "UART1_RXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_rxd_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_rxd_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Uart1RxdSelSpec ; impl crate :: RegisterSpec for Uart1RxdSelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`uart1_rxd_sel::R`](R) reader structure"] impl crate :: Readable for Uart1RxdSelSpec { }
#[doc = "`write(|w| ..)` method takes [`uart1_rxd_sel::W`](W) writer structure"] impl crate :: Writable for Uart1RxdSelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets UART1_RXD_SEL to value 0"] impl crate :: Resettable for Uart1RxdSelSpec { } }
#[doc = "UART0_TXD_SEL (rw) register accessor: UART0_TXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_txd_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_txd_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_txd_sel`] module"]
#[doc (alias = "UART0_TXD_SEL")] pub type Uart0TxdSel = crate :: Reg < uart0_txd_sel :: Uart0TxdSelSpec > ;
#[doc = "UART0_TXD pin mux select"] pub mod uart0_txd_sel {
#[doc = "Register `UART0_TXD_SEL` reader"] pub type R = crate :: R < Uart0TxdSelSpec > ;
#[doc = "Register `UART0_TXD_SEL` writer"] pub type W = crate :: W < Uart0TxdSelSpec > ;
#[doc = "Field `uart0_txd_sel` reader - UART0_TXD pin mux: 0:GPIO_17; 1:UART0_TXD; 2:I2C0_SDA"] pub type Uart0TxdSelR = crate :: FieldReader ;
#[doc = "Field `uart0_txd_sel` writer - UART0_TXD pin mux: 0:GPIO_17; 1:UART0_TXD; 2:I2C0_SDA"] pub type Uart0TxdSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R {
#[doc = "Bits 0:1 - UART0_TXD pin mux: 0:GPIO_17; 1:UART0_TXD; 2:I2C0_SDA"]
#[inline (always)] pub fn uart0_txd_sel (& self) -> Uart0TxdSelR { Uart0TxdSelR :: new ((self . bits & 3) as u8) } } impl W {
#[doc = "Bits 0:1 - UART0_TXD pin mux: 0:GPIO_17; 1:UART0_TXD; 2:I2C0_SDA"]
#[inline (always)] pub fn uart0_txd_sel (& mut self) -> Uart0TxdSelW < '_ , Uart0TxdSelSpec > { Uart0TxdSelW :: new (self , 0) } }
#[doc = "UART0_TXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_txd_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_txd_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Uart0TxdSelSpec ; impl crate :: RegisterSpec for Uart0TxdSelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`uart0_txd_sel::R`](R) reader structure"] impl crate :: Readable for Uart0TxdSelSpec { }
#[doc = "`write(|w| ..)` method takes [`uart0_txd_sel::W`](W) writer structure"] impl crate :: Writable for Uart0TxdSelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets UART0_TXD_SEL to value 0"] impl crate :: Resettable for Uart0TxdSelSpec { } }
#[doc = "UART0_RXD_SEL (rw) register accessor: UART0_RXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_rxd_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_rxd_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_rxd_sel`] module"]
#[doc (alias = "UART0_RXD_SEL")] pub type Uart0RxdSel = crate :: Reg < uart0_rxd_sel :: Uart0RxdSelSpec > ;
#[doc = "UART0_RXD pin mux select"] pub mod uart0_rxd_sel {
#[doc = "Register `UART0_RXD_SEL` reader"] pub type R = crate :: R < Uart0RxdSelSpec > ;
#[doc = "Register `UART0_RXD_SEL` writer"] pub type W = crate :: W < Uart0RxdSelSpec > ;
#[doc = "Field `uart0_rxd_sel` reader - UART0_RXD pin mux: 0:GPIO_18; 1:UART0_RXD; 2:I2C0_SCL"] pub type Uart0RxdSelR = crate :: FieldReader ;
#[doc = "Field `uart0_rxd_sel` writer - UART0_RXD pin mux: 0:GPIO_18; 1:UART0_RXD; 2:I2C0_SCL"] pub type Uart0RxdSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R {
#[doc = "Bits 0:1 - UART0_RXD pin mux: 0:GPIO_18; 1:UART0_RXD; 2:I2C0_SCL"]
#[inline (always)] pub fn uart0_rxd_sel (& self) -> Uart0RxdSelR { Uart0RxdSelR :: new ((self . bits & 3) as u8) } } impl W {
#[doc = "Bits 0:1 - UART0_RXD pin mux: 0:GPIO_18; 1:UART0_RXD; 2:I2C0_SCL"]
#[inline (always)] pub fn uart0_rxd_sel (& mut self) -> Uart0RxdSelW < '_ , Uart0RxdSelSpec > { Uart0RxdSelW :: new (self , 0) } }
#[doc = "UART0_RXD pin mux select\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_rxd_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_rxd_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Uart0RxdSelSpec ; impl crate :: RegisterSpec for Uart0RxdSelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`uart0_rxd_sel::R`](R) reader structure"] impl crate :: Readable for Uart0RxdSelSpec { }
#[doc = "`write(|w| ..)` method takes [`uart0_rxd_sel::W`](W) writer structure"] impl crate :: Writable for Uart0RxdSelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets UART0_RXD_SEL to value 0"] impl crate :: Resettable for Uart0RxdSelSpec { } }
#[doc = "PAD_GPIO_00_CTRL (rw) register accessor: GPIO_00 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_00_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_00_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_00_ctrl`] module"]
#[doc (alias = "PAD_GPIO_00_CTRL")] pub type PadGpio00Ctrl = crate :: Reg < pad_gpio_00_ctrl :: PadGpio00CtrlSpec > ;
#[doc = "GPIO_00 pad control register"] pub mod pad_gpio_00_ctrl {
#[doc = "Register `PAD_GPIO_00_CTRL` reader"] pub type R = crate :: R < PadGpio00CtrlSpec > ;
#[doc = "Register `PAD_GPIO_00_CTRL` writer"] pub type W = crate :: W < PadGpio00CtrlSpec > ;
#[doc = "Field `pad_gpio_00_ctrl_st` reader - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"] pub type PadGpio00CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_00_ctrl_st` writer - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"] pub type PadGpio00CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_00_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio00CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_00_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio00CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_00_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio00CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_00_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio00CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_00_ctrl_ds2` reader - Drive strength bit 2. DS2~DS0: 111~000, drive strength decreases"] pub type PadGpio00CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_00_ctrl_ds2` writer - Drive strength bit 2. DS2~DS0: 111~000, drive strength decreases"] pub type PadGpio00CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_00_ctrl_pe` reader - Pull enable. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"] pub type PadGpio00CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_00_ctrl_pe` writer - Pull enable. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"] pub type PadGpio00CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_00_ctrl_ps` reader - Pull select. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"] pub type PadGpio00CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_00_ctrl_ps` writer - Pull select. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"] pub type PadGpio00CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_00_ctrl_ie` reader - Input enable: 0:input disabled; 1:input enabled"] pub type PadGpio00CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_00_ctrl_ie` writer - Input enable: 0:input disabled; 1:input enabled"] pub type PadGpio00CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
#[inline (always)] pub fn pad_gpio_00_ctrl_st (& self) -> PadGpio00CtrlStR { PadGpio00CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_00_ctrl_ds0 (& self) -> PadGpio00CtrlDs0R { PadGpio00CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_00_ctrl_ds1 (& self) -> PadGpio00CtrlDs1R { PadGpio00CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2. DS2~DS0: 111~000, drive strength decreases"]
#[inline (always)] pub fn pad_gpio_00_ctrl_ds2 (& self) -> PadGpio00CtrlDs2R { PadGpio00CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
#[inline (always)] pub fn pad_gpio_00_ctrl_pe (& self) -> PadGpio00CtrlPeR { PadGpio00CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
#[inline (always)] pub fn pad_gpio_00_ctrl_ps (& self) -> PadGpio00CtrlPsR { PadGpio00CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable: 0:input disabled; 1:input enabled"]
#[inline (always)] pub fn pad_gpio_00_ctrl_ie (& self) -> PadGpio00CtrlIeR { PadGpio00CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
#[inline (always)] pub fn pad_gpio_00_ctrl_st (& mut self) -> PadGpio00CtrlStW < '_ , PadGpio00CtrlSpec > { PadGpio00CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_00_ctrl_ds0 (& mut self) -> PadGpio00CtrlDs0W < '_ , PadGpio00CtrlSpec > { PadGpio00CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_00_ctrl_ds1 (& mut self) -> PadGpio00CtrlDs1W < '_ , PadGpio00CtrlSpec > { PadGpio00CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2. DS2~DS0: 111~000, drive strength decreases"]
#[inline (always)] pub fn pad_gpio_00_ctrl_ds2 (& mut self) -> PadGpio00CtrlDs2W < '_ , PadGpio00CtrlSpec > { PadGpio00CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
#[inline (always)] pub fn pad_gpio_00_ctrl_pe (& mut self) -> PadGpio00CtrlPeW < '_ , PadGpio00CtrlSpec > { PadGpio00CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select. PE/PS: 00:no pull; 01:strong pull-up; 10:pull-down; 11:pull-up"]
#[inline (always)] pub fn pad_gpio_00_ctrl_ps (& mut self) -> PadGpio00CtrlPsW < '_ , PadGpio00CtrlSpec > { PadGpio00CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable: 0:input disabled; 1:input enabled"]
#[inline (always)] pub fn pad_gpio_00_ctrl_ie (& mut self) -> PadGpio00CtrlIeW < '_ , PadGpio00CtrlSpec > { PadGpio00CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_00 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_00_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_00_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio00CtrlSpec ; impl crate :: RegisterSpec for PadGpio00CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_00_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio00CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_00_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio00CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_00_CTRL to value 0x0800"] impl crate :: Resettable for PadGpio00CtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_GPIO_01_CTRL (rw) register accessor: GPIO_01 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_01_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_01_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_01_ctrl`] module"]
#[doc (alias = "PAD_GPIO_01_CTRL")] pub type PadGpio01Ctrl = crate :: Reg < pad_gpio_01_ctrl :: PadGpio01CtrlSpec > ;
#[doc = "GPIO_01 pad control register"] pub mod pad_gpio_01_ctrl {
#[doc = "Register `PAD_GPIO_01_CTRL` reader"] pub type R = crate :: R < PadGpio01CtrlSpec > ;
#[doc = "Register `PAD_GPIO_01_CTRL` writer"] pub type W = crate :: W < PadGpio01CtrlSpec > ;
#[doc = "Field `pad_gpio_01_ctrl_st` reader - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"] pub type PadGpio01CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_01_ctrl_st` writer - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"] pub type PadGpio01CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_01_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio01CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_01_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio01CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_01_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio01CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_01_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio01CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_01_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio01CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_01_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio01CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_01_ctrl_pe` reader - Pull enable"] pub type PadGpio01CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_01_ctrl_pe` writer - Pull enable"] pub type PadGpio01CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_01_ctrl_ps` reader - Pull select"] pub type PadGpio01CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_01_ctrl_ps` writer - Pull select"] pub type PadGpio01CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_01_ctrl_ie` reader - Input enable"] pub type PadGpio01CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_01_ctrl_ie` writer - Input enable"] pub type PadGpio01CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
#[inline (always)] pub fn pad_gpio_01_ctrl_st (& self) -> PadGpio01CtrlStR { PadGpio01CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_01_ctrl_ds0 (& self) -> PadGpio01CtrlDs0R { PadGpio01CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_01_ctrl_ds1 (& self) -> PadGpio01CtrlDs1R { PadGpio01CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_01_ctrl_ds2 (& self) -> PadGpio01CtrlDs2R { PadGpio01CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_01_ctrl_pe (& self) -> PadGpio01CtrlPeR { PadGpio01CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_01_ctrl_ps (& self) -> PadGpio01CtrlPsR { PadGpio01CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_01_ctrl_ie (& self) -> PadGpio01CtrlIeR { PadGpio01CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger: 0:No Schmitt; 1:Schmitt Enable"]
#[inline (always)] pub fn pad_gpio_01_ctrl_st (& mut self) -> PadGpio01CtrlStW < '_ , PadGpio01CtrlSpec > { PadGpio01CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_01_ctrl_ds0 (& mut self) -> PadGpio01CtrlDs0W < '_ , PadGpio01CtrlSpec > { PadGpio01CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_01_ctrl_ds1 (& mut self) -> PadGpio01CtrlDs1W < '_ , PadGpio01CtrlSpec > { PadGpio01CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_01_ctrl_ds2 (& mut self) -> PadGpio01CtrlDs2W < '_ , PadGpio01CtrlSpec > { PadGpio01CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_01_ctrl_pe (& mut self) -> PadGpio01CtrlPeW < '_ , PadGpio01CtrlSpec > { PadGpio01CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_01_ctrl_ps (& mut self) -> PadGpio01CtrlPsW < '_ , PadGpio01CtrlSpec > { PadGpio01CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_01_ctrl_ie (& mut self) -> PadGpio01CtrlIeW < '_ , PadGpio01CtrlSpec > { PadGpio01CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_01 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_01_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_01_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio01CtrlSpec ; impl crate :: RegisterSpec for PadGpio01CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_01_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio01CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_01_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio01CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_01_CTRL to value 0x0a00"] impl crate :: Resettable for PadGpio01CtrlSpec { const RESET_VALUE : u32 = 0x0a00 ; } }
#[doc = "PAD_GPIO_02_CTRL (rw) register accessor: GPIO_02 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_02_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_02_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_02_ctrl`] module"]
#[doc (alias = "PAD_GPIO_02_CTRL")] pub type PadGpio02Ctrl = crate :: Reg < pad_gpio_02_ctrl :: PadGpio02CtrlSpec > ;
#[doc = "GPIO_02 pad control register"] pub mod pad_gpio_02_ctrl {
#[doc = "Register `PAD_GPIO_02_CTRL` reader"] pub type R = crate :: R < PadGpio02CtrlSpec > ;
#[doc = "Register `PAD_GPIO_02_CTRL` writer"] pub type W = crate :: W < PadGpio02CtrlSpec > ;
#[doc = "Field `pad_gpio_02_ctrl_st` reader - Schmitt trigger"] pub type PadGpio02CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_02_ctrl_st` writer - Schmitt trigger"] pub type PadGpio02CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_02_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio02CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_02_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio02CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_02_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio02CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_02_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio02CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_02_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio02CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_02_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio02CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_02_ctrl_pe` reader - Pull enable"] pub type PadGpio02CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_02_ctrl_pe` writer - Pull enable"] pub type PadGpio02CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_02_ctrl_ps` reader - Pull select"] pub type PadGpio02CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_02_ctrl_ps` writer - Pull select"] pub type PadGpio02CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_02_ctrl_ie` reader - Input enable"] pub type PadGpio02CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_02_ctrl_ie` writer - Input enable"] pub type PadGpio02CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_02_ctrl_st (& self) -> PadGpio02CtrlStR { PadGpio02CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_02_ctrl_ds0 (& self) -> PadGpio02CtrlDs0R { PadGpio02CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_02_ctrl_ds1 (& self) -> PadGpio02CtrlDs1R { PadGpio02CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_02_ctrl_ds2 (& self) -> PadGpio02CtrlDs2R { PadGpio02CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_02_ctrl_pe (& self) -> PadGpio02CtrlPeR { PadGpio02CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_02_ctrl_ps (& self) -> PadGpio02CtrlPsR { PadGpio02CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_02_ctrl_ie (& self) -> PadGpio02CtrlIeR { PadGpio02CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_02_ctrl_st (& mut self) -> PadGpio02CtrlStW < '_ , PadGpio02CtrlSpec > { PadGpio02CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_02_ctrl_ds0 (& mut self) -> PadGpio02CtrlDs0W < '_ , PadGpio02CtrlSpec > { PadGpio02CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_02_ctrl_ds1 (& mut self) -> PadGpio02CtrlDs1W < '_ , PadGpio02CtrlSpec > { PadGpio02CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_02_ctrl_ds2 (& mut self) -> PadGpio02CtrlDs2W < '_ , PadGpio02CtrlSpec > { PadGpio02CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_02_ctrl_pe (& mut self) -> PadGpio02CtrlPeW < '_ , PadGpio02CtrlSpec > { PadGpio02CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_02_ctrl_ps (& mut self) -> PadGpio02CtrlPsW < '_ , PadGpio02CtrlSpec > { PadGpio02CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_02_ctrl_ie (& mut self) -> PadGpio02CtrlIeW < '_ , PadGpio02CtrlSpec > { PadGpio02CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_02 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_02_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_02_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio02CtrlSpec ; impl crate :: RegisterSpec for PadGpio02CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_02_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio02CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_02_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio02CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_02_CTRL to value 0x0800"] impl crate :: Resettable for PadGpio02CtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_GPIO_03_CTRL (rw) register accessor: GPIO_03 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_03_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_03_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_03_ctrl`] module"]
#[doc (alias = "PAD_GPIO_03_CTRL")] pub type PadGpio03Ctrl = crate :: Reg < pad_gpio_03_ctrl :: PadGpio03CtrlSpec > ;
#[doc = "GPIO_03 pad control register"] pub mod pad_gpio_03_ctrl {
#[doc = "Register `PAD_GPIO_03_CTRL` reader"] pub type R = crate :: R < PadGpio03CtrlSpec > ;
#[doc = "Register `PAD_GPIO_03_CTRL` writer"] pub type W = crate :: W < PadGpio03CtrlSpec > ;
#[doc = "Field `pad_gpio_03_ctrl_st` reader - Schmitt trigger"] pub type PadGpio03CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_03_ctrl_st` writer - Schmitt trigger"] pub type PadGpio03CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_03_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio03CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_03_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio03CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_03_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio03CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_03_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio03CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_03_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio03CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_03_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio03CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_03_ctrl_pe` reader - Pull enable"] pub type PadGpio03CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_03_ctrl_pe` writer - Pull enable"] pub type PadGpio03CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_03_ctrl_ps` reader - Pull select"] pub type PadGpio03CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_03_ctrl_ps` writer - Pull select"] pub type PadGpio03CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_03_ctrl_ie` reader - Input enable"] pub type PadGpio03CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_03_ctrl_ie` writer - Input enable"] pub type PadGpio03CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_03_ctrl_st (& self) -> PadGpio03CtrlStR { PadGpio03CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_03_ctrl_ds0 (& self) -> PadGpio03CtrlDs0R { PadGpio03CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_03_ctrl_ds1 (& self) -> PadGpio03CtrlDs1R { PadGpio03CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_03_ctrl_ds2 (& self) -> PadGpio03CtrlDs2R { PadGpio03CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_03_ctrl_pe (& self) -> PadGpio03CtrlPeR { PadGpio03CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_03_ctrl_ps (& self) -> PadGpio03CtrlPsR { PadGpio03CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_03_ctrl_ie (& self) -> PadGpio03CtrlIeR { PadGpio03CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_03_ctrl_st (& mut self) -> PadGpio03CtrlStW < '_ , PadGpio03CtrlSpec > { PadGpio03CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_03_ctrl_ds0 (& mut self) -> PadGpio03CtrlDs0W < '_ , PadGpio03CtrlSpec > { PadGpio03CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_03_ctrl_ds1 (& mut self) -> PadGpio03CtrlDs1W < '_ , PadGpio03CtrlSpec > { PadGpio03CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_03_ctrl_ds2 (& mut self) -> PadGpio03CtrlDs2W < '_ , PadGpio03CtrlSpec > { PadGpio03CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_03_ctrl_pe (& mut self) -> PadGpio03CtrlPeW < '_ , PadGpio03CtrlSpec > { PadGpio03CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_03_ctrl_ps (& mut self) -> PadGpio03CtrlPsW < '_ , PadGpio03CtrlSpec > { PadGpio03CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_03_ctrl_ie (& mut self) -> PadGpio03CtrlIeW < '_ , PadGpio03CtrlSpec > { PadGpio03CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_03 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_03_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_03_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio03CtrlSpec ; impl crate :: RegisterSpec for PadGpio03CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_03_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio03CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_03_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio03CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_03_CTRL to value 0x0a00"] impl crate :: Resettable for PadGpio03CtrlSpec { const RESET_VALUE : u32 = 0x0a00 ; } }
#[doc = "PAD_GPIO_04_CTRL (rw) register accessor: GPIO_04 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_04_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_04_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_04_ctrl`] module"]
#[doc (alias = "PAD_GPIO_04_CTRL")] pub type PadGpio04Ctrl = crate :: Reg < pad_gpio_04_ctrl :: PadGpio04CtrlSpec > ;
#[doc = "GPIO_04 pad control register"] pub mod pad_gpio_04_ctrl {
#[doc = "Register `PAD_GPIO_04_CTRL` reader"] pub type R = crate :: R < PadGpio04CtrlSpec > ;
#[doc = "Register `PAD_GPIO_04_CTRL` writer"] pub type W = crate :: W < PadGpio04CtrlSpec > ;
#[doc = "Field `pad_gpio_04_ctrl_st` reader - Schmitt trigger"] pub type PadGpio04CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_04_ctrl_st` writer - Schmitt trigger"] pub type PadGpio04CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_04_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio04CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_04_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio04CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_04_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio04CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_04_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio04CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_04_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio04CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_04_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio04CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_04_ctrl_pe` reader - Pull enable"] pub type PadGpio04CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_04_ctrl_pe` writer - Pull enable"] pub type PadGpio04CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_04_ctrl_ps` reader - Pull select"] pub type PadGpio04CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_04_ctrl_ps` writer - Pull select"] pub type PadGpio04CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_04_ctrl_ie` reader - Input enable"] pub type PadGpio04CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_04_ctrl_ie` writer - Input enable"] pub type PadGpio04CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_04_ctrl_st (& self) -> PadGpio04CtrlStR { PadGpio04CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_04_ctrl_ds0 (& self) -> PadGpio04CtrlDs0R { PadGpio04CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_04_ctrl_ds1 (& self) -> PadGpio04CtrlDs1R { PadGpio04CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_04_ctrl_ds2 (& self) -> PadGpio04CtrlDs2R { PadGpio04CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_04_ctrl_pe (& self) -> PadGpio04CtrlPeR { PadGpio04CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_04_ctrl_ps (& self) -> PadGpio04CtrlPsR { PadGpio04CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_04_ctrl_ie (& self) -> PadGpio04CtrlIeR { PadGpio04CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_04_ctrl_st (& mut self) -> PadGpio04CtrlStW < '_ , PadGpio04CtrlSpec > { PadGpio04CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_04_ctrl_ds0 (& mut self) -> PadGpio04CtrlDs0W < '_ , PadGpio04CtrlSpec > { PadGpio04CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_04_ctrl_ds1 (& mut self) -> PadGpio04CtrlDs1W < '_ , PadGpio04CtrlSpec > { PadGpio04CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_04_ctrl_ds2 (& mut self) -> PadGpio04CtrlDs2W < '_ , PadGpio04CtrlSpec > { PadGpio04CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_04_ctrl_pe (& mut self) -> PadGpio04CtrlPeW < '_ , PadGpio04CtrlSpec > { PadGpio04CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_04_ctrl_ps (& mut self) -> PadGpio04CtrlPsW < '_ , PadGpio04CtrlSpec > { PadGpio04CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_04_ctrl_ie (& mut self) -> PadGpio04CtrlIeW < '_ , PadGpio04CtrlSpec > { PadGpio04CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_04 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_04_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_04_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio04CtrlSpec ; impl crate :: RegisterSpec for PadGpio04CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_04_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio04CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_04_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio04CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_04_CTRL to value 0x0a00"] impl crate :: Resettable for PadGpio04CtrlSpec { const RESET_VALUE : u32 = 0x0a00 ; } }
#[doc = "PAD_GPIO_05_CTRL (rw) register accessor: GPIO_05 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_05_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_05_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_05_ctrl`] module"]
#[doc (alias = "PAD_GPIO_05_CTRL")] pub type PadGpio05Ctrl = crate :: Reg < pad_gpio_05_ctrl :: PadGpio05CtrlSpec > ;
#[doc = "GPIO_05 pad control register"] pub mod pad_gpio_05_ctrl {
#[doc = "Register `PAD_GPIO_05_CTRL` reader"] pub type R = crate :: R < PadGpio05CtrlSpec > ;
#[doc = "Register `PAD_GPIO_05_CTRL` writer"] pub type W = crate :: W < PadGpio05CtrlSpec > ;
#[doc = "Field `pad_gpio_05_ctrl_st` reader - Schmitt trigger"] pub type PadGpio05CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_05_ctrl_st` writer - Schmitt trigger"] pub type PadGpio05CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_05_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio05CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_05_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio05CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_05_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio05CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_05_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio05CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_05_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio05CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_05_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio05CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_05_ctrl_pe` reader - Pull enable"] pub type PadGpio05CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_05_ctrl_pe` writer - Pull enable"] pub type PadGpio05CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_05_ctrl_ps` reader - Pull select"] pub type PadGpio05CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_05_ctrl_ps` writer - Pull select"] pub type PadGpio05CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_05_ctrl_ie` reader - Input enable"] pub type PadGpio05CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_05_ctrl_ie` writer - Input enable"] pub type PadGpio05CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_05_ctrl_st (& self) -> PadGpio05CtrlStR { PadGpio05CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_05_ctrl_ds0 (& self) -> PadGpio05CtrlDs0R { PadGpio05CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_05_ctrl_ds1 (& self) -> PadGpio05CtrlDs1R { PadGpio05CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_05_ctrl_ds2 (& self) -> PadGpio05CtrlDs2R { PadGpio05CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_05_ctrl_pe (& self) -> PadGpio05CtrlPeR { PadGpio05CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_05_ctrl_ps (& self) -> PadGpio05CtrlPsR { PadGpio05CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_05_ctrl_ie (& self) -> PadGpio05CtrlIeR { PadGpio05CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_05_ctrl_st (& mut self) -> PadGpio05CtrlStW < '_ , PadGpio05CtrlSpec > { PadGpio05CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_05_ctrl_ds0 (& mut self) -> PadGpio05CtrlDs0W < '_ , PadGpio05CtrlSpec > { PadGpio05CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_05_ctrl_ds1 (& mut self) -> PadGpio05CtrlDs1W < '_ , PadGpio05CtrlSpec > { PadGpio05CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_05_ctrl_ds2 (& mut self) -> PadGpio05CtrlDs2W < '_ , PadGpio05CtrlSpec > { PadGpio05CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_05_ctrl_pe (& mut self) -> PadGpio05CtrlPeW < '_ , PadGpio05CtrlSpec > { PadGpio05CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_05_ctrl_ps (& mut self) -> PadGpio05CtrlPsW < '_ , PadGpio05CtrlSpec > { PadGpio05CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_05_ctrl_ie (& mut self) -> PadGpio05CtrlIeW < '_ , PadGpio05CtrlSpec > { PadGpio05CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_05 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_05_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_05_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio05CtrlSpec ; impl crate :: RegisterSpec for PadGpio05CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_05_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio05CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_05_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio05CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_05_CTRL to value 0x0820"] impl crate :: Resettable for PadGpio05CtrlSpec { const RESET_VALUE : u32 = 0x0820 ; } }
#[doc = "PAD_GPIO_06_CTRL (rw) register accessor: GPIO_06 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_06_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_06_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_06_ctrl`] module"]
#[doc (alias = "PAD_GPIO_06_CTRL")] pub type PadGpio06Ctrl = crate :: Reg < pad_gpio_06_ctrl :: PadGpio06CtrlSpec > ;
#[doc = "GPIO_06 pad control register"] pub mod pad_gpio_06_ctrl {
#[doc = "Register `PAD_GPIO_06_CTRL` reader"] pub type R = crate :: R < PadGpio06CtrlSpec > ;
#[doc = "Register `PAD_GPIO_06_CTRL` writer"] pub type W = crate :: W < PadGpio06CtrlSpec > ;
#[doc = "Field `pad_gpio_06_ctrl_st` reader - Schmitt trigger"] pub type PadGpio06CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_06_ctrl_st` writer - Schmitt trigger"] pub type PadGpio06CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_06_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio06CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_06_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio06CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_06_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio06CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_06_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio06CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_06_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio06CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_06_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio06CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_06_ctrl_pe` reader - Pull enable"] pub type PadGpio06CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_06_ctrl_pe` writer - Pull enable"] pub type PadGpio06CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_06_ctrl_ps` reader - Pull select"] pub type PadGpio06CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_06_ctrl_ps` writer - Pull select"] pub type PadGpio06CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_06_ctrl_ie` reader - Input enable"] pub type PadGpio06CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_06_ctrl_ie` writer - Input enable"] pub type PadGpio06CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_06_ctrl_st (& self) -> PadGpio06CtrlStR { PadGpio06CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_06_ctrl_ds0 (& self) -> PadGpio06CtrlDs0R { PadGpio06CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_06_ctrl_ds1 (& self) -> PadGpio06CtrlDs1R { PadGpio06CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_06_ctrl_ds2 (& self) -> PadGpio06CtrlDs2R { PadGpio06CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_06_ctrl_pe (& self) -> PadGpio06CtrlPeR { PadGpio06CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_06_ctrl_ps (& self) -> PadGpio06CtrlPsR { PadGpio06CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_06_ctrl_ie (& self) -> PadGpio06CtrlIeR { PadGpio06CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_06_ctrl_st (& mut self) -> PadGpio06CtrlStW < '_ , PadGpio06CtrlSpec > { PadGpio06CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_06_ctrl_ds0 (& mut self) -> PadGpio06CtrlDs0W < '_ , PadGpio06CtrlSpec > { PadGpio06CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_06_ctrl_ds1 (& mut self) -> PadGpio06CtrlDs1W < '_ , PadGpio06CtrlSpec > { PadGpio06CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_06_ctrl_ds2 (& mut self) -> PadGpio06CtrlDs2W < '_ , PadGpio06CtrlSpec > { PadGpio06CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_06_ctrl_pe (& mut self) -> PadGpio06CtrlPeW < '_ , PadGpio06CtrlSpec > { PadGpio06CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_06_ctrl_ps (& mut self) -> PadGpio06CtrlPsW < '_ , PadGpio06CtrlSpec > { PadGpio06CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_06_ctrl_ie (& mut self) -> PadGpio06CtrlIeW < '_ , PadGpio06CtrlSpec > { PadGpio06CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_06 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_06_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_06_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio06CtrlSpec ; impl crate :: RegisterSpec for PadGpio06CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_06_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio06CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_06_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio06CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_06_CTRL to value 0x0a00"] impl crate :: Resettable for PadGpio06CtrlSpec { const RESET_VALUE : u32 = 0x0a00 ; } }
#[doc = "PAD_GPIO_07_CTRL (rw) register accessor: GPIO_07 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_07_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_07_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_07_ctrl`] module"]
#[doc (alias = "PAD_GPIO_07_CTRL")] pub type PadGpio07Ctrl = crate :: Reg < pad_gpio_07_ctrl :: PadGpio07CtrlSpec > ;
#[doc = "GPIO_07 pad control register"] pub mod pad_gpio_07_ctrl {
#[doc = "Register `PAD_GPIO_07_CTRL` reader"] pub type R = crate :: R < PadGpio07CtrlSpec > ;
#[doc = "Register `PAD_GPIO_07_CTRL` writer"] pub type W = crate :: W < PadGpio07CtrlSpec > ;
#[doc = "Field `pad_gpio_07_ctrl_st` reader - Schmitt trigger"] pub type PadGpio07CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_07_ctrl_st` writer - Schmitt trigger"] pub type PadGpio07CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_07_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio07CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_07_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio07CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_07_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio07CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_07_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio07CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_07_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio07CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_07_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio07CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_07_ctrl_pe` reader - Pull enable"] pub type PadGpio07CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_07_ctrl_pe` writer - Pull enable"] pub type PadGpio07CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_07_ctrl_ps` reader - Pull select"] pub type PadGpio07CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_07_ctrl_ps` writer - Pull select"] pub type PadGpio07CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_07_ctrl_ie` reader - Input enable"] pub type PadGpio07CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_07_ctrl_ie` writer - Input enable"] pub type PadGpio07CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_07_ctrl_st (& self) -> PadGpio07CtrlStR { PadGpio07CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_07_ctrl_ds0 (& self) -> PadGpio07CtrlDs0R { PadGpio07CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_07_ctrl_ds1 (& self) -> PadGpio07CtrlDs1R { PadGpio07CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_07_ctrl_ds2 (& self) -> PadGpio07CtrlDs2R { PadGpio07CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_07_ctrl_pe (& self) -> PadGpio07CtrlPeR { PadGpio07CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_07_ctrl_ps (& self) -> PadGpio07CtrlPsR { PadGpio07CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_07_ctrl_ie (& self) -> PadGpio07CtrlIeR { PadGpio07CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_07_ctrl_st (& mut self) -> PadGpio07CtrlStW < '_ , PadGpio07CtrlSpec > { PadGpio07CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_07_ctrl_ds0 (& mut self) -> PadGpio07CtrlDs0W < '_ , PadGpio07CtrlSpec > { PadGpio07CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_07_ctrl_ds1 (& mut self) -> PadGpio07CtrlDs1W < '_ , PadGpio07CtrlSpec > { PadGpio07CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_07_ctrl_ds2 (& mut self) -> PadGpio07CtrlDs2W < '_ , PadGpio07CtrlSpec > { PadGpio07CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_07_ctrl_pe (& mut self) -> PadGpio07CtrlPeW < '_ , PadGpio07CtrlSpec > { PadGpio07CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_07_ctrl_ps (& mut self) -> PadGpio07CtrlPsW < '_ , PadGpio07CtrlSpec > { PadGpio07CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_07_ctrl_ie (& mut self) -> PadGpio07CtrlIeW < '_ , PadGpio07CtrlSpec > { PadGpio07CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_07 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_07_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_07_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio07CtrlSpec ; impl crate :: RegisterSpec for PadGpio07CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_07_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio07CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_07_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio07CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_07_CTRL to value 0x0800"] impl crate :: Resettable for PadGpio07CtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_GPIO_08_CTRL (rw) register accessor: GPIO_08 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_08_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_08_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_08_ctrl`] module"]
#[doc (alias = "PAD_GPIO_08_CTRL")] pub type PadGpio08Ctrl = crate :: Reg < pad_gpio_08_ctrl :: PadGpio08CtrlSpec > ;
#[doc = "GPIO_08 pad control register"] pub mod pad_gpio_08_ctrl {
#[doc = "Register `PAD_GPIO_08_CTRL` reader"] pub type R = crate :: R < PadGpio08CtrlSpec > ;
#[doc = "Register `PAD_GPIO_08_CTRL` writer"] pub type W = crate :: W < PadGpio08CtrlSpec > ;
#[doc = "Field `pad_gpio_08_ctrl_st` reader - Schmitt trigger"] pub type PadGpio08CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_08_ctrl_st` writer - Schmitt trigger"] pub type PadGpio08CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_08_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio08CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_08_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio08CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_08_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio08CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_08_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio08CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_08_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio08CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_08_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio08CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_08_ctrl_pe` reader - Pull enable"] pub type PadGpio08CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_08_ctrl_pe` writer - Pull enable"] pub type PadGpio08CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_08_ctrl_ps` reader - Pull select"] pub type PadGpio08CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_08_ctrl_ps` writer - Pull select"] pub type PadGpio08CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_08_ctrl_ie` reader - Input enable"] pub type PadGpio08CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_08_ctrl_ie` writer - Input enable"] pub type PadGpio08CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_08_ctrl_st (& self) -> PadGpio08CtrlStR { PadGpio08CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_08_ctrl_ds0 (& self) -> PadGpio08CtrlDs0R { PadGpio08CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_08_ctrl_ds1 (& self) -> PadGpio08CtrlDs1R { PadGpio08CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_08_ctrl_ds2 (& self) -> PadGpio08CtrlDs2R { PadGpio08CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_08_ctrl_pe (& self) -> PadGpio08CtrlPeR { PadGpio08CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_08_ctrl_ps (& self) -> PadGpio08CtrlPsR { PadGpio08CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_08_ctrl_ie (& self) -> PadGpio08CtrlIeR { PadGpio08CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_08_ctrl_st (& mut self) -> PadGpio08CtrlStW < '_ , PadGpio08CtrlSpec > { PadGpio08CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_08_ctrl_ds0 (& mut self) -> PadGpio08CtrlDs0W < '_ , PadGpio08CtrlSpec > { PadGpio08CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_08_ctrl_ds1 (& mut self) -> PadGpio08CtrlDs1W < '_ , PadGpio08CtrlSpec > { PadGpio08CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_08_ctrl_ds2 (& mut self) -> PadGpio08CtrlDs2W < '_ , PadGpio08CtrlSpec > { PadGpio08CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_08_ctrl_pe (& mut self) -> PadGpio08CtrlPeW < '_ , PadGpio08CtrlSpec > { PadGpio08CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_08_ctrl_ps (& mut self) -> PadGpio08CtrlPsW < '_ , PadGpio08CtrlSpec > { PadGpio08CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_08_ctrl_ie (& mut self) -> PadGpio08CtrlIeW < '_ , PadGpio08CtrlSpec > { PadGpio08CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_08 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_08_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_08_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio08CtrlSpec ; impl crate :: RegisterSpec for PadGpio08CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_08_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio08CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_08_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio08CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_08_CTRL to value 0x0800"] impl crate :: Resettable for PadGpio08CtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_GPIO_09_CTRL (rw) register accessor: GPIO_09 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_09_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_09_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_09_ctrl`] module"]
#[doc (alias = "PAD_GPIO_09_CTRL")] pub type PadGpio09Ctrl = crate :: Reg < pad_gpio_09_ctrl :: PadGpio09CtrlSpec > ;
#[doc = "GPIO_09 pad control register"] pub mod pad_gpio_09_ctrl {
#[doc = "Register `PAD_GPIO_09_CTRL` reader"] pub type R = crate :: R < PadGpio09CtrlSpec > ;
#[doc = "Register `PAD_GPIO_09_CTRL` writer"] pub type W = crate :: W < PadGpio09CtrlSpec > ;
#[doc = "Field `pad_gpio_09_ctrl_st` reader - Schmitt trigger"] pub type PadGpio09CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_09_ctrl_st` writer - Schmitt trigger"] pub type PadGpio09CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_09_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio09CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_09_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio09CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_09_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio09CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_09_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio09CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_09_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio09CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_09_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio09CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_09_ctrl_pe` reader - Pull enable"] pub type PadGpio09CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_09_ctrl_pe` writer - Pull enable"] pub type PadGpio09CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_09_ctrl_ps` reader - Pull select"] pub type PadGpio09CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_09_ctrl_ps` writer - Pull select"] pub type PadGpio09CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_09_ctrl_ie` reader - Input enable"] pub type PadGpio09CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_09_ctrl_ie` writer - Input enable"] pub type PadGpio09CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_09_ctrl_st (& self) -> PadGpio09CtrlStR { PadGpio09CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_09_ctrl_ds0 (& self) -> PadGpio09CtrlDs0R { PadGpio09CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_09_ctrl_ds1 (& self) -> PadGpio09CtrlDs1R { PadGpio09CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_09_ctrl_ds2 (& self) -> PadGpio09CtrlDs2R { PadGpio09CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_09_ctrl_pe (& self) -> PadGpio09CtrlPeR { PadGpio09CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_09_ctrl_ps (& self) -> PadGpio09CtrlPsR { PadGpio09CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_09_ctrl_ie (& self) -> PadGpio09CtrlIeR { PadGpio09CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_09_ctrl_st (& mut self) -> PadGpio09CtrlStW < '_ , PadGpio09CtrlSpec > { PadGpio09CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_09_ctrl_ds0 (& mut self) -> PadGpio09CtrlDs0W < '_ , PadGpio09CtrlSpec > { PadGpio09CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_09_ctrl_ds1 (& mut self) -> PadGpio09CtrlDs1W < '_ , PadGpio09CtrlSpec > { PadGpio09CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_09_ctrl_ds2 (& mut self) -> PadGpio09CtrlDs2W < '_ , PadGpio09CtrlSpec > { PadGpio09CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_09_ctrl_pe (& mut self) -> PadGpio09CtrlPeW < '_ , PadGpio09CtrlSpec > { PadGpio09CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_09_ctrl_ps (& mut self) -> PadGpio09CtrlPsW < '_ , PadGpio09CtrlSpec > { PadGpio09CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_09_ctrl_ie (& mut self) -> PadGpio09CtrlIeW < '_ , PadGpio09CtrlSpec > { PadGpio09CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_09 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_09_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_09_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio09CtrlSpec ; impl crate :: RegisterSpec for PadGpio09CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_09_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio09CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_09_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio09CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_09_CTRL to value 0x0a00"] impl crate :: Resettable for PadGpio09CtrlSpec { const RESET_VALUE : u32 = 0x0a00 ; } }
#[doc = "PAD_GPIO_10_CTRL (rw) register accessor: GPIO_10 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_10_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_10_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_10_ctrl`] module"]
#[doc (alias = "PAD_GPIO_10_CTRL")] pub type PadGpio10Ctrl = crate :: Reg < pad_gpio_10_ctrl :: PadGpio10CtrlSpec > ;
#[doc = "GPIO_10 pad control register"] pub mod pad_gpio_10_ctrl {
#[doc = "Register `PAD_GPIO_10_CTRL` reader"] pub type R = crate :: R < PadGpio10CtrlSpec > ;
#[doc = "Register `PAD_GPIO_10_CTRL` writer"] pub type W = crate :: W < PadGpio10CtrlSpec > ;
#[doc = "Field `pad_gpio_10_ctrl_st` reader - Schmitt trigger"] pub type PadGpio10CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_10_ctrl_st` writer - Schmitt trigger"] pub type PadGpio10CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_10_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio10CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_10_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio10CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_10_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio10CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_10_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio10CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_10_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio10CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_10_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio10CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_10_ctrl_pe` reader - Pull enable"] pub type PadGpio10CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_10_ctrl_pe` writer - Pull enable"] pub type PadGpio10CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_10_ctrl_ps` reader - Pull select"] pub type PadGpio10CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_10_ctrl_ps` writer - Pull select"] pub type PadGpio10CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_10_ctrl_ie` reader - Input enable"] pub type PadGpio10CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_10_ctrl_ie` writer - Input enable"] pub type PadGpio10CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_10_ctrl_st (& self) -> PadGpio10CtrlStR { PadGpio10CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_10_ctrl_ds0 (& self) -> PadGpio10CtrlDs0R { PadGpio10CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_10_ctrl_ds1 (& self) -> PadGpio10CtrlDs1R { PadGpio10CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_10_ctrl_ds2 (& self) -> PadGpio10CtrlDs2R { PadGpio10CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_10_ctrl_pe (& self) -> PadGpio10CtrlPeR { PadGpio10CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_10_ctrl_ps (& self) -> PadGpio10CtrlPsR { PadGpio10CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_10_ctrl_ie (& self) -> PadGpio10CtrlIeR { PadGpio10CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_10_ctrl_st (& mut self) -> PadGpio10CtrlStW < '_ , PadGpio10CtrlSpec > { PadGpio10CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_10_ctrl_ds0 (& mut self) -> PadGpio10CtrlDs0W < '_ , PadGpio10CtrlSpec > { PadGpio10CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_10_ctrl_ds1 (& mut self) -> PadGpio10CtrlDs1W < '_ , PadGpio10CtrlSpec > { PadGpio10CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_10_ctrl_ds2 (& mut self) -> PadGpio10CtrlDs2W < '_ , PadGpio10CtrlSpec > { PadGpio10CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_10_ctrl_pe (& mut self) -> PadGpio10CtrlPeW < '_ , PadGpio10CtrlSpec > { PadGpio10CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_10_ctrl_ps (& mut self) -> PadGpio10CtrlPsW < '_ , PadGpio10CtrlSpec > { PadGpio10CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_10_ctrl_ie (& mut self) -> PadGpio10CtrlIeW < '_ , PadGpio10CtrlSpec > { PadGpio10CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_10 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_10_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_10_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio10CtrlSpec ; impl crate :: RegisterSpec for PadGpio10CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_10_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio10CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_10_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio10CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_10_CTRL to value 0x0800"] impl crate :: Resettable for PadGpio10CtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_GPIO_11_CTRL (rw) register accessor: GPIO_11 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_11_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_11_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_11_ctrl`] module"]
#[doc (alias = "PAD_GPIO_11_CTRL")] pub type PadGpio11Ctrl = crate :: Reg < pad_gpio_11_ctrl :: PadGpio11CtrlSpec > ;
#[doc = "GPIO_11 pad control register"] pub mod pad_gpio_11_ctrl {
#[doc = "Register `PAD_GPIO_11_CTRL` reader"] pub type R = crate :: R < PadGpio11CtrlSpec > ;
#[doc = "Register `PAD_GPIO_11_CTRL` writer"] pub type W = crate :: W < PadGpio11CtrlSpec > ;
#[doc = "Field `pad_gpio_11_ctrl_st` reader - Schmitt trigger"] pub type PadGpio11CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_11_ctrl_st` writer - Schmitt trigger"] pub type PadGpio11CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_11_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio11CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_11_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio11CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_11_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio11CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_11_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio11CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_11_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio11CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_11_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio11CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_11_ctrl_pe` reader - Pull enable"] pub type PadGpio11CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_11_ctrl_pe` writer - Pull enable"] pub type PadGpio11CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_11_ctrl_ps` reader - Pull select"] pub type PadGpio11CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_11_ctrl_ps` writer - Pull select"] pub type PadGpio11CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_11_ctrl_ie` reader - Input enable"] pub type PadGpio11CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_11_ctrl_ie` writer - Input enable"] pub type PadGpio11CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_11_ctrl_st (& self) -> PadGpio11CtrlStR { PadGpio11CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_11_ctrl_ds0 (& self) -> PadGpio11CtrlDs0R { PadGpio11CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_11_ctrl_ds1 (& self) -> PadGpio11CtrlDs1R { PadGpio11CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_11_ctrl_ds2 (& self) -> PadGpio11CtrlDs2R { PadGpio11CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_11_ctrl_pe (& self) -> PadGpio11CtrlPeR { PadGpio11CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_11_ctrl_ps (& self) -> PadGpio11CtrlPsR { PadGpio11CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_11_ctrl_ie (& self) -> PadGpio11CtrlIeR { PadGpio11CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_11_ctrl_st (& mut self) -> PadGpio11CtrlStW < '_ , PadGpio11CtrlSpec > { PadGpio11CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_11_ctrl_ds0 (& mut self) -> PadGpio11CtrlDs0W < '_ , PadGpio11CtrlSpec > { PadGpio11CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_11_ctrl_ds1 (& mut self) -> PadGpio11CtrlDs1W < '_ , PadGpio11CtrlSpec > { PadGpio11CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_11_ctrl_ds2 (& mut self) -> PadGpio11CtrlDs2W < '_ , PadGpio11CtrlSpec > { PadGpio11CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_11_ctrl_pe (& mut self) -> PadGpio11CtrlPeW < '_ , PadGpio11CtrlSpec > { PadGpio11CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_11_ctrl_ps (& mut self) -> PadGpio11CtrlPsW < '_ , PadGpio11CtrlSpec > { PadGpio11CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_11_ctrl_ie (& mut self) -> PadGpio11CtrlIeW < '_ , PadGpio11CtrlSpec > { PadGpio11CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_11 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_11_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_11_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio11CtrlSpec ; impl crate :: RegisterSpec for PadGpio11CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_11_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio11CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_11_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio11CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_11_CTRL to value 0x0a00"] impl crate :: Resettable for PadGpio11CtrlSpec { const RESET_VALUE : u32 = 0x0a00 ; } }
#[doc = "PAD_GPIO_12_CTRL (rw) register accessor: GPIO_12 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_12_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_12_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_12_ctrl`] module"]
#[doc (alias = "PAD_GPIO_12_CTRL")] pub type PadGpio12Ctrl = crate :: Reg < pad_gpio_12_ctrl :: PadGpio12CtrlSpec > ;
#[doc = "GPIO_12 pad control register"] pub mod pad_gpio_12_ctrl {
#[doc = "Register `PAD_GPIO_12_CTRL` reader"] pub type R = crate :: R < PadGpio12CtrlSpec > ;
#[doc = "Register `PAD_GPIO_12_CTRL` writer"] pub type W = crate :: W < PadGpio12CtrlSpec > ;
#[doc = "Field `pad_gpio_12_ctrl_st` reader - Schmitt trigger"] pub type PadGpio12CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_12_ctrl_st` writer - Schmitt trigger"] pub type PadGpio12CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_12_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio12CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_12_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio12CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_12_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio12CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_12_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio12CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_12_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio12CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_12_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio12CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_12_ctrl_pe` reader - Pull enable"] pub type PadGpio12CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_12_ctrl_pe` writer - Pull enable"] pub type PadGpio12CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_12_ctrl_ps` reader - Pull select"] pub type PadGpio12CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_12_ctrl_ps` writer - Pull select"] pub type PadGpio12CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_12_ctrl_ie` reader - Input enable"] pub type PadGpio12CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_12_ctrl_ie` writer - Input enable"] pub type PadGpio12CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_12_ctrl_st (& self) -> PadGpio12CtrlStR { PadGpio12CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_12_ctrl_ds0 (& self) -> PadGpio12CtrlDs0R { PadGpio12CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_12_ctrl_ds1 (& self) -> PadGpio12CtrlDs1R { PadGpio12CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_12_ctrl_ds2 (& self) -> PadGpio12CtrlDs2R { PadGpio12CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_12_ctrl_pe (& self) -> PadGpio12CtrlPeR { PadGpio12CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_12_ctrl_ps (& self) -> PadGpio12CtrlPsR { PadGpio12CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_12_ctrl_ie (& self) -> PadGpio12CtrlIeR { PadGpio12CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_12_ctrl_st (& mut self) -> PadGpio12CtrlStW < '_ , PadGpio12CtrlSpec > { PadGpio12CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_12_ctrl_ds0 (& mut self) -> PadGpio12CtrlDs0W < '_ , PadGpio12CtrlSpec > { PadGpio12CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_12_ctrl_ds1 (& mut self) -> PadGpio12CtrlDs1W < '_ , PadGpio12CtrlSpec > { PadGpio12CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_12_ctrl_ds2 (& mut self) -> PadGpio12CtrlDs2W < '_ , PadGpio12CtrlSpec > { PadGpio12CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_12_ctrl_pe (& mut self) -> PadGpio12CtrlPeW < '_ , PadGpio12CtrlSpec > { PadGpio12CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_12_ctrl_ps (& mut self) -> PadGpio12CtrlPsW < '_ , PadGpio12CtrlSpec > { PadGpio12CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_12_ctrl_ie (& mut self) -> PadGpio12CtrlIeW < '_ , PadGpio12CtrlSpec > { PadGpio12CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_12 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_12_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_12_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio12CtrlSpec ; impl crate :: RegisterSpec for PadGpio12CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_12_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio12CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_12_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio12CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_12_CTRL to value 0x0a00"] impl crate :: Resettable for PadGpio12CtrlSpec { const RESET_VALUE : u32 = 0x0a00 ; } }
#[doc = "PAD_GPIO_13_CTRL (rw) register accessor: GPIO_13 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_13_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_13_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_13_ctrl`] module"]
#[doc (alias = "PAD_GPIO_13_CTRL")] pub type PadGpio13Ctrl = crate :: Reg < pad_gpio_13_ctrl :: PadGpio13CtrlSpec > ;
#[doc = "GPIO_13 pad control register"] pub mod pad_gpio_13_ctrl {
#[doc = "Register `PAD_GPIO_13_CTRL` reader"] pub type R = crate :: R < PadGpio13CtrlSpec > ;
#[doc = "Register `PAD_GPIO_13_CTRL` writer"] pub type W = crate :: W < PadGpio13CtrlSpec > ;
#[doc = "Field `pad_gpio_13_ctrl_st` reader - Schmitt trigger"] pub type PadGpio13CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_13_ctrl_st` writer - Schmitt trigger"] pub type PadGpio13CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_13_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio13CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_13_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio13CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_13_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio13CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_13_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio13CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_13_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio13CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_13_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio13CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_13_ctrl_pe` reader - Pull enable"] pub type PadGpio13CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_13_ctrl_pe` writer - Pull enable"] pub type PadGpio13CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_13_ctrl_ps` reader - Pull select"] pub type PadGpio13CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_13_ctrl_ps` writer - Pull select"] pub type PadGpio13CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_13_ctrl_ie` reader - Input enable"] pub type PadGpio13CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_13_ctrl_ie` writer - Input enable"] pub type PadGpio13CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_13_ctrl_st (& self) -> PadGpio13CtrlStR { PadGpio13CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_13_ctrl_ds0 (& self) -> PadGpio13CtrlDs0R { PadGpio13CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_13_ctrl_ds1 (& self) -> PadGpio13CtrlDs1R { PadGpio13CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_13_ctrl_ds2 (& self) -> PadGpio13CtrlDs2R { PadGpio13CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_13_ctrl_pe (& self) -> PadGpio13CtrlPeR { PadGpio13CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_13_ctrl_ps (& self) -> PadGpio13CtrlPsR { PadGpio13CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_13_ctrl_ie (& self) -> PadGpio13CtrlIeR { PadGpio13CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_13_ctrl_st (& mut self) -> PadGpio13CtrlStW < '_ , PadGpio13CtrlSpec > { PadGpio13CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_13_ctrl_ds0 (& mut self) -> PadGpio13CtrlDs0W < '_ , PadGpio13CtrlSpec > { PadGpio13CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_13_ctrl_ds1 (& mut self) -> PadGpio13CtrlDs1W < '_ , PadGpio13CtrlSpec > { PadGpio13CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_13_ctrl_ds2 (& mut self) -> PadGpio13CtrlDs2W < '_ , PadGpio13CtrlSpec > { PadGpio13CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_13_ctrl_pe (& mut self) -> PadGpio13CtrlPeW < '_ , PadGpio13CtrlSpec > { PadGpio13CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_13_ctrl_ps (& mut self) -> PadGpio13CtrlPsW < '_ , PadGpio13CtrlSpec > { PadGpio13CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_13_ctrl_ie (& mut self) -> PadGpio13CtrlIeW < '_ , PadGpio13CtrlSpec > { PadGpio13CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_13 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_13_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_13_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio13CtrlSpec ; impl crate :: RegisterSpec for PadGpio13CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_13_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio13CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_13_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio13CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_13_CTRL to value 0x0800"] impl crate :: Resettable for PadGpio13CtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_GPIO_14_CTRL (rw) register accessor: GPIO_14 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_14_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_14_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_gpio_14_ctrl`] module"]
#[doc (alias = "PAD_GPIO_14_CTRL")] pub type PadGpio14Ctrl = crate :: Reg < pad_gpio_14_ctrl :: PadGpio14CtrlSpec > ;
#[doc = "GPIO_14 pad control register"] pub mod pad_gpio_14_ctrl {
#[doc = "Register `PAD_GPIO_14_CTRL` reader"] pub type R = crate :: R < PadGpio14CtrlSpec > ;
#[doc = "Register `PAD_GPIO_14_CTRL` writer"] pub type W = crate :: W < PadGpio14CtrlSpec > ;
#[doc = "Field `pad_gpio_14_ctrl_st` reader - Schmitt trigger"] pub type PadGpio14CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_gpio_14_ctrl_st` writer - Schmitt trigger"] pub type PadGpio14CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_14_ctrl_ds0` reader - Drive strength bit 0"] pub type PadGpio14CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_gpio_14_ctrl_ds0` writer - Drive strength bit 0"] pub type PadGpio14CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_14_ctrl_ds1` reader - Drive strength bit 1"] pub type PadGpio14CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_gpio_14_ctrl_ds1` writer - Drive strength bit 1"] pub type PadGpio14CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_14_ctrl_ds2` reader - Drive strength bit 2"] pub type PadGpio14CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_gpio_14_ctrl_ds2` writer - Drive strength bit 2"] pub type PadGpio14CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_14_ctrl_pe` reader - Pull enable"] pub type PadGpio14CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_14_ctrl_pe` writer - Pull enable"] pub type PadGpio14CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_14_ctrl_ps` reader - Pull select"] pub type PadGpio14CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_gpio_14_ctrl_ps` writer - Pull select"] pub type PadGpio14CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_gpio_14_ctrl_ie` reader - Input enable"] pub type PadGpio14CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_gpio_14_ctrl_ie` writer - Input enable"] pub type PadGpio14CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_14_ctrl_st (& self) -> PadGpio14CtrlStR { PadGpio14CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_14_ctrl_ds0 (& self) -> PadGpio14CtrlDs0R { PadGpio14CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_14_ctrl_ds1 (& self) -> PadGpio14CtrlDs1R { PadGpio14CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_14_ctrl_ds2 (& self) -> PadGpio14CtrlDs2R { PadGpio14CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_14_ctrl_pe (& self) -> PadGpio14CtrlPeR { PadGpio14CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_14_ctrl_ps (& self) -> PadGpio14CtrlPsR { PadGpio14CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_14_ctrl_ie (& self) -> PadGpio14CtrlIeR { PadGpio14CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_gpio_14_ctrl_st (& mut self) -> PadGpio14CtrlStW < '_ , PadGpio14CtrlSpec > { PadGpio14CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_gpio_14_ctrl_ds0 (& mut self) -> PadGpio14CtrlDs0W < '_ , PadGpio14CtrlSpec > { PadGpio14CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_gpio_14_ctrl_ds1 (& mut self) -> PadGpio14CtrlDs1W < '_ , PadGpio14CtrlSpec > { PadGpio14CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_gpio_14_ctrl_ds2 (& mut self) -> PadGpio14CtrlDs2W < '_ , PadGpio14CtrlSpec > { PadGpio14CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_gpio_14_ctrl_pe (& mut self) -> PadGpio14CtrlPeW < '_ , PadGpio14CtrlSpec > { PadGpio14CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_gpio_14_ctrl_ps (& mut self) -> PadGpio14CtrlPsW < '_ , PadGpio14CtrlSpec > { PadGpio14CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_gpio_14_ctrl_ie (& mut self) -> PadGpio14CtrlIeW < '_ , PadGpio14CtrlSpec > { PadGpio14CtrlIeW :: new (self , 11) } }
#[doc = "GPIO_14 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_gpio_14_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_gpio_14_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadGpio14CtrlSpec ; impl crate :: RegisterSpec for PadGpio14CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_gpio_14_ctrl::R`](R) reader structure"] impl crate :: Readable for PadGpio14CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_gpio_14_ctrl::W`](W) writer structure"] impl crate :: Writable for PadGpio14CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_GPIO_14_CTRL to value 0x0800"] impl crate :: Resettable for PadGpio14CtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_UART1_TXD_CTRL (rw) register accessor: UART1_TXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart1_txd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart1_txd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_uart1_txd_ctrl`] module"]
#[doc (alias = "PAD_UART1_TXD_CTRL")] pub type PadUart1TxdCtrl = crate :: Reg < pad_uart1_txd_ctrl :: PadUart1TxdCtrlSpec > ;
#[doc = "UART1_TXD pad control register"] pub mod pad_uart1_txd_ctrl {
#[doc = "Register `PAD_UART1_TXD_CTRL` reader"] pub type R = crate :: R < PadUart1TxdCtrlSpec > ;
#[doc = "Register `PAD_UART1_TXD_CTRL` writer"] pub type W = crate :: W < PadUart1TxdCtrlSpec > ;
#[doc = "Field `pad_uart1_txd_ctrl_st` reader - Schmitt trigger"] pub type PadUart1TxdCtrlStR = crate :: BitReader ;
#[doc = "Field `pad_uart1_txd_ctrl_st` writer - Schmitt trigger"] pub type PadUart1TxdCtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_uart1_txd_ctrl_ie` reader - Input enable"] pub type PadUart1TxdCtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_uart1_txd_ctrl_ie` writer - Input enable"] pub type PadUart1TxdCtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_uart1_txd_ctrl_st (& self) -> PadUart1TxdCtrlStR { PadUart1TxdCtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_uart1_txd_ctrl_ie (& self) -> PadUart1TxdCtrlIeR { PadUart1TxdCtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_uart1_txd_ctrl_st (& mut self) -> PadUart1TxdCtrlStW < '_ , PadUart1TxdCtrlSpec > { PadUart1TxdCtrlStW :: new (self , 3) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_uart1_txd_ctrl_ie (& mut self) -> PadUart1TxdCtrlIeW < '_ , PadUart1TxdCtrlSpec > { PadUart1TxdCtrlIeW :: new (self , 11) } }
#[doc = "UART1_TXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart1_txd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart1_txd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadUart1TxdCtrlSpec ; impl crate :: RegisterSpec for PadUart1TxdCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_uart1_txd_ctrl::R`](R) reader structure"] impl crate :: Readable for PadUart1TxdCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_uart1_txd_ctrl::W`](W) writer structure"] impl crate :: Writable for PadUart1TxdCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_UART1_TXD_CTRL to value 0x0800"] impl crate :: Resettable for PadUart1TxdCtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_UART1_RXD_CTRL (rw) register accessor: UART1_RXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart1_rxd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart1_rxd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_uart1_rxd_ctrl`] module"]
#[doc (alias = "PAD_UART1_RXD_CTRL")] pub type PadUart1RxdCtrl = crate :: Reg < pad_uart1_rxd_ctrl :: PadUart1RxdCtrlSpec > ;
#[doc = "UART1_RXD pad control register"] pub mod pad_uart1_rxd_ctrl {
#[doc = "Register `PAD_UART1_RXD_CTRL` reader"] pub type R = crate :: R < PadUart1RxdCtrlSpec > ;
#[doc = "Register `PAD_UART1_RXD_CTRL` writer"] pub type W = crate :: W < PadUart1RxdCtrlSpec > ;
#[doc = "Field `pad_uart1_rxd_ctrl_st` reader - Schmitt trigger"] pub type PadUart1RxdCtrlStR = crate :: BitReader ;
#[doc = "Field `pad_uart1_rxd_ctrl_st` writer - Schmitt trigger"] pub type PadUart1RxdCtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_uart1_rxd_ctrl_ie` reader - Input enable"] pub type PadUart1RxdCtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_uart1_rxd_ctrl_ie` writer - Input enable"] pub type PadUart1RxdCtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_uart1_rxd_ctrl_st (& self) -> PadUart1RxdCtrlStR { PadUart1RxdCtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_uart1_rxd_ctrl_ie (& self) -> PadUart1RxdCtrlIeR { PadUart1RxdCtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_uart1_rxd_ctrl_st (& mut self) -> PadUart1RxdCtrlStW < '_ , PadUart1RxdCtrlSpec > { PadUart1RxdCtrlStW :: new (self , 3) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_uart1_rxd_ctrl_ie (& mut self) -> PadUart1RxdCtrlIeW < '_ , PadUart1RxdCtrlSpec > { PadUart1RxdCtrlIeW :: new (self , 11) } }
#[doc = "UART1_RXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart1_rxd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart1_rxd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadUart1RxdCtrlSpec ; impl crate :: RegisterSpec for PadUart1RxdCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_uart1_rxd_ctrl::R`](R) reader structure"] impl crate :: Readable for PadUart1RxdCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_uart1_rxd_ctrl::W`](W) writer structure"] impl crate :: Writable for PadUart1RxdCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_UART1_RXD_CTRL to value 0x0800"] impl crate :: Resettable for PadUart1RxdCtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_UART0_TXD_CTRL (rw) register accessor: UART0_TXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart0_txd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart0_txd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_uart0_txd_ctrl`] module"]
#[doc (alias = "PAD_UART0_TXD_CTRL")] pub type PadUart0TxdCtrl = crate :: Reg < pad_uart0_txd_ctrl :: PadUart0TxdCtrlSpec > ;
#[doc = "UART0_TXD pad control register"] pub mod pad_uart0_txd_ctrl {
#[doc = "Register `PAD_UART0_TXD_CTRL` reader"] pub type R = crate :: R < PadUart0TxdCtrlSpec > ;
#[doc = "Register `PAD_UART0_TXD_CTRL` writer"] pub type W = crate :: W < PadUart0TxdCtrlSpec > ;
#[doc = "Field `pad_uart0_txd_ctrl_st` reader - Schmitt trigger"] pub type PadUart0TxdCtrlStR = crate :: BitReader ;
#[doc = "Field `pad_uart0_txd_ctrl_st` writer - Schmitt trigger"] pub type PadUart0TxdCtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_uart0_txd_ctrl_ie` reader - Input enable"] pub type PadUart0TxdCtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_uart0_txd_ctrl_ie` writer - Input enable"] pub type PadUart0TxdCtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_uart0_txd_ctrl_st (& self) -> PadUart0TxdCtrlStR { PadUart0TxdCtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_uart0_txd_ctrl_ie (& self) -> PadUart0TxdCtrlIeR { PadUart0TxdCtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_uart0_txd_ctrl_st (& mut self) -> PadUart0TxdCtrlStW < '_ , PadUart0TxdCtrlSpec > { PadUart0TxdCtrlStW :: new (self , 3) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_uart0_txd_ctrl_ie (& mut self) -> PadUart0TxdCtrlIeW < '_ , PadUart0TxdCtrlSpec > { PadUart0TxdCtrlIeW :: new (self , 11) } }
#[doc = "UART0_TXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart0_txd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart0_txd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadUart0TxdCtrlSpec ; impl crate :: RegisterSpec for PadUart0TxdCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_uart0_txd_ctrl::R`](R) reader structure"] impl crate :: Readable for PadUart0TxdCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_uart0_txd_ctrl::W`](W) writer structure"] impl crate :: Writable for PadUart0TxdCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_UART0_TXD_CTRL to value 0x0800"] impl crate :: Resettable for PadUart0TxdCtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_UART0_RXD_CTRL (rw) register accessor: UART0_RXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart0_rxd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart0_rxd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_uart0_rxd_ctrl`] module"]
#[doc (alias = "PAD_UART0_RXD_CTRL")] pub type PadUart0RxdCtrl = crate :: Reg < pad_uart0_rxd_ctrl :: PadUart0RxdCtrlSpec > ;
#[doc = "UART0_RXD pad control register"] pub mod pad_uart0_rxd_ctrl {
#[doc = "Register `PAD_UART0_RXD_CTRL` reader"] pub type R = crate :: R < PadUart0RxdCtrlSpec > ;
#[doc = "Register `PAD_UART0_RXD_CTRL` writer"] pub type W = crate :: W < PadUart0RxdCtrlSpec > ;
#[doc = "Field `pad_uart0_rxd_ctrl_st` reader - Schmitt trigger"] pub type PadUart0RxdCtrlStR = crate :: BitReader ;
#[doc = "Field `pad_uart0_rxd_ctrl_st` writer - Schmitt trigger"] pub type PadUart0RxdCtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_uart0_rxd_ctrl_ie` reader - Input enable"] pub type PadUart0RxdCtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_uart0_rxd_ctrl_ie` writer - Input enable"] pub type PadUart0RxdCtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_uart0_rxd_ctrl_st (& self) -> PadUart0RxdCtrlStR { PadUart0RxdCtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_uart0_rxd_ctrl_ie (& self) -> PadUart0RxdCtrlIeR { PadUart0RxdCtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_uart0_rxd_ctrl_st (& mut self) -> PadUart0RxdCtrlStW < '_ , PadUart0RxdCtrlSpec > { PadUart0RxdCtrlStW :: new (self , 3) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_uart0_rxd_ctrl_ie (& mut self) -> PadUart0RxdCtrlIeW < '_ , PadUart0RxdCtrlSpec > { PadUart0RxdCtrlIeW :: new (self , 11) } }
#[doc = "UART0_RXD pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_uart0_rxd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_uart0_rxd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadUart0RxdCtrlSpec ; impl crate :: RegisterSpec for PadUart0RxdCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_uart0_rxd_ctrl::R`](R) reader structure"] impl crate :: Readable for PadUart0RxdCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_uart0_rxd_ctrl::W`](W) writer structure"] impl crate :: Writable for PadUart0RxdCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_UART0_RXD_CTRL to value 0x0800"] impl crate :: Resettable for PadUart0RxdCtrlSpec { const RESET_VALUE : u32 = 0x0800 ; } }
#[doc = "PAD_SFC_CLK_CTRL (rw) register accessor: SFC_CLK pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_clk_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_clk_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_clk_ctrl`] module"]
#[doc (alias = "PAD_SFC_CLK_CTRL")] pub type PadSfcClkCtrl = crate :: Reg < pad_sfc_clk_ctrl :: PadSfcClkCtrlSpec > ;
#[doc = "SFC_CLK pad control register"] pub mod pad_sfc_clk_ctrl {
#[doc = "Register `PAD_SFC_CLK_CTRL` reader"] pub type R = crate :: R < PadSfcClkCtrlSpec > ;
#[doc = "Register `PAD_SFC_CLK_CTRL` writer"] pub type W = crate :: W < PadSfcClkCtrlSpec > ;
#[doc = "Field `pad_sfc_clk_ctrl_st` reader - Schmitt trigger"] pub type PadSfcClkCtrlStR = crate :: BitReader ;
#[doc = "Field `pad_sfc_clk_ctrl_st` writer - Schmitt trigger"] pub type PadSfcClkCtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_clk_ctrl_ds0` reader - Drive strength bit 0"] pub type PadSfcClkCtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_sfc_clk_ctrl_ds0` writer - Drive strength bit 0"] pub type PadSfcClkCtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_clk_ctrl_ds1` reader - Drive strength bit 1"] pub type PadSfcClkCtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_sfc_clk_ctrl_ds1` writer - Drive strength bit 1"] pub type PadSfcClkCtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_clk_ctrl_ds2` reader - Drive strength bit 2"] pub type PadSfcClkCtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_sfc_clk_ctrl_ds2` writer - Drive strength bit 2"] pub type PadSfcClkCtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_clk_ctrl_pe` reader - Pull enable"] pub type PadSfcClkCtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_clk_ctrl_pe` writer - Pull enable"] pub type PadSfcClkCtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_clk_ctrl_ps` reader - Pull select"] pub type PadSfcClkCtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_sfc_clk_ctrl_ps` writer - Pull select"] pub type PadSfcClkCtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_clk_ctrl_ie` reader - Input enable"] pub type PadSfcClkCtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_clk_ctrl_ie` writer - Input enable"] pub type PadSfcClkCtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_st (& self) -> PadSfcClkCtrlStR { PadSfcClkCtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_ds0 (& self) -> PadSfcClkCtrlDs0R { PadSfcClkCtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_ds1 (& self) -> PadSfcClkCtrlDs1R { PadSfcClkCtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_ds2 (& self) -> PadSfcClkCtrlDs2R { PadSfcClkCtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_pe (& self) -> PadSfcClkCtrlPeR { PadSfcClkCtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_ps (& self) -> PadSfcClkCtrlPsR { PadSfcClkCtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_ie (& self) -> PadSfcClkCtrlIeR { PadSfcClkCtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_st (& mut self) -> PadSfcClkCtrlStW < '_ , PadSfcClkCtrlSpec > { PadSfcClkCtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_ds0 (& mut self) -> PadSfcClkCtrlDs0W < '_ , PadSfcClkCtrlSpec > { PadSfcClkCtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_ds1 (& mut self) -> PadSfcClkCtrlDs1W < '_ , PadSfcClkCtrlSpec > { PadSfcClkCtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_ds2 (& mut self) -> PadSfcClkCtrlDs2W < '_ , PadSfcClkCtrlSpec > { PadSfcClkCtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_pe (& mut self) -> PadSfcClkCtrlPeW < '_ , PadSfcClkCtrlSpec > { PadSfcClkCtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_ps (& mut self) -> PadSfcClkCtrlPsW < '_ , PadSfcClkCtrlSpec > { PadSfcClkCtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_clk_ctrl_ie (& mut self) -> PadSfcClkCtrlIeW < '_ , PadSfcClkCtrlSpec > { PadSfcClkCtrlIeW :: new (self , 11) } }
#[doc = "SFC_CLK pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_clk_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_clk_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadSfcClkCtrlSpec ; impl crate :: RegisterSpec for PadSfcClkCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_sfc_clk_ctrl::R`](R) reader structure"] impl crate :: Readable for PadSfcClkCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_sfc_clk_ctrl::W`](W) writer structure"] impl crate :: Writable for PadSfcClkCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_SFC_CLK_CTRL to value 0x0810"] impl crate :: Resettable for PadSfcClkCtrlSpec { const RESET_VALUE : u32 = 0x0810 ; } }
#[doc = "PAD_SFC_CSN_CTRL (rw) register accessor: SFC_CSN pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_csn_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_csn_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_csn_ctrl`] module"]
#[doc (alias = "PAD_SFC_CSN_CTRL")] pub type PadSfcCsnCtrl = crate :: Reg < pad_sfc_csn_ctrl :: PadSfcCsnCtrlSpec > ;
#[doc = "SFC_CSN pad control register"] pub mod pad_sfc_csn_ctrl {
#[doc = "Register `PAD_SFC_CSN_CTRL` reader"] pub type R = crate :: R < PadSfcCsnCtrlSpec > ;
#[doc = "Register `PAD_SFC_CSN_CTRL` writer"] pub type W = crate :: W < PadSfcCsnCtrlSpec > ;
#[doc = "Field `pad_sfc_csn_ctrl_st` reader - Schmitt trigger"] pub type PadSfcCsnCtrlStR = crate :: BitReader ;
#[doc = "Field `pad_sfc_csn_ctrl_st` writer - Schmitt trigger"] pub type PadSfcCsnCtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_csn_ctrl_ds0` reader - Drive strength bit 0"] pub type PadSfcCsnCtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_sfc_csn_ctrl_ds0` writer - Drive strength bit 0"] pub type PadSfcCsnCtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_csn_ctrl_ds1` reader - Drive strength bit 1"] pub type PadSfcCsnCtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_sfc_csn_ctrl_ds1` writer - Drive strength bit 1"] pub type PadSfcCsnCtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_csn_ctrl_ds2` reader - Drive strength bit 2"] pub type PadSfcCsnCtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_sfc_csn_ctrl_ds2` writer - Drive strength bit 2"] pub type PadSfcCsnCtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_csn_ctrl_pe` reader - Pull enable"] pub type PadSfcCsnCtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_csn_ctrl_pe` writer - Pull enable"] pub type PadSfcCsnCtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_csn_ctrl_ps` reader - Pull select"] pub type PadSfcCsnCtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_sfc_csn_ctrl_ps` writer - Pull select"] pub type PadSfcCsnCtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_csn_ctrl_ie` reader - Input enable"] pub type PadSfcCsnCtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_csn_ctrl_ie` writer - Input enable"] pub type PadSfcCsnCtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_st (& self) -> PadSfcCsnCtrlStR { PadSfcCsnCtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_ds0 (& self) -> PadSfcCsnCtrlDs0R { PadSfcCsnCtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_ds1 (& self) -> PadSfcCsnCtrlDs1R { PadSfcCsnCtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_ds2 (& self) -> PadSfcCsnCtrlDs2R { PadSfcCsnCtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_pe (& self) -> PadSfcCsnCtrlPeR { PadSfcCsnCtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_ps (& self) -> PadSfcCsnCtrlPsR { PadSfcCsnCtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_ie (& self) -> PadSfcCsnCtrlIeR { PadSfcCsnCtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_st (& mut self) -> PadSfcCsnCtrlStW < '_ , PadSfcCsnCtrlSpec > { PadSfcCsnCtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_ds0 (& mut self) -> PadSfcCsnCtrlDs0W < '_ , PadSfcCsnCtrlSpec > { PadSfcCsnCtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_ds1 (& mut self) -> PadSfcCsnCtrlDs1W < '_ , PadSfcCsnCtrlSpec > { PadSfcCsnCtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_ds2 (& mut self) -> PadSfcCsnCtrlDs2W < '_ , PadSfcCsnCtrlSpec > { PadSfcCsnCtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_pe (& mut self) -> PadSfcCsnCtrlPeW < '_ , PadSfcCsnCtrlSpec > { PadSfcCsnCtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_ps (& mut self) -> PadSfcCsnCtrlPsW < '_ , PadSfcCsnCtrlSpec > { PadSfcCsnCtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_csn_ctrl_ie (& mut self) -> PadSfcCsnCtrlIeW < '_ , PadSfcCsnCtrlSpec > { PadSfcCsnCtrlIeW :: new (self , 11) } }
#[doc = "SFC_CSN pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_csn_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_csn_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadSfcCsnCtrlSpec ; impl crate :: RegisterSpec for PadSfcCsnCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_sfc_csn_ctrl::R`](R) reader structure"] impl crate :: Readable for PadSfcCsnCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_sfc_csn_ctrl::W`](W) writer structure"] impl crate :: Writable for PadSfcCsnCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_SFC_CSN_CTRL to value 0x0e10"] impl crate :: Resettable for PadSfcCsnCtrlSpec { const RESET_VALUE : u32 = 0x0e10 ; } }
#[doc = "PAD_SFC_IO0_CTRL (rw) register accessor: SFC_IO0 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_io0_ctrl`] module"]
#[doc (alias = "PAD_SFC_IO0_CTRL")] pub type PadSfcIo0Ctrl = crate :: Reg < pad_sfc_io0_ctrl :: PadSfcIo0CtrlSpec > ;
#[doc = "SFC_IO0 pad control register"] pub mod pad_sfc_io0_ctrl {
#[doc = "Register `PAD_SFC_IO0_CTRL` reader"] pub type R = crate :: R < PadSfcIo0CtrlSpec > ;
#[doc = "Register `PAD_SFC_IO0_CTRL` writer"] pub type W = crate :: W < PadSfcIo0CtrlSpec > ;
#[doc = "Field `pad_sfc_io0_ctrl_st` reader - Schmitt trigger"] pub type PadSfcIo0CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io0_ctrl_st` writer - Schmitt trigger"] pub type PadSfcIo0CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io0_ctrl_ds0` reader - Drive strength bit 0"] pub type PadSfcIo0CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io0_ctrl_ds0` writer - Drive strength bit 0"] pub type PadSfcIo0CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io0_ctrl_ds1` reader - Drive strength bit 1"] pub type PadSfcIo0CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io0_ctrl_ds1` writer - Drive strength bit 1"] pub type PadSfcIo0CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io0_ctrl_ds2` reader - Drive strength bit 2"] pub type PadSfcIo0CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io0_ctrl_ds2` writer - Drive strength bit 2"] pub type PadSfcIo0CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io0_ctrl_pe` reader - Pull enable"] pub type PadSfcIo0CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io0_ctrl_pe` writer - Pull enable"] pub type PadSfcIo0CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io0_ctrl_ps` reader - Pull select"] pub type PadSfcIo0CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io0_ctrl_ps` writer - Pull select"] pub type PadSfcIo0CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io0_ctrl_ie` reader - Input enable"] pub type PadSfcIo0CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io0_ctrl_ie` writer - Input enable"] pub type PadSfcIo0CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_st (& self) -> PadSfcIo0CtrlStR { PadSfcIo0CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_ds0 (& self) -> PadSfcIo0CtrlDs0R { PadSfcIo0CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_ds1 (& self) -> PadSfcIo0CtrlDs1R { PadSfcIo0CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_ds2 (& self) -> PadSfcIo0CtrlDs2R { PadSfcIo0CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_pe (& self) -> PadSfcIo0CtrlPeR { PadSfcIo0CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_ps (& self) -> PadSfcIo0CtrlPsR { PadSfcIo0CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_ie (& self) -> PadSfcIo0CtrlIeR { PadSfcIo0CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_st (& mut self) -> PadSfcIo0CtrlStW < '_ , PadSfcIo0CtrlSpec > { PadSfcIo0CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_ds0 (& mut self) -> PadSfcIo0CtrlDs0W < '_ , PadSfcIo0CtrlSpec > { PadSfcIo0CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_ds1 (& mut self) -> PadSfcIo0CtrlDs1W < '_ , PadSfcIo0CtrlSpec > { PadSfcIo0CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_ds2 (& mut self) -> PadSfcIo0CtrlDs2W < '_ , PadSfcIo0CtrlSpec > { PadSfcIo0CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_pe (& mut self) -> PadSfcIo0CtrlPeW < '_ , PadSfcIo0CtrlSpec > { PadSfcIo0CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_ps (& mut self) -> PadSfcIo0CtrlPsW < '_ , PadSfcIo0CtrlSpec > { PadSfcIo0CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_io0_ctrl_ie (& mut self) -> PadSfcIo0CtrlIeW < '_ , PadSfcIo0CtrlSpec > { PadSfcIo0CtrlIeW :: new (self , 11) } }
#[doc = "SFC_IO0 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadSfcIo0CtrlSpec ; impl crate :: RegisterSpec for PadSfcIo0CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_sfc_io0_ctrl::R`](R) reader structure"] impl crate :: Readable for PadSfcIo0CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_sfc_io0_ctrl::W`](W) writer structure"] impl crate :: Writable for PadSfcIo0CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_SFC_IO0_CTRL to value 0x0e10"] impl crate :: Resettable for PadSfcIo0CtrlSpec { const RESET_VALUE : u32 = 0x0e10 ; } }
#[doc = "PAD_SFC_IO1_CTRL (rw) register accessor: SFC_IO1 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io1_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io1_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_io1_ctrl`] module"]
#[doc (alias = "PAD_SFC_IO1_CTRL")] pub type PadSfcIo1Ctrl = crate :: Reg < pad_sfc_io1_ctrl :: PadSfcIo1CtrlSpec > ;
#[doc = "SFC_IO1 pad control register"] pub mod pad_sfc_io1_ctrl {
#[doc = "Register `PAD_SFC_IO1_CTRL` reader"] pub type R = crate :: R < PadSfcIo1CtrlSpec > ;
#[doc = "Register `PAD_SFC_IO1_CTRL` writer"] pub type W = crate :: W < PadSfcIo1CtrlSpec > ;
#[doc = "Field `pad_sfc_io1_ctrl_st` reader - Schmitt trigger"] pub type PadSfcIo1CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io1_ctrl_st` writer - Schmitt trigger"] pub type PadSfcIo1CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io1_ctrl_ds0` reader - Drive strength bit 0"] pub type PadSfcIo1CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io1_ctrl_ds0` writer - Drive strength bit 0"] pub type PadSfcIo1CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io1_ctrl_ds1` reader - Drive strength bit 1"] pub type PadSfcIo1CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io1_ctrl_ds1` writer - Drive strength bit 1"] pub type PadSfcIo1CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io1_ctrl_ds2` reader - Drive strength bit 2"] pub type PadSfcIo1CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io1_ctrl_ds2` writer - Drive strength bit 2"] pub type PadSfcIo1CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io1_ctrl_pe` reader - Pull enable"] pub type PadSfcIo1CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io1_ctrl_pe` writer - Pull enable"] pub type PadSfcIo1CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io1_ctrl_ps` reader - Pull select"] pub type PadSfcIo1CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io1_ctrl_ps` writer - Pull select"] pub type PadSfcIo1CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io1_ctrl_ie` reader - Input enable"] pub type PadSfcIo1CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io1_ctrl_ie` writer - Input enable"] pub type PadSfcIo1CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_st (& self) -> PadSfcIo1CtrlStR { PadSfcIo1CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_ds0 (& self) -> PadSfcIo1CtrlDs0R { PadSfcIo1CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_ds1 (& self) -> PadSfcIo1CtrlDs1R { PadSfcIo1CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_ds2 (& self) -> PadSfcIo1CtrlDs2R { PadSfcIo1CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_pe (& self) -> PadSfcIo1CtrlPeR { PadSfcIo1CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_ps (& self) -> PadSfcIo1CtrlPsR { PadSfcIo1CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_ie (& self) -> PadSfcIo1CtrlIeR { PadSfcIo1CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_st (& mut self) -> PadSfcIo1CtrlStW < '_ , PadSfcIo1CtrlSpec > { PadSfcIo1CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_ds0 (& mut self) -> PadSfcIo1CtrlDs0W < '_ , PadSfcIo1CtrlSpec > { PadSfcIo1CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_ds1 (& mut self) -> PadSfcIo1CtrlDs1W < '_ , PadSfcIo1CtrlSpec > { PadSfcIo1CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_ds2 (& mut self) -> PadSfcIo1CtrlDs2W < '_ , PadSfcIo1CtrlSpec > { PadSfcIo1CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_pe (& mut self) -> PadSfcIo1CtrlPeW < '_ , PadSfcIo1CtrlSpec > { PadSfcIo1CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_ps (& mut self) -> PadSfcIo1CtrlPsW < '_ , PadSfcIo1CtrlSpec > { PadSfcIo1CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_io1_ctrl_ie (& mut self) -> PadSfcIo1CtrlIeW < '_ , PadSfcIo1CtrlSpec > { PadSfcIo1CtrlIeW :: new (self , 11) } }
#[doc = "SFC_IO1 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadSfcIo1CtrlSpec ; impl crate :: RegisterSpec for PadSfcIo1CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_sfc_io1_ctrl::R`](R) reader structure"] impl crate :: Readable for PadSfcIo1CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_sfc_io1_ctrl::W`](W) writer structure"] impl crate :: Writable for PadSfcIo1CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_SFC_IO1_CTRL to value 0x0e10"] impl crate :: Resettable for PadSfcIo1CtrlSpec { const RESET_VALUE : u32 = 0x0e10 ; } }
#[doc = "PAD_SFC_IO2_CTRL (rw) register accessor: SFC_IO2 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io2_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io2_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_io2_ctrl`] module"]
#[doc (alias = "PAD_SFC_IO2_CTRL")] pub type PadSfcIo2Ctrl = crate :: Reg < pad_sfc_io2_ctrl :: PadSfcIo2CtrlSpec > ;
#[doc = "SFC_IO2 pad control register"] pub mod pad_sfc_io2_ctrl {
#[doc = "Register `PAD_SFC_IO2_CTRL` reader"] pub type R = crate :: R < PadSfcIo2CtrlSpec > ;
#[doc = "Register `PAD_SFC_IO2_CTRL` writer"] pub type W = crate :: W < PadSfcIo2CtrlSpec > ;
#[doc = "Field `pad_sfc_io2_ctrl_st` reader - Schmitt trigger"] pub type PadSfcIo2CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io2_ctrl_st` writer - Schmitt trigger"] pub type PadSfcIo2CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io2_ctrl_ds0` reader - Drive strength bit 0"] pub type PadSfcIo2CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io2_ctrl_ds0` writer - Drive strength bit 0"] pub type PadSfcIo2CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io2_ctrl_ds1` reader - Drive strength bit 1"] pub type PadSfcIo2CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io2_ctrl_ds1` writer - Drive strength bit 1"] pub type PadSfcIo2CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io2_ctrl_ds2` reader - Drive strength bit 2"] pub type PadSfcIo2CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io2_ctrl_ds2` writer - Drive strength bit 2"] pub type PadSfcIo2CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io2_ctrl_pe` reader - Pull enable"] pub type PadSfcIo2CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io2_ctrl_pe` writer - Pull enable"] pub type PadSfcIo2CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io2_ctrl_ps` reader - Pull select"] pub type PadSfcIo2CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io2_ctrl_ps` writer - Pull select"] pub type PadSfcIo2CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io2_ctrl_ie` reader - Input enable"] pub type PadSfcIo2CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io2_ctrl_ie` writer - Input enable"] pub type PadSfcIo2CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_st (& self) -> PadSfcIo2CtrlStR { PadSfcIo2CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_ds0 (& self) -> PadSfcIo2CtrlDs0R { PadSfcIo2CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_ds1 (& self) -> PadSfcIo2CtrlDs1R { PadSfcIo2CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_ds2 (& self) -> PadSfcIo2CtrlDs2R { PadSfcIo2CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_pe (& self) -> PadSfcIo2CtrlPeR { PadSfcIo2CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_ps (& self) -> PadSfcIo2CtrlPsR { PadSfcIo2CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_ie (& self) -> PadSfcIo2CtrlIeR { PadSfcIo2CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_st (& mut self) -> PadSfcIo2CtrlStW < '_ , PadSfcIo2CtrlSpec > { PadSfcIo2CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_ds0 (& mut self) -> PadSfcIo2CtrlDs0W < '_ , PadSfcIo2CtrlSpec > { PadSfcIo2CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_ds1 (& mut self) -> PadSfcIo2CtrlDs1W < '_ , PadSfcIo2CtrlSpec > { PadSfcIo2CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_ds2 (& mut self) -> PadSfcIo2CtrlDs2W < '_ , PadSfcIo2CtrlSpec > { PadSfcIo2CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_pe (& mut self) -> PadSfcIo2CtrlPeW < '_ , PadSfcIo2CtrlSpec > { PadSfcIo2CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_ps (& mut self) -> PadSfcIo2CtrlPsW < '_ , PadSfcIo2CtrlSpec > { PadSfcIo2CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_io2_ctrl_ie (& mut self) -> PadSfcIo2CtrlIeW < '_ , PadSfcIo2CtrlSpec > { PadSfcIo2CtrlIeW :: new (self , 11) } }
#[doc = "SFC_IO2 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadSfcIo2CtrlSpec ; impl crate :: RegisterSpec for PadSfcIo2CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_sfc_io2_ctrl::R`](R) reader structure"] impl crate :: Readable for PadSfcIo2CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_sfc_io2_ctrl::W`](W) writer structure"] impl crate :: Writable for PadSfcIo2CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_SFC_IO2_CTRL to value 0x0e10"] impl crate :: Resettable for PadSfcIo2CtrlSpec { const RESET_VALUE : u32 = 0x0e10 ; } }
#[doc = "PAD_SFC_IO3_CTRL (rw) register accessor: SFC_IO3 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io3_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io3_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_sfc_io3_ctrl`] module"]
#[doc (alias = "PAD_SFC_IO3_CTRL")] pub type PadSfcIo3Ctrl = crate :: Reg < pad_sfc_io3_ctrl :: PadSfcIo3CtrlSpec > ;
#[doc = "SFC_IO3 pad control register"] pub mod pad_sfc_io3_ctrl {
#[doc = "Register `PAD_SFC_IO3_CTRL` reader"] pub type R = crate :: R < PadSfcIo3CtrlSpec > ;
#[doc = "Register `PAD_SFC_IO3_CTRL` writer"] pub type W = crate :: W < PadSfcIo3CtrlSpec > ;
#[doc = "Field `pad_sfc_io3_ctrl_st` reader - Schmitt trigger"] pub type PadSfcIo3CtrlStR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io3_ctrl_st` writer - Schmitt trigger"] pub type PadSfcIo3CtrlStW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io3_ctrl_ds0` reader - Drive strength bit 0"] pub type PadSfcIo3CtrlDs0R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io3_ctrl_ds0` writer - Drive strength bit 0"] pub type PadSfcIo3CtrlDs0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io3_ctrl_ds1` reader - Drive strength bit 1"] pub type PadSfcIo3CtrlDs1R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io3_ctrl_ds1` writer - Drive strength bit 1"] pub type PadSfcIo3CtrlDs1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io3_ctrl_ds2` reader - Drive strength bit 2"] pub type PadSfcIo3CtrlDs2R = crate :: BitReader ;
#[doc = "Field `pad_sfc_io3_ctrl_ds2` writer - Drive strength bit 2"] pub type PadSfcIo3CtrlDs2W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io3_ctrl_pe` reader - Pull enable"] pub type PadSfcIo3CtrlPeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io3_ctrl_pe` writer - Pull enable"] pub type PadSfcIo3CtrlPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io3_ctrl_ps` reader - Pull select"] pub type PadSfcIo3CtrlPsR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io3_ctrl_ps` writer - Pull select"] pub type PadSfcIo3CtrlPsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pad_sfc_io3_ctrl_ie` reader - Input enable"] pub type PadSfcIo3CtrlIeR = crate :: BitReader ;
#[doc = "Field `pad_sfc_io3_ctrl_ie` writer - Input enable"] pub type PadSfcIo3CtrlIeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_st (& self) -> PadSfcIo3CtrlStR { PadSfcIo3CtrlStR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_ds0 (& self) -> PadSfcIo3CtrlDs0R { PadSfcIo3CtrlDs0R :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_ds1 (& self) -> PadSfcIo3CtrlDs1R { PadSfcIo3CtrlDs1R :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_ds2 (& self) -> PadSfcIo3CtrlDs2R { PadSfcIo3CtrlDs2R :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_pe (& self) -> PadSfcIo3CtrlPeR { PadSfcIo3CtrlPeR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_ps (& self) -> PadSfcIo3CtrlPsR { PadSfcIo3CtrlPsR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_ie (& self) -> PadSfcIo3CtrlIeR { PadSfcIo3CtrlIeR :: new (((self . bits >> 11) & 1) != 0) } } impl W {
#[doc = "Bit 3 - Schmitt trigger"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_st (& mut self) -> PadSfcIo3CtrlStW < '_ , PadSfcIo3CtrlSpec > { PadSfcIo3CtrlStW :: new (self , 3) }
#[doc = "Bit 4 - Drive strength bit 0"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_ds0 (& mut self) -> PadSfcIo3CtrlDs0W < '_ , PadSfcIo3CtrlSpec > { PadSfcIo3CtrlDs0W :: new (self , 4) }
#[doc = "Bit 5 - Drive strength bit 1"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_ds1 (& mut self) -> PadSfcIo3CtrlDs1W < '_ , PadSfcIo3CtrlSpec > { PadSfcIo3CtrlDs1W :: new (self , 5) }
#[doc = "Bit 6 - Drive strength bit 2"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_ds2 (& mut self) -> PadSfcIo3CtrlDs2W < '_ , PadSfcIo3CtrlSpec > { PadSfcIo3CtrlDs2W :: new (self , 6) }
#[doc = "Bit 9 - Pull enable"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_pe (& mut self) -> PadSfcIo3CtrlPeW < '_ , PadSfcIo3CtrlSpec > { PadSfcIo3CtrlPeW :: new (self , 9) }
#[doc = "Bit 10 - Pull select"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_ps (& mut self) -> PadSfcIo3CtrlPsW < '_ , PadSfcIo3CtrlSpec > { PadSfcIo3CtrlPsW :: new (self , 10) }
#[doc = "Bit 11 - Input enable"]
#[inline (always)] pub fn pad_sfc_io3_ctrl_ie (& mut self) -> PadSfcIo3CtrlIeW < '_ , PadSfcIo3CtrlSpec > { PadSfcIo3CtrlIeW :: new (self , 11) } }
#[doc = "SFC_IO3 pad control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_sfc_io3_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_sfc_io3_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PadSfcIo3CtrlSpec ; impl crate :: RegisterSpec for PadSfcIo3CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pad_sfc_io3_ctrl::R`](R) reader structure"] impl crate :: Readable for PadSfcIo3CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pad_sfc_io3_ctrl::W`](W) writer structure"] impl crate :: Writable for PadSfcIo3CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PAD_SFC_IO3_CTRL to value 0x0e10"] impl crate :: Resettable for PadSfcIo3CtrlSpec { const RESET_VALUE : u32 = 0x0e10 ; } } }
#[doc = "GPIO controller for GPIO\\[7:0\\]"] pub type Gpio0 = crate :: Periph < gpio0 :: RegisterBlock , 0x4402_8000 > ; impl core :: fmt :: Debug for Gpio0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Gpio0") . finish () } }
#[doc = "GPIO controller for GPIO\\[7:0\\]"] pub mod gpio0 {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { gpio_sw_out : GpioSwOut , gpio_sw_oen : GpioSwOen , _reserved2 : [u8 ; 0x04] , gpio_int_en : GpioIntEn , gpio_int_mask : GpioIntMask , gpio_int_type : GpioIntType , gpio_int_polarity : GpioIntPolarity , gpio_int_dedge : GpioIntDedge , gpio_int_debounce : GpioIntDebounce , gpio_int_raw : GpioIntRaw , gpio_intr : GpioIntr , gpio_int_eoi : GpioIntEoi , gpio_data_set : GpioDataSet , gpio_data_clr : GpioDataClr , } impl RegisterBlock {
#[doc = "0x00 - GPIO data register"]
#[inline (always)] pub const fn gpio_sw_out (& self) -> & GpioSwOut { & self . gpio_sw_out }
#[doc = "0x04 - GPIO data direction register"]
#[inline (always)] pub const fn gpio_sw_oen (& self) -> & GpioSwOen { & self . gpio_sw_oen }
#[doc = "0x0c - GPIO interrupt enable register"]
#[inline (always)] pub const fn gpio_int_en (& self) -> & GpioIntEn { & self . gpio_int_en }
#[doc = "0x10 - GPIO interrupt mask register"]
#[inline (always)] pub const fn gpio_int_mask (& self) -> & GpioIntMask { & self . gpio_int_mask }
#[doc = "0x14 - GPIO interrupt type register"]
#[inline (always)] pub const fn gpio_int_type (& self) -> & GpioIntType { & self . gpio_int_type }
#[doc = "0x18 - GPIO interrupt polarity register"]
#[inline (always)] pub const fn gpio_int_polarity (& self) -> & GpioIntPolarity { & self . gpio_int_polarity }
#[doc = "0x1c - GPIO dual-edge interrupt enable register"]
#[inline (always)] pub const fn gpio_int_dedge (& self) -> & GpioIntDedge { & self . gpio_int_dedge }
#[doc = "0x20 - GPIO interrupt debounce control register"]
#[inline (always)] pub const fn gpio_int_debounce (& self) -> & GpioIntDebounce { & self . gpio_int_debounce }
#[doc = "0x24 - GPIO raw interrupt status register"]
#[inline (always)] pub const fn gpio_int_raw (& self) -> & GpioIntRaw { & self . gpio_int_raw }
#[doc = "0x28 - GPIO interrupt status register"]
#[inline (always)] pub const fn gpio_intr (& self) -> & GpioIntr { & self . gpio_intr }
#[doc = "0x2c - GPIO interrupt clear register"]
#[inline (always)] pub const fn gpio_int_eoi (& self) -> & GpioIntEoi { & self . gpio_int_eoi }
#[doc = "0x30 - GPIO data set register"]
#[inline (always)] pub const fn gpio_data_set (& self) -> & GpioDataSet { & self . gpio_data_set }
#[doc = "0x34 - GPIO data clear register"]
#[inline (always)] pub const fn gpio_data_clr (& self) -> & GpioDataClr { & self . gpio_data_clr } }
#[doc = "GPIO_SW_OUT (rw) register accessor: GPIO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_sw_out`] module"]
#[doc (alias = "GPIO_SW_OUT")] pub type GpioSwOut = crate :: Reg < gpio_sw_out :: GpioSwOutSpec > ;
#[doc = "GPIO data register"] pub mod gpio_sw_out {
#[doc = "Register `GPIO_SW_OUT` reader"] pub type R = crate :: R < GpioSwOutSpec > ;
#[doc = "Register `GPIO_SW_OUT` writer"] pub type W = crate :: W < GpioSwOutSpec > ;
#[doc = "Field `gpio_sw_out` reader - GPIO data. Output: written value drives I/O; Input: reads external port"] pub type GpioSwOutR = crate :: FieldReader ;
#[doc = "Field `gpio_sw_out` writer - GPIO data. Output: written value drives I/O; Input: reads external port"] pub type GpioSwOutW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - GPIO data. Output: written value drives I/O; Input: reads external port"]
#[inline (always)] pub fn gpio_sw_out (& self) -> GpioSwOutR { GpioSwOutR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - GPIO data. Output: written value drives I/O; Input: reads external port"]
#[inline (always)] pub fn gpio_sw_out (& mut self) -> GpioSwOutW < '_ , GpioSwOutSpec > { GpioSwOutW :: new (self , 0) } }
#[doc = "GPIO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioSwOutSpec ; impl crate :: RegisterSpec for GpioSwOutSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_sw_out::R`](R) reader structure"] impl crate :: Readable for GpioSwOutSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_sw_out::W`](W) writer structure"] impl crate :: Writable for GpioSwOutSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_SW_OUT to value 0"] impl crate :: Resettable for GpioSwOutSpec { } }
#[doc = "GPIO_SW_OEN (rw) register accessor: GPIO data direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_oen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_oen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_sw_oen`] module"]
#[doc (alias = "GPIO_SW_OEN")] pub type GpioSwOen = crate :: Reg < gpio_sw_oen :: GpioSwOenSpec > ;
#[doc = "GPIO data direction register"] pub mod gpio_sw_oen {
#[doc = "Register `GPIO_SW_OEN` reader"] pub type R = crate :: R < GpioSwOenSpec > ;
#[doc = "Register `GPIO_SW_OEN` writer"] pub type W = crate :: W < GpioSwOenSpec > ;
#[doc = "GPIO direction: 0=output; 1=input (default)\n\nValue on reset: 255"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum GpioSwOen {
#[doc = "0: Output direction"] Output = 0 ,
#[doc = "1: Input direction"] Input = 1 , } impl From < GpioSwOen > for u8 {
#[inline (always)] fn from (variant : GpioSwOen) -> Self { variant as _ } } impl crate :: FieldSpec for GpioSwOen { type Ux = u8 ; } impl crate :: IsEnum for GpioSwOen { }
#[doc = "Field `gpio_sw_oen` reader - GPIO direction: 0=output; 1=input (default)"] pub type GpioSwOenR = crate :: FieldReader < GpioSwOen > ; impl GpioSwOenR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < GpioSwOen > { match self . bits { 0 => Some (GpioSwOen :: Output) , 1 => Some (GpioSwOen :: Input) , _ => None , } }
#[doc = "Output direction"]
#[inline (always)] pub fn is_output (& self) -> bool { * self == GpioSwOen :: Output }
#[doc = "Input direction"]
#[inline (always)] pub fn is_input (& self) -> bool { * self == GpioSwOen :: Input } }
#[doc = "Field `gpio_sw_oen` writer - GPIO direction: 0=output; 1=input (default)"] pub type GpioSwOenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 , GpioSwOen > ; impl < 'a , REG > GpioSwOenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Output direction"]
#[inline (always)] pub fn output (self) -> & 'a mut crate :: W < REG > { self . variant (GpioSwOen :: Output) }
#[doc = "Input direction"]
#[inline (always)] pub fn input (self) -> & 'a mut crate :: W < REG > { self . variant (GpioSwOen :: Input) } } impl R {
#[doc = "Bits 0:7 - GPIO direction: 0=output; 1=input (default)"]
#[inline (always)] pub fn gpio_sw_oen (& self) -> GpioSwOenR { GpioSwOenR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - GPIO direction: 0=output; 1=input (default)"]
#[inline (always)] pub fn gpio_sw_oen (& mut self) -> GpioSwOenW < '_ , GpioSwOenSpec > { GpioSwOenW :: new (self , 0) } }
#[doc = "GPIO data direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_oen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_oen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioSwOenSpec ; impl crate :: RegisterSpec for GpioSwOenSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_sw_oen::R`](R) reader structure"] impl crate :: Readable for GpioSwOenSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_sw_oen::W`](W) writer structure"] impl crate :: Writable for GpioSwOenSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_SW_OEN to value 0xff"] impl crate :: Resettable for GpioSwOenSpec { const RESET_VALUE : u32 = 0xff ; } }
#[doc = "GPIO_INT_EN (rw) register accessor: GPIO interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_en`] module"]
#[doc (alias = "GPIO_INT_EN")] pub type GpioIntEn = crate :: Reg < gpio_int_en :: GpioIntEnSpec > ;
#[doc = "GPIO interrupt enable register"] pub mod gpio_int_en {
#[doc = "Register `GPIO_INT_EN` reader"] pub type R = crate :: R < GpioIntEnSpec > ;
#[doc = "Register `GPIO_INT_EN` writer"] pub type W = crate :: W < GpioIntEnSpec > ;
#[doc = "Field `gpio_int_en` reader - Interrupt enable: 0=normal GPIO; 1=interrupt port"] pub type GpioIntEnR = crate :: FieldReader ;
#[doc = "Field `gpio_int_en` writer - Interrupt enable: 0=normal GPIO; 1=interrupt port"] pub type GpioIntEnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
#[inline (always)] pub fn gpio_int_en (& self) -> GpioIntEnR { GpioIntEnR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
#[inline (always)] pub fn gpio_int_en (& mut self) -> GpioIntEnW < '_ , GpioIntEnSpec > { GpioIntEnW :: new (self , 0) } }
#[doc = "GPIO interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioIntEnSpec ; impl crate :: RegisterSpec for GpioIntEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_int_en::R`](R) reader structure"] impl crate :: Readable for GpioIntEnSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_int_en::W`](W) writer structure"] impl crate :: Writable for GpioIntEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_INT_EN to value 0"] impl crate :: Resettable for GpioIntEnSpec { } }
#[doc = "GPIO_INT_MASK (rw) register accessor: GPIO interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_mask`] module"]
#[doc (alias = "GPIO_INT_MASK")] pub type GpioIntMask = crate :: Reg < gpio_int_mask :: GpioIntMaskSpec > ;
#[doc = "GPIO interrupt mask register"] pub mod gpio_int_mask {
#[doc = "Register `GPIO_INT_MASK` reader"] pub type R = crate :: R < GpioIntMaskSpec > ;
#[doc = "Register `GPIO_INT_MASK` writer"] pub type W = crate :: W < GpioIntMaskSpec > ;
#[doc = "Field `gpio_int_mask` reader - Interrupt mask: 0=not masked; 1=masked"] pub type GpioIntMaskR = crate :: FieldReader ;
#[doc = "Field `gpio_int_mask` writer - Interrupt mask: 0=not masked; 1=masked"] pub type GpioIntMaskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - Interrupt mask: 0=not masked; 1=masked"]
#[inline (always)] pub fn gpio_int_mask (& self) -> GpioIntMaskR { GpioIntMaskR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Interrupt mask: 0=not masked; 1=masked"]
#[inline (always)] pub fn gpio_int_mask (& mut self) -> GpioIntMaskW < '_ , GpioIntMaskSpec > { GpioIntMaskW :: new (self , 0) } }
#[doc = "GPIO interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioIntMaskSpec ; impl crate :: RegisterSpec for GpioIntMaskSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_int_mask::R`](R) reader structure"] impl crate :: Readable for GpioIntMaskSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_int_mask::W`](W) writer structure"] impl crate :: Writable for GpioIntMaskSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_INT_MASK to value 0"] impl crate :: Resettable for GpioIntMaskSpec { } }
#[doc = "GPIO_INT_TYPE (rw) register accessor: GPIO interrupt type register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_type`] module"]
#[doc (alias = "GPIO_INT_TYPE")] pub type GpioIntType = crate :: Reg < gpio_int_type :: GpioIntTypeSpec > ;
#[doc = "GPIO interrupt type register"] pub mod gpio_int_type {
#[doc = "Register `GPIO_INT_TYPE` reader"] pub type R = crate :: R < GpioIntTypeSpec > ;
#[doc = "Register `GPIO_INT_TYPE` writer"] pub type W = crate :: W < GpioIntTypeSpec > ;
#[doc = "Interrupt type: 0=level; 1=edge\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum GpioIntType {
#[doc = "0: Level-sensitive"] Level = 0 ,
#[doc = "1: Edge-triggered"] Edge = 1 , } impl From < GpioIntType > for u8 {
#[inline (always)] fn from (variant : GpioIntType) -> Self { variant as _ } } impl crate :: FieldSpec for GpioIntType { type Ux = u8 ; } impl crate :: IsEnum for GpioIntType { }
#[doc = "Field `gpio_int_type` reader - Interrupt type: 0=level; 1=edge"] pub type GpioIntTypeR = crate :: FieldReader < GpioIntType > ; impl GpioIntTypeR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < GpioIntType > { match self . bits { 0 => Some (GpioIntType :: Level) , 1 => Some (GpioIntType :: Edge) , _ => None , } }
#[doc = "Level-sensitive"]
#[inline (always)] pub fn is_level (& self) -> bool { * self == GpioIntType :: Level }
#[doc = "Edge-triggered"]
#[inline (always)] pub fn is_edge (& self) -> bool { * self == GpioIntType :: Edge } }
#[doc = "Field `gpio_int_type` writer - Interrupt type: 0=level; 1=edge"] pub type GpioIntTypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 , GpioIntType > ; impl < 'a , REG > GpioIntTypeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Level-sensitive"]
#[inline (always)] pub fn level (self) -> & 'a mut crate :: W < REG > { self . variant (GpioIntType :: Level) }
#[doc = "Edge-triggered"]
#[inline (always)] pub fn edge (self) -> & 'a mut crate :: W < REG > { self . variant (GpioIntType :: Edge) } } impl R {
#[doc = "Bits 0:7 - Interrupt type: 0=level; 1=edge"]
#[inline (always)] pub fn gpio_int_type (& self) -> GpioIntTypeR { GpioIntTypeR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Interrupt type: 0=level; 1=edge"]
#[inline (always)] pub fn gpio_int_type (& mut self) -> GpioIntTypeW < '_ , GpioIntTypeSpec > { GpioIntTypeW :: new (self , 0) } }
#[doc = "GPIO interrupt type register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_type::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_type::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioIntTypeSpec ; impl crate :: RegisterSpec for GpioIntTypeSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_int_type::R`](R) reader structure"] impl crate :: Readable for GpioIntTypeSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_int_type::W`](W) writer structure"] impl crate :: Writable for GpioIntTypeSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_INT_TYPE to value 0"] impl crate :: Resettable for GpioIntTypeSpec { } }
#[doc = "GPIO_INT_POLARITY (rw) register accessor: GPIO interrupt polarity register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_polarity::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_polarity::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_polarity`] module"]
#[doc (alias = "GPIO_INT_POLARITY")] pub type GpioIntPolarity = crate :: Reg < gpio_int_polarity :: GpioIntPolaritySpec > ;
#[doc = "GPIO interrupt polarity register"] pub mod gpio_int_polarity {
#[doc = "Register `GPIO_INT_POLARITY` reader"] pub type R = crate :: R < GpioIntPolaritySpec > ;
#[doc = "Register `GPIO_INT_POLARITY` writer"] pub type W = crate :: W < GpioIntPolaritySpec > ;
#[doc = "Interrupt polarity: 0=low/falling; 1=high/rising\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum GpioIntPolarity {
#[doc = "0: Low level or falling edge"] LowFalling = 0 ,
#[doc = "1: High level or rising edge"] HighRising = 1 , } impl From < GpioIntPolarity > for u8 {
#[inline (always)] fn from (variant : GpioIntPolarity) -> Self { variant as _ } } impl crate :: FieldSpec for GpioIntPolarity { type Ux = u8 ; } impl crate :: IsEnum for GpioIntPolarity { }
#[doc = "Field `gpio_int_polarity` reader - Interrupt polarity: 0=low/falling; 1=high/rising"] pub type GpioIntPolarityR = crate :: FieldReader < GpioIntPolarity > ; impl GpioIntPolarityR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < GpioIntPolarity > { match self . bits { 0 => Some (GpioIntPolarity :: LowFalling) , 1 => Some (GpioIntPolarity :: HighRising) , _ => None , } }
#[doc = "Low level or falling edge"]
#[inline (always)] pub fn is_low_falling (& self) -> bool { * self == GpioIntPolarity :: LowFalling }
#[doc = "High level or rising edge"]
#[inline (always)] pub fn is_high_rising (& self) -> bool { * self == GpioIntPolarity :: HighRising } }
#[doc = "Field `gpio_int_polarity` writer - Interrupt polarity: 0=low/falling; 1=high/rising"] pub type GpioIntPolarityW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 , GpioIntPolarity > ; impl < 'a , REG > GpioIntPolarityW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Low level or falling edge"]
#[inline (always)] pub fn low_falling (self) -> & 'a mut crate :: W < REG > { self . variant (GpioIntPolarity :: LowFalling) }
#[doc = "High level or rising edge"]
#[inline (always)] pub fn high_rising (self) -> & 'a mut crate :: W < REG > { self . variant (GpioIntPolarity :: HighRising) } } impl R {
#[doc = "Bits 0:7 - Interrupt polarity: 0=low/falling; 1=high/rising"]
#[inline (always)] pub fn gpio_int_polarity (& self) -> GpioIntPolarityR { GpioIntPolarityR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Interrupt polarity: 0=low/falling; 1=high/rising"]
#[inline (always)] pub fn gpio_int_polarity (& mut self) -> GpioIntPolarityW < '_ , GpioIntPolaritySpec > { GpioIntPolarityW :: new (self , 0) } }
#[doc = "GPIO interrupt polarity register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_polarity::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_polarity::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioIntPolaritySpec ; impl crate :: RegisterSpec for GpioIntPolaritySpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_int_polarity::R`](R) reader structure"] impl crate :: Readable for GpioIntPolaritySpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_int_polarity::W`](W) writer structure"] impl crate :: Writable for GpioIntPolaritySpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_INT_POLARITY to value 0"] impl crate :: Resettable for GpioIntPolaritySpec { } }
#[doc = "GPIO_INT_DEDGE (rw) register accessor: GPIO dual-edge interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_dedge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_dedge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_dedge`] module"]
#[doc (alias = "GPIO_INT_DEDGE")] pub type GpioIntDedge = crate :: Reg < gpio_int_dedge :: GpioIntDedgeSpec > ;
#[doc = "GPIO dual-edge interrupt enable register"] pub mod gpio_int_dedge {
#[doc = "Register `GPIO_INT_DEDGE` reader"] pub type R = crate :: R < GpioIntDedgeSpec > ;
#[doc = "Register `GPIO_INT_DEDGE` writer"] pub type W = crate :: W < GpioIntDedgeSpec > ;
#[doc = "Dual-edge interrupt enable: 0=disabled; 1=enabled\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum GpioIntDedge {
#[doc = "0: Single-edge mode"] Disabled = 0 ,
#[doc = "1: Dual-edge triggered"] Enabled = 1 , } impl From < GpioIntDedge > for u8 {
#[inline (always)] fn from (variant : GpioIntDedge) -> Self { variant as _ } } impl crate :: FieldSpec for GpioIntDedge { type Ux = u8 ; } impl crate :: IsEnum for GpioIntDedge { }
#[doc = "Field `gpio_int_dedge` reader - Dual-edge interrupt enable: 0=disabled; 1=enabled"] pub type GpioIntDedgeR = crate :: FieldReader < GpioIntDedge > ; impl GpioIntDedgeR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < GpioIntDedge > { match self . bits { 0 => Some (GpioIntDedge :: Disabled) , 1 => Some (GpioIntDedge :: Enabled) , _ => None , } }
#[doc = "Single-edge mode"]
#[inline (always)] pub fn is_disabled (& self) -> bool { * self == GpioIntDedge :: Disabled }
#[doc = "Dual-edge triggered"]
#[inline (always)] pub fn is_enabled (& self) -> bool { * self == GpioIntDedge :: Enabled } }
#[doc = "Field `gpio_int_dedge` writer - Dual-edge interrupt enable: 0=disabled; 1=enabled"] pub type GpioIntDedgeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 , GpioIntDedge > ; impl < 'a , REG > GpioIntDedgeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Single-edge mode"]
#[inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (GpioIntDedge :: Disabled) }
#[doc = "Dual-edge triggered"]
#[inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (GpioIntDedge :: Enabled) } } impl R {
#[doc = "Bits 0:7 - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn gpio_int_dedge (& self) -> GpioIntDedgeR { GpioIntDedgeR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn gpio_int_dedge (& mut self) -> GpioIntDedgeW < '_ , GpioIntDedgeSpec > { GpioIntDedgeW :: new (self , 0) } }
#[doc = "GPIO dual-edge interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_dedge::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_dedge::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioIntDedgeSpec ; impl crate :: RegisterSpec for GpioIntDedgeSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_int_dedge::R`](R) reader structure"] impl crate :: Readable for GpioIntDedgeSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_int_dedge::W`](W) writer structure"] impl crate :: Writable for GpioIntDedgeSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_INT_DEDGE to value 0"] impl crate :: Resettable for GpioIntDedgeSpec { } }
#[doc = "GPIO_INT_DEBOUNCE (rw) register accessor: GPIO interrupt debounce control register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_debounce::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_debounce::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_debounce`] module"]
#[doc (alias = "GPIO_INT_DEBOUNCE")] pub type GpioIntDebounce = crate :: Reg < gpio_int_debounce :: GpioIntDebounceSpec > ;
#[doc = "GPIO interrupt debounce control register"] pub mod gpio_int_debounce {
#[doc = "Register `GPIO_INT_DEBOUNCE` reader"] pub type R = crate :: R < GpioIntDebounceSpec > ;
#[doc = "Register `GPIO_INT_DEBOUNCE` writer"] pub type W = crate :: W < GpioIntDebounceSpec > ;
#[doc = "Field `gpio_int_debounce` reader - Debounce enable: 0=disabled; 1=enabled"] pub type GpioIntDebounceR = crate :: FieldReader ;
#[doc = "Field `gpio_int_debounce` writer - Debounce enable: 0=disabled; 1=enabled"] pub type GpioIntDebounceW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - Debounce enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn gpio_int_debounce (& self) -> GpioIntDebounceR { GpioIntDebounceR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Debounce enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn gpio_int_debounce (& mut self) -> GpioIntDebounceW < '_ , GpioIntDebounceSpec > { GpioIntDebounceW :: new (self , 0) } }
#[doc = "GPIO interrupt debounce control register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_debounce::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_debounce::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioIntDebounceSpec ; impl crate :: RegisterSpec for GpioIntDebounceSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_int_debounce::R`](R) reader structure"] impl crate :: Readable for GpioIntDebounceSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_int_debounce::W`](W) writer structure"] impl crate :: Writable for GpioIntDebounceSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_INT_DEBOUNCE to value 0"] impl crate :: Resettable for GpioIntDebounceSpec { } }
#[doc = "GPIO_INT_RAW (rw) register accessor: GPIO raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_raw`] module"]
#[doc (alias = "GPIO_INT_RAW")] pub type GpioIntRaw = crate :: Reg < gpio_int_raw :: GpioIntRawSpec > ;
#[doc = "GPIO raw interrupt status register"] pub mod gpio_int_raw {
#[doc = "Register `GPIO_INT_RAW` reader"] pub type R = crate :: R < GpioIntRawSpec > ;
#[doc = "Register `GPIO_INT_RAW` writer"] pub type W = crate :: W < GpioIntRawSpec > ;
#[doc = "Field `gpio_int_raw` reader - Raw interrupt status (before mask): 0=no interrupt; 1=interrupt"] pub type GpioIntRawR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - Raw interrupt status (before mask): 0=no interrupt; 1=interrupt"]
#[inline (always)] pub fn gpio_int_raw (& self) -> GpioIntRawR { GpioIntRawR :: new ((self . bits & 0xff) as u8) } } impl W { }
#[doc = "GPIO raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioIntRawSpec ; impl crate :: RegisterSpec for GpioIntRawSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_int_raw::R`](R) reader structure"] impl crate :: Readable for GpioIntRawSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_int_raw::W`](W) writer structure"] impl crate :: Writable for GpioIntRawSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_INT_RAW to value 0"] impl crate :: Resettable for GpioIntRawSpec { } }
#[doc = "GPIO_INTR (rw) register accessor: GPIO interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_intr`] module"]
#[doc (alias = "GPIO_INTR")] pub type GpioIntr = crate :: Reg < gpio_intr :: GpioIntrSpec > ;
#[doc = "GPIO interrupt status register"] pub mod gpio_intr {
#[doc = "Register `GPIO_INTR` reader"] pub type R = crate :: R < GpioIntrSpec > ;
#[doc = "Register `GPIO_INTR` writer"] pub type W = crate :: W < GpioIntrSpec > ;
#[doc = "Field `gpio_intr` reader - Interrupt status (after mask): 0=no interrupt; 1=interrupt"] pub type GpioIntrR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - Interrupt status (after mask): 0=no interrupt; 1=interrupt"]
#[inline (always)] pub fn gpio_intr (& self) -> GpioIntrR { GpioIntrR :: new ((self . bits & 0xff) as u8) } } impl W { }
#[doc = "GPIO interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioIntrSpec ; impl crate :: RegisterSpec for GpioIntrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_intr::R`](R) reader structure"] impl crate :: Readable for GpioIntrSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_intr::W`](W) writer structure"] impl crate :: Writable for GpioIntrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_INTR to value 0"] impl crate :: Resettable for GpioIntrSpec { } }
#[doc = "GPIO_INT_EOI (rw) register accessor: GPIO interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_eoi`] module"]
#[doc (alias = "GPIO_INT_EOI")] pub type GpioIntEoi = crate :: Reg < gpio_int_eoi :: GpioIntEoiSpec > ;
#[doc = "GPIO interrupt clear register"] pub mod gpio_int_eoi {
#[doc = "Register `GPIO_INT_EOI` reader"] pub type R = crate :: R < GpioIntEoiSpec > ;
#[doc = "Register `GPIO_INT_EOI` writer"] pub type W = crate :: W < GpioIntEoiSpec > ;
#[doc = "Field `gpio_int_eoi` writer - Edge interrupt clear: 0=no clear; 1=clear interrupt"] pub type GpioIntEoiW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl W {
#[doc = "Bits 0:7 - Edge interrupt clear: 0=no clear; 1=clear interrupt"]
#[inline (always)] pub fn gpio_int_eoi (& mut self) -> GpioIntEoiW < '_ , GpioIntEoiSpec > { GpioIntEoiW :: new (self , 0) } }
#[doc = "GPIO interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioIntEoiSpec ; impl crate :: RegisterSpec for GpioIntEoiSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_int_eoi::R`](R) reader structure"] impl crate :: Readable for GpioIntEoiSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_int_eoi::W`](W) writer structure"] impl crate :: Writable for GpioIntEoiSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_INT_EOI to value 0"] impl crate :: Resettable for GpioIntEoiSpec { } }
#[doc = "GPIO_DATA_SET (rw) register accessor: GPIO data set register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_data_set`] module"]
#[doc (alias = "GPIO_DATA_SET")] pub type GpioDataSet = crate :: Reg < gpio_data_set :: GpioDataSetSpec > ;
#[doc = "GPIO data set register"] pub mod gpio_data_set {
#[doc = "Register `GPIO_DATA_SET` reader"] pub type R = crate :: R < GpioDataSetSpec > ;
#[doc = "Register `GPIO_DATA_SET` writer"] pub type W = crate :: W < GpioDataSetSpec > ;
#[doc = "Field `gpio_data_set` writer - Write 1 to set corresponding GPIO_SW_OUT bits"] pub type GpioDataSetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl W {
#[doc = "Bits 0:7 - Write 1 to set corresponding GPIO_SW_OUT bits"]
#[inline (always)] pub fn gpio_data_set (& mut self) -> GpioDataSetW < '_ , GpioDataSetSpec > { GpioDataSetW :: new (self , 0) } }
#[doc = "GPIO data set register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioDataSetSpec ; impl crate :: RegisterSpec for GpioDataSetSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_data_set::R`](R) reader structure"] impl crate :: Readable for GpioDataSetSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_data_set::W`](W) writer structure"] impl crate :: Writable for GpioDataSetSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_DATA_SET to value 0"] impl crate :: Resettable for GpioDataSetSpec { } }
#[doc = "GPIO_DATA_CLR (rw) register accessor: GPIO data clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_data_clr`] module"]
#[doc (alias = "GPIO_DATA_CLR")] pub type GpioDataClr = crate :: Reg < gpio_data_clr :: GpioDataClrSpec > ;
#[doc = "GPIO data clear register"] pub mod gpio_data_clr {
#[doc = "Register `GPIO_DATA_CLR` reader"] pub type R = crate :: R < GpioDataClrSpec > ;
#[doc = "Register `GPIO_DATA_CLR` writer"] pub type W = crate :: W < GpioDataClrSpec > ;
#[doc = "Field `gpio_data_clr` writer - Write 1 to clear corresponding GPIO_SW_OUT bits"] pub type GpioDataClrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl W {
#[doc = "Bits 0:7 - Write 1 to clear corresponding GPIO_SW_OUT bits"]
#[inline (always)] pub fn gpio_data_clr (& mut self) -> GpioDataClrW < '_ , GpioDataClrSpec > { GpioDataClrW :: new (self , 0) } }
#[doc = "GPIO data clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GpioDataClrSpec ; impl crate :: RegisterSpec for GpioDataClrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`gpio_data_clr::R`](R) reader structure"] impl crate :: Readable for GpioDataClrSpec { }
#[doc = "`write(|w| ..)` method takes [`gpio_data_clr::W`](W) writer structure"] impl crate :: Writable for GpioDataClrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GPIO_DATA_CLR to value 0"] impl crate :: Resettable for GpioDataClrSpec { } } }
#[doc = "GPIO controller for GPIO\\[15:8\\]"] pub type Gpio1 = crate :: Periph < gpio0 :: RegisterBlock , 0x4402_9000 > ; impl core :: fmt :: Debug for Gpio1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Gpio1") . finish () } }
#[doc = "GPIO controller for GPIO\\[15:8\\]"] pub use self :: gpio0 as gpio1 ;
#[doc = "GPIO controller for GPIO\\[18:16\\] — only 3 bits used; bits \\[7:3\\] are reserved and unused."] pub type Gpio2 = crate :: Periph < gpio0 :: RegisterBlock , 0x4402_a000 > ; impl core :: fmt :: Debug for Gpio2 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Gpio2") . finish () } }
#[doc = "GPIO controller for GPIO\\[18:16\\] — only 3 bits used; bits \\[7:3\\] are reserved and unused."] pub use self :: gpio0 as gpio2 ;
#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"] pub type Uart0 = crate :: Periph < uart0 :: RegisterBlock , 0x4401_0000 > ; impl core :: fmt :: Debug for Uart0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Uart0") . finish () } }
#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"] pub mod uart0 {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { intr_id : IntrId , _reserved1 : [u8 ; 0x02] , data : Data , _reserved2 : [u8 ; 0x02] , uart_ctl : UartCtl , _reserved3 : [u8 ; 0x02] , div_h : DivH , _reserved4 : [u8 ; 0x02] , div_l : DivL , _reserved5 : [u8 ; 0x02] , div_fra : DivFra , _reserved6 : [u8 ; 0x02] , intr_en : IntrEn , _reserved7 : [u8 ; 0x02] , intr_status : IntrStatus , _reserved8 : [u8 ; 0x06] , fifo_ctl : FifoCtl , _reserved9 : [u8 ; 0x02] , far : Far , _reserved10 : [u8 ; 0x02] , modem_ctl : ModemCtl , _reserved11 : [u8 ; 0x02] , modem_status : ModemStatus , _reserved12 : [u8 ; 0x02] , line_status : LineStatus , _reserved13 : [u8 ; 0x02] , uart_gp_reg : UartGpReg , _reserved14 : [u8 ; 0x02] , tx_fifo_read : TxFifoRead , _reserved15 : [u8 ; 0x02] , rx_fifo_write : RxFifoWrite , _reserved16 : [u8 ; 0x02] , fifo_status : FifoStatus , _reserved17 : [u8 ; 0x02] , tx_fifo_cnt : TxFifoCnt , _reserved18 : [u8 ; 0x02] , rx_fifo_cnt : RxFifoCnt , _reserved19 : [u8 ; 0x02] , halt_tx : HaltTx , _reserved20 : [u8 ; 0x02] , dma_sw_ack : DmaSwAck , _reserved21 : [u8 ; 0x02] , baud_ctl : BaudCtl , _reserved22 : [u8 ; 0x02] , stp_ctl : StpCtl , _reserved23 : [u8 ; 0x02] , uart_parameter : UartParameter , } impl RegisterBlock {
#[doc = "0x00 - Interrupt ID register"]
#[inline (always)] pub const fn intr_id (& self) -> & IntrId { & self . intr_id }
#[doc = "0x04 - Data register"]
#[inline (always)] pub const fn data (& self) -> & Data { & self . data }
#[doc = "0x08 - UART control register"]
#[inline (always)] pub const fn uart_ctl (& self) -> & UartCtl { & self . uart_ctl }
#[doc = "0x0c - Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
#[inline (always)] pub const fn div_h (& self) -> & DivH { & self . div_h }
#[doc = "0x10 - Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
#[inline (always)] pub const fn div_l (& self) -> & DivL { & self . div_l }
#[doc = "0x14 - Baud rate divider fractional part"]
#[inline (always)] pub const fn div_fra (& self) -> & DivFra { & self . div_fra }
#[doc = "0x18 - Interrupt enable register"]
#[inline (always)] pub const fn intr_en (& self) -> & IntrEn { & self . intr_en }
#[doc = "0x1c - Interrupt status register"]
#[inline (always)] pub const fn intr_status (& self) -> & IntrStatus { & self . intr_status }
#[doc = "0x24 - FIFO control register"]
#[inline (always)] pub const fn fifo_ctl (& self) -> & FifoCtl { & self . fifo_ctl }
#[doc = "0x28 - FIFO access mode enable register"]
#[inline (always)] pub const fn far (& self) -> & Far { & self . far }
#[doc = "0x2c - Modem control register"]
#[inline (always)] pub const fn modem_ctl (& self) -> & ModemCtl { & self . modem_ctl }
#[doc = "0x30 - Modem status register"]
#[inline (always)] pub const fn modem_status (& self) -> & ModemStatus { & self . modem_status }
#[doc = "0x34 - Line status register"]
#[inline (always)] pub const fn line_status (& self) -> & LineStatus { & self . line_status }
#[doc = "0x38 - UART general purpose register"]
#[inline (always)] pub const fn uart_gp_reg (& self) -> & UartGpReg { & self . uart_gp_reg }
#[doc = "0x3c - TX FIFO read register"]
#[inline (always)] pub const fn tx_fifo_read (& self) -> & TxFifoRead { & self . tx_fifo_read }
#[doc = "0x40 - RX FIFO write register"]
#[inline (always)] pub const fn rx_fifo_write (& self) -> & RxFifoWrite { & self . rx_fifo_write }
#[doc = "0x44 - FIFO status register"]
#[inline (always)] pub const fn fifo_status (& self) -> & FifoStatus { & self . fifo_status }
#[doc = "0x48 - TX FIFO data counter"]
#[inline (always)] pub const fn tx_fifo_cnt (& self) -> & TxFifoCnt { & self . tx_fifo_cnt }
#[doc = "0x4c - RX FIFO data counter"]
#[inline (always)] pub const fn rx_fifo_cnt (& self) -> & RxFifoCnt { & self . rx_fifo_cnt }
#[doc = "0x50 - TX halt register"]
#[inline (always)] pub const fn halt_tx (& self) -> & HaltTx { & self . halt_tx }
#[doc = "0x54 - DMA software acknowledge register"]
#[inline (always)] pub const fn dma_sw_ack (& self) -> & DmaSwAck { & self . dma_sw_ack }
#[doc = "0x58 - Baud rate control register"]
#[inline (always)] pub const fn baud_ctl (& self) -> & BaudCtl { & self . baud_ctl }
#[doc = "0x5c - Stop bit control register"]
#[inline (always)] pub const fn stp_ctl (& self) -> & StpCtl { & self . stp_ctl }
#[doc = "0x60 - UART parameter register"]
#[inline (always)] pub const fn uart_parameter (& self) -> & UartParameter { & self . uart_parameter } }
#[doc = "INTR_ID (rw) register accessor: Interrupt ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_id`] module"]
#[doc (alias = "INTR_ID")] pub type IntrId = crate :: Reg < intr_id :: IntrIdSpec > ;
#[doc = "Interrupt ID register"] pub mod intr_id {
#[doc = "Register `INTR_ID` reader"] pub type R = crate :: R < IntrIdSpec > ;
#[doc = "Register `INTR_ID` writer"] pub type W = crate :: W < IntrIdSpec > ;
#[doc = "Field `intr_id` reader - Interrupt ID: 0x0=modem status; 0x1=no interrupt; 0x2=THR empty; 0x4=rx data; 0x6=rx line status; 0x7=busy; 0xC=char timeout"] pub type IntrIdR = crate :: FieldReader ;
#[doc = "Field `fifo_en_s` reader - FIFO enable status: 0=FIFO disabled; 1=FIFO enabled"] pub type FifoEnSR = crate :: BitReader ; impl R {
#[doc = "Bits 0:3 - Interrupt ID: 0x0=modem status; 0x1=no interrupt; 0x2=THR empty; 0x4=rx data; 0x6=rx line status; 0x7=busy; 0xC=char timeout"]
#[inline (always)] pub fn intr_id (& self) -> IntrIdR { IntrIdR :: new ((self . bits & 0x0f) as u8) }
#[doc = "Bit 4 - FIFO enable status: 0=FIFO disabled; 1=FIFO enabled"]
#[inline (always)] pub fn fifo_en_s (& self) -> FifoEnSR { FifoEnSR :: new (((self . bits >> 4) & 1) != 0) } } impl W { }
#[doc = "Interrupt ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntrIdSpec ; impl crate :: RegisterSpec for IntrIdSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`intr_id::R`](R) reader structure"] impl crate :: Readable for IntrIdSpec { }
#[doc = "`write(|w| ..)` method takes [`intr_id::W`](W) writer structure"] impl crate :: Writable for IntrIdSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INTR_ID to value 0x01"] impl crate :: Resettable for IntrIdSpec { const RESET_VALUE : u16 = 0x01 ; } }
#[doc = "DATA (rw) register accessor: Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
#[doc (alias = "DATA")] pub type Data = crate :: Reg < data :: DataSpec > ;
#[doc = "Data register"] pub mod data {
#[doc = "Register `DATA` reader"] pub type R = crate :: R < DataSpec > ;
#[doc = "Register `DATA` writer"] pub type W = crate :: W < DataSpec > ;
#[doc = "Field `data` reader - Write: TX data; Read: RX data"] pub type DataR = crate :: FieldReader ;
#[doc = "Field `data` writer - Write: TX data; Read: RX data"] pub type DataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - Write: TX data; Read: RX data"]
#[inline (always)] pub fn data (& self) -> DataR { DataR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Write: TX data; Read: RX data"]
#[inline (always)] pub fn data (& mut self) -> DataW < '_ , DataSpec > { DataW :: new (self , 0) } }
#[doc = "Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DataSpec ; impl crate :: RegisterSpec for DataSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`data::R`](R) reader structure"] impl crate :: Readable for DataSpec { }
#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] impl crate :: Writable for DataSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DATA to value 0"] impl crate :: Resettable for DataSpec { } }
#[doc = "UART_CTL (rw) register accessor: UART control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_ctl`] module"]
#[doc (alias = "UART_CTL")] pub type UartCtl = crate :: Reg < uart_ctl :: UartCtlSpec > ;
#[doc = "UART control register"] pub mod uart_ctl {
#[doc = "Register `UART_CTL` reader"] pub type R = crate :: R < UartCtlSpec > ;
#[doc = "Register `UART_CTL` writer"] pub type W = crate :: W < UartCtlSpec > ;
#[doc = "Field `div_en` reader - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"] pub type DivEnR = crate :: BitReader ;
#[doc = "Field `div_en` writer - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"] pub type DivEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `xbreak` reader - Break control: 0=normal; 1=force TX to space"] pub type XbreakR = crate :: BitReader ;
#[doc = "Field `xbreak` writer - Break control: 0=normal; 1=force TX to space"] pub type XbreakW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum Dlen {
#[doc = "0: 5-bit data"] Bits5 = 0 ,
#[doc = "1: 6-bit data"] Bits6 = 1 ,
#[doc = "2: 7-bit data"] Bits7 = 2 ,
#[doc = "3: 8-bit data"] Bits8 = 3 , } impl From < Dlen > for u8 {
#[inline (always)] fn from (variant : Dlen) -> Self { variant as _ } } impl crate :: FieldSpec for Dlen { type Ux = u8 ; } impl crate :: IsEnum for Dlen { }
#[doc = "Field `dlen` reader - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"] pub type DlenR = crate :: FieldReader < Dlen > ; impl DlenR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Dlen { match self . bits { 0 => Dlen :: Bits5 , 1 => Dlen :: Bits6 , 2 => Dlen :: Bits7 , 3 => Dlen :: Bits8 , _ => unreachable ! () , } }
#[doc = "5-bit data"]
#[inline (always)] pub fn is_bits5 (& self) -> bool { * self == Dlen :: Bits5 }
#[doc = "6-bit data"]
#[inline (always)] pub fn is_bits6 (& self) -> bool { * self == Dlen :: Bits6 }
#[doc = "7-bit data"]
#[inline (always)] pub fn is_bits7 (& self) -> bool { * self == Dlen :: Bits7 }
#[doc = "8-bit data"]
#[inline (always)] pub fn is_bits8 (& self) -> bool { * self == Dlen :: Bits8 } }
#[doc = "Field `dlen` writer - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"] pub type DlenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Dlen , crate :: Safe > ; impl < 'a , REG > DlenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "5-bit data"]
#[inline (always)] pub fn bits5 (self) -> & 'a mut crate :: W < REG > { self . variant (Dlen :: Bits5) }
#[doc = "6-bit data"]
#[inline (always)] pub fn bits6 (self) -> & 'a mut crate :: W < REG > { self . variant (Dlen :: Bits6) }
#[doc = "7-bit data"]
#[inline (always)] pub fn bits7 (self) -> & 'a mut crate :: W < REG > { self . variant (Dlen :: Bits7) }
#[doc = "8-bit data"]
#[inline (always)] pub fn bits8 (self) -> & 'a mut crate :: W < REG > { self . variant (Dlen :: Bits8) } }
#[doc = "Parity select: 0=odd; 1=even\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Eps {
#[doc = "0: Odd parity"] Odd = 0 ,
#[doc = "1: Even parity"] Even = 1 , } impl From < Eps > for bool {
#[inline (always)] fn from (variant : Eps) -> Self { variant as u8 != 0 } }
#[doc = "Field `eps` reader - Parity select: 0=odd; 1=even"] pub type EpsR = crate :: BitReader < Eps > ; impl EpsR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Eps { match self . bits { false => Eps :: Odd , true => Eps :: Even , } }
#[doc = "Odd parity"]
#[inline (always)] pub fn is_odd (& self) -> bool { * self == Eps :: Odd }
#[doc = "Even parity"]
#[inline (always)] pub fn is_even (& self) -> bool { * self == Eps :: Even } }
#[doc = "Field `eps` writer - Parity select: 0=odd; 1=even"] pub type EpsW < 'a , REG > = crate :: BitWriter < 'a , REG , Eps > ; impl < 'a , REG > EpsW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "Odd parity"]
#[inline (always)] pub fn odd (self) -> & 'a mut crate :: W < REG > { self . variant (Eps :: Odd) }
#[doc = "Even parity"]
#[inline (always)] pub fn even (self) -> & 'a mut crate :: W < REG > { self . variant (Eps :: Even) } }
#[doc = "Parity enable: 0=disabled; 1=enabled\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Pen {
#[doc = "0: No parity"] Disabled = 0 ,
#[doc = "1: Parity enabled"] Enabled = 1 , } impl From < Pen > for bool {
#[inline (always)] fn from (variant : Pen) -> Self { variant as u8 != 0 } }
#[doc = "Field `pen` reader - Parity enable: 0=disabled; 1=enabled"] pub type PenR = crate :: BitReader < Pen > ; impl PenR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Pen { match self . bits { false => Pen :: Disabled , true => Pen :: Enabled , } }
#[doc = "No parity"]
#[inline (always)] pub fn is_disabled (& self) -> bool { * self == Pen :: Disabled }
#[doc = "Parity enabled"]
#[inline (always)] pub fn is_enabled (& self) -> bool { * self == Pen :: Enabled } }
#[doc = "Field `pen` writer - Parity enable: 0=disabled; 1=enabled"] pub type PenW < 'a , REG > = crate :: BitWriter < 'a , REG , Pen > ; impl < 'a , REG > PenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "No parity"]
#[inline (always)] pub fn disabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pen :: Disabled) }
#[doc = "Parity enabled"]
#[inline (always)] pub fn enabled (self) -> & 'a mut crate :: W < REG > { self . variant (Pen :: Enabled) } }
#[doc = "Field `sps` reader - Sticky parity: 0=disabled; 1=enabled"] pub type SpsR = crate :: BitReader ;
#[doc = "Field `sps` writer - Sticky parity: 0=disabled; 1=enabled"] pub type SpsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Stop bits: 0=1bit; 1=1.5/2bit\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Stp {
#[doc = "0: 1 stop bit"] Stop1 = 0 ,
#[doc = "1: 1.5 (5-bit data) or 2 stop bits"] Stop1_5Or2 = 1 , } impl From < Stp > for bool {
#[inline (always)] fn from (variant : Stp) -> Self { variant as u8 != 0 } }
#[doc = "Field `stp` reader - Stop bits: 0=1bit; 1=1.5/2bit"] pub type StpR = crate :: BitReader < Stp > ; impl StpR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Stp { match self . bits { false => Stp :: Stop1 , true => Stp :: Stop1_5Or2 , } }
#[doc = "1 stop bit"]
#[inline (always)] pub fn is_stop1 (& self) -> bool { * self == Stp :: Stop1 }
#[doc = "1.5 (5-bit data) or 2 stop bits"]
#[inline (always)] pub fn is_stop1_5_or_2 (& self) -> bool { * self == Stp :: Stop1_5Or2 } }
#[doc = "Field `stp` writer - Stop bits: 0=1bit; 1=1.5/2bit"] pub type StpW < 'a , REG > = crate :: BitWriter < 'a , REG , Stp > ; impl < 'a , REG > StpW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "1 stop bit"]
#[inline (always)] pub fn stop1 (self) -> & 'a mut crate :: W < REG > { self . variant (Stp :: Stop1) }
#[doc = "1.5 (5-bit data) or 2 stop bits"]
#[inline (always)] pub fn stop1_5_or_2 (self) -> & 'a mut crate :: W < REG > { self . variant (Stp :: Stop1_5Or2) } } impl R {
#[doc = "Bit 0 - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
#[inline (always)] pub fn div_en (& self) -> DivEnR { DivEnR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Break control: 0=normal; 1=force TX to space"]
#[inline (always)] pub fn xbreak (& self) -> XbreakR { XbreakR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bits 2:3 - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
#[inline (always)] pub fn dlen (& self) -> DlenR { DlenR :: new (((self . bits >> 2) & 3) as u8) }
#[doc = "Bit 4 - Parity select: 0=odd; 1=even"]
#[inline (always)] pub fn eps (& self) -> EpsR { EpsR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Parity enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn pen (& self) -> PenR { PenR :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Sticky parity: 0=disabled; 1=enabled"]
#[inline (always)] pub fn sps (& self) -> SpsR { SpsR :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 7 - Stop bits: 0=1bit; 1=1.5/2bit"]
#[inline (always)] pub fn stp (& self) -> StpR { StpR :: new (((self . bits >> 7) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
#[inline (always)] pub fn div_en (& mut self) -> DivEnW < '_ , UartCtlSpec > { DivEnW :: new (self , 0) }
#[doc = "Bit 1 - Break control: 0=normal; 1=force TX to space"]
#[inline (always)] pub fn xbreak (& mut self) -> XbreakW < '_ , UartCtlSpec > { XbreakW :: new (self , 1) }
#[doc = "Bits 2:3 - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
#[inline (always)] pub fn dlen (& mut self) -> DlenW < '_ , UartCtlSpec > { DlenW :: new (self , 2) }
#[doc = "Bit 4 - Parity select: 0=odd; 1=even"]
#[inline (always)] pub fn eps (& mut self) -> EpsW < '_ , UartCtlSpec > { EpsW :: new (self , 4) }
#[doc = "Bit 5 - Parity enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn pen (& mut self) -> PenW < '_ , UartCtlSpec > { PenW :: new (self , 5) }
#[doc = "Bit 6 - Sticky parity: 0=disabled; 1=enabled"]
#[inline (always)] pub fn sps (& mut self) -> SpsW < '_ , UartCtlSpec > { SpsW :: new (self , 6) }
#[doc = "Bit 7 - Stop bits: 0=1bit; 1=1.5/2bit"]
#[inline (always)] pub fn stp (& mut self) -> StpW < '_ , UartCtlSpec > { StpW :: new (self , 7) } }
#[doc = "UART control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UartCtlSpec ; impl crate :: RegisterSpec for UartCtlSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`uart_ctl::R`](R) reader structure"] impl crate :: Readable for UartCtlSpec { }
#[doc = "`write(|w| ..)` method takes [`uart_ctl::W`](W) writer structure"] impl crate :: Writable for UartCtlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets UART_CTL to value 0"] impl crate :: Resettable for UartCtlSpec { } }
#[doc = "DIV_H (rw) register accessor: Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_h`] module"]
#[doc (alias = "DIV_H")] pub type DivH = crate :: Reg < div_h :: DivHSpec > ;
#[doc = "Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"] pub mod div_h {
#[doc = "Register `DIV_H` reader"] pub type R = crate :: R < DivHSpec > ;
#[doc = "Register `DIV_H` writer"] pub type W = crate :: W < DivHSpec > ;
#[doc = "Field `div_h` reader - Divider integer high 8 bits"] pub type DivHR = crate :: FieldReader ;
#[doc = "Field `div_h` writer - Divider integer high 8 bits"] pub type DivHW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - Divider integer high 8 bits"]
#[inline (always)] pub fn div_h (& self) -> DivHR { DivHR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Divider integer high 8 bits"]
#[inline (always)] pub fn div_h (& mut self) -> DivHW < '_ , DivHSpec > { DivHW :: new (self , 0) } }
#[doc = "Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DivHSpec ; impl crate :: RegisterSpec for DivHSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`div_h::R`](R) reader structure"] impl crate :: Readable for DivHSpec { }
#[doc = "`write(|w| ..)` method takes [`div_h::W`](W) writer structure"] impl crate :: Writable for DivHSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DIV_H to value 0"] impl crate :: Resettable for DivHSpec { } }
#[doc = "DIV_L (rw) register accessor: Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_l`] module"]
#[doc (alias = "DIV_L")] pub type DivL = crate :: Reg < div_l :: DivLSpec > ;
#[doc = "Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"] pub mod div_l {
#[doc = "Register `DIV_L` reader"] pub type R = crate :: R < DivLSpec > ;
#[doc = "Register `DIV_L` writer"] pub type W = crate :: W < DivLSpec > ;
#[doc = "Field `div_l` reader - Divider integer low 8 bits"] pub type DivLR = crate :: FieldReader ;
#[doc = "Field `div_l` writer - Divider integer low 8 bits"] pub type DivLW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - Divider integer low 8 bits"]
#[inline (always)] pub fn div_l (& self) -> DivLR { DivLR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Divider integer low 8 bits"]
#[inline (always)] pub fn div_l (& mut self) -> DivLW < '_ , DivLSpec > { DivLW :: new (self , 0) } }
#[doc = "Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DivLSpec ; impl crate :: RegisterSpec for DivLSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`div_l::R`](R) reader structure"] impl crate :: Readable for DivLSpec { }
#[doc = "`write(|w| ..)` method takes [`div_l::W`](W) writer structure"] impl crate :: Writable for DivLSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DIV_L to value 0"] impl crate :: Resettable for DivLSpec { } }
#[doc = "DIV_FRA (rw) register accessor: Baud rate divider fractional part\n\nYou can [`read`](crate::Reg::read) this register and get [`div_fra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_fra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_fra`] module"]
#[doc (alias = "DIV_FRA")] pub type DivFra = crate :: Reg < div_fra :: DivFraSpec > ;
#[doc = "Baud rate divider fractional part"] pub mod div_fra {
#[doc = "Register `DIV_FRA` reader"] pub type R = crate :: R < DivFraSpec > ;
#[doc = "Register `DIV_FRA` writer"] pub type W = crate :: W < DivFraSpec > ;
#[doc = "Field `div_fra` reader - Divider fractional part (divided by 2^6)"] pub type DivFraR = crate :: FieldReader ;
#[doc = "Field `div_fra` writer - Divider fractional part (divided by 2^6)"] pub type DivFraW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R {
#[doc = "Bits 0:5 - Divider fractional part (divided by 2^6)"]
#[inline (always)] pub fn div_fra (& self) -> DivFraR { DivFraR :: new ((self . bits & 0x3f) as u8) } } impl W {
#[doc = "Bits 0:5 - Divider fractional part (divided by 2^6)"]
#[inline (always)] pub fn div_fra (& mut self) -> DivFraW < '_ , DivFraSpec > { DivFraW :: new (self , 0) } }
#[doc = "Baud rate divider fractional part\n\nYou can [`read`](crate::Reg::read) this register and get [`div_fra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_fra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DivFraSpec ; impl crate :: RegisterSpec for DivFraSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`div_fra::R`](R) reader structure"] impl crate :: Readable for DivFraSpec { }
#[doc = "`write(|w| ..)` method takes [`div_fra::W`](W) writer structure"] impl crate :: Writable for DivFraSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DIV_FRA to value 0"] impl crate :: Resettable for DivFraSpec { } }
#[doc = "INTR_EN (rw) register accessor: Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_en`] module"]
#[doc (alias = "INTR_EN")] pub type IntrEn = crate :: Reg < intr_en :: IntrEnSpec > ;
#[doc = "Interrupt enable register"] pub mod intr_en {
#[doc = "Register `INTR_EN` reader"] pub type R = crate :: R < IntrEnSpec > ;
#[doc = "Register `INTR_EN` writer"] pub type W = crate :: W < IntrEnSpec > ;
#[doc = "Field `rece_line_stat_intr_en` reader - RX line status interrupt enable"] pub type ReceLineStatIntrEnR = crate :: BitReader ;
#[doc = "Field `rece_line_stat_intr_en` writer - RX line status interrupt enable"] pub type ReceLineStatIntrEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `modem_intr_en` reader - Modem status interrupt enable"] pub type ModemIntrEnR = crate :: BitReader ;
#[doc = "Field `modem_intr_en` writer - Modem status interrupt enable"] pub type ModemIntrEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rece_data_intr_en` reader - RX data available interrupt enable"] pub type ReceDataIntrEnR = crate :: BitReader ;
#[doc = "Field `rece_data_intr_en` writer - RX data available interrupt enable"] pub type ReceDataIntrEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tran_em_intr_en` reader - TX empty interrupt enable"] pub type TranEmIntrEnR = crate :: BitReader ;
#[doc = "Field `tran_em_intr_en` writer - TX empty interrupt enable"] pub type TranEmIntrEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `ptim_en` reader - Programmable THRE interrupt mode enable"] pub type PtimEnR = crate :: BitReader ;
#[doc = "Field `ptim_en` writer - Programmable THRE interrupt mode enable"] pub type PtimEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - RX line status interrupt enable"]
#[inline (always)] pub fn rece_line_stat_intr_en (& self) -> ReceLineStatIntrEnR { ReceLineStatIntrEnR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Modem status interrupt enable"]
#[inline (always)] pub fn modem_intr_en (& self) -> ModemIntrEnR { ModemIntrEnR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - RX data available interrupt enable"]
#[inline (always)] pub fn rece_data_intr_en (& self) -> ReceDataIntrEnR { ReceDataIntrEnR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - TX empty interrupt enable"]
#[inline (always)] pub fn tran_em_intr_en (& self) -> TranEmIntrEnR { TranEmIntrEnR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Programmable THRE interrupt mode enable"]
#[inline (always)] pub fn ptim_en (& self) -> PtimEnR { PtimEnR :: new (((self . bits >> 4) & 1) != 0) } } impl W {
#[doc = "Bit 0 - RX line status interrupt enable"]
#[inline (always)] pub fn rece_line_stat_intr_en (& mut self) -> ReceLineStatIntrEnW < '_ , IntrEnSpec > { ReceLineStatIntrEnW :: new (self , 0) }
#[doc = "Bit 1 - Modem status interrupt enable"]
#[inline (always)] pub fn modem_intr_en (& mut self) -> ModemIntrEnW < '_ , IntrEnSpec > { ModemIntrEnW :: new (self , 1) }
#[doc = "Bit 2 - RX data available interrupt enable"]
#[inline (always)] pub fn rece_data_intr_en (& mut self) -> ReceDataIntrEnW < '_ , IntrEnSpec > { ReceDataIntrEnW :: new (self , 2) }
#[doc = "Bit 3 - TX empty interrupt enable"]
#[inline (always)] pub fn tran_em_intr_en (& mut self) -> TranEmIntrEnW < '_ , IntrEnSpec > { TranEmIntrEnW :: new (self , 3) }
#[doc = "Bit 4 - Programmable THRE interrupt mode enable"]
#[inline (always)] pub fn ptim_en (& mut self) -> PtimEnW < '_ , IntrEnSpec > { PtimEnW :: new (self , 4) } }
#[doc = "Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntrEnSpec ; impl crate :: RegisterSpec for IntrEnSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`intr_en::R`](R) reader structure"] impl crate :: Readable for IntrEnSpec { }
#[doc = "`write(|w| ..)` method takes [`intr_en::W`](W) writer structure"] impl crate :: Writable for IntrEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INTR_EN to value 0"] impl crate :: Resettable for IntrEnSpec { } }
#[doc = "INTR_STATUS (rw) register accessor: Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status`] module"]
#[doc (alias = "INTR_STATUS")] pub type IntrStatus = crate :: Reg < intr_status :: IntrStatusSpec > ;
#[doc = "Interrupt status register"] pub mod intr_status {
#[doc = "Register `INTR_STATUS` reader"] pub type R = crate :: R < IntrStatusSpec > ;
#[doc = "Register `INTR_STATUS` writer"] pub type W = crate :: W < IntrStatusSpec > ;
#[doc = "Field `busy_det_intr` reader - Busy detect interrupt status"] pub type BusyDetIntrR = crate :: BitReader ;
#[doc = "Field `modem_intr_status` reader - Modem interrupt status"] pub type ModemIntrStatusR = crate :: BitReader ;
#[doc = "Field `thre_intr_status` reader - THR empty interrupt status"] pub type ThreIntrStatusR = crate :: BitReader ;
#[doc = "Field `char_to_intr_status` reader - Character timeout interrupt status"] pub type CharToIntrStatusR = crate :: BitReader ;
#[doc = "Field `data_avail_intr_status` reader - RX data available interrupt status"] pub type DataAvailIntrStatusR = crate :: BitReader ;
#[doc = "Field `line_intr_status` reader - RX line interrupt status"] pub type LineIntrStatusR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Busy detect interrupt status"]
#[inline (always)] pub fn busy_det_intr (& self) -> BusyDetIntrR { BusyDetIntrR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Modem interrupt status"]
#[inline (always)] pub fn modem_intr_status (& self) -> ModemIntrStatusR { ModemIntrStatusR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - THR empty interrupt status"]
#[inline (always)] pub fn thre_intr_status (& self) -> ThreIntrStatusR { ThreIntrStatusR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - Character timeout interrupt status"]
#[inline (always)] pub fn char_to_intr_status (& self) -> CharToIntrStatusR { CharToIntrStatusR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - RX data available interrupt status"]
#[inline (always)] pub fn data_avail_intr_status (& self) -> DataAvailIntrStatusR { DataAvailIntrStatusR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - RX line interrupt status"]
#[inline (always)] pub fn line_intr_status (& self) -> LineIntrStatusR { LineIntrStatusR :: new (((self . bits >> 5) & 1) != 0) } } impl W { }
#[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntrStatusSpec ; impl crate :: RegisterSpec for IntrStatusSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`intr_status::R`](R) reader structure"] impl crate :: Readable for IntrStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`intr_status::W`](W) writer structure"] impl crate :: Writable for IntrStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INTR_STATUS to value 0"] impl crate :: Resettable for IntrStatusSpec { } }
#[doc = "FIFO_CTL (rw) register accessor: FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_ctl`] module"]
#[doc (alias = "FIFO_CTL")] pub type FifoCtl = crate :: Reg < fifo_ctl :: FifoCtlSpec > ;
#[doc = "FIFO control register"] pub mod fifo_ctl {
#[doc = "Register `FIFO_CTL` reader"] pub type R = crate :: R < FifoCtlSpec > ;
#[doc = "Register `FIFO_CTL` writer"] pub type W = crate :: W < FifoCtlSpec > ;
#[doc = "TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum TxEmptyTrig {
#[doc = "0: FIFO empty"] Empty = 0 ,
#[doc = "1: 2 characters remaining"] Chars2 = 1 ,
#[doc = "2: FIFO 1/4 full"] Quarter = 2 ,
#[doc = "3: FIFO 1/2 full"] Half = 3 , } impl From < TxEmptyTrig > for u8 {
#[inline (always)] fn from (variant : TxEmptyTrig) -> Self { variant as _ } } impl crate :: FieldSpec for TxEmptyTrig { type Ux = u8 ; } impl crate :: IsEnum for TxEmptyTrig { }
#[doc = "Field `tx_empty_trig` writer - TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2"] pub type TxEmptyTrigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , TxEmptyTrig , crate :: Safe > ; impl < 'a , REG > TxEmptyTrigW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "FIFO empty"]
#[inline (always)] pub fn empty (self) -> & 'a mut crate :: W < REG > { self . variant (TxEmptyTrig :: Empty) }
#[doc = "2 characters remaining"]
#[inline (always)] pub fn chars2 (self) -> & 'a mut crate :: W < REG > { self . variant (TxEmptyTrig :: Chars2) }
#[doc = "FIFO 1/4 full"]
#[inline (always)] pub fn quarter (self) -> & 'a mut crate :: W < REG > { self . variant (TxEmptyTrig :: Quarter) }
#[doc = "FIFO 1/2 full"]
#[inline (always)] pub fn half (self) -> & 'a mut crate :: W < REG > { self . variant (TxEmptyTrig :: Half) } }
#[doc = "RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum RxEmptyTrig {
#[doc = "0: 1 character in FIFO"] Char1 = 0 ,
#[doc = "1: FIFO 1/4 full"] Quarter = 1 ,
#[doc = "2: FIFO 1/2 full"] Half = 2 ,
#[doc = "3: 2 below full"] Less2 = 3 , } impl From < RxEmptyTrig > for u8 {
#[inline (always)] fn from (variant : RxEmptyTrig) -> Self { variant as _ } } impl crate :: FieldSpec for RxEmptyTrig { type Ux = u8 ; } impl crate :: IsEnum for RxEmptyTrig { }
#[doc = "Field `rx_empty_trig` writer - RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full"] pub type RxEmptyTrigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , RxEmptyTrig , crate :: Safe > ; impl < 'a , REG > RxEmptyTrigW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "1 character in FIFO"]
#[inline (always)] pub fn char1 (self) -> & 'a mut crate :: W < REG > { self . variant (RxEmptyTrig :: Char1) }
#[doc = "FIFO 1/4 full"]
#[inline (always)] pub fn quarter (self) -> & 'a mut crate :: W < REG > { self . variant (RxEmptyTrig :: Quarter) }
#[doc = "FIFO 1/2 full"]
#[inline (always)] pub fn half (self) -> & 'a mut crate :: W < REG > { self . variant (RxEmptyTrig :: Half) }
#[doc = "2 below full"]
#[inline (always)] pub fn less2 (self) -> & 'a mut crate :: W < REG > { self . variant (RxEmptyTrig :: Less2) } }
#[doc = "Field `fifo_en` writer - FIFO enable"] pub type FifoEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tx_fifo_rst` writer - TX FIFO reset: 0=no reset; 1=reset"] pub type TxFifoRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rx_fifo_rst` writer - RX FIFO reset: 0=no reset; 1=reset"] pub type RxFifoRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bits 0:1 - TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2"]
#[inline (always)] pub fn tx_empty_trig (& mut self) -> TxEmptyTrigW < '_ , FifoCtlSpec > { TxEmptyTrigW :: new (self , 0) }
#[doc = "Bits 2:3 - RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full"]
#[inline (always)] pub fn rx_empty_trig (& mut self) -> RxEmptyTrigW < '_ , FifoCtlSpec > { RxEmptyTrigW :: new (self , 2) }
#[doc = "Bit 4 - FIFO enable"]
#[inline (always)] pub fn fifo_en (& mut self) -> FifoEnW < '_ , FifoCtlSpec > { FifoEnW :: new (self , 4) }
#[doc = "Bit 5 - TX FIFO reset: 0=no reset; 1=reset"]
#[inline (always)] pub fn tx_fifo_rst (& mut self) -> TxFifoRstW < '_ , FifoCtlSpec > { TxFifoRstW :: new (self , 5) }
#[doc = "Bit 6 - RX FIFO reset: 0=no reset; 1=reset"]
#[inline (always)] pub fn rx_fifo_rst (& mut self) -> RxFifoRstW < '_ , FifoCtlSpec > { RxFifoRstW :: new (self , 6) } }
#[doc = "FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FifoCtlSpec ; impl crate :: RegisterSpec for FifoCtlSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`fifo_ctl::R`](R) reader structure"] impl crate :: Readable for FifoCtlSpec { }
#[doc = "`write(|w| ..)` method takes [`fifo_ctl::W`](W) writer structure"] impl crate :: Writable for FifoCtlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets FIFO_CTL to value 0"] impl crate :: Resettable for FifoCtlSpec { } }
#[doc = "FAR (rw) register accessor: FIFO access mode enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"]
#[doc (alias = "FAR")] pub type Far = crate :: Reg < far :: FarSpec > ;
#[doc = "FIFO access mode enable register"] pub mod far {
#[doc = "Register `FAR` reader"] pub type R = crate :: R < FarSpec > ;
#[doc = "Register `FAR` writer"] pub type W = crate :: W < FarSpec > ;
#[doc = "Field `far` reader - FIFO access mode: 0=disabled; 1=enabled"] pub type FarR = crate :: BitReader ;
#[doc = "Field `far` writer - FIFO access mode: 0=disabled; 1=enabled"] pub type FarW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - FIFO access mode: 0=disabled; 1=enabled"]
#[inline (always)] pub fn far (& self) -> FarR { FarR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - FIFO access mode: 0=disabled; 1=enabled"]
#[inline (always)] pub fn far (& mut self) -> FarW < '_ , FarSpec > { FarW :: new (self , 0) } }
#[doc = "FIFO access mode enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`far::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`far::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FarSpec ; impl crate :: RegisterSpec for FarSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`far::R`](R) reader structure"] impl crate :: Readable for FarSpec { }
#[doc = "`write(|w| ..)` method takes [`far::W`](W) writer structure"] impl crate :: Writable for FarSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets FAR to value 0"] impl crate :: Resettable for FarSpec { } }
#[doc = "MODEM_CTL (rw) register accessor: Modem control register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modem_ctl`] module"]
#[doc (alias = "MODEM_CTL")] pub type ModemCtl = crate :: Reg < modem_ctl :: ModemCtlSpec > ;
#[doc = "Modem control register"] pub mod modem_ctl {
#[doc = "Register `MODEM_CTL` reader"] pub type R = crate :: R < ModemCtlSpec > ;
#[doc = "Register `MODEM_CTL` writer"] pub type W = crate :: W < ModemCtlSpec > ;
#[doc = "Field `afc_en` reader - Auto flow control enable"] pub type AfcEnR = crate :: BitReader ;
#[doc = "Field `afc_en` writer - Auto flow control enable"] pub type AfcEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `lb_mode` reader - Loopback mode: 0=disabled; 1=enabled"] pub type LbModeR = crate :: BitReader ;
#[doc = "Field `lb_mode` writer - Loopback mode: 0=disabled; 1=enabled"] pub type LbModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rts` reader - RTS software control"] pub type RtsR = crate :: BitReader ;
#[doc = "Field `rts` writer - RTS software control"] pub type RtsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Auto flow control enable"]
#[inline (always)] pub fn afc_en (& self) -> AfcEnR { AfcEnR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Loopback mode: 0=disabled; 1=enabled"]
#[inline (always)] pub fn lb_mode (& self) -> LbModeR { LbModeR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - RTS software control"]
#[inline (always)] pub fn rts (& self) -> RtsR { RtsR :: new (((self . bits >> 2) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Auto flow control enable"]
#[inline (always)] pub fn afc_en (& mut self) -> AfcEnW < '_ , ModemCtlSpec > { AfcEnW :: new (self , 0) }
#[doc = "Bit 1 - Loopback mode: 0=disabled; 1=enabled"]
#[inline (always)] pub fn lb_mode (& mut self) -> LbModeW < '_ , ModemCtlSpec > { LbModeW :: new (self , 1) }
#[doc = "Bit 2 - RTS software control"]
#[inline (always)] pub fn rts (& mut self) -> RtsW < '_ , ModemCtlSpec > { RtsW :: new (self , 2) } }
#[doc = "Modem control register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ModemCtlSpec ; impl crate :: RegisterSpec for ModemCtlSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`modem_ctl::R`](R) reader structure"] impl crate :: Readable for ModemCtlSpec { }
#[doc = "`write(|w| ..)` method takes [`modem_ctl::W`](W) writer structure"] impl crate :: Writable for ModemCtlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets MODEM_CTL to value 0"] impl crate :: Resettable for ModemCtlSpec { } }
#[doc = "MODEM_STATUS (rw) register accessor: Modem status register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modem_status`] module"]
#[doc (alias = "MODEM_STATUS")] pub type ModemStatus = crate :: Reg < modem_status :: ModemStatusSpec > ;
#[doc = "Modem status register"] pub mod modem_status {
#[doc = "Register `MODEM_STATUS` reader"] pub type R = crate :: R < ModemStatusSpec > ;
#[doc = "Register `MODEM_STATUS` writer"] pub type W = crate :: W < ModemStatusSpec > ;
#[doc = "Field `dcts` reader - CTS change indicator"] pub type DctsR = crate :: BitReader ;
#[doc = "Field `cts` reader - CTS signal state"] pub type CtsR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - CTS change indicator"]
#[inline (always)] pub fn dcts (& self) -> DctsR { DctsR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - CTS signal state"]
#[inline (always)] pub fn cts (& self) -> CtsR { CtsR :: new (((self . bits >> 1) & 1) != 0) } } impl W { }
#[doc = "Modem status register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ModemStatusSpec ; impl crate :: RegisterSpec for ModemStatusSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`modem_status::R`](R) reader structure"] impl crate :: Readable for ModemStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`modem_status::W`](W) writer structure"] impl crate :: Writable for ModemStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets MODEM_STATUS to value 0"] impl crate :: Resettable for ModemStatusSpec { } }
#[doc = "LINE_STATUS (rw) register accessor: Line status register\n\nYou can [`read`](crate::Reg::read) this register and get [`line_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`line_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@line_status`] module"]
#[doc (alias = "LINE_STATUS")] pub type LineStatus = crate :: Reg < line_status :: LineStatusSpec > ;
#[doc = "Line status register"] pub mod line_status {
#[doc = "Register `LINE_STATUS` reader"] pub type R = crate :: R < LineStatusSpec > ;
#[doc = "Register `LINE_STATUS` writer"] pub type W = crate :: W < LineStatusSpec > ;
#[doc = "Field `rx_fifo_err` reader - RX FIFO error status"] pub type RxFifoErrR = crate :: BitReader ;
#[doc = "Field `frame_err` reader - Framing error"] pub type FrameErrR = crate :: BitReader ;
#[doc = "Field `parity_err` reader - Parity error"] pub type ParityErrR = crate :: BitReader ;
#[doc = "Field `overrun_err` reader - Overrun error"] pub type OverrunErrR = crate :: BitReader ;
#[doc = "Field `break_intr` reader - Break interrupt"] pub type BreakIntrR = crate :: BitReader ;
#[doc = "Field `data_available` reader - Data available in RX FIFO/RBR"] pub type DataAvailableR = crate :: BitReader ;
#[doc = "Field `thre_s` reader - THR empty flag"] pub type ThreSR = crate :: BitReader ;
#[doc = "Field `tx_empty_s` reader - Transmitter empty flag"] pub type TxEmptySR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - RX FIFO error status"]
#[inline (always)] pub fn rx_fifo_err (& self) -> RxFifoErrR { RxFifoErrR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Framing error"]
#[inline (always)] pub fn frame_err (& self) -> FrameErrR { FrameErrR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Parity error"]
#[inline (always)] pub fn parity_err (& self) -> ParityErrR { ParityErrR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - Overrun error"]
#[inline (always)] pub fn overrun_err (& self) -> OverrunErrR { OverrunErrR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Break interrupt"]
#[inline (always)] pub fn break_intr (& self) -> BreakIntrR { BreakIntrR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Data available in RX FIFO/RBR"]
#[inline (always)] pub fn data_available (& self) -> DataAvailableR { DataAvailableR :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - THR empty flag"]
#[inline (always)] pub fn thre_s (& self) -> ThreSR { ThreSR :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 7 - Transmitter empty flag"]
#[inline (always)] pub fn tx_empty_s (& self) -> TxEmptySR { TxEmptySR :: new (((self . bits >> 7) & 1) != 0) } } impl W { }
#[doc = "Line status register\n\nYou can [`read`](crate::Reg::read) this register and get [`line_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`line_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LineStatusSpec ; impl crate :: RegisterSpec for LineStatusSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`line_status::R`](R) reader structure"] impl crate :: Readable for LineStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`line_status::W`](W) writer structure"] impl crate :: Writable for LineStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LINE_STATUS to value 0xc0"] impl crate :: Resettable for LineStatusSpec { const RESET_VALUE : u16 = 0xc0 ; } }
#[doc = "UART_GP_REG (rw) register accessor: UART general purpose register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_gp_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_gp_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_gp_reg`] module"]
#[doc (alias = "UART_GP_REG")] pub type UartGpReg = crate :: Reg < uart_gp_reg :: UartGpRegSpec > ;
#[doc = "UART general purpose register"] pub mod uart_gp_reg {
#[doc = "Register `UART_GP_REG` reader"] pub type R = crate :: R < UartGpRegSpec > ;
#[doc = "Register `UART_GP_REG` writer"] pub type W = crate :: W < UartGpRegSpec > ;
#[doc = "Field `uart_gp_reg` reader - General purpose storage"] pub type UartGpRegR = crate :: FieldReader ;
#[doc = "Field `uart_gp_reg` writer - General purpose storage"] pub type UartGpRegW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - General purpose storage"]
#[inline (always)] pub fn uart_gp_reg (& self) -> UartGpRegR { UartGpRegR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - General purpose storage"]
#[inline (always)] pub fn uart_gp_reg (& mut self) -> UartGpRegW < '_ , UartGpRegSpec > { UartGpRegW :: new (self , 0) } }
#[doc = "UART general purpose register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_gp_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_gp_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UartGpRegSpec ; impl crate :: RegisterSpec for UartGpRegSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`uart_gp_reg::R`](R) reader structure"] impl crate :: Readable for UartGpRegSpec { }
#[doc = "`write(|w| ..)` method takes [`uart_gp_reg::W`](W) writer structure"] impl crate :: Writable for UartGpRegSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets UART_GP_REG to value 0"] impl crate :: Resettable for UartGpRegSpec { } }
#[doc = "TX_FIFO_READ (rw) register accessor: TX FIFO read register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_read::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_read::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_fifo_read`] module"]
#[doc (alias = "TX_FIFO_READ")] pub type TxFifoRead = crate :: Reg < tx_fifo_read :: TxFifoReadSpec > ;
#[doc = "TX FIFO read register"] pub mod tx_fifo_read {
#[doc = "Register `TX_FIFO_READ` reader"] pub type R = crate :: R < TxFifoReadSpec > ;
#[doc = "Register `TX_FIFO_READ` writer"] pub type W = crate :: W < TxFifoReadSpec > ;
#[doc = "Field `tx_fifo_read` reader - TX FIFO top data"] pub type TxFifoReadR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - TX FIFO top data"]
#[inline (always)] pub fn tx_fifo_read (& self) -> TxFifoReadR { TxFifoReadR :: new ((self . bits & 0xff) as u8) } } impl W { }
#[doc = "TX FIFO read register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_read::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_read::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TxFifoReadSpec ; impl crate :: RegisterSpec for TxFifoReadSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`tx_fifo_read::R`](R) reader structure"] impl crate :: Readable for TxFifoReadSpec { }
#[doc = "`write(|w| ..)` method takes [`tx_fifo_read::W`](W) writer structure"] impl crate :: Writable for TxFifoReadSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TX_FIFO_READ to value 0"] impl crate :: Resettable for TxFifoReadSpec { } }
#[doc = "RX_FIFO_WRITE (rw) register accessor: RX FIFO write register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_write::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_write::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_fifo_write`] module"]
#[doc (alias = "RX_FIFO_WRITE")] pub type RxFifoWrite = crate :: Reg < rx_fifo_write :: RxFifoWriteSpec > ;
#[doc = "RX FIFO write register"] pub mod rx_fifo_write {
#[doc = "Register `RX_FIFO_WRITE` reader"] pub type R = crate :: R < RxFifoWriteSpec > ;
#[doc = "Register `RX_FIFO_WRITE` writer"] pub type W = crate :: W < RxFifoWriteSpec > ;
#[doc = "Field `rx_fifo_write` reader - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"] pub type RxFifoWriteR = crate :: FieldReader ;
#[doc = "Field `rx_fifo_write` writer - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"] pub type RxFifoWriteW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ;
#[doc = "Field `rx_fifo_pe` writer - RX FIFO parity error"] pub type RxFifoPeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rx_fifo_fe` writer - RX FIFO framing error"] pub type RxFifoFeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:7 - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
#[inline (always)] pub fn rx_fifo_write (& self) -> RxFifoWriteR { RxFifoWriteR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
#[inline (always)] pub fn rx_fifo_write (& mut self) -> RxFifoWriteW < '_ , RxFifoWriteSpec > { RxFifoWriteW :: new (self , 0) }
#[doc = "Bit 8 - RX FIFO parity error"]
#[inline (always)] pub fn rx_fifo_pe (& mut self) -> RxFifoPeW < '_ , RxFifoWriteSpec > { RxFifoPeW :: new (self , 8) }
#[doc = "Bit 9 - RX FIFO framing error"]
#[inline (always)] pub fn rx_fifo_fe (& mut self) -> RxFifoFeW < '_ , RxFifoWriteSpec > { RxFifoFeW :: new (self , 9) } }
#[doc = "RX FIFO write register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_write::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_write::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RxFifoWriteSpec ; impl crate :: RegisterSpec for RxFifoWriteSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`rx_fifo_write::R`](R) reader structure"] impl crate :: Readable for RxFifoWriteSpec { }
#[doc = "`write(|w| ..)` method takes [`rx_fifo_write::W`](W) writer structure"] impl crate :: Writable for RxFifoWriteSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RX_FIFO_WRITE to value 0"] impl crate :: Resettable for RxFifoWriteSpec { } }
#[doc = "FIFO_STATUS (rw) register accessor: FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_status`] module"]
#[doc (alias = "FIFO_STATUS")] pub type FifoStatus = crate :: Reg < fifo_status :: FifoStatusSpec > ;
#[doc = "FIFO status register"] pub mod fifo_status {
#[doc = "Register `FIFO_STATUS` reader"] pub type R = crate :: R < FifoStatusSpec > ;
#[doc = "Register `FIFO_STATUS` writer"] pub type W = crate :: W < FifoStatusSpec > ;
#[doc = "Field `tx_fifo_full` reader - TX FIFO full flag"] pub type TxFifoFullR = crate :: BitReader ;
#[doc = "Field `tx_fifo_empty` reader - TX FIFO empty flag"] pub type TxFifoEmptyR = crate :: BitReader ;
#[doc = "Field `rx_fifo_full` reader - RX FIFO full flag"] pub type RxFifoFullR = crate :: BitReader ;
#[doc = "Field `rx_fifo_empty` reader - RX FIFO empty flag"] pub type RxFifoEmptyR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - TX FIFO full flag"]
#[inline (always)] pub fn tx_fifo_full (& self) -> TxFifoFullR { TxFifoFullR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TX FIFO empty flag"]
#[inline (always)] pub fn tx_fifo_empty (& self) -> TxFifoEmptyR { TxFifoEmptyR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - RX FIFO full flag"]
#[inline (always)] pub fn rx_fifo_full (& self) -> RxFifoFullR { RxFifoFullR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - RX FIFO empty flag"]
#[inline (always)] pub fn rx_fifo_empty (& self) -> RxFifoEmptyR { RxFifoEmptyR :: new (((self . bits >> 3) & 1) != 0) } } impl W { }
#[doc = "FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FifoStatusSpec ; impl crate :: RegisterSpec for FifoStatusSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`fifo_status::R`](R) reader structure"] impl crate :: Readable for FifoStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`fifo_status::W`](W) writer structure"] impl crate :: Writable for FifoStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets FIFO_STATUS to value 0x02"] impl crate :: Resettable for FifoStatusSpec { const RESET_VALUE : u16 = 0x02 ; } }
#[doc = "TX_FIFO_CNT (rw) register accessor: TX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_fifo_cnt`] module"]
#[doc (alias = "TX_FIFO_CNT")] pub type TxFifoCnt = crate :: Reg < tx_fifo_cnt :: TxFifoCntSpec > ;
#[doc = "TX FIFO data counter"] pub mod tx_fifo_cnt {
#[doc = "Register `TX_FIFO_CNT` reader"] pub type R = crate :: R < TxFifoCntSpec > ;
#[doc = "Register `TX_FIFO_CNT` writer"] pub type W = crate :: W < TxFifoCntSpec > ;
#[doc = "Field `tx_fifo_level` reader - TX FIFO data count"] pub type TxFifoLevelR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:6 - TX FIFO data count"]
#[inline (always)] pub fn tx_fifo_level (& self) -> TxFifoLevelR { TxFifoLevelR :: new ((self . bits & 0x7f) as u8) } } impl W { }
#[doc = "TX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TxFifoCntSpec ; impl crate :: RegisterSpec for TxFifoCntSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`tx_fifo_cnt::R`](R) reader structure"] impl crate :: Readable for TxFifoCntSpec { }
#[doc = "`write(|w| ..)` method takes [`tx_fifo_cnt::W`](W) writer structure"] impl crate :: Writable for TxFifoCntSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TX_FIFO_CNT to value 0"] impl crate :: Resettable for TxFifoCntSpec { } }
#[doc = "RX_FIFO_CNT (rw) register accessor: RX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_fifo_cnt`] module"]
#[doc (alias = "RX_FIFO_CNT")] pub type RxFifoCnt = crate :: Reg < rx_fifo_cnt :: RxFifoCntSpec > ;
#[doc = "RX FIFO data counter"] pub mod rx_fifo_cnt {
#[doc = "Register `RX_FIFO_CNT` reader"] pub type R = crate :: R < RxFifoCntSpec > ;
#[doc = "Register `RX_FIFO_CNT` writer"] pub type W = crate :: W < RxFifoCntSpec > ; impl W { }
#[doc = "RX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RxFifoCntSpec ; impl crate :: RegisterSpec for RxFifoCntSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`rx_fifo_cnt::R`](R) reader structure"] impl crate :: Readable for RxFifoCntSpec { }
#[doc = "`write(|w| ..)` method takes [`rx_fifo_cnt::W`](W) writer structure"] impl crate :: Writable for RxFifoCntSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RX_FIFO_CNT to value 0"] impl crate :: Resettable for RxFifoCntSpec { } }
#[doc = "HALT_TX (rw) register accessor: TX halt register\n\nYou can [`read`](crate::Reg::read) this register and get [`halt_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halt_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@halt_tx`] module"]
#[doc (alias = "HALT_TX")] pub type HaltTx = crate :: Reg < halt_tx :: HaltTxSpec > ;
#[doc = "TX halt register"] pub mod halt_tx {
#[doc = "Register `HALT_TX` reader"] pub type R = crate :: R < HaltTxSpec > ;
#[doc = "Register `HALT_TX` writer"] pub type W = crate :: W < HaltTxSpec > ;
#[doc = "Field `halt_tx` reader - TX halt: 0=disabled; 1=enabled"] pub type HaltTxR = crate :: BitReader ;
#[doc = "Field `halt_tx` writer - TX halt: 0=disabled; 1=enabled"] pub type HaltTxW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - TX halt: 0=disabled; 1=enabled"]
#[inline (always)] pub fn halt_tx (& self) -> HaltTxR { HaltTxR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - TX halt: 0=disabled; 1=enabled"]
#[inline (always)] pub fn halt_tx (& mut self) -> HaltTxW < '_ , HaltTxSpec > { HaltTxW :: new (self , 0) } }
#[doc = "TX halt register\n\nYou can [`read`](crate::Reg::read) this register and get [`halt_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halt_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HaltTxSpec ; impl crate :: RegisterSpec for HaltTxSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`halt_tx::R`](R) reader structure"] impl crate :: Readable for HaltTxSpec { }
#[doc = "`write(|w| ..)` method takes [`halt_tx::W`](W) writer structure"] impl crate :: Writable for HaltTxSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets HALT_TX to value 0"] impl crate :: Resettable for HaltTxSpec { } }
#[doc = "DMA_SW_ACK (rw) register accessor: DMA software acknowledge register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_sw_ack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_sw_ack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_sw_ack`] module"]
#[doc (alias = "DMA_SW_ACK")] pub type DmaSwAck = crate :: Reg < dma_sw_ack :: DmaSwAckSpec > ;
#[doc = "DMA software acknowledge register"] pub mod dma_sw_ack {
#[doc = "Register `DMA_SW_ACK` reader"] pub type R = crate :: R < DmaSwAckSpec > ;
#[doc = "Register `DMA_SW_ACK` writer"] pub type W = crate :: W < DmaSwAckSpec > ;
#[doc = "Field `dma_sw_ack` writer - DMA software acknowledge (write-clear)"] pub type DmaSwAckW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - DMA software acknowledge (write-clear)"]
#[inline (always)] pub fn dma_sw_ack (& mut self) -> DmaSwAckW < '_ , DmaSwAckSpec > { DmaSwAckW :: new (self , 0) } }
#[doc = "DMA software acknowledge register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_sw_ack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_sw_ack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmaSwAckSpec ; impl crate :: RegisterSpec for DmaSwAckSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`dma_sw_ack::R`](R) reader structure"] impl crate :: Readable for DmaSwAckSpec { }
#[doc = "`write(|w| ..)` method takes [`dma_sw_ack::W`](W) writer structure"] impl crate :: Writable for DmaSwAckSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMA_SW_ACK to value 0"] impl crate :: Resettable for DmaSwAckSpec { } }
#[doc = "BAUD_CTL (rw) register accessor: Baud rate control register\n\nYou can [`read`](crate::Reg::read) this register and get [`baud_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud_ctl`] module"]
#[doc (alias = "BAUD_CTL")] pub type BaudCtl = crate :: Reg < baud_ctl :: BaudCtlSpec > ;
#[doc = "Baud rate control register"] pub mod baud_ctl {
#[doc = "Register `BAUD_CTL` reader"] pub type R = crate :: R < BaudCtlSpec > ;
#[doc = "Register `BAUD_CTL` writer"] pub type W = crate :: W < BaudCtlSpec > ;
#[doc = "Baud rate oversampling: 0x7=8x; 0xF=16x\n\nValue on reset: 15"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum BaudDiv {
#[doc = "7: 8x oversampling"] Div8 = 7 ,
#[doc = "15: 16x oversampling"] Div16 = 15 , } impl From < BaudDiv > for u8 {
#[inline (always)] fn from (variant : BaudDiv) -> Self { variant as _ } } impl crate :: FieldSpec for BaudDiv { type Ux = u8 ; } impl crate :: IsEnum for BaudDiv { }
#[doc = "Field `baud_div` reader - Baud rate oversampling: 0x7=8x; 0xF=16x"] pub type BaudDivR = crate :: FieldReader < BaudDiv > ; impl BaudDivR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < BaudDiv > { match self . bits { 7 => Some (BaudDiv :: Div8) , 15 => Some (BaudDiv :: Div16) , _ => None , } }
#[doc = "8x oversampling"]
#[inline (always)] pub fn is_div8 (& self) -> bool { * self == BaudDiv :: Div8 }
#[doc = "16x oversampling"]
#[inline (always)] pub fn is_div16 (& self) -> bool { * self == BaudDiv :: Div16 } }
#[doc = "Field `baud_div` writer - Baud rate oversampling: 0x7=8x; 0xF=16x"] pub type BaudDivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , BaudDiv > ; impl < 'a , REG > BaudDivW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "8x oversampling"]
#[inline (always)] pub fn div8 (self) -> & 'a mut crate :: W < REG > { self . variant (BaudDiv :: Div8) }
#[doc = "16x oversampling"]
#[inline (always)] pub fn div16 (self) -> & 'a mut crate :: W < REG > { self . variant (BaudDiv :: Div16) } }
#[doc = "Field `sample_phase` reader - RX sample phase"] pub type SamplePhaseR = crate :: FieldReader ;
#[doc = "Field `sample_phase` writer - RX sample phase"] pub type SamplePhaseW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R {
#[doc = "Bits 0:3 - Baud rate oversampling: 0x7=8x; 0xF=16x"]
#[inline (always)] pub fn baud_div (& self) -> BaudDivR { BaudDivR :: new ((self . bits & 0x0f) as u8) }
#[doc = "Bits 4:7 - RX sample phase"]
#[inline (always)] pub fn sample_phase (& self) -> SamplePhaseR { SamplePhaseR :: new (((self . bits >> 4) & 0x0f) as u8) } } impl W {
#[doc = "Bits 0:3 - Baud rate oversampling: 0x7=8x; 0xF=16x"]
#[inline (always)] pub fn baud_div (& mut self) -> BaudDivW < '_ , BaudCtlSpec > { BaudDivW :: new (self , 0) }
#[doc = "Bits 4:7 - RX sample phase"]
#[inline (always)] pub fn sample_phase (& mut self) -> SamplePhaseW < '_ , BaudCtlSpec > { SamplePhaseW :: new (self , 4) } }
#[doc = "Baud rate control register\n\nYou can [`read`](crate::Reg::read) this register and get [`baud_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BaudCtlSpec ; impl crate :: RegisterSpec for BaudCtlSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`baud_ctl::R`](R) reader structure"] impl crate :: Readable for BaudCtlSpec { }
#[doc = "`write(|w| ..)` method takes [`baud_ctl::W`](W) writer structure"] impl crate :: Writable for BaudCtlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets BAUD_CTL to value 0x7f"] impl crate :: Resettable for BaudCtlSpec { const RESET_VALUE : u16 = 0x7f ; } }
#[doc = "STP_CTL (rw) register accessor: Stop bit control register\n\nYou can [`read`](crate::Reg::read) this register and get [`stp_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stp_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stp_ctl`] module"]
#[doc (alias = "STP_CTL")] pub type StpCtl = crate :: Reg < stp_ctl :: StpCtlSpec > ;
#[doc = "Stop bit control register"] pub mod stp_ctl {
#[doc = "Register `STP_CTL` reader"] pub type R = crate :: R < StpCtlSpec > ;
#[doc = "Register `STP_CTL` writer"] pub type W = crate :: W < StpCtlSpec > ;
#[doc = "Field `rx_sp` reader - RX stop bits when stp_mode=1"] pub type RxSpR = crate :: BitReader ;
#[doc = "Field `rx_sp` writer - RX stop bits when stp_mode=1"] pub type RxSpW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tx_sp` reader - TX stop bits when stp_mode=1"] pub type TxSpR = crate :: BitReader ;
#[doc = "Field `tx_sp` writer - TX stop bits when stp_mode=1"] pub type TxSpW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `stp_mode` reader - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"] pub type StpModeR = crate :: BitReader ;
#[doc = "Field `stp_mode` writer - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"] pub type StpModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - RX stop bits when stp_mode=1"]
#[inline (always)] pub fn rx_sp (& self) -> RxSpR { RxSpR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TX stop bits when stp_mode=1"]
#[inline (always)] pub fn tx_sp (& self) -> TxSpR { TxSpR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
#[inline (always)] pub fn stp_mode (& self) -> StpModeR { StpModeR :: new (((self . bits >> 2) & 1) != 0) } } impl W {
#[doc = "Bit 0 - RX stop bits when stp_mode=1"]
#[inline (always)] pub fn rx_sp (& mut self) -> RxSpW < '_ , StpCtlSpec > { RxSpW :: new (self , 0) }
#[doc = "Bit 1 - TX stop bits when stp_mode=1"]
#[inline (always)] pub fn tx_sp (& mut self) -> TxSpW < '_ , StpCtlSpec > { TxSpW :: new (self , 1) }
#[doc = "Bit 2 - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
#[inline (always)] pub fn stp_mode (& mut self) -> StpModeW < '_ , StpCtlSpec > { StpModeW :: new (self , 2) } }
#[doc = "Stop bit control register\n\nYou can [`read`](crate::Reg::read) this register and get [`stp_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stp_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct StpCtlSpec ; impl crate :: RegisterSpec for StpCtlSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`stp_ctl::R`](R) reader structure"] impl crate :: Readable for StpCtlSpec { }
#[doc = "`write(|w| ..)` method takes [`stp_ctl::W`](W) writer structure"] impl crate :: Writable for StpCtlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets STP_CTL to value 0"] impl crate :: Resettable for StpCtlSpec { } }
#[doc = "UART_PARAMETER (rw) register accessor: UART parameter register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_parameter::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_parameter::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_parameter`] module"]
#[doc (alias = "UART_PARAMETER")] pub type UartParameter = crate :: Reg < uart_parameter :: UartParameterSpec > ;
#[doc = "UART parameter register"] pub mod uart_parameter {
#[doc = "Register `UART_PARAMETER` reader"] pub type R = crate :: R < UartParameterSpec > ;
#[doc = "Register `UART_PARAMETER` writer"] pub type W = crate :: W < UartParameterSpec > ;
#[doc = "Field `fifo_depth` reader - FIFO depth: 0x4=64"] pub type FifoDepthR = crate :: FieldReader ;
#[doc = "Field `apb_data_width` reader - APB data width: 0x1=16bit"] pub type ApbDataWidthR = crate :: FieldReader ;
#[doc = "Field `afce_mode` reader - AFCE mode: 0=disabled; 1=enabled"] pub type AfceModeR = crate :: BitReader ;
#[doc = "Field `dma_mode` reader - DMA mode: 0=DMA_EXTRA disabled; 1=enabled"] pub type DmaModeR = crate :: BitReader ;
#[doc = "Field `shadow` reader - Shadow feature enable"] pub type ShadowR = crate :: BitReader ; impl R {
#[doc = "Bits 0:7 - FIFO depth: 0x4=64"]
#[inline (always)] pub fn fifo_depth (& self) -> FifoDepthR { FifoDepthR :: new ((self . bits & 0xff) as u8) }
#[doc = "Bits 8:9 - APB data width: 0x1=16bit"]
#[inline (always)] pub fn apb_data_width (& self) -> ApbDataWidthR { ApbDataWidthR :: new (((self . bits >> 8) & 3) as u8) }
#[doc = "Bit 10 - AFCE mode: 0=disabled; 1=enabled"]
#[inline (always)] pub fn afce_mode (& self) -> AfceModeR { AfceModeR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - DMA mode: 0=DMA_EXTRA disabled; 1=enabled"]
#[inline (always)] pub fn dma_mode (& self) -> DmaModeR { DmaModeR :: new (((self . bits >> 11) & 1) != 0) }
#[doc = "Bit 12 - Shadow feature enable"]
#[inline (always)] pub fn shadow (& self) -> ShadowR { ShadowR :: new (((self . bits >> 12) & 1) != 0) } } impl W { }
#[doc = "UART parameter register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_parameter::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_parameter::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UartParameterSpec ; impl crate :: RegisterSpec for UartParameterSpec { type Ux = u16 ; }
#[doc = "`read()` method returns [`uart_parameter::R`](R) reader structure"] impl crate :: Readable for UartParameterSpec { }
#[doc = "`write(|w| ..)` method takes [`uart_parameter::W`](W) writer structure"] impl crate :: Writable for UartParameterSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets UART_PARAMETER to value 0x0d04"] impl crate :: Resettable for UartParameterSpec { const RESET_VALUE : u16 = 0x0d04 ; } } }
#[doc = "UART1 with flow control support"] pub type Uart1 = crate :: Periph < uart0 :: RegisterBlock , 0x4401_1000 > ; impl core :: fmt :: Debug for Uart1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Uart1") . finish () } }
#[doc = "UART1 with flow control support"] pub use self :: uart0 as uart1 ;
#[doc = "UART2 with flow control support"] pub type Uart2 = crate :: Periph < uart0 :: RegisterBlock , 0x4401_2000 > ; impl core :: fmt :: Debug for Uart2 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Uart2") . finish () } }
#[doc = "UART2 with flow control support"] pub use self :: uart0 as uart2 ;
#[doc = "I2C0 master controller"] pub type I2c0 = crate :: Periph < i2c0 :: RegisterBlock , 0x4401_8000 > ; impl core :: fmt :: Debug for I2c0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("I2c0") . finish () } }
#[doc = "I2C0 master controller"] pub mod i2c0 {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { i2c_ctrl : I2cCtrl , i2c_com : I2cCom , i2c_icr : I2cIcr , i2c_sr : I2cSr , i2c_scl_h : I2cSclH , i2c_scl_l : I2cSclL , i2c_txr : I2cTxr , i2c_rxr : I2cRxr , i2c_fifostatus : I2cFifostatus , i2c_txcount : I2cTxcount , i2c_rxcount : I2cRxcount , i2c_rxtide : I2cRxtide , i2c_txtide : I2cTxtide , i2c_ftrper : I2cFtrper , } impl RegisterBlock {
#[doc = "0x00 - I2C control register"]
#[inline (always)] pub const fn i2c_ctrl (& self) -> & I2cCtrl { & self . i2c_ctrl }
#[doc = "0x04 - I2C command register"]
#[inline (always)] pub const fn i2c_com (& self) -> & I2cCom { & self . i2c_com }
#[doc = "0x08 - I2C interrupt clear register"]
#[inline (always)] pub const fn i2c_icr (& self) -> & I2cIcr { & self . i2c_icr }
#[doc = "0x0c - I2C status register"]
#[inline (always)] pub const fn i2c_sr (& self) -> & I2cSr { & self . i2c_sr }
#[doc = "0x10 - SCL high period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]"]
#[inline (always)] pub const fn i2c_scl_h (& self) -> & I2cSclH { & self . i2c_scl_h }
#[doc = "0x14 - SCL low period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]"]
#[inline (always)] pub const fn i2c_scl_l (& self) -> & I2cSclL { & self . i2c_scl_l }
#[doc = "0x18 - I2C TX data register"]
#[inline (always)] pub const fn i2c_txr (& self) -> & I2cTxr { & self . i2c_txr }
#[doc = "0x1c - I2C RX data register"]
#[inline (always)] pub const fn i2c_rxr (& self) -> & I2cRxr { & self . i2c_rxr }
#[doc = "0x20 - FIFO status register"]
#[inline (always)] pub const fn i2c_fifostatus (& self) -> & I2cFifostatus { & self . i2c_fifostatus }
#[doc = "0x24 - TX FIFO count register"]
#[inline (always)] pub const fn i2c_txcount (& self) -> & I2cTxcount { & self . i2c_txcount }
#[doc = "0x28 - RX FIFO count register"]
#[inline (always)] pub const fn i2c_rxcount (& self) -> & I2cRxcount { & self . i2c_rxcount }
#[doc = "0x2c - RX FIFO threshold register"]
#[inline (always)] pub const fn i2c_rxtide (& self) -> & I2cRxtide { & self . i2c_rxtide }
#[doc = "0x30 - TX FIFO threshold register"]
#[inline (always)] pub const fn i2c_txtide (& self) -> & I2cTxtide { & self . i2c_txtide }
#[doc = "0x34 - Glitch filter configuration register"]
#[inline (always)] pub const fn i2c_ftrper (& self) -> & I2cFtrper { & self . i2c_ftrper } }
#[doc = "I2C_CTRL (rw) register accessor: I2C control register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_ctrl`] module"]
#[doc (alias = "I2C_CTRL")] pub type I2cCtrl = crate :: Reg < i2c_ctrl :: I2cCtrlSpec > ;
#[doc = "I2C control register"] pub mod i2c_ctrl {
#[doc = "Register `I2C_CTRL` reader"] pub type R = crate :: R < I2cCtrlSpec > ;
#[doc = "Register `I2C_CTRL` writer"] pub type W = crate :: W < I2cCtrlSpec > ;
#[doc = "Field `int_done_mask` reader - Transfer complete interrupt mask: 0=masked; 1=unmasked"] pub type IntDoneMaskR = crate :: BitReader ;
#[doc = "Field `int_done_mask` writer - Transfer complete interrupt mask: 0=masked; 1=unmasked"] pub type IntDoneMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `int_arb_loss_mask` reader - Arbitration loss interrupt mask"] pub type IntArbLossMaskR = crate :: BitReader ;
#[doc = "Field `int_arb_loss_mask` writer - Arbitration loss interrupt mask"] pub type IntArbLossMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `int_ack_err_mask` reader - ACK error interrupt mask"] pub type IntAckErrMaskR = crate :: BitReader ;
#[doc = "Field `int_ack_err_mask` writer - ACK error interrupt mask"] pub type IntAckErrMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `int_rx_mask` reader - RX interrupt mask"] pub type IntRxMaskR = crate :: BitReader ;
#[doc = "Field `int_rx_mask` writer - RX interrupt mask"] pub type IntRxMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `int_tx_mask` reader - TX interrupt mask"] pub type IntTxMaskR = crate :: BitReader ;
#[doc = "Field `int_tx_mask` writer - TX interrupt mask"] pub type IntTxMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `int_stop_mask` reader - Stop condition interrupt mask"] pub type IntStopMaskR = crate :: BitReader ;
#[doc = "Field `int_stop_mask` writer - Stop condition interrupt mask"] pub type IntStopMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `int_start_mask` reader - Start condition interrupt mask"] pub type IntStartMaskR = crate :: BitReader ;
#[doc = "Field `int_start_mask` writer - Start condition interrupt mask"] pub type IntStartMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `int_mask` reader - I2C interrupt master mask"] pub type IntMaskR = crate :: BitReader ;
#[doc = "Field `int_mask` writer - I2C interrupt master mask"] pub type IntMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `i2c_en` reader - I2C enable: 0=disabled; 1=enabled"] pub type I2cEnR = crate :: BitReader ;
#[doc = "Field `i2c_en` writer - I2C enable: 0=disabled; 1=enabled"] pub type I2cEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `int_rxtide_mask` reader - RX FIFO overflow interrupt mask"] pub type IntRxtideMaskR = crate :: BitReader ;
#[doc = "Field `int_rxtide_mask` writer - RX FIFO overflow interrupt mask"] pub type IntRxtideMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `int_txtide_mask` reader - TX FIFO overflow interrupt mask"] pub type IntTxtideMaskR = crate :: BitReader ;
#[doc = "Field `int_txtide_mask` writer - TX FIFO overflow interrupt mask"] pub type IntTxtideMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "I2C mode: 0=no FIFO; 1=FIFO mode\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum ModeCtrl {
#[doc = "0: No FIFO transfer mode"] NoFifo = 0 ,
#[doc = "1: FIFO transfer mode"] Fifo = 1 , } impl From < ModeCtrl > for bool {
#[inline (always)] fn from (variant : ModeCtrl) -> Self { variant as u8 != 0 } }
#[doc = "Field `mode_ctrl` reader - I2C mode: 0=no FIFO; 1=FIFO mode"] pub type ModeCtrlR = crate :: BitReader < ModeCtrl > ; impl ModeCtrlR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> ModeCtrl { match self . bits { false => ModeCtrl :: NoFifo , true => ModeCtrl :: Fifo , } }
#[doc = "No FIFO transfer mode"]
#[inline (always)] pub fn is_no_fifo (& self) -> bool { * self == ModeCtrl :: NoFifo }
#[doc = "FIFO transfer mode"]
#[inline (always)] pub fn is_fifo (& self) -> bool { * self == ModeCtrl :: Fifo } }
#[doc = "Field `mode_ctrl` writer - I2C mode: 0=no FIFO; 1=FIFO mode"] pub type ModeCtrlW < 'a , REG > = crate :: BitWriter < 'a , REG , ModeCtrl > ; impl < 'a , REG > ModeCtrlW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "No FIFO transfer mode"]
#[inline (always)] pub fn no_fifo (self) -> & 'a mut crate :: W < REG > { self . variant (ModeCtrl :: NoFifo) }
#[doc = "FIFO transfer mode"]
#[inline (always)] pub fn fifo (self) -> & 'a mut crate :: W < REG > { self . variant (ModeCtrl :: Fifo) } }
#[doc = "Field `int_txfifo_over_mask` reader - TX FIFO complete interrupt mask"] pub type IntTxfifoOverMaskR = crate :: BitReader ;
#[doc = "Field `int_txfifo_over_mask` writer - TX FIFO complete interrupt mask"] pub type IntTxfifoOverMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
#[inline (always)] pub fn int_done_mask (& self) -> IntDoneMaskR { IntDoneMaskR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Arbitration loss interrupt mask"]
#[inline (always)] pub fn int_arb_loss_mask (& self) -> IntArbLossMaskR { IntArbLossMaskR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - ACK error interrupt mask"]
#[inline (always)] pub fn int_ack_err_mask (& self) -> IntAckErrMaskR { IntAckErrMaskR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - RX interrupt mask"]
#[inline (always)] pub fn int_rx_mask (& self) -> IntRxMaskR { IntRxMaskR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - TX interrupt mask"]
#[inline (always)] pub fn int_tx_mask (& self) -> IntTxMaskR { IntTxMaskR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Stop condition interrupt mask"]
#[inline (always)] pub fn int_stop_mask (& self) -> IntStopMaskR { IntStopMaskR :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Start condition interrupt mask"]
#[inline (always)] pub fn int_start_mask (& self) -> IntStartMaskR { IntStartMaskR :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 7 - I2C interrupt master mask"]
#[inline (always)] pub fn int_mask (& self) -> IntMaskR { IntMaskR :: new (((self . bits >> 7) & 1) != 0) }
#[doc = "Bit 8 - I2C enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn i2c_en (& self) -> I2cEnR { I2cEnR :: new (((self . bits >> 8) & 1) != 0) }
#[doc = "Bit 9 - RX FIFO overflow interrupt mask"]
#[inline (always)] pub fn int_rxtide_mask (& self) -> IntRxtideMaskR { IntRxtideMaskR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - TX FIFO overflow interrupt mask"]
#[inline (always)] pub fn int_txtide_mask (& self) -> IntTxtideMaskR { IntTxtideMaskR :: new (((self . bits >> 10) & 1) != 0) }
#[doc = "Bit 11 - I2C mode: 0=no FIFO; 1=FIFO mode"]
#[inline (always)] pub fn mode_ctrl (& self) -> ModeCtrlR { ModeCtrlR :: new (((self . bits >> 11) & 1) != 0) }
#[doc = "Bit 12 - TX FIFO complete interrupt mask"]
#[inline (always)] pub fn int_txfifo_over_mask (& self) -> IntTxfifoOverMaskR { IntTxfifoOverMaskR :: new (((self . bits >> 12) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
#[inline (always)] pub fn int_done_mask (& mut self) -> IntDoneMaskW < '_ , I2cCtrlSpec > { IntDoneMaskW :: new (self , 0) }
#[doc = "Bit 1 - Arbitration loss interrupt mask"]
#[inline (always)] pub fn int_arb_loss_mask (& mut self) -> IntArbLossMaskW < '_ , I2cCtrlSpec > { IntArbLossMaskW :: new (self , 1) }
#[doc = "Bit 2 - ACK error interrupt mask"]
#[inline (always)] pub fn int_ack_err_mask (& mut self) -> IntAckErrMaskW < '_ , I2cCtrlSpec > { IntAckErrMaskW :: new (self , 2) }
#[doc = "Bit 3 - RX interrupt mask"]
#[inline (always)] pub fn int_rx_mask (& mut self) -> IntRxMaskW < '_ , I2cCtrlSpec > { IntRxMaskW :: new (self , 3) }
#[doc = "Bit 4 - TX interrupt mask"]
#[inline (always)] pub fn int_tx_mask (& mut self) -> IntTxMaskW < '_ , I2cCtrlSpec > { IntTxMaskW :: new (self , 4) }
#[doc = "Bit 5 - Stop condition interrupt mask"]
#[inline (always)] pub fn int_stop_mask (& mut self) -> IntStopMaskW < '_ , I2cCtrlSpec > { IntStopMaskW :: new (self , 5) }
#[doc = "Bit 6 - Start condition interrupt mask"]
#[inline (always)] pub fn int_start_mask (& mut self) -> IntStartMaskW < '_ , I2cCtrlSpec > { IntStartMaskW :: new (self , 6) }
#[doc = "Bit 7 - I2C interrupt master mask"]
#[inline (always)] pub fn int_mask (& mut self) -> IntMaskW < '_ , I2cCtrlSpec > { IntMaskW :: new (self , 7) }
#[doc = "Bit 8 - I2C enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn i2c_en (& mut self) -> I2cEnW < '_ , I2cCtrlSpec > { I2cEnW :: new (self , 8) }
#[doc = "Bit 9 - RX FIFO overflow interrupt mask"]
#[inline (always)] pub fn int_rxtide_mask (& mut self) -> IntRxtideMaskW < '_ , I2cCtrlSpec > { IntRxtideMaskW :: new (self , 9) }
#[doc = "Bit 10 - TX FIFO overflow interrupt mask"]
#[inline (always)] pub fn int_txtide_mask (& mut self) -> IntTxtideMaskW < '_ , I2cCtrlSpec > { IntTxtideMaskW :: new (self , 10) }
#[doc = "Bit 11 - I2C mode: 0=no FIFO; 1=FIFO mode"]
#[inline (always)] pub fn mode_ctrl (& mut self) -> ModeCtrlW < '_ , I2cCtrlSpec > { ModeCtrlW :: new (self , 11) }
#[doc = "Bit 12 - TX FIFO complete interrupt mask"]
#[inline (always)] pub fn int_txfifo_over_mask (& mut self) -> IntTxfifoOverMaskW < '_ , I2cCtrlSpec > { IntTxfifoOverMaskW :: new (self , 12) } }
#[doc = "I2C control register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cCtrlSpec ; impl crate :: RegisterSpec for I2cCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_ctrl::R`](R) reader structure"] impl crate :: Readable for I2cCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_ctrl::W`](W) writer structure"] impl crate :: Writable for I2cCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_CTRL to value 0"] impl crate :: Resettable for I2cCtrlSpec { } }
#[doc = "I2C_COM (rw) register accessor: I2C command register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_com::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_com::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_com`] module"]
#[doc (alias = "I2C_COM")] pub type I2cCom = crate :: Reg < i2c_com :: I2cComSpec > ;
#[doc = "I2C command register"] pub mod i2c_com {
#[doc = "Register `I2C_COM` reader"] pub type R = crate :: R < I2cComSpec > ;
#[doc = "Register `I2C_COM` writer"] pub type W = crate :: W < I2cComSpec > ;
#[doc = "Field `op_stop` reader - Generate stop condition: 0=end; 1=active"] pub type OpStopR = crate :: BitReader ;
#[doc = "Field `op_stop` writer - Generate stop condition: 0=end; 1=active"] pub type OpStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `op_we` reader - Generate write operation"] pub type OpWeR = crate :: BitReader ;
#[doc = "Field `op_we` writer - Generate write operation"] pub type OpWeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `op_rd` reader - Generate read operation"] pub type OpRdR = crate :: BitReader ;
#[doc = "Field `op_rd` writer - Generate read operation"] pub type OpRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `op_start` reader - Generate start condition"] pub type OpStartR = crate :: BitReader ;
#[doc = "Field `op_start` writer - Generate start condition"] pub type OpStartW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `op_ack` reader - Master RX ACK: 0=send ACK; 1=no ACK"] pub type OpAckR = crate :: BitReader ;
#[doc = "Field `op_ack` writer - Master RX ACK: 0=send ACK; 1=no ACK"] pub type OpAckW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Generate stop condition: 0=end; 1=active"]
#[inline (always)] pub fn op_stop (& self) -> OpStopR { OpStopR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Generate write operation"]
#[inline (always)] pub fn op_we (& self) -> OpWeR { OpWeR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Generate read operation"]
#[inline (always)] pub fn op_rd (& self) -> OpRdR { OpRdR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - Generate start condition"]
#[inline (always)] pub fn op_start (& self) -> OpStartR { OpStartR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Master RX ACK: 0=send ACK; 1=no ACK"]
#[inline (always)] pub fn op_ack (& self) -> OpAckR { OpAckR :: new (((self . bits >> 4) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Generate stop condition: 0=end; 1=active"]
#[inline (always)] pub fn op_stop (& mut self) -> OpStopW < '_ , I2cComSpec > { OpStopW :: new (self , 0) }
#[doc = "Bit 1 - Generate write operation"]
#[inline (always)] pub fn op_we (& mut self) -> OpWeW < '_ , I2cComSpec > { OpWeW :: new (self , 1) }
#[doc = "Bit 2 - Generate read operation"]
#[inline (always)] pub fn op_rd (& mut self) -> OpRdW < '_ , I2cComSpec > { OpRdW :: new (self , 2) }
#[doc = "Bit 3 - Generate start condition"]
#[inline (always)] pub fn op_start (& mut self) -> OpStartW < '_ , I2cComSpec > { OpStartW :: new (self , 3) }
#[doc = "Bit 4 - Master RX ACK: 0=send ACK; 1=no ACK"]
#[inline (always)] pub fn op_ack (& mut self) -> OpAckW < '_ , I2cComSpec > { OpAckW :: new (self , 4) } }
#[doc = "I2C command register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_com::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_com::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cComSpec ; impl crate :: RegisterSpec for I2cComSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_com::R`](R) reader structure"] impl crate :: Readable for I2cComSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_com::W`](W) writer structure"] impl crate :: Writable for I2cComSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_COM to value 0"] impl crate :: Resettable for I2cComSpec { } }
#[doc = "I2C_ICR (rw) register accessor: I2C interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_icr`] module"]
#[doc (alias = "I2C_ICR")] pub type I2cIcr = crate :: Reg < i2c_icr :: I2cIcrSpec > ;
#[doc = "I2C interrupt clear register"] pub mod i2c_icr {
#[doc = "Register `I2C_ICR` reader"] pub type R = crate :: R < I2cIcrSpec > ;
#[doc = "Register `I2C_ICR` writer"] pub type W = crate :: W < I2cIcrSpec > ;
#[doc = "Field `clr_int_done` writer - Clear transfer complete interrupt"] pub type ClrIntDoneW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clr_int_arb_loss` writer - Clear arbitration loss interrupt"] pub type ClrIntArbLossW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clr_int_ack_err` writer - Clear ACK error interrupt"] pub type ClrIntAckErrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clr_int_rx` writer - Clear RX interrupt"] pub type ClrIntRxW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clr_int_tx` writer - Clear TX interrupt"] pub type ClrIntTxW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clr_int_stop` writer - Clear stop interrupt"] pub type ClrIntStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clr_int_start` writer - Clear start interrupt"] pub type ClrIntStartW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clr_int_rxtide` writer - Clear RX FIFO overflow interrupt"] pub type ClrIntRxtideW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clr_int_txtide` writer - Clear TX FIFO overflow interrupt"] pub type ClrIntTxtideW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clr_int_txfifo_over` writer - Clear TX FIFO complete interrupt"] pub type ClrIntTxfifoOverW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Clear transfer complete interrupt"]
#[inline (always)] pub fn clr_int_done (& mut self) -> ClrIntDoneW < '_ , I2cIcrSpec > { ClrIntDoneW :: new (self , 0) }
#[doc = "Bit 1 - Clear arbitration loss interrupt"]
#[inline (always)] pub fn clr_int_arb_loss (& mut self) -> ClrIntArbLossW < '_ , I2cIcrSpec > { ClrIntArbLossW :: new (self , 1) }
#[doc = "Bit 2 - Clear ACK error interrupt"]
#[inline (always)] pub fn clr_int_ack_err (& mut self) -> ClrIntAckErrW < '_ , I2cIcrSpec > { ClrIntAckErrW :: new (self , 2) }
#[doc = "Bit 3 - Clear RX interrupt"]
#[inline (always)] pub fn clr_int_rx (& mut self) -> ClrIntRxW < '_ , I2cIcrSpec > { ClrIntRxW :: new (self , 3) }
#[doc = "Bit 4 - Clear TX interrupt"]
#[inline (always)] pub fn clr_int_tx (& mut self) -> ClrIntTxW < '_ , I2cIcrSpec > { ClrIntTxW :: new (self , 4) }
#[doc = "Bit 5 - Clear stop interrupt"]
#[inline (always)] pub fn clr_int_stop (& mut self) -> ClrIntStopW < '_ , I2cIcrSpec > { ClrIntStopW :: new (self , 5) }
#[doc = "Bit 6 - Clear start interrupt"]
#[inline (always)] pub fn clr_int_start (& mut self) -> ClrIntStartW < '_ , I2cIcrSpec > { ClrIntStartW :: new (self , 6) }
#[doc = "Bit 7 - Clear RX FIFO overflow interrupt"]
#[inline (always)] pub fn clr_int_rxtide (& mut self) -> ClrIntRxtideW < '_ , I2cIcrSpec > { ClrIntRxtideW :: new (self , 7) }
#[doc = "Bit 8 - Clear TX FIFO overflow interrupt"]
#[inline (always)] pub fn clr_int_txtide (& mut self) -> ClrIntTxtideW < '_ , I2cIcrSpec > { ClrIntTxtideW :: new (self , 8) }
#[doc = "Bit 9 - Clear TX FIFO complete interrupt"]
#[inline (always)] pub fn clr_int_txfifo_over (& mut self) -> ClrIntTxfifoOverW < '_ , I2cIcrSpec > { ClrIntTxfifoOverW :: new (self , 9) } }
#[doc = "I2C interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cIcrSpec ; impl crate :: RegisterSpec for I2cIcrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_icr::R`](R) reader structure"] impl crate :: Readable for I2cIcrSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_icr::W`](W) writer structure"] impl crate :: Writable for I2cIcrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_ICR to value 0"] impl crate :: Resettable for I2cIcrSpec { } }
#[doc = "I2C_SR (rw) register accessor: I2C status register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_sr`] module"]
#[doc (alias = "I2C_SR")] pub type I2cSr = crate :: Reg < i2c_sr :: I2cSrSpec > ;
#[doc = "I2C status register"] pub mod i2c_sr {
#[doc = "Register `I2C_SR` reader"] pub type R = crate :: R < I2cSrSpec > ;
#[doc = "Register `I2C_SR` writer"] pub type W = crate :: W < I2cSrSpec > ;
#[doc = "Field `int_done` reader - Transfer complete interrupt flag"] pub type IntDoneR = crate :: BitReader ;
#[doc = "Field `int_arb_loss` reader - Arbitration loss interrupt flag"] pub type IntArbLossR = crate :: BitReader ;
#[doc = "Field `int_ack_err` reader - ACK error interrupt flag"] pub type IntAckErrR = crate :: BitReader ;
#[doc = "Field `int_rx` reader - RX interrupt flag"] pub type IntRxR = crate :: BitReader ;
#[doc = "Field `int_tx` reader - TX interrupt flag"] pub type IntTxR = crate :: BitReader ;
#[doc = "Field `int_stop` reader - Stop interrupt flag"] pub type IntStopR = crate :: BitReader ;
#[doc = "Field `int_start` reader - Start interrupt flag"] pub type IntStartR = crate :: BitReader ;
#[doc = "Field `bus_busy` reader - Bus busy: 0=idle; 1=busy"] pub type BusBusyR = crate :: BitReader ;
#[doc = "Field `int_rxtide` reader - RX FIFO overflow flag"] pub type IntRxtideR = crate :: BitReader ;
#[doc = "Field `int_txtide` reader - TX FIFO overflow flag"] pub type IntTxtideR = crate :: BitReader ;
#[doc = "Field `int_txfifo_over` reader - TX FIFO complete flag"] pub type IntTxfifoOverR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Transfer complete interrupt flag"]
#[inline (always)] pub fn int_done (& self) -> IntDoneR { IntDoneR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Arbitration loss interrupt flag"]
#[inline (always)] pub fn int_arb_loss (& self) -> IntArbLossR { IntArbLossR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - ACK error interrupt flag"]
#[inline (always)] pub fn int_ack_err (& self) -> IntAckErrR { IntAckErrR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - RX interrupt flag"]
#[inline (always)] pub fn int_rx (& self) -> IntRxR { IntRxR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - TX interrupt flag"]
#[inline (always)] pub fn int_tx (& self) -> IntTxR { IntTxR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Stop interrupt flag"]
#[inline (always)] pub fn int_stop (& self) -> IntStopR { IntStopR :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Start interrupt flag"]
#[inline (always)] pub fn int_start (& self) -> IntStartR { IntStartR :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 7 - Bus busy: 0=idle; 1=busy"]
#[inline (always)] pub fn bus_busy (& self) -> BusBusyR { BusBusyR :: new (((self . bits >> 7) & 1) != 0) }
#[doc = "Bit 8 - RX FIFO overflow flag"]
#[inline (always)] pub fn int_rxtide (& self) -> IntRxtideR { IntRxtideR :: new (((self . bits >> 8) & 1) != 0) }
#[doc = "Bit 9 - TX FIFO overflow flag"]
#[inline (always)] pub fn int_txtide (& self) -> IntTxtideR { IntTxtideR :: new (((self . bits >> 9) & 1) != 0) }
#[doc = "Bit 10 - TX FIFO complete flag"]
#[inline (always)] pub fn int_txfifo_over (& self) -> IntTxfifoOverR { IntTxfifoOverR :: new (((self . bits >> 10) & 1) != 0) } } impl W { }
#[doc = "I2C status register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cSrSpec ; impl crate :: RegisterSpec for I2cSrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_sr::R`](R) reader structure"] impl crate :: Readable for I2cSrSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_sr::W`](W) writer structure"] impl crate :: Writable for I2cSrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_SR to value 0"] impl crate :: Resettable for I2cSrSpec { } }
#[doc = "I2C_SCL_H (rw) register accessor: SCL high period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_h`] module"]
#[doc (alias = "I2C_SCL_H")] pub type I2cSclH = crate :: Reg < i2c_scl_h :: I2cSclHSpec > ;
#[doc = "SCL high period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]"] pub mod i2c_scl_h {
#[doc = "Register `I2C_SCL_H` reader"] pub type R = crate :: R < I2cSclHSpec > ;
#[doc = "Register `I2C_SCL_H` writer"] pub type W = crate :: W < I2cSclHSpec > ;
#[doc = "Field `scl_h` reader - SCL high period (value*2 = actual period)"] pub type SclHR = crate :: FieldReader < u16 > ;
#[doc = "Field `scl_h` writer - SCL high period (value*2 = actual period)"] pub type SclHW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - SCL high period (value*2 = actual period)"]
#[inline (always)] pub fn scl_h (& self) -> SclHR { SclHR :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - SCL high period (value*2 = actual period)"]
#[inline (always)] pub fn scl_h (& mut self) -> SclHW < '_ , I2cSclHSpec > { SclHW :: new (self , 0) } }
#[doc = "SCL high period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cSclHSpec ; impl crate :: RegisterSpec for I2cSclHSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_scl_h::R`](R) reader structure"] impl crate :: Readable for I2cSclHSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_scl_h::W`](W) writer structure"] impl crate :: Writable for I2cSclHSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_SCL_H to value 0"] impl crate :: Resettable for I2cSclHSpec { } }
#[doc = "I2C_SCL_L (rw) register accessor: SCL low period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_scl_l`] module"]
#[doc (alias = "I2C_SCL_L")] pub type I2cSclL = crate :: Reg < i2c_scl_l :: I2cSclLSpec > ;
#[doc = "SCL low period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]"] pub mod i2c_scl_l {
#[doc = "Register `I2C_SCL_L` reader"] pub type R = crate :: R < I2cSclLSpec > ;
#[doc = "Register `I2C_SCL_L` writer"] pub type W = crate :: W < I2cSclLSpec > ;
#[doc = "Field `scl_l` reader - SCL low period (value*2 = actual period)"] pub type SclLR = crate :: FieldReader < u16 > ;
#[doc = "Field `scl_l` writer - SCL low period (value*2 = actual period)"] pub type SclLW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - SCL low period (value*2 = actual period)"]
#[inline (always)] pub fn scl_l (& self) -> SclLR { SclLR :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - SCL low period (value*2 = actual period)"]
#[inline (always)] pub fn scl_l (& mut self) -> SclLW < '_ , I2cSclLSpec > { SclLW :: new (self , 0) } }
#[doc = "SCL low period register \\[Constraint: write only when I2C_CTRL\\[int_mask\\]=0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_scl_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_scl_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cSclLSpec ; impl crate :: RegisterSpec for I2cSclLSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_scl_l::R`](R) reader structure"] impl crate :: Readable for I2cSclLSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_scl_l::W`](W) writer structure"] impl crate :: Writable for I2cSclLSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_SCL_L to value 0"] impl crate :: Resettable for I2cSclLSpec { } }
#[doc = "I2C_TXR (rw) register accessor: I2C TX data register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_txr`] module"]
#[doc (alias = "I2C_TXR")] pub type I2cTxr = crate :: Reg < i2c_txr :: I2cTxrSpec > ;
#[doc = "I2C TX data register"] pub mod i2c_txr {
#[doc = "Register `I2C_TXR` reader"] pub type R = crate :: R < I2cTxrSpec > ;
#[doc = "Register `I2C_TXR` writer"] pub type W = crate :: W < I2cTxrSpec > ;
#[doc = "Field `i2c_txr` reader - TX data byte"] pub type I2cTxrR = crate :: FieldReader ;
#[doc = "Field `i2c_txr` writer - TX data byte"] pub type I2cTxrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - TX data byte"]
#[inline (always)] pub fn i2c_txr (& self) -> I2cTxrR { I2cTxrR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - TX data byte"]
#[inline (always)] pub fn i2c_txr (& mut self) -> I2cTxrW < '_ , I2cTxrSpec > { I2cTxrW :: new (self , 0) } }
#[doc = "I2C TX data register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cTxrSpec ; impl crate :: RegisterSpec for I2cTxrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_txr::R`](R) reader structure"] impl crate :: Readable for I2cTxrSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_txr::W`](W) writer structure"] impl crate :: Writable for I2cTxrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_TXR to value 0"] impl crate :: Resettable for I2cTxrSpec { } }
#[doc = "I2C_RXR (rw) register accessor: I2C RX data register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_rxr`] module"]
#[doc (alias = "I2C_RXR")] pub type I2cRxr = crate :: Reg < i2c_rxr :: I2cRxrSpec > ;
#[doc = "I2C RX data register"] pub mod i2c_rxr {
#[doc = "Register `I2C_RXR` reader"] pub type R = crate :: R < I2cRxrSpec > ;
#[doc = "Register `I2C_RXR` writer"] pub type W = crate :: W < I2cRxrSpec > ;
#[doc = "Field `i2c_rxr` reader - RX data byte"] pub type I2cRxrR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - RX data byte"]
#[inline (always)] pub fn i2c_rxr (& self) -> I2cRxrR { I2cRxrR :: new ((self . bits & 0xff) as u8) } } impl W { }
#[doc = "I2C RX data register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cRxrSpec ; impl crate :: RegisterSpec for I2cRxrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_rxr::R`](R) reader structure"] impl crate :: Readable for I2cRxrSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_rxr::W`](W) writer structure"] impl crate :: Writable for I2cRxrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_RXR to value 0"] impl crate :: Resettable for I2cRxrSpec { } }
#[doc = "I2C_FIFOSTATUS (rw) register accessor: FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_fifostatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_fifostatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_fifostatus`] module"]
#[doc (alias = "I2C_FIFOSTATUS")] pub type I2cFifostatus = crate :: Reg < i2c_fifostatus :: I2cFifostatusSpec > ;
#[doc = "FIFO status register"] pub mod i2c_fifostatus {
#[doc = "Register `I2C_FIFOSTATUS` reader"] pub type R = crate :: R < I2cFifostatusSpec > ;
#[doc = "Register `I2C_FIFOSTATUS` writer"] pub type W = crate :: W < I2cFifostatusSpec > ;
#[doc = "Field `txff` reader - TX FIFO full: 0=not full; 1=full"] pub type TxffR = crate :: BitReader ;
#[doc = "Field `txfe` reader - TX FIFO empty: 0=not empty; 1=empty"] pub type TxfeR = crate :: BitReader ;
#[doc = "Field `rxff` reader - RX FIFO full"] pub type RxffR = crate :: BitReader ;
#[doc = "Field `rxfe` reader - RX FIFO empty"] pub type RxfeR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - TX FIFO full: 0=not full; 1=full"]
#[inline (always)] pub fn txff (& self) -> TxffR { TxffR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TX FIFO empty: 0=not empty; 1=empty"]
#[inline (always)] pub fn txfe (& self) -> TxfeR { TxfeR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - RX FIFO full"]
#[inline (always)] pub fn rxff (& self) -> RxffR { RxffR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - RX FIFO empty"]
#[inline (always)] pub fn rxfe (& self) -> RxfeR { RxfeR :: new (((self . bits >> 3) & 1) != 0) } } impl W { }
#[doc = "FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_fifostatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_fifostatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cFifostatusSpec ; impl crate :: RegisterSpec for I2cFifostatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_fifostatus::R`](R) reader structure"] impl crate :: Readable for I2cFifostatusSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_fifostatus::W`](W) writer structure"] impl crate :: Writable for I2cFifostatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_FIFOSTATUS to value 0"] impl crate :: Resettable for I2cFifostatusSpec { } }
#[doc = "I2C_TXCOUNT (rw) register accessor: TX FIFO count register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txcount::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txcount::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_txcount`] module"]
#[doc (alias = "I2C_TXCOUNT")] pub type I2cTxcount = crate :: Reg < i2c_txcount :: I2cTxcountSpec > ;
#[doc = "TX FIFO count register"] pub mod i2c_txcount {
#[doc = "Register `I2C_TXCOUNT` reader"] pub type R = crate :: R < I2cTxcountSpec > ;
#[doc = "Register `I2C_TXCOUNT` writer"] pub type W = crate :: W < I2cTxcountSpec > ;
#[doc = "Field `txcount` reader - TX FIFO character count (write any value to clear TX FIFO)"] pub type TxcountR = crate :: FieldReader ;
#[doc = "Field `txcount` writer - TX FIFO character count (write any value to clear TX FIFO)"] pub type TxcountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R {
#[doc = "Bits 0:5 - TX FIFO character count (write any value to clear TX FIFO)"]
#[inline (always)] pub fn txcount (& self) -> TxcountR { TxcountR :: new ((self . bits & 0x3f) as u8) } } impl W {
#[doc = "Bits 0:5 - TX FIFO character count (write any value to clear TX FIFO)"]
#[inline (always)] pub fn txcount (& mut self) -> TxcountW < '_ , I2cTxcountSpec > { TxcountW :: new (self , 0) } }
#[doc = "TX FIFO count register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txcount::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txcount::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cTxcountSpec ; impl crate :: RegisterSpec for I2cTxcountSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_txcount::R`](R) reader structure"] impl crate :: Readable for I2cTxcountSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_txcount::W`](W) writer structure"] impl crate :: Writable for I2cTxcountSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_TXCOUNT to value 0"] impl crate :: Resettable for I2cTxcountSpec { } }
#[doc = "I2C_RXCOUNT (rw) register accessor: RX FIFO count register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxcount::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxcount::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_rxcount`] module"]
#[doc (alias = "I2C_RXCOUNT")] pub type I2cRxcount = crate :: Reg < i2c_rxcount :: I2cRxcountSpec > ;
#[doc = "RX FIFO count register"] pub mod i2c_rxcount {
#[doc = "Register `I2C_RXCOUNT` reader"] pub type R = crate :: R < I2cRxcountSpec > ;
#[doc = "Register `I2C_RXCOUNT` writer"] pub type W = crate :: W < I2cRxcountSpec > ;
#[doc = "Field `rxcount` reader - RX FIFO character count (write any value to clear RX FIFO)"] pub type RxcountR = crate :: FieldReader ;
#[doc = "Field `rxcount` writer - RX FIFO character count (write any value to clear RX FIFO)"] pub type RxcountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R {
#[doc = "Bits 0:5 - RX FIFO character count (write any value to clear RX FIFO)"]
#[inline (always)] pub fn rxcount (& self) -> RxcountR { RxcountR :: new ((self . bits & 0x3f) as u8) } } impl W {
#[doc = "Bits 0:5 - RX FIFO character count (write any value to clear RX FIFO)"]
#[inline (always)] pub fn rxcount (& mut self) -> RxcountW < '_ , I2cRxcountSpec > { RxcountW :: new (self , 0) } }
#[doc = "RX FIFO count register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxcount::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxcount::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cRxcountSpec ; impl crate :: RegisterSpec for I2cRxcountSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_rxcount::R`](R) reader structure"] impl crate :: Readable for I2cRxcountSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_rxcount::W`](W) writer structure"] impl crate :: Writable for I2cRxcountSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_RXCOUNT to value 0"] impl crate :: Resettable for I2cRxcountSpec { } }
#[doc = "I2C_RXTIDE (rw) register accessor: RX FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxtide::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxtide::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_rxtide`] module"]
#[doc (alias = "I2C_RXTIDE")] pub type I2cRxtide = crate :: Reg < i2c_rxtide :: I2cRxtideSpec > ;
#[doc = "RX FIFO threshold register"] pub mod i2c_rxtide {
#[doc = "Register `I2C_RXTIDE` reader"] pub type R = crate :: R < I2cRxtideSpec > ;
#[doc = "Register `I2C_RXTIDE` writer"] pub type W = crate :: W < I2cRxtideSpec > ;
#[doc = "Field `rxtide` reader - RX FIFO overflow interrupt trigger value"] pub type RxtideR = crate :: FieldReader ;
#[doc = "Field `rxtide` writer - RX FIFO overflow interrupt trigger value"] pub type RxtideW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R {
#[doc = "Bits 0:5 - RX FIFO overflow interrupt trigger value"]
#[inline (always)] pub fn rxtide (& self) -> RxtideR { RxtideR :: new ((self . bits & 0x3f) as u8) } } impl W {
#[doc = "Bits 0:5 - RX FIFO overflow interrupt trigger value"]
#[inline (always)] pub fn rxtide (& mut self) -> RxtideW < '_ , I2cRxtideSpec > { RxtideW :: new (self , 0) } }
#[doc = "RX FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_rxtide::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_rxtide::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cRxtideSpec ; impl crate :: RegisterSpec for I2cRxtideSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_rxtide::R`](R) reader structure"] impl crate :: Readable for I2cRxtideSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_rxtide::W`](W) writer structure"] impl crate :: Writable for I2cRxtideSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_RXTIDE to value 0x01"] impl crate :: Resettable for I2cRxtideSpec { const RESET_VALUE : u32 = 0x01 ; } }
#[doc = "I2C_TXTIDE (rw) register accessor: TX FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txtide::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txtide::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_txtide`] module"]
#[doc (alias = "I2C_TXTIDE")] pub type I2cTxtide = crate :: Reg < i2c_txtide :: I2cTxtideSpec > ;
#[doc = "TX FIFO threshold register"] pub mod i2c_txtide {
#[doc = "Register `I2C_TXTIDE` reader"] pub type R = crate :: R < I2cTxtideSpec > ;
#[doc = "Register `I2C_TXTIDE` writer"] pub type W = crate :: W < I2cTxtideSpec > ;
#[doc = "Field `txtide` reader - TX FIFO overflow interrupt trigger value"] pub type TxtideR = crate :: FieldReader ;
#[doc = "Field `txtide` writer - TX FIFO overflow interrupt trigger value"] pub type TxtideW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R {
#[doc = "Bits 0:5 - TX FIFO overflow interrupt trigger value"]
#[inline (always)] pub fn txtide (& self) -> TxtideR { TxtideR :: new ((self . bits & 0x3f) as u8) } } impl W {
#[doc = "Bits 0:5 - TX FIFO overflow interrupt trigger value"]
#[inline (always)] pub fn txtide (& mut self) -> TxtideW < '_ , I2cTxtideSpec > { TxtideW :: new (self , 0) } }
#[doc = "TX FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_txtide::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_txtide::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cTxtideSpec ; impl crate :: RegisterSpec for I2cTxtideSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_txtide::R`](R) reader structure"] impl crate :: Readable for I2cTxtideSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_txtide::W`](W) writer structure"] impl crate :: Writable for I2cTxtideSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_TXTIDE to value 0x01"] impl crate :: Resettable for I2cTxtideSpec { const RESET_VALUE : u32 = 0x01 ; } }
#[doc = "I2C_FTRPER (rw) register accessor: Glitch filter configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ftrper::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ftrper::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_ftrper`] module"]
#[doc (alias = "I2C_FTRPER")] pub type I2cFtrper = crate :: Reg < i2c_ftrper :: I2cFtrperSpec > ;
#[doc = "Glitch filter configuration register"] pub mod i2c_ftrper {
#[doc = "Register `I2C_FTRPER` reader"] pub type R = crate :: R < I2cFtrperSpec > ;
#[doc = "Register `I2C_FTRPER` writer"] pub type W = crate :: W < I2cFtrperSpec > ;
#[doc = "Field `ftrper` reader - Glitch filter period in ic_clk cycles"] pub type FtrperR = crate :: FieldReader ;
#[doc = "Field `ftrper` writer - Glitch filter period in ic_clk cycles"] pub type FtrperW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R {
#[doc = "Bits 0:3 - Glitch filter period in ic_clk cycles"]
#[inline (always)] pub fn ftrper (& self) -> FtrperR { FtrperR :: new ((self . bits & 0x0f) as u8) } } impl W {
#[doc = "Bits 0:3 - Glitch filter period in ic_clk cycles"]
#[inline (always)] pub fn ftrper (& mut self) -> FtrperW < '_ , I2cFtrperSpec > { FtrperW :: new (self , 0) } }
#[doc = "Glitch filter configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ftrper::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ftrper::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2cFtrperSpec ; impl crate :: RegisterSpec for I2cFtrperSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2c_ftrper::R`](R) reader structure"] impl crate :: Readable for I2cFtrperSpec { }
#[doc = "`write(|w| ..)` method takes [`i2c_ftrper::W`](W) writer structure"] impl crate :: Writable for I2cFtrperSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2C_FTRPER to value 0x0f"] impl crate :: Resettable for I2cFtrperSpec { const RESET_VALUE : u32 = 0x0f ; } } }
#[doc = "I2C1 master controller"] pub type I2c1 = crate :: Periph < i2c0 :: RegisterBlock , 0x4401_8100 > ; impl core :: fmt :: Debug for I2c1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("I2c1") . finish () } }
#[doc = "I2C1 master controller"] pub use self :: i2c0 as i2c1 ;
#[doc = "PWM controller with 8 channels"] pub type Pwm = crate :: Periph < pwm :: RegisterBlock , 0x4402_4000 > ; impl core :: fmt :: Debug for Pwm { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Pwm") . finish () } }
#[doc = "PWM controller with 8 channels"] pub mod pwm {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { pwm_sel0 : PwmSel0 , pwm_startclrcnt_en0 : PwmStartclrcntEn0 , pwm_start0 : PwmStart0 , _reserved3 : [u8 ; 0x04] , pwm_sel1 : PwmSel1 , pwm_startclrcnt_en1 : PwmStartclrcntEn1 , pwm_start1 : PwmStart1 , _reserved6 : [u8 ; 0x04] , pwm_sel2 : PwmSel2 , pwm_startclrcnt_en2 : PwmStartclrcntEn2 , pwm_start2 : PwmStart2 , _reserved9 : [u8 ; 0x04] , pwm_sel3 : PwmSel3 , pwm_startclrcnt_en3 : PwmStartclrcntEn3 , pwm_start3 : PwmStart3 , _reserved12 : [u8 ; 0xc4] , pwm_en0 : PwmEn0 , pwm_portity0 : PwmPortity0 , pwm_oen_cfg0 : PwmOenCfg0 , pwm_offset_l0 : PwmOffsetL0 , pwm_offset_h0 : PwmOffsetH0 , pwm_freq_l0 : PwmFreqL0 , pwm_freq_h0 : PwmFreqH0 , pwm_duty_l0 : PwmDutyL0 , pwm_duty_h0 : PwmDutyH0 , pwm_periodload_flag0 : PwmPeriodloadFlag0 , pwm_period_val0 : PwmPeriodVal0 , pwm_periodcnt0 : PwmPeriodcnt0 , _reserved24 : [u8 ; 0x10] , pwm_en1 : PwmEn1 , pwm_portity1 : PwmPortity1 , pwm_oen_cfg1 : PwmOenCfg1 , pwm_offset_l1 : PwmOffsetL1 , pwm_offset_h1 : PwmOffsetH1 , pwm_freq_l1 : PwmFreqL1 , pwm_freq_h1 : PwmFreqH1 , pwm_duty_l1 : PwmDutyL1 , pwm_duty_h1 : PwmDutyH1 , pwm_periodload_flag1 : PwmPeriodloadFlag1 , pwm_period_val1 : PwmPeriodVal1 , pwm_periodcnt1 : PwmPeriodcnt1 , _reserved36 : [u8 ; 0x10] , pwm_en2 : PwmEn2 , pwm_portity2 : PwmPortity2 , pwm_oen_cfg2 : PwmOenCfg2 , pwm_offset_l2 : PwmOffsetL2 , pwm_offset_h2 : PwmOffsetH2 , pwm_freq_l2 : PwmFreqL2 , pwm_freq_h2 : PwmFreqH2 , pwm_duty_l2 : PwmDutyL2 , pwm_duty_h2 : PwmDutyH2 , pwm_periodload_flag2 : PwmPeriodloadFlag2 , pwm_period_val2 : PwmPeriodVal2 , pwm_periodcnt2 : PwmPeriodcnt2 , _reserved48 : [u8 ; 0x10] , pwm_en3 : PwmEn3 , pwm_portity3 : PwmPortity3 , pwm_oen_cfg3 : PwmOenCfg3 , pwm_offset_l3 : PwmOffsetL3 , pwm_offset_h3 : PwmOffsetH3 , pwm_freq_l3 : PwmFreqL3 , pwm_freq_h3 : PwmFreqH3 , pwm_duty_l3 : PwmDutyL3 , pwm_duty_h3 : PwmDutyH3 , pwm_periodload_flag3 : PwmPeriodloadFlag3 , pwm_period_val3 : PwmPeriodVal3 , pwm_periodcnt3 : PwmPeriodcnt3 , _reserved60 : [u8 ; 0x10] , pwm_en4 : PwmEn4 , pwm_portity4 : PwmPortity4 , pwm_oen_cfg4 : PwmOenCfg4 , pwm_offset_l4 : PwmOffsetL4 , pwm_offset_h4 : PwmOffsetH4 , pwm_freq_l4 : PwmFreqL4 , pwm_freq_h4 : PwmFreqH4 , pwm_duty_l4 : PwmDutyL4 , pwm_duty_h4 : PwmDutyH4 , pwm_periodload_flag4 : PwmPeriodloadFlag4 , pwm_period_val4 : PwmPeriodVal4 , pwm_periodcnt4 : PwmPeriodcnt4 , _reserved72 : [u8 ; 0x10] , pwm_en5 : PwmEn5 , pwm_portity5 : PwmPortity5 , pwm_oen_cfg5 : PwmOenCfg5 , pwm_offset_l5 : PwmOffsetL5 , pwm_offset_h5 : PwmOffsetH5 , pwm_freq_l5 : PwmFreqL5 , pwm_freq_h5 : PwmFreqH5 , pwm_duty_l5 : PwmDutyL5 , pwm_duty_h5 : PwmDutyH5 , pwm_periodload_flag5 : PwmPeriodloadFlag5 , pwm_period_val5 : PwmPeriodVal5 , pwm_periodcnt5 : PwmPeriodcnt5 , _reserved84 : [u8 ; 0x10] , pwm_en6 : PwmEn6 , pwm_portity6 : PwmPortity6 , pwm_oen_cfg6 : PwmOenCfg6 , pwm_offset_l6 : PwmOffsetL6 , pwm_offset_h6 : PwmOffsetH6 , pwm_freq_l6 : PwmFreqL6 , pwm_freq_h6 : PwmFreqH6 , pwm_duty_l6 : PwmDutyL6 , pwm_duty_h6 : PwmDutyH6 , pwm_periodload_flag6 : PwmPeriodloadFlag6 , pwm_period_val6 : PwmPeriodVal6 , pwm_periodcnt6 : PwmPeriodcnt6 , _reserved96 : [u8 ; 0x10] , pwm_en7 : PwmEn7 , pwm_portity7 : PwmPortity7 , pwm_oen_cfg7 : PwmOenCfg7 , pwm_offset_l7 : PwmOffsetL7 , pwm_offset_h7 : PwmOffsetH7 , pwm_freq_l7 : PwmFreqL7 , pwm_freq_h7 : PwmFreqH7 , pwm_duty_l7 : PwmDutyL7 , pwm_duty_h7 : PwmDutyH7 , pwm_periodload_flag7 : PwmPeriodloadFlag7 , pwm_period_val7 : PwmPeriodVal7 , pwm_periodcnt7 : PwmPeriodcnt7 , _reserved108 : [u8 ; 0x0210] , pwm_abnor_state0 : PwmAbnorState0 , pwm_abnor_state1 : PwmAbnorState1 , pwm_abnor_state_clr0 : PwmAbnorStateClr0 , pwm_abnor_state_clr1 : PwmAbnorStateClr1 , pwm_int_mask : PwmIntMask , pwm_dma_en : PwmDmaEn , pwm_cfg_int_clr0 : PwmCfgIntClr0 , } impl RegisterBlock {
#[doc = "0x00 - PWM group 0 select"]
#[inline (always)] pub const fn pwm_sel0 (& self) -> & PwmSel0 { & self . pwm_sel0 }
#[doc = "0x04 - PWM group 0 start clear counter enable"]
#[inline (always)] pub const fn pwm_startclrcnt_en0 (& self) -> & PwmStartclrcntEn0 { & self . pwm_startclrcnt_en0 }
#[doc = "0x08 - PWM group 0 start"]
#[inline (always)] pub const fn pwm_start0 (& self) -> & PwmStart0 { & self . pwm_start0 }
#[doc = "0x10 - PWM group 1 select"]
#[inline (always)] pub const fn pwm_sel1 (& self) -> & PwmSel1 { & self . pwm_sel1 }
#[doc = "0x14 - PWM group 1 start clear counter enable"]
#[inline (always)] pub const fn pwm_startclrcnt_en1 (& self) -> & PwmStartclrcntEn1 { & self . pwm_startclrcnt_en1 }
#[doc = "0x18 - PWM group 1 start"]
#[inline (always)] pub const fn pwm_start1 (& self) -> & PwmStart1 { & self . pwm_start1 }
#[doc = "0x20 - PWM group 2 select"]
#[inline (always)] pub const fn pwm_sel2 (& self) -> & PwmSel2 { & self . pwm_sel2 }
#[doc = "0x24 - PWM group 2 start clear counter enable"]
#[inline (always)] pub const fn pwm_startclrcnt_en2 (& self) -> & PwmStartclrcntEn2 { & self . pwm_startclrcnt_en2 }
#[doc = "0x28 - PWM group 2 start"]
#[inline (always)] pub const fn pwm_start2 (& self) -> & PwmStart2 { & self . pwm_start2 }
#[doc = "0x30 - PWM group 3 select"]
#[inline (always)] pub const fn pwm_sel3 (& self) -> & PwmSel3 { & self . pwm_sel3 }
#[doc = "0x34 - PWM group 3 start clear counter enable"]
#[inline (always)] pub const fn pwm_startclrcnt_en3 (& self) -> & PwmStartclrcntEn3 { & self . pwm_startclrcnt_en3 }
#[doc = "0x38 - PWM group 3 start"]
#[inline (always)] pub const fn pwm_start3 (& self) -> & PwmStart3 { & self . pwm_start3 }
#[doc = "0x100 - PWM0 enable"]
#[inline (always)] pub const fn pwm_en0 (& self) -> & PwmEn0 { & self . pwm_en0 }
#[doc = "0x104 - PWM0 polarity"]
#[inline (always)] pub const fn pwm_portity0 (& self) -> & PwmPortity0 { & self . pwm_portity0 }
#[doc = "0x108 - PWM0 high-impedance config"]
#[inline (always)] pub const fn pwm_oen_cfg0 (& self) -> & PwmOenCfg0 { & self . pwm_oen_cfg0 }
#[doc = "0x10c - PWM0 phase offset low 16 bits"]
#[inline (always)] pub const fn pwm_offset_l0 (& self) -> & PwmOffsetL0 { & self . pwm_offset_l0 }
#[doc = "0x110 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub const fn pwm_offset_h0 (& self) -> & PwmOffsetH0 { & self . pwm_offset_h0 }
#[doc = "0x114 - PWM0 frequency low 16 bits"]
#[inline (always)] pub const fn pwm_freq_l0 (& self) -> & PwmFreqL0 { & self . pwm_freq_l0 }
#[doc = "0x118 - PWM0 frequency high 16 bits"]
#[inline (always)] pub const fn pwm_freq_h0 (& self) -> & PwmFreqH0 { & self . pwm_freq_h0 }
#[doc = "0x11c - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub const fn pwm_duty_l0 (& self) -> & PwmDutyL0 { & self . pwm_duty_l0 }
#[doc = "0x120 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub const fn pwm_duty_h0 (& self) -> & PwmDutyH0 { & self . pwm_duty_h0 }
#[doc = "0x124 - PWM0 period load flag"]
#[inline (always)] pub const fn pwm_periodload_flag0 (& self) -> & PwmPeriodloadFlag0 { & self . pwm_periodload_flag0 }
#[doc = "0x128 - PWM0 pulse count value"]
#[inline (always)] pub const fn pwm_period_val0 (& self) -> & PwmPeriodVal0 { & self . pwm_period_val0 }
#[doc = "0x12c - PWM0 pulse count current value"]
#[inline (always)] pub const fn pwm_periodcnt0 (& self) -> & PwmPeriodcnt0 { & self . pwm_periodcnt0 }
#[doc = "0x140 - PWM1 enable"]
#[inline (always)] pub const fn pwm_en1 (& self) -> & PwmEn1 { & self . pwm_en1 }
#[doc = "0x144 - PWM1 polarity"]
#[inline (always)] pub const fn pwm_portity1 (& self) -> & PwmPortity1 { & self . pwm_portity1 }
#[doc = "0x148 - PWM1 high-impedance config"]
#[inline (always)] pub const fn pwm_oen_cfg1 (& self) -> & PwmOenCfg1 { & self . pwm_oen_cfg1 }
#[doc = "0x14c - PWM1 phase offset low"]
#[inline (always)] pub const fn pwm_offset_l1 (& self) -> & PwmOffsetL1 { & self . pwm_offset_l1 }
#[doc = "0x150 - PWM1 phase offset high"]
#[inline (always)] pub const fn pwm_offset_h1 (& self) -> & PwmOffsetH1 { & self . pwm_offset_h1 }
#[doc = "0x154 - PWM1 frequency low"]
#[inline (always)] pub const fn pwm_freq_l1 (& self) -> & PwmFreqL1 { & self . pwm_freq_l1 }
#[doc = "0x158 - PWM1 frequency high"]
#[inline (always)] pub const fn pwm_freq_h1 (& self) -> & PwmFreqH1 { & self . pwm_freq_h1 }
#[doc = "0x15c - PWM1 duty cycle low"]
#[inline (always)] pub const fn pwm_duty_l1 (& self) -> & PwmDutyL1 { & self . pwm_duty_l1 }
#[doc = "0x160 - PWM1 duty cycle high"]
#[inline (always)] pub const fn pwm_duty_h1 (& self) -> & PwmDutyH1 { & self . pwm_duty_h1 }
#[doc = "0x164 - PWM1 period load flag"]
#[inline (always)] pub const fn pwm_periodload_flag1 (& self) -> & PwmPeriodloadFlag1 { & self . pwm_periodload_flag1 }
#[doc = "0x168 - PWM1 pulse count"]
#[inline (always)] pub const fn pwm_period_val1 (& self) -> & PwmPeriodVal1 { & self . pwm_period_val1 }
#[doc = "0x16c - PWM1 pulse count current"]
#[inline (always)] pub const fn pwm_periodcnt1 (& self) -> & PwmPeriodcnt1 { & self . pwm_periodcnt1 }
#[doc = "0x180 - PWM2 enable"]
#[inline (always)] pub const fn pwm_en2 (& self) -> & PwmEn2 { & self . pwm_en2 }
#[doc = "0x184 - PWM2 polarity"]
#[inline (always)] pub const fn pwm_portity2 (& self) -> & PwmPortity2 { & self . pwm_portity2 }
#[doc = "0x188 - PWM2 high-impedance config"]
#[inline (always)] pub const fn pwm_oen_cfg2 (& self) -> & PwmOenCfg2 { & self . pwm_oen_cfg2 }
#[doc = "0x18c - PWM2 phase offset low 16 bits"]
#[inline (always)] pub const fn pwm_offset_l2 (& self) -> & PwmOffsetL2 { & self . pwm_offset_l2 }
#[doc = "0x190 - PWM2 phase offset high 16 bits"]
#[inline (always)] pub const fn pwm_offset_h2 (& self) -> & PwmOffsetH2 { & self . pwm_offset_h2 }
#[doc = "0x194 - PWM2 frequency low 16 bits"]
#[inline (always)] pub const fn pwm_freq_l2 (& self) -> & PwmFreqL2 { & self . pwm_freq_l2 }
#[doc = "0x198 - PWM2 frequency high 16 bits"]
#[inline (always)] pub const fn pwm_freq_h2 (& self) -> & PwmFreqH2 { & self . pwm_freq_h2 }
#[doc = "0x19c - PWM2 duty cycle low 16 bits"]
#[inline (always)] pub const fn pwm_duty_l2 (& self) -> & PwmDutyL2 { & self . pwm_duty_l2 }
#[doc = "0x1a0 - PWM2 duty cycle high 16 bits"]
#[inline (always)] pub const fn pwm_duty_h2 (& self) -> & PwmDutyH2 { & self . pwm_duty_h2 }
#[doc = "0x1a4 - PWM2 period load flag"]
#[inline (always)] pub const fn pwm_periodload_flag2 (& self) -> & PwmPeriodloadFlag2 { & self . pwm_periodload_flag2 }
#[doc = "0x1a8 - PWM2 pulse count value"]
#[inline (always)] pub const fn pwm_period_val2 (& self) -> & PwmPeriodVal2 { & self . pwm_period_val2 }
#[doc = "0x1ac - PWM2 pulse count current value"]
#[inline (always)] pub const fn pwm_periodcnt2 (& self) -> & PwmPeriodcnt2 { & self . pwm_periodcnt2 }
#[doc = "0x1c0 - PWM3 enable"]
#[inline (always)] pub const fn pwm_en3 (& self) -> & PwmEn3 { & self . pwm_en3 }
#[doc = "0x1c4 - PWM3 polarity"]
#[inline (always)] pub const fn pwm_portity3 (& self) -> & PwmPortity3 { & self . pwm_portity3 }
#[doc = "0x1c8 - PWM3 high-impedance config"]
#[inline (always)] pub const fn pwm_oen_cfg3 (& self) -> & PwmOenCfg3 { & self . pwm_oen_cfg3 }
#[doc = "0x1cc - PWM3 phase offset low 16 bits"]
#[inline (always)] pub const fn pwm_offset_l3 (& self) -> & PwmOffsetL3 { & self . pwm_offset_l3 }
#[doc = "0x1d0 - PWM3 phase offset high 16 bits"]
#[inline (always)] pub const fn pwm_offset_h3 (& self) -> & PwmOffsetH3 { & self . pwm_offset_h3 }
#[doc = "0x1d4 - PWM3 frequency low 16 bits"]
#[inline (always)] pub const fn pwm_freq_l3 (& self) -> & PwmFreqL3 { & self . pwm_freq_l3 }
#[doc = "0x1d8 - PWM3 frequency high 16 bits"]
#[inline (always)] pub const fn pwm_freq_h3 (& self) -> & PwmFreqH3 { & self . pwm_freq_h3 }
#[doc = "0x1dc - PWM3 duty cycle low 16 bits"]
#[inline (always)] pub const fn pwm_duty_l3 (& self) -> & PwmDutyL3 { & self . pwm_duty_l3 }
#[doc = "0x1e0 - PWM3 duty cycle high 16 bits"]
#[inline (always)] pub const fn pwm_duty_h3 (& self) -> & PwmDutyH3 { & self . pwm_duty_h3 }
#[doc = "0x1e4 - PWM3 period load flag"]
#[inline (always)] pub const fn pwm_periodload_flag3 (& self) -> & PwmPeriodloadFlag3 { & self . pwm_periodload_flag3 }
#[doc = "0x1e8 - PWM3 pulse count value"]
#[inline (always)] pub const fn pwm_period_val3 (& self) -> & PwmPeriodVal3 { & self . pwm_period_val3 }
#[doc = "0x1ec - PWM3 pulse count current value"]
#[inline (always)] pub const fn pwm_periodcnt3 (& self) -> & PwmPeriodcnt3 { & self . pwm_periodcnt3 }
#[doc = "0x200 - PWM4 enable"]
#[inline (always)] pub const fn pwm_en4 (& self) -> & PwmEn4 { & self . pwm_en4 }
#[doc = "0x204 - PWM4 polarity"]
#[inline (always)] pub const fn pwm_portity4 (& self) -> & PwmPortity4 { & self . pwm_portity4 }
#[doc = "0x208 - PWM4 high-impedance config"]
#[inline (always)] pub const fn pwm_oen_cfg4 (& self) -> & PwmOenCfg4 { & self . pwm_oen_cfg4 }
#[doc = "0x20c - PWM4 phase offset low 16 bits"]
#[inline (always)] pub const fn pwm_offset_l4 (& self) -> & PwmOffsetL4 { & self . pwm_offset_l4 }
#[doc = "0x210 - PWM4 phase offset high 16 bits"]
#[inline (always)] pub const fn pwm_offset_h4 (& self) -> & PwmOffsetH4 { & self . pwm_offset_h4 }
#[doc = "0x214 - PWM4 frequency low 16 bits"]
#[inline (always)] pub const fn pwm_freq_l4 (& self) -> & PwmFreqL4 { & self . pwm_freq_l4 }
#[doc = "0x218 - PWM4 frequency high 16 bits"]
#[inline (always)] pub const fn pwm_freq_h4 (& self) -> & PwmFreqH4 { & self . pwm_freq_h4 }
#[doc = "0x21c - PWM4 duty cycle low 16 bits"]
#[inline (always)] pub const fn pwm_duty_l4 (& self) -> & PwmDutyL4 { & self . pwm_duty_l4 }
#[doc = "0x220 - PWM4 duty cycle high 16 bits"]
#[inline (always)] pub const fn pwm_duty_h4 (& self) -> & PwmDutyH4 { & self . pwm_duty_h4 }
#[doc = "0x224 - PWM4 period load flag"]
#[inline (always)] pub const fn pwm_periodload_flag4 (& self) -> & PwmPeriodloadFlag4 { & self . pwm_periodload_flag4 }
#[doc = "0x228 - PWM4 pulse count value"]
#[inline (always)] pub const fn pwm_period_val4 (& self) -> & PwmPeriodVal4 { & self . pwm_period_val4 }
#[doc = "0x22c - PWM4 pulse count current value"]
#[inline (always)] pub const fn pwm_periodcnt4 (& self) -> & PwmPeriodcnt4 { & self . pwm_periodcnt4 }
#[doc = "0x240 - PWM5 enable"]
#[inline (always)] pub const fn pwm_en5 (& self) -> & PwmEn5 { & self . pwm_en5 }
#[doc = "0x244 - PWM5 polarity"]
#[inline (always)] pub const fn pwm_portity5 (& self) -> & PwmPortity5 { & self . pwm_portity5 }
#[doc = "0x248 - PWM5 high-impedance config"]
#[inline (always)] pub const fn pwm_oen_cfg5 (& self) -> & PwmOenCfg5 { & self . pwm_oen_cfg5 }
#[doc = "0x24c - PWM5 phase offset low 16 bits"]
#[inline (always)] pub const fn pwm_offset_l5 (& self) -> & PwmOffsetL5 { & self . pwm_offset_l5 }
#[doc = "0x250 - PWM5 phase offset high 16 bits"]
#[inline (always)] pub const fn pwm_offset_h5 (& self) -> & PwmOffsetH5 { & self . pwm_offset_h5 }
#[doc = "0x254 - PWM5 frequency low 16 bits"]
#[inline (always)] pub const fn pwm_freq_l5 (& self) -> & PwmFreqL5 { & self . pwm_freq_l5 }
#[doc = "0x258 - PWM5 frequency high 16 bits"]
#[inline (always)] pub const fn pwm_freq_h5 (& self) -> & PwmFreqH5 { & self . pwm_freq_h5 }
#[doc = "0x25c - PWM5 duty cycle low 16 bits"]
#[inline (always)] pub const fn pwm_duty_l5 (& self) -> & PwmDutyL5 { & self . pwm_duty_l5 }
#[doc = "0x260 - PWM5 duty cycle high 16 bits"]
#[inline (always)] pub const fn pwm_duty_h5 (& self) -> & PwmDutyH5 { & self . pwm_duty_h5 }
#[doc = "0x264 - PWM5 period load flag"]
#[inline (always)] pub const fn pwm_periodload_flag5 (& self) -> & PwmPeriodloadFlag5 { & self . pwm_periodload_flag5 }
#[doc = "0x268 - PWM5 pulse count value"]
#[inline (always)] pub const fn pwm_period_val5 (& self) -> & PwmPeriodVal5 { & self . pwm_period_val5 }
#[doc = "0x26c - PWM5 pulse count current value"]
#[inline (always)] pub const fn pwm_periodcnt5 (& self) -> & PwmPeriodcnt5 { & self . pwm_periodcnt5 }
#[doc = "0x280 - PWM6 enable"]
#[inline (always)] pub const fn pwm_en6 (& self) -> & PwmEn6 { & self . pwm_en6 }
#[doc = "0x284 - PWM6 polarity"]
#[inline (always)] pub const fn pwm_portity6 (& self) -> & PwmPortity6 { & self . pwm_portity6 }
#[doc = "0x288 - PWM6 high-impedance config"]
#[inline (always)] pub const fn pwm_oen_cfg6 (& self) -> & PwmOenCfg6 { & self . pwm_oen_cfg6 }
#[doc = "0x28c - PWM6 phase offset low 16 bits"]
#[inline (always)] pub const fn pwm_offset_l6 (& self) -> & PwmOffsetL6 { & self . pwm_offset_l6 }
#[doc = "0x290 - PWM6 phase offset high 16 bits"]
#[inline (always)] pub const fn pwm_offset_h6 (& self) -> & PwmOffsetH6 { & self . pwm_offset_h6 }
#[doc = "0x294 - PWM6 frequency low 16 bits"]
#[inline (always)] pub const fn pwm_freq_l6 (& self) -> & PwmFreqL6 { & self . pwm_freq_l6 }
#[doc = "0x298 - PWM6 frequency high 16 bits"]
#[inline (always)] pub const fn pwm_freq_h6 (& self) -> & PwmFreqH6 { & self . pwm_freq_h6 }
#[doc = "0x29c - PWM6 duty cycle low 16 bits"]
#[inline (always)] pub const fn pwm_duty_l6 (& self) -> & PwmDutyL6 { & self . pwm_duty_l6 }
#[doc = "0x2a0 - PWM6 duty cycle high 16 bits"]
#[inline (always)] pub const fn pwm_duty_h6 (& self) -> & PwmDutyH6 { & self . pwm_duty_h6 }
#[doc = "0x2a4 - PWM6 period load flag"]
#[inline (always)] pub const fn pwm_periodload_flag6 (& self) -> & PwmPeriodloadFlag6 { & self . pwm_periodload_flag6 }
#[doc = "0x2a8 - PWM6 pulse count value"]
#[inline (always)] pub const fn pwm_period_val6 (& self) -> & PwmPeriodVal6 { & self . pwm_period_val6 }
#[doc = "0x2ac - PWM6 pulse count current value"]
#[inline (always)] pub const fn pwm_periodcnt6 (& self) -> & PwmPeriodcnt6 { & self . pwm_periodcnt6 }
#[doc = "0x2c0 - PWM7 enable"]
#[inline (always)] pub const fn pwm_en7 (& self) -> & PwmEn7 { & self . pwm_en7 }
#[doc = "0x2c4 - PWM7 polarity"]
#[inline (always)] pub const fn pwm_portity7 (& self) -> & PwmPortity7 { & self . pwm_portity7 }
#[doc = "0x2c8 - PWM7 high-impedance config"]
#[inline (always)] pub const fn pwm_oen_cfg7 (& self) -> & PwmOenCfg7 { & self . pwm_oen_cfg7 }
#[doc = "0x2cc - PWM7 phase offset low 16 bits"]
#[inline (always)] pub const fn pwm_offset_l7 (& self) -> & PwmOffsetL7 { & self . pwm_offset_l7 }
#[doc = "0x2d0 - PWM7 phase offset high 16 bits"]
#[inline (always)] pub const fn pwm_offset_h7 (& self) -> & PwmOffsetH7 { & self . pwm_offset_h7 }
#[doc = "0x2d4 - PWM7 frequency low 16 bits"]
#[inline (always)] pub const fn pwm_freq_l7 (& self) -> & PwmFreqL7 { & self . pwm_freq_l7 }
#[doc = "0x2d8 - PWM7 frequency high 16 bits"]
#[inline (always)] pub const fn pwm_freq_h7 (& self) -> & PwmFreqH7 { & self . pwm_freq_h7 }
#[doc = "0x2dc - PWM7 duty cycle low 16 bits"]
#[inline (always)] pub const fn pwm_duty_l7 (& self) -> & PwmDutyL7 { & self . pwm_duty_l7 }
#[doc = "0x2e0 - PWM7 duty cycle high 16 bits"]
#[inline (always)] pub const fn pwm_duty_h7 (& self) -> & PwmDutyH7 { & self . pwm_duty_h7 }
#[doc = "0x2e4 - PWM7 period load flag"]
#[inline (always)] pub const fn pwm_periodload_flag7 (& self) -> & PwmPeriodloadFlag7 { & self . pwm_periodload_flag7 }
#[doc = "0x2e8 - PWM7 pulse count value"]
#[inline (always)] pub const fn pwm_period_val7 (& self) -> & PwmPeriodVal7 { & self . pwm_period_val7 }
#[doc = "0x2ec - PWM7 pulse count current value"]
#[inline (always)] pub const fn pwm_periodcnt7 (& self) -> & PwmPeriodcnt7 { & self . pwm_periodcnt7 }
#[doc = "0x500 - PWM abnormal state register 0"]
#[inline (always)] pub const fn pwm_abnor_state0 (& self) -> & PwmAbnorState0 { & self . pwm_abnor_state0 }
#[doc = "0x504 - PWM abnormal state register 1"]
#[inline (always)] pub const fn pwm_abnor_state1 (& self) -> & PwmAbnorState1 { & self . pwm_abnor_state1 }
#[doc = "0x508 - PWM abnormal state clear 0"]
#[inline (always)] pub const fn pwm_abnor_state_clr0 (& self) -> & PwmAbnorStateClr0 { & self . pwm_abnor_state_clr0 }
#[doc = "0x50c - PWM abnormal state clear 1"]
#[inline (always)] pub const fn pwm_abnor_state_clr1 (& self) -> & PwmAbnorStateClr1 { & self . pwm_abnor_state_clr1 }
#[doc = "0x510 - PWM interrupt mask"]
#[inline (always)] pub const fn pwm_int_mask (& self) -> & PwmIntMask { & self . pwm_int_mask }
#[doc = "0x514 - PWM DMA enable"]
#[inline (always)] pub const fn pwm_dma_en (& self) -> & PwmDmaEn { & self . pwm_dma_en }
#[doc = "0x518 - PWM stepping cycle end interrupt clear"]
#[inline (always)] pub const fn pwm_cfg_int_clr0 (& self) -> & PwmCfgIntClr0 { & self . pwm_cfg_int_clr0 } }
#[doc = "PWM_SEL0 (rw) register accessor: PWM group 0 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel0`] module"]
#[doc (alias = "PWM_SEL0")] pub type PwmSel0 = crate :: Reg < pwm_sel0 :: PwmSel0Spec > ;
#[doc = "PWM group 0 select"] pub mod pwm_sel0 {
#[doc = "Register `PWM_SEL0` reader"] pub type R = crate :: R < PwmSel0Spec > ;
#[doc = "Register `PWM_SEL0` writer"] pub type W = crate :: W < PwmSel0Spec > ;
#[doc = "Field `pwm_sel_0` reader - Group 0 PWM select, each bit corresponds to one PWM channel"] pub type PwmSel0R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_sel_0` writer - Group 0 PWM select, each bit corresponds to one PWM channel"] pub type PwmSel0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Group 0 PWM select, each bit corresponds to one PWM channel"]
#[inline (always)] pub fn pwm_sel_0 (& self) -> PwmSel0R { PwmSel0R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Group 0 PWM select, each bit corresponds to one PWM channel"]
#[inline (always)] pub fn pwm_sel_0 (& mut self) -> PwmSel0W < '_ , PwmSel0Spec > { PwmSel0W :: new (self , 0) } }
#[doc = "PWM group 0 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmSel0Spec ; impl crate :: RegisterSpec for PwmSel0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_sel0::R`](R) reader structure"] impl crate :: Readable for PwmSel0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_sel0::W`](W) writer structure"] impl crate :: Writable for PwmSel0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_SEL0 to value 0"] impl crate :: Resettable for PwmSel0Spec { } }
#[doc = "PWM_STARTCLRCNT_EN0 (rw) register accessor: PWM group 0 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en0`] module"]
#[doc (alias = "PWM_STARTCLRCNT_EN0")] pub type PwmStartclrcntEn0 = crate :: Reg < pwm_startclrcnt_en0 :: PwmStartclrcntEn0Spec > ;
#[doc = "PWM group 0 start clear counter enable"] pub mod pwm_startclrcnt_en0 {
#[doc = "Register `PWM_STARTCLRCNT_EN0` reader"] pub type R = crate :: R < PwmStartclrcntEn0Spec > ;
#[doc = "Register `PWM_STARTCLRCNT_EN0` writer"] pub type W = crate :: W < PwmStartclrcntEn0Spec > ;
#[doc = "Field `pwm_startclrcnt_en_0` reader - Start clear counter enable for group 0"] pub type PwmStartclrcntEn0R = crate :: BitReader ;
#[doc = "Field `pwm_startclrcnt_en_0` writer - Start clear counter enable for group 0"] pub type PwmStartclrcntEn0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Start clear counter enable for group 0"]
#[inline (always)] pub fn pwm_startclrcnt_en_0 (& self) -> PwmStartclrcntEn0R { PwmStartclrcntEn0R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Start clear counter enable for group 0"]
#[inline (always)] pub fn pwm_startclrcnt_en_0 (& mut self) -> PwmStartclrcntEn0W < '_ , PwmStartclrcntEn0Spec > { PwmStartclrcntEn0W :: new (self , 0) } }
#[doc = "PWM group 0 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmStartclrcntEn0Spec ; impl crate :: RegisterSpec for PwmStartclrcntEn0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_startclrcnt_en0::R`](R) reader structure"] impl crate :: Readable for PwmStartclrcntEn0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en0::W`](W) writer structure"] impl crate :: Writable for PwmStartclrcntEn0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_STARTCLRCNT_EN0 to value 0"] impl crate :: Resettable for PwmStartclrcntEn0Spec { } }
#[doc = "PWM_START0 (rw) register accessor: PWM group 0 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start0`] module"]
#[doc (alias = "PWM_START0")] pub type PwmStart0 = crate :: Reg < pwm_start0 :: PwmStart0Spec > ;
#[doc = "PWM group 0 start"] pub mod pwm_start0 {
#[doc = "Register `PWM_START0` reader"] pub type R = crate :: R < PwmStart0Spec > ;
#[doc = "Register `PWM_START0` writer"] pub type W = crate :: W < PwmStart0Spec > ;
#[doc = "Field `pwm_start_0` writer - Start group 0 (self-clearing)"] pub type PwmStart0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Start group 0 (self-clearing)"]
#[inline (always)] pub fn pwm_start_0 (& mut self) -> PwmStart0W < '_ , PwmStart0Spec > { PwmStart0W :: new (self , 0) } }
#[doc = "PWM group 0 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmStart0Spec ; impl crate :: RegisterSpec for PwmStart0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_start0::R`](R) reader structure"] impl crate :: Readable for PwmStart0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_start0::W`](W) writer structure"] impl crate :: Writable for PwmStart0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_START0 to value 0"] impl crate :: Resettable for PwmStart0Spec { } }
#[doc = "PWM_SEL1 (rw) register accessor: PWM group 1 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel1`] module"]
#[doc (alias = "PWM_SEL1")] pub type PwmSel1 = crate :: Reg < pwm_sel1 :: PwmSel1Spec > ;
#[doc = "PWM group 1 select"] pub mod pwm_sel1 {
#[doc = "Register `PWM_SEL1` reader"] pub type R = crate :: R < PwmSel1Spec > ;
#[doc = "Register `PWM_SEL1` writer"] pub type W = crate :: W < PwmSel1Spec > ;
#[doc = "Field `pwm_sel_1` reader - Group 1 PWM select"] pub type PwmSel1R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_sel_1` writer - Group 1 PWM select"] pub type PwmSel1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Group 1 PWM select"]
#[inline (always)] pub fn pwm_sel_1 (& self) -> PwmSel1R { PwmSel1R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Group 1 PWM select"]
#[inline (always)] pub fn pwm_sel_1 (& mut self) -> PwmSel1W < '_ , PwmSel1Spec > { PwmSel1W :: new (self , 0) } }
#[doc = "PWM group 1 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmSel1Spec ; impl crate :: RegisterSpec for PwmSel1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_sel1::R`](R) reader structure"] impl crate :: Readable for PwmSel1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_sel1::W`](W) writer structure"] impl crate :: Writable for PwmSel1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_SEL1 to value 0"] impl crate :: Resettable for PwmSel1Spec { } }
#[doc = "PWM_STARTCLRCNT_EN1 (rw) register accessor: PWM group 1 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en1`] module"]
#[doc (alias = "PWM_STARTCLRCNT_EN1")] pub type PwmStartclrcntEn1 = crate :: Reg < pwm_startclrcnt_en1 :: PwmStartclrcntEn1Spec > ;
#[doc = "PWM group 1 start clear counter enable"] pub mod pwm_startclrcnt_en1 {
#[doc = "Register `PWM_STARTCLRCNT_EN1` reader"] pub type R = crate :: R < PwmStartclrcntEn1Spec > ;
#[doc = "Register `PWM_STARTCLRCNT_EN1` writer"] pub type W = crate :: W < PwmStartclrcntEn1Spec > ;
#[doc = "Field `pwm_startclrcnt_en_1` reader - Start clear counter enable for group 1"] pub type PwmStartclrcntEn1R = crate :: BitReader ;
#[doc = "Field `pwm_startclrcnt_en_1` writer - Start clear counter enable for group 1"] pub type PwmStartclrcntEn1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Start clear counter enable for group 1"]
#[inline (always)] pub fn pwm_startclrcnt_en_1 (& self) -> PwmStartclrcntEn1R { PwmStartclrcntEn1R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Start clear counter enable for group 1"]
#[inline (always)] pub fn pwm_startclrcnt_en_1 (& mut self) -> PwmStartclrcntEn1W < '_ , PwmStartclrcntEn1Spec > { PwmStartclrcntEn1W :: new (self , 0) } }
#[doc = "PWM group 1 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmStartclrcntEn1Spec ; impl crate :: RegisterSpec for PwmStartclrcntEn1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_startclrcnt_en1::R`](R) reader structure"] impl crate :: Readable for PwmStartclrcntEn1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en1::W`](W) writer structure"] impl crate :: Writable for PwmStartclrcntEn1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_STARTCLRCNT_EN1 to value 0"] impl crate :: Resettable for PwmStartclrcntEn1Spec { } }
#[doc = "PWM_START1 (rw) register accessor: PWM group 1 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start1`] module"]
#[doc (alias = "PWM_START1")] pub type PwmStart1 = crate :: Reg < pwm_start1 :: PwmStart1Spec > ;
#[doc = "PWM group 1 start"] pub mod pwm_start1 {
#[doc = "Register `PWM_START1` reader"] pub type R = crate :: R < PwmStart1Spec > ;
#[doc = "Register `PWM_START1` writer"] pub type W = crate :: W < PwmStart1Spec > ;
#[doc = "Field `pwm_start_1` writer - Start group 1 (self-clearing)"] pub type PwmStart1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Start group 1 (self-clearing)"]
#[inline (always)] pub fn pwm_start_1 (& mut self) -> PwmStart1W < '_ , PwmStart1Spec > { PwmStart1W :: new (self , 0) } }
#[doc = "PWM group 1 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmStart1Spec ; impl crate :: RegisterSpec for PwmStart1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_start1::R`](R) reader structure"] impl crate :: Readable for PwmStart1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_start1::W`](W) writer structure"] impl crate :: Writable for PwmStart1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_START1 to value 0"] impl crate :: Resettable for PwmStart1Spec { } }
#[doc = "PWM_SEL2 (rw) register accessor: PWM group 2 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel2`] module"]
#[doc (alias = "PWM_SEL2")] pub type PwmSel2 = crate :: Reg < pwm_sel2 :: PwmSel2Spec > ;
#[doc = "PWM group 2 select"] pub mod pwm_sel2 {
#[doc = "Register `PWM_SEL2` reader"] pub type R = crate :: R < PwmSel2Spec > ;
#[doc = "Register `PWM_SEL2` writer"] pub type W = crate :: W < PwmSel2Spec > ;
#[doc = "Field `pwm_sel_2` reader - Group 2 PWM select"] pub type PwmSel2R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_sel_2` writer - Group 2 PWM select"] pub type PwmSel2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Group 2 PWM select"]
#[inline (always)] pub fn pwm_sel_2 (& self) -> PwmSel2R { PwmSel2R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Group 2 PWM select"]
#[inline (always)] pub fn pwm_sel_2 (& mut self) -> PwmSel2W < '_ , PwmSel2Spec > { PwmSel2W :: new (self , 0) } }
#[doc = "PWM group 2 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmSel2Spec ; impl crate :: RegisterSpec for PwmSel2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_sel2::R`](R) reader structure"] impl crate :: Readable for PwmSel2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_sel2::W`](W) writer structure"] impl crate :: Writable for PwmSel2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_SEL2 to value 0"] impl crate :: Resettable for PwmSel2Spec { } }
#[doc = "PWM_STARTCLRCNT_EN2 (rw) register accessor: PWM group 2 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en2`] module"]
#[doc (alias = "PWM_STARTCLRCNT_EN2")] pub type PwmStartclrcntEn2 = crate :: Reg < pwm_startclrcnt_en2 :: PwmStartclrcntEn2Spec > ;
#[doc = "PWM group 2 start clear counter enable"] pub mod pwm_startclrcnt_en2 {
#[doc = "Register `PWM_STARTCLRCNT_EN2` reader"] pub type R = crate :: R < PwmStartclrcntEn2Spec > ;
#[doc = "Register `PWM_STARTCLRCNT_EN2` writer"] pub type W = crate :: W < PwmStartclrcntEn2Spec > ;
#[doc = "Field `pwm_startclrcnt_en_2` reader - Start clear counter enable for group 2"] pub type PwmStartclrcntEn2R = crate :: BitReader ;
#[doc = "Field `pwm_startclrcnt_en_2` writer - Start clear counter enable for group 2"] pub type PwmStartclrcntEn2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Start clear counter enable for group 2"]
#[inline (always)] pub fn pwm_startclrcnt_en_2 (& self) -> PwmStartclrcntEn2R { PwmStartclrcntEn2R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Start clear counter enable for group 2"]
#[inline (always)] pub fn pwm_startclrcnt_en_2 (& mut self) -> PwmStartclrcntEn2W < '_ , PwmStartclrcntEn2Spec > { PwmStartclrcntEn2W :: new (self , 0) } }
#[doc = "PWM group 2 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmStartclrcntEn2Spec ; impl crate :: RegisterSpec for PwmStartclrcntEn2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_startclrcnt_en2::R`](R) reader structure"] impl crate :: Readable for PwmStartclrcntEn2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en2::W`](W) writer structure"] impl crate :: Writable for PwmStartclrcntEn2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_STARTCLRCNT_EN2 to value 0"] impl crate :: Resettable for PwmStartclrcntEn2Spec { } }
#[doc = "PWM_START2 (rw) register accessor: PWM group 2 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start2`] module"]
#[doc (alias = "PWM_START2")] pub type PwmStart2 = crate :: Reg < pwm_start2 :: PwmStart2Spec > ;
#[doc = "PWM group 2 start"] pub mod pwm_start2 {
#[doc = "Register `PWM_START2` reader"] pub type R = crate :: R < PwmStart2Spec > ;
#[doc = "Register `PWM_START2` writer"] pub type W = crate :: W < PwmStart2Spec > ;
#[doc = "Field `pwm_start_2` writer - Start group 2 (self-clearing)"] pub type PwmStart2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Start group 2 (self-clearing)"]
#[inline (always)] pub fn pwm_start_2 (& mut self) -> PwmStart2W < '_ , PwmStart2Spec > { PwmStart2W :: new (self , 0) } }
#[doc = "PWM group 2 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmStart2Spec ; impl crate :: RegisterSpec for PwmStart2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_start2::R`](R) reader structure"] impl crate :: Readable for PwmStart2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_start2::W`](W) writer structure"] impl crate :: Writable for PwmStart2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_START2 to value 0"] impl crate :: Resettable for PwmStart2Spec { } }
#[doc = "PWM_SEL3 (rw) register accessor: PWM group 3 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel3`] module"]
#[doc (alias = "PWM_SEL3")] pub type PwmSel3 = crate :: Reg < pwm_sel3 :: PwmSel3Spec > ;
#[doc = "PWM group 3 select"] pub mod pwm_sel3 {
#[doc = "Register `PWM_SEL3` reader"] pub type R = crate :: R < PwmSel3Spec > ;
#[doc = "Register `PWM_SEL3` writer"] pub type W = crate :: W < PwmSel3Spec > ;
#[doc = "Field `pwm_sel_3` reader - Group 3 PWM select"] pub type PwmSel3R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_sel_3` writer - Group 3 PWM select"] pub type PwmSel3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Group 3 PWM select"]
#[inline (always)] pub fn pwm_sel_3 (& self) -> PwmSel3R { PwmSel3R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Group 3 PWM select"]
#[inline (always)] pub fn pwm_sel_3 (& mut self) -> PwmSel3W < '_ , PwmSel3Spec > { PwmSel3W :: new (self , 0) } }
#[doc = "PWM group 3 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmSel3Spec ; impl crate :: RegisterSpec for PwmSel3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_sel3::R`](R) reader structure"] impl crate :: Readable for PwmSel3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_sel3::W`](W) writer structure"] impl crate :: Writable for PwmSel3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_SEL3 to value 0"] impl crate :: Resettable for PwmSel3Spec { } }
#[doc = "PWM_STARTCLRCNT_EN3 (rw) register accessor: PWM group 3 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en3`] module"]
#[doc (alias = "PWM_STARTCLRCNT_EN3")] pub type PwmStartclrcntEn3 = crate :: Reg < pwm_startclrcnt_en3 :: PwmStartclrcntEn3Spec > ;
#[doc = "PWM group 3 start clear counter enable"] pub mod pwm_startclrcnt_en3 {
#[doc = "Register `PWM_STARTCLRCNT_EN3` reader"] pub type R = crate :: R < PwmStartclrcntEn3Spec > ;
#[doc = "Register `PWM_STARTCLRCNT_EN3` writer"] pub type W = crate :: W < PwmStartclrcntEn3Spec > ;
#[doc = "Field `pwm_startclrcnt_en_3` reader - Start clear counter enable for group 3"] pub type PwmStartclrcntEn3R = crate :: BitReader ;
#[doc = "Field `pwm_startclrcnt_en_3` writer - Start clear counter enable for group 3"] pub type PwmStartclrcntEn3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Start clear counter enable for group 3"]
#[inline (always)] pub fn pwm_startclrcnt_en_3 (& self) -> PwmStartclrcntEn3R { PwmStartclrcntEn3R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Start clear counter enable for group 3"]
#[inline (always)] pub fn pwm_startclrcnt_en_3 (& mut self) -> PwmStartclrcntEn3W < '_ , PwmStartclrcntEn3Spec > { PwmStartclrcntEn3W :: new (self , 0) } }
#[doc = "PWM group 3 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmStartclrcntEn3Spec ; impl crate :: RegisterSpec for PwmStartclrcntEn3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_startclrcnt_en3::R`](R) reader structure"] impl crate :: Readable for PwmStartclrcntEn3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en3::W`](W) writer structure"] impl crate :: Writable for PwmStartclrcntEn3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_STARTCLRCNT_EN3 to value 0"] impl crate :: Resettable for PwmStartclrcntEn3Spec { } }
#[doc = "PWM_START3 (rw) register accessor: PWM group 3 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start3`] module"]
#[doc (alias = "PWM_START3")] pub type PwmStart3 = crate :: Reg < pwm_start3 :: PwmStart3Spec > ;
#[doc = "PWM group 3 start"] pub mod pwm_start3 {
#[doc = "Register `PWM_START3` reader"] pub type R = crate :: R < PwmStart3Spec > ;
#[doc = "Register `PWM_START3` writer"] pub type W = crate :: W < PwmStart3Spec > ;
#[doc = "Field `pwm_start_3` writer - Start group 3 (self-clearing)"] pub type PwmStart3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Start group 3 (self-clearing)"]
#[inline (always)] pub fn pwm_start_3 (& mut self) -> PwmStart3W < '_ , PwmStart3Spec > { PwmStart3W :: new (self , 0) } }
#[doc = "PWM group 3 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmStart3Spec ; impl crate :: RegisterSpec for PwmStart3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_start3::R`](R) reader structure"] impl crate :: Readable for PwmStart3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_start3::W`](W) writer structure"] impl crate :: Writable for PwmStart3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_START3 to value 0"] impl crate :: Resettable for PwmStart3Spec { } }
#[doc = "PWM_EN0 (rw) register accessor: PWM0 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en0`] module"]
#[doc (alias = "PWM_EN0")] pub type PwmEn0 = crate :: Reg < pwm_en0 :: PwmEn0Spec > ;
#[doc = "PWM0 enable"] pub mod pwm_en0 {
#[doc = "Register `PWM_EN0` reader"] pub type R = crate :: R < PwmEn0Spec > ;
#[doc = "Register `PWM_EN0` writer"] pub type W = crate :: W < PwmEn0Spec > ;
#[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmEn0 {
#[doc = "0: PWM disabled, output low"] Off = 0 ,
#[doc = "1: PWM enabled"] On = 1 , } impl From < PwmEn0 > for bool {
#[inline (always)] fn from (variant : PwmEn0) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_en_0` reader - PWM0 enable: 0=off; 1=on"] pub type PwmEn0R = crate :: BitReader < PwmEn0 > ; impl PwmEn0R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmEn0 { match self . bits { false => PwmEn0 :: Off , true => PwmEn0 :: On , } }
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn is_off (& self) -> bool { * self == PwmEn0 :: Off }
#[doc = "PWM enabled"]
#[inline (always)] pub fn is_on (& self) -> bool { * self == PwmEn0 :: On } }
#[doc = "Field `pwm_en_0` writer - PWM0 enable: 0=off; 1=on"] pub type PwmEn0W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmEn0 > ; impl < 'a , REG > PwmEn0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn0 :: Off) }
#[doc = "PWM enabled"]
#[inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn0 :: On) } } impl R {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_0 (& self) -> PwmEn0R { PwmEn0R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_0 (& mut self) -> PwmEn0W < '_ , PwmEn0Spec > { PwmEn0W :: new (self , 0) } }
#[doc = "PWM0 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmEn0Spec ; impl crate :: RegisterSpec for PwmEn0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_en0::R`](R) reader structure"] impl crate :: Readable for PwmEn0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_en0::W`](W) writer structure"] impl crate :: Writable for PwmEn0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_EN0 to value 0"] impl crate :: Resettable for PwmEn0Spec { } }
#[doc = "PWM_PORTITY0 (rw) register accessor: PWM0 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity0`] module"]
#[doc (alias = "PWM_PORTITY0")] pub type PwmPortity0 = crate :: Reg < pwm_portity0 :: PwmPortity0Spec > ;
#[doc = "PWM0 polarity"] pub mod pwm_portity0 {
#[doc = "Register `PWM_PORTITY0` reader"] pub type R = crate :: R < PwmPortity0Spec > ;
#[doc = "Register `PWM_PORTITY0` writer"] pub type W = crate :: W < PwmPortity0Spec > ;
#[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmPoarity0 {
#[doc = "0: Normal polarity"] Normal = 0 ,
#[doc = "1: Inverted polarity"] Inverted = 1 , } impl From < PwmPoarity0 > for bool {
#[inline (always)] fn from (variant : PwmPoarity0) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_poarity_0` reader - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity0R = crate :: BitReader < PwmPoarity0 > ; impl PwmPoarity0R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmPoarity0 { match self . bits { false => PwmPoarity0 :: Normal , true => PwmPoarity0 :: Inverted , } }
#[doc = "Normal polarity"]
#[inline (always)] pub fn is_normal (& self) -> bool { * self == PwmPoarity0 :: Normal }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn is_inverted (& self) -> bool { * self == PwmPoarity0 :: Inverted } }
#[doc = "Field `pwm_poarity_0` writer - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity0W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmPoarity0 > ; impl < 'a , REG > PwmPoarity0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "Normal polarity"]
#[inline (always)] pub fn normal (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity0 :: Normal) }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn inverted (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity0 :: Inverted) } } impl R {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_0 (& self) -> PwmPoarity0R { PwmPoarity0R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_0 (& mut self) -> PwmPoarity0W < '_ , PwmPortity0Spec > { PwmPoarity0W :: new (self , 0) } }
#[doc = "PWM0 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPortity0Spec ; impl crate :: RegisterSpec for PwmPortity0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_portity0::R`](R) reader structure"] impl crate :: Readable for PwmPortity0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_portity0::W`](W) writer structure"] impl crate :: Writable for PwmPortity0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PORTITY0 to value 0"] impl crate :: Resettable for PwmPortity0Spec { } }
#[doc = "PWM_OEN_CFG0 (rw) register accessor: PWM0 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg0`] module"]
#[doc (alias = "PWM_OEN_CFG0")] pub type PwmOenCfg0 = crate :: Reg < pwm_oen_cfg0 :: PwmOenCfg0Spec > ;
#[doc = "PWM0 high-impedance config"] pub mod pwm_oen_cfg0 {
#[doc = "Register `PWM_OEN_CFG0` reader"] pub type R = crate :: R < PwmOenCfg0Spec > ;
#[doc = "Register `PWM_OEN_CFG0` writer"] pub type W = crate :: W < PwmOenCfg0Spec > ;
#[doc = "Field `pwm_oen_cfg_0` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg0R = crate :: BitReader ;
#[doc = "Field `pwm_oen_cfg_0` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_0 (& self) -> PwmOenCfg0R { PwmOenCfg0R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_0 (& mut self) -> PwmOenCfg0W < '_ , PwmOenCfg0Spec > { PwmOenCfg0W :: new (self , 0) } }
#[doc = "PWM0 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOenCfg0Spec ; impl crate :: RegisterSpec for PwmOenCfg0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_oen_cfg0::R`](R) reader structure"] impl crate :: Readable for PwmOenCfg0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg0::W`](W) writer structure"] impl crate :: Writable for PwmOenCfg0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OEN_CFG0 to value 0"] impl crate :: Resettable for PwmOenCfg0Spec { } }
#[doc = "PWM_OFFSET_L0 (rw) register accessor: PWM0 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l0`] module"]
#[doc (alias = "PWM_OFFSET_L0")] pub type PwmOffsetL0 = crate :: Reg < pwm_offset_l0 :: PwmOffsetL0Spec > ;
#[doc = "PWM0 phase offset low 16 bits"] pub mod pwm_offset_l0 {
#[doc = "Register `PWM_OFFSET_L0` reader"] pub type R = crate :: R < PwmOffsetL0Spec > ;
#[doc = "Register `PWM_OFFSET_L0` writer"] pub type W = crate :: W < PwmOffsetL0Spec > ;
#[doc = "Field `pwm_offset_l_0` reader - PWM0 phase offset low 16 bits"] pub type PwmOffsetL0R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_l_0` writer - PWM0 phase offset low 16 bits"] pub type PwmOffsetL0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_0 (& self) -> PwmOffsetL0R { PwmOffsetL0R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_0 (& mut self) -> PwmOffsetL0W < '_ , PwmOffsetL0Spec > { PwmOffsetL0W :: new (self , 0) } }
#[doc = "PWM0 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetL0Spec ; impl crate :: RegisterSpec for PwmOffsetL0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_l0::R`](R) reader structure"] impl crate :: Readable for PwmOffsetL0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_l0::W`](W) writer structure"] impl crate :: Writable for PwmOffsetL0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_L0 to value 0"] impl crate :: Resettable for PwmOffsetL0Spec { } }
#[doc = "PWM_OFFSET_H0 (rw) register accessor: PWM0 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h0`] module"]
#[doc (alias = "PWM_OFFSET_H0")] pub type PwmOffsetH0 = crate :: Reg < pwm_offset_h0 :: PwmOffsetH0Spec > ;
#[doc = "PWM0 phase offset high 16 bits"] pub mod pwm_offset_h0 {
#[doc = "Register `PWM_OFFSET_H0` reader"] pub type R = crate :: R < PwmOffsetH0Spec > ;
#[doc = "Register `PWM_OFFSET_H0` writer"] pub type W = crate :: W < PwmOffsetH0Spec > ;
#[doc = "Field `pwm_offset_h_0` reader - PWM0 phase offset high 16 bits"] pub type PwmOffsetH0R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_h_0` writer - PWM0 phase offset high 16 bits"] pub type PwmOffsetH0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_0 (& self) -> PwmOffsetH0R { PwmOffsetH0R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_0 (& mut self) -> PwmOffsetH0W < '_ , PwmOffsetH0Spec > { PwmOffsetH0W :: new (self , 0) } }
#[doc = "PWM0 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetH0Spec ; impl crate :: RegisterSpec for PwmOffsetH0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_h0::R`](R) reader structure"] impl crate :: Readable for PwmOffsetH0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_h0::W`](W) writer structure"] impl crate :: Writable for PwmOffsetH0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_H0 to value 0"] impl crate :: Resettable for PwmOffsetH0Spec { } }
#[doc = "PWM_FREQ_L0 (rw) register accessor: PWM0 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l0`] module"]
#[doc (alias = "PWM_FREQ_L0")] pub type PwmFreqL0 = crate :: Reg < pwm_freq_l0 :: PwmFreqL0Spec > ;
#[doc = "PWM0 frequency low 16 bits"] pub mod pwm_freq_l0 {
#[doc = "Register `PWM_FREQ_L0` reader"] pub type R = crate :: R < PwmFreqL0Spec > ;
#[doc = "Register `PWM_FREQ_L0` writer"] pub type W = crate :: W < PwmFreqL0Spec > ;
#[doc = "Field `pwm_freq_l_0` reader - PWM0 clock divider low 16 bits"] pub type PwmFreqL0R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_l_0` writer - PWM0 clock divider low 16 bits"] pub type PwmFreqL0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_0 (& self) -> PwmFreqL0R { PwmFreqL0R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_0 (& mut self) -> PwmFreqL0W < '_ , PwmFreqL0Spec > { PwmFreqL0W :: new (self , 0) } }
#[doc = "PWM0 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqL0Spec ; impl crate :: RegisterSpec for PwmFreqL0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_l0::R`](R) reader structure"] impl crate :: Readable for PwmFreqL0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_l0::W`](W) writer structure"] impl crate :: Writable for PwmFreqL0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_L0 to value 0"] impl crate :: Resettable for PwmFreqL0Spec { } }
#[doc = "PWM_FREQ_H0 (rw) register accessor: PWM0 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h0`] module"]
#[doc (alias = "PWM_FREQ_H0")] pub type PwmFreqH0 = crate :: Reg < pwm_freq_h0 :: PwmFreqH0Spec > ;
#[doc = "PWM0 frequency high 16 bits"] pub mod pwm_freq_h0 {
#[doc = "Register `PWM_FREQ_H0` reader"] pub type R = crate :: R < PwmFreqH0Spec > ;
#[doc = "Register `PWM_FREQ_H0` writer"] pub type W = crate :: W < PwmFreqH0Spec > ;
#[doc = "Field `pwm_freq_h_0` reader - PWM0 clock divider high 16 bits"] pub type PwmFreqH0R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_h_0` writer - PWM0 clock divider high 16 bits"] pub type PwmFreqH0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_0 (& self) -> PwmFreqH0R { PwmFreqH0R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_0 (& mut self) -> PwmFreqH0W < '_ , PwmFreqH0Spec > { PwmFreqH0W :: new (self , 0) } }
#[doc = "PWM0 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqH0Spec ; impl crate :: RegisterSpec for PwmFreqH0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_h0::R`](R) reader structure"] impl crate :: Readable for PwmFreqH0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_h0::W`](W) writer structure"] impl crate :: Writable for PwmFreqH0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_H0 to value 0"] impl crate :: Resettable for PwmFreqH0Spec { } }
#[doc = "PWM_DUTY_L0 (rw) register accessor: PWM0 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l0`] module"]
#[doc (alias = "PWM_DUTY_L0")] pub type PwmDutyL0 = crate :: Reg < pwm_duty_l0 :: PwmDutyL0Spec > ;
#[doc = "PWM0 duty cycle low 16 bits"] pub mod pwm_duty_l0 {
#[doc = "Register `PWM_DUTY_L0` reader"] pub type R = crate :: R < PwmDutyL0Spec > ;
#[doc = "Register `PWM_DUTY_L0` writer"] pub type W = crate :: W < PwmDutyL0Spec > ;
#[doc = "Field `pwm_duty_l_0` reader - PWM0 duty cycle low 16 bits"] pub type PwmDutyL0R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_l_0` writer - PWM0 duty cycle low 16 bits"] pub type PwmDutyL0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_0 (& self) -> PwmDutyL0R { PwmDutyL0R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_0 (& mut self) -> PwmDutyL0W < '_ , PwmDutyL0Spec > { PwmDutyL0W :: new (self , 0) } }
#[doc = "PWM0 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyL0Spec ; impl crate :: RegisterSpec for PwmDutyL0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_l0::R`](R) reader structure"] impl crate :: Readable for PwmDutyL0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_l0::W`](W) writer structure"] impl crate :: Writable for PwmDutyL0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_L0 to value 0"] impl crate :: Resettable for PwmDutyL0Spec { } }
#[doc = "PWM_DUTY_H0 (rw) register accessor: PWM0 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h0`] module"]
#[doc (alias = "PWM_DUTY_H0")] pub type PwmDutyH0 = crate :: Reg < pwm_duty_h0 :: PwmDutyH0Spec > ;
#[doc = "PWM0 duty cycle high 16 bits"] pub mod pwm_duty_h0 {
#[doc = "Register `PWM_DUTY_H0` reader"] pub type R = crate :: R < PwmDutyH0Spec > ;
#[doc = "Register `PWM_DUTY_H0` writer"] pub type W = crate :: W < PwmDutyH0Spec > ;
#[doc = "Field `pwm_duty_h_0` reader - PWM0 duty cycle high 16 bits"] pub type PwmDutyH0R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_h_0` writer - PWM0 duty cycle high 16 bits"] pub type PwmDutyH0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_0 (& self) -> PwmDutyH0R { PwmDutyH0R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_0 (& mut self) -> PwmDutyH0W < '_ , PwmDutyH0Spec > { PwmDutyH0W :: new (self , 0) } }
#[doc = "PWM0 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyH0Spec ; impl crate :: RegisterSpec for PwmDutyH0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_h0::R`](R) reader structure"] impl crate :: Readable for PwmDutyH0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_h0::W`](W) writer structure"] impl crate :: Writable for PwmDutyH0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_H0 to value 0"] impl crate :: Resettable for PwmDutyH0Spec { } }
#[doc = "PWM_PERIODLOAD_FLAG0 (rw) register accessor: PWM0 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag0`] module"]
#[doc (alias = "PWM_PERIODLOAD_FLAG0")] pub type PwmPeriodloadFlag0 = crate :: Reg < pwm_periodload_flag0 :: PwmPeriodloadFlag0Spec > ;
#[doc = "PWM0 period load flag"] pub mod pwm_periodload_flag0 {
#[doc = "Register `PWM_PERIODLOAD_FLAG0` reader"] pub type R = crate :: R < PwmPeriodloadFlag0Spec > ;
#[doc = "Register `PWM_PERIODLOAD_FLAG0` writer"] pub type W = crate :: W < PwmPeriodloadFlag0Spec > ;
#[doc = "Field `pwm_periodload_flag_0` reader - Period load complete flag"] pub type PwmPeriodloadFlag0R = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Period load complete flag"]
#[inline (always)] pub fn pwm_periodload_flag_0 (& self) -> PwmPeriodloadFlag0R { PwmPeriodloadFlag0R :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "PWM0 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodloadFlag0Spec ; impl crate :: RegisterSpec for PwmPeriodloadFlag0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodload_flag0::R`](R) reader structure"] impl crate :: Readable for PwmPeriodloadFlag0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag0::W`](W) writer structure"] impl crate :: Writable for PwmPeriodloadFlag0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG0 to value 0"] impl crate :: Resettable for PwmPeriodloadFlag0Spec { } }
#[doc = "PWM_PERIOD_VAL0 (rw) register accessor: PWM0 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val0`] module"]
#[doc (alias = "PWM_PERIOD_VAL0")] pub type PwmPeriodVal0 = crate :: Reg < pwm_period_val0 :: PwmPeriodVal0Spec > ;
#[doc = "PWM0 pulse count value"] pub mod pwm_period_val0 {
#[doc = "Register `PWM_PERIOD_VAL0` reader"] pub type R = crate :: R < PwmPeriodVal0Spec > ;
#[doc = "Register `PWM_PERIOD_VAL0` writer"] pub type W = crate :: W < PwmPeriodVal0Spec > ;
#[doc = "Field `pwm_period_val_0` reader - Pulse count for stepping mode"] pub type PwmPeriodVal0R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_period_val_0` writer - Pulse count for stepping mode"] pub type PwmPeriodVal0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_0 (& self) -> PwmPeriodVal0R { PwmPeriodVal0R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_0 (& mut self) -> PwmPeriodVal0W < '_ , PwmPeriodVal0Spec > { PwmPeriodVal0W :: new (self , 0) } }
#[doc = "PWM0 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodVal0Spec ; impl crate :: RegisterSpec for PwmPeriodVal0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_period_val0::R`](R) reader structure"] impl crate :: Readable for PwmPeriodVal0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_period_val0::W`](W) writer structure"] impl crate :: Writable for PwmPeriodVal0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIOD_VAL0 to value 0"] impl crate :: Resettable for PwmPeriodVal0Spec { } }
#[doc = "PWM_PERIODCNT0 (rw) register accessor: PWM0 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt0`] module"]
#[doc (alias = "PWM_PERIODCNT0")] pub type PwmPeriodcnt0 = crate :: Reg < pwm_periodcnt0 :: PwmPeriodcnt0Spec > ;
#[doc = "PWM0 pulse count current value"] pub mod pwm_periodcnt0 {
#[doc = "Register `PWM_PERIODCNT0` reader"] pub type R = crate :: R < PwmPeriodcnt0Spec > ;
#[doc = "Register `PWM_PERIODCNT0` writer"] pub type W = crate :: W < PwmPeriodcnt0Spec > ;
#[doc = "Field `pwm_periodcnt_0` reader - Current pulse count"] pub type PwmPeriodcnt0R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Current pulse count"]
#[inline (always)] pub fn pwm_periodcnt_0 (& self) -> PwmPeriodcnt0R { PwmPeriodcnt0R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "PWM0 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodcnt0Spec ; impl crate :: RegisterSpec for PwmPeriodcnt0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodcnt0::R`](R) reader structure"] impl crate :: Readable for PwmPeriodcnt0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodcnt0::W`](W) writer structure"] impl crate :: Writable for PwmPeriodcnt0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODCNT0 to value 0"] impl crate :: Resettable for PwmPeriodcnt0Spec { } }
#[doc = "PWM_EN1 (rw) register accessor: PWM1 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en1`] module"]
#[doc (alias = "PWM_EN1")] pub type PwmEn1 = crate :: Reg < pwm_en1 :: PwmEn1Spec > ;
#[doc = "PWM1 enable"] pub mod pwm_en1 {
#[doc = "Register `PWM_EN1` reader"] pub type R = crate :: R < PwmEn1Spec > ;
#[doc = "Register `PWM_EN1` writer"] pub type W = crate :: W < PwmEn1Spec > ;
#[doc = "Field `pwm_en_1` reader - PWM1 enable"] pub type PwmEn1R = crate :: BitReader ;
#[doc = "Field `pwm_en_1` writer - PWM1 enable"] pub type PwmEn1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - PWM1 enable"]
#[inline (always)] pub fn pwm_en_1 (& self) -> PwmEn1R { PwmEn1R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM1 enable"]
#[inline (always)] pub fn pwm_en_1 (& mut self) -> PwmEn1W < '_ , PwmEn1Spec > { PwmEn1W :: new (self , 0) } }
#[doc = "PWM1 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmEn1Spec ; impl crate :: RegisterSpec for PwmEn1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_en1::R`](R) reader structure"] impl crate :: Readable for PwmEn1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_en1::W`](W) writer structure"] impl crate :: Writable for PwmEn1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_EN1 to value 0"] impl crate :: Resettable for PwmEn1Spec { } }
#[doc = "PWM_PORTITY1 (rw) register accessor: PWM1 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity1`] module"]
#[doc (alias = "PWM_PORTITY1")] pub type PwmPortity1 = crate :: Reg < pwm_portity1 :: PwmPortity1Spec > ;
#[doc = "PWM1 polarity"] pub mod pwm_portity1 {
#[doc = "Register `PWM_PORTITY1` reader"] pub type R = crate :: R < PwmPortity1Spec > ;
#[doc = "Register `PWM_PORTITY1` writer"] pub type W = crate :: W < PwmPortity1Spec > ;
#[doc = "Field `pwm_poarity_1` reader - PWM1 polarity"] pub type PwmPoarity1R = crate :: BitReader ;
#[doc = "Field `pwm_poarity_1` writer - PWM1 polarity"] pub type PwmPoarity1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - PWM1 polarity"]
#[inline (always)] pub fn pwm_poarity_1 (& self) -> PwmPoarity1R { PwmPoarity1R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM1 polarity"]
#[inline (always)] pub fn pwm_poarity_1 (& mut self) -> PwmPoarity1W < '_ , PwmPortity1Spec > { PwmPoarity1W :: new (self , 0) } }
#[doc = "PWM1 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPortity1Spec ; impl crate :: RegisterSpec for PwmPortity1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_portity1::R`](R) reader structure"] impl crate :: Readable for PwmPortity1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_portity1::W`](W) writer structure"] impl crate :: Writable for PwmPortity1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PORTITY1 to value 0"] impl crate :: Resettable for PwmPortity1Spec { } }
#[doc = "PWM_OEN_CFG1 (rw) register accessor: PWM1 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg1`] module"]
#[doc (alias = "PWM_OEN_CFG1")] pub type PwmOenCfg1 = crate :: Reg < pwm_oen_cfg1 :: PwmOenCfg1Spec > ;
#[doc = "PWM1 high-impedance config"] pub mod pwm_oen_cfg1 {
#[doc = "Register `PWM_OEN_CFG1` reader"] pub type R = crate :: R < PwmOenCfg1Spec > ;
#[doc = "Register `PWM_OEN_CFG1` writer"] pub type W = crate :: W < PwmOenCfg1Spec > ;
#[doc = "Field `pwm_oen_cfg_1` reader - PWM1 high-Z enable"] pub type PwmOenCfg1R = crate :: BitReader ;
#[doc = "Field `pwm_oen_cfg_1` writer - PWM1 high-Z enable"] pub type PwmOenCfg1W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - PWM1 high-Z enable"]
#[inline (always)] pub fn pwm_oen_cfg_1 (& self) -> PwmOenCfg1R { PwmOenCfg1R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM1 high-Z enable"]
#[inline (always)] pub fn pwm_oen_cfg_1 (& mut self) -> PwmOenCfg1W < '_ , PwmOenCfg1Spec > { PwmOenCfg1W :: new (self , 0) } }
#[doc = "PWM1 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOenCfg1Spec ; impl crate :: RegisterSpec for PwmOenCfg1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_oen_cfg1::R`](R) reader structure"] impl crate :: Readable for PwmOenCfg1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg1::W`](W) writer structure"] impl crate :: Writable for PwmOenCfg1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OEN_CFG1 to value 0"] impl crate :: Resettable for PwmOenCfg1Spec { } }
#[doc = "PWM_OFFSET_L1 (rw) register accessor: PWM1 phase offset low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l1`] module"]
#[doc (alias = "PWM_OFFSET_L1")] pub type PwmOffsetL1 = crate :: Reg < pwm_offset_l1 :: PwmOffsetL1Spec > ;
#[doc = "PWM1 phase offset low"] pub mod pwm_offset_l1 {
#[doc = "Register `PWM_OFFSET_L1` reader"] pub type R = crate :: R < PwmOffsetL1Spec > ;
#[doc = "Register `PWM_OFFSET_L1` writer"] pub type W = crate :: W < PwmOffsetL1Spec > ;
#[doc = "Field `pwm_offset_l_1` reader - PWM1 phase offset low 16 bits"] pub type PwmOffsetL1R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_l_1` writer - PWM1 phase offset low 16 bits"] pub type PwmOffsetL1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM1 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_1 (& self) -> PwmOffsetL1R { PwmOffsetL1R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM1 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_1 (& mut self) -> PwmOffsetL1W < '_ , PwmOffsetL1Spec > { PwmOffsetL1W :: new (self , 0) } }
#[doc = "PWM1 phase offset low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetL1Spec ; impl crate :: RegisterSpec for PwmOffsetL1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_l1::R`](R) reader structure"] impl crate :: Readable for PwmOffsetL1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_l1::W`](W) writer structure"] impl crate :: Writable for PwmOffsetL1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_L1 to value 0"] impl crate :: Resettable for PwmOffsetL1Spec { } }
#[doc = "PWM_OFFSET_H1 (rw) register accessor: PWM1 phase offset high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h1`] module"]
#[doc (alias = "PWM_OFFSET_H1")] pub type PwmOffsetH1 = crate :: Reg < pwm_offset_h1 :: PwmOffsetH1Spec > ;
#[doc = "PWM1 phase offset high"] pub mod pwm_offset_h1 {
#[doc = "Register `PWM_OFFSET_H1` reader"] pub type R = crate :: R < PwmOffsetH1Spec > ;
#[doc = "Register `PWM_OFFSET_H1` writer"] pub type W = crate :: W < PwmOffsetH1Spec > ;
#[doc = "Field `pwm_offset_h_1` reader - PWM1 phase offset high 16 bits"] pub type PwmOffsetH1R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_h_1` writer - PWM1 phase offset high 16 bits"] pub type PwmOffsetH1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM1 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_1 (& self) -> PwmOffsetH1R { PwmOffsetH1R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM1 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_1 (& mut self) -> PwmOffsetH1W < '_ , PwmOffsetH1Spec > { PwmOffsetH1W :: new (self , 0) } }
#[doc = "PWM1 phase offset high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetH1Spec ; impl crate :: RegisterSpec for PwmOffsetH1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_h1::R`](R) reader structure"] impl crate :: Readable for PwmOffsetH1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_h1::W`](W) writer structure"] impl crate :: Writable for PwmOffsetH1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_H1 to value 0"] impl crate :: Resettable for PwmOffsetH1Spec { } }
#[doc = "PWM_FREQ_L1 (rw) register accessor: PWM1 frequency low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l1`] module"]
#[doc (alias = "PWM_FREQ_L1")] pub type PwmFreqL1 = crate :: Reg < pwm_freq_l1 :: PwmFreqL1Spec > ;
#[doc = "PWM1 frequency low"] pub mod pwm_freq_l1 {
#[doc = "Register `PWM_FREQ_L1` reader"] pub type R = crate :: R < PwmFreqL1Spec > ;
#[doc = "Register `PWM_FREQ_L1` writer"] pub type W = crate :: W < PwmFreqL1Spec > ;
#[doc = "Field `pwm_freq_l_1` reader - PWM1 clock divider low 16 bits"] pub type PwmFreqL1R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_l_1` writer - PWM1 clock divider low 16 bits"] pub type PwmFreqL1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM1 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_1 (& self) -> PwmFreqL1R { PwmFreqL1R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM1 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_1 (& mut self) -> PwmFreqL1W < '_ , PwmFreqL1Spec > { PwmFreqL1W :: new (self , 0) } }
#[doc = "PWM1 frequency low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqL1Spec ; impl crate :: RegisterSpec for PwmFreqL1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_l1::R`](R) reader structure"] impl crate :: Readable for PwmFreqL1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_l1::W`](W) writer structure"] impl crate :: Writable for PwmFreqL1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_L1 to value 0"] impl crate :: Resettable for PwmFreqL1Spec { } }
#[doc = "PWM_FREQ_H1 (rw) register accessor: PWM1 frequency high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h1`] module"]
#[doc (alias = "PWM_FREQ_H1")] pub type PwmFreqH1 = crate :: Reg < pwm_freq_h1 :: PwmFreqH1Spec > ;
#[doc = "PWM1 frequency high"] pub mod pwm_freq_h1 {
#[doc = "Register `PWM_FREQ_H1` reader"] pub type R = crate :: R < PwmFreqH1Spec > ;
#[doc = "Register `PWM_FREQ_H1` writer"] pub type W = crate :: W < PwmFreqH1Spec > ;
#[doc = "Field `pwm_freq_h_1` reader - PWM1 clock divider high 16 bits"] pub type PwmFreqH1R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_h_1` writer - PWM1 clock divider high 16 bits"] pub type PwmFreqH1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM1 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_1 (& self) -> PwmFreqH1R { PwmFreqH1R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM1 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_1 (& mut self) -> PwmFreqH1W < '_ , PwmFreqH1Spec > { PwmFreqH1W :: new (self , 0) } }
#[doc = "PWM1 frequency high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqH1Spec ; impl crate :: RegisterSpec for PwmFreqH1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_h1::R`](R) reader structure"] impl crate :: Readable for PwmFreqH1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_h1::W`](W) writer structure"] impl crate :: Writable for PwmFreqH1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_H1 to value 0"] impl crate :: Resettable for PwmFreqH1Spec { } }
#[doc = "PWM_DUTY_L1 (rw) register accessor: PWM1 duty cycle low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l1`] module"]
#[doc (alias = "PWM_DUTY_L1")] pub type PwmDutyL1 = crate :: Reg < pwm_duty_l1 :: PwmDutyL1Spec > ;
#[doc = "PWM1 duty cycle low"] pub mod pwm_duty_l1 {
#[doc = "Register `PWM_DUTY_L1` reader"] pub type R = crate :: R < PwmDutyL1Spec > ;
#[doc = "Register `PWM_DUTY_L1` writer"] pub type W = crate :: W < PwmDutyL1Spec > ;
#[doc = "Field `pwm_duty_l_1` reader - PWM1 duty low 16 bits"] pub type PwmDutyL1R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_l_1` writer - PWM1 duty low 16 bits"] pub type PwmDutyL1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM1 duty low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_1 (& self) -> PwmDutyL1R { PwmDutyL1R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM1 duty low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_1 (& mut self) -> PwmDutyL1W < '_ , PwmDutyL1Spec > { PwmDutyL1W :: new (self , 0) } }
#[doc = "PWM1 duty cycle low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyL1Spec ; impl crate :: RegisterSpec for PwmDutyL1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_l1::R`](R) reader structure"] impl crate :: Readable for PwmDutyL1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_l1::W`](W) writer structure"] impl crate :: Writable for PwmDutyL1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_L1 to value 0"] impl crate :: Resettable for PwmDutyL1Spec { } }
#[doc = "PWM_DUTY_H1 (rw) register accessor: PWM1 duty cycle high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h1`] module"]
#[doc (alias = "PWM_DUTY_H1")] pub type PwmDutyH1 = crate :: Reg < pwm_duty_h1 :: PwmDutyH1Spec > ;
#[doc = "PWM1 duty cycle high"] pub mod pwm_duty_h1 {
#[doc = "Register `PWM_DUTY_H1` reader"] pub type R = crate :: R < PwmDutyH1Spec > ;
#[doc = "Register `PWM_DUTY_H1` writer"] pub type W = crate :: W < PwmDutyH1Spec > ;
#[doc = "Field `pwm_duty_h_1` reader - PWM1 duty high 16 bits"] pub type PwmDutyH1R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_h_1` writer - PWM1 duty high 16 bits"] pub type PwmDutyH1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM1 duty high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_1 (& self) -> PwmDutyH1R { PwmDutyH1R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM1 duty high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_1 (& mut self) -> PwmDutyH1W < '_ , PwmDutyH1Spec > { PwmDutyH1W :: new (self , 0) } }
#[doc = "PWM1 duty cycle high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyH1Spec ; impl crate :: RegisterSpec for PwmDutyH1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_h1::R`](R) reader structure"] impl crate :: Readable for PwmDutyH1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_h1::W`](W) writer structure"] impl crate :: Writable for PwmDutyH1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_H1 to value 0"] impl crate :: Resettable for PwmDutyH1Spec { } }
#[doc = "PWM_PERIODLOAD_FLAG1 (rw) register accessor: PWM1 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag1`] module"]
#[doc (alias = "PWM_PERIODLOAD_FLAG1")] pub type PwmPeriodloadFlag1 = crate :: Reg < pwm_periodload_flag1 :: PwmPeriodloadFlag1Spec > ;
#[doc = "PWM1 period load flag"] pub mod pwm_periodload_flag1 {
#[doc = "Register `PWM_PERIODLOAD_FLAG1` reader"] pub type R = crate :: R < PwmPeriodloadFlag1Spec > ;
#[doc = "Register `PWM_PERIODLOAD_FLAG1` writer"] pub type W = crate :: W < PwmPeriodloadFlag1Spec > ;
#[doc = "Field `pwm_periodload_flag_1` reader - Period load flag"] pub type PwmPeriodloadFlag1R = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Period load flag"]
#[inline (always)] pub fn pwm_periodload_flag_1 (& self) -> PwmPeriodloadFlag1R { PwmPeriodloadFlag1R :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "PWM1 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodloadFlag1Spec ; impl crate :: RegisterSpec for PwmPeriodloadFlag1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodload_flag1::R`](R) reader structure"] impl crate :: Readable for PwmPeriodloadFlag1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag1::W`](W) writer structure"] impl crate :: Writable for PwmPeriodloadFlag1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG1 to value 0"] impl crate :: Resettable for PwmPeriodloadFlag1Spec { } }
#[doc = "PWM_PERIOD_VAL1 (rw) register accessor: PWM1 pulse count\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val1`] module"]
#[doc (alias = "PWM_PERIOD_VAL1")] pub type PwmPeriodVal1 = crate :: Reg < pwm_period_val1 :: PwmPeriodVal1Spec > ;
#[doc = "PWM1 pulse count"] pub mod pwm_period_val1 {
#[doc = "Register `PWM_PERIOD_VAL1` reader"] pub type R = crate :: R < PwmPeriodVal1Spec > ;
#[doc = "Register `PWM_PERIOD_VAL1` writer"] pub type W = crate :: W < PwmPeriodVal1Spec > ;
#[doc = "Field `pwm_period_val_1` reader - Pulse count"] pub type PwmPeriodVal1R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_period_val_1` writer - Pulse count"] pub type PwmPeriodVal1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Pulse count"]
#[inline (always)] pub fn pwm_period_val_1 (& self) -> PwmPeriodVal1R { PwmPeriodVal1R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Pulse count"]
#[inline (always)] pub fn pwm_period_val_1 (& mut self) -> PwmPeriodVal1W < '_ , PwmPeriodVal1Spec > { PwmPeriodVal1W :: new (self , 0) } }
#[doc = "PWM1 pulse count\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodVal1Spec ; impl crate :: RegisterSpec for PwmPeriodVal1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_period_val1::R`](R) reader structure"] impl crate :: Readable for PwmPeriodVal1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_period_val1::W`](W) writer structure"] impl crate :: Writable for PwmPeriodVal1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIOD_VAL1 to value 0"] impl crate :: Resettable for PwmPeriodVal1Spec { } }
#[doc = "PWM_PERIODCNT1 (rw) register accessor: PWM1 pulse count current\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt1`] module"]
#[doc (alias = "PWM_PERIODCNT1")] pub type PwmPeriodcnt1 = crate :: Reg < pwm_periodcnt1 :: PwmPeriodcnt1Spec > ;
#[doc = "PWM1 pulse count current"] pub mod pwm_periodcnt1 {
#[doc = "Register `PWM_PERIODCNT1` reader"] pub type R = crate :: R < PwmPeriodcnt1Spec > ;
#[doc = "Register `PWM_PERIODCNT1` writer"] pub type W = crate :: W < PwmPeriodcnt1Spec > ;
#[doc = "Field `pwm_periodcnt_1` reader - Current pulse count"] pub type PwmPeriodcnt1R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Current pulse count"]
#[inline (always)] pub fn pwm_periodcnt_1 (& self) -> PwmPeriodcnt1R { PwmPeriodcnt1R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "PWM1 pulse count current\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodcnt1Spec ; impl crate :: RegisterSpec for PwmPeriodcnt1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodcnt1::R`](R) reader structure"] impl crate :: Readable for PwmPeriodcnt1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodcnt1::W`](W) writer structure"] impl crate :: Writable for PwmPeriodcnt1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODCNT1 to value 0"] impl crate :: Resettable for PwmPeriodcnt1Spec { } }
#[doc = "PWM_ABNOR_STATE0 (rw) register accessor: PWM abnormal state register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state0`] module"]
#[doc (alias = "PWM_ABNOR_STATE0")] pub type PwmAbnorState0 = crate :: Reg < pwm_abnor_state0 :: PwmAbnorState0Spec > ;
#[doc = "PWM abnormal state register 0"] pub mod pwm_abnor_state0 {
#[doc = "Register `PWM_ABNOR_STATE0` reader"] pub type R = crate :: R < PwmAbnorState0Spec > ;
#[doc = "Register `PWM_ABNOR_STATE0` writer"] pub type W = crate :: W < PwmAbnorState0Spec > ;
#[doc = "Field `pwm_abnor_state0` reader - Multi-channel config abnormal state, each bit per PWM"] pub type PwmAbnorState0R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Multi-channel config abnormal state, each bit per PWM"]
#[inline (always)] pub fn pwm_abnor_state0 (& self) -> PwmAbnorState0R { PwmAbnorState0R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "PWM abnormal state register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmAbnorState0Spec ; impl crate :: RegisterSpec for PwmAbnorState0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_abnor_state0::R`](R) reader structure"] impl crate :: Readable for PwmAbnorState0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_abnor_state0::W`](W) writer structure"] impl crate :: Writable for PwmAbnorState0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_ABNOR_STATE0 to value 0"] impl crate :: Resettable for PwmAbnorState0Spec { } }
#[doc = "PWM_ABNOR_STATE1 (rw) register accessor: PWM abnormal state register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state1`] module"]
#[doc (alias = "PWM_ABNOR_STATE1")] pub type PwmAbnorState1 = crate :: Reg < pwm_abnor_state1 :: PwmAbnorState1Spec > ;
#[doc = "PWM abnormal state register 1"] pub mod pwm_abnor_state1 {
#[doc = "Register `PWM_ABNOR_STATE1` reader"] pub type R = crate :: R < PwmAbnorState1Spec > ;
#[doc = "Register `PWM_ABNOR_STATE1` writer"] pub type W = crate :: W < PwmAbnorState1Spec > ;
#[doc = "Field `pwm_abnor_state1` reader - Counter config abnormal state, each bit per PWM"] pub type PwmAbnorState1R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Counter config abnormal state, each bit per PWM"]
#[inline (always)] pub fn pwm_abnor_state1 (& self) -> PwmAbnorState1R { PwmAbnorState1R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "PWM abnormal state register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmAbnorState1Spec ; impl crate :: RegisterSpec for PwmAbnorState1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_abnor_state1::R`](R) reader structure"] impl crate :: Readable for PwmAbnorState1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_abnor_state1::W`](W) writer structure"] impl crate :: Writable for PwmAbnorState1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_ABNOR_STATE1 to value 0"] impl crate :: Resettable for PwmAbnorState1Spec { } }
#[doc = "PWM_ABNOR_STATE_CLR0 (rw) register accessor: PWM abnormal state clear 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state_clr0`] module"]
#[doc (alias = "PWM_ABNOR_STATE_CLR0")] pub type PwmAbnorStateClr0 = crate :: Reg < pwm_abnor_state_clr0 :: PwmAbnorStateClr0Spec > ;
#[doc = "PWM abnormal state clear 0"] pub mod pwm_abnor_state_clr0 {
#[doc = "Register `PWM_ABNOR_STATE_CLR0` reader"] pub type R = crate :: R < PwmAbnorStateClr0Spec > ;
#[doc = "Register `PWM_ABNOR_STATE_CLR0` writer"] pub type W = crate :: W < PwmAbnorStateClr0Spec > ;
#[doc = "Field `pwm_abnor_state_clr0` writer - Clear abnormal state 0 (self-clearing)"] pub type PwmAbnorStateClr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl W {
#[doc = "Bits 0:15 - Clear abnormal state 0 (self-clearing)"]
#[inline (always)] pub fn pwm_abnor_state_clr0 (& mut self) -> PwmAbnorStateClr0W < '_ , PwmAbnorStateClr0Spec > { PwmAbnorStateClr0W :: new (self , 0) } }
#[doc = "PWM abnormal state clear 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmAbnorStateClr0Spec ; impl crate :: RegisterSpec for PwmAbnorStateClr0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_abnor_state_clr0::R`](R) reader structure"] impl crate :: Readable for PwmAbnorStateClr0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_abnor_state_clr0::W`](W) writer structure"] impl crate :: Writable for PwmAbnorStateClr0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_ABNOR_STATE_CLR0 to value 0"] impl crate :: Resettable for PwmAbnorStateClr0Spec { } }
#[doc = "PWM_ABNOR_STATE_CLR1 (rw) register accessor: PWM abnormal state clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state_clr1`] module"]
#[doc (alias = "PWM_ABNOR_STATE_CLR1")] pub type PwmAbnorStateClr1 = crate :: Reg < pwm_abnor_state_clr1 :: PwmAbnorStateClr1Spec > ;
#[doc = "PWM abnormal state clear 1"] pub mod pwm_abnor_state_clr1 {
#[doc = "Register `PWM_ABNOR_STATE_CLR1` reader"] pub type R = crate :: R < PwmAbnorStateClr1Spec > ;
#[doc = "Register `PWM_ABNOR_STATE_CLR1` writer"] pub type W = crate :: W < PwmAbnorStateClr1Spec > ;
#[doc = "Field `pwm_abnor_state_clr1` writer - Clear abnormal state 1 (self-clearing)"] pub type PwmAbnorStateClr1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl W {
#[doc = "Bits 0:15 - Clear abnormal state 1 (self-clearing)"]
#[inline (always)] pub fn pwm_abnor_state_clr1 (& mut self) -> PwmAbnorStateClr1W < '_ , PwmAbnorStateClr1Spec > { PwmAbnorStateClr1W :: new (self , 0) } }
#[doc = "PWM abnormal state clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmAbnorStateClr1Spec ; impl crate :: RegisterSpec for PwmAbnorStateClr1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_abnor_state_clr1::R`](R) reader structure"] impl crate :: Readable for PwmAbnorStateClr1Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_abnor_state_clr1::W`](W) writer structure"] impl crate :: Writable for PwmAbnorStateClr1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_ABNOR_STATE_CLR1 to value 0"] impl crate :: Resettable for PwmAbnorStateClr1Spec { } }
#[doc = "PWM_INT_MASK (rw) register accessor: PWM interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_int_mask`] module"]
#[doc (alias = "PWM_INT_MASK")] pub type PwmIntMask = crate :: Reg < pwm_int_mask :: PwmIntMaskSpec > ;
#[doc = "PWM interrupt mask"] pub mod pwm_int_mask {
#[doc = "Register `PWM_INT_MASK` reader"] pub type R = crate :: R < PwmIntMaskSpec > ;
#[doc = "Register `PWM_INT_MASK` writer"] pub type W = crate :: W < PwmIntMaskSpec > ;
#[doc = "Field `pwm_int_mask` reader - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"] pub type PwmIntMaskR = crate :: FieldReader ;
#[doc = "Field `pwm_int_mask` writer - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"] pub type PwmIntMaskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R {
#[doc = "Bits 0:1 - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
#[inline (always)] pub fn pwm_int_mask (& self) -> PwmIntMaskR { PwmIntMaskR :: new ((self . bits & 3) as u8) } } impl W {
#[doc = "Bits 0:1 - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
#[inline (always)] pub fn pwm_int_mask (& mut self) -> PwmIntMaskW < '_ , PwmIntMaskSpec > { PwmIntMaskW :: new (self , 0) } }
#[doc = "PWM interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmIntMaskSpec ; impl crate :: RegisterSpec for PwmIntMaskSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_int_mask::R`](R) reader structure"] impl crate :: Readable for PwmIntMaskSpec { }
#[doc = "`write(|w| ..)` method takes [`pwm_int_mask::W`](W) writer structure"] impl crate :: Writable for PwmIntMaskSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_INT_MASK to value 0"] impl crate :: Resettable for PwmIntMaskSpec { } }
#[doc = "PWM_DMA_EN (rw) register accessor: PWM DMA enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_dma_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_dma_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_dma_en`] module"]
#[doc (alias = "PWM_DMA_EN")] pub type PwmDmaEn = crate :: Reg < pwm_dma_en :: PwmDmaEnSpec > ;
#[doc = "PWM DMA enable"] pub mod pwm_dma_en {
#[doc = "Register `PWM_DMA_EN` reader"] pub type R = crate :: R < PwmDmaEnSpec > ;
#[doc = "Register `PWM_DMA_EN` writer"] pub type W = crate :: W < PwmDmaEnSpec > ;
#[doc = "Field `pwm_dma_en` reader - DMA enable: 0=disabled; 1=enabled"] pub type PwmDmaEnR = crate :: BitReader ;
#[doc = "Field `pwm_dma_en` writer - DMA enable: 0=disabled; 1=enabled"] pub type PwmDmaEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - DMA enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn pwm_dma_en (& self) -> PwmDmaEnR { PwmDmaEnR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - DMA enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn pwm_dma_en (& mut self) -> PwmDmaEnW < '_ , PwmDmaEnSpec > { PwmDmaEnW :: new (self , 0) } }
#[doc = "PWM DMA enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_dma_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_dma_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDmaEnSpec ; impl crate :: RegisterSpec for PwmDmaEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_dma_en::R`](R) reader structure"] impl crate :: Readable for PwmDmaEnSpec { }
#[doc = "`write(|w| ..)` method takes [`pwm_dma_en::W`](W) writer structure"] impl crate :: Writable for PwmDmaEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DMA_EN to value 0"] impl crate :: Resettable for PwmDmaEnSpec { } }
#[doc = "PWM_CFG_INT_CLR0 (rw) register accessor: PWM stepping cycle end interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_cfg_int_clr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_cfg_int_clr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_cfg_int_clr0`] module"]
#[doc (alias = "PWM_CFG_INT_CLR0")] pub type PwmCfgIntClr0 = crate :: Reg < pwm_cfg_int_clr0 :: PwmCfgIntClr0Spec > ;
#[doc = "PWM stepping cycle end interrupt clear"] pub mod pwm_cfg_int_clr0 {
#[doc = "Register `PWM_CFG_INT_CLR0` reader"] pub type R = crate :: R < PwmCfgIntClr0Spec > ;
#[doc = "Register `PWM_CFG_INT_CLR0` writer"] pub type W = crate :: W < PwmCfgIntClr0Spec > ;
#[doc = "Field `pwm_cfg_int_clr0` writer - Stepping cycle end interrupt clear (self-clearing)"] pub type PwmCfgIntClr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl W {
#[doc = "Bits 0:15 - Stepping cycle end interrupt clear (self-clearing)"]
#[inline (always)] pub fn pwm_cfg_int_clr0 (& mut self) -> PwmCfgIntClr0W < '_ , PwmCfgIntClr0Spec > { PwmCfgIntClr0W :: new (self , 0) } }
#[doc = "PWM stepping cycle end interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_cfg_int_clr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_cfg_int_clr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmCfgIntClr0Spec ; impl crate :: RegisterSpec for PwmCfgIntClr0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_cfg_int_clr0::R`](R) reader structure"] impl crate :: Readable for PwmCfgIntClr0Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_cfg_int_clr0::W`](W) writer structure"] impl crate :: Writable for PwmCfgIntClr0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_CFG_INT_CLR0 to value 0"] impl crate :: Resettable for PwmCfgIntClr0Spec { } }
#[doc = "PWM_EN2 (rw) register accessor: PWM2 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en2`] module"]
#[doc (alias = "PWM_EN2")] pub type PwmEn2 = crate :: Reg < pwm_en2 :: PwmEn2Spec > ;
#[doc = "PWM2 enable"] pub mod pwm_en2 {
#[doc = "Register `PWM_EN2` reader"] pub type R = crate :: R < PwmEn2Spec > ;
#[doc = "Register `PWM_EN2` writer"] pub type W = crate :: W < PwmEn2Spec > ;
#[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmEn2 {
#[doc = "0: PWM disabled, output low"] Off = 0 ,
#[doc = "1: PWM enabled"] On = 1 , } impl From < PwmEn2 > for bool {
#[inline (always)] fn from (variant : PwmEn2) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_en_2` reader - PWM0 enable: 0=off; 1=on"] pub type PwmEn2R = crate :: BitReader < PwmEn2 > ; impl PwmEn2R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmEn2 { match self . bits { false => PwmEn2 :: Off , true => PwmEn2 :: On , } }
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn is_off (& self) -> bool { * self == PwmEn2 :: Off }
#[doc = "PWM enabled"]
#[inline (always)] pub fn is_on (& self) -> bool { * self == PwmEn2 :: On } }
#[doc = "Field `pwm_en_2` writer - PWM0 enable: 0=off; 1=on"] pub type PwmEn2W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmEn2 > ; impl < 'a , REG > PwmEn2W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn2 :: Off) }
#[doc = "PWM enabled"]
#[inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn2 :: On) } } impl R {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_2 (& self) -> PwmEn2R { PwmEn2R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_2 (& mut self) -> PwmEn2W < '_ , PwmEn2Spec > { PwmEn2W :: new (self , 0) } }
#[doc = "PWM2 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmEn2Spec ; impl crate :: RegisterSpec for PwmEn2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_en2::R`](R) reader structure"] impl crate :: Readable for PwmEn2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_en2::W`](W) writer structure"] impl crate :: Writable for PwmEn2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_EN2 to value 0"] impl crate :: Resettable for PwmEn2Spec { } }
#[doc = "PWM_PORTITY2 (rw) register accessor: PWM2 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity2`] module"]
#[doc (alias = "PWM_PORTITY2")] pub type PwmPortity2 = crate :: Reg < pwm_portity2 :: PwmPortity2Spec > ;
#[doc = "PWM2 polarity"] pub mod pwm_portity2 {
#[doc = "Register `PWM_PORTITY2` reader"] pub type R = crate :: R < PwmPortity2Spec > ;
#[doc = "Register `PWM_PORTITY2` writer"] pub type W = crate :: W < PwmPortity2Spec > ;
#[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmPoarity2 {
#[doc = "0: Normal polarity"] Normal = 0 ,
#[doc = "1: Inverted polarity"] Inverted = 1 , } impl From < PwmPoarity2 > for bool {
#[inline (always)] fn from (variant : PwmPoarity2) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_poarity_2` reader - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity2R = crate :: BitReader < PwmPoarity2 > ; impl PwmPoarity2R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmPoarity2 { match self . bits { false => PwmPoarity2 :: Normal , true => PwmPoarity2 :: Inverted , } }
#[doc = "Normal polarity"]
#[inline (always)] pub fn is_normal (& self) -> bool { * self == PwmPoarity2 :: Normal }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn is_inverted (& self) -> bool { * self == PwmPoarity2 :: Inverted } }
#[doc = "Field `pwm_poarity_2` writer - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity2W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmPoarity2 > ; impl < 'a , REG > PwmPoarity2W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "Normal polarity"]
#[inline (always)] pub fn normal (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity2 :: Normal) }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn inverted (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity2 :: Inverted) } } impl R {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_2 (& self) -> PwmPoarity2R { PwmPoarity2R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_2 (& mut self) -> PwmPoarity2W < '_ , PwmPortity2Spec > { PwmPoarity2W :: new (self , 0) } }
#[doc = "PWM2 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPortity2Spec ; impl crate :: RegisterSpec for PwmPortity2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_portity2::R`](R) reader structure"] impl crate :: Readable for PwmPortity2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_portity2::W`](W) writer structure"] impl crate :: Writable for PwmPortity2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PORTITY2 to value 0"] impl crate :: Resettable for PwmPortity2Spec { } }
#[doc = "PWM_OEN_CFG2 (rw) register accessor: PWM2 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg2`] module"]
#[doc (alias = "PWM_OEN_CFG2")] pub type PwmOenCfg2 = crate :: Reg < pwm_oen_cfg2 :: PwmOenCfg2Spec > ;
#[doc = "PWM2 high-impedance config"] pub mod pwm_oen_cfg2 {
#[doc = "Register `PWM_OEN_CFG2` reader"] pub type R = crate :: R < PwmOenCfg2Spec > ;
#[doc = "Register `PWM_OEN_CFG2` writer"] pub type W = crate :: W < PwmOenCfg2Spec > ;
#[doc = "Field `pwm_oen_cfg_2` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg2R = crate :: BitReader ;
#[doc = "Field `pwm_oen_cfg_2` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_2 (& self) -> PwmOenCfg2R { PwmOenCfg2R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_2 (& mut self) -> PwmOenCfg2W < '_ , PwmOenCfg2Spec > { PwmOenCfg2W :: new (self , 0) } }
#[doc = "PWM2 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOenCfg2Spec ; impl crate :: RegisterSpec for PwmOenCfg2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_oen_cfg2::R`](R) reader structure"] impl crate :: Readable for PwmOenCfg2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg2::W`](W) writer structure"] impl crate :: Writable for PwmOenCfg2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OEN_CFG2 to value 0"] impl crate :: Resettable for PwmOenCfg2Spec { } }
#[doc = "PWM_OFFSET_L2 (rw) register accessor: PWM2 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l2`] module"]
#[doc (alias = "PWM_OFFSET_L2")] pub type PwmOffsetL2 = crate :: Reg < pwm_offset_l2 :: PwmOffsetL2Spec > ;
#[doc = "PWM2 phase offset low 16 bits"] pub mod pwm_offset_l2 {
#[doc = "Register `PWM_OFFSET_L2` reader"] pub type R = crate :: R < PwmOffsetL2Spec > ;
#[doc = "Register `PWM_OFFSET_L2` writer"] pub type W = crate :: W < PwmOffsetL2Spec > ;
#[doc = "Field `pwm_offset_l_2` reader - PWM0 phase offset low 16 bits"] pub type PwmOffsetL2R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_l_2` writer - PWM0 phase offset low 16 bits"] pub type PwmOffsetL2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_2 (& self) -> PwmOffsetL2R { PwmOffsetL2R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_2 (& mut self) -> PwmOffsetL2W < '_ , PwmOffsetL2Spec > { PwmOffsetL2W :: new (self , 0) } }
#[doc = "PWM2 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetL2Spec ; impl crate :: RegisterSpec for PwmOffsetL2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_l2::R`](R) reader structure"] impl crate :: Readable for PwmOffsetL2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_l2::W`](W) writer structure"] impl crate :: Writable for PwmOffsetL2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_L2 to value 0"] impl crate :: Resettable for PwmOffsetL2Spec { } }
#[doc = "PWM_OFFSET_H2 (rw) register accessor: PWM2 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h2`] module"]
#[doc (alias = "PWM_OFFSET_H2")] pub type PwmOffsetH2 = crate :: Reg < pwm_offset_h2 :: PwmOffsetH2Spec > ;
#[doc = "PWM2 phase offset high 16 bits"] pub mod pwm_offset_h2 {
#[doc = "Register `PWM_OFFSET_H2` reader"] pub type R = crate :: R < PwmOffsetH2Spec > ;
#[doc = "Register `PWM_OFFSET_H2` writer"] pub type W = crate :: W < PwmOffsetH2Spec > ;
#[doc = "Field `pwm_offset_h_2` reader - PWM0 phase offset high 16 bits"] pub type PwmOffsetH2R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_h_2` writer - PWM0 phase offset high 16 bits"] pub type PwmOffsetH2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_2 (& self) -> PwmOffsetH2R { PwmOffsetH2R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_2 (& mut self) -> PwmOffsetH2W < '_ , PwmOffsetH2Spec > { PwmOffsetH2W :: new (self , 0) } }
#[doc = "PWM2 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetH2Spec ; impl crate :: RegisterSpec for PwmOffsetH2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_h2::R`](R) reader structure"] impl crate :: Readable for PwmOffsetH2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_h2::W`](W) writer structure"] impl crate :: Writable for PwmOffsetH2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_H2 to value 0"] impl crate :: Resettable for PwmOffsetH2Spec { } }
#[doc = "PWM_FREQ_L2 (rw) register accessor: PWM2 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l2`] module"]
#[doc (alias = "PWM_FREQ_L2")] pub type PwmFreqL2 = crate :: Reg < pwm_freq_l2 :: PwmFreqL2Spec > ;
#[doc = "PWM2 frequency low 16 bits"] pub mod pwm_freq_l2 {
#[doc = "Register `PWM_FREQ_L2` reader"] pub type R = crate :: R < PwmFreqL2Spec > ;
#[doc = "Register `PWM_FREQ_L2` writer"] pub type W = crate :: W < PwmFreqL2Spec > ;
#[doc = "Field `pwm_freq_l_2` reader - PWM0 clock divider low 16 bits"] pub type PwmFreqL2R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_l_2` writer - PWM0 clock divider low 16 bits"] pub type PwmFreqL2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_2 (& self) -> PwmFreqL2R { PwmFreqL2R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_2 (& mut self) -> PwmFreqL2W < '_ , PwmFreqL2Spec > { PwmFreqL2W :: new (self , 0) } }
#[doc = "PWM2 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqL2Spec ; impl crate :: RegisterSpec for PwmFreqL2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_l2::R`](R) reader structure"] impl crate :: Readable for PwmFreqL2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_l2::W`](W) writer structure"] impl crate :: Writable for PwmFreqL2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_L2 to value 0"] impl crate :: Resettable for PwmFreqL2Spec { } }
#[doc = "PWM_FREQ_H2 (rw) register accessor: PWM2 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h2`] module"]
#[doc (alias = "PWM_FREQ_H2")] pub type PwmFreqH2 = crate :: Reg < pwm_freq_h2 :: PwmFreqH2Spec > ;
#[doc = "PWM2 frequency high 16 bits"] pub mod pwm_freq_h2 {
#[doc = "Register `PWM_FREQ_H2` reader"] pub type R = crate :: R < PwmFreqH2Spec > ;
#[doc = "Register `PWM_FREQ_H2` writer"] pub type W = crate :: W < PwmFreqH2Spec > ;
#[doc = "Field `pwm_freq_h_2` reader - PWM0 clock divider high 16 bits"] pub type PwmFreqH2R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_h_2` writer - PWM0 clock divider high 16 bits"] pub type PwmFreqH2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_2 (& self) -> PwmFreqH2R { PwmFreqH2R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_2 (& mut self) -> PwmFreqH2W < '_ , PwmFreqH2Spec > { PwmFreqH2W :: new (self , 0) } }
#[doc = "PWM2 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqH2Spec ; impl crate :: RegisterSpec for PwmFreqH2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_h2::R`](R) reader structure"] impl crate :: Readable for PwmFreqH2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_h2::W`](W) writer structure"] impl crate :: Writable for PwmFreqH2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_H2 to value 0"] impl crate :: Resettable for PwmFreqH2Spec { } }
#[doc = "PWM_DUTY_L2 (rw) register accessor: PWM2 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l2`] module"]
#[doc (alias = "PWM_DUTY_L2")] pub type PwmDutyL2 = crate :: Reg < pwm_duty_l2 :: PwmDutyL2Spec > ;
#[doc = "PWM2 duty cycle low 16 bits"] pub mod pwm_duty_l2 {
#[doc = "Register `PWM_DUTY_L2` reader"] pub type R = crate :: R < PwmDutyL2Spec > ;
#[doc = "Register `PWM_DUTY_L2` writer"] pub type W = crate :: W < PwmDutyL2Spec > ;
#[doc = "Field `pwm_duty_l_2` reader - PWM0 duty cycle low 16 bits"] pub type PwmDutyL2R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_l_2` writer - PWM0 duty cycle low 16 bits"] pub type PwmDutyL2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_2 (& self) -> PwmDutyL2R { PwmDutyL2R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_2 (& mut self) -> PwmDutyL2W < '_ , PwmDutyL2Spec > { PwmDutyL2W :: new (self , 0) } }
#[doc = "PWM2 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyL2Spec ; impl crate :: RegisterSpec for PwmDutyL2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_l2::R`](R) reader structure"] impl crate :: Readable for PwmDutyL2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_l2::W`](W) writer structure"] impl crate :: Writable for PwmDutyL2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_L2 to value 0"] impl crate :: Resettable for PwmDutyL2Spec { } }
#[doc = "PWM_DUTY_H2 (rw) register accessor: PWM2 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h2`] module"]
#[doc (alias = "PWM_DUTY_H2")] pub type PwmDutyH2 = crate :: Reg < pwm_duty_h2 :: PwmDutyH2Spec > ;
#[doc = "PWM2 duty cycle high 16 bits"] pub mod pwm_duty_h2 {
#[doc = "Register `PWM_DUTY_H2` reader"] pub type R = crate :: R < PwmDutyH2Spec > ;
#[doc = "Register `PWM_DUTY_H2` writer"] pub type W = crate :: W < PwmDutyH2Spec > ;
#[doc = "Field `pwm_duty_h_2` reader - PWM0 duty cycle high 16 bits"] pub type PwmDutyH2R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_h_2` writer - PWM0 duty cycle high 16 bits"] pub type PwmDutyH2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_2 (& self) -> PwmDutyH2R { PwmDutyH2R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_2 (& mut self) -> PwmDutyH2W < '_ , PwmDutyH2Spec > { PwmDutyH2W :: new (self , 0) } }
#[doc = "PWM2 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyH2Spec ; impl crate :: RegisterSpec for PwmDutyH2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_h2::R`](R) reader structure"] impl crate :: Readable for PwmDutyH2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_h2::W`](W) writer structure"] impl crate :: Writable for PwmDutyH2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_H2 to value 0"] impl crate :: Resettable for PwmDutyH2Spec { } }
#[doc = "PWM_PERIODLOAD_FLAG2 (rw) register accessor: PWM2 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag2`] module"]
#[doc (alias = "PWM_PERIODLOAD_FLAG2")] pub type PwmPeriodloadFlag2 = crate :: Reg < pwm_periodload_flag2 :: PwmPeriodloadFlag2Spec > ;
#[doc = "PWM2 period load flag"] pub mod pwm_periodload_flag2 {
#[doc = "Register `PWM_PERIODLOAD_FLAG2` reader"] pub type R = crate :: R < PwmPeriodloadFlag2Spec > ;
#[doc = "Register `PWM_PERIODLOAD_FLAG2` writer"] pub type W = crate :: W < PwmPeriodloadFlag2Spec > ;
#[doc = "Field `pwm_periodload_flag_2` reader - Period load complete flag"] pub type PwmPeriodloadFlag2R = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Period load complete flag"]
#[inline (always)] pub fn pwm_periodload_flag_2 (& self) -> PwmPeriodloadFlag2R { PwmPeriodloadFlag2R :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "PWM2 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodloadFlag2Spec ; impl crate :: RegisterSpec for PwmPeriodloadFlag2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodload_flag2::R`](R) reader structure"] impl crate :: Readable for PwmPeriodloadFlag2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag2::W`](W) writer structure"] impl crate :: Writable for PwmPeriodloadFlag2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG2 to value 0"] impl crate :: Resettable for PwmPeriodloadFlag2Spec { } }
#[doc = "PWM_PERIOD_VAL2 (rw) register accessor: PWM2 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val2`] module"]
#[doc (alias = "PWM_PERIOD_VAL2")] pub type PwmPeriodVal2 = crate :: Reg < pwm_period_val2 :: PwmPeriodVal2Spec > ;
#[doc = "PWM2 pulse count value"] pub mod pwm_period_val2 {
#[doc = "Register `PWM_PERIOD_VAL2` reader"] pub type R = crate :: R < PwmPeriodVal2Spec > ;
#[doc = "Register `PWM_PERIOD_VAL2` writer"] pub type W = crate :: W < PwmPeriodVal2Spec > ;
#[doc = "Field `pwm_period_val_2` reader - Pulse count for stepping mode"] pub type PwmPeriodVal2R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_period_val_2` writer - Pulse count for stepping mode"] pub type PwmPeriodVal2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_2 (& self) -> PwmPeriodVal2R { PwmPeriodVal2R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_2 (& mut self) -> PwmPeriodVal2W < '_ , PwmPeriodVal2Spec > { PwmPeriodVal2W :: new (self , 0) } }
#[doc = "PWM2 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodVal2Spec ; impl crate :: RegisterSpec for PwmPeriodVal2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_period_val2::R`](R) reader structure"] impl crate :: Readable for PwmPeriodVal2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_period_val2::W`](W) writer structure"] impl crate :: Writable for PwmPeriodVal2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIOD_VAL2 to value 0"] impl crate :: Resettable for PwmPeriodVal2Spec { } }
#[doc = "PWM_PERIODCNT2 (rw) register accessor: PWM2 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt2`] module"]
#[doc (alias = "PWM_PERIODCNT2")] pub type PwmPeriodcnt2 = crate :: Reg < pwm_periodcnt2 :: PwmPeriodcnt2Spec > ;
#[doc = "PWM2 pulse count current value"] pub mod pwm_periodcnt2 {
#[doc = "Register `PWM_PERIODCNT2` reader"] pub type R = crate :: R < PwmPeriodcnt2Spec > ;
#[doc = "Register `PWM_PERIODCNT2` writer"] pub type W = crate :: W < PwmPeriodcnt2Spec > ;
#[doc = "Field `pwm_periodcnt_2` reader - Current pulse count"] pub type PwmPeriodcnt2R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Current pulse count"]
#[inline (always)] pub fn pwm_periodcnt_2 (& self) -> PwmPeriodcnt2R { PwmPeriodcnt2R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "PWM2 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodcnt2Spec ; impl crate :: RegisterSpec for PwmPeriodcnt2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodcnt2::R`](R) reader structure"] impl crate :: Readable for PwmPeriodcnt2Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodcnt2::W`](W) writer structure"] impl crate :: Writable for PwmPeriodcnt2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODCNT2 to value 0"] impl crate :: Resettable for PwmPeriodcnt2Spec { } }
#[doc = "PWM_EN3 (rw) register accessor: PWM3 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en3`] module"]
#[doc (alias = "PWM_EN3")] pub type PwmEn3 = crate :: Reg < pwm_en3 :: PwmEn3Spec > ;
#[doc = "PWM3 enable"] pub mod pwm_en3 {
#[doc = "Register `PWM_EN3` reader"] pub type R = crate :: R < PwmEn3Spec > ;
#[doc = "Register `PWM_EN3` writer"] pub type W = crate :: W < PwmEn3Spec > ;
#[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmEn3 {
#[doc = "0: PWM disabled, output low"] Off = 0 ,
#[doc = "1: PWM enabled"] On = 1 , } impl From < PwmEn3 > for bool {
#[inline (always)] fn from (variant : PwmEn3) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_en_3` reader - PWM0 enable: 0=off; 1=on"] pub type PwmEn3R = crate :: BitReader < PwmEn3 > ; impl PwmEn3R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmEn3 { match self . bits { false => PwmEn3 :: Off , true => PwmEn3 :: On , } }
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn is_off (& self) -> bool { * self == PwmEn3 :: Off }
#[doc = "PWM enabled"]
#[inline (always)] pub fn is_on (& self) -> bool { * self == PwmEn3 :: On } }
#[doc = "Field `pwm_en_3` writer - PWM0 enable: 0=off; 1=on"] pub type PwmEn3W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmEn3 > ; impl < 'a , REG > PwmEn3W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn3 :: Off) }
#[doc = "PWM enabled"]
#[inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn3 :: On) } } impl R {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_3 (& self) -> PwmEn3R { PwmEn3R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_3 (& mut self) -> PwmEn3W < '_ , PwmEn3Spec > { PwmEn3W :: new (self , 0) } }
#[doc = "PWM3 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmEn3Spec ; impl crate :: RegisterSpec for PwmEn3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_en3::R`](R) reader structure"] impl crate :: Readable for PwmEn3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_en3::W`](W) writer structure"] impl crate :: Writable for PwmEn3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_EN3 to value 0"] impl crate :: Resettable for PwmEn3Spec { } }
#[doc = "PWM_PORTITY3 (rw) register accessor: PWM3 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity3`] module"]
#[doc (alias = "PWM_PORTITY3")] pub type PwmPortity3 = crate :: Reg < pwm_portity3 :: PwmPortity3Spec > ;
#[doc = "PWM3 polarity"] pub mod pwm_portity3 {
#[doc = "Register `PWM_PORTITY3` reader"] pub type R = crate :: R < PwmPortity3Spec > ;
#[doc = "Register `PWM_PORTITY3` writer"] pub type W = crate :: W < PwmPortity3Spec > ;
#[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmPoarity3 {
#[doc = "0: Normal polarity"] Normal = 0 ,
#[doc = "1: Inverted polarity"] Inverted = 1 , } impl From < PwmPoarity3 > for bool {
#[inline (always)] fn from (variant : PwmPoarity3) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_poarity_3` reader - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity3R = crate :: BitReader < PwmPoarity3 > ; impl PwmPoarity3R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmPoarity3 { match self . bits { false => PwmPoarity3 :: Normal , true => PwmPoarity3 :: Inverted , } }
#[doc = "Normal polarity"]
#[inline (always)] pub fn is_normal (& self) -> bool { * self == PwmPoarity3 :: Normal }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn is_inverted (& self) -> bool { * self == PwmPoarity3 :: Inverted } }
#[doc = "Field `pwm_poarity_3` writer - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity3W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmPoarity3 > ; impl < 'a , REG > PwmPoarity3W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "Normal polarity"]
#[inline (always)] pub fn normal (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity3 :: Normal) }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn inverted (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity3 :: Inverted) } } impl R {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_3 (& self) -> PwmPoarity3R { PwmPoarity3R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_3 (& mut self) -> PwmPoarity3W < '_ , PwmPortity3Spec > { PwmPoarity3W :: new (self , 0) } }
#[doc = "PWM3 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPortity3Spec ; impl crate :: RegisterSpec for PwmPortity3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_portity3::R`](R) reader structure"] impl crate :: Readable for PwmPortity3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_portity3::W`](W) writer structure"] impl crate :: Writable for PwmPortity3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PORTITY3 to value 0"] impl crate :: Resettable for PwmPortity3Spec { } }
#[doc = "PWM_OEN_CFG3 (rw) register accessor: PWM3 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg3`] module"]
#[doc (alias = "PWM_OEN_CFG3")] pub type PwmOenCfg3 = crate :: Reg < pwm_oen_cfg3 :: PwmOenCfg3Spec > ;
#[doc = "PWM3 high-impedance config"] pub mod pwm_oen_cfg3 {
#[doc = "Register `PWM_OEN_CFG3` reader"] pub type R = crate :: R < PwmOenCfg3Spec > ;
#[doc = "Register `PWM_OEN_CFG3` writer"] pub type W = crate :: W < PwmOenCfg3Spec > ;
#[doc = "Field `pwm_oen_cfg_3` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg3R = crate :: BitReader ;
#[doc = "Field `pwm_oen_cfg_3` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg3W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_3 (& self) -> PwmOenCfg3R { PwmOenCfg3R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_3 (& mut self) -> PwmOenCfg3W < '_ , PwmOenCfg3Spec > { PwmOenCfg3W :: new (self , 0) } }
#[doc = "PWM3 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOenCfg3Spec ; impl crate :: RegisterSpec for PwmOenCfg3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_oen_cfg3::R`](R) reader structure"] impl crate :: Readable for PwmOenCfg3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg3::W`](W) writer structure"] impl crate :: Writable for PwmOenCfg3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OEN_CFG3 to value 0"] impl crate :: Resettable for PwmOenCfg3Spec { } }
#[doc = "PWM_OFFSET_L3 (rw) register accessor: PWM3 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l3`] module"]
#[doc (alias = "PWM_OFFSET_L3")] pub type PwmOffsetL3 = crate :: Reg < pwm_offset_l3 :: PwmOffsetL3Spec > ;
#[doc = "PWM3 phase offset low 16 bits"] pub mod pwm_offset_l3 {
#[doc = "Register `PWM_OFFSET_L3` reader"] pub type R = crate :: R < PwmOffsetL3Spec > ;
#[doc = "Register `PWM_OFFSET_L3` writer"] pub type W = crate :: W < PwmOffsetL3Spec > ;
#[doc = "Field `pwm_offset_l_3` reader - PWM0 phase offset low 16 bits"] pub type PwmOffsetL3R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_l_3` writer - PWM0 phase offset low 16 bits"] pub type PwmOffsetL3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_3 (& self) -> PwmOffsetL3R { PwmOffsetL3R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_3 (& mut self) -> PwmOffsetL3W < '_ , PwmOffsetL3Spec > { PwmOffsetL3W :: new (self , 0) } }
#[doc = "PWM3 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetL3Spec ; impl crate :: RegisterSpec for PwmOffsetL3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_l3::R`](R) reader structure"] impl crate :: Readable for PwmOffsetL3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_l3::W`](W) writer structure"] impl crate :: Writable for PwmOffsetL3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_L3 to value 0"] impl crate :: Resettable for PwmOffsetL3Spec { } }
#[doc = "PWM_OFFSET_H3 (rw) register accessor: PWM3 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h3`] module"]
#[doc (alias = "PWM_OFFSET_H3")] pub type PwmOffsetH3 = crate :: Reg < pwm_offset_h3 :: PwmOffsetH3Spec > ;
#[doc = "PWM3 phase offset high 16 bits"] pub mod pwm_offset_h3 {
#[doc = "Register `PWM_OFFSET_H3` reader"] pub type R = crate :: R < PwmOffsetH3Spec > ;
#[doc = "Register `PWM_OFFSET_H3` writer"] pub type W = crate :: W < PwmOffsetH3Spec > ;
#[doc = "Field `pwm_offset_h_3` reader - PWM0 phase offset high 16 bits"] pub type PwmOffsetH3R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_h_3` writer - PWM0 phase offset high 16 bits"] pub type PwmOffsetH3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_3 (& self) -> PwmOffsetH3R { PwmOffsetH3R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_3 (& mut self) -> PwmOffsetH3W < '_ , PwmOffsetH3Spec > { PwmOffsetH3W :: new (self , 0) } }
#[doc = "PWM3 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetH3Spec ; impl crate :: RegisterSpec for PwmOffsetH3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_h3::R`](R) reader structure"] impl crate :: Readable for PwmOffsetH3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_h3::W`](W) writer structure"] impl crate :: Writable for PwmOffsetH3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_H3 to value 0"] impl crate :: Resettable for PwmOffsetH3Spec { } }
#[doc = "PWM_FREQ_L3 (rw) register accessor: PWM3 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l3`] module"]
#[doc (alias = "PWM_FREQ_L3")] pub type PwmFreqL3 = crate :: Reg < pwm_freq_l3 :: PwmFreqL3Spec > ;
#[doc = "PWM3 frequency low 16 bits"] pub mod pwm_freq_l3 {
#[doc = "Register `PWM_FREQ_L3` reader"] pub type R = crate :: R < PwmFreqL3Spec > ;
#[doc = "Register `PWM_FREQ_L3` writer"] pub type W = crate :: W < PwmFreqL3Spec > ;
#[doc = "Field `pwm_freq_l_3` reader - PWM0 clock divider low 16 bits"] pub type PwmFreqL3R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_l_3` writer - PWM0 clock divider low 16 bits"] pub type PwmFreqL3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_3 (& self) -> PwmFreqL3R { PwmFreqL3R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_3 (& mut self) -> PwmFreqL3W < '_ , PwmFreqL3Spec > { PwmFreqL3W :: new (self , 0) } }
#[doc = "PWM3 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqL3Spec ; impl crate :: RegisterSpec for PwmFreqL3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_l3::R`](R) reader structure"] impl crate :: Readable for PwmFreqL3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_l3::W`](W) writer structure"] impl crate :: Writable for PwmFreqL3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_L3 to value 0"] impl crate :: Resettable for PwmFreqL3Spec { } }
#[doc = "PWM_FREQ_H3 (rw) register accessor: PWM3 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h3`] module"]
#[doc (alias = "PWM_FREQ_H3")] pub type PwmFreqH3 = crate :: Reg < pwm_freq_h3 :: PwmFreqH3Spec > ;
#[doc = "PWM3 frequency high 16 bits"] pub mod pwm_freq_h3 {
#[doc = "Register `PWM_FREQ_H3` reader"] pub type R = crate :: R < PwmFreqH3Spec > ;
#[doc = "Register `PWM_FREQ_H3` writer"] pub type W = crate :: W < PwmFreqH3Spec > ;
#[doc = "Field `pwm_freq_h_3` reader - PWM0 clock divider high 16 bits"] pub type PwmFreqH3R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_h_3` writer - PWM0 clock divider high 16 bits"] pub type PwmFreqH3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_3 (& self) -> PwmFreqH3R { PwmFreqH3R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_3 (& mut self) -> PwmFreqH3W < '_ , PwmFreqH3Spec > { PwmFreqH3W :: new (self , 0) } }
#[doc = "PWM3 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqH3Spec ; impl crate :: RegisterSpec for PwmFreqH3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_h3::R`](R) reader structure"] impl crate :: Readable for PwmFreqH3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_h3::W`](W) writer structure"] impl crate :: Writable for PwmFreqH3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_H3 to value 0"] impl crate :: Resettable for PwmFreqH3Spec { } }
#[doc = "PWM_DUTY_L3 (rw) register accessor: PWM3 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l3`] module"]
#[doc (alias = "PWM_DUTY_L3")] pub type PwmDutyL3 = crate :: Reg < pwm_duty_l3 :: PwmDutyL3Spec > ;
#[doc = "PWM3 duty cycle low 16 bits"] pub mod pwm_duty_l3 {
#[doc = "Register `PWM_DUTY_L3` reader"] pub type R = crate :: R < PwmDutyL3Spec > ;
#[doc = "Register `PWM_DUTY_L3` writer"] pub type W = crate :: W < PwmDutyL3Spec > ;
#[doc = "Field `pwm_duty_l_3` reader - PWM0 duty cycle low 16 bits"] pub type PwmDutyL3R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_l_3` writer - PWM0 duty cycle low 16 bits"] pub type PwmDutyL3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_3 (& self) -> PwmDutyL3R { PwmDutyL3R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_3 (& mut self) -> PwmDutyL3W < '_ , PwmDutyL3Spec > { PwmDutyL3W :: new (self , 0) } }
#[doc = "PWM3 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyL3Spec ; impl crate :: RegisterSpec for PwmDutyL3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_l3::R`](R) reader structure"] impl crate :: Readable for PwmDutyL3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_l3::W`](W) writer structure"] impl crate :: Writable for PwmDutyL3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_L3 to value 0"] impl crate :: Resettable for PwmDutyL3Spec { } }
#[doc = "PWM_DUTY_H3 (rw) register accessor: PWM3 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h3`] module"]
#[doc (alias = "PWM_DUTY_H3")] pub type PwmDutyH3 = crate :: Reg < pwm_duty_h3 :: PwmDutyH3Spec > ;
#[doc = "PWM3 duty cycle high 16 bits"] pub mod pwm_duty_h3 {
#[doc = "Register `PWM_DUTY_H3` reader"] pub type R = crate :: R < PwmDutyH3Spec > ;
#[doc = "Register `PWM_DUTY_H3` writer"] pub type W = crate :: W < PwmDutyH3Spec > ;
#[doc = "Field `pwm_duty_h_3` reader - PWM0 duty cycle high 16 bits"] pub type PwmDutyH3R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_h_3` writer - PWM0 duty cycle high 16 bits"] pub type PwmDutyH3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_3 (& self) -> PwmDutyH3R { PwmDutyH3R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_3 (& mut self) -> PwmDutyH3W < '_ , PwmDutyH3Spec > { PwmDutyH3W :: new (self , 0) } }
#[doc = "PWM3 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyH3Spec ; impl crate :: RegisterSpec for PwmDutyH3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_h3::R`](R) reader structure"] impl crate :: Readable for PwmDutyH3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_h3::W`](W) writer structure"] impl crate :: Writable for PwmDutyH3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_H3 to value 0"] impl crate :: Resettable for PwmDutyH3Spec { } }
#[doc = "PWM_PERIODLOAD_FLAG3 (rw) register accessor: PWM3 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag3`] module"]
#[doc (alias = "PWM_PERIODLOAD_FLAG3")] pub type PwmPeriodloadFlag3 = crate :: Reg < pwm_periodload_flag3 :: PwmPeriodloadFlag3Spec > ;
#[doc = "PWM3 period load flag"] pub mod pwm_periodload_flag3 {
#[doc = "Register `PWM_PERIODLOAD_FLAG3` reader"] pub type R = crate :: R < PwmPeriodloadFlag3Spec > ;
#[doc = "Register `PWM_PERIODLOAD_FLAG3` writer"] pub type W = crate :: W < PwmPeriodloadFlag3Spec > ;
#[doc = "Field `pwm_periodload_flag_3` reader - Period load complete flag"] pub type PwmPeriodloadFlag3R = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Period load complete flag"]
#[inline (always)] pub fn pwm_periodload_flag_3 (& self) -> PwmPeriodloadFlag3R { PwmPeriodloadFlag3R :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "PWM3 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodloadFlag3Spec ; impl crate :: RegisterSpec for PwmPeriodloadFlag3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodload_flag3::R`](R) reader structure"] impl crate :: Readable for PwmPeriodloadFlag3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag3::W`](W) writer structure"] impl crate :: Writable for PwmPeriodloadFlag3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG3 to value 0"] impl crate :: Resettable for PwmPeriodloadFlag3Spec { } }
#[doc = "PWM_PERIOD_VAL3 (rw) register accessor: PWM3 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val3`] module"]
#[doc (alias = "PWM_PERIOD_VAL3")] pub type PwmPeriodVal3 = crate :: Reg < pwm_period_val3 :: PwmPeriodVal3Spec > ;
#[doc = "PWM3 pulse count value"] pub mod pwm_period_val3 {
#[doc = "Register `PWM_PERIOD_VAL3` reader"] pub type R = crate :: R < PwmPeriodVal3Spec > ;
#[doc = "Register `PWM_PERIOD_VAL3` writer"] pub type W = crate :: W < PwmPeriodVal3Spec > ;
#[doc = "Field `pwm_period_val_3` reader - Pulse count for stepping mode"] pub type PwmPeriodVal3R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_period_val_3` writer - Pulse count for stepping mode"] pub type PwmPeriodVal3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_3 (& self) -> PwmPeriodVal3R { PwmPeriodVal3R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_3 (& mut self) -> PwmPeriodVal3W < '_ , PwmPeriodVal3Spec > { PwmPeriodVal3W :: new (self , 0) } }
#[doc = "PWM3 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodVal3Spec ; impl crate :: RegisterSpec for PwmPeriodVal3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_period_val3::R`](R) reader structure"] impl crate :: Readable for PwmPeriodVal3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_period_val3::W`](W) writer structure"] impl crate :: Writable for PwmPeriodVal3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIOD_VAL3 to value 0"] impl crate :: Resettable for PwmPeriodVal3Spec { } }
#[doc = "PWM_PERIODCNT3 (rw) register accessor: PWM3 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt3`] module"]
#[doc (alias = "PWM_PERIODCNT3")] pub type PwmPeriodcnt3 = crate :: Reg < pwm_periodcnt3 :: PwmPeriodcnt3Spec > ;
#[doc = "PWM3 pulse count current value"] pub mod pwm_periodcnt3 {
#[doc = "Register `PWM_PERIODCNT3` reader"] pub type R = crate :: R < PwmPeriodcnt3Spec > ;
#[doc = "Register `PWM_PERIODCNT3` writer"] pub type W = crate :: W < PwmPeriodcnt3Spec > ;
#[doc = "Field `pwm_periodcnt_3` reader - Current pulse count"] pub type PwmPeriodcnt3R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Current pulse count"]
#[inline (always)] pub fn pwm_periodcnt_3 (& self) -> PwmPeriodcnt3R { PwmPeriodcnt3R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "PWM3 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodcnt3Spec ; impl crate :: RegisterSpec for PwmPeriodcnt3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodcnt3::R`](R) reader structure"] impl crate :: Readable for PwmPeriodcnt3Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodcnt3::W`](W) writer structure"] impl crate :: Writable for PwmPeriodcnt3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODCNT3 to value 0"] impl crate :: Resettable for PwmPeriodcnt3Spec { } }
#[doc = "PWM_EN4 (rw) register accessor: PWM4 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en4`] module"]
#[doc (alias = "PWM_EN4")] pub type PwmEn4 = crate :: Reg < pwm_en4 :: PwmEn4Spec > ;
#[doc = "PWM4 enable"] pub mod pwm_en4 {
#[doc = "Register `PWM_EN4` reader"] pub type R = crate :: R < PwmEn4Spec > ;
#[doc = "Register `PWM_EN4` writer"] pub type W = crate :: W < PwmEn4Spec > ;
#[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmEn4 {
#[doc = "0: PWM disabled, output low"] Off = 0 ,
#[doc = "1: PWM enabled"] On = 1 , } impl From < PwmEn4 > for bool {
#[inline (always)] fn from (variant : PwmEn4) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_en_4` reader - PWM0 enable: 0=off; 1=on"] pub type PwmEn4R = crate :: BitReader < PwmEn4 > ; impl PwmEn4R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmEn4 { match self . bits { false => PwmEn4 :: Off , true => PwmEn4 :: On , } }
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn is_off (& self) -> bool { * self == PwmEn4 :: Off }
#[doc = "PWM enabled"]
#[inline (always)] pub fn is_on (& self) -> bool { * self == PwmEn4 :: On } }
#[doc = "Field `pwm_en_4` writer - PWM0 enable: 0=off; 1=on"] pub type PwmEn4W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmEn4 > ; impl < 'a , REG > PwmEn4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn4 :: Off) }
#[doc = "PWM enabled"]
#[inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn4 :: On) } } impl R {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_4 (& self) -> PwmEn4R { PwmEn4R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_4 (& mut self) -> PwmEn4W < '_ , PwmEn4Spec > { PwmEn4W :: new (self , 0) } }
#[doc = "PWM4 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmEn4Spec ; impl crate :: RegisterSpec for PwmEn4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_en4::R`](R) reader structure"] impl crate :: Readable for PwmEn4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_en4::W`](W) writer structure"] impl crate :: Writable for PwmEn4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_EN4 to value 0"] impl crate :: Resettable for PwmEn4Spec { } }
#[doc = "PWM_PORTITY4 (rw) register accessor: PWM4 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity4`] module"]
#[doc (alias = "PWM_PORTITY4")] pub type PwmPortity4 = crate :: Reg < pwm_portity4 :: PwmPortity4Spec > ;
#[doc = "PWM4 polarity"] pub mod pwm_portity4 {
#[doc = "Register `PWM_PORTITY4` reader"] pub type R = crate :: R < PwmPortity4Spec > ;
#[doc = "Register `PWM_PORTITY4` writer"] pub type W = crate :: W < PwmPortity4Spec > ;
#[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmPoarity4 {
#[doc = "0: Normal polarity"] Normal = 0 ,
#[doc = "1: Inverted polarity"] Inverted = 1 , } impl From < PwmPoarity4 > for bool {
#[inline (always)] fn from (variant : PwmPoarity4) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_poarity_4` reader - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity4R = crate :: BitReader < PwmPoarity4 > ; impl PwmPoarity4R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmPoarity4 { match self . bits { false => PwmPoarity4 :: Normal , true => PwmPoarity4 :: Inverted , } }
#[doc = "Normal polarity"]
#[inline (always)] pub fn is_normal (& self) -> bool { * self == PwmPoarity4 :: Normal }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn is_inverted (& self) -> bool { * self == PwmPoarity4 :: Inverted } }
#[doc = "Field `pwm_poarity_4` writer - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity4W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmPoarity4 > ; impl < 'a , REG > PwmPoarity4W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "Normal polarity"]
#[inline (always)] pub fn normal (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity4 :: Normal) }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn inverted (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity4 :: Inverted) } } impl R {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_4 (& self) -> PwmPoarity4R { PwmPoarity4R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_4 (& mut self) -> PwmPoarity4W < '_ , PwmPortity4Spec > { PwmPoarity4W :: new (self , 0) } }
#[doc = "PWM4 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPortity4Spec ; impl crate :: RegisterSpec for PwmPortity4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_portity4::R`](R) reader structure"] impl crate :: Readable for PwmPortity4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_portity4::W`](W) writer structure"] impl crate :: Writable for PwmPortity4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PORTITY4 to value 0"] impl crate :: Resettable for PwmPortity4Spec { } }
#[doc = "PWM_OEN_CFG4 (rw) register accessor: PWM4 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg4`] module"]
#[doc (alias = "PWM_OEN_CFG4")] pub type PwmOenCfg4 = crate :: Reg < pwm_oen_cfg4 :: PwmOenCfg4Spec > ;
#[doc = "PWM4 high-impedance config"] pub mod pwm_oen_cfg4 {
#[doc = "Register `PWM_OEN_CFG4` reader"] pub type R = crate :: R < PwmOenCfg4Spec > ;
#[doc = "Register `PWM_OEN_CFG4` writer"] pub type W = crate :: W < PwmOenCfg4Spec > ;
#[doc = "Field `pwm_oen_cfg_4` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg4R = crate :: BitReader ;
#[doc = "Field `pwm_oen_cfg_4` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg4W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_4 (& self) -> PwmOenCfg4R { PwmOenCfg4R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_4 (& mut self) -> PwmOenCfg4W < '_ , PwmOenCfg4Spec > { PwmOenCfg4W :: new (self , 0) } }
#[doc = "PWM4 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOenCfg4Spec ; impl crate :: RegisterSpec for PwmOenCfg4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_oen_cfg4::R`](R) reader structure"] impl crate :: Readable for PwmOenCfg4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg4::W`](W) writer structure"] impl crate :: Writable for PwmOenCfg4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OEN_CFG4 to value 0"] impl crate :: Resettable for PwmOenCfg4Spec { } }
#[doc = "PWM_OFFSET_L4 (rw) register accessor: PWM4 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l4`] module"]
#[doc (alias = "PWM_OFFSET_L4")] pub type PwmOffsetL4 = crate :: Reg < pwm_offset_l4 :: PwmOffsetL4Spec > ;
#[doc = "PWM4 phase offset low 16 bits"] pub mod pwm_offset_l4 {
#[doc = "Register `PWM_OFFSET_L4` reader"] pub type R = crate :: R < PwmOffsetL4Spec > ;
#[doc = "Register `PWM_OFFSET_L4` writer"] pub type W = crate :: W < PwmOffsetL4Spec > ;
#[doc = "Field `pwm_offset_l_4` reader - PWM0 phase offset low 16 bits"] pub type PwmOffsetL4R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_l_4` writer - PWM0 phase offset low 16 bits"] pub type PwmOffsetL4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_4 (& self) -> PwmOffsetL4R { PwmOffsetL4R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_4 (& mut self) -> PwmOffsetL4W < '_ , PwmOffsetL4Spec > { PwmOffsetL4W :: new (self , 0) } }
#[doc = "PWM4 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetL4Spec ; impl crate :: RegisterSpec for PwmOffsetL4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_l4::R`](R) reader structure"] impl crate :: Readable for PwmOffsetL4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_l4::W`](W) writer structure"] impl crate :: Writable for PwmOffsetL4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_L4 to value 0"] impl crate :: Resettable for PwmOffsetL4Spec { } }
#[doc = "PWM_OFFSET_H4 (rw) register accessor: PWM4 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h4`] module"]
#[doc (alias = "PWM_OFFSET_H4")] pub type PwmOffsetH4 = crate :: Reg < pwm_offset_h4 :: PwmOffsetH4Spec > ;
#[doc = "PWM4 phase offset high 16 bits"] pub mod pwm_offset_h4 {
#[doc = "Register `PWM_OFFSET_H4` reader"] pub type R = crate :: R < PwmOffsetH4Spec > ;
#[doc = "Register `PWM_OFFSET_H4` writer"] pub type W = crate :: W < PwmOffsetH4Spec > ;
#[doc = "Field `pwm_offset_h_4` reader - PWM0 phase offset high 16 bits"] pub type PwmOffsetH4R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_h_4` writer - PWM0 phase offset high 16 bits"] pub type PwmOffsetH4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_4 (& self) -> PwmOffsetH4R { PwmOffsetH4R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_4 (& mut self) -> PwmOffsetH4W < '_ , PwmOffsetH4Spec > { PwmOffsetH4W :: new (self , 0) } }
#[doc = "PWM4 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetH4Spec ; impl crate :: RegisterSpec for PwmOffsetH4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_h4::R`](R) reader structure"] impl crate :: Readable for PwmOffsetH4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_h4::W`](W) writer structure"] impl crate :: Writable for PwmOffsetH4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_H4 to value 0"] impl crate :: Resettable for PwmOffsetH4Spec { } }
#[doc = "PWM_FREQ_L4 (rw) register accessor: PWM4 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l4`] module"]
#[doc (alias = "PWM_FREQ_L4")] pub type PwmFreqL4 = crate :: Reg < pwm_freq_l4 :: PwmFreqL4Spec > ;
#[doc = "PWM4 frequency low 16 bits"] pub mod pwm_freq_l4 {
#[doc = "Register `PWM_FREQ_L4` reader"] pub type R = crate :: R < PwmFreqL4Spec > ;
#[doc = "Register `PWM_FREQ_L4` writer"] pub type W = crate :: W < PwmFreqL4Spec > ;
#[doc = "Field `pwm_freq_l_4` reader - PWM0 clock divider low 16 bits"] pub type PwmFreqL4R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_l_4` writer - PWM0 clock divider low 16 bits"] pub type PwmFreqL4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_4 (& self) -> PwmFreqL4R { PwmFreqL4R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_4 (& mut self) -> PwmFreqL4W < '_ , PwmFreqL4Spec > { PwmFreqL4W :: new (self , 0) } }
#[doc = "PWM4 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqL4Spec ; impl crate :: RegisterSpec for PwmFreqL4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_l4::R`](R) reader structure"] impl crate :: Readable for PwmFreqL4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_l4::W`](W) writer structure"] impl crate :: Writable for PwmFreqL4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_L4 to value 0"] impl crate :: Resettable for PwmFreqL4Spec { } }
#[doc = "PWM_FREQ_H4 (rw) register accessor: PWM4 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h4`] module"]
#[doc (alias = "PWM_FREQ_H4")] pub type PwmFreqH4 = crate :: Reg < pwm_freq_h4 :: PwmFreqH4Spec > ;
#[doc = "PWM4 frequency high 16 bits"] pub mod pwm_freq_h4 {
#[doc = "Register `PWM_FREQ_H4` reader"] pub type R = crate :: R < PwmFreqH4Spec > ;
#[doc = "Register `PWM_FREQ_H4` writer"] pub type W = crate :: W < PwmFreqH4Spec > ;
#[doc = "Field `pwm_freq_h_4` reader - PWM0 clock divider high 16 bits"] pub type PwmFreqH4R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_h_4` writer - PWM0 clock divider high 16 bits"] pub type PwmFreqH4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_4 (& self) -> PwmFreqH4R { PwmFreqH4R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_4 (& mut self) -> PwmFreqH4W < '_ , PwmFreqH4Spec > { PwmFreqH4W :: new (self , 0) } }
#[doc = "PWM4 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqH4Spec ; impl crate :: RegisterSpec for PwmFreqH4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_h4::R`](R) reader structure"] impl crate :: Readable for PwmFreqH4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_h4::W`](W) writer structure"] impl crate :: Writable for PwmFreqH4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_H4 to value 0"] impl crate :: Resettable for PwmFreqH4Spec { } }
#[doc = "PWM_DUTY_L4 (rw) register accessor: PWM4 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l4`] module"]
#[doc (alias = "PWM_DUTY_L4")] pub type PwmDutyL4 = crate :: Reg < pwm_duty_l4 :: PwmDutyL4Spec > ;
#[doc = "PWM4 duty cycle low 16 bits"] pub mod pwm_duty_l4 {
#[doc = "Register `PWM_DUTY_L4` reader"] pub type R = crate :: R < PwmDutyL4Spec > ;
#[doc = "Register `PWM_DUTY_L4` writer"] pub type W = crate :: W < PwmDutyL4Spec > ;
#[doc = "Field `pwm_duty_l_4` reader - PWM0 duty cycle low 16 bits"] pub type PwmDutyL4R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_l_4` writer - PWM0 duty cycle low 16 bits"] pub type PwmDutyL4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_4 (& self) -> PwmDutyL4R { PwmDutyL4R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_4 (& mut self) -> PwmDutyL4W < '_ , PwmDutyL4Spec > { PwmDutyL4W :: new (self , 0) } }
#[doc = "PWM4 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyL4Spec ; impl crate :: RegisterSpec for PwmDutyL4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_l4::R`](R) reader structure"] impl crate :: Readable for PwmDutyL4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_l4::W`](W) writer structure"] impl crate :: Writable for PwmDutyL4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_L4 to value 0"] impl crate :: Resettable for PwmDutyL4Spec { } }
#[doc = "PWM_DUTY_H4 (rw) register accessor: PWM4 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h4`] module"]
#[doc (alias = "PWM_DUTY_H4")] pub type PwmDutyH4 = crate :: Reg < pwm_duty_h4 :: PwmDutyH4Spec > ;
#[doc = "PWM4 duty cycle high 16 bits"] pub mod pwm_duty_h4 {
#[doc = "Register `PWM_DUTY_H4` reader"] pub type R = crate :: R < PwmDutyH4Spec > ;
#[doc = "Register `PWM_DUTY_H4` writer"] pub type W = crate :: W < PwmDutyH4Spec > ;
#[doc = "Field `pwm_duty_h_4` reader - PWM0 duty cycle high 16 bits"] pub type PwmDutyH4R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_h_4` writer - PWM0 duty cycle high 16 bits"] pub type PwmDutyH4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_4 (& self) -> PwmDutyH4R { PwmDutyH4R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_4 (& mut self) -> PwmDutyH4W < '_ , PwmDutyH4Spec > { PwmDutyH4W :: new (self , 0) } }
#[doc = "PWM4 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyH4Spec ; impl crate :: RegisterSpec for PwmDutyH4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_h4::R`](R) reader structure"] impl crate :: Readable for PwmDutyH4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_h4::W`](W) writer structure"] impl crate :: Writable for PwmDutyH4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_H4 to value 0"] impl crate :: Resettable for PwmDutyH4Spec { } }
#[doc = "PWM_PERIODLOAD_FLAG4 (rw) register accessor: PWM4 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag4`] module"]
#[doc (alias = "PWM_PERIODLOAD_FLAG4")] pub type PwmPeriodloadFlag4 = crate :: Reg < pwm_periodload_flag4 :: PwmPeriodloadFlag4Spec > ;
#[doc = "PWM4 period load flag"] pub mod pwm_periodload_flag4 {
#[doc = "Register `PWM_PERIODLOAD_FLAG4` reader"] pub type R = crate :: R < PwmPeriodloadFlag4Spec > ;
#[doc = "Register `PWM_PERIODLOAD_FLAG4` writer"] pub type W = crate :: W < PwmPeriodloadFlag4Spec > ;
#[doc = "Field `pwm_periodload_flag_4` reader - Period load complete flag"] pub type PwmPeriodloadFlag4R = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Period load complete flag"]
#[inline (always)] pub fn pwm_periodload_flag_4 (& self) -> PwmPeriodloadFlag4R { PwmPeriodloadFlag4R :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "PWM4 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodloadFlag4Spec ; impl crate :: RegisterSpec for PwmPeriodloadFlag4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodload_flag4::R`](R) reader structure"] impl crate :: Readable for PwmPeriodloadFlag4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag4::W`](W) writer structure"] impl crate :: Writable for PwmPeriodloadFlag4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG4 to value 0"] impl crate :: Resettable for PwmPeriodloadFlag4Spec { } }
#[doc = "PWM_PERIOD_VAL4 (rw) register accessor: PWM4 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val4`] module"]
#[doc (alias = "PWM_PERIOD_VAL4")] pub type PwmPeriodVal4 = crate :: Reg < pwm_period_val4 :: PwmPeriodVal4Spec > ;
#[doc = "PWM4 pulse count value"] pub mod pwm_period_val4 {
#[doc = "Register `PWM_PERIOD_VAL4` reader"] pub type R = crate :: R < PwmPeriodVal4Spec > ;
#[doc = "Register `PWM_PERIOD_VAL4` writer"] pub type W = crate :: W < PwmPeriodVal4Spec > ;
#[doc = "Field `pwm_period_val_4` reader - Pulse count for stepping mode"] pub type PwmPeriodVal4R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_period_val_4` writer - Pulse count for stepping mode"] pub type PwmPeriodVal4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_4 (& self) -> PwmPeriodVal4R { PwmPeriodVal4R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_4 (& mut self) -> PwmPeriodVal4W < '_ , PwmPeriodVal4Spec > { PwmPeriodVal4W :: new (self , 0) } }
#[doc = "PWM4 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodVal4Spec ; impl crate :: RegisterSpec for PwmPeriodVal4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_period_val4::R`](R) reader structure"] impl crate :: Readable for PwmPeriodVal4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_period_val4::W`](W) writer structure"] impl crate :: Writable for PwmPeriodVal4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIOD_VAL4 to value 0"] impl crate :: Resettable for PwmPeriodVal4Spec { } }
#[doc = "PWM_PERIODCNT4 (rw) register accessor: PWM4 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt4`] module"]
#[doc (alias = "PWM_PERIODCNT4")] pub type PwmPeriodcnt4 = crate :: Reg < pwm_periodcnt4 :: PwmPeriodcnt4Spec > ;
#[doc = "PWM4 pulse count current value"] pub mod pwm_periodcnt4 {
#[doc = "Register `PWM_PERIODCNT4` reader"] pub type R = crate :: R < PwmPeriodcnt4Spec > ;
#[doc = "Register `PWM_PERIODCNT4` writer"] pub type W = crate :: W < PwmPeriodcnt4Spec > ;
#[doc = "Field `pwm_periodcnt_4` reader - Current pulse count"] pub type PwmPeriodcnt4R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Current pulse count"]
#[inline (always)] pub fn pwm_periodcnt_4 (& self) -> PwmPeriodcnt4R { PwmPeriodcnt4R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "PWM4 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodcnt4Spec ; impl crate :: RegisterSpec for PwmPeriodcnt4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodcnt4::R`](R) reader structure"] impl crate :: Readable for PwmPeriodcnt4Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodcnt4::W`](W) writer structure"] impl crate :: Writable for PwmPeriodcnt4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODCNT4 to value 0"] impl crate :: Resettable for PwmPeriodcnt4Spec { } }
#[doc = "PWM_EN5 (rw) register accessor: PWM5 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en5`] module"]
#[doc (alias = "PWM_EN5")] pub type PwmEn5 = crate :: Reg < pwm_en5 :: PwmEn5Spec > ;
#[doc = "PWM5 enable"] pub mod pwm_en5 {
#[doc = "Register `PWM_EN5` reader"] pub type R = crate :: R < PwmEn5Spec > ;
#[doc = "Register `PWM_EN5` writer"] pub type W = crate :: W < PwmEn5Spec > ;
#[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmEn5 {
#[doc = "0: PWM disabled, output low"] Off = 0 ,
#[doc = "1: PWM enabled"] On = 1 , } impl From < PwmEn5 > for bool {
#[inline (always)] fn from (variant : PwmEn5) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_en_5` reader - PWM0 enable: 0=off; 1=on"] pub type PwmEn5R = crate :: BitReader < PwmEn5 > ; impl PwmEn5R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmEn5 { match self . bits { false => PwmEn5 :: Off , true => PwmEn5 :: On , } }
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn is_off (& self) -> bool { * self == PwmEn5 :: Off }
#[doc = "PWM enabled"]
#[inline (always)] pub fn is_on (& self) -> bool { * self == PwmEn5 :: On } }
#[doc = "Field `pwm_en_5` writer - PWM0 enable: 0=off; 1=on"] pub type PwmEn5W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmEn5 > ; impl < 'a , REG > PwmEn5W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn5 :: Off) }
#[doc = "PWM enabled"]
#[inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn5 :: On) } } impl R {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_5 (& self) -> PwmEn5R { PwmEn5R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_5 (& mut self) -> PwmEn5W < '_ , PwmEn5Spec > { PwmEn5W :: new (self , 0) } }
#[doc = "PWM5 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmEn5Spec ; impl crate :: RegisterSpec for PwmEn5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_en5::R`](R) reader structure"] impl crate :: Readable for PwmEn5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_en5::W`](W) writer structure"] impl crate :: Writable for PwmEn5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_EN5 to value 0"] impl crate :: Resettable for PwmEn5Spec { } }
#[doc = "PWM_PORTITY5 (rw) register accessor: PWM5 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity5`] module"]
#[doc (alias = "PWM_PORTITY5")] pub type PwmPortity5 = crate :: Reg < pwm_portity5 :: PwmPortity5Spec > ;
#[doc = "PWM5 polarity"] pub mod pwm_portity5 {
#[doc = "Register `PWM_PORTITY5` reader"] pub type R = crate :: R < PwmPortity5Spec > ;
#[doc = "Register `PWM_PORTITY5` writer"] pub type W = crate :: W < PwmPortity5Spec > ;
#[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmPoarity5 {
#[doc = "0: Normal polarity"] Normal = 0 ,
#[doc = "1: Inverted polarity"] Inverted = 1 , } impl From < PwmPoarity5 > for bool {
#[inline (always)] fn from (variant : PwmPoarity5) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_poarity_5` reader - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity5R = crate :: BitReader < PwmPoarity5 > ; impl PwmPoarity5R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmPoarity5 { match self . bits { false => PwmPoarity5 :: Normal , true => PwmPoarity5 :: Inverted , } }
#[doc = "Normal polarity"]
#[inline (always)] pub fn is_normal (& self) -> bool { * self == PwmPoarity5 :: Normal }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn is_inverted (& self) -> bool { * self == PwmPoarity5 :: Inverted } }
#[doc = "Field `pwm_poarity_5` writer - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity5W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmPoarity5 > ; impl < 'a , REG > PwmPoarity5W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "Normal polarity"]
#[inline (always)] pub fn normal (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity5 :: Normal) }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn inverted (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity5 :: Inverted) } } impl R {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_5 (& self) -> PwmPoarity5R { PwmPoarity5R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_5 (& mut self) -> PwmPoarity5W < '_ , PwmPortity5Spec > { PwmPoarity5W :: new (self , 0) } }
#[doc = "PWM5 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPortity5Spec ; impl crate :: RegisterSpec for PwmPortity5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_portity5::R`](R) reader structure"] impl crate :: Readable for PwmPortity5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_portity5::W`](W) writer structure"] impl crate :: Writable for PwmPortity5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PORTITY5 to value 0"] impl crate :: Resettable for PwmPortity5Spec { } }
#[doc = "PWM_OEN_CFG5 (rw) register accessor: PWM5 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg5`] module"]
#[doc (alias = "PWM_OEN_CFG5")] pub type PwmOenCfg5 = crate :: Reg < pwm_oen_cfg5 :: PwmOenCfg5Spec > ;
#[doc = "PWM5 high-impedance config"] pub mod pwm_oen_cfg5 {
#[doc = "Register `PWM_OEN_CFG5` reader"] pub type R = crate :: R < PwmOenCfg5Spec > ;
#[doc = "Register `PWM_OEN_CFG5` writer"] pub type W = crate :: W < PwmOenCfg5Spec > ;
#[doc = "Field `pwm_oen_cfg_5` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg5R = crate :: BitReader ;
#[doc = "Field `pwm_oen_cfg_5` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg5W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_5 (& self) -> PwmOenCfg5R { PwmOenCfg5R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_5 (& mut self) -> PwmOenCfg5W < '_ , PwmOenCfg5Spec > { PwmOenCfg5W :: new (self , 0) } }
#[doc = "PWM5 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOenCfg5Spec ; impl crate :: RegisterSpec for PwmOenCfg5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_oen_cfg5::R`](R) reader structure"] impl crate :: Readable for PwmOenCfg5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg5::W`](W) writer structure"] impl crate :: Writable for PwmOenCfg5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OEN_CFG5 to value 0"] impl crate :: Resettable for PwmOenCfg5Spec { } }
#[doc = "PWM_OFFSET_L5 (rw) register accessor: PWM5 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l5`] module"]
#[doc (alias = "PWM_OFFSET_L5")] pub type PwmOffsetL5 = crate :: Reg < pwm_offset_l5 :: PwmOffsetL5Spec > ;
#[doc = "PWM5 phase offset low 16 bits"] pub mod pwm_offset_l5 {
#[doc = "Register `PWM_OFFSET_L5` reader"] pub type R = crate :: R < PwmOffsetL5Spec > ;
#[doc = "Register `PWM_OFFSET_L5` writer"] pub type W = crate :: W < PwmOffsetL5Spec > ;
#[doc = "Field `pwm_offset_l_5` reader - PWM0 phase offset low 16 bits"] pub type PwmOffsetL5R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_l_5` writer - PWM0 phase offset low 16 bits"] pub type PwmOffsetL5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_5 (& self) -> PwmOffsetL5R { PwmOffsetL5R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_5 (& mut self) -> PwmOffsetL5W < '_ , PwmOffsetL5Spec > { PwmOffsetL5W :: new (self , 0) } }
#[doc = "PWM5 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetL5Spec ; impl crate :: RegisterSpec for PwmOffsetL5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_l5::R`](R) reader structure"] impl crate :: Readable for PwmOffsetL5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_l5::W`](W) writer structure"] impl crate :: Writable for PwmOffsetL5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_L5 to value 0"] impl crate :: Resettable for PwmOffsetL5Spec { } }
#[doc = "PWM_OFFSET_H5 (rw) register accessor: PWM5 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h5`] module"]
#[doc (alias = "PWM_OFFSET_H5")] pub type PwmOffsetH5 = crate :: Reg < pwm_offset_h5 :: PwmOffsetH5Spec > ;
#[doc = "PWM5 phase offset high 16 bits"] pub mod pwm_offset_h5 {
#[doc = "Register `PWM_OFFSET_H5` reader"] pub type R = crate :: R < PwmOffsetH5Spec > ;
#[doc = "Register `PWM_OFFSET_H5` writer"] pub type W = crate :: W < PwmOffsetH5Spec > ;
#[doc = "Field `pwm_offset_h_5` reader - PWM0 phase offset high 16 bits"] pub type PwmOffsetH5R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_h_5` writer - PWM0 phase offset high 16 bits"] pub type PwmOffsetH5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_5 (& self) -> PwmOffsetH5R { PwmOffsetH5R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_5 (& mut self) -> PwmOffsetH5W < '_ , PwmOffsetH5Spec > { PwmOffsetH5W :: new (self , 0) } }
#[doc = "PWM5 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetH5Spec ; impl crate :: RegisterSpec for PwmOffsetH5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_h5::R`](R) reader structure"] impl crate :: Readable for PwmOffsetH5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_h5::W`](W) writer structure"] impl crate :: Writable for PwmOffsetH5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_H5 to value 0"] impl crate :: Resettable for PwmOffsetH5Spec { } }
#[doc = "PWM_FREQ_L5 (rw) register accessor: PWM5 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l5`] module"]
#[doc (alias = "PWM_FREQ_L5")] pub type PwmFreqL5 = crate :: Reg < pwm_freq_l5 :: PwmFreqL5Spec > ;
#[doc = "PWM5 frequency low 16 bits"] pub mod pwm_freq_l5 {
#[doc = "Register `PWM_FREQ_L5` reader"] pub type R = crate :: R < PwmFreqL5Spec > ;
#[doc = "Register `PWM_FREQ_L5` writer"] pub type W = crate :: W < PwmFreqL5Spec > ;
#[doc = "Field `pwm_freq_l_5` reader - PWM0 clock divider low 16 bits"] pub type PwmFreqL5R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_l_5` writer - PWM0 clock divider low 16 bits"] pub type PwmFreqL5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_5 (& self) -> PwmFreqL5R { PwmFreqL5R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_5 (& mut self) -> PwmFreqL5W < '_ , PwmFreqL5Spec > { PwmFreqL5W :: new (self , 0) } }
#[doc = "PWM5 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqL5Spec ; impl crate :: RegisterSpec for PwmFreqL5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_l5::R`](R) reader structure"] impl crate :: Readable for PwmFreqL5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_l5::W`](W) writer structure"] impl crate :: Writable for PwmFreqL5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_L5 to value 0"] impl crate :: Resettable for PwmFreqL5Spec { } }
#[doc = "PWM_FREQ_H5 (rw) register accessor: PWM5 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h5`] module"]
#[doc (alias = "PWM_FREQ_H5")] pub type PwmFreqH5 = crate :: Reg < pwm_freq_h5 :: PwmFreqH5Spec > ;
#[doc = "PWM5 frequency high 16 bits"] pub mod pwm_freq_h5 {
#[doc = "Register `PWM_FREQ_H5` reader"] pub type R = crate :: R < PwmFreqH5Spec > ;
#[doc = "Register `PWM_FREQ_H5` writer"] pub type W = crate :: W < PwmFreqH5Spec > ;
#[doc = "Field `pwm_freq_h_5` reader - PWM0 clock divider high 16 bits"] pub type PwmFreqH5R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_h_5` writer - PWM0 clock divider high 16 bits"] pub type PwmFreqH5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_5 (& self) -> PwmFreqH5R { PwmFreqH5R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_5 (& mut self) -> PwmFreqH5W < '_ , PwmFreqH5Spec > { PwmFreqH5W :: new (self , 0) } }
#[doc = "PWM5 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqH5Spec ; impl crate :: RegisterSpec for PwmFreqH5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_h5::R`](R) reader structure"] impl crate :: Readable for PwmFreqH5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_h5::W`](W) writer structure"] impl crate :: Writable for PwmFreqH5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_H5 to value 0"] impl crate :: Resettable for PwmFreqH5Spec { } }
#[doc = "PWM_DUTY_L5 (rw) register accessor: PWM5 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l5`] module"]
#[doc (alias = "PWM_DUTY_L5")] pub type PwmDutyL5 = crate :: Reg < pwm_duty_l5 :: PwmDutyL5Spec > ;
#[doc = "PWM5 duty cycle low 16 bits"] pub mod pwm_duty_l5 {
#[doc = "Register `PWM_DUTY_L5` reader"] pub type R = crate :: R < PwmDutyL5Spec > ;
#[doc = "Register `PWM_DUTY_L5` writer"] pub type W = crate :: W < PwmDutyL5Spec > ;
#[doc = "Field `pwm_duty_l_5` reader - PWM0 duty cycle low 16 bits"] pub type PwmDutyL5R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_l_5` writer - PWM0 duty cycle low 16 bits"] pub type PwmDutyL5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_5 (& self) -> PwmDutyL5R { PwmDutyL5R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_5 (& mut self) -> PwmDutyL5W < '_ , PwmDutyL5Spec > { PwmDutyL5W :: new (self , 0) } }
#[doc = "PWM5 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyL5Spec ; impl crate :: RegisterSpec for PwmDutyL5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_l5::R`](R) reader structure"] impl crate :: Readable for PwmDutyL5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_l5::W`](W) writer structure"] impl crate :: Writable for PwmDutyL5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_L5 to value 0"] impl crate :: Resettable for PwmDutyL5Spec { } }
#[doc = "PWM_DUTY_H5 (rw) register accessor: PWM5 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h5`] module"]
#[doc (alias = "PWM_DUTY_H5")] pub type PwmDutyH5 = crate :: Reg < pwm_duty_h5 :: PwmDutyH5Spec > ;
#[doc = "PWM5 duty cycle high 16 bits"] pub mod pwm_duty_h5 {
#[doc = "Register `PWM_DUTY_H5` reader"] pub type R = crate :: R < PwmDutyH5Spec > ;
#[doc = "Register `PWM_DUTY_H5` writer"] pub type W = crate :: W < PwmDutyH5Spec > ;
#[doc = "Field `pwm_duty_h_5` reader - PWM0 duty cycle high 16 bits"] pub type PwmDutyH5R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_h_5` writer - PWM0 duty cycle high 16 bits"] pub type PwmDutyH5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_5 (& self) -> PwmDutyH5R { PwmDutyH5R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_5 (& mut self) -> PwmDutyH5W < '_ , PwmDutyH5Spec > { PwmDutyH5W :: new (self , 0) } }
#[doc = "PWM5 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyH5Spec ; impl crate :: RegisterSpec for PwmDutyH5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_h5::R`](R) reader structure"] impl crate :: Readable for PwmDutyH5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_h5::W`](W) writer structure"] impl crate :: Writable for PwmDutyH5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_H5 to value 0"] impl crate :: Resettable for PwmDutyH5Spec { } }
#[doc = "PWM_PERIODLOAD_FLAG5 (rw) register accessor: PWM5 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag5`] module"]
#[doc (alias = "PWM_PERIODLOAD_FLAG5")] pub type PwmPeriodloadFlag5 = crate :: Reg < pwm_periodload_flag5 :: PwmPeriodloadFlag5Spec > ;
#[doc = "PWM5 period load flag"] pub mod pwm_periodload_flag5 {
#[doc = "Register `PWM_PERIODLOAD_FLAG5` reader"] pub type R = crate :: R < PwmPeriodloadFlag5Spec > ;
#[doc = "Register `PWM_PERIODLOAD_FLAG5` writer"] pub type W = crate :: W < PwmPeriodloadFlag5Spec > ;
#[doc = "Field `pwm_periodload_flag_5` reader - Period load complete flag"] pub type PwmPeriodloadFlag5R = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Period load complete flag"]
#[inline (always)] pub fn pwm_periodload_flag_5 (& self) -> PwmPeriodloadFlag5R { PwmPeriodloadFlag5R :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "PWM5 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodloadFlag5Spec ; impl crate :: RegisterSpec for PwmPeriodloadFlag5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodload_flag5::R`](R) reader structure"] impl crate :: Readable for PwmPeriodloadFlag5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag5::W`](W) writer structure"] impl crate :: Writable for PwmPeriodloadFlag5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG5 to value 0"] impl crate :: Resettable for PwmPeriodloadFlag5Spec { } }
#[doc = "PWM_PERIOD_VAL5 (rw) register accessor: PWM5 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val5`] module"]
#[doc (alias = "PWM_PERIOD_VAL5")] pub type PwmPeriodVal5 = crate :: Reg < pwm_period_val5 :: PwmPeriodVal5Spec > ;
#[doc = "PWM5 pulse count value"] pub mod pwm_period_val5 {
#[doc = "Register `PWM_PERIOD_VAL5` reader"] pub type R = crate :: R < PwmPeriodVal5Spec > ;
#[doc = "Register `PWM_PERIOD_VAL5` writer"] pub type W = crate :: W < PwmPeriodVal5Spec > ;
#[doc = "Field `pwm_period_val_5` reader - Pulse count for stepping mode"] pub type PwmPeriodVal5R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_period_val_5` writer - Pulse count for stepping mode"] pub type PwmPeriodVal5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_5 (& self) -> PwmPeriodVal5R { PwmPeriodVal5R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_5 (& mut self) -> PwmPeriodVal5W < '_ , PwmPeriodVal5Spec > { PwmPeriodVal5W :: new (self , 0) } }
#[doc = "PWM5 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodVal5Spec ; impl crate :: RegisterSpec for PwmPeriodVal5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_period_val5::R`](R) reader structure"] impl crate :: Readable for PwmPeriodVal5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_period_val5::W`](W) writer structure"] impl crate :: Writable for PwmPeriodVal5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIOD_VAL5 to value 0"] impl crate :: Resettable for PwmPeriodVal5Spec { } }
#[doc = "PWM_PERIODCNT5 (rw) register accessor: PWM5 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt5`] module"]
#[doc (alias = "PWM_PERIODCNT5")] pub type PwmPeriodcnt5 = crate :: Reg < pwm_periodcnt5 :: PwmPeriodcnt5Spec > ;
#[doc = "PWM5 pulse count current value"] pub mod pwm_periodcnt5 {
#[doc = "Register `PWM_PERIODCNT5` reader"] pub type R = crate :: R < PwmPeriodcnt5Spec > ;
#[doc = "Register `PWM_PERIODCNT5` writer"] pub type W = crate :: W < PwmPeriodcnt5Spec > ;
#[doc = "Field `pwm_periodcnt_5` reader - Current pulse count"] pub type PwmPeriodcnt5R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Current pulse count"]
#[inline (always)] pub fn pwm_periodcnt_5 (& self) -> PwmPeriodcnt5R { PwmPeriodcnt5R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "PWM5 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodcnt5Spec ; impl crate :: RegisterSpec for PwmPeriodcnt5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodcnt5::R`](R) reader structure"] impl crate :: Readable for PwmPeriodcnt5Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodcnt5::W`](W) writer structure"] impl crate :: Writable for PwmPeriodcnt5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODCNT5 to value 0"] impl crate :: Resettable for PwmPeriodcnt5Spec { } }
#[doc = "PWM_EN6 (rw) register accessor: PWM6 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en6`] module"]
#[doc (alias = "PWM_EN6")] pub type PwmEn6 = crate :: Reg < pwm_en6 :: PwmEn6Spec > ;
#[doc = "PWM6 enable"] pub mod pwm_en6 {
#[doc = "Register `PWM_EN6` reader"] pub type R = crate :: R < PwmEn6Spec > ;
#[doc = "Register `PWM_EN6` writer"] pub type W = crate :: W < PwmEn6Spec > ;
#[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmEn6 {
#[doc = "0: PWM disabled, output low"] Off = 0 ,
#[doc = "1: PWM enabled"] On = 1 , } impl From < PwmEn6 > for bool {
#[inline (always)] fn from (variant : PwmEn6) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_en_6` reader - PWM0 enable: 0=off; 1=on"] pub type PwmEn6R = crate :: BitReader < PwmEn6 > ; impl PwmEn6R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmEn6 { match self . bits { false => PwmEn6 :: Off , true => PwmEn6 :: On , } }
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn is_off (& self) -> bool { * self == PwmEn6 :: Off }
#[doc = "PWM enabled"]
#[inline (always)] pub fn is_on (& self) -> bool { * self == PwmEn6 :: On } }
#[doc = "Field `pwm_en_6` writer - PWM0 enable: 0=off; 1=on"] pub type PwmEn6W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmEn6 > ; impl < 'a , REG > PwmEn6W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn6 :: Off) }
#[doc = "PWM enabled"]
#[inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn6 :: On) } } impl R {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_6 (& self) -> PwmEn6R { PwmEn6R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_6 (& mut self) -> PwmEn6W < '_ , PwmEn6Spec > { PwmEn6W :: new (self , 0) } }
#[doc = "PWM6 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmEn6Spec ; impl crate :: RegisterSpec for PwmEn6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_en6::R`](R) reader structure"] impl crate :: Readable for PwmEn6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_en6::W`](W) writer structure"] impl crate :: Writable for PwmEn6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_EN6 to value 0"] impl crate :: Resettable for PwmEn6Spec { } }
#[doc = "PWM_PORTITY6 (rw) register accessor: PWM6 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity6`] module"]
#[doc (alias = "PWM_PORTITY6")] pub type PwmPortity6 = crate :: Reg < pwm_portity6 :: PwmPortity6Spec > ;
#[doc = "PWM6 polarity"] pub mod pwm_portity6 {
#[doc = "Register `PWM_PORTITY6` reader"] pub type R = crate :: R < PwmPortity6Spec > ;
#[doc = "Register `PWM_PORTITY6` writer"] pub type W = crate :: W < PwmPortity6Spec > ;
#[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmPoarity6 {
#[doc = "0: Normal polarity"] Normal = 0 ,
#[doc = "1: Inverted polarity"] Inverted = 1 , } impl From < PwmPoarity6 > for bool {
#[inline (always)] fn from (variant : PwmPoarity6) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_poarity_6` reader - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity6R = crate :: BitReader < PwmPoarity6 > ; impl PwmPoarity6R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmPoarity6 { match self . bits { false => PwmPoarity6 :: Normal , true => PwmPoarity6 :: Inverted , } }
#[doc = "Normal polarity"]
#[inline (always)] pub fn is_normal (& self) -> bool { * self == PwmPoarity6 :: Normal }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn is_inverted (& self) -> bool { * self == PwmPoarity6 :: Inverted } }
#[doc = "Field `pwm_poarity_6` writer - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity6W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmPoarity6 > ; impl < 'a , REG > PwmPoarity6W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "Normal polarity"]
#[inline (always)] pub fn normal (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity6 :: Normal) }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn inverted (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity6 :: Inverted) } } impl R {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_6 (& self) -> PwmPoarity6R { PwmPoarity6R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_6 (& mut self) -> PwmPoarity6W < '_ , PwmPortity6Spec > { PwmPoarity6W :: new (self , 0) } }
#[doc = "PWM6 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPortity6Spec ; impl crate :: RegisterSpec for PwmPortity6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_portity6::R`](R) reader structure"] impl crate :: Readable for PwmPortity6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_portity6::W`](W) writer structure"] impl crate :: Writable for PwmPortity6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PORTITY6 to value 0"] impl crate :: Resettable for PwmPortity6Spec { } }
#[doc = "PWM_OEN_CFG6 (rw) register accessor: PWM6 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg6`] module"]
#[doc (alias = "PWM_OEN_CFG6")] pub type PwmOenCfg6 = crate :: Reg < pwm_oen_cfg6 :: PwmOenCfg6Spec > ;
#[doc = "PWM6 high-impedance config"] pub mod pwm_oen_cfg6 {
#[doc = "Register `PWM_OEN_CFG6` reader"] pub type R = crate :: R < PwmOenCfg6Spec > ;
#[doc = "Register `PWM_OEN_CFG6` writer"] pub type W = crate :: W < PwmOenCfg6Spec > ;
#[doc = "Field `pwm_oen_cfg_6` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg6R = crate :: BitReader ;
#[doc = "Field `pwm_oen_cfg_6` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg6W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_6 (& self) -> PwmOenCfg6R { PwmOenCfg6R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_6 (& mut self) -> PwmOenCfg6W < '_ , PwmOenCfg6Spec > { PwmOenCfg6W :: new (self , 0) } }
#[doc = "PWM6 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOenCfg6Spec ; impl crate :: RegisterSpec for PwmOenCfg6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_oen_cfg6::R`](R) reader structure"] impl crate :: Readable for PwmOenCfg6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg6::W`](W) writer structure"] impl crate :: Writable for PwmOenCfg6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OEN_CFG6 to value 0"] impl crate :: Resettable for PwmOenCfg6Spec { } }
#[doc = "PWM_OFFSET_L6 (rw) register accessor: PWM6 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l6`] module"]
#[doc (alias = "PWM_OFFSET_L6")] pub type PwmOffsetL6 = crate :: Reg < pwm_offset_l6 :: PwmOffsetL6Spec > ;
#[doc = "PWM6 phase offset low 16 bits"] pub mod pwm_offset_l6 {
#[doc = "Register `PWM_OFFSET_L6` reader"] pub type R = crate :: R < PwmOffsetL6Spec > ;
#[doc = "Register `PWM_OFFSET_L6` writer"] pub type W = crate :: W < PwmOffsetL6Spec > ;
#[doc = "Field `pwm_offset_l_6` reader - PWM0 phase offset low 16 bits"] pub type PwmOffsetL6R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_l_6` writer - PWM0 phase offset low 16 bits"] pub type PwmOffsetL6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_6 (& self) -> PwmOffsetL6R { PwmOffsetL6R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_6 (& mut self) -> PwmOffsetL6W < '_ , PwmOffsetL6Spec > { PwmOffsetL6W :: new (self , 0) } }
#[doc = "PWM6 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetL6Spec ; impl crate :: RegisterSpec for PwmOffsetL6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_l6::R`](R) reader structure"] impl crate :: Readable for PwmOffsetL6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_l6::W`](W) writer structure"] impl crate :: Writable for PwmOffsetL6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_L6 to value 0"] impl crate :: Resettable for PwmOffsetL6Spec { } }
#[doc = "PWM_OFFSET_H6 (rw) register accessor: PWM6 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h6`] module"]
#[doc (alias = "PWM_OFFSET_H6")] pub type PwmOffsetH6 = crate :: Reg < pwm_offset_h6 :: PwmOffsetH6Spec > ;
#[doc = "PWM6 phase offset high 16 bits"] pub mod pwm_offset_h6 {
#[doc = "Register `PWM_OFFSET_H6` reader"] pub type R = crate :: R < PwmOffsetH6Spec > ;
#[doc = "Register `PWM_OFFSET_H6` writer"] pub type W = crate :: W < PwmOffsetH6Spec > ;
#[doc = "Field `pwm_offset_h_6` reader - PWM0 phase offset high 16 bits"] pub type PwmOffsetH6R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_h_6` writer - PWM0 phase offset high 16 bits"] pub type PwmOffsetH6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_6 (& self) -> PwmOffsetH6R { PwmOffsetH6R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_6 (& mut self) -> PwmOffsetH6W < '_ , PwmOffsetH6Spec > { PwmOffsetH6W :: new (self , 0) } }
#[doc = "PWM6 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetH6Spec ; impl crate :: RegisterSpec for PwmOffsetH6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_h6::R`](R) reader structure"] impl crate :: Readable for PwmOffsetH6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_h6::W`](W) writer structure"] impl crate :: Writable for PwmOffsetH6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_H6 to value 0"] impl crate :: Resettable for PwmOffsetH6Spec { } }
#[doc = "PWM_FREQ_L6 (rw) register accessor: PWM6 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l6`] module"]
#[doc (alias = "PWM_FREQ_L6")] pub type PwmFreqL6 = crate :: Reg < pwm_freq_l6 :: PwmFreqL6Spec > ;
#[doc = "PWM6 frequency low 16 bits"] pub mod pwm_freq_l6 {
#[doc = "Register `PWM_FREQ_L6` reader"] pub type R = crate :: R < PwmFreqL6Spec > ;
#[doc = "Register `PWM_FREQ_L6` writer"] pub type W = crate :: W < PwmFreqL6Spec > ;
#[doc = "Field `pwm_freq_l_6` reader - PWM0 clock divider low 16 bits"] pub type PwmFreqL6R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_l_6` writer - PWM0 clock divider low 16 bits"] pub type PwmFreqL6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_6 (& self) -> PwmFreqL6R { PwmFreqL6R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_6 (& mut self) -> PwmFreqL6W < '_ , PwmFreqL6Spec > { PwmFreqL6W :: new (self , 0) } }
#[doc = "PWM6 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqL6Spec ; impl crate :: RegisterSpec for PwmFreqL6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_l6::R`](R) reader structure"] impl crate :: Readable for PwmFreqL6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_l6::W`](W) writer structure"] impl crate :: Writable for PwmFreqL6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_L6 to value 0"] impl crate :: Resettable for PwmFreqL6Spec { } }
#[doc = "PWM_FREQ_H6 (rw) register accessor: PWM6 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h6`] module"]
#[doc (alias = "PWM_FREQ_H6")] pub type PwmFreqH6 = crate :: Reg < pwm_freq_h6 :: PwmFreqH6Spec > ;
#[doc = "PWM6 frequency high 16 bits"] pub mod pwm_freq_h6 {
#[doc = "Register `PWM_FREQ_H6` reader"] pub type R = crate :: R < PwmFreqH6Spec > ;
#[doc = "Register `PWM_FREQ_H6` writer"] pub type W = crate :: W < PwmFreqH6Spec > ;
#[doc = "Field `pwm_freq_h_6` reader - PWM0 clock divider high 16 bits"] pub type PwmFreqH6R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_h_6` writer - PWM0 clock divider high 16 bits"] pub type PwmFreqH6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_6 (& self) -> PwmFreqH6R { PwmFreqH6R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_6 (& mut self) -> PwmFreqH6W < '_ , PwmFreqH6Spec > { PwmFreqH6W :: new (self , 0) } }
#[doc = "PWM6 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqH6Spec ; impl crate :: RegisterSpec for PwmFreqH6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_h6::R`](R) reader structure"] impl crate :: Readable for PwmFreqH6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_h6::W`](W) writer structure"] impl crate :: Writable for PwmFreqH6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_H6 to value 0"] impl crate :: Resettable for PwmFreqH6Spec { } }
#[doc = "PWM_DUTY_L6 (rw) register accessor: PWM6 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l6`] module"]
#[doc (alias = "PWM_DUTY_L6")] pub type PwmDutyL6 = crate :: Reg < pwm_duty_l6 :: PwmDutyL6Spec > ;
#[doc = "PWM6 duty cycle low 16 bits"] pub mod pwm_duty_l6 {
#[doc = "Register `PWM_DUTY_L6` reader"] pub type R = crate :: R < PwmDutyL6Spec > ;
#[doc = "Register `PWM_DUTY_L6` writer"] pub type W = crate :: W < PwmDutyL6Spec > ;
#[doc = "Field `pwm_duty_l_6` reader - PWM0 duty cycle low 16 bits"] pub type PwmDutyL6R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_l_6` writer - PWM0 duty cycle low 16 bits"] pub type PwmDutyL6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_6 (& self) -> PwmDutyL6R { PwmDutyL6R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_6 (& mut self) -> PwmDutyL6W < '_ , PwmDutyL6Spec > { PwmDutyL6W :: new (self , 0) } }
#[doc = "PWM6 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyL6Spec ; impl crate :: RegisterSpec for PwmDutyL6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_l6::R`](R) reader structure"] impl crate :: Readable for PwmDutyL6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_l6::W`](W) writer structure"] impl crate :: Writable for PwmDutyL6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_L6 to value 0"] impl crate :: Resettable for PwmDutyL6Spec { } }
#[doc = "PWM_DUTY_H6 (rw) register accessor: PWM6 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h6`] module"]
#[doc (alias = "PWM_DUTY_H6")] pub type PwmDutyH6 = crate :: Reg < pwm_duty_h6 :: PwmDutyH6Spec > ;
#[doc = "PWM6 duty cycle high 16 bits"] pub mod pwm_duty_h6 {
#[doc = "Register `PWM_DUTY_H6` reader"] pub type R = crate :: R < PwmDutyH6Spec > ;
#[doc = "Register `PWM_DUTY_H6` writer"] pub type W = crate :: W < PwmDutyH6Spec > ;
#[doc = "Field `pwm_duty_h_6` reader - PWM0 duty cycle high 16 bits"] pub type PwmDutyH6R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_h_6` writer - PWM0 duty cycle high 16 bits"] pub type PwmDutyH6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_6 (& self) -> PwmDutyH6R { PwmDutyH6R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_6 (& mut self) -> PwmDutyH6W < '_ , PwmDutyH6Spec > { PwmDutyH6W :: new (self , 0) } }
#[doc = "PWM6 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyH6Spec ; impl crate :: RegisterSpec for PwmDutyH6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_h6::R`](R) reader structure"] impl crate :: Readable for PwmDutyH6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_h6::W`](W) writer structure"] impl crate :: Writable for PwmDutyH6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_H6 to value 0"] impl crate :: Resettable for PwmDutyH6Spec { } }
#[doc = "PWM_PERIODLOAD_FLAG6 (rw) register accessor: PWM6 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag6`] module"]
#[doc (alias = "PWM_PERIODLOAD_FLAG6")] pub type PwmPeriodloadFlag6 = crate :: Reg < pwm_periodload_flag6 :: PwmPeriodloadFlag6Spec > ;
#[doc = "PWM6 period load flag"] pub mod pwm_periodload_flag6 {
#[doc = "Register `PWM_PERIODLOAD_FLAG6` reader"] pub type R = crate :: R < PwmPeriodloadFlag6Spec > ;
#[doc = "Register `PWM_PERIODLOAD_FLAG6` writer"] pub type W = crate :: W < PwmPeriodloadFlag6Spec > ;
#[doc = "Field `pwm_periodload_flag_6` reader - Period load complete flag"] pub type PwmPeriodloadFlag6R = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Period load complete flag"]
#[inline (always)] pub fn pwm_periodload_flag_6 (& self) -> PwmPeriodloadFlag6R { PwmPeriodloadFlag6R :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "PWM6 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodloadFlag6Spec ; impl crate :: RegisterSpec for PwmPeriodloadFlag6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodload_flag6::R`](R) reader structure"] impl crate :: Readable for PwmPeriodloadFlag6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag6::W`](W) writer structure"] impl crate :: Writable for PwmPeriodloadFlag6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG6 to value 0"] impl crate :: Resettable for PwmPeriodloadFlag6Spec { } }
#[doc = "PWM_PERIOD_VAL6 (rw) register accessor: PWM6 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val6`] module"]
#[doc (alias = "PWM_PERIOD_VAL6")] pub type PwmPeriodVal6 = crate :: Reg < pwm_period_val6 :: PwmPeriodVal6Spec > ;
#[doc = "PWM6 pulse count value"] pub mod pwm_period_val6 {
#[doc = "Register `PWM_PERIOD_VAL6` reader"] pub type R = crate :: R < PwmPeriodVal6Spec > ;
#[doc = "Register `PWM_PERIOD_VAL6` writer"] pub type W = crate :: W < PwmPeriodVal6Spec > ;
#[doc = "Field `pwm_period_val_6` reader - Pulse count for stepping mode"] pub type PwmPeriodVal6R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_period_val_6` writer - Pulse count for stepping mode"] pub type PwmPeriodVal6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_6 (& self) -> PwmPeriodVal6R { PwmPeriodVal6R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_6 (& mut self) -> PwmPeriodVal6W < '_ , PwmPeriodVal6Spec > { PwmPeriodVal6W :: new (self , 0) } }
#[doc = "PWM6 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodVal6Spec ; impl crate :: RegisterSpec for PwmPeriodVal6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_period_val6::R`](R) reader structure"] impl crate :: Readable for PwmPeriodVal6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_period_val6::W`](W) writer structure"] impl crate :: Writable for PwmPeriodVal6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIOD_VAL6 to value 0"] impl crate :: Resettable for PwmPeriodVal6Spec { } }
#[doc = "PWM_PERIODCNT6 (rw) register accessor: PWM6 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt6`] module"]
#[doc (alias = "PWM_PERIODCNT6")] pub type PwmPeriodcnt6 = crate :: Reg < pwm_periodcnt6 :: PwmPeriodcnt6Spec > ;
#[doc = "PWM6 pulse count current value"] pub mod pwm_periodcnt6 {
#[doc = "Register `PWM_PERIODCNT6` reader"] pub type R = crate :: R < PwmPeriodcnt6Spec > ;
#[doc = "Register `PWM_PERIODCNT6` writer"] pub type W = crate :: W < PwmPeriodcnt6Spec > ;
#[doc = "Field `pwm_periodcnt_6` reader - Current pulse count"] pub type PwmPeriodcnt6R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Current pulse count"]
#[inline (always)] pub fn pwm_periodcnt_6 (& self) -> PwmPeriodcnt6R { PwmPeriodcnt6R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "PWM6 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodcnt6Spec ; impl crate :: RegisterSpec for PwmPeriodcnt6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodcnt6::R`](R) reader structure"] impl crate :: Readable for PwmPeriodcnt6Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodcnt6::W`](W) writer structure"] impl crate :: Writable for PwmPeriodcnt6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODCNT6 to value 0"] impl crate :: Resettable for PwmPeriodcnt6Spec { } }
#[doc = "PWM_EN7 (rw) register accessor: PWM7 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en7`] module"]
#[doc (alias = "PWM_EN7")] pub type PwmEn7 = crate :: Reg < pwm_en7 :: PwmEn7Spec > ;
#[doc = "PWM7 enable"] pub mod pwm_en7 {
#[doc = "Register `PWM_EN7` reader"] pub type R = crate :: R < PwmEn7Spec > ;
#[doc = "Register `PWM_EN7` writer"] pub type W = crate :: W < PwmEn7Spec > ;
#[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmEn7 {
#[doc = "0: PWM disabled, output low"] Off = 0 ,
#[doc = "1: PWM enabled"] On = 1 , } impl From < PwmEn7 > for bool {
#[inline (always)] fn from (variant : PwmEn7) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_en_7` reader - PWM0 enable: 0=off; 1=on"] pub type PwmEn7R = crate :: BitReader < PwmEn7 > ; impl PwmEn7R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmEn7 { match self . bits { false => PwmEn7 :: Off , true => PwmEn7 :: On , } }
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn is_off (& self) -> bool { * self == PwmEn7 :: Off }
#[doc = "PWM enabled"]
#[inline (always)] pub fn is_on (& self) -> bool { * self == PwmEn7 :: On } }
#[doc = "Field `pwm_en_7` writer - PWM0 enable: 0=off; 1=on"] pub type PwmEn7W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmEn7 > ; impl < 'a , REG > PwmEn7W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "PWM disabled, output low"]
#[inline (always)] pub fn off (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn7 :: Off) }
#[doc = "PWM enabled"]
#[inline (always)] pub fn on (self) -> & 'a mut crate :: W < REG > { self . variant (PwmEn7 :: On) } } impl R {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_7 (& self) -> PwmEn7R { PwmEn7R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
#[inline (always)] pub fn pwm_en_7 (& mut self) -> PwmEn7W < '_ , PwmEn7Spec > { PwmEn7W :: new (self , 0) } }
#[doc = "PWM7 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmEn7Spec ; impl crate :: RegisterSpec for PwmEn7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_en7::R`](R) reader structure"] impl crate :: Readable for PwmEn7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_en7::W`](W) writer structure"] impl crate :: Writable for PwmEn7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_EN7 to value 0"] impl crate :: Resettable for PwmEn7Spec { } }
#[doc = "PWM_PORTITY7 (rw) register accessor: PWM7 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity7`] module"]
#[doc (alias = "PWM_PORTITY7")] pub type PwmPortity7 = crate :: Reg < pwm_portity7 :: PwmPortity7Spec > ;
#[doc = "PWM7 polarity"] pub mod pwm_portity7 {
#[doc = "Register `PWM_PORTITY7` reader"] pub type R = crate :: R < PwmPortity7Spec > ;
#[doc = "Register `PWM_PORTITY7` writer"] pub type W = crate :: W < PwmPortity7Spec > ;
#[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum PwmPoarity7 {
#[doc = "0: Normal polarity"] Normal = 0 ,
#[doc = "1: Inverted polarity"] Inverted = 1 , } impl From < PwmPoarity7 > for bool {
#[inline (always)] fn from (variant : PwmPoarity7) -> Self { variant as u8 != 0 } }
#[doc = "Field `pwm_poarity_7` reader - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity7R = crate :: BitReader < PwmPoarity7 > ; impl PwmPoarity7R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> PwmPoarity7 { match self . bits { false => PwmPoarity7 :: Normal , true => PwmPoarity7 :: Inverted , } }
#[doc = "Normal polarity"]
#[inline (always)] pub fn is_normal (& self) -> bool { * self == PwmPoarity7 :: Normal }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn is_inverted (& self) -> bool { * self == PwmPoarity7 :: Inverted } }
#[doc = "Field `pwm_poarity_7` writer - PWM0 polarity: 0=normal; 1=inverted"] pub type PwmPoarity7W < 'a , REG > = crate :: BitWriter < 'a , REG , PwmPoarity7 > ; impl < 'a , REG > PwmPoarity7W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "Normal polarity"]
#[inline (always)] pub fn normal (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity7 :: Normal) }
#[doc = "Inverted polarity"]
#[inline (always)] pub fn inverted (self) -> & 'a mut crate :: W < REG > { self . variant (PwmPoarity7 :: Inverted) } } impl R {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_7 (& self) -> PwmPoarity7R { PwmPoarity7R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
#[inline (always)] pub fn pwm_poarity_7 (& mut self) -> PwmPoarity7W < '_ , PwmPortity7Spec > { PwmPoarity7W :: new (self , 0) } }
#[doc = "PWM7 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPortity7Spec ; impl crate :: RegisterSpec for PwmPortity7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_portity7::R`](R) reader structure"] impl crate :: Readable for PwmPortity7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_portity7::W`](W) writer structure"] impl crate :: Writable for PwmPortity7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PORTITY7 to value 0"] impl crate :: Resettable for PwmPortity7Spec { } }
#[doc = "PWM_OEN_CFG7 (rw) register accessor: PWM7 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg7`] module"]
#[doc (alias = "PWM_OEN_CFG7")] pub type PwmOenCfg7 = crate :: Reg < pwm_oen_cfg7 :: PwmOenCfg7Spec > ;
#[doc = "PWM7 high-impedance config"] pub mod pwm_oen_cfg7 {
#[doc = "Register `PWM_OEN_CFG7` reader"] pub type R = crate :: R < PwmOenCfg7Spec > ;
#[doc = "Register `PWM_OEN_CFG7` writer"] pub type W = crate :: W < PwmOenCfg7Spec > ;
#[doc = "Field `pwm_oen_cfg_7` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg7R = crate :: BitReader ;
#[doc = "Field `pwm_oen_cfg_7` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"] pub type PwmOenCfg7W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_7 (& self) -> PwmOenCfg7R { PwmOenCfg7R :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
#[inline (always)] pub fn pwm_oen_cfg_7 (& mut self) -> PwmOenCfg7W < '_ , PwmOenCfg7Spec > { PwmOenCfg7W :: new (self , 0) } }
#[doc = "PWM7 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOenCfg7Spec ; impl crate :: RegisterSpec for PwmOenCfg7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_oen_cfg7::R`](R) reader structure"] impl crate :: Readable for PwmOenCfg7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg7::W`](W) writer structure"] impl crate :: Writable for PwmOenCfg7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OEN_CFG7 to value 0"] impl crate :: Resettable for PwmOenCfg7Spec { } }
#[doc = "PWM_OFFSET_L7 (rw) register accessor: PWM7 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l7`] module"]
#[doc (alias = "PWM_OFFSET_L7")] pub type PwmOffsetL7 = crate :: Reg < pwm_offset_l7 :: PwmOffsetL7Spec > ;
#[doc = "PWM7 phase offset low 16 bits"] pub mod pwm_offset_l7 {
#[doc = "Register `PWM_OFFSET_L7` reader"] pub type R = crate :: R < PwmOffsetL7Spec > ;
#[doc = "Register `PWM_OFFSET_L7` writer"] pub type W = crate :: W < PwmOffsetL7Spec > ;
#[doc = "Field `pwm_offset_l_7` reader - PWM0 phase offset low 16 bits"] pub type PwmOffsetL7R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_l_7` writer - PWM0 phase offset low 16 bits"] pub type PwmOffsetL7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_7 (& self) -> PwmOffsetL7R { PwmOffsetL7R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
#[inline (always)] pub fn pwm_offset_l_7 (& mut self) -> PwmOffsetL7W < '_ , PwmOffsetL7Spec > { PwmOffsetL7W :: new (self , 0) } }
#[doc = "PWM7 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetL7Spec ; impl crate :: RegisterSpec for PwmOffsetL7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_l7::R`](R) reader structure"] impl crate :: Readable for PwmOffsetL7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_l7::W`](W) writer structure"] impl crate :: Writable for PwmOffsetL7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_L7 to value 0"] impl crate :: Resettable for PwmOffsetL7Spec { } }
#[doc = "PWM_OFFSET_H7 (rw) register accessor: PWM7 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h7`] module"]
#[doc (alias = "PWM_OFFSET_H7")] pub type PwmOffsetH7 = crate :: Reg < pwm_offset_h7 :: PwmOffsetH7Spec > ;
#[doc = "PWM7 phase offset high 16 bits"] pub mod pwm_offset_h7 {
#[doc = "Register `PWM_OFFSET_H7` reader"] pub type R = crate :: R < PwmOffsetH7Spec > ;
#[doc = "Register `PWM_OFFSET_H7` writer"] pub type W = crate :: W < PwmOffsetH7Spec > ;
#[doc = "Field `pwm_offset_h_7` reader - PWM0 phase offset high 16 bits"] pub type PwmOffsetH7R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_offset_h_7` writer - PWM0 phase offset high 16 bits"] pub type PwmOffsetH7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_7 (& self) -> PwmOffsetH7R { PwmOffsetH7R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
#[inline (always)] pub fn pwm_offset_h_7 (& mut self) -> PwmOffsetH7W < '_ , PwmOffsetH7Spec > { PwmOffsetH7W :: new (self , 0) } }
#[doc = "PWM7 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmOffsetH7Spec ; impl crate :: RegisterSpec for PwmOffsetH7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_offset_h7::R`](R) reader structure"] impl crate :: Readable for PwmOffsetH7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_offset_h7::W`](W) writer structure"] impl crate :: Writable for PwmOffsetH7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_OFFSET_H7 to value 0"] impl crate :: Resettable for PwmOffsetH7Spec { } }
#[doc = "PWM_FREQ_L7 (rw) register accessor: PWM7 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l7`] module"]
#[doc (alias = "PWM_FREQ_L7")] pub type PwmFreqL7 = crate :: Reg < pwm_freq_l7 :: PwmFreqL7Spec > ;
#[doc = "PWM7 frequency low 16 bits"] pub mod pwm_freq_l7 {
#[doc = "Register `PWM_FREQ_L7` reader"] pub type R = crate :: R < PwmFreqL7Spec > ;
#[doc = "Register `PWM_FREQ_L7` writer"] pub type W = crate :: W < PwmFreqL7Spec > ;
#[doc = "Field `pwm_freq_l_7` reader - PWM0 clock divider low 16 bits"] pub type PwmFreqL7R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_l_7` writer - PWM0 clock divider low 16 bits"] pub type PwmFreqL7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_7 (& self) -> PwmFreqL7R { PwmFreqL7R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
#[inline (always)] pub fn pwm_freq_l_7 (& mut self) -> PwmFreqL7W < '_ , PwmFreqL7Spec > { PwmFreqL7W :: new (self , 0) } }
#[doc = "PWM7 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqL7Spec ; impl crate :: RegisterSpec for PwmFreqL7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_l7::R`](R) reader structure"] impl crate :: Readable for PwmFreqL7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_l7::W`](W) writer structure"] impl crate :: Writable for PwmFreqL7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_L7 to value 0"] impl crate :: Resettable for PwmFreqL7Spec { } }
#[doc = "PWM_FREQ_H7 (rw) register accessor: PWM7 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h7`] module"]
#[doc (alias = "PWM_FREQ_H7")] pub type PwmFreqH7 = crate :: Reg < pwm_freq_h7 :: PwmFreqH7Spec > ;
#[doc = "PWM7 frequency high 16 bits"] pub mod pwm_freq_h7 {
#[doc = "Register `PWM_FREQ_H7` reader"] pub type R = crate :: R < PwmFreqH7Spec > ;
#[doc = "Register `PWM_FREQ_H7` writer"] pub type W = crate :: W < PwmFreqH7Spec > ;
#[doc = "Field `pwm_freq_h_7` reader - PWM0 clock divider high 16 bits"] pub type PwmFreqH7R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_freq_h_7` writer - PWM0 clock divider high 16 bits"] pub type PwmFreqH7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_7 (& self) -> PwmFreqH7R { PwmFreqH7R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
#[inline (always)] pub fn pwm_freq_h_7 (& mut self) -> PwmFreqH7W < '_ , PwmFreqH7Spec > { PwmFreqH7W :: new (self , 0) } }
#[doc = "PWM7 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmFreqH7Spec ; impl crate :: RegisterSpec for PwmFreqH7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_freq_h7::R`](R) reader structure"] impl crate :: Readable for PwmFreqH7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_freq_h7::W`](W) writer structure"] impl crate :: Writable for PwmFreqH7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_FREQ_H7 to value 0"] impl crate :: Resettable for PwmFreqH7Spec { } }
#[doc = "PWM_DUTY_L7 (rw) register accessor: PWM7 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l7`] module"]
#[doc (alias = "PWM_DUTY_L7")] pub type PwmDutyL7 = crate :: Reg < pwm_duty_l7 :: PwmDutyL7Spec > ;
#[doc = "PWM7 duty cycle low 16 bits"] pub mod pwm_duty_l7 {
#[doc = "Register `PWM_DUTY_L7` reader"] pub type R = crate :: R < PwmDutyL7Spec > ;
#[doc = "Register `PWM_DUTY_L7` writer"] pub type W = crate :: W < PwmDutyL7Spec > ;
#[doc = "Field `pwm_duty_l_7` reader - PWM0 duty cycle low 16 bits"] pub type PwmDutyL7R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_l_7` writer - PWM0 duty cycle low 16 bits"] pub type PwmDutyL7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_7 (& self) -> PwmDutyL7R { PwmDutyL7R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
#[inline (always)] pub fn pwm_duty_l_7 (& mut self) -> PwmDutyL7W < '_ , PwmDutyL7Spec > { PwmDutyL7W :: new (self , 0) } }
#[doc = "PWM7 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyL7Spec ; impl crate :: RegisterSpec for PwmDutyL7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_l7::R`](R) reader structure"] impl crate :: Readable for PwmDutyL7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_l7::W`](W) writer structure"] impl crate :: Writable for PwmDutyL7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_L7 to value 0"] impl crate :: Resettable for PwmDutyL7Spec { } }
#[doc = "PWM_DUTY_H7 (rw) register accessor: PWM7 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h7`] module"]
#[doc (alias = "PWM_DUTY_H7")] pub type PwmDutyH7 = crate :: Reg < pwm_duty_h7 :: PwmDutyH7Spec > ;
#[doc = "PWM7 duty cycle high 16 bits"] pub mod pwm_duty_h7 {
#[doc = "Register `PWM_DUTY_H7` reader"] pub type R = crate :: R < PwmDutyH7Spec > ;
#[doc = "Register `PWM_DUTY_H7` writer"] pub type W = crate :: W < PwmDutyH7Spec > ;
#[doc = "Field `pwm_duty_h_7` reader - PWM0 duty cycle high 16 bits"] pub type PwmDutyH7R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_duty_h_7` writer - PWM0 duty cycle high 16 bits"] pub type PwmDutyH7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_7 (& self) -> PwmDutyH7R { PwmDutyH7R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
#[inline (always)] pub fn pwm_duty_h_7 (& mut self) -> PwmDutyH7W < '_ , PwmDutyH7Spec > { PwmDutyH7W :: new (self , 0) } }
#[doc = "PWM7 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmDutyH7Spec ; impl crate :: RegisterSpec for PwmDutyH7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_duty_h7::R`](R) reader structure"] impl crate :: Readable for PwmDutyH7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_duty_h7::W`](W) writer structure"] impl crate :: Writable for PwmDutyH7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_DUTY_H7 to value 0"] impl crate :: Resettable for PwmDutyH7Spec { } }
#[doc = "PWM_PERIODLOAD_FLAG7 (rw) register accessor: PWM7 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag7`] module"]
#[doc (alias = "PWM_PERIODLOAD_FLAG7")] pub type PwmPeriodloadFlag7 = crate :: Reg < pwm_periodload_flag7 :: PwmPeriodloadFlag7Spec > ;
#[doc = "PWM7 period load flag"] pub mod pwm_periodload_flag7 {
#[doc = "Register `PWM_PERIODLOAD_FLAG7` reader"] pub type R = crate :: R < PwmPeriodloadFlag7Spec > ;
#[doc = "Register `PWM_PERIODLOAD_FLAG7` writer"] pub type W = crate :: W < PwmPeriodloadFlag7Spec > ;
#[doc = "Field `pwm_periodload_flag_7` reader - Period load complete flag"] pub type PwmPeriodloadFlag7R = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Period load complete flag"]
#[inline (always)] pub fn pwm_periodload_flag_7 (& self) -> PwmPeriodloadFlag7R { PwmPeriodloadFlag7R :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "PWM7 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodloadFlag7Spec ; impl crate :: RegisterSpec for PwmPeriodloadFlag7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodload_flag7::R`](R) reader structure"] impl crate :: Readable for PwmPeriodloadFlag7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag7::W`](W) writer structure"] impl crate :: Writable for PwmPeriodloadFlag7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG7 to value 0"] impl crate :: Resettable for PwmPeriodloadFlag7Spec { } }
#[doc = "PWM_PERIOD_VAL7 (rw) register accessor: PWM7 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val7`] module"]
#[doc (alias = "PWM_PERIOD_VAL7")] pub type PwmPeriodVal7 = crate :: Reg < pwm_period_val7 :: PwmPeriodVal7Spec > ;
#[doc = "PWM7 pulse count value"] pub mod pwm_period_val7 {
#[doc = "Register `PWM_PERIOD_VAL7` reader"] pub type R = crate :: R < PwmPeriodVal7Spec > ;
#[doc = "Register `PWM_PERIOD_VAL7` writer"] pub type W = crate :: W < PwmPeriodVal7Spec > ;
#[doc = "Field `pwm_period_val_7` reader - Pulse count for stepping mode"] pub type PwmPeriodVal7R = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_period_val_7` writer - Pulse count for stepping mode"] pub type PwmPeriodVal7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_7 (& self) -> PwmPeriodVal7R { PwmPeriodVal7R :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Pulse count for stepping mode"]
#[inline (always)] pub fn pwm_period_val_7 (& mut self) -> PwmPeriodVal7W < '_ , PwmPeriodVal7Spec > { PwmPeriodVal7W :: new (self , 0) } }
#[doc = "PWM7 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodVal7Spec ; impl crate :: RegisterSpec for PwmPeriodVal7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_period_val7::R`](R) reader structure"] impl crate :: Readable for PwmPeriodVal7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_period_val7::W`](W) writer structure"] impl crate :: Writable for PwmPeriodVal7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIOD_VAL7 to value 0"] impl crate :: Resettable for PwmPeriodVal7Spec { } }
#[doc = "PWM_PERIODCNT7 (rw) register accessor: PWM7 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt7`] module"]
#[doc (alias = "PWM_PERIODCNT7")] pub type PwmPeriodcnt7 = crate :: Reg < pwm_periodcnt7 :: PwmPeriodcnt7Spec > ;
#[doc = "PWM7 pulse count current value"] pub mod pwm_periodcnt7 {
#[doc = "Register `PWM_PERIODCNT7` reader"] pub type R = crate :: R < PwmPeriodcnt7Spec > ;
#[doc = "Register `PWM_PERIODCNT7` writer"] pub type W = crate :: W < PwmPeriodcnt7Spec > ;
#[doc = "Field `pwm_periodcnt_7` reader - Current pulse count"] pub type PwmPeriodcnt7R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Current pulse count"]
#[inline (always)] pub fn pwm_periodcnt_7 (& self) -> PwmPeriodcnt7R { PwmPeriodcnt7R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "PWM7 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PwmPeriodcnt7Spec ; impl crate :: RegisterSpec for PwmPeriodcnt7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pwm_periodcnt7::R`](R) reader structure"] impl crate :: Readable for PwmPeriodcnt7Spec { }
#[doc = "`write(|w| ..)` method takes [`pwm_periodcnt7::W`](W) writer structure"] impl crate :: Writable for PwmPeriodcnt7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PWM_PERIODCNT7 to value 0"] impl crate :: Resettable for PwmPeriodcnt7Spec { } } }
#[doc = "DMA controller with 4 channels"] pub type Dma = crate :: Periph < dma :: RegisterBlock , 0x4a00_0000 > ; impl core :: fmt :: Debug for Dma { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Dma") . finish () } }
#[doc = "DMA controller with 4 channels"] pub mod dma {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x04] , dmac_int_st : DmacIntSt , dmac_int_clr : DmacIntClr , dmac_ori_int_st : DmacOriIntSt , dmac_en_chns : DmacEnChns , dmac_burst_req : DmacBurstReq , dmac_single_req : DmacSingleReq , dmac_config : DmacConfig , dmac_sync : DmacSync , _reserved8 : [u8 ; 0xdc] , dmac_lli_0 : () , _reserved9 : [u8 ; 0x04] , dmac_d_addr_0 : () , _reserved10 : [u8 ; 0x04] , dmac_chn_config_0 : () , _reserved11 : [u8 ; 0x08] , dmac_s_addr_0 : () , _reserved12 : [u8 ; 0x04] , dmac_chn_control_0 : () , } impl RegisterBlock {
#[doc = "0x04 - Interrupt status register"]
#[inline (always)] pub const fn dmac_int_st (& self) -> & DmacIntSt { & self . dmac_int_st }
#[doc = "0x08 - Interrupt clear register"]
#[inline (always)] pub const fn dmac_int_clr (& self) -> & DmacIntClr { & self . dmac_int_clr }
#[doc = "0x0c - Raw interrupt status register"]
#[inline (always)] pub const fn dmac_ori_int_st (& self) -> & DmacOriIntSt { & self . dmac_ori_int_st }
#[doc = "0x10 - Channel enable query register"]
#[inline (always)] pub const fn dmac_en_chns (& self) -> & DmacEnChns { & self . dmac_en_chns }
#[doc = "0x14 - Burst software request register"]
#[inline (always)] pub const fn dmac_burst_req (& self) -> & DmacBurstReq { & self . dmac_burst_req }
#[doc = "0x18 - Single software request register"]
#[inline (always)] pub const fn dmac_single_req (& self) -> & DmacSingleReq { & self . dmac_single_req }
#[doc = "0x1c - DMA configuration register"]
#[inline (always)] pub const fn dmac_config (& self) -> & DmacConfig { & self . dmac_config }
#[doc = "0x20 - DMA sync register"]
#[inline (always)] pub const fn dmac_sync (& self) -> & DmacSync { & self . dmac_sync }
#[doc = "0x100..0x110 - Channel %s \\[dim=4\\] linked list register"]
#[inline (always)] pub const fn dmac_lli_0 (& self , n : usize) -> & DmacLli_ {
#[allow (clippy :: no_effect)] [() ; 4] [n] ; unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (256) . add (32 * n) . cast () } }
#[doc = "Iterator for array of:"]
#[doc = "0x100..0x110 - Channel %s \\[dim=4\\] linked list register"]
#[inline (always)] pub fn dmac_lli_0_iter (& self) -> impl Iterator < Item = & DmacLli_ > { (0 .. 4) . map (move | n | unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (256) . add (32 * n) . cast () }) }
#[doc = "0x104..0x114 - Channel %s \\[dim=4\\] destination address"]
#[inline (always)] pub const fn dmac_d_addr_0 (& self , n : usize) -> & DmacDAddr_ {
#[allow (clippy :: no_effect)] [() ; 4] [n] ; unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (260) . add (32 * n) . cast () } }
#[doc = "Iterator for array of:"]
#[doc = "0x104..0x114 - Channel %s \\[dim=4\\] destination address"]
#[inline (always)] pub fn dmac_d_addr_0_iter (& self) -> impl Iterator < Item = & DmacDAddr_ > { (0 .. 4) . map (move | n | unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (260) . add (32 * n) . cast () }) }
#[doc = "0x108..0x118 - Channel %s \\[dim=4\\] configuration register"]
#[inline (always)] pub const fn dmac_chn_config_0 (& self , n : usize) -> & DmacChnConfig_ {
#[allow (clippy :: no_effect)] [() ; 4] [n] ; unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (264) . add (32 * n) . cast () } }
#[doc = "Iterator for array of:"]
#[doc = "0x108..0x118 - Channel %s \\[dim=4\\] configuration register"]
#[inline (always)] pub fn dmac_chn_config_0_iter (& self) -> impl Iterator < Item = & DmacChnConfig_ > { (0 .. 4) . map (move | n | unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (264) . add (32 * n) . cast () }) }
#[doc = "0x110..0x120 - Channel %s \\[dim=4\\] source address"]
#[inline (always)] pub const fn dmac_s_addr_0 (& self , n : usize) -> & DmacSAddr_ {
#[allow (clippy :: no_effect)] [() ; 4] [n] ; unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (272) . add (32 * n) . cast () } }
#[doc = "Iterator for array of:"]
#[doc = "0x110..0x120 - Channel %s \\[dim=4\\] source address"]
#[inline (always)] pub fn dmac_s_addr_0_iter (& self) -> impl Iterator < Item = & DmacSAddr_ > { (0 .. 4) . map (move | n | unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (272) . add (32 * n) . cast () }) }
#[doc = "0x114..0x124 - Channel %s \\[dim=4\\] control register"]
#[inline (always)] pub const fn dmac_chn_control_0 (& self , n : usize) -> & DmacChnControl_ {
#[allow (clippy :: no_effect)] [() ; 4] [n] ; unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (276) . add (32 * n) . cast () } }
#[doc = "Iterator for array of:"]
#[doc = "0x114..0x124 - Channel %s \\[dim=4\\] control register"]
#[inline (always)] pub fn dmac_chn_control_0_iter (& self) -> impl Iterator < Item = & DmacChnControl_ > { (0 .. 4) . map (move | n | unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (276) . add (32 * n) . cast () }) } }
#[doc = "DMAC_INT_ST (rw) register accessor: Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_int_st`] module"]
#[doc (alias = "DMAC_INT_ST")] pub type DmacIntSt = crate :: Reg < dmac_int_st :: DmacIntStSpec > ;
#[doc = "Interrupt status register"] pub mod dmac_int_st {
#[doc = "Register `DMAC_INT_ST` reader"] pub type R = crate :: R < DmacIntStSpec > ;
#[doc = "Register `DMAC_INT_ST` writer"] pub type W = crate :: W < DmacIntStSpec > ;
#[doc = "Field `int_st` reader - Channel interrupt status (after mask)"] pub type IntStR = crate :: FieldReader ;
#[doc = "Field `int_trans_st` reader - Channel transfer interrupt status (after mask)"] pub type IntTransStR = crate :: FieldReader ;
#[doc = "Field `int_err_st` reader - Channel error interrupt status (after mask)"] pub type IntErrStR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - Channel interrupt status (after mask)"]
#[inline (always)] pub fn int_st (& self) -> IntStR { IntStR :: new ((self . bits & 0xff) as u8) }
#[doc = "Bits 8:15 - Channel transfer interrupt status (after mask)"]
#[inline (always)] pub fn int_trans_st (& self) -> IntTransStR { IntTransStR :: new (((self . bits >> 8) & 0xff) as u8) }
#[doc = "Bits 16:23 - Channel error interrupt status (after mask)"]
#[inline (always)] pub fn int_err_st (& self) -> IntErrStR { IntErrStR :: new (((self . bits >> 16) & 0xff) as u8) } } impl W { }
#[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacIntStSpec ; impl crate :: RegisterSpec for DmacIntStSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_int_st::R`](R) reader structure"] impl crate :: Readable for DmacIntStSpec { }
#[doc = "`write(|w| ..)` method takes [`dmac_int_st::W`](W) writer structure"] impl crate :: Writable for DmacIntStSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_INT_ST to value 0"] impl crate :: Resettable for DmacIntStSpec { } }
#[doc = "DMAC_INT_CLR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_int_clr`] module"]
#[doc (alias = "DMAC_INT_CLR")] pub type DmacIntClr = crate :: Reg < dmac_int_clr :: DmacIntClrSpec > ;
#[doc = "Interrupt clear register"] pub mod dmac_int_clr {
#[doc = "Register `DMAC_INT_CLR` reader"] pub type R = crate :: R < DmacIntClrSpec > ;
#[doc = "Register `DMAC_INT_CLR` writer"] pub type W = crate :: W < DmacIntClrSpec > ;
#[doc = "Field `int_trans_clr` reader - Clear channel transfer interrupt"] pub type IntTransClrR = crate :: FieldReader ;
#[doc = "Field `int_trans_clr` writer - Clear channel transfer interrupt"] pub type IntTransClrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ;
#[doc = "Field `int_err_clr` reader - Clear channel error interrupt"] pub type IntErrClrR = crate :: FieldReader ;
#[doc = "Field `int_err_clr` writer - Clear channel error interrupt"] pub type IntErrClrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - Clear channel transfer interrupt"]
#[inline (always)] pub fn int_trans_clr (& self) -> IntTransClrR { IntTransClrR :: new ((self . bits & 0xff) as u8) }
#[doc = "Bits 8:15 - Clear channel error interrupt"]
#[inline (always)] pub fn int_err_clr (& self) -> IntErrClrR { IntErrClrR :: new (((self . bits >> 8) & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Clear channel transfer interrupt"]
#[inline (always)] pub fn int_trans_clr (& mut self) -> IntTransClrW < '_ , DmacIntClrSpec > { IntTransClrW :: new (self , 0) }
#[doc = "Bits 8:15 - Clear channel error interrupt"]
#[inline (always)] pub fn int_err_clr (& mut self) -> IntErrClrW < '_ , DmacIntClrSpec > { IntErrClrW :: new (self , 8) } }
#[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacIntClrSpec ; impl crate :: RegisterSpec for DmacIntClrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_int_clr::R`](R) reader structure"] impl crate :: Readable for DmacIntClrSpec { }
#[doc = "`write(|w| ..)` method takes [`dmac_int_clr::W`](W) writer structure"] impl crate :: Writable for DmacIntClrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_INT_CLR to value 0"] impl crate :: Resettable for DmacIntClrSpec { } }
#[doc = "DMAC_ORI_INT_ST (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_ori_int_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_ori_int_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_ori_int_st`] module"]
#[doc (alias = "DMAC_ORI_INT_ST")] pub type DmacOriIntSt = crate :: Reg < dmac_ori_int_st :: DmacOriIntStSpec > ;
#[doc = "Raw interrupt status register"] pub mod dmac_ori_int_st {
#[doc = "Register `DMAC_ORI_INT_ST` reader"] pub type R = crate :: R < DmacOriIntStSpec > ;
#[doc = "Register `DMAC_ORI_INT_ST` writer"] pub type W = crate :: W < DmacOriIntStSpec > ;
#[doc = "Field `ori_int_trans_st` reader - Raw transfer interrupt status (before mask)"] pub type OriIntTransStR = crate :: FieldReader ;
#[doc = "Field `ori_int_err_st` reader - Raw error interrupt status (before mask)"] pub type OriIntErrStR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - Raw transfer interrupt status (before mask)"]
#[inline (always)] pub fn ori_int_trans_st (& self) -> OriIntTransStR { OriIntTransStR :: new ((self . bits & 0xff) as u8) }
#[doc = "Bits 8:15 - Raw error interrupt status (before mask)"]
#[inline (always)] pub fn ori_int_err_st (& self) -> OriIntErrStR { OriIntErrStR :: new (((self . bits >> 8) & 0xff) as u8) } } impl W { }
#[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_ori_int_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_ori_int_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacOriIntStSpec ; impl crate :: RegisterSpec for DmacOriIntStSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_ori_int_st::R`](R) reader structure"] impl crate :: Readable for DmacOriIntStSpec { }
#[doc = "`write(|w| ..)` method takes [`dmac_ori_int_st::W`](W) writer structure"] impl crate :: Writable for DmacOriIntStSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_ORI_INT_ST to value 0"] impl crate :: Resettable for DmacOriIntStSpec { } }
#[doc = "DMAC_EN_CHNS (rw) register accessor: Channel enable query register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_en_chns::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_en_chns::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_en_chns`] module"]
#[doc (alias = "DMAC_EN_CHNS")] pub type DmacEnChns = crate :: Reg < dmac_en_chns :: DmacEnChnsSpec > ;
#[doc = "Channel enable query register"] pub mod dmac_en_chns {
#[doc = "Register `DMAC_EN_CHNS` reader"] pub type R = crate :: R < DmacEnChnsSpec > ;
#[doc = "Register `DMAC_EN_CHNS` writer"] pub type W = crate :: W < DmacEnChnsSpec > ;
#[doc = "Field `en_chns` reader - Channel enable status: 0=disabled; 1=enabled"] pub type EnChnsR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - Channel enable status: 0=disabled; 1=enabled"]
#[inline (always)] pub fn en_chns (& self) -> EnChnsR { EnChnsR :: new ((self . bits & 0xff) as u8) } } impl W { }
#[doc = "Channel enable query register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_en_chns::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_en_chns::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacEnChnsSpec ; impl crate :: RegisterSpec for DmacEnChnsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_en_chns::R`](R) reader structure"] impl crate :: Readable for DmacEnChnsSpec { }
#[doc = "`write(|w| ..)` method takes [`dmac_en_chns::W`](W) writer structure"] impl crate :: Writable for DmacEnChnsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_EN_CHNS to value 0"] impl crate :: Resettable for DmacEnChnsSpec { } }
#[doc = "DMAC_BURST_REQ (rw) register accessor: Burst software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_burst_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_burst_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_burst_req`] module"]
#[doc (alias = "DMAC_BURST_REQ")] pub type DmacBurstReq = crate :: Reg < dmac_burst_req :: DmacBurstReqSpec > ;
#[doc = "Burst software request register"] pub mod dmac_burst_req {
#[doc = "Register `DMAC_BURST_REQ` reader"] pub type R = crate :: R < DmacBurstReqSpec > ;
#[doc = "Register `DMAC_BURST_REQ` writer"] pub type W = crate :: W < DmacBurstReqSpec > ;
#[doc = "Field `last_burst_req` reader - Last burst request per peripheral"] pub type LastBurstReqR = crate :: FieldReader < u16 > ;
#[doc = "Field `last_burst_req` writer - Last burst request per peripheral"] pub type LastBurstReqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ;
#[doc = "Field `burst_req` reader - Burst request per peripheral"] pub type BurstReqR = crate :: FieldReader < u16 > ;
#[doc = "Field `burst_req` writer - Burst request per peripheral"] pub type BurstReqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Last burst request per peripheral"]
#[inline (always)] pub fn last_burst_req (& self) -> LastBurstReqR { LastBurstReqR :: new ((self . bits & 0xffff) as u16) }
#[doc = "Bits 16:31 - Burst request per peripheral"]
#[inline (always)] pub fn burst_req (& self) -> BurstReqR { BurstReqR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Last burst request per peripheral"]
#[inline (always)] pub fn last_burst_req (& mut self) -> LastBurstReqW < '_ , DmacBurstReqSpec > { LastBurstReqW :: new (self , 0) }
#[doc = "Bits 16:31 - Burst request per peripheral"]
#[inline (always)] pub fn burst_req (& mut self) -> BurstReqW < '_ , DmacBurstReqSpec > { BurstReqW :: new (self , 16) } }
#[doc = "Burst software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_burst_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_burst_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacBurstReqSpec ; impl crate :: RegisterSpec for DmacBurstReqSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_burst_req::R`](R) reader structure"] impl crate :: Readable for DmacBurstReqSpec { }
#[doc = "`write(|w| ..)` method takes [`dmac_burst_req::W`](W) writer structure"] impl crate :: Writable for DmacBurstReqSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_BURST_REQ to value 0"] impl crate :: Resettable for DmacBurstReqSpec { } }
#[doc = "DMAC_SINGLE_REQ (rw) register accessor: Single software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_single_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_single_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_single_req`] module"]
#[doc (alias = "DMAC_SINGLE_REQ")] pub type DmacSingleReq = crate :: Reg < dmac_single_req :: DmacSingleReqSpec > ;
#[doc = "Single software request register"] pub mod dmac_single_req {
#[doc = "Register `DMAC_SINGLE_REQ` reader"] pub type R = crate :: R < DmacSingleReqSpec > ;
#[doc = "Register `DMAC_SINGLE_REQ` writer"] pub type W = crate :: W < DmacSingleReqSpec > ;
#[doc = "Field `last_single_req` reader - Last single request per peripheral"] pub type LastSingleReqR = crate :: FieldReader < u16 > ;
#[doc = "Field `last_single_req` writer - Last single request per peripheral"] pub type LastSingleReqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ;
#[doc = "Field `single_req` reader - Single request per peripheral"] pub type SingleReqR = crate :: FieldReader < u16 > ;
#[doc = "Field `single_req` writer - Single request per peripheral"] pub type SingleReqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Last single request per peripheral"]
#[inline (always)] pub fn last_single_req (& self) -> LastSingleReqR { LastSingleReqR :: new ((self . bits & 0xffff) as u16) }
#[doc = "Bits 16:31 - Single request per peripheral"]
#[inline (always)] pub fn single_req (& self) -> SingleReqR { SingleReqR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Last single request per peripheral"]
#[inline (always)] pub fn last_single_req (& mut self) -> LastSingleReqW < '_ , DmacSingleReqSpec > { LastSingleReqW :: new (self , 0) }
#[doc = "Bits 16:31 - Single request per peripheral"]
#[inline (always)] pub fn single_req (& mut self) -> SingleReqW < '_ , DmacSingleReqSpec > { SingleReqW :: new (self , 16) } }
#[doc = "Single software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_single_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_single_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacSingleReqSpec ; impl crate :: RegisterSpec for DmacSingleReqSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_single_req::R`](R) reader structure"] impl crate :: Readable for DmacSingleReqSpec { }
#[doc = "`write(|w| ..)` method takes [`dmac_single_req::W`](W) writer structure"] impl crate :: Writable for DmacSingleReqSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_SINGLE_REQ to value 0"] impl crate :: Resettable for DmacSingleReqSpec { } }
#[doc = "DMAC_CONFIG (rw) register accessor: DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_config`] module"]
#[doc (alias = "DMAC_CONFIG")] pub type DmacConfig = crate :: Reg < dmac_config :: DmacConfigSpec > ;
#[doc = "DMA configuration register"] pub mod dmac_config {
#[doc = "Register `DMAC_CONFIG` reader"] pub type R = crate :: R < DmacConfigSpec > ;
#[doc = "Register `DMAC_CONFIG` writer"] pub type W = crate :: W < DmacConfigSpec > ;
#[doc = "Field `dmac_en` reader - DMAC enable: 0=disabled; 1=enabled"] pub type DmacEnR = crate :: BitReader ;
#[doc = "Field `dmac_en` writer - DMAC enable: 0=disabled; 1=enabled"] pub type DmacEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_m1` reader - Master 1 endianness: 0=little; 1=big"] pub type DmacM1R = crate :: BitReader ;
#[doc = "Field `dmac_m1` writer - Master 1 endianness: 0=little; 1=big"] pub type DmacM1W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_m2` reader - Master 2 endianness: 0=little; 1=big"] pub type DmacM2R = crate :: BitReader ;
#[doc = "Field `dmac_m2` writer - Master 2 endianness: 0=little; 1=big"] pub type DmacM2W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - DMAC enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn dmac_en (& self) -> DmacEnR { DmacEnR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Master 1 endianness: 0=little; 1=big"]
#[inline (always)] pub fn dmac_m1 (& self) -> DmacM1R { DmacM1R :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Master 2 endianness: 0=little; 1=big"]
#[inline (always)] pub fn dmac_m2 (& self) -> DmacM2R { DmacM2R :: new (((self . bits >> 2) & 1) != 0) } } impl W {
#[doc = "Bit 0 - DMAC enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn dmac_en (& mut self) -> DmacEnW < '_ , DmacConfigSpec > { DmacEnW :: new (self , 0) }
#[doc = "Bit 1 - Master 1 endianness: 0=little; 1=big"]
#[inline (always)] pub fn dmac_m1 (& mut self) -> DmacM1W < '_ , DmacConfigSpec > { DmacM1W :: new (self , 1) }
#[doc = "Bit 2 - Master 2 endianness: 0=little; 1=big"]
#[inline (always)] pub fn dmac_m2 (& mut self) -> DmacM2W < '_ , DmacConfigSpec > { DmacM2W :: new (self , 2) } }
#[doc = "DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacConfigSpec ; impl crate :: RegisterSpec for DmacConfigSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_config::R`](R) reader structure"] impl crate :: Readable for DmacConfigSpec { }
#[doc = "`write(|w| ..)` method takes [`dmac_config::W`](W) writer structure"] impl crate :: Writable for DmacConfigSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_CONFIG to value 0"] impl crate :: Resettable for DmacConfigSpec { } }
#[doc = "DMAC_SYNC (rw) register accessor: DMA sync register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_sync`] module"]
#[doc (alias = "DMAC_SYNC")] pub type DmacSync = crate :: Reg < dmac_sync :: DmacSyncSpec > ;
#[doc = "DMA sync register"] pub mod dmac_sync {
#[doc = "Register `DMAC_SYNC` reader"] pub type R = crate :: R < DmacSyncSpec > ;
#[doc = "Register `DMAC_SYNC` writer"] pub type W = crate :: W < DmacSyncSpec > ;
#[doc = "Field `damc_sync` reader - DMA request sync: 0=enable sync; 1=disable sync"] pub type DamcSyncR = crate :: FieldReader < u16 > ;
#[doc = "Field `damc_sync` writer - DMA request sync: 0=enable sync; 1=disable sync"] pub type DamcSyncW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - DMA request sync: 0=enable sync; 1=disable sync"]
#[inline (always)] pub fn damc_sync (& self) -> DamcSyncR { DamcSyncR :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - DMA request sync: 0=enable sync; 1=disable sync"]
#[inline (always)] pub fn damc_sync (& mut self) -> DamcSyncW < '_ , DmacSyncSpec > { DamcSyncW :: new (self , 0) } }
#[doc = "DMA sync register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_sync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_sync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacSyncSpec ; impl crate :: RegisterSpec for DmacSyncSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_sync::R`](R) reader structure"] impl crate :: Readable for DmacSyncSpec { }
#[doc = "`write(|w| ..)` method takes [`dmac_sync::W`](W) writer structure"] impl crate :: Writable for DmacSyncSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_SYNC to value 0"] impl crate :: Resettable for DmacSyncSpec { } }
#[doc = "DMAC_D_ADDR_ (rw) register accessor: Channel %s \\[dim=4\\] destination address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_d_addr_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_d_addr_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_d_addr_`] module"]
#[doc (alias = "DMAC_D_ADDR_")] pub type DmacDAddr_ = crate :: Reg < dmac_d_addr_ :: DmacDAddr_Spec > ;
#[doc = "Channel %s \\[dim=4\\] destination address"] pub mod dmac_d_addr_ {
#[doc = "Register `DMAC_D_ADDR_%s` reader"] pub type R = crate :: R < DmacDAddr_Spec > ;
#[doc = "Register `DMAC_D_ADDR_%s` writer"] pub type W = crate :: W < DmacDAddr_Spec > ;
#[doc = "Field `dmac_d_addr_0` reader - Channel 0 destination address"] pub type DmacDAddr0R = crate :: FieldReader < u32 > ;
#[doc = "Field `dmac_d_addr_0` writer - Channel 0 destination address"] pub type DmacDAddr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Channel 0 destination address"]
#[inline (always)] pub fn dmac_d_addr_0 (& self) -> DmacDAddr0R { DmacDAddr0R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Channel 0 destination address"]
#[inline (always)] pub fn dmac_d_addr_0 (& mut self) -> DmacDAddr0W < '_ , DmacDAddr_Spec > { DmacDAddr0W :: new (self , 0) } }
#[doc = "Channel %s \\[dim=4\\] destination address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_d_addr_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_d_addr_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacDAddr_Spec ; impl crate :: RegisterSpec for DmacDAddr_Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_d_addr_::R`](R) reader structure"] impl crate :: Readable for DmacDAddr_Spec { }
#[doc = "`write(|w| ..)` method takes [`dmac_d_addr_::W`](W) writer structure"] impl crate :: Writable for DmacDAddr_Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_D_ADDR_%s to value 0"] impl crate :: Resettable for DmacDAddr_Spec { } }
#[doc = "DMAC_LLI_ (rw) register accessor: Channel %s \\[dim=4\\] linked list register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_lli_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_lli_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_lli_`] module"]
#[doc (alias = "DMAC_LLI_")] pub type DmacLli_ = crate :: Reg < dmac_lli_ :: DmacLli_Spec > ;
#[doc = "Channel %s \\[dim=4\\] linked list register"] pub mod dmac_lli_ {
#[doc = "Register `DMAC_LLI_%s` reader"] pub type R = crate :: R < DmacLli_Spec > ;
#[doc = "Register `DMAC_LLI_%s` writer"] pub type W = crate :: W < DmacLli_Spec > ;
#[doc = "Field `dmac_lm_0` reader - Master for next LLI node: 0=Master1; 1=Master2"] pub type DmacLm0R = crate :: BitReader ;
#[doc = "Field `dmac_lm_0` writer - Master for next LLI node: 0=Master1; 1=Master2"] pub type DmacLm0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_lli_0` reader - Linked list address \\[31:2\\]"] pub type DmacLli0R = crate :: FieldReader < u32 > ;
#[doc = "Field `dmac_lli_0` writer - Linked list address \\[31:2\\]"] pub type DmacLli0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R {
#[doc = "Bit 0 - Master for next LLI node: 0=Master1; 1=Master2"]
#[inline (always)] pub fn dmac_lm_0 (& self) -> DmacLm0R { DmacLm0R :: new ((self . bits & 1) != 0) }
#[doc = "Bits 2:31 - Linked list address \\[31:2\\]"]
#[inline (always)] pub fn dmac_lli_0 (& self) -> DmacLli0R { DmacLli0R :: new ((self . bits >> 2) & 0x3fff_ffff) } } impl W {
#[doc = "Bit 0 - Master for next LLI node: 0=Master1; 1=Master2"]
#[inline (always)] pub fn dmac_lm_0 (& mut self) -> DmacLm0W < '_ , DmacLli_Spec > { DmacLm0W :: new (self , 0) }
#[doc = "Bits 2:31 - Linked list address \\[31:2\\]"]
#[inline (always)] pub fn dmac_lli_0 (& mut self) -> DmacLli0W < '_ , DmacLli_Spec > { DmacLli0W :: new (self , 2) } }
#[doc = "Channel %s \\[dim=4\\] linked list register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_lli_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_lli_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacLli_Spec ; impl crate :: RegisterSpec for DmacLli_Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_lli_::R`](R) reader structure"] impl crate :: Readable for DmacLli_Spec { }
#[doc = "`write(|w| ..)` method takes [`dmac_lli_::W`](W) writer structure"] impl crate :: Writable for DmacLli_Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_LLI_%s to value 0"] impl crate :: Resettable for DmacLli_Spec { } }
#[doc = "DMAC_S_ADDR_ (rw) register accessor: Channel %s \\[dim=4\\] source address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_s_addr_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_s_addr_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_s_addr_`] module"]
#[doc (alias = "DMAC_S_ADDR_")] pub type DmacSAddr_ = crate :: Reg < dmac_s_addr_ :: DmacSAddr_Spec > ;
#[doc = "Channel %s \\[dim=4\\] source address"] pub mod dmac_s_addr_ {
#[doc = "Register `DMAC_S_ADDR_%s` reader"] pub type R = crate :: R < DmacSAddr_Spec > ;
#[doc = "Register `DMAC_S_ADDR_%s` writer"] pub type W = crate :: W < DmacSAddr_Spec > ;
#[doc = "Field `dmac_s_addr_0` reader - Channel 0 source address"] pub type DmacSAddr0R = crate :: FieldReader < u32 > ;
#[doc = "Field `dmac_s_addr_0` writer - Channel 0 source address"] pub type DmacSAddr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Channel 0 source address"]
#[inline (always)] pub fn dmac_s_addr_0 (& self) -> DmacSAddr0R { DmacSAddr0R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Channel 0 source address"]
#[inline (always)] pub fn dmac_s_addr_0 (& mut self) -> DmacSAddr0W < '_ , DmacSAddr_Spec > { DmacSAddr0W :: new (self , 0) } }
#[doc = "Channel %s \\[dim=4\\] source address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_s_addr_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_s_addr_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacSAddr_Spec ; impl crate :: RegisterSpec for DmacSAddr_Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_s_addr_::R`](R) reader structure"] impl crate :: Readable for DmacSAddr_Spec { }
#[doc = "`write(|w| ..)` method takes [`dmac_s_addr_::W`](W) writer structure"] impl crate :: Writable for DmacSAddr_Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_S_ADDR_%s to value 0"] impl crate :: Resettable for DmacSAddr_Spec { } }
#[doc = "DMAC_CHN_CONTROL_ (rw) register accessor: Channel %s \\[dim=4\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_control_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_control_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_chn_control_`] module"]
#[doc (alias = "DMAC_CHN_CONTROL_")] pub type DmacChnControl_ = crate :: Reg < dmac_chn_control_ :: DmacChnControl_Spec > ;
#[doc = "Channel %s \\[dim=4\\] control register"] pub mod dmac_chn_control_ {
#[doc = "Register `DMAC_CHN_CONTROL_%s` reader"] pub type R = crate :: R < DmacChnControl_Spec > ;
#[doc = "Register `DMAC_CHN_CONTROL_%s` writer"] pub type W = crate :: W < DmacChnControl_Spec > ;
#[doc = "Field `dmac_trans_size_0` reader - Transfer size"] pub type DmacTransSize0R = crate :: FieldReader < u16 > ;
#[doc = "Field `dmac_trans_size_0` writer - Transfer size"] pub type DmacTransSize0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ;
#[doc = "Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum DmacSBsize0 {
#[doc = "0: Burst size 1"] Bs1 = 0 ,
#[doc = "1: Burst size 4"] Bs4 = 1 ,
#[doc = "2: Burst size 8"] Bs8 = 2 ,
#[doc = "3: Burst size 16"] Bs16 = 3 ,
#[doc = "4: Burst size 32"] Bs32 = 4 ,
#[doc = "5: Burst size 64"] Bs64 = 5 ,
#[doc = "6: Burst size 128"] Bs128 = 6 ,
#[doc = "7: Burst size 256"] Bs256 = 7 , } impl From < DmacSBsize0 > for u8 {
#[inline (always)] fn from (variant : DmacSBsize0) -> Self { variant as _ } } impl crate :: FieldSpec for DmacSBsize0 { type Ux = u8 ; } impl crate :: IsEnum for DmacSBsize0 { }
#[doc = "Field `dmac_s_bsize_0` reader - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"] pub type DmacSBsize0R = crate :: FieldReader < DmacSBsize0 > ; impl DmacSBsize0R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> DmacSBsize0 { match self . bits { 0 => DmacSBsize0 :: Bs1 , 1 => DmacSBsize0 :: Bs4 , 2 => DmacSBsize0 :: Bs8 , 3 => DmacSBsize0 :: Bs16 , 4 => DmacSBsize0 :: Bs32 , 5 => DmacSBsize0 :: Bs64 , 6 => DmacSBsize0 :: Bs128 , 7 => DmacSBsize0 :: Bs256 , _ => unreachable ! () , } }
#[doc = "Burst size 1"]
#[inline (always)] pub fn is_bs1 (& self) -> bool { * self == DmacSBsize0 :: Bs1 }
#[doc = "Burst size 4"]
#[inline (always)] pub fn is_bs4 (& self) -> bool { * self == DmacSBsize0 :: Bs4 }
#[doc = "Burst size 8"]
#[inline (always)] pub fn is_bs8 (& self) -> bool { * self == DmacSBsize0 :: Bs8 }
#[doc = "Burst size 16"]
#[inline (always)] pub fn is_bs16 (& self) -> bool { * self == DmacSBsize0 :: Bs16 }
#[doc = "Burst size 32"]
#[inline (always)] pub fn is_bs32 (& self) -> bool { * self == DmacSBsize0 :: Bs32 }
#[doc = "Burst size 64"]
#[inline (always)] pub fn is_bs64 (& self) -> bool { * self == DmacSBsize0 :: Bs64 }
#[doc = "Burst size 128"]
#[inline (always)] pub fn is_bs128 (& self) -> bool { * self == DmacSBsize0 :: Bs128 }
#[doc = "Burst size 256"]
#[inline (always)] pub fn is_bs256 (& self) -> bool { * self == DmacSBsize0 :: Bs256 } }
#[doc = "Field `dmac_s_bsize_0` writer - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"] pub type DmacSBsize0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , DmacSBsize0 , crate :: Safe > ; impl < 'a , REG > DmacSBsize0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Burst size 1"]
#[inline (always)] pub fn bs1 (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSBsize0 :: Bs1) }
#[doc = "Burst size 4"]
#[inline (always)] pub fn bs4 (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSBsize0 :: Bs4) }
#[doc = "Burst size 8"]
#[inline (always)] pub fn bs8 (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSBsize0 :: Bs8) }
#[doc = "Burst size 16"]
#[inline (always)] pub fn bs16 (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSBsize0 :: Bs16) }
#[doc = "Burst size 32"]
#[inline (always)] pub fn bs32 (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSBsize0 :: Bs32) }
#[doc = "Burst size 64"]
#[inline (always)] pub fn bs64 (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSBsize0 :: Bs64) }
#[doc = "Burst size 128"]
#[inline (always)] pub fn bs128 (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSBsize0 :: Bs128) }
#[doc = "Burst size 256"]
#[inline (always)] pub fn bs256 (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSBsize0 :: Bs256) } }
#[doc = "Field `dmac_d_bsize_0` reader - Destination burst size"] pub type DmacDBsize0R = crate :: FieldReader ;
#[doc = "Field `dmac_d_bsize_0` writer - Destination burst size"] pub type DmacDBsize0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Source width: 000=8bit; 001=16bit; 010=32bit\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum DmacSWidth0 {
#[doc = "0: 8-bit"] Byte = 0 ,
#[doc = "1: 16-bit"] Halfword = 1 ,
#[doc = "2: 32-bit"] Word = 2 , } impl From < DmacSWidth0 > for u8 {
#[inline (always)] fn from (variant : DmacSWidth0) -> Self { variant as _ } } impl crate :: FieldSpec for DmacSWidth0 { type Ux = u8 ; } impl crate :: IsEnum for DmacSWidth0 { }
#[doc = "Field `dmac_s_width_0` reader - Source width: 000=8bit; 001=16bit; 010=32bit"] pub type DmacSWidth0R = crate :: FieldReader < DmacSWidth0 > ; impl DmacSWidth0R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < DmacSWidth0 > { match self . bits { 0 => Some (DmacSWidth0 :: Byte) , 1 => Some (DmacSWidth0 :: Halfword) , 2 => Some (DmacSWidth0 :: Word) , _ => None , } }
#[doc = "8-bit"]
#[inline (always)] pub fn is_byte (& self) -> bool { * self == DmacSWidth0 :: Byte }
#[doc = "16-bit"]
#[inline (always)] pub fn is_halfword (& self) -> bool { * self == DmacSWidth0 :: Halfword }
#[doc = "32-bit"]
#[inline (always)] pub fn is_word (& self) -> bool { * self == DmacSWidth0 :: Word } }
#[doc = "Field `dmac_s_width_0` writer - Source width: 000=8bit; 001=16bit; 010=32bit"] pub type DmacSWidth0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , DmacSWidth0 > ; impl < 'a , REG > DmacSWidth0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "8-bit"]
#[inline (always)] pub fn byte (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSWidth0 :: Byte) }
#[doc = "16-bit"]
#[inline (always)] pub fn halfword (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSWidth0 :: Halfword) }
#[doc = "32-bit"]
#[inline (always)] pub fn word (self) -> & 'a mut crate :: W < REG > { self . variant (DmacSWidth0 :: Word) } }
#[doc = "Destination width\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum DmacDWidth0 {
#[doc = "0: 8-bit"] Byte = 0 ,
#[doc = "1: 16-bit"] Halfword = 1 ,
#[doc = "2: 32-bit"] Word = 2 , } impl From < DmacDWidth0 > for u8 {
#[inline (always)] fn from (variant : DmacDWidth0) -> Self { variant as _ } } impl crate :: FieldSpec for DmacDWidth0 { type Ux = u8 ; } impl crate :: IsEnum for DmacDWidth0 { }
#[doc = "Field `dmac_d_width_0` reader - Destination width"] pub type DmacDWidth0R = crate :: FieldReader < DmacDWidth0 > ; impl DmacDWidth0R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < DmacDWidth0 > { match self . bits { 0 => Some (DmacDWidth0 :: Byte) , 1 => Some (DmacDWidth0 :: Halfword) , 2 => Some (DmacDWidth0 :: Word) , _ => None , } }
#[doc = "8-bit"]
#[inline (always)] pub fn is_byte (& self) -> bool { * self == DmacDWidth0 :: Byte }
#[doc = "16-bit"]
#[inline (always)] pub fn is_halfword (& self) -> bool { * self == DmacDWidth0 :: Halfword }
#[doc = "32-bit"]
#[inline (always)] pub fn is_word (& self) -> bool { * self == DmacDWidth0 :: Word } }
#[doc = "Field `dmac_d_width_0` writer - Destination width"] pub type DmacDWidth0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , DmacDWidth0 > ; impl < 'a , REG > DmacDWidth0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "8-bit"]
#[inline (always)] pub fn byte (self) -> & 'a mut crate :: W < REG > { self . variant (DmacDWidth0 :: Byte) }
#[doc = "16-bit"]
#[inline (always)] pub fn halfword (self) -> & 'a mut crate :: W < REG > { self . variant (DmacDWidth0 :: Halfword) }
#[doc = "32-bit"]
#[inline (always)] pub fn word (self) -> & 'a mut crate :: W < REG > { self . variant (DmacDWidth0 :: Word) } }
#[doc = "Field `dmac_s_master_0` reader - Source master: 0=Master1; 1=Master2"] pub type DmacSMaster0R = crate :: BitReader ;
#[doc = "Field `dmac_s_master_0` writer - Source master: 0=Master1; 1=Master2"] pub type DmacSMaster0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_d_master_0` reader - Destination master"] pub type DmacDMaster0R = crate :: BitReader ;
#[doc = "Field `dmac_d_master_0` writer - Destination master"] pub type DmacDMaster0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_s_inc_0` reader - Source address increment: 0=no; 1=yes"] pub type DmacSInc0R = crate :: BitReader ;
#[doc = "Field `dmac_s_inc_0` writer - Source address increment: 0=no; 1=yes"] pub type DmacSInc0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_d_inc_0` reader - Destination address increment"] pub type DmacDInc0R = crate :: BitReader ;
#[doc = "Field `dmac_d_inc_0` writer - Destination address increment"] pub type DmacDInc0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_prot_0` reader - Protection HPROT\\[2:0\\]"] pub type DmacProt0R = crate :: FieldReader ;
#[doc = "Field `dmac_prot_0` writer - Protection HPROT\\[2:0\\]"] pub type DmacProt0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `dmac_trans_int_0` reader - Transfer complete interrupt enable"] pub type DmacTransInt0R = crate :: BitReader ;
#[doc = "Field `dmac_trans_int_0` writer - Transfer complete interrupt enable"] pub type DmacTransInt0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:11 - Transfer size"]
#[inline (always)] pub fn dmac_trans_size_0 (& self) -> DmacTransSize0R { DmacTransSize0R :: new ((self . bits & 0x0fff) as u16) }
#[doc = "Bits 12:14 - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
#[inline (always)] pub fn dmac_s_bsize_0 (& self) -> DmacSBsize0R { DmacSBsize0R :: new (((self . bits >> 12) & 7) as u8) }
#[doc = "Bits 15:17 - Destination burst size"]
#[inline (always)] pub fn dmac_d_bsize_0 (& self) -> DmacDBsize0R { DmacDBsize0R :: new (((self . bits >> 15) & 7) as u8) }
#[doc = "Bits 18:20 - Source width: 000=8bit; 001=16bit; 010=32bit"]
#[inline (always)] pub fn dmac_s_width_0 (& self) -> DmacSWidth0R { DmacSWidth0R :: new (((self . bits >> 18) & 7) as u8) }
#[doc = "Bits 21:23 - Destination width"]
#[inline (always)] pub fn dmac_d_width_0 (& self) -> DmacDWidth0R { DmacDWidth0R :: new (((self . bits >> 21) & 7) as u8) }
#[doc = "Bit 24 - Source master: 0=Master1; 1=Master2"]
#[inline (always)] pub fn dmac_s_master_0 (& self) -> DmacSMaster0R { DmacSMaster0R :: new (((self . bits >> 24) & 1) != 0) }
#[doc = "Bit 25 - Destination master"]
#[inline (always)] pub fn dmac_d_master_0 (& self) -> DmacDMaster0R { DmacDMaster0R :: new (((self . bits >> 25) & 1) != 0) }
#[doc = "Bit 26 - Source address increment: 0=no; 1=yes"]
#[inline (always)] pub fn dmac_s_inc_0 (& self) -> DmacSInc0R { DmacSInc0R :: new (((self . bits >> 26) & 1) != 0) }
#[doc = "Bit 27 - Destination address increment"]
#[inline (always)] pub fn dmac_d_inc_0 (& self) -> DmacDInc0R { DmacDInc0R :: new (((self . bits >> 27) & 1) != 0) }
#[doc = "Bits 28:30 - Protection HPROT\\[2:0\\]"]
#[inline (always)] pub fn dmac_prot_0 (& self) -> DmacProt0R { DmacProt0R :: new (((self . bits >> 28) & 7) as u8) }
#[doc = "Bit 31 - Transfer complete interrupt enable"]
#[inline (always)] pub fn dmac_trans_int_0 (& self) -> DmacTransInt0R { DmacTransInt0R :: new (((self . bits >> 31) & 1) != 0) } } impl W {
#[doc = "Bits 0:11 - Transfer size"]
#[inline (always)] pub fn dmac_trans_size_0 (& mut self) -> DmacTransSize0W < '_ , DmacChnControl_Spec > { DmacTransSize0W :: new (self , 0) }
#[doc = "Bits 12:14 - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
#[inline (always)] pub fn dmac_s_bsize_0 (& mut self) -> DmacSBsize0W < '_ , DmacChnControl_Spec > { DmacSBsize0W :: new (self , 12) }
#[doc = "Bits 15:17 - Destination burst size"]
#[inline (always)] pub fn dmac_d_bsize_0 (& mut self) -> DmacDBsize0W < '_ , DmacChnControl_Spec > { DmacDBsize0W :: new (self , 15) }
#[doc = "Bits 18:20 - Source width: 000=8bit; 001=16bit; 010=32bit"]
#[inline (always)] pub fn dmac_s_width_0 (& mut self) -> DmacSWidth0W < '_ , DmacChnControl_Spec > { DmacSWidth0W :: new (self , 18) }
#[doc = "Bits 21:23 - Destination width"]
#[inline (always)] pub fn dmac_d_width_0 (& mut self) -> DmacDWidth0W < '_ , DmacChnControl_Spec > { DmacDWidth0W :: new (self , 21) }
#[doc = "Bit 24 - Source master: 0=Master1; 1=Master2"]
#[inline (always)] pub fn dmac_s_master_0 (& mut self) -> DmacSMaster0W < '_ , DmacChnControl_Spec > { DmacSMaster0W :: new (self , 24) }
#[doc = "Bit 25 - Destination master"]
#[inline (always)] pub fn dmac_d_master_0 (& mut self) -> DmacDMaster0W < '_ , DmacChnControl_Spec > { DmacDMaster0W :: new (self , 25) }
#[doc = "Bit 26 - Source address increment: 0=no; 1=yes"]
#[inline (always)] pub fn dmac_s_inc_0 (& mut self) -> DmacSInc0W < '_ , DmacChnControl_Spec > { DmacSInc0W :: new (self , 26) }
#[doc = "Bit 27 - Destination address increment"]
#[inline (always)] pub fn dmac_d_inc_0 (& mut self) -> DmacDInc0W < '_ , DmacChnControl_Spec > { DmacDInc0W :: new (self , 27) }
#[doc = "Bits 28:30 - Protection HPROT\\[2:0\\]"]
#[inline (always)] pub fn dmac_prot_0 (& mut self) -> DmacProt0W < '_ , DmacChnControl_Spec > { DmacProt0W :: new (self , 28) }
#[doc = "Bit 31 - Transfer complete interrupt enable"]
#[inline (always)] pub fn dmac_trans_int_0 (& mut self) -> DmacTransInt0W < '_ , DmacChnControl_Spec > { DmacTransInt0W :: new (self , 31) } }
#[doc = "Channel %s \\[dim=4\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_control_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_control_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacChnControl_Spec ; impl crate :: RegisterSpec for DmacChnControl_Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_chn_control_::R`](R) reader structure"] impl crate :: Readable for DmacChnControl_Spec { }
#[doc = "`write(|w| ..)` method takes [`dmac_chn_control_::W`](W) writer structure"] impl crate :: Writable for DmacChnControl_Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_CHN_CONTROL_%s to value 0"] impl crate :: Resettable for DmacChnControl_Spec { } }
#[doc = "DMAC_CHN_CONFIG_ (rw) register accessor: Channel %s \\[dim=4\\] configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_config_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_config_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_chn_config_`] module"]
#[doc (alias = "DMAC_CHN_CONFIG_")] pub type DmacChnConfig_ = crate :: Reg < dmac_chn_config_ :: DmacChnConfig_Spec > ;
#[doc = "Channel %s \\[dim=4\\] configuration register"] pub mod dmac_chn_config_ {
#[doc = "Register `DMAC_CHN_CONFIG_%s` reader"] pub type R = crate :: R < DmacChnConfig_Spec > ;
#[doc = "Register `DMAC_CHN_CONFIG_%s` writer"] pub type W = crate :: W < DmacChnConfig_Spec > ;
#[doc = "Field `dmac_chn_en_0` reader - Channel enable: 0=disable; 1=enable"] pub type DmacChnEn0R = crate :: BitReader ;
#[doc = "Field `dmac_chn_en_0` writer - Channel enable: 0=disable; 1=enable"] pub type DmacChnEn0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_s_peripheral_0` reader - Source peripheral select"] pub type DmacSPeripheral0R = crate :: FieldReader ;
#[doc = "Field `dmac_s_peripheral_0` writer - Source peripheral select"] pub type DmacSPeripheral0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ;
#[doc = "Field `dmac_d_peripheral_0` reader - Destination peripheral select"] pub type DmacDPeripheral0R = crate :: FieldReader ;
#[doc = "Field `dmac_d_peripheral_0` writer - Destination peripheral select"] pub type DmacDPeripheral0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ;
#[doc = "Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum DmacFlowCtl0 {
#[doc = "0: Memory to Memory, DMAC flow control"] Mem2memDmac = 0 ,
#[doc = "1: Memory to Peripheral, DMAC flow control"] Mem2perDmac = 1 ,
#[doc = "2: Peripheral to Memory, DMAC flow control"] Per2memDmac = 2 ,
#[doc = "3: Peripheral to Peripheral, DMAC flow control"] Per2perDmac = 3 ,
#[doc = "4: Peripheral to Peripheral, Destination flow control"] Per2perDst = 4 ,
#[doc = "5: Memory to Peripheral, Destination flow control"] Mem2perDst = 5 ,
#[doc = "6: Peripheral to Memory, Source flow control"] Per2memSrc = 6 ,
#[doc = "7: Peripheral to Peripheral, Source flow control"] Per2perSrc = 7 , } impl From < DmacFlowCtl0 > for u8 {
#[inline (always)] fn from (variant : DmacFlowCtl0) -> Self { variant as _ } } impl crate :: FieldSpec for DmacFlowCtl0 { type Ux = u8 ; } impl crate :: IsEnum for DmacFlowCtl0 { }
#[doc = "Field `dmac_flow_ctl_0` reader - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"] pub type DmacFlowCtl0R = crate :: FieldReader < DmacFlowCtl0 > ; impl DmacFlowCtl0R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> DmacFlowCtl0 { match self . bits { 0 => DmacFlowCtl0 :: Mem2memDmac , 1 => DmacFlowCtl0 :: Mem2perDmac , 2 => DmacFlowCtl0 :: Per2memDmac , 3 => DmacFlowCtl0 :: Per2perDmac , 4 => DmacFlowCtl0 :: Per2perDst , 5 => DmacFlowCtl0 :: Mem2perDst , 6 => DmacFlowCtl0 :: Per2memSrc , 7 => DmacFlowCtl0 :: Per2perSrc , _ => unreachable ! () , } }
#[doc = "Memory to Memory, DMAC flow control"]
#[inline (always)] pub fn is_mem2mem_dmac (& self) -> bool { * self == DmacFlowCtl0 :: Mem2memDmac }
#[doc = "Memory to Peripheral, DMAC flow control"]
#[inline (always)] pub fn is_mem2per_dmac (& self) -> bool { * self == DmacFlowCtl0 :: Mem2perDmac }
#[doc = "Peripheral to Memory, DMAC flow control"]
#[inline (always)] pub fn is_per2mem_dmac (& self) -> bool { * self == DmacFlowCtl0 :: Per2memDmac }
#[doc = "Peripheral to Peripheral, DMAC flow control"]
#[inline (always)] pub fn is_per2per_dmac (& self) -> bool { * self == DmacFlowCtl0 :: Per2perDmac }
#[doc = "Peripheral to Peripheral, Destination flow control"]
#[inline (always)] pub fn is_per2per_dst (& self) -> bool { * self == DmacFlowCtl0 :: Per2perDst }
#[doc = "Memory to Peripheral, Destination flow control"]
#[inline (always)] pub fn is_mem2per_dst (& self) -> bool { * self == DmacFlowCtl0 :: Mem2perDst }
#[doc = "Peripheral to Memory, Source flow control"]
#[inline (always)] pub fn is_per2mem_src (& self) -> bool { * self == DmacFlowCtl0 :: Per2memSrc }
#[doc = "Peripheral to Peripheral, Source flow control"]
#[inline (always)] pub fn is_per2per_src (& self) -> bool { * self == DmacFlowCtl0 :: Per2perSrc } }
#[doc = "Field `dmac_flow_ctl_0` writer - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"] pub type DmacFlowCtl0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 , DmacFlowCtl0 , crate :: Safe > ; impl < 'a , REG > DmacFlowCtl0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Memory to Memory, DMAC flow control"]
#[inline (always)] pub fn mem2mem_dmac (self) -> & 'a mut crate :: W < REG > { self . variant (DmacFlowCtl0 :: Mem2memDmac) }
#[doc = "Memory to Peripheral, DMAC flow control"]
#[inline (always)] pub fn mem2per_dmac (self) -> & 'a mut crate :: W < REG > { self . variant (DmacFlowCtl0 :: Mem2perDmac) }
#[doc = "Peripheral to Memory, DMAC flow control"]
#[inline (always)] pub fn per2mem_dmac (self) -> & 'a mut crate :: W < REG > { self . variant (DmacFlowCtl0 :: Per2memDmac) }
#[doc = "Peripheral to Peripheral, DMAC flow control"]
#[inline (always)] pub fn per2per_dmac (self) -> & 'a mut crate :: W < REG > { self . variant (DmacFlowCtl0 :: Per2perDmac) }
#[doc = "Peripheral to Peripheral, Destination flow control"]
#[inline (always)] pub fn per2per_dst (self) -> & 'a mut crate :: W < REG > { self . variant (DmacFlowCtl0 :: Per2perDst) }
#[doc = "Memory to Peripheral, Destination flow control"]
#[inline (always)] pub fn mem2per_dst (self) -> & 'a mut crate :: W < REG > { self . variant (DmacFlowCtl0 :: Mem2perDst) }
#[doc = "Peripheral to Memory, Source flow control"]
#[inline (always)] pub fn per2mem_src (self) -> & 'a mut crate :: W < REG > { self . variant (DmacFlowCtl0 :: Per2memSrc) }
#[doc = "Peripheral to Peripheral, Source flow control"]
#[inline (always)] pub fn per2per_src (self) -> & 'a mut crate :: W < REG > { self . variant (DmacFlowCtl0 :: Per2perSrc) } }
#[doc = "Field `dmac_int_en_0` reader - Error interrupt mask: 0=masked; 1=unmasked"] pub type DmacIntEn0R = crate :: BitReader ;
#[doc = "Field `dmac_int_en_0` writer - Error interrupt mask: 0=masked; 1=unmasked"] pub type DmacIntEn0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_int_tc_0` reader - Transfer complete interrupt mask: 0=masked; 1=unmasked"] pub type DmacIntTc0R = crate :: BitReader ;
#[doc = "Field `dmac_int_tc_0` writer - Transfer complete interrupt mask: 0=masked; 1=unmasked"] pub type DmacIntTc0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_lock_0` reader - Bus lock: 0=disabled; 1=enabled"] pub type DmacLock0R = crate :: BitReader ;
#[doc = "Field `dmac_lock_0` writer - Bus lock: 0=disabled; 1=enabled"] pub type DmacLock0W < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dmac_active_0` reader - FIFO has data: 0=no; 1=yes"] pub type DmacActive0R = crate :: BitReader ;
#[doc = "Field `dmac_halt_0` reader - Halt: 0=allow DMA; 1=ignore DMA requests"] pub type DmacHalt0R = crate :: BitReader ;
#[doc = "Field `dmac_halt_0` writer - Halt: 0=allow DMA; 1=ignore DMA requests"] pub type DmacHalt0W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Channel enable: 0=disable; 1=enable"]
#[inline (always)] pub fn dmac_chn_en_0 (& self) -> DmacChnEn0R { DmacChnEn0R :: new ((self . bits & 1) != 0) }
#[doc = "Bits 1:4 - Source peripheral select"]
#[inline (always)] pub fn dmac_s_peripheral_0 (& self) -> DmacSPeripheral0R { DmacSPeripheral0R :: new (((self . bits >> 1) & 0x0f) as u8) }
#[doc = "Bits 5:8 - Destination peripheral select"]
#[inline (always)] pub fn dmac_d_peripheral_0 (& self) -> DmacDPeripheral0R { DmacDPeripheral0R :: new (((self . bits >> 5) & 0x0f) as u8) }
#[doc = "Bits 9:11 - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
#[inline (always)] pub fn dmac_flow_ctl_0 (& self) -> DmacFlowCtl0R { DmacFlowCtl0R :: new (((self . bits >> 9) & 7) as u8) }
#[doc = "Bit 12 - Error interrupt mask: 0=masked; 1=unmasked"]
#[inline (always)] pub fn dmac_int_en_0 (& self) -> DmacIntEn0R { DmacIntEn0R :: new (((self . bits >> 12) & 1) != 0) }
#[doc = "Bit 13 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
#[inline (always)] pub fn dmac_int_tc_0 (& self) -> DmacIntTc0R { DmacIntTc0R :: new (((self . bits >> 13) & 1) != 0) }
#[doc = "Bit 14 - Bus lock: 0=disabled; 1=enabled"]
#[inline (always)] pub fn dmac_lock_0 (& self) -> DmacLock0R { DmacLock0R :: new (((self . bits >> 14) & 1) != 0) }
#[doc = "Bit 15 - FIFO has data: 0=no; 1=yes"]
#[inline (always)] pub fn dmac_active_0 (& self) -> DmacActive0R { DmacActive0R :: new (((self . bits >> 15) & 1) != 0) }
#[doc = "Bit 16 - Halt: 0=allow DMA; 1=ignore DMA requests"]
#[inline (always)] pub fn dmac_halt_0 (& self) -> DmacHalt0R { DmacHalt0R :: new (((self . bits >> 16) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Channel enable: 0=disable; 1=enable"]
#[inline (always)] pub fn dmac_chn_en_0 (& mut self) -> DmacChnEn0W < '_ , DmacChnConfig_Spec > { DmacChnEn0W :: new (self , 0) }
#[doc = "Bits 1:4 - Source peripheral select"]
#[inline (always)] pub fn dmac_s_peripheral_0 (& mut self) -> DmacSPeripheral0W < '_ , DmacChnConfig_Spec > { DmacSPeripheral0W :: new (self , 1) }
#[doc = "Bits 5:8 - Destination peripheral select"]
#[inline (always)] pub fn dmac_d_peripheral_0 (& mut self) -> DmacDPeripheral0W < '_ , DmacChnConfig_Spec > { DmacDPeripheral0W :: new (self , 5) }
#[doc = "Bits 9:11 - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
#[inline (always)] pub fn dmac_flow_ctl_0 (& mut self) -> DmacFlowCtl0W < '_ , DmacChnConfig_Spec > { DmacFlowCtl0W :: new (self , 9) }
#[doc = "Bit 12 - Error interrupt mask: 0=masked; 1=unmasked"]
#[inline (always)] pub fn dmac_int_en_0 (& mut self) -> DmacIntEn0W < '_ , DmacChnConfig_Spec > { DmacIntEn0W :: new (self , 12) }
#[doc = "Bit 13 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
#[inline (always)] pub fn dmac_int_tc_0 (& mut self) -> DmacIntTc0W < '_ , DmacChnConfig_Spec > { DmacIntTc0W :: new (self , 13) }
#[doc = "Bit 14 - Bus lock: 0=disabled; 1=enabled"]
#[inline (always)] pub fn dmac_lock_0 (& mut self) -> DmacLock0W < '_ , DmacChnConfig_Spec > { DmacLock0W :: new (self , 14) }
#[doc = "Bit 16 - Halt: 0=allow DMA; 1=ignore DMA requests"]
#[inline (always)] pub fn dmac_halt_0 (& mut self) -> DmacHalt0W < '_ , DmacChnConfig_Spec > { DmacHalt0W :: new (self , 16) } }
#[doc = "Channel %s \\[dim=4\\] configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_config_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_config_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DmacChnConfig_Spec ; impl crate :: RegisterSpec for DmacChnConfig_Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`dmac_chn_config_::R`](R) reader structure"] impl crate :: Readable for DmacChnConfig_Spec { }
#[doc = "`write(|w| ..)` method takes [`dmac_chn_config_::W`](W) writer structure"] impl crate :: Writable for DmacChnConfig_Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DMAC_CHN_CONFIG_%s to value 0"] impl crate :: Resettable for DmacChnConfig_Spec { } } }
#[doc = "SPI Flash Controller configuration"] pub type SfcCfg = crate :: Periph < sfc_cfg :: RegisterBlock , 0x4800_0000 > ; impl core :: fmt :: Debug for SfcCfg { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("SfcCfg") . finish () } }
#[doc = "SPI Flash Controller configuration"] pub mod sfc_cfg {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x0100] , global_config : GlobalConfig , _reserved1 : [u8 ; 0x0c] , timing : Timing , _reserved2 : [u8 ; 0x0c] , int_raw_status : IntRawStatus , int_status : IntStatus , int_mask : IntMask , int_clear : IntClear , soft_rst_mask : SoftRstMask , _reserved7 : [u8 ; 0xcc] , bus_config1 : BusConfig1 , bus_config2 : BusConfig2 , _reserved9 : [u8 ; 0x38] , bus_dma_ctrl : BusDmaCtrl , bus_dma_mem_saddr : BusDmaMemSaddr , bus_dma_flash_saddr : BusDmaFlashSaddr , bus_dma_len : BusDmaLen , bus_dma_ahb_ctrl : BusDmaAhbCtrl , _reserved14 : [u8 ; 0xac] , cmd_config : CmdConfig , _reserved15 : [u8 ; 0x04] , cmd_ins : CmdIns , cmd_addr : CmdAddr , _reserved17 : [u8 ; 0xf0] , cmd_databuf_0 : CmdDatabuf0 , cmd_databuf_1 : CmdDatabuf1 , cmd_databuf_2 : CmdDatabuf2 , cmd_databuf_3 : CmdDatabuf3 , cmd_databuf_4 : CmdDatabuf4 , cmd_databuf_5 : CmdDatabuf5 , cmd_databuf_6 : CmdDatabuf6 , cmd_databuf_7 : CmdDatabuf7 , cmd_databuf_8 : CmdDatabuf8 , cmd_databuf_9 : CmdDatabuf9 , cmd_databuf_10 : CmdDatabuf10 , cmd_databuf_11 : CmdDatabuf11 , cmd_databuf_12 : CmdDatabuf12 , cmd_databuf_13 : CmdDatabuf13 , cmd_databuf_14 : CmdDatabuf14 , cmd_databuf_15 : CmdDatabuf15 , _reserved33 : [u8 ; 0x0ec0] , lea_lp_en : LeaLpEn , lea_dfx_info : LeaDfxInfo , _reserved35 : [u8 ; 0x02f8] , lea_iv_vld : LeaIvVld , } impl RegisterBlock {
#[doc = "0x100 - Global configuration register"]
#[inline (always)] pub const fn global_config (& self) -> & GlobalConfig { & self . global_config }
#[doc = "0x110 - Timing configuration register"]
#[inline (always)] pub const fn timing (& self) -> & Timing { & self . timing }
#[doc = "0x120 - Interrupt raw status register"]
#[inline (always)] pub const fn int_raw_status (& self) -> & IntRawStatus { & self . int_raw_status }
#[doc = "0x124 - Interrupt status register (masked)"]
#[inline (always)] pub const fn int_status (& self) -> & IntStatus { & self . int_status }
#[doc = "0x128 - Interrupt mask register"]
#[inline (always)] pub const fn int_mask (& self) -> & IntMask { & self . int_mask }
#[doc = "0x12c - Interrupt clear register"]
#[inline (always)] pub const fn int_clear (& self) -> & IntClear { & self . int_clear }
#[doc = "0x130 - Soft reset mask register"]
#[inline (always)] pub const fn soft_rst_mask (& self) -> & SoftRstMask { & self . soft_rst_mask }
#[doc = "0x200 - Bus operation config 1"]
#[inline (always)] pub const fn bus_config1 (& self) -> & BusConfig1 { & self . bus_config1 }
#[doc = "0x204 - Bus operation config 2"]
#[inline (always)] pub const fn bus_config2 (& self) -> & BusConfig2 { & self . bus_config2 }
#[doc = "0x240 - DMA operation control register"]
#[inline (always)] pub const fn bus_dma_ctrl (& self) -> & BusDmaCtrl { & self . bus_dma_ctrl }
#[doc = "0x244 - DMA memory start address"]
#[inline (always)] pub const fn bus_dma_mem_saddr (& self) -> & BusDmaMemSaddr { & self . bus_dma_mem_saddr }
#[doc = "0x248 - DMA Flash start address"]
#[inline (always)] pub const fn bus_dma_flash_saddr (& self) -> & BusDmaFlashSaddr { & self . bus_dma_flash_saddr }
#[doc = "0x24c - DMA transfer length"]
#[inline (always)] pub const fn bus_dma_len (& self) -> & BusDmaLen { & self . bus_dma_len }
#[doc = "0x250 - DMA AHB burst control"]
#[inline (always)] pub const fn bus_dma_ahb_ctrl (& self) -> & BusDmaAhbCtrl { & self . bus_dma_ahb_ctrl }
#[doc = "0x300 - Command operation config"]
#[inline (always)] pub const fn cmd_config (& self) -> & CmdConfig { & self . cmd_config }
#[doc = "0x308 - Command instruction register"]
#[inline (always)] pub const fn cmd_ins (& self) -> & CmdIns { & self . cmd_ins }
#[doc = "0x30c - Command address register"]
#[inline (always)] pub const fn cmd_addr (& self) -> & CmdAddr { & self . cmd_addr }
#[doc = "0x400 - Command data buffer 0"]
#[inline (always)] pub const fn cmd_databuf_0 (& self) -> & CmdDatabuf0 { & self . cmd_databuf_0 }
#[doc = "0x404 - Command data buffer 1"]
#[inline (always)] pub const fn cmd_databuf_1 (& self) -> & CmdDatabuf1 { & self . cmd_databuf_1 }
#[doc = "0x408 - Command data buffer 2"]
#[inline (always)] pub const fn cmd_databuf_2 (& self) -> & CmdDatabuf2 { & self . cmd_databuf_2 }
#[doc = "0x40c - Command data buffer 3"]
#[inline (always)] pub const fn cmd_databuf_3 (& self) -> & CmdDatabuf3 { & self . cmd_databuf_3 }
#[doc = "0x410 - Command data buffer 4"]
#[inline (always)] pub const fn cmd_databuf_4 (& self) -> & CmdDatabuf4 { & self . cmd_databuf_4 }
#[doc = "0x414 - Command data buffer 5"]
#[inline (always)] pub const fn cmd_databuf_5 (& self) -> & CmdDatabuf5 { & self . cmd_databuf_5 }
#[doc = "0x418 - Command data buffer 6"]
#[inline (always)] pub const fn cmd_databuf_6 (& self) -> & CmdDatabuf6 { & self . cmd_databuf_6 }
#[doc = "0x41c - Command data buffer 7"]
#[inline (always)] pub const fn cmd_databuf_7 (& self) -> & CmdDatabuf7 { & self . cmd_databuf_7 }
#[doc = "0x420 - Command data buffer 8"]
#[inline (always)] pub const fn cmd_databuf_8 (& self) -> & CmdDatabuf8 { & self . cmd_databuf_8 }
#[doc = "0x424 - Command data buffer 9"]
#[inline (always)] pub const fn cmd_databuf_9 (& self) -> & CmdDatabuf9 { & self . cmd_databuf_9 }
#[doc = "0x428 - Command data buffer 10"]
#[inline (always)] pub const fn cmd_databuf_10 (& self) -> & CmdDatabuf10 { & self . cmd_databuf_10 }
#[doc = "0x42c - Command data buffer 11"]
#[inline (always)] pub const fn cmd_databuf_11 (& self) -> & CmdDatabuf11 { & self . cmd_databuf_11 }
#[doc = "0x430 - Command data buffer 12"]
#[inline (always)] pub const fn cmd_databuf_12 (& self) -> & CmdDatabuf12 { & self . cmd_databuf_12 }
#[doc = "0x434 - Command data buffer 13"]
#[inline (always)] pub const fn cmd_databuf_13 (& self) -> & CmdDatabuf13 { & self . cmd_databuf_13 }
#[doc = "0x438 - Command data buffer 14"]
#[inline (always)] pub const fn cmd_databuf_14 (& self) -> & CmdDatabuf14 { & self . cmd_databuf_14 }
#[doc = "0x43c - Command data buffer 15"]
#[inline (always)] pub const fn cmd_databuf_15 (& self) -> & CmdDatabuf15 { & self . cmd_databuf_15 }
#[doc = "0x1300 - LEA control register"]
#[inline (always)] pub const fn lea_lp_en (& self) -> & LeaLpEn { & self . lea_lp_en }
#[doc = "0x1304 - LEA DFX register"]
#[inline (always)] pub const fn lea_dfx_info (& self) -> & LeaDfxInfo { & self . lea_dfx_info }
#[doc = "0x1600 - LEA IV valid register"]
#[inline (always)] pub const fn lea_iv_vld (& self) -> & LeaIvVld { & self . lea_iv_vld } }
#[doc = "GLOBAL_CONFIG (rw) register accessor: Global configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`global_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`global_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@global_config`] module"]
#[doc (alias = "GLOBAL_CONFIG")] pub type GlobalConfig = crate :: Reg < global_config :: GlobalConfigSpec > ;
#[doc = "Global configuration register"] pub mod global_config {
#[doc = "Register `GLOBAL_CONFIG` reader"] pub type R = crate :: R < GlobalConfigSpec > ;
#[doc = "Register `GLOBAL_CONFIG` writer"] pub type W = crate :: W < GlobalConfigSpec > ;
#[doc = "SPI mode: 0=Mode0; 1=Mode3\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Mode {
#[doc = "0: SPI Mode 0 (CPOL=0, CPHA=0)"] Mode0 = 0 ,
#[doc = "1: SPI Mode 3 (CPOL=1, CPHA=1)"] Mode3 = 1 , } impl From < Mode > for bool {
#[inline (always)] fn from (variant : Mode) -> Self { variant as u8 != 0 } }
#[doc = "Field `mode` reader - SPI mode: 0=Mode0; 1=Mode3"] pub type ModeR = crate :: BitReader < Mode > ; impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Mode { match self . bits { false => Mode :: Mode0 , true => Mode :: Mode3 , } }
#[doc = "SPI Mode 0 (CPOL=0, CPHA=0)"]
#[inline (always)] pub fn is_mode0 (& self) -> bool { * self == Mode :: Mode0 }
#[doc = "SPI Mode 3 (CPOL=1, CPHA=1)"]
#[inline (always)] pub fn is_mode3 (& self) -> bool { * self == Mode :: Mode3 } }
#[doc = "Field `mode` writer - SPI mode: 0=Mode0; 1=Mode3"] pub type ModeW < 'a , REG > = crate :: BitWriter < 'a , REG , Mode > ; impl < 'a , REG > ModeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "SPI Mode 0 (CPOL=0, CPHA=0)"]
#[inline (always)] pub fn mode0 (self) -> & 'a mut crate :: W < REG > { self . variant (Mode :: Mode0) }
#[doc = "SPI Mode 3 (CPOL=1, CPHA=1)"]
#[inline (always)] pub fn mode3 (self) -> & 'a mut crate :: W < REG > { self . variant (Mode :: Mode3) } }
#[doc = "Field `wp_en` reader - Hardware write protect: 0=disabled; 1=enabled"] pub type WpEnR = crate :: BitReader ;
#[doc = "Field `wp_en` writer - Hardware write protect: 0=disabled; 1=enabled"] pub type WpEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Address mode: 0=3byte; 1=4byte. NOTE: write has no effect when CMD_CONFIG\\[start\\]=1\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum FlashAddrMode {
#[doc = "0: 3-byte addressing"] Addr3byte = 0 ,
#[doc = "1: 4-byte addressing"] Addr4byte = 1 , } impl From < FlashAddrMode > for bool {
#[inline (always)] fn from (variant : FlashAddrMode) -> Self { variant as u8 != 0 } }
#[doc = "Field `flash_addr_mode` reader - Address mode: 0=3byte; 1=4byte. NOTE: write has no effect when CMD_CONFIG\\[start\\]=1"] pub type FlashAddrModeR = crate :: BitReader < FlashAddrMode > ; impl FlashAddrModeR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> FlashAddrMode { match self . bits { false => FlashAddrMode :: Addr3byte , true => FlashAddrMode :: Addr4byte , } }
#[doc = "3-byte addressing"]
#[inline (always)] pub fn is_addr3byte (& self) -> bool { * self == FlashAddrMode :: Addr3byte }
#[doc = "4-byte addressing"]
#[inline (always)] pub fn is_addr4byte (& self) -> bool { * self == FlashAddrMode :: Addr4byte } }
#[doc = "Field `flash_addr_mode` writer - Address mode: 0=3byte; 1=4byte. NOTE: write has no effect when CMD_CONFIG\\[start\\]=1"] pub type FlashAddrModeW < 'a , REG > = crate :: BitWriter < 'a , REG , FlashAddrMode > ; impl < 'a , REG > FlashAddrModeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "3-byte addressing"]
#[inline (always)] pub fn addr3byte (self) -> & 'a mut crate :: W < REG > { self . variant (FlashAddrMode :: Addr3byte) }
#[doc = "4-byte addressing"]
#[inline (always)] pub fn addr4byte (self) -> & 'a mut crate :: W < REG > { self . variant (FlashAddrMode :: Addr4byte) } }
#[doc = "Field `rd_delay` reader - SPI read data delay: 000=0.5~1clk; 001=1~1.5clk; etc."] pub type RdDelayR = crate :: FieldReader ;
#[doc = "Field `rd_delay` writer - SPI read data delay: 000=0.5~1clk; 001=1~1.5clk; etc."] pub type RdDelayW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bit 0 - SPI mode: 0=Mode0; 1=Mode3"]
#[inline (always)] pub fn mode (& self) -> ModeR { ModeR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Hardware write protect: 0=disabled; 1=enabled"]
#[inline (always)] pub fn wp_en (& self) -> WpEnR { WpEnR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Address mode: 0=3byte; 1=4byte. NOTE: write has no effect when CMD_CONFIG\\[start\\]=1"]
#[inline (always)] pub fn flash_addr_mode (& self) -> FlashAddrModeR { FlashAddrModeR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bits 3:5 - SPI read data delay: 000=0.5~1clk; 001=1~1.5clk; etc."]
#[inline (always)] pub fn rd_delay (& self) -> RdDelayR { RdDelayR :: new (((self . bits >> 3) & 7) as u8) } } impl W {
#[doc = "Bit 0 - SPI mode: 0=Mode0; 1=Mode3"]
#[inline (always)] pub fn mode (& mut self) -> ModeW < '_ , GlobalConfigSpec > { ModeW :: new (self , 0) }
#[doc = "Bit 1 - Hardware write protect: 0=disabled; 1=enabled"]
#[inline (always)] pub fn wp_en (& mut self) -> WpEnW < '_ , GlobalConfigSpec > { WpEnW :: new (self , 1) }
#[doc = "Bit 2 - Address mode: 0=3byte; 1=4byte. NOTE: write has no effect when CMD_CONFIG\\[start\\]=1"]
#[inline (always)] pub fn flash_addr_mode (& mut self) -> FlashAddrModeW < '_ , GlobalConfigSpec > { FlashAddrModeW :: new (self , 2) }
#[doc = "Bits 3:5 - SPI read data delay: 000=0.5~1clk; 001=1~1.5clk; etc."]
#[inline (always)] pub fn rd_delay (& mut self) -> RdDelayW < '_ , GlobalConfigSpec > { RdDelayW :: new (self , 3) } }
#[doc = "Global configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`global_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`global_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GlobalConfigSpec ; impl crate :: RegisterSpec for GlobalConfigSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`global_config::R`](R) reader structure"] impl crate :: Readable for GlobalConfigSpec { }
#[doc = "`write(|w| ..)` method takes [`global_config::W`](W) writer structure"] impl crate :: Writable for GlobalConfigSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets GLOBAL_CONFIG to value 0"] impl crate :: Resettable for GlobalConfigSpec { } }
#[doc = "TIMING (rw) register accessor: Timing configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`timing::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timing::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timing`] module"]
#[doc (alias = "TIMING")] pub type Timing = crate :: Reg < timing :: TimingSpec > ;
#[doc = "Timing configuration register"] pub mod timing {
#[doc = "Register `TIMING` reader"] pub type R = crate :: R < TimingSpec > ;
#[doc = "Register `TIMING` writer"] pub type W = crate :: W < TimingSpec > ;
#[doc = "Field `tshsl` reader - Inter-operation delay: (n+2) clock cycles"] pub type TshslR = crate :: FieldReader ;
#[doc = "Field `tshsl` writer - Inter-operation delay: (n+2) clock cycles"] pub type TshslW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ;
#[doc = "Field `tcss` reader - CS setup time: (n+1) clock cycles"] pub type TcssR = crate :: FieldReader ;
#[doc = "Field `tcss` writer - CS setup time: (n+1) clock cycles"] pub type TcssW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `tcsh` reader - CS hold time: (n+1) clock cycles"] pub type TcshR = crate :: FieldReader ;
#[doc = "Field `tcsh` writer - CS hold time: (n+1) clock cycles"] pub type TcshW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:3 - Inter-operation delay: (n+2) clock cycles"]
#[inline (always)] pub fn tshsl (& self) -> TshslR { TshslR :: new ((self . bits & 0x0f) as u8) }
#[doc = "Bits 8:10 - CS setup time: (n+1) clock cycles"]
#[inline (always)] pub fn tcss (& self) -> TcssR { TcssR :: new (((self . bits >> 8) & 7) as u8) }
#[doc = "Bits 12:14 - CS hold time: (n+1) clock cycles"]
#[inline (always)] pub fn tcsh (& self) -> TcshR { TcshR :: new (((self . bits >> 12) & 7) as u8) } } impl W {
#[doc = "Bits 0:3 - Inter-operation delay: (n+2) clock cycles"]
#[inline (always)] pub fn tshsl (& mut self) -> TshslW < '_ , TimingSpec > { TshslW :: new (self , 0) }
#[doc = "Bits 8:10 - CS setup time: (n+1) clock cycles"]
#[inline (always)] pub fn tcss (& mut self) -> TcssW < '_ , TimingSpec > { TcssW :: new (self , 8) }
#[doc = "Bits 12:14 - CS hold time: (n+1) clock cycles"]
#[inline (always)] pub fn tcsh (& mut self) -> TcshW < '_ , TimingSpec > { TcshW :: new (self , 12) } }
#[doc = "Timing configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`timing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TimingSpec ; impl crate :: RegisterSpec for TimingSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`timing::R`](R) reader structure"] impl crate :: Readable for TimingSpec { }
#[doc = "`write(|w| ..)` method takes [`timing::W`](W) writer structure"] impl crate :: Writable for TimingSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TIMING to value 0x660f"] impl crate :: Resettable for TimingSpec { const RESET_VALUE : u32 = 0x660f ; } }
#[doc = "INT_RAW_STATUS (rw) register accessor: Interrupt raw status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw_status`] module"]
#[doc (alias = "INT_RAW_STATUS")] pub type IntRawStatus = crate :: Reg < int_raw_status :: IntRawStatusSpec > ;
#[doc = "Interrupt raw status register"] pub mod int_raw_status {
#[doc = "Register `INT_RAW_STATUS` reader"] pub type R = crate :: R < IntRawStatusSpec > ;
#[doc = "Register `INT_RAW_STATUS` writer"] pub type W = crate :: W < IntRawStatusSpec > ;
#[doc = "Field `cmd_op_end_raw_status` reader - Command operation end raw status"] pub type CmdOpEndRawStatusR = crate :: BitReader ;
#[doc = "Field `dma_done_int_raw_status` reader - DMA done raw status"] pub type DmaDoneIntRawStatusR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Command operation end raw status"]
#[inline (always)] pub fn cmd_op_end_raw_status (& self) -> CmdOpEndRawStatusR { CmdOpEndRawStatusR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - DMA done raw status"]
#[inline (always)] pub fn dma_done_int_raw_status (& self) -> DmaDoneIntRawStatusR { DmaDoneIntRawStatusR :: new (((self . bits >> 1) & 1) != 0) } } impl W { }
#[doc = "Interrupt raw status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntRawStatusSpec ; impl crate :: RegisterSpec for IntRawStatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`int_raw_status::R`](R) reader structure"] impl crate :: Readable for IntRawStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`int_raw_status::W`](W) writer structure"] impl crate :: Writable for IntRawStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INT_RAW_STATUS to value 0"] impl crate :: Resettable for IntRawStatusSpec { } }
#[doc = "INT_STATUS (rw) register accessor: Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`] module"]
#[doc (alias = "INT_STATUS")] pub type IntStatus = crate :: Reg < int_status :: IntStatusSpec > ;
#[doc = "Interrupt status register (masked)"] pub mod int_status {
#[doc = "Register `INT_STATUS` reader"] pub type R = crate :: R < IntStatusSpec > ;
#[doc = "Register `INT_STATUS` writer"] pub type W = crate :: W < IntStatusSpec > ;
#[doc = "Field `cmd_op_end_status` reader - Command operation end status"] pub type CmdOpEndStatusR = crate :: BitReader ;
#[doc = "Field `dma_done_int_status` reader - DMA done status"] pub type DmaDoneIntStatusR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Command operation end status"]
#[inline (always)] pub fn cmd_op_end_status (& self) -> CmdOpEndStatusR { CmdOpEndStatusR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - DMA done status"]
#[inline (always)] pub fn dma_done_int_status (& self) -> DmaDoneIntStatusR { DmaDoneIntStatusR :: new (((self . bits >> 1) & 1) != 0) } } impl W { }
#[doc = "Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntStatusSpec ; impl crate :: RegisterSpec for IntStatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`int_status::R`](R) reader structure"] impl crate :: Readable for IntStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`int_status::W`](W) writer structure"] impl crate :: Writable for IntStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INT_STATUS to value 0"] impl crate :: Resettable for IntStatusSpec { } }
#[doc = "INT_MASK (rw) register accessor: Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_mask`] module"]
#[doc (alias = "INT_MASK")] pub type IntMask = crate :: Reg < int_mask :: IntMaskSpec > ;
#[doc = "Interrupt mask register"] pub mod int_mask {
#[doc = "Register `INT_MASK` reader"] pub type R = crate :: R < IntMaskSpec > ;
#[doc = "Register `INT_MASK` writer"] pub type W = crate :: W < IntMaskSpec > ;
#[doc = "Field `cmd_op_end_int_mask` reader - Command end mask: 0=masked; 1=unmasked"] pub type CmdOpEndIntMaskR = crate :: BitReader ;
#[doc = "Field `cmd_op_end_int_mask` writer - Command end mask: 0=masked; 1=unmasked"] pub type CmdOpEndIntMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dma_done_int_mask` reader - DMA done mask"] pub type DmaDoneIntMaskR = crate :: BitReader ;
#[doc = "Field `dma_done_int_mask` writer - DMA done mask"] pub type DmaDoneIntMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Command end mask: 0=masked; 1=unmasked"]
#[inline (always)] pub fn cmd_op_end_int_mask (& self) -> CmdOpEndIntMaskR { CmdOpEndIntMaskR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - DMA done mask"]
#[inline (always)] pub fn dma_done_int_mask (& self) -> DmaDoneIntMaskR { DmaDoneIntMaskR :: new (((self . bits >> 1) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Command end mask: 0=masked; 1=unmasked"]
#[inline (always)] pub fn cmd_op_end_int_mask (& mut self) -> CmdOpEndIntMaskW < '_ , IntMaskSpec > { CmdOpEndIntMaskW :: new (self , 0) }
#[doc = "Bit 1 - DMA done mask"]
#[inline (always)] pub fn dma_done_int_mask (& mut self) -> DmaDoneIntMaskW < '_ , IntMaskSpec > { DmaDoneIntMaskW :: new (self , 1) } }
#[doc = "Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntMaskSpec ; impl crate :: RegisterSpec for IntMaskSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`int_mask::R`](R) reader structure"] impl crate :: Readable for IntMaskSpec { }
#[doc = "`write(|w| ..)` method takes [`int_mask::W`](W) writer structure"] impl crate :: Writable for IntMaskSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INT_MASK to value 0"] impl crate :: Resettable for IntMaskSpec { } }
#[doc = "INT_CLEAR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clear`] module"]
#[doc (alias = "INT_CLEAR")] pub type IntClear = crate :: Reg < int_clear :: IntClearSpec > ;
#[doc = "Interrupt clear register"] pub mod int_clear {
#[doc = "Register `INT_CLEAR` reader"] pub type R = crate :: R < IntClearSpec > ;
#[doc = "Register `INT_CLEAR` writer"] pub type W = crate :: W < IntClearSpec > ;
#[doc = "Field `cmd_op_end_int_clr` writer - Command end interrupt clear (self-clearing)"] pub type CmdOpEndIntClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dma_done_int_clr` writer - DMA done interrupt clear (self-clearing)"] pub type DmaDoneIntClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Command end interrupt clear (self-clearing)"]
#[inline (always)] pub fn cmd_op_end_int_clr (& mut self) -> CmdOpEndIntClrW < '_ , IntClearSpec > { CmdOpEndIntClrW :: new (self , 0) }
#[doc = "Bit 1 - DMA done interrupt clear (self-clearing)"]
#[inline (always)] pub fn dma_done_int_clr (& mut self) -> DmaDoneIntClrW < '_ , IntClearSpec > { DmaDoneIntClrW :: new (self , 1) } }
#[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntClearSpec ; impl crate :: RegisterSpec for IntClearSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`int_clear::R`](R) reader structure"] impl crate :: Readable for IntClearSpec { }
#[doc = "`write(|w| ..)` method takes [`int_clear::W`](W) writer structure"] impl crate :: Writable for IntClearSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INT_CLEAR to value 0"] impl crate :: Resettable for IntClearSpec { } }
#[doc = "SOFT_RST_MASK (rw) register accessor: Soft reset mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_rst_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_rst_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst_mask`] module"]
#[doc (alias = "SOFT_RST_MASK")] pub type SoftRstMask = crate :: Reg < soft_rst_mask :: SoftRstMaskSpec > ;
#[doc = "Soft reset mask register"] pub mod soft_rst_mask {
#[doc = "Register `SOFT_RST_MASK` reader"] pub type R = crate :: R < SoftRstMaskSpec > ;
#[doc = "Register `SOFT_RST_MASK` writer"] pub type W = crate :: W < SoftRstMaskSpec > ;
#[doc = "Field `sfc_bus_soft_rst_mask` reader - SFC bus soft reset mask: 0=reset active; 1=reset masked"] pub type SfcBusSoftRstMaskR = crate :: BitReader ;
#[doc = "Field `sfc_bus_soft_rst_mask` writer - SFC bus soft reset mask: 0=reset active; 1=reset masked"] pub type SfcBusSoftRstMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - SFC bus soft reset mask: 0=reset active; 1=reset masked"]
#[inline (always)] pub fn sfc_bus_soft_rst_mask (& self) -> SfcBusSoftRstMaskR { SfcBusSoftRstMaskR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - SFC bus soft reset mask: 0=reset active; 1=reset masked"]
#[inline (always)] pub fn sfc_bus_soft_rst_mask (& mut self) -> SfcBusSoftRstMaskW < '_ , SoftRstMaskSpec > { SfcBusSoftRstMaskW :: new (self , 0) } }
#[doc = "Soft reset mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_rst_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_rst_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SoftRstMaskSpec ; impl crate :: RegisterSpec for SoftRstMaskSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`soft_rst_mask::R`](R) reader structure"] impl crate :: Readable for SoftRstMaskSpec { }
#[doc = "`write(|w| ..)` method takes [`soft_rst_mask::W`](W) writer structure"] impl crate :: Writable for SoftRstMaskSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SOFT_RST_MASK to value 0x01"] impl crate :: Resettable for SoftRstMaskSpec { const RESET_VALUE : u32 = 0x01 ; } }
#[doc = "BUS_CONFIG1 (rw) register accessor: Bus operation config 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_config1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_config1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_config1`] module"]
#[doc (alias = "BUS_CONFIG1")] pub type BusConfig1 = crate :: Reg < bus_config1 :: BusConfig1Spec > ;
#[doc = "Bus operation config 1"] pub mod bus_config1 {
#[doc = "Register `BUS_CONFIG1` reader"] pub type R = crate :: R < BusConfig1Spec > ;
#[doc = "Register `BUS_CONFIG1` writer"] pub type W = crate :: W < BusConfig1Spec > ;
#[doc = "Field `rd_mem_if_type` reader - Read SPI interface type: 000=Standard; 001=Dual I/O; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"] pub type RdMemIfTypeR = crate :: FieldReader ;
#[doc = "Field `rd_mem_if_type` writer - Read SPI interface type: 000=Standard; 001=Dual I/O; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"] pub type RdMemIfTypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `rd_dummy_bytes` reader - Read dummy bytes: 000=0; 001=1; etc."] pub type RdDummyBytesR = crate :: FieldReader ;
#[doc = "Field `rd_dummy_bytes` writer - Read dummy bytes: 000=0; 001=1; etc."] pub type RdDummyBytesW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `rd_prefetch_cnt` reader - Read prefetch count: 00=none; 01=1clk; 10=2clk; 11=3clk"] pub type RdPrefetchCntR = crate :: FieldReader ;
#[doc = "Field `rd_prefetch_cnt` writer - Read prefetch count: 00=none; 01=1clk; 10=2clk; 11=3clk"] pub type RdPrefetchCntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ;
#[doc = "Field `rd_ins` reader - Read instruction code"] pub type RdInsR = crate :: FieldReader ;
#[doc = "Field `rd_ins` writer - Read instruction code"] pub type RdInsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ;
#[doc = "Field `wr_mem_if_type` reader - Write SPI interface type"] pub type WrMemIfTypeR = crate :: FieldReader ;
#[doc = "Field `wr_mem_if_type` writer - Write SPI interface type"] pub type WrMemIfTypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `wr_dummy_bytes` reader - Write dummy bytes"] pub type WrDummyBytesR = crate :: FieldReader ;
#[doc = "Field `wr_dummy_bytes` writer - Write dummy bytes"] pub type WrDummyBytesW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `wr_ins` reader - Write instruction code"] pub type WrInsR = crate :: FieldReader ;
#[doc = "Field `wr_ins` writer - Write instruction code"] pub type WrInsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ;
#[doc = "Field `wr_enable` reader - Bus write enable"] pub type WrEnableR = crate :: BitReader ;
#[doc = "Field `wr_enable` writer - Bus write enable"] pub type WrEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rd_enable` reader - Bus read enable"] pub type RdEnableR = crate :: BitReader ;
#[doc = "Field `rd_enable` writer - Bus read enable"] pub type RdEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:2 - Read SPI interface type: 000=Standard; 001=Dual I/O; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
#[inline (always)] pub fn rd_mem_if_type (& self) -> RdMemIfTypeR { RdMemIfTypeR :: new ((self . bits & 7) as u8) }
#[doc = "Bits 3:5 - Read dummy bytes: 000=0; 001=1; etc."]
#[inline (always)] pub fn rd_dummy_bytes (& self) -> RdDummyBytesR { RdDummyBytesR :: new (((self . bits >> 3) & 7) as u8) }
#[doc = "Bits 6:7 - Read prefetch count: 00=none; 01=1clk; 10=2clk; 11=3clk"]
#[inline (always)] pub fn rd_prefetch_cnt (& self) -> RdPrefetchCntR { RdPrefetchCntR :: new (((self . bits >> 6) & 3) as u8) }
#[doc = "Bits 8:15 - Read instruction code"]
#[inline (always)] pub fn rd_ins (& self) -> RdInsR { RdInsR :: new (((self . bits >> 8) & 0xff) as u8) }
#[doc = "Bits 16:18 - Write SPI interface type"]
#[inline (always)] pub fn wr_mem_if_type (& self) -> WrMemIfTypeR { WrMemIfTypeR :: new (((self . bits >> 16) & 7) as u8) }
#[doc = "Bits 19:21 - Write dummy bytes"]
#[inline (always)] pub fn wr_dummy_bytes (& self) -> WrDummyBytesR { WrDummyBytesR :: new (((self . bits >> 19) & 7) as u8) }
#[doc = "Bits 22:29 - Write instruction code"]
#[inline (always)] pub fn wr_ins (& self) -> WrInsR { WrInsR :: new (((self . bits >> 22) & 0xff) as u8) }
#[doc = "Bit 30 - Bus write enable"]
#[inline (always)] pub fn wr_enable (& self) -> WrEnableR { WrEnableR :: new (((self . bits >> 30) & 1) != 0) }
#[doc = "Bit 31 - Bus read enable"]
#[inline (always)] pub fn rd_enable (& self) -> RdEnableR { RdEnableR :: new (((self . bits >> 31) & 1) != 0) } } impl W {
#[doc = "Bits 0:2 - Read SPI interface type: 000=Standard; 001=Dual I/O; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
#[inline (always)] pub fn rd_mem_if_type (& mut self) -> RdMemIfTypeW < '_ , BusConfig1Spec > { RdMemIfTypeW :: new (self , 0) }
#[doc = "Bits 3:5 - Read dummy bytes: 000=0; 001=1; etc."]
#[inline (always)] pub fn rd_dummy_bytes (& mut self) -> RdDummyBytesW < '_ , BusConfig1Spec > { RdDummyBytesW :: new (self , 3) }
#[doc = "Bits 6:7 - Read prefetch count: 00=none; 01=1clk; 10=2clk; 11=3clk"]
#[inline (always)] pub fn rd_prefetch_cnt (& mut self) -> RdPrefetchCntW < '_ , BusConfig1Spec > { RdPrefetchCntW :: new (self , 6) }
#[doc = "Bits 8:15 - Read instruction code"]
#[inline (always)] pub fn rd_ins (& mut self) -> RdInsW < '_ , BusConfig1Spec > { RdInsW :: new (self , 8) }
#[doc = "Bits 16:18 - Write SPI interface type"]
#[inline (always)] pub fn wr_mem_if_type (& mut self) -> WrMemIfTypeW < '_ , BusConfig1Spec > { WrMemIfTypeW :: new (self , 16) }
#[doc = "Bits 19:21 - Write dummy bytes"]
#[inline (always)] pub fn wr_dummy_bytes (& mut self) -> WrDummyBytesW < '_ , BusConfig1Spec > { WrDummyBytesW :: new (self , 19) }
#[doc = "Bits 22:29 - Write instruction code"]
#[inline (always)] pub fn wr_ins (& mut self) -> WrInsW < '_ , BusConfig1Spec > { WrInsW :: new (self , 22) }
#[doc = "Bit 30 - Bus write enable"]
#[inline (always)] pub fn wr_enable (& mut self) -> WrEnableW < '_ , BusConfig1Spec > { WrEnableW :: new (self , 30) }
#[doc = "Bit 31 - Bus read enable"]
#[inline (always)] pub fn rd_enable (& mut self) -> RdEnableW < '_ , BusConfig1Spec > { RdEnableW :: new (self , 31) } }
#[doc = "Bus operation config 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_config1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_config1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BusConfig1Spec ; impl crate :: RegisterSpec for BusConfig1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`bus_config1::R`](R) reader structure"] impl crate :: Readable for BusConfig1Spec { }
#[doc = "`write(|w| ..)` method takes [`bus_config1::W`](W) writer structure"] impl crate :: Writable for BusConfig1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets BUS_CONFIG1 to value 0x8080_0300"] impl crate :: Resettable for BusConfig1Spec { const RESET_VALUE : u32 = 0x8080_0300 ; } }
#[doc = "BUS_CONFIG2 (rw) register accessor: Bus operation config 2\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_config2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_config2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_config2`] module"]
#[doc (alias = "BUS_CONFIG2")] pub type BusConfig2 = crate :: Reg < bus_config2 :: BusConfig2Spec > ;
#[doc = "Bus operation config 2"] pub mod bus_config2 {
#[doc = "Register `BUS_CONFIG2` reader"] pub type R = crate :: R < BusConfig2Spec > ;
#[doc = "Register `BUS_CONFIG2` writer"] pub type W = crate :: W < BusConfig2Spec > ;
#[doc = "Field `wip_locate` reader - WIP bit position in Flash status register: 000=bit0; etc."] pub type WipLocateR = crate :: FieldReader ;
#[doc = "Field `wip_locate` writer - WIP bit position in Flash status register: 000=bit0; etc."] pub type WipLocateW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - WIP bit position in Flash status register: 000=bit0; etc."]
#[inline (always)] pub fn wip_locate (& self) -> WipLocateR { WipLocateR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - WIP bit position in Flash status register: 000=bit0; etc."]
#[inline (always)] pub fn wip_locate (& mut self) -> WipLocateW < '_ , BusConfig2Spec > { WipLocateW :: new (self , 0) } }
#[doc = "Bus operation config 2\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_config2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_config2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BusConfig2Spec ; impl crate :: RegisterSpec for BusConfig2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`bus_config2::R`](R) reader structure"] impl crate :: Readable for BusConfig2Spec { }
#[doc = "`write(|w| ..)` method takes [`bus_config2::W`](W) writer structure"] impl crate :: Writable for BusConfig2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets BUS_CONFIG2 to value 0"] impl crate :: Resettable for BusConfig2Spec { } }
#[doc = "BUS_DMA_CTRL (rw) register accessor: DMA operation control register\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_dma_ctrl`] module"]
#[doc (alias = "BUS_DMA_CTRL")] pub type BusDmaCtrl = crate :: Reg < bus_dma_ctrl :: BusDmaCtrlSpec > ;
#[doc = "DMA operation control register"] pub mod bus_dma_ctrl {
#[doc = "Register `BUS_DMA_CTRL` reader"] pub type R = crate :: R < BusDmaCtrlSpec > ;
#[doc = "Register `BUS_DMA_CTRL` writer"] pub type W = crate :: W < BusDmaCtrlSpec > ;
#[doc = "Field `dma_start` reader - DMA transfer enable (auto-clears)"] pub type DmaStartR = crate :: BitReader ;
#[doc = "Field `dma_start` writer - DMA transfer enable (auto-clears)"] pub type DmaStartW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dma_rw` reader - DMA direction: 0=write; 1=read"] pub type DmaRwR = crate :: BitReader ;
#[doc = "Field `dma_rw` writer - DMA direction: 0=write; 1=read"] pub type DmaRwW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dma_sel_cs` reader - DMA chip select: 0=CS0; 1=CS1"] pub type DmaSelCsR = crate :: BitReader ;
#[doc = "Field `dma_sel_cs` writer - DMA chip select: 0=CS0; 1=CS1"] pub type DmaSelCsW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - DMA transfer enable (auto-clears)"]
#[inline (always)] pub fn dma_start (& self) -> DmaStartR { DmaStartR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - DMA direction: 0=write; 1=read"]
#[inline (always)] pub fn dma_rw (& self) -> DmaRwR { DmaRwR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 4 - DMA chip select: 0=CS0; 1=CS1"]
#[inline (always)] pub fn dma_sel_cs (& self) -> DmaSelCsR { DmaSelCsR :: new (((self . bits >> 4) & 1) != 0) } } impl W {
#[doc = "Bit 0 - DMA transfer enable (auto-clears)"]
#[inline (always)] pub fn dma_start (& mut self) -> DmaStartW < '_ , BusDmaCtrlSpec > { DmaStartW :: new (self , 0) }
#[doc = "Bit 1 - DMA direction: 0=write; 1=read"]
#[inline (always)] pub fn dma_rw (& mut self) -> DmaRwW < '_ , BusDmaCtrlSpec > { DmaRwW :: new (self , 1) }
#[doc = "Bit 4 - DMA chip select: 0=CS0; 1=CS1"]
#[inline (always)] pub fn dma_sel_cs (& mut self) -> DmaSelCsW < '_ , BusDmaCtrlSpec > { DmaSelCsW :: new (self , 4) } }
#[doc = "DMA operation control register\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BusDmaCtrlSpec ; impl crate :: RegisterSpec for BusDmaCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`bus_dma_ctrl::R`](R) reader structure"] impl crate :: Readable for BusDmaCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`bus_dma_ctrl::W`](W) writer structure"] impl crate :: Writable for BusDmaCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets BUS_DMA_CTRL to value 0"] impl crate :: Resettable for BusDmaCtrlSpec { } }
#[doc = "BUS_DMA_MEM_SADDR (rw) register accessor: DMA memory start address\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_mem_saddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_mem_saddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_dma_mem_saddr`] module"]
#[doc (alias = "BUS_DMA_MEM_SADDR")] pub type BusDmaMemSaddr = crate :: Reg < bus_dma_mem_saddr :: BusDmaMemSaddrSpec > ;
#[doc = "DMA memory start address"] pub mod bus_dma_mem_saddr {
#[doc = "Register `BUS_DMA_MEM_SADDR` reader"] pub type R = crate :: R < BusDmaMemSaddrSpec > ;
#[doc = "Register `BUS_DMA_MEM_SADDR` writer"] pub type W = crate :: W < BusDmaMemSaddrSpec > ;
#[doc = "Field `dma_mem_saddr` reader - DMA memory start address (0x00100000~0x00BFFFFF)"] pub type DmaMemSaddrR = crate :: FieldReader < u32 > ;
#[doc = "Field `dma_mem_saddr` writer - DMA memory start address (0x00100000~0x00BFFFFF)"] pub type DmaMemSaddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - DMA memory start address (0x00100000~0x00BFFFFF)"]
#[inline (always)] pub fn dma_mem_saddr (& self) -> DmaMemSaddrR { DmaMemSaddrR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - DMA memory start address (0x00100000~0x00BFFFFF)"]
#[inline (always)] pub fn dma_mem_saddr (& mut self) -> DmaMemSaddrW < '_ , BusDmaMemSaddrSpec > { DmaMemSaddrW :: new (self , 0) } }
#[doc = "DMA memory start address\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_mem_saddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_mem_saddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BusDmaMemSaddrSpec ; impl crate :: RegisterSpec for BusDmaMemSaddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`bus_dma_mem_saddr::R`](R) reader structure"] impl crate :: Readable for BusDmaMemSaddrSpec { }
#[doc = "`write(|w| ..)` method takes [`bus_dma_mem_saddr::W`](W) writer structure"] impl crate :: Writable for BusDmaMemSaddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets BUS_DMA_MEM_SADDR to value 0"] impl crate :: Resettable for BusDmaMemSaddrSpec { } }
#[doc = "BUS_DMA_FLASH_SADDR (rw) register accessor: DMA Flash start address\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_flash_saddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_flash_saddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_dma_flash_saddr`] module"]
#[doc (alias = "BUS_DMA_FLASH_SADDR")] pub type BusDmaFlashSaddr = crate :: Reg < bus_dma_flash_saddr :: BusDmaFlashSaddrSpec > ;
#[doc = "DMA Flash start address"] pub mod bus_dma_flash_saddr {
#[doc = "Register `BUS_DMA_FLASH_SADDR` reader"] pub type R = crate :: R < BusDmaFlashSaddrSpec > ;
#[doc = "Register `BUS_DMA_FLASH_SADDR` writer"] pub type W = crate :: W < BusDmaFlashSaddrSpec > ;
#[doc = "Field `dma_flash_saddr` reader - DMA Flash start address"] pub type DmaFlashSaddrR = crate :: FieldReader < u32 > ;
#[doc = "Field `dma_flash_saddr` writer - DMA Flash start address"] pub type DmaFlashSaddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - DMA Flash start address"]
#[inline (always)] pub fn dma_flash_saddr (& self) -> DmaFlashSaddrR { DmaFlashSaddrR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - DMA Flash start address"]
#[inline (always)] pub fn dma_flash_saddr (& mut self) -> DmaFlashSaddrW < '_ , BusDmaFlashSaddrSpec > { DmaFlashSaddrW :: new (self , 0) } }
#[doc = "DMA Flash start address\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_flash_saddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_flash_saddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BusDmaFlashSaddrSpec ; impl crate :: RegisterSpec for BusDmaFlashSaddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`bus_dma_flash_saddr::R`](R) reader structure"] impl crate :: Readable for BusDmaFlashSaddrSpec { }
#[doc = "`write(|w| ..)` method takes [`bus_dma_flash_saddr::W`](W) writer structure"] impl crate :: Writable for BusDmaFlashSaddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets BUS_DMA_FLASH_SADDR to value 0"] impl crate :: Resettable for BusDmaFlashSaddrSpec { } }
#[doc = "BUS_DMA_LEN (rw) register accessor: DMA transfer length\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_dma_len`] module"]
#[doc (alias = "BUS_DMA_LEN")] pub type BusDmaLen = crate :: Reg < bus_dma_len :: BusDmaLenSpec > ;
#[doc = "DMA transfer length"] pub mod bus_dma_len {
#[doc = "Register `BUS_DMA_LEN` reader"] pub type R = crate :: R < BusDmaLenSpec > ;
#[doc = "Register `BUS_DMA_LEN` writer"] pub type W = crate :: W < BusDmaLenSpec > ;
#[doc = "Field `dma_len` reader - DMA length (n+1 bytes)"] pub type DmaLenR = crate :: FieldReader < u32 > ;
#[doc = "Field `dma_len` writer - DMA length (n+1 bytes)"] pub type DmaLenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R {
#[doc = "Bits 0:29 - DMA length (n+1 bytes)"]
#[inline (always)] pub fn dma_len (& self) -> DmaLenR { DmaLenR :: new (self . bits & 0x3fff_ffff) } } impl W {
#[doc = "Bits 0:29 - DMA length (n+1 bytes)"]
#[inline (always)] pub fn dma_len (& mut self) -> DmaLenW < '_ , BusDmaLenSpec > { DmaLenW :: new (self , 0) } }
#[doc = "DMA transfer length\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BusDmaLenSpec ; impl crate :: RegisterSpec for BusDmaLenSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`bus_dma_len::R`](R) reader structure"] impl crate :: Readable for BusDmaLenSpec { }
#[doc = "`write(|w| ..)` method takes [`bus_dma_len::W`](W) writer structure"] impl crate :: Writable for BusDmaLenSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets BUS_DMA_LEN to value 0"] impl crate :: Resettable for BusDmaLenSpec { } }
#[doc = "BUS_DMA_AHB_CTRL (rw) register accessor: DMA AHB burst control\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_ahb_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_ahb_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_dma_ahb_ctrl`] module"]
#[doc (alias = "BUS_DMA_AHB_CTRL")] pub type BusDmaAhbCtrl = crate :: Reg < bus_dma_ahb_ctrl :: BusDmaAhbCtrlSpec > ;
#[doc = "DMA AHB burst control"] pub mod bus_dma_ahb_ctrl {
#[doc = "Register `BUS_DMA_AHB_CTRL` reader"] pub type R = crate :: R < BusDmaAhbCtrlSpec > ;
#[doc = "Register `BUS_DMA_AHB_CTRL` writer"] pub type W = crate :: W < BusDmaAhbCtrlSpec > ;
#[doc = "Field `incr4_en` reader - INCR4 burst enable"] pub type Incr4EnR = crate :: BitReader ;
#[doc = "Field `incr4_en` writer - INCR4 burst enable"] pub type Incr4EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `incr8_en` reader - INCR8 burst enable"] pub type Incr8EnR = crate :: BitReader ;
#[doc = "Field `incr8_en` writer - INCR8 burst enable"] pub type Incr8EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `incr16_en` reader - INCR16 burst enable"] pub type Incr16EnR = crate :: BitReader ;
#[doc = "Field `incr16_en` writer - INCR16 burst enable"] pub type Incr16EnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - INCR4 burst enable"]
#[inline (always)] pub fn incr4_en (& self) -> Incr4EnR { Incr4EnR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - INCR8 burst enable"]
#[inline (always)] pub fn incr8_en (& self) -> Incr8EnR { Incr8EnR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - INCR16 burst enable"]
#[inline (always)] pub fn incr16_en (& self) -> Incr16EnR { Incr16EnR :: new (((self . bits >> 2) & 1) != 0) } } impl W {
#[doc = "Bit 0 - INCR4 burst enable"]
#[inline (always)] pub fn incr4_en (& mut self) -> Incr4EnW < '_ , BusDmaAhbCtrlSpec > { Incr4EnW :: new (self , 0) }
#[doc = "Bit 1 - INCR8 burst enable"]
#[inline (always)] pub fn incr8_en (& mut self) -> Incr8EnW < '_ , BusDmaAhbCtrlSpec > { Incr8EnW :: new (self , 1) }
#[doc = "Bit 2 - INCR16 burst enable"]
#[inline (always)] pub fn incr16_en (& mut self) -> Incr16EnW < '_ , BusDmaAhbCtrlSpec > { Incr16EnW :: new (self , 2) } }
#[doc = "DMA AHB burst control\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_dma_ahb_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_dma_ahb_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BusDmaAhbCtrlSpec ; impl crate :: RegisterSpec for BusDmaAhbCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`bus_dma_ahb_ctrl::R`](R) reader structure"] impl crate :: Readable for BusDmaAhbCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`bus_dma_ahb_ctrl::W`](W) writer structure"] impl crate :: Writable for BusDmaAhbCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets BUS_DMA_AHB_CTRL to value 0x07"] impl crate :: Resettable for BusDmaAhbCtrlSpec { const RESET_VALUE : u32 = 0x07 ; } }
#[doc = "CMD_CONFIG (rw) register accessor: Command operation config\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_config`] module"]
#[doc (alias = "CMD_CONFIG")] pub type CmdConfig = crate :: Reg < cmd_config :: CmdConfigSpec > ;
#[doc = "Command operation config"] pub mod cmd_config {
#[doc = "Register `CMD_CONFIG` reader"] pub type R = crate :: R < CmdConfigSpec > ;
#[doc = "Register `CMD_CONFIG` writer"] pub type W = crate :: W < CmdConfigSpec > ;
#[doc = "Field `start` reader - Command start (auto-clears)"] pub type StartR = crate :: BitReader ;
#[doc = "Field `start` writer - Command start (auto-clears)"] pub type StartW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `sel_cs` reader - Chip select: 0=CS0; 1=CS1"] pub type SelCsR = crate :: BitReader ;
#[doc = "Field `sel_cs` writer - Chip select: 0=CS0; 1=CS1"] pub type SelCsW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `addr_en` reader - Address present: 0=no; 1=yes"] pub type AddrEnR = crate :: BitReader ;
#[doc = "Field `addr_en` writer - Address present: 0=no; 1=yes"] pub type AddrEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dummy_byte_cnt` reader - Dummy bytes: 000=0; 001=1; etc."] pub type DummyByteCntR = crate :: FieldReader ;
#[doc = "Field `dummy_byte_cnt` writer - Dummy bytes: 000=0; 001=1; etc."] pub type DummyByteCntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `data_en` reader - Data present: 0=no; 1=yes"] pub type DataEnR = crate :: BitReader ;
#[doc = "Field `data_en` writer - Data present: 0=no; 1=yes"] pub type DataEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rw` reader - Data direction: 0=write; 1=read"] pub type RwR = crate :: BitReader ;
#[doc = "Field `rw` writer - Data direction: 0=write; 1=read"] pub type RwW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `data_cnt` reader - Data length (n+1 bytes)"] pub type DataCntR = crate :: FieldReader ;
#[doc = "Field `data_cnt` writer - Data length (n+1 bytes)"] pub type DataCntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ;
#[doc = "Field `mem_if_type` reader - SPI interface type: 000=Standard; 001=Dual; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"] pub type MemIfTypeR = crate :: FieldReader ;
#[doc = "Field `mem_if_type` writer - SPI interface type: 000=Standard; 001=Dual; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"] pub type MemIfTypeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bit 0 - Command start (auto-clears)"]
#[inline (always)] pub fn start (& self) -> StartR { StartR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Chip select: 0=CS0; 1=CS1"]
#[inline (always)] pub fn sel_cs (& self) -> SelCsR { SelCsR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 3 - Address present: 0=no; 1=yes"]
#[inline (always)] pub fn addr_en (& self) -> AddrEnR { AddrEnR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bits 4:6 - Dummy bytes: 000=0; 001=1; etc."]
#[inline (always)] pub fn dummy_byte_cnt (& self) -> DummyByteCntR { DummyByteCntR :: new (((self . bits >> 4) & 7) as u8) }
#[doc = "Bit 7 - Data present: 0=no; 1=yes"]
#[inline (always)] pub fn data_en (& self) -> DataEnR { DataEnR :: new (((self . bits >> 7) & 1) != 0) }
#[doc = "Bit 8 - Data direction: 0=write; 1=read"]
#[inline (always)] pub fn rw (& self) -> RwR { RwR :: new (((self . bits >> 8) & 1) != 0) }
#[doc = "Bits 9:14 - Data length (n+1 bytes)"]
#[inline (always)] pub fn data_cnt (& self) -> DataCntR { DataCntR :: new (((self . bits >> 9) & 0x3f) as u8) }
#[doc = "Bits 17:19 - SPI interface type: 000=Standard; 001=Dual; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
#[inline (always)] pub fn mem_if_type (& self) -> MemIfTypeR { MemIfTypeR :: new (((self . bits >> 17) & 7) as u8) } } impl W {
#[doc = "Bit 0 - Command start (auto-clears)"]
#[inline (always)] pub fn start (& mut self) -> StartW < '_ , CmdConfigSpec > { StartW :: new (self , 0) }
#[doc = "Bit 1 - Chip select: 0=CS0; 1=CS1"]
#[inline (always)] pub fn sel_cs (& mut self) -> SelCsW < '_ , CmdConfigSpec > { SelCsW :: new (self , 1) }
#[doc = "Bit 3 - Address present: 0=no; 1=yes"]
#[inline (always)] pub fn addr_en (& mut self) -> AddrEnW < '_ , CmdConfigSpec > { AddrEnW :: new (self , 3) }
#[doc = "Bits 4:6 - Dummy bytes: 000=0; 001=1; etc."]
#[inline (always)] pub fn dummy_byte_cnt (& mut self) -> DummyByteCntW < '_ , CmdConfigSpec > { DummyByteCntW :: new (self , 4) }
#[doc = "Bit 7 - Data present: 0=no; 1=yes"]
#[inline (always)] pub fn data_en (& mut self) -> DataEnW < '_ , CmdConfigSpec > { DataEnW :: new (self , 7) }
#[doc = "Bit 8 - Data direction: 0=write; 1=read"]
#[inline (always)] pub fn rw (& mut self) -> RwW < '_ , CmdConfigSpec > { RwW :: new (self , 8) }
#[doc = "Bits 9:14 - Data length (n+1 bytes)"]
#[inline (always)] pub fn data_cnt (& mut self) -> DataCntW < '_ , CmdConfigSpec > { DataCntW :: new (self , 9) }
#[doc = "Bits 17:19 - SPI interface type: 000=Standard; 001=Dual; 010=Dual-IO; 101=Quad-Input; 110=Quad-IO"]
#[inline (always)] pub fn mem_if_type (& mut self) -> MemIfTypeW < '_ , CmdConfigSpec > { MemIfTypeW :: new (self , 17) } }
#[doc = "Command operation config\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdConfigSpec ; impl crate :: RegisterSpec for CmdConfigSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_config::R`](R) reader structure"] impl crate :: Readable for CmdConfigSpec { }
#[doc = "`write(|w| ..)` method takes [`cmd_config::W`](W) writer structure"] impl crate :: Writable for CmdConfigSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_CONFIG to value 0x7e00"] impl crate :: Resettable for CmdConfigSpec { const RESET_VALUE : u32 = 0x7e00 ; } }
#[doc = "CMD_INS (rw) register accessor: Command instruction register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_ins::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_ins::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_ins`] module"]
#[doc (alias = "CMD_INS")] pub type CmdIns = crate :: Reg < cmd_ins :: CmdInsSpec > ;
#[doc = "Command instruction register"] pub mod cmd_ins {
#[doc = "Register `CMD_INS` reader"] pub type R = crate :: R < CmdInsSpec > ;
#[doc = "Register `CMD_INS` writer"] pub type W = crate :: W < CmdInsSpec > ;
#[doc = "Field `reg_ins` reader - Instruction code"] pub type RegInsR = crate :: FieldReader ;
#[doc = "Field `reg_ins` writer - Instruction code"] pub type RegInsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - Instruction code"]
#[inline (always)] pub fn reg_ins (& self) -> RegInsR { RegInsR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Instruction code"]
#[inline (always)] pub fn reg_ins (& mut self) -> RegInsW < '_ , CmdInsSpec > { RegInsW :: new (self , 0) } }
#[doc = "Command instruction register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_ins::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_ins::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdInsSpec ; impl crate :: RegisterSpec for CmdInsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_ins::R`](R) reader structure"] impl crate :: Readable for CmdInsSpec { }
#[doc = "`write(|w| ..)` method takes [`cmd_ins::W`](W) writer structure"] impl crate :: Writable for CmdInsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_INS to value 0"] impl crate :: Resettable for CmdInsSpec { } }
#[doc = "CMD_ADDR (rw) register accessor: Command address register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_addr`] module"]
#[doc (alias = "CMD_ADDR")] pub type CmdAddr = crate :: Reg < cmd_addr :: CmdAddrSpec > ;
#[doc = "Command address register"] pub mod cmd_addr {
#[doc = "Register `CMD_ADDR` reader"] pub type R = crate :: R < CmdAddrSpec > ;
#[doc = "Register `CMD_ADDR` writer"] pub type W = crate :: W < CmdAddrSpec > ;
#[doc = "Field `cmd_addr` reader - Operation address"] pub type CmdAddrR = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_addr` writer - Operation address"] pub type CmdAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 30 , u32 > ; impl R {
#[doc = "Bits 0:29 - Operation address"]
#[inline (always)] pub fn cmd_addr (& self) -> CmdAddrR { CmdAddrR :: new (self . bits & 0x3fff_ffff) } } impl W {
#[doc = "Bits 0:29 - Operation address"]
#[inline (always)] pub fn cmd_addr (& mut self) -> CmdAddrW < '_ , CmdAddrSpec > { CmdAddrW :: new (self , 0) } }
#[doc = "Command address register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdAddrSpec ; impl crate :: RegisterSpec for CmdAddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_addr::R`](R) reader structure"] impl crate :: Readable for CmdAddrSpec { }
#[doc = "`write(|w| ..)` method takes [`cmd_addr::W`](W) writer structure"] impl crate :: Writable for CmdAddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_ADDR to value 0"] impl crate :: Resettable for CmdAddrSpec { } }
#[doc = "CMD_DATABUF_0 (rw) register accessor: Command data buffer 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_0`] module"]
#[doc (alias = "CMD_DATABUF_0")] pub type CmdDatabuf0 = crate :: Reg < cmd_databuf_0 :: CmdDatabuf0Spec > ;
#[doc = "Command data buffer 0"] pub mod cmd_databuf_0 {
#[doc = "Register `CMD_DATABUF_0` reader"] pub type R = crate :: R < CmdDatabuf0Spec > ;
#[doc = "Register `CMD_DATABUF_0` writer"] pub type W = crate :: W < CmdDatabuf0Spec > ;
#[doc = "Field `cmd_databuf_0` reader - Data buffer 0"] pub type CmdDatabuf0R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_0` writer - Data buffer 0"] pub type CmdDatabuf0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Data buffer 0"]
#[inline (always)] pub fn cmd_databuf_0 (& self) -> CmdDatabuf0R { CmdDatabuf0R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Data buffer 0"]
#[inline (always)] pub fn cmd_databuf_0 (& mut self) -> CmdDatabuf0W < '_ , CmdDatabuf0Spec > { CmdDatabuf0W :: new (self , 0) } }
#[doc = "Command data buffer 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf0Spec ; impl crate :: RegisterSpec for CmdDatabuf0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_0::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf0Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_0::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_0 to value 0"] impl crate :: Resettable for CmdDatabuf0Spec { } }
#[doc = "LEA_LP_EN (rw) register accessor: LEA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_lp_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_lp_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lea_lp_en`] module"]
#[doc (alias = "LEA_LP_EN")] pub type LeaLpEn = crate :: Reg < lea_lp_en :: LeaLpEnSpec > ;
#[doc = "LEA control register"] pub mod lea_lp_en {
#[doc = "Register `LEA_LP_EN` reader"] pub type R = crate :: R < LeaLpEnSpec > ;
#[doc = "Register `LEA_LP_EN` writer"] pub type W = crate :: W < LeaLpEnSpec > ;
#[doc = "Field `lea_lp_en` reader - AES low power: 0=disabled; 1=enabled"] pub type LeaLpEnR = crate :: BitReader ;
#[doc = "Field `lea_lp_en` writer - AES low power: 0=disabled; 1=enabled"] pub type LeaLpEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - AES low power: 0=disabled; 1=enabled"]
#[inline (always)] pub fn lea_lp_en (& self) -> LeaLpEnR { LeaLpEnR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - AES low power: 0=disabled; 1=enabled"]
#[inline (always)] pub fn lea_lp_en (& mut self) -> LeaLpEnW < '_ , LeaLpEnSpec > { LeaLpEnW :: new (self , 0) } }
#[doc = "LEA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_lp_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_lp_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LeaLpEnSpec ; impl crate :: RegisterSpec for LeaLpEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lea_lp_en::R`](R) reader structure"] impl crate :: Readable for LeaLpEnSpec { }
#[doc = "`write(|w| ..)` method takes [`lea_lp_en::W`](W) writer structure"] impl crate :: Writable for LeaLpEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LEA_LP_EN to value 0x01"] impl crate :: Resettable for LeaLpEnSpec { const RESET_VALUE : u32 = 0x01 ; } }
#[doc = "LEA_DFX_INFO (rw) register accessor: LEA DFX register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_dfx_info::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_dfx_info::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lea_dfx_info`] module"]
#[doc (alias = "LEA_DFX_INFO")] pub type LeaDfxInfo = crate :: Reg < lea_dfx_info :: LeaDfxInfoSpec > ;
#[doc = "LEA DFX register"] pub mod lea_dfx_info {
#[doc = "Register `LEA_DFX_INFO` reader"] pub type R = crate :: R < LeaDfxInfoSpec > ;
#[doc = "Register `LEA_DFX_INFO` writer"] pub type W = crate :: W < LeaDfxInfoSpec > ;
#[doc = "Field `lea_dfx_info` reader - AES DFX observation"] pub type LeaDfxInfoR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - AES DFX observation"]
#[inline (always)] pub fn lea_dfx_info (& self) -> LeaDfxInfoR { LeaDfxInfoR :: new (self . bits) } } impl W { }
#[doc = "LEA DFX register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_dfx_info::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_dfx_info::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LeaDfxInfoSpec ; impl crate :: RegisterSpec for LeaDfxInfoSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lea_dfx_info::R`](R) reader structure"] impl crate :: Readable for LeaDfxInfoSpec { }
#[doc = "`write(|w| ..)` method takes [`lea_dfx_info::W`](W) writer structure"] impl crate :: Writable for LeaDfxInfoSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LEA_DFX_INFO to value 0"] impl crate :: Resettable for LeaDfxInfoSpec { } }
#[doc = "LEA_IV_VLD (rw) register accessor: LEA IV valid register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_iv_vld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_iv_vld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lea_iv_vld`] module"]
#[doc (alias = "LEA_IV_VLD")] pub type LeaIvVld = crate :: Reg < lea_iv_vld :: LeaIvVldSpec > ;
#[doc = "LEA IV valid register"] pub mod lea_iv_vld {
#[doc = "Register `LEA_IV_VLD` reader"] pub type R = crate :: R < LeaIvVldSpec > ;
#[doc = "Register `LEA_IV_VLD` writer"] pub type W = crate :: W < LeaIvVldSpec > ;
#[doc = "Field `lea_iv_vld` reader - AES IV value valid (auto-clears after sync)"] pub type LeaIvVldR = crate :: BitReader ;
#[doc = "Field `lea_iv_vld` writer - AES IV value valid (auto-clears after sync)"] pub type LeaIvVldW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - AES IV value valid (auto-clears after sync)"]
#[inline (always)] pub fn lea_iv_vld (& self) -> LeaIvVldR { LeaIvVldR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - AES IV value valid (auto-clears after sync)"]
#[inline (always)] pub fn lea_iv_vld (& mut self) -> LeaIvVldW < '_ , LeaIvVldSpec > { LeaIvVldW :: new (self , 0) } }
#[doc = "LEA IV valid register\n\nYou can [`read`](crate::Reg::read) this register and get [`lea_iv_vld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lea_iv_vld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LeaIvVldSpec ; impl crate :: RegisterSpec for LeaIvVldSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lea_iv_vld::R`](R) reader structure"] impl crate :: Readable for LeaIvVldSpec { }
#[doc = "`write(|w| ..)` method takes [`lea_iv_vld::W`](W) writer structure"] impl crate :: Writable for LeaIvVldSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LEA_IV_VLD to value 0"] impl crate :: Resettable for LeaIvVldSpec { } }
#[doc = "CMD_DATABUF_1 (rw) register accessor: Command data buffer 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_1`] module"]
#[doc (alias = "CMD_DATABUF_1")] pub type CmdDatabuf1 = crate :: Reg < cmd_databuf_1 :: CmdDatabuf1Spec > ;
#[doc = "Command data buffer 1"] pub mod cmd_databuf_1 {
#[doc = "Register `CMD_DATABUF_1` reader"] pub type R = crate :: R < CmdDatabuf1Spec > ;
#[doc = "Register `CMD_DATABUF_1` writer"] pub type W = crate :: W < CmdDatabuf1Spec > ;
#[doc = "Field `cmd_databuf_1` reader - Command data buffer 1"] pub type CmdDatabuf1R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_1` writer - Command data buffer 1"] pub type CmdDatabuf1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 1"]
#[inline (always)] pub fn cmd_databuf_1 (& self) -> CmdDatabuf1R { CmdDatabuf1R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 1"]
#[inline (always)] pub fn cmd_databuf_1 (& mut self) -> CmdDatabuf1W < '_ , CmdDatabuf1Spec > { CmdDatabuf1W :: new (self , 0) } }
#[doc = "Command data buffer 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf1Spec ; impl crate :: RegisterSpec for CmdDatabuf1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_1::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf1Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_1::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_1 to value 0"] impl crate :: Resettable for CmdDatabuf1Spec { } }
#[doc = "CMD_DATABUF_2 (rw) register accessor: Command data buffer 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_2`] module"]
#[doc (alias = "CMD_DATABUF_2")] pub type CmdDatabuf2 = crate :: Reg < cmd_databuf_2 :: CmdDatabuf2Spec > ;
#[doc = "Command data buffer 2"] pub mod cmd_databuf_2 {
#[doc = "Register `CMD_DATABUF_2` reader"] pub type R = crate :: R < CmdDatabuf2Spec > ;
#[doc = "Register `CMD_DATABUF_2` writer"] pub type W = crate :: W < CmdDatabuf2Spec > ;
#[doc = "Field `cmd_databuf_2` reader - Command data buffer 2"] pub type CmdDatabuf2R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_2` writer - Command data buffer 2"] pub type CmdDatabuf2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 2"]
#[inline (always)] pub fn cmd_databuf_2 (& self) -> CmdDatabuf2R { CmdDatabuf2R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 2"]
#[inline (always)] pub fn cmd_databuf_2 (& mut self) -> CmdDatabuf2W < '_ , CmdDatabuf2Spec > { CmdDatabuf2W :: new (self , 0) } }
#[doc = "Command data buffer 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf2Spec ; impl crate :: RegisterSpec for CmdDatabuf2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_2::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf2Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_2::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_2 to value 0"] impl crate :: Resettable for CmdDatabuf2Spec { } }
#[doc = "CMD_DATABUF_3 (rw) register accessor: Command data buffer 3\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_3`] module"]
#[doc (alias = "CMD_DATABUF_3")] pub type CmdDatabuf3 = crate :: Reg < cmd_databuf_3 :: CmdDatabuf3Spec > ;
#[doc = "Command data buffer 3"] pub mod cmd_databuf_3 {
#[doc = "Register `CMD_DATABUF_3` reader"] pub type R = crate :: R < CmdDatabuf3Spec > ;
#[doc = "Register `CMD_DATABUF_3` writer"] pub type W = crate :: W < CmdDatabuf3Spec > ;
#[doc = "Field `cmd_databuf_3` reader - Command data buffer 3"] pub type CmdDatabuf3R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_3` writer - Command data buffer 3"] pub type CmdDatabuf3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 3"]
#[inline (always)] pub fn cmd_databuf_3 (& self) -> CmdDatabuf3R { CmdDatabuf3R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 3"]
#[inline (always)] pub fn cmd_databuf_3 (& mut self) -> CmdDatabuf3W < '_ , CmdDatabuf3Spec > { CmdDatabuf3W :: new (self , 0) } }
#[doc = "Command data buffer 3\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf3Spec ; impl crate :: RegisterSpec for CmdDatabuf3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_3::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf3Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_3::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_3 to value 0"] impl crate :: Resettable for CmdDatabuf3Spec { } }
#[doc = "CMD_DATABUF_4 (rw) register accessor: Command data buffer 4\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_4`] module"]
#[doc (alias = "CMD_DATABUF_4")] pub type CmdDatabuf4 = crate :: Reg < cmd_databuf_4 :: CmdDatabuf4Spec > ;
#[doc = "Command data buffer 4"] pub mod cmd_databuf_4 {
#[doc = "Register `CMD_DATABUF_4` reader"] pub type R = crate :: R < CmdDatabuf4Spec > ;
#[doc = "Register `CMD_DATABUF_4` writer"] pub type W = crate :: W < CmdDatabuf4Spec > ;
#[doc = "Field `cmd_databuf_4` reader - Command data buffer 4"] pub type CmdDatabuf4R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_4` writer - Command data buffer 4"] pub type CmdDatabuf4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 4"]
#[inline (always)] pub fn cmd_databuf_4 (& self) -> CmdDatabuf4R { CmdDatabuf4R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 4"]
#[inline (always)] pub fn cmd_databuf_4 (& mut self) -> CmdDatabuf4W < '_ , CmdDatabuf4Spec > { CmdDatabuf4W :: new (self , 0) } }
#[doc = "Command data buffer 4\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf4Spec ; impl crate :: RegisterSpec for CmdDatabuf4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_4::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf4Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_4::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_4 to value 0"] impl crate :: Resettable for CmdDatabuf4Spec { } }
#[doc = "CMD_DATABUF_5 (rw) register accessor: Command data buffer 5\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_5`] module"]
#[doc (alias = "CMD_DATABUF_5")] pub type CmdDatabuf5 = crate :: Reg < cmd_databuf_5 :: CmdDatabuf5Spec > ;
#[doc = "Command data buffer 5"] pub mod cmd_databuf_5 {
#[doc = "Register `CMD_DATABUF_5` reader"] pub type R = crate :: R < CmdDatabuf5Spec > ;
#[doc = "Register `CMD_DATABUF_5` writer"] pub type W = crate :: W < CmdDatabuf5Spec > ;
#[doc = "Field `cmd_databuf_5` reader - Command data buffer 5"] pub type CmdDatabuf5R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_5` writer - Command data buffer 5"] pub type CmdDatabuf5W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 5"]
#[inline (always)] pub fn cmd_databuf_5 (& self) -> CmdDatabuf5R { CmdDatabuf5R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 5"]
#[inline (always)] pub fn cmd_databuf_5 (& mut self) -> CmdDatabuf5W < '_ , CmdDatabuf5Spec > { CmdDatabuf5W :: new (self , 0) } }
#[doc = "Command data buffer 5\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf5Spec ; impl crate :: RegisterSpec for CmdDatabuf5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_5::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf5Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_5::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_5 to value 0"] impl crate :: Resettable for CmdDatabuf5Spec { } }
#[doc = "CMD_DATABUF_6 (rw) register accessor: Command data buffer 6\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_6`] module"]
#[doc (alias = "CMD_DATABUF_6")] pub type CmdDatabuf6 = crate :: Reg < cmd_databuf_6 :: CmdDatabuf6Spec > ;
#[doc = "Command data buffer 6"] pub mod cmd_databuf_6 {
#[doc = "Register `CMD_DATABUF_6` reader"] pub type R = crate :: R < CmdDatabuf6Spec > ;
#[doc = "Register `CMD_DATABUF_6` writer"] pub type W = crate :: W < CmdDatabuf6Spec > ;
#[doc = "Field `cmd_databuf_6` reader - Command data buffer 6"] pub type CmdDatabuf6R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_6` writer - Command data buffer 6"] pub type CmdDatabuf6W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 6"]
#[inline (always)] pub fn cmd_databuf_6 (& self) -> CmdDatabuf6R { CmdDatabuf6R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 6"]
#[inline (always)] pub fn cmd_databuf_6 (& mut self) -> CmdDatabuf6W < '_ , CmdDatabuf6Spec > { CmdDatabuf6W :: new (self , 0) } }
#[doc = "Command data buffer 6\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf6Spec ; impl crate :: RegisterSpec for CmdDatabuf6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_6::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf6Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_6::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_6 to value 0"] impl crate :: Resettable for CmdDatabuf6Spec { } }
#[doc = "CMD_DATABUF_7 (rw) register accessor: Command data buffer 7\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_7`] module"]
#[doc (alias = "CMD_DATABUF_7")] pub type CmdDatabuf7 = crate :: Reg < cmd_databuf_7 :: CmdDatabuf7Spec > ;
#[doc = "Command data buffer 7"] pub mod cmd_databuf_7 {
#[doc = "Register `CMD_DATABUF_7` reader"] pub type R = crate :: R < CmdDatabuf7Spec > ;
#[doc = "Register `CMD_DATABUF_7` writer"] pub type W = crate :: W < CmdDatabuf7Spec > ;
#[doc = "Field `cmd_databuf_7` reader - Command data buffer 7"] pub type CmdDatabuf7R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_7` writer - Command data buffer 7"] pub type CmdDatabuf7W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 7"]
#[inline (always)] pub fn cmd_databuf_7 (& self) -> CmdDatabuf7R { CmdDatabuf7R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 7"]
#[inline (always)] pub fn cmd_databuf_7 (& mut self) -> CmdDatabuf7W < '_ , CmdDatabuf7Spec > { CmdDatabuf7W :: new (self , 0) } }
#[doc = "Command data buffer 7\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf7Spec ; impl crate :: RegisterSpec for CmdDatabuf7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_7::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf7Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_7::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_7 to value 0"] impl crate :: Resettable for CmdDatabuf7Spec { } }
#[doc = "CMD_DATABUF_8 (rw) register accessor: Command data buffer 8\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_8`] module"]
#[doc (alias = "CMD_DATABUF_8")] pub type CmdDatabuf8 = crate :: Reg < cmd_databuf_8 :: CmdDatabuf8Spec > ;
#[doc = "Command data buffer 8"] pub mod cmd_databuf_8 {
#[doc = "Register `CMD_DATABUF_8` reader"] pub type R = crate :: R < CmdDatabuf8Spec > ;
#[doc = "Register `CMD_DATABUF_8` writer"] pub type W = crate :: W < CmdDatabuf8Spec > ;
#[doc = "Field `cmd_databuf_8` reader - Command data buffer 8"] pub type CmdDatabuf8R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_8` writer - Command data buffer 8"] pub type CmdDatabuf8W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 8"]
#[inline (always)] pub fn cmd_databuf_8 (& self) -> CmdDatabuf8R { CmdDatabuf8R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 8"]
#[inline (always)] pub fn cmd_databuf_8 (& mut self) -> CmdDatabuf8W < '_ , CmdDatabuf8Spec > { CmdDatabuf8W :: new (self , 0) } }
#[doc = "Command data buffer 8\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf8Spec ; impl crate :: RegisterSpec for CmdDatabuf8Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_8::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf8Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_8::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf8Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_8 to value 0"] impl crate :: Resettable for CmdDatabuf8Spec { } }
#[doc = "CMD_DATABUF_9 (rw) register accessor: Command data buffer 9\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_9`] module"]
#[doc (alias = "CMD_DATABUF_9")] pub type CmdDatabuf9 = crate :: Reg < cmd_databuf_9 :: CmdDatabuf9Spec > ;
#[doc = "Command data buffer 9"] pub mod cmd_databuf_9 {
#[doc = "Register `CMD_DATABUF_9` reader"] pub type R = crate :: R < CmdDatabuf9Spec > ;
#[doc = "Register `CMD_DATABUF_9` writer"] pub type W = crate :: W < CmdDatabuf9Spec > ;
#[doc = "Field `cmd_databuf_9` reader - Command data buffer 9"] pub type CmdDatabuf9R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_9` writer - Command data buffer 9"] pub type CmdDatabuf9W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 9"]
#[inline (always)] pub fn cmd_databuf_9 (& self) -> CmdDatabuf9R { CmdDatabuf9R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 9"]
#[inline (always)] pub fn cmd_databuf_9 (& mut self) -> CmdDatabuf9W < '_ , CmdDatabuf9Spec > { CmdDatabuf9W :: new (self , 0) } }
#[doc = "Command data buffer 9\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf9Spec ; impl crate :: RegisterSpec for CmdDatabuf9Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_9::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf9Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_9::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf9Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_9 to value 0"] impl crate :: Resettable for CmdDatabuf9Spec { } }
#[doc = "CMD_DATABUF_10 (rw) register accessor: Command data buffer 10\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_10`] module"]
#[doc (alias = "CMD_DATABUF_10")] pub type CmdDatabuf10 = crate :: Reg < cmd_databuf_10 :: CmdDatabuf10Spec > ;
#[doc = "Command data buffer 10"] pub mod cmd_databuf_10 {
#[doc = "Register `CMD_DATABUF_10` reader"] pub type R = crate :: R < CmdDatabuf10Spec > ;
#[doc = "Register `CMD_DATABUF_10` writer"] pub type W = crate :: W < CmdDatabuf10Spec > ;
#[doc = "Field `cmd_databuf_10` reader - Command data buffer 10"] pub type CmdDatabuf10R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_10` writer - Command data buffer 10"] pub type CmdDatabuf10W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 10"]
#[inline (always)] pub fn cmd_databuf_10 (& self) -> CmdDatabuf10R { CmdDatabuf10R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 10"]
#[inline (always)] pub fn cmd_databuf_10 (& mut self) -> CmdDatabuf10W < '_ , CmdDatabuf10Spec > { CmdDatabuf10W :: new (self , 0) } }
#[doc = "Command data buffer 10\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf10Spec ; impl crate :: RegisterSpec for CmdDatabuf10Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_10::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf10Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_10::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf10Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_10 to value 0"] impl crate :: Resettable for CmdDatabuf10Spec { } }
#[doc = "CMD_DATABUF_11 (rw) register accessor: Command data buffer 11\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_11`] module"]
#[doc (alias = "CMD_DATABUF_11")] pub type CmdDatabuf11 = crate :: Reg < cmd_databuf_11 :: CmdDatabuf11Spec > ;
#[doc = "Command data buffer 11"] pub mod cmd_databuf_11 {
#[doc = "Register `CMD_DATABUF_11` reader"] pub type R = crate :: R < CmdDatabuf11Spec > ;
#[doc = "Register `CMD_DATABUF_11` writer"] pub type W = crate :: W < CmdDatabuf11Spec > ;
#[doc = "Field `cmd_databuf_11` reader - Command data buffer 11"] pub type CmdDatabuf11R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_11` writer - Command data buffer 11"] pub type CmdDatabuf11W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 11"]
#[inline (always)] pub fn cmd_databuf_11 (& self) -> CmdDatabuf11R { CmdDatabuf11R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 11"]
#[inline (always)] pub fn cmd_databuf_11 (& mut self) -> CmdDatabuf11W < '_ , CmdDatabuf11Spec > { CmdDatabuf11W :: new (self , 0) } }
#[doc = "Command data buffer 11\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf11Spec ; impl crate :: RegisterSpec for CmdDatabuf11Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_11::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf11Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_11::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf11Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_11 to value 0"] impl crate :: Resettable for CmdDatabuf11Spec { } }
#[doc = "CMD_DATABUF_12 (rw) register accessor: Command data buffer 12\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_12`] module"]
#[doc (alias = "CMD_DATABUF_12")] pub type CmdDatabuf12 = crate :: Reg < cmd_databuf_12 :: CmdDatabuf12Spec > ;
#[doc = "Command data buffer 12"] pub mod cmd_databuf_12 {
#[doc = "Register `CMD_DATABUF_12` reader"] pub type R = crate :: R < CmdDatabuf12Spec > ;
#[doc = "Register `CMD_DATABUF_12` writer"] pub type W = crate :: W < CmdDatabuf12Spec > ;
#[doc = "Field `cmd_databuf_12` reader - Command data buffer 12"] pub type CmdDatabuf12R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_12` writer - Command data buffer 12"] pub type CmdDatabuf12W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 12"]
#[inline (always)] pub fn cmd_databuf_12 (& self) -> CmdDatabuf12R { CmdDatabuf12R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 12"]
#[inline (always)] pub fn cmd_databuf_12 (& mut self) -> CmdDatabuf12W < '_ , CmdDatabuf12Spec > { CmdDatabuf12W :: new (self , 0) } }
#[doc = "Command data buffer 12\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf12Spec ; impl crate :: RegisterSpec for CmdDatabuf12Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_12::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf12Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_12::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf12Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_12 to value 0"] impl crate :: Resettable for CmdDatabuf12Spec { } }
#[doc = "CMD_DATABUF_13 (rw) register accessor: Command data buffer 13\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_13`] module"]
#[doc (alias = "CMD_DATABUF_13")] pub type CmdDatabuf13 = crate :: Reg < cmd_databuf_13 :: CmdDatabuf13Spec > ;
#[doc = "Command data buffer 13"] pub mod cmd_databuf_13 {
#[doc = "Register `CMD_DATABUF_13` reader"] pub type R = crate :: R < CmdDatabuf13Spec > ;
#[doc = "Register `CMD_DATABUF_13` writer"] pub type W = crate :: W < CmdDatabuf13Spec > ;
#[doc = "Field `cmd_databuf_13` reader - Command data buffer 13"] pub type CmdDatabuf13R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_13` writer - Command data buffer 13"] pub type CmdDatabuf13W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 13"]
#[inline (always)] pub fn cmd_databuf_13 (& self) -> CmdDatabuf13R { CmdDatabuf13R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 13"]
#[inline (always)] pub fn cmd_databuf_13 (& mut self) -> CmdDatabuf13W < '_ , CmdDatabuf13Spec > { CmdDatabuf13W :: new (self , 0) } }
#[doc = "Command data buffer 13\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf13Spec ; impl crate :: RegisterSpec for CmdDatabuf13Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_13::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf13Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_13::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf13Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_13 to value 0"] impl crate :: Resettable for CmdDatabuf13Spec { } }
#[doc = "CMD_DATABUF_14 (rw) register accessor: Command data buffer 14\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_14`] module"]
#[doc (alias = "CMD_DATABUF_14")] pub type CmdDatabuf14 = crate :: Reg < cmd_databuf_14 :: CmdDatabuf14Spec > ;
#[doc = "Command data buffer 14"] pub mod cmd_databuf_14 {
#[doc = "Register `CMD_DATABUF_14` reader"] pub type R = crate :: R < CmdDatabuf14Spec > ;
#[doc = "Register `CMD_DATABUF_14` writer"] pub type W = crate :: W < CmdDatabuf14Spec > ;
#[doc = "Field `cmd_databuf_14` reader - Command data buffer 14"] pub type CmdDatabuf14R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_14` writer - Command data buffer 14"] pub type CmdDatabuf14W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 14"]
#[inline (always)] pub fn cmd_databuf_14 (& self) -> CmdDatabuf14R { CmdDatabuf14R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 14"]
#[inline (always)] pub fn cmd_databuf_14 (& mut self) -> CmdDatabuf14W < '_ , CmdDatabuf14Spec > { CmdDatabuf14W :: new (self , 0) } }
#[doc = "Command data buffer 14\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf14Spec ; impl crate :: RegisterSpec for CmdDatabuf14Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_14::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf14Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_14::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf14Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_14 to value 0"] impl crate :: Resettable for CmdDatabuf14Spec { } }
#[doc = "CMD_DATABUF_15 (rw) register accessor: Command data buffer 15\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_databuf_15`] module"]
#[doc (alias = "CMD_DATABUF_15")] pub type CmdDatabuf15 = crate :: Reg < cmd_databuf_15 :: CmdDatabuf15Spec > ;
#[doc = "Command data buffer 15"] pub mod cmd_databuf_15 {
#[doc = "Register `CMD_DATABUF_15` reader"] pub type R = crate :: R < CmdDatabuf15Spec > ;
#[doc = "Register `CMD_DATABUF_15` writer"] pub type W = crate :: W < CmdDatabuf15Spec > ;
#[doc = "Field `cmd_databuf_15` reader - Command data buffer 15"] pub type CmdDatabuf15R = crate :: FieldReader < u32 > ;
#[doc = "Field `cmd_databuf_15` writer - Command data buffer 15"] pub type CmdDatabuf15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Command data buffer 15"]
#[inline (always)] pub fn cmd_databuf_15 (& self) -> CmdDatabuf15R { CmdDatabuf15R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Command data buffer 15"]
#[inline (always)] pub fn cmd_databuf_15 (& mut self) -> CmdDatabuf15W < '_ , CmdDatabuf15Spec > { CmdDatabuf15W :: new (self , 0) } }
#[doc = "Command data buffer 15\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd_databuf_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd_databuf_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CmdDatabuf15Spec ; impl crate :: RegisterSpec for CmdDatabuf15Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cmd_databuf_15::R`](R) reader structure"] impl crate :: Readable for CmdDatabuf15Spec { }
#[doc = "`write(|w| ..)` method takes [`cmd_databuf_15::W`](W) writer structure"] impl crate :: Writable for CmdDatabuf15Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CMD_DATABUF_15 to value 0"] impl crate :: Resettable for CmdDatabuf15Spec { } } }
#[doc = "SPI0 master/slave controller (SSI v151)"] pub type Spi0 = crate :: Periph < spi0 :: RegisterBlock , 0x4402_0000 > ; impl core :: fmt :: Debug for Spi0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Spi0") . finish () } }
#[doc = "SPI0 master/slave controller (SSI v151)"] pub mod spi0 {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { spi_er : SpiEr , spi_ctra : SpiCtra , spi_ctrb : SpiCtrb , spi_enhctl : SpiEnhctl , _reserved4 : [u8 ; 0x04] , spi_brs : SpiBrs , spi_dcr : SpiDcr , spi_drdl : SpiDrdl , spi_dtdl : SpiDtdl , _reserved8 : [u8 ; 0x3c] , spi_dr : SpiDr , _reserved9 : [u8 ; 0x58] , spi_rainsr : SpiRainsr , spi_insr : SpiInsr , spi_inmar : SpiInmar , spi_slenr : SpiSlenr , spi_twlr : SpiTwlr , spi_tlr : SpiTlr , _reserved15 : [u8 ; 0x04] , spi_rwlr : SpiRwlr , spi_rlr : SpiRlr , _reserved17 : [u8 ; 0x04] , spi_wsr : SpiWsr , _reserved18 : [u8 ; 0x10] , spi_icr : SpiIcr , } impl RegisterBlock {
#[doc = "0x00 - SPI enable register"]
#[inline (always)] pub const fn spi_er (& self) -> & SpiEr { & self . spi_er }
#[doc = "0x04 - SPI control register 0"]
#[inline (always)] pub const fn spi_ctra (& self) -> & SpiCtra { & self . spi_ctra }
#[doc = "0x08 - SPI control register 1 (master only)"]
#[inline (always)] pub const fn spi_ctrb (& self) -> & SpiCtrb { & self . spi_ctrb }
#[doc = "0x0c - Enhanced control register (Dual/Quad/Octal)"]
#[inline (always)] pub const fn spi_enhctl (& self) -> & SpiEnhctl { & self . spi_enhctl }
#[doc = "0x14 - Baud rate select register"]
#[inline (always)] pub const fn spi_brs (& self) -> & SpiBrs { & self . spi_brs }
#[doc = "0x18 - DMA control register"]
#[inline (always)] pub const fn spi_dcr (& self) -> & SpiDcr { & self . spi_dcr }
#[doc = "0x1c - DMA RX data level"]
#[inline (always)] pub const fn spi_drdl (& self) -> & SpiDrdl { & self . spi_drdl }
#[doc = "0x20 - DMA TX data level"]
#[inline (always)] pub const fn spi_dtdl (& self) -> & SpiDtdl { & self . spi_dtdl }
#[doc = "0x60 - Data register (FIFO read/write)"]
#[inline (always)] pub const fn spi_dr (& self) -> & SpiDr { & self . spi_dr }
#[doc = "0xbc - Raw interrupt status register"]
#[inline (always)] pub const fn spi_rainsr (& self) -> & SpiRainsr { & self . spi_rainsr }
#[doc = "0xc0 - Interrupt status register (masked)"]
#[inline (always)] pub const fn spi_insr (& self) -> & SpiInsr { & self . spi_insr }
#[doc = "0xc4 - Interrupt mask register"]
#[inline (always)] pub const fn spi_inmar (& self) -> & SpiInmar { & self . spi_inmar }
#[doc = "0xc8 - Slave enable register (master only)"]
#[inline (always)] pub const fn spi_slenr (& self) -> & SpiSlenr { & self . spi_slenr }
#[doc = "0xcc - TX FIFO threshold level"]
#[inline (always)] pub const fn spi_twlr (& self) -> & SpiTwlr { & self . spi_twlr }
#[doc = "0xd0 - TX FIFO level register"]
#[inline (always)] pub const fn spi_tlr (& self) -> & SpiTlr { & self . spi_tlr }
#[doc = "0xd8 - RX FIFO threshold level"]
#[inline (always)] pub const fn spi_rwlr (& self) -> & SpiRwlr { & self . spi_rwlr }
#[doc = "0xdc - RX FIFO level register"]
#[inline (always)] pub const fn spi_rlr (& self) -> & SpiRlr { & self . spi_rlr }
#[doc = "0xe4 - Status register"]
#[inline (always)] pub const fn spi_wsr (& self) -> & SpiWsr { & self . spi_wsr }
#[doc = "0xf8 - Interrupt clear register"]
#[inline (always)] pub const fn spi_icr (& self) -> & SpiIcr { & self . spi_icr } }
#[doc = "SPI_ER (rw) register accessor: SPI enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_er::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_er::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_er`] module"]
#[doc (alias = "SPI_ER")] pub type SpiEr = crate :: Reg < spi_er :: SpiErSpec > ;
#[doc = "SPI enable register"] pub mod spi_er {
#[doc = "Register `SPI_ER` reader"] pub type R = crate :: R < SpiErSpec > ;
#[doc = "Register `SPI_ER` writer"] pub type W = crate :: W < SpiErSpec > ;
#[doc = "Field `spi_en` reader - SPI enable: 0=disabled; 1=enabled"] pub type SpiEnR = crate :: BitReader ;
#[doc = "Field `spi_en` writer - SPI enable: 0=disabled; 1=enabled"] pub type SpiEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - SPI enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn spi_en (& self) -> SpiEnR { SpiEnR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - SPI enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn spi_en (& mut self) -> SpiEnW < '_ , SpiErSpec > { SpiEnW :: new (self , 0) } }
#[doc = "SPI enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_er::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_er::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiErSpec ; impl crate :: RegisterSpec for SpiErSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_er::R`](R) reader structure"] impl crate :: Readable for SpiErSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_er::W`](W) writer structure"] impl crate :: Writable for SpiErSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_ER to value 0"] impl crate :: Resettable for SpiErSpec { } }
#[doc = "SPI_CTRA (rw) register accessor: SPI control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctra`] module"]
#[doc (alias = "SPI_CTRA")] pub type SpiCtra = crate :: Reg < spi_ctra :: SpiCtraSpec > ;
#[doc = "SPI control register 0"] pub mod spi_ctra {
#[doc = "Register `SPI_CTRA` reader"] pub type R = crate :: R < SpiCtraSpec > ;
#[doc = "Register `SPI_CTRA` writer"] pub type W = crate :: W < SpiCtraSpec > ;
#[doc = "Field `soe` reader - Shift register loop test: 0=normal; 1=loopback"] pub type SoeR = crate :: BitReader ;
#[doc = "Field `soe` writer - Shift register loop test: 0=normal; 1=loopback"] pub type SoeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Clock phase: 0=first edge sample; 1=second edge sample\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Scph {
#[doc = "0: Sample on first clock edge"] FirstEdge = 0 ,
#[doc = "1: Sample on second clock edge"] SecondEdge = 1 , } impl From < Scph > for bool {
#[inline (always)] fn from (variant : Scph) -> Self { variant as u8 != 0 } }
#[doc = "Field `scph` reader - Clock phase: 0=first edge sample; 1=second edge sample"] pub type ScphR = crate :: BitReader < Scph > ; impl ScphR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Scph { match self . bits { false => Scph :: FirstEdge , true => Scph :: SecondEdge , } }
#[doc = "Sample on first clock edge"]
#[inline (always)] pub fn is_first_edge (& self) -> bool { * self == Scph :: FirstEdge }
#[doc = "Sample on second clock edge"]
#[inline (always)] pub fn is_second_edge (& self) -> bool { * self == Scph :: SecondEdge } }
#[doc = "Field `scph` writer - Clock phase: 0=first edge sample; 1=second edge sample"] pub type ScphW < 'a , REG > = crate :: BitWriter < 'a , REG , Scph > ; impl < 'a , REG > ScphW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "Sample on first clock edge"]
#[inline (always)] pub fn first_edge (self) -> & 'a mut crate :: W < REG > { self . variant (Scph :: FirstEdge) }
#[doc = "Sample on second clock edge"]
#[inline (always)] pub fn second_edge (self) -> & 'a mut crate :: W < REG > { self . variant (Scph :: SecondEdge) } }
#[doc = "Clock polarity: 0=low idle; 1=high idle\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum Scpol {
#[doc = "0: SCK idle low"] LowIdle = 0 ,
#[doc = "1: SCK idle high"] HighIdle = 1 , } impl From < Scpol > for bool {
#[inline (always)] fn from (variant : Scpol) -> Self { variant as u8 != 0 } }
#[doc = "Field `scpol` reader - Clock polarity: 0=low idle; 1=high idle"] pub type ScpolR = crate :: BitReader < Scpol > ; impl ScpolR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Scpol { match self . bits { false => Scpol :: LowIdle , true => Scpol :: HighIdle , } }
#[doc = "SCK idle low"]
#[inline (always)] pub fn is_low_idle (& self) -> bool { * self == Scpol :: LowIdle }
#[doc = "SCK idle high"]
#[inline (always)] pub fn is_high_idle (& self) -> bool { * self == Scpol :: HighIdle } }
#[doc = "Field `scpol` writer - Clock polarity: 0=low idle; 1=high idle"] pub type ScpolW < 'a , REG > = crate :: BitWriter < 'a , REG , Scpol > ; impl < 'a , REG > ScpolW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "SCK idle low"]
#[inline (always)] pub fn low_idle (self) -> & 'a mut crate :: W < REG > { self . variant (Scpol :: LowIdle) }
#[doc = "SCK idle high"]
#[inline (always)] pub fn high_idle (self) -> & 'a mut crate :: W < REG > { self . variant (Scpol :: HighIdle) } }
#[doc = "Field `dfs32` reader - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"] pub type Dfs32R = crate :: FieldReader ;
#[doc = "Field `dfs32` writer - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"] pub type Dfs32W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ;
#[doc = "Transfer mode: 00=TX/RX; 01=TX only; 10=RX only\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum Trsm {
#[doc = "0: Transmit and Receive"] TxRx = 0 ,
#[doc = "1: Transmit Only"] TxOnly = 1 ,
#[doc = "2: Receive Only"] RxOnly = 2 , } impl From < Trsm > for u8 {
#[inline (always)] fn from (variant : Trsm) -> Self { variant as _ } } impl crate :: FieldSpec for Trsm { type Ux = u8 ; } impl crate :: IsEnum for Trsm { }
#[doc = "Field `trsm` reader - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"] pub type TrsmR = crate :: FieldReader < Trsm > ; impl TrsmR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < Trsm > { match self . bits { 0 => Some (Trsm :: TxRx) , 1 => Some (Trsm :: TxOnly) , 2 => Some (Trsm :: RxOnly) , _ => None , } }
#[doc = "Transmit and Receive"]
#[inline (always)] pub fn is_tx_rx (& self) -> bool { * self == Trsm :: TxRx }
#[doc = "Transmit Only"]
#[inline (always)] pub fn is_tx_only (& self) -> bool { * self == Trsm :: TxOnly }
#[doc = "Receive Only"]
#[inline (always)] pub fn is_rx_only (& self) -> bool { * self == Trsm :: RxOnly } }
#[doc = "Field `trsm` writer - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"] pub type TrsmW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Trsm > ; impl < 'a , REG > TrsmW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Transmit and Receive"]
#[inline (always)] pub fn tx_rx (self) -> & 'a mut crate :: W < REG > { self . variant (Trsm :: TxRx) }
#[doc = "Transmit Only"]
#[inline (always)] pub fn tx_only (self) -> & 'a mut crate :: W < REG > { self . variant (Trsm :: TxOnly) }
#[doc = "Receive Only"]
#[inline (always)] pub fn rx_only (self) -> & 'a mut crate :: W < REG > { self . variant (Trsm :: RxOnly) } } impl R {
#[doc = "Bit 0 - Shift register loop test: 0=normal; 1=loopback"]
#[inline (always)] pub fn soe (& self) -> SoeR { SoeR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 3 - Clock phase: 0=first edge sample; 1=second edge sample"]
#[inline (always)] pub fn scph (& self) -> ScphR { ScphR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Clock polarity: 0=low idle; 1=high idle"]
#[inline (always)] pub fn scpol (& self) -> ScpolR { ScpolR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bits 13:17 - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
#[inline (always)] pub fn dfs32 (& self) -> Dfs32R { Dfs32R :: new (((self . bits >> 13) & 0x1f) as u8) }
#[doc = "Bits 18:19 - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
#[inline (always)] pub fn trsm (& self) -> TrsmR { TrsmR :: new (((self . bits >> 18) & 3) as u8) } } impl W {
#[doc = "Bit 0 - Shift register loop test: 0=normal; 1=loopback"]
#[inline (always)] pub fn soe (& mut self) -> SoeW < '_ , SpiCtraSpec > { SoeW :: new (self , 0) }
#[doc = "Bit 3 - Clock phase: 0=first edge sample; 1=second edge sample"]
#[inline (always)] pub fn scph (& mut self) -> ScphW < '_ , SpiCtraSpec > { ScphW :: new (self , 3) }
#[doc = "Bit 4 - Clock polarity: 0=low idle; 1=high idle"]
#[inline (always)] pub fn scpol (& mut self) -> ScpolW < '_ , SpiCtraSpec > { ScpolW :: new (self , 4) }
#[doc = "Bits 13:17 - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
#[inline (always)] pub fn dfs32 (& mut self) -> Dfs32W < '_ , SpiCtraSpec > { Dfs32W :: new (self , 13) }
#[doc = "Bits 18:19 - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
#[inline (always)] pub fn trsm (& mut self) -> TrsmW < '_ , SpiCtraSpec > { TrsmW :: new (self , 18) } }
#[doc = "SPI control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiCtraSpec ; impl crate :: RegisterSpec for SpiCtraSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_ctra::R`](R) reader structure"] impl crate :: Readable for SpiCtraSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_ctra::W`](W) writer structure"] impl crate :: Writable for SpiCtraSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_CTRA to value 0"] impl crate :: Resettable for SpiCtraSpec { } }
#[doc = "SPI_CTRB (rw) register accessor: SPI control register 1 (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrb`] module"]
#[doc (alias = "SPI_CTRB")] pub type SpiCtrb = crate :: Reg < spi_ctrb :: SpiCtrbSpec > ;
#[doc = "SPI control register 1 (master only)"] pub mod spi_ctrb {
#[doc = "Register `SPI_CTRB` reader"] pub type R = crate :: R < SpiCtrbSpec > ;
#[doc = "Register `SPI_CTRB` writer"] pub type W = crate :: W < SpiCtrbSpec > ;
#[doc = "Field `ndf` reader - Number of data frames (master TX only mode)"] pub type NdfR = crate :: FieldReader < u16 > ;
#[doc = "Field `ndf` writer - Number of data frames (master TX only mode)"] pub type NdfW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ;
#[doc = "Field `ssi_clk_stretch_en` reader - Clock stretch enable"] pub type SsiClkStretchEnR = crate :: BitReader ;
#[doc = "Field `ssi_clk_stretch_en` writer - Clock stretch enable"] pub type SsiClkStretchEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:15 - Number of data frames (master TX only mode)"]
#[inline (always)] pub fn ndf (& self) -> NdfR { NdfR :: new ((self . bits & 0xffff) as u16) }
#[doc = "Bit 27 - Clock stretch enable"]
#[inline (always)] pub fn ssi_clk_stretch_en (& self) -> SsiClkStretchEnR { SsiClkStretchEnR :: new (((self . bits >> 27) & 1) != 0) } } impl W {
#[doc = "Bits 0:15 - Number of data frames (master TX only mode)"]
#[inline (always)] pub fn ndf (& mut self) -> NdfW < '_ , SpiCtrbSpec > { NdfW :: new (self , 0) }
#[doc = "Bit 27 - Clock stretch enable"]
#[inline (always)] pub fn ssi_clk_stretch_en (& mut self) -> SsiClkStretchEnW < '_ , SpiCtrbSpec > { SsiClkStretchEnW :: new (self , 27) } }
#[doc = "SPI control register 1 (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiCtrbSpec ; impl crate :: RegisterSpec for SpiCtrbSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_ctrb::R`](R) reader structure"] impl crate :: Readable for SpiCtrbSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_ctrb::W`](W) writer structure"] impl crate :: Writable for SpiCtrbSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_CTRB to value 0"] impl crate :: Resettable for SpiCtrbSpec { } }
#[doc = "SPI_ENHCTL (rw) register accessor: Enhanced control register (Dual/Quad/Octal)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_enhctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_enhctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_enhctl`] module"]
#[doc (alias = "SPI_ENHCTL")] pub type SpiEnhctl = crate :: Reg < spi_enhctl :: SpiEnhctlSpec > ;
#[doc = "Enhanced control register (Dual/Quad/Octal)"] pub mod spi_enhctl {
#[doc = "Register `SPI_ENHCTL` reader"] pub type R = crate :: R < SpiEnhctlSpec > ;
#[doc = "Register `SPI_ENHCTL` writer"] pub type W = crate :: W < SpiEnhctlSpec > ;
#[doc = "Field `spi_dual_en` reader - Dual SPI mode enable"] pub type SpiDualEnR = crate :: BitReader ;
#[doc = "Field `spi_dual_en` writer - Dual SPI mode enable"] pub type SpiDualEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `spi_quad_en` reader - Quad SPI mode enable"] pub type SpiQuadEnR = crate :: BitReader ;
#[doc = "Field `spi_quad_en` writer - Quad SPI mode enable"] pub type SpiQuadEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `spi_oct_en` reader - Octal SPI mode enable"] pub type SpiOctEnR = crate :: BitReader ;
#[doc = "Field `spi_oct_en` writer - Octal SPI mode enable"] pub type SpiOctEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Dual SPI mode enable"]
#[inline (always)] pub fn spi_dual_en (& self) -> SpiDualEnR { SpiDualEnR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Quad SPI mode enable"]
#[inline (always)] pub fn spi_quad_en (& self) -> SpiQuadEnR { SpiQuadEnR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Octal SPI mode enable"]
#[inline (always)] pub fn spi_oct_en (& self) -> SpiOctEnR { SpiOctEnR :: new (((self . bits >> 2) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Dual SPI mode enable"]
#[inline (always)] pub fn spi_dual_en (& mut self) -> SpiDualEnW < '_ , SpiEnhctlSpec > { SpiDualEnW :: new (self , 0) }
#[doc = "Bit 1 - Quad SPI mode enable"]
#[inline (always)] pub fn spi_quad_en (& mut self) -> SpiQuadEnW < '_ , SpiEnhctlSpec > { SpiQuadEnW :: new (self , 1) }
#[doc = "Bit 2 - Octal SPI mode enable"]
#[inline (always)] pub fn spi_oct_en (& mut self) -> SpiOctEnW < '_ , SpiEnhctlSpec > { SpiOctEnW :: new (self , 2) } }
#[doc = "Enhanced control register (Dual/Quad/Octal)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_enhctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_enhctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiEnhctlSpec ; impl crate :: RegisterSpec for SpiEnhctlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_enhctl::R`](R) reader structure"] impl crate :: Readable for SpiEnhctlSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_enhctl::W`](W) writer structure"] impl crate :: Writable for SpiEnhctlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_ENHCTL to value 0"] impl crate :: Resettable for SpiEnhctlSpec { } }
#[doc = "SPI_BRS (rw) register accessor: Baud rate select register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_brs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_brs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_brs`] module"]
#[doc (alias = "SPI_BRS")] pub type SpiBrs = crate :: Reg < spi_brs :: SpiBrsSpec > ;
#[doc = "Baud rate select register"] pub mod spi_brs {
#[doc = "Register `SPI_BRS` reader"] pub type R = crate :: R < SpiBrsSpec > ;
#[doc = "Register `SPI_BRS` writer"] pub type W = crate :: W < SpiBrsSpec > ;
#[doc = "Field `clk_div` reader - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"] pub type ClkDivR = crate :: FieldReader < u16 > ;
#[doc = "Field `clk_div` writer - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"] pub type ClkDivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
#[inline (always)] pub fn clk_div (& self) -> ClkDivR { ClkDivR :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
#[inline (always)] pub fn clk_div (& mut self) -> ClkDivW < '_ , SpiBrsSpec > { ClkDivW :: new (self , 0) } }
#[doc = "Baud rate select register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_brs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_brs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiBrsSpec ; impl crate :: RegisterSpec for SpiBrsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_brs::R`](R) reader structure"] impl crate :: Readable for SpiBrsSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_brs::W`](W) writer structure"] impl crate :: Writable for SpiBrsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_BRS to value 0"] impl crate :: Resettable for SpiBrsSpec { } }
#[doc = "SPI_DCR (rw) register accessor: DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dcr`] module"]
#[doc (alias = "SPI_DCR")] pub type SpiDcr = crate :: Reg < spi_dcr :: SpiDcrSpec > ;
#[doc = "DMA control register"] pub mod spi_dcr {
#[doc = "Register `SPI_DCR` reader"] pub type R = crate :: R < SpiDcrSpec > ;
#[doc = "Register `SPI_DCR` writer"] pub type W = crate :: W < SpiDcrSpec > ;
#[doc = "Field `tdmae` reader - TX DMA enable"] pub type TdmaeR = crate :: BitReader ;
#[doc = "Field `tdmae` writer - TX DMA enable"] pub type TdmaeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rdmae` reader - RX DMA enable"] pub type RdmaeR = crate :: BitReader ;
#[doc = "Field `rdmae` writer - RX DMA enable"] pub type RdmaeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - TX DMA enable"]
#[inline (always)] pub fn tdmae (& self) -> TdmaeR { TdmaeR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - RX DMA enable"]
#[inline (always)] pub fn rdmae (& self) -> RdmaeR { RdmaeR :: new (((self . bits >> 1) & 1) != 0) } } impl W {
#[doc = "Bit 0 - TX DMA enable"]
#[inline (always)] pub fn tdmae (& mut self) -> TdmaeW < '_ , SpiDcrSpec > { TdmaeW :: new (self , 0) }
#[doc = "Bit 1 - RX DMA enable"]
#[inline (always)] pub fn rdmae (& mut self) -> RdmaeW < '_ , SpiDcrSpec > { RdmaeW :: new (self , 1) } }
#[doc = "DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiDcrSpec ; impl crate :: RegisterSpec for SpiDcrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_dcr::R`](R) reader structure"] impl crate :: Readable for SpiDcrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_dcr::W`](W) writer structure"] impl crate :: Writable for SpiDcrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_DCR to value 0"] impl crate :: Resettable for SpiDcrSpec { } }
#[doc = "SPI_DRDL (rw) register accessor: DMA RX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_drdl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_drdl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_drdl`] module"]
#[doc (alias = "SPI_DRDL")] pub type SpiDrdl = crate :: Reg < spi_drdl :: SpiDrdlSpec > ;
#[doc = "DMA RX data level"] pub mod spi_drdl {
#[doc = "Register `SPI_DRDL` reader"] pub type R = crate :: R < SpiDrdlSpec > ;
#[doc = "Register `SPI_DRDL` writer"] pub type W = crate :: W < SpiDrdlSpec > ;
#[doc = "Field `dma_rx_data_level` reader - DMA RX FIFO threshold"] pub type DmaRxDataLevelR = crate :: FieldReader ;
#[doc = "Field `dma_rx_data_level` writer - DMA RX FIFO threshold"] pub type DmaRxDataLevelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - DMA RX FIFO threshold"]
#[inline (always)] pub fn dma_rx_data_level (& self) -> DmaRxDataLevelR { DmaRxDataLevelR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - DMA RX FIFO threshold"]
#[inline (always)] pub fn dma_rx_data_level (& mut self) -> DmaRxDataLevelW < '_ , SpiDrdlSpec > { DmaRxDataLevelW :: new (self , 0) } }
#[doc = "DMA RX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_drdl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_drdl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiDrdlSpec ; impl crate :: RegisterSpec for SpiDrdlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_drdl::R`](R) reader structure"] impl crate :: Readable for SpiDrdlSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_drdl::W`](W) writer structure"] impl crate :: Writable for SpiDrdlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_DRDL to value 0"] impl crate :: Resettable for SpiDrdlSpec { } }
#[doc = "SPI_DTDL (rw) register accessor: DMA TX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dtdl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dtdl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dtdl`] module"]
#[doc (alias = "SPI_DTDL")] pub type SpiDtdl = crate :: Reg < spi_dtdl :: SpiDtdlSpec > ;
#[doc = "DMA TX data level"] pub mod spi_dtdl {
#[doc = "Register `SPI_DTDL` reader"] pub type R = crate :: R < SpiDtdlSpec > ;
#[doc = "Register `SPI_DTDL` writer"] pub type W = crate :: W < SpiDtdlSpec > ;
#[doc = "Field `dma_tx_data_level` reader - DMA TX FIFO threshold"] pub type DmaTxDataLevelR = crate :: FieldReader ;
#[doc = "Field `dma_tx_data_level` writer - DMA TX FIFO threshold"] pub type DmaTxDataLevelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - DMA TX FIFO threshold"]
#[inline (always)] pub fn dma_tx_data_level (& self) -> DmaTxDataLevelR { DmaTxDataLevelR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - DMA TX FIFO threshold"]
#[inline (always)] pub fn dma_tx_data_level (& mut self) -> DmaTxDataLevelW < '_ , SpiDtdlSpec > { DmaTxDataLevelW :: new (self , 0) } }
#[doc = "DMA TX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dtdl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dtdl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiDtdlSpec ; impl crate :: RegisterSpec for SpiDtdlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_dtdl::R`](R) reader structure"] impl crate :: Readable for SpiDtdlSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_dtdl::W`](W) writer structure"] impl crate :: Writable for SpiDtdlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_DTDL to value 0"] impl crate :: Resettable for SpiDtdlSpec { } }
#[doc = "SPI_DR (rw) register accessor: Data register (FIFO read/write)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dr`] module"]
#[doc (alias = "SPI_DR")] pub type SpiDr = crate :: Reg < spi_dr :: SpiDrSpec > ;
#[doc = "Data register (FIFO read/write)"] pub mod spi_dr {
#[doc = "Register `SPI_DR` reader"] pub type R = crate :: R < SpiDrSpec > ;
#[doc = "Register `SPI_DR` writer"] pub type W = crate :: W < SpiDrSpec > ;
#[doc = "Field `dr` reader - Write: push to TX FIFO; Read: pop from RX FIFO"] pub type DrR = crate :: FieldReader < u32 > ;
#[doc = "Field `dr` writer - Write: push to TX FIFO; Read: pop from RX FIFO"] pub type DrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Write: push to TX FIFO; Read: pop from RX FIFO"]
#[inline (always)] pub fn dr (& self) -> DrR { DrR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Write: push to TX FIFO; Read: pop from RX FIFO"]
#[inline (always)] pub fn dr (& mut self) -> DrW < '_ , SpiDrSpec > { DrW :: new (self , 0) } }
#[doc = "Data register (FIFO read/write)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiDrSpec ; impl crate :: RegisterSpec for SpiDrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_dr::R`](R) reader structure"] impl crate :: Readable for SpiDrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_dr::W`](W) writer structure"] impl crate :: Writable for SpiDrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_DR to value 0"] impl crate :: Resettable for SpiDrSpec { } }
#[doc = "SPI_RAINSR (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rainsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rainsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rainsr`] module"]
#[doc (alias = "SPI_RAINSR")] pub type SpiRainsr = crate :: Reg < spi_rainsr :: SpiRainsrSpec > ;
#[doc = "Raw interrupt status register"] pub mod spi_rainsr {
#[doc = "Register `SPI_RAINSR` reader"] pub type R = crate :: R < SpiRainsrSpec > ;
#[doc = "Register `SPI_RAINSR` writer"] pub type W = crate :: W < SpiRainsrSpec > ;
#[doc = "Field `txe_irq` reader - TX FIFO empty raw status"] pub type TxeIrqR = crate :: BitReader ;
#[doc = "Field `txo_irq` reader - TX FIFO overflow raw status"] pub type TxoIrqR = crate :: BitReader ;
#[doc = "Field `rxu_irq` reader - RX FIFO underflow raw status"] pub type RxuIrqR = crate :: BitReader ;
#[doc = "Field `rxo_irq` reader - RX FIFO overflow raw status"] pub type RxoIrqR = crate :: BitReader ;
#[doc = "Field `rxf_irq` reader - RX FIFO full raw status"] pub type RxfIrqR = crate :: BitReader ;
#[doc = "Field `mst_irq` reader - Multi-master contention raw status"] pub type MstIrqR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - TX FIFO empty raw status"]
#[inline (always)] pub fn txe_irq (& self) -> TxeIrqR { TxeIrqR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TX FIFO overflow raw status"]
#[inline (always)] pub fn txo_irq (& self) -> TxoIrqR { TxoIrqR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - RX FIFO underflow raw status"]
#[inline (always)] pub fn rxu_irq (& self) -> RxuIrqR { RxuIrqR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - RX FIFO overflow raw status"]
#[inline (always)] pub fn rxo_irq (& self) -> RxoIrqR { RxoIrqR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - RX FIFO full raw status"]
#[inline (always)] pub fn rxf_irq (& self) -> RxfIrqR { RxfIrqR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Multi-master contention raw status"]
#[inline (always)] pub fn mst_irq (& self) -> MstIrqR { MstIrqR :: new (((self . bits >> 5) & 1) != 0) } } impl W { }
#[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rainsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rainsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiRainsrSpec ; impl crate :: RegisterSpec for SpiRainsrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_rainsr::R`](R) reader structure"] impl crate :: Readable for SpiRainsrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_rainsr::W`](W) writer structure"] impl crate :: Writable for SpiRainsrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_RAINSR to value 0"] impl crate :: Resettable for SpiRainsrSpec { } }
#[doc = "SPI_INSR (rw) register accessor: Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_insr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_insr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_insr`] module"]
#[doc (alias = "SPI_INSR")] pub type SpiInsr = crate :: Reg < spi_insr :: SpiInsrSpec > ;
#[doc = "Interrupt status register (masked)"] pub mod spi_insr {
#[doc = "Register `SPI_INSR` reader"] pub type R = crate :: R < SpiInsrSpec > ;
#[doc = "Register `SPI_INSR` writer"] pub type W = crate :: W < SpiInsrSpec > ;
#[doc = "Field `txe_is` reader - TX empty interrupt status"] pub type TxeIsR = crate :: BitReader ;
#[doc = "Field `txo_is` reader - TX overflow interrupt status"] pub type TxoIsR = crate :: BitReader ;
#[doc = "Field `rxu_is` reader - RX underflow interrupt status"] pub type RxuIsR = crate :: BitReader ;
#[doc = "Field `rxo_is` reader - RX overflow interrupt status"] pub type RxoIsR = crate :: BitReader ;
#[doc = "Field `rxf_is` reader - RX full interrupt status"] pub type RxfIsR = crate :: BitReader ;
#[doc = "Field `mst_is` reader - Multi-master interrupt status"] pub type MstIsR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - TX empty interrupt status"]
#[inline (always)] pub fn txe_is (& self) -> TxeIsR { TxeIsR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TX overflow interrupt status"]
#[inline (always)] pub fn txo_is (& self) -> TxoIsR { TxoIsR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - RX underflow interrupt status"]
#[inline (always)] pub fn rxu_is (& self) -> RxuIsR { RxuIsR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - RX overflow interrupt status"]
#[inline (always)] pub fn rxo_is (& self) -> RxoIsR { RxoIsR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - RX full interrupt status"]
#[inline (always)] pub fn rxf_is (& self) -> RxfIsR { RxfIsR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Multi-master interrupt status"]
#[inline (always)] pub fn mst_is (& self) -> MstIsR { MstIsR :: new (((self . bits >> 5) & 1) != 0) } } impl W { }
#[doc = "Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_insr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_insr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiInsrSpec ; impl crate :: RegisterSpec for SpiInsrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_insr::R`](R) reader structure"] impl crate :: Readable for SpiInsrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_insr::W`](W) writer structure"] impl crate :: Writable for SpiInsrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_INSR to value 0"] impl crate :: Resettable for SpiInsrSpec { } }
#[doc = "SPI_INMAR (rw) register accessor: Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_inmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_inmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_inmar`] module"]
#[doc (alias = "SPI_INMAR")] pub type SpiInmar = crate :: Reg < spi_inmar :: SpiInmarSpec > ;
#[doc = "Interrupt mask register"] pub mod spi_inmar {
#[doc = "Register `SPI_INMAR` reader"] pub type R = crate :: R < SpiInmarSpec > ;
#[doc = "Register `SPI_INMAR` writer"] pub type W = crate :: W < SpiInmarSpec > ;
#[doc = "Field `txe_im` reader - TX empty interrupt mask"] pub type TxeImR = crate :: BitReader ;
#[doc = "Field `txe_im` writer - TX empty interrupt mask"] pub type TxeImW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `txo_im` reader - TX overflow interrupt mask"] pub type TxoImR = crate :: BitReader ;
#[doc = "Field `txo_im` writer - TX overflow interrupt mask"] pub type TxoImW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rxu_im` reader - RX underflow interrupt mask"] pub type RxuImR = crate :: BitReader ;
#[doc = "Field `rxu_im` writer - RX underflow interrupt mask"] pub type RxuImW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rxo_im` reader - RX overflow interrupt mask"] pub type RxoImR = crate :: BitReader ;
#[doc = "Field `rxo_im` writer - RX overflow interrupt mask"] pub type RxoImW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rxf_im` reader - RX full interrupt mask"] pub type RxfImR = crate :: BitReader ;
#[doc = "Field `rxf_im` writer - RX full interrupt mask"] pub type RxfImW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `mst_im` reader - Multi-master interrupt mask"] pub type MstImR = crate :: BitReader ;
#[doc = "Field `mst_im` writer - Multi-master interrupt mask"] pub type MstImW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - TX empty interrupt mask"]
#[inline (always)] pub fn txe_im (& self) -> TxeImR { TxeImR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TX overflow interrupt mask"]
#[inline (always)] pub fn txo_im (& self) -> TxoImR { TxoImR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - RX underflow interrupt mask"]
#[inline (always)] pub fn rxu_im (& self) -> RxuImR { RxuImR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - RX overflow interrupt mask"]
#[inline (always)] pub fn rxo_im (& self) -> RxoImR { RxoImR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - RX full interrupt mask"]
#[inline (always)] pub fn rxf_im (& self) -> RxfImR { RxfImR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Multi-master interrupt mask"]
#[inline (always)] pub fn mst_im (& self) -> MstImR { MstImR :: new (((self . bits >> 5) & 1) != 0) } } impl W {
#[doc = "Bit 0 - TX empty interrupt mask"]
#[inline (always)] pub fn txe_im (& mut self) -> TxeImW < '_ , SpiInmarSpec > { TxeImW :: new (self , 0) }
#[doc = "Bit 1 - TX overflow interrupt mask"]
#[inline (always)] pub fn txo_im (& mut self) -> TxoImW < '_ , SpiInmarSpec > { TxoImW :: new (self , 1) }
#[doc = "Bit 2 - RX underflow interrupt mask"]
#[inline (always)] pub fn rxu_im (& mut self) -> RxuImW < '_ , SpiInmarSpec > { RxuImW :: new (self , 2) }
#[doc = "Bit 3 - RX overflow interrupt mask"]
#[inline (always)] pub fn rxo_im (& mut self) -> RxoImW < '_ , SpiInmarSpec > { RxoImW :: new (self , 3) }
#[doc = "Bit 4 - RX full interrupt mask"]
#[inline (always)] pub fn rxf_im (& mut self) -> RxfImW < '_ , SpiInmarSpec > { RxfImW :: new (self , 4) }
#[doc = "Bit 5 - Multi-master interrupt mask"]
#[inline (always)] pub fn mst_im (& mut self) -> MstImW < '_ , SpiInmarSpec > { MstImW :: new (self , 5) } }
#[doc = "Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_inmar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_inmar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiInmarSpec ; impl crate :: RegisterSpec for SpiInmarSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_inmar::R`](R) reader structure"] impl crate :: Readable for SpiInmarSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_inmar::W`](W) writer structure"] impl crate :: Writable for SpiInmarSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_INMAR to value 0"] impl crate :: Resettable for SpiInmarSpec { } }
#[doc = "SPI_SLENR (rw) register accessor: Slave enable register (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_slenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_slenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slenr`] module"]
#[doc (alias = "SPI_SLENR")] pub type SpiSlenr = crate :: Reg < spi_slenr :: SpiSlenrSpec > ;
#[doc = "Slave enable register (master only)"] pub mod spi_slenr {
#[doc = "Register `SPI_SLENR` reader"] pub type R = crate :: R < SpiSlenrSpec > ;
#[doc = "Register `SPI_SLENR` writer"] pub type W = crate :: W < SpiSlenrSpec > ;
#[doc = "Field `slave_enable` reader - Slave select enable"] pub type SlaveEnableR = crate :: BitReader ;
#[doc = "Field `slave_enable` writer - Slave select enable"] pub type SlaveEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Slave select enable"]
#[inline (always)] pub fn slave_enable (& self) -> SlaveEnableR { SlaveEnableR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Slave select enable"]
#[inline (always)] pub fn slave_enable (& mut self) -> SlaveEnableW < '_ , SpiSlenrSpec > { SlaveEnableW :: new (self , 0) } }
#[doc = "Slave enable register (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_slenr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_slenr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiSlenrSpec ; impl crate :: RegisterSpec for SpiSlenrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_slenr::R`](R) reader structure"] impl crate :: Readable for SpiSlenrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_slenr::W`](W) writer structure"] impl crate :: Writable for SpiSlenrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_SLENR to value 0"] impl crate :: Resettable for SpiSlenrSpec { } }
#[doc = "SPI_TWLR (rw) register accessor: TX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_twlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_twlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_twlr`] module"]
#[doc (alias = "SPI_TWLR")] pub type SpiTwlr = crate :: Reg < spi_twlr :: SpiTwlrSpec > ;
#[doc = "TX FIFO threshold level"] pub mod spi_twlr {
#[doc = "Register `SPI_TWLR` reader"] pub type R = crate :: R < SpiTwlrSpec > ;
#[doc = "Register `SPI_TWLR` writer"] pub type W = crate :: W < SpiTwlrSpec > ;
#[doc = "Field `tx_fifo_threshold` reader - TX FIFO threshold level"] pub type TxFifoThresholdR = crate :: FieldReader ;
#[doc = "Field `tx_fifo_threshold` writer - TX FIFO threshold level"] pub type TxFifoThresholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - TX FIFO threshold level"]
#[inline (always)] pub fn tx_fifo_threshold (& self) -> TxFifoThresholdR { TxFifoThresholdR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - TX FIFO threshold level"]
#[inline (always)] pub fn tx_fifo_threshold (& mut self) -> TxFifoThresholdW < '_ , SpiTwlrSpec > { TxFifoThresholdW :: new (self , 0) } }
#[doc = "TX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_twlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_twlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiTwlrSpec ; impl crate :: RegisterSpec for SpiTwlrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_twlr::R`](R) reader structure"] impl crate :: Readable for SpiTwlrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_twlr::W`](W) writer structure"] impl crate :: Writable for SpiTwlrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_TWLR to value 0"] impl crate :: Resettable for SpiTwlrSpec { } }
#[doc = "SPI_TLR (rw) register accessor: TX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_tlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_tlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_tlr`] module"]
#[doc (alias = "SPI_TLR")] pub type SpiTlr = crate :: Reg < spi_tlr :: SpiTlrSpec > ;
#[doc = "TX FIFO level register"] pub mod spi_tlr {
#[doc = "Register `SPI_TLR` reader"] pub type R = crate :: R < SpiTlrSpec > ;
#[doc = "Register `SPI_TLR` writer"] pub type W = crate :: W < SpiTlrSpec > ;
#[doc = "Field `tx_fifo_level` reader - TX FIFO data level"] pub type TxFifoLevelR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - TX FIFO data level"]
#[inline (always)] pub fn tx_fifo_level (& self) -> TxFifoLevelR { TxFifoLevelR :: new ((self . bits & 0xff) as u8) } } impl W { }
#[doc = "TX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_tlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_tlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiTlrSpec ; impl crate :: RegisterSpec for SpiTlrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_tlr::R`](R) reader structure"] impl crate :: Readable for SpiTlrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_tlr::W`](W) writer structure"] impl crate :: Writable for SpiTlrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_TLR to value 0"] impl crate :: Resettable for SpiTlrSpec { } }
#[doc = "SPI_RWLR (rw) register accessor: RX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rwlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rwlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rwlr`] module"]
#[doc (alias = "SPI_RWLR")] pub type SpiRwlr = crate :: Reg < spi_rwlr :: SpiRwlrSpec > ;
#[doc = "RX FIFO threshold level"] pub mod spi_rwlr {
#[doc = "Register `SPI_RWLR` reader"] pub type R = crate :: R < SpiRwlrSpec > ;
#[doc = "Register `SPI_RWLR` writer"] pub type W = crate :: W < SpiRwlrSpec > ;
#[doc = "Field `rx_fifo_threshold` reader - RX FIFO threshold level"] pub type RxFifoThresholdR = crate :: FieldReader ;
#[doc = "Field `rx_fifo_threshold` writer - RX FIFO threshold level"] pub type RxFifoThresholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - RX FIFO threshold level"]
#[inline (always)] pub fn rx_fifo_threshold (& self) -> RxFifoThresholdR { RxFifoThresholdR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - RX FIFO threshold level"]
#[inline (always)] pub fn rx_fifo_threshold (& mut self) -> RxFifoThresholdW < '_ , SpiRwlrSpec > { RxFifoThresholdW :: new (self , 0) } }
#[doc = "RX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rwlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rwlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiRwlrSpec ; impl crate :: RegisterSpec for SpiRwlrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_rwlr::R`](R) reader structure"] impl crate :: Readable for SpiRwlrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_rwlr::W`](W) writer structure"] impl crate :: Writable for SpiRwlrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_RWLR to value 0"] impl crate :: Resettable for SpiRwlrSpec { } }
#[doc = "SPI_RLR (rw) register accessor: RX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rlr`] module"]
#[doc (alias = "SPI_RLR")] pub type SpiRlr = crate :: Reg < spi_rlr :: SpiRlrSpec > ;
#[doc = "RX FIFO level register"] pub mod spi_rlr {
#[doc = "Register `SPI_RLR` reader"] pub type R = crate :: R < SpiRlrSpec > ;
#[doc = "Register `SPI_RLR` writer"] pub type W = crate :: W < SpiRlrSpec > ;
#[doc = "Field `rx_fifo_level` reader - RX FIFO data level"] pub type RxFifoLevelR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - RX FIFO data level"]
#[inline (always)] pub fn rx_fifo_level (& self) -> RxFifoLevelR { RxFifoLevelR :: new ((self . bits & 0xff) as u8) } } impl W { }
#[doc = "RX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiRlrSpec ; impl crate :: RegisterSpec for SpiRlrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_rlr::R`](R) reader structure"] impl crate :: Readable for SpiRlrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_rlr::W`](W) writer structure"] impl crate :: Writable for SpiRlrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_RLR to value 0"] impl crate :: Resettable for SpiRlrSpec { } }
#[doc = "SPI_WSR (rw) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_wsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_wsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_wsr`] module"]
#[doc (alias = "SPI_WSR")] pub type SpiWsr = crate :: Reg < spi_wsr :: SpiWsrSpec > ;
#[doc = "Status register"] pub mod spi_wsr {
#[doc = "Register `SPI_WSR` reader"] pub type R = crate :: R < SpiWsrSpec > ;
#[doc = "Register `SPI_WSR` writer"] pub type W = crate :: W < SpiWsrSpec > ;
#[doc = "Field `busy` reader - SPI busy flag"] pub type BusyR = crate :: BitReader ;
#[doc = "Field `txfnf` reader - TX FIFO not full"] pub type TxfnfR = crate :: BitReader ;
#[doc = "Field `txfe` reader - TX FIFO empty"] pub type TxfeR = crate :: BitReader ;
#[doc = "Field `rxfne` reader - RX FIFO not empty"] pub type RxfneR = crate :: BitReader ;
#[doc = "Field `rxfo` reader - RX FIFO overflow"] pub type RxfoR = crate :: BitReader ;
#[doc = "Field `txfo` reader - TX FIFO overflow"] pub type TxfoR = crate :: BitReader ;
#[doc = "Field `dcm` reader - Data conflict mask"] pub type DcmR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - SPI busy flag"]
#[inline (always)] pub fn busy (& self) -> BusyR { BusyR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TX FIFO not full"]
#[inline (always)] pub fn txfnf (& self) -> TxfnfR { TxfnfR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - TX FIFO empty"]
#[inline (always)] pub fn txfe (& self) -> TxfeR { TxfeR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - RX FIFO not empty"]
#[inline (always)] pub fn rxfne (& self) -> RxfneR { RxfneR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - RX FIFO overflow"]
#[inline (always)] pub fn rxfo (& self) -> RxfoR { RxfoR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - TX FIFO overflow"]
#[inline (always)] pub fn txfo (& self) -> TxfoR { TxfoR :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - Data conflict mask"]
#[inline (always)] pub fn dcm (& self) -> DcmR { DcmR :: new (((self . bits >> 6) & 1) != 0) } } impl W { }
#[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_wsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_wsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiWsrSpec ; impl crate :: RegisterSpec for SpiWsrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_wsr::R`](R) reader structure"] impl crate :: Readable for SpiWsrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_wsr::W`](W) writer structure"] impl crate :: Writable for SpiWsrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_WSR to value 0x06"] impl crate :: Resettable for SpiWsrSpec { const RESET_VALUE : u32 = 0x06 ; } }
#[doc = "SPI_ICR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_icr`] module"]
#[doc (alias = "SPI_ICR")] pub type SpiIcr = crate :: Reg < spi_icr :: SpiIcrSpec > ;
#[doc = "Interrupt clear register"] pub mod spi_icr {
#[doc = "Register `SPI_ICR` reader"] pub type R = crate :: R < SpiIcrSpec > ;
#[doc = "Register `SPI_ICR` writer"] pub type W = crate :: W < SpiIcrSpec > ;
#[doc = "Field `txo_ic` writer - TX overflow interrupt clear"] pub type TxoIcW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rxu_ic` writer - RX underflow interrupt clear"] pub type RxuIcW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rxo_ic` writer - RX overflow interrupt clear"] pub type RxoIcW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `mst_ic` writer - Multi-master interrupt clear"] pub type MstIcW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - TX overflow interrupt clear"]
#[inline (always)] pub fn txo_ic (& mut self) -> TxoIcW < '_ , SpiIcrSpec > { TxoIcW :: new (self , 0) }
#[doc = "Bit 1 - RX underflow interrupt clear"]
#[inline (always)] pub fn rxu_ic (& mut self) -> RxuIcW < '_ , SpiIcrSpec > { RxuIcW :: new (self , 1) }
#[doc = "Bit 2 - RX overflow interrupt clear"]
#[inline (always)] pub fn rxo_ic (& mut self) -> RxoIcW < '_ , SpiIcrSpec > { RxoIcW :: new (self , 2) }
#[doc = "Bit 3 - Multi-master interrupt clear"]
#[inline (always)] pub fn mst_ic (& mut self) -> MstIcW < '_ , SpiIcrSpec > { MstIcW :: new (self , 3) } }
#[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpiIcrSpec ; impl crate :: RegisterSpec for SpiIcrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spi_icr::R`](R) reader structure"] impl crate :: Readable for SpiIcrSpec { }
#[doc = "`write(|w| ..)` method takes [`spi_icr::W`](W) writer structure"] impl crate :: Writable for SpiIcrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPI_ICR to value 0"] impl crate :: Resettable for SpiIcrSpec { } } }
#[doc = "SPI1/QSPI controller (SSI v151)"] pub type Spi1 = crate :: Periph < spi0 :: RegisterBlock , 0x4402_1000 > ; impl core :: fmt :: Debug for Spi1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Spi1") . finish () } }
#[doc = "SPI1/QSPI controller (SSI v151)"] pub use self :: spi0 as spi1 ;
#[doc = "I2S/SIO synchronous audio interface (v151)"] pub type I2s = crate :: Periph < i2s :: RegisterBlock , 0x4402_5000 > ; impl core :: fmt :: Debug for I2s { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("I2s") . finish () } }
#[doc = "I2S/SIO synchronous audio interface (v151)"] pub mod i2s {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x3c] , version : Version , mode : Mode , intstatus : Intstatus , intclr : Intclr , left_tx : LeftTx , right_tx : RightTx , left_rx : LeftRx , right_rx : RightRx , ct_set : CtSet , ct_clr : CtClr , fifo_threshold : FifoThreshold , rx_sta : RxSta , tx_sta : TxSta , _reserved13 : [u8 ; 0x08] , data_width_set : DataWidthSet , _reserved14 : [u8 ; 0x08] , signed_ext : SignedExt , _reserved15 : [u8 ; 0x04] , intmask : Intmask , i2s_crg : I2sCrg , i2s_bclk_div_num : I2sBclkDivNum , i2s_fs_div_num : I2sFsDivNum , i2s_fs_div_ratio_num : I2sFsDivRatioNum , } impl RegisterBlock {
#[doc = "0x3c - Version and loopback register"]
#[inline (always)] pub const fn version (& self) -> & Version { & self . version }
#[doc = "0x40 - I2S/PCM mode register"]
#[inline (always)] pub const fn mode (& self) -> & Mode { & self . mode }
#[doc = "0x44 - Interrupt status register"]
#[inline (always)] pub const fn intstatus (& self) -> & Intstatus { & self . intstatus }
#[doc = "0x48 - Interrupt clear register"]
#[inline (always)] pub const fn intclr (& self) -> & Intclr { & self . intclr }
#[doc = "0x4c - TX left channel data"]
#[inline (always)] pub const fn left_tx (& self) -> & LeftTx { & self . left_tx }
#[doc = "0x50 - TX right channel data"]
#[inline (always)] pub const fn right_tx (& self) -> & RightTx { & self . right_tx }
#[doc = "0x54 - RX left channel data"]
#[inline (always)] pub const fn left_rx (& self) -> & LeftRx { & self . left_rx }
#[doc = "0x58 - RX right channel data"]
#[inline (always)] pub const fn right_rx (& self) -> & RightRx { & self . right_rx }
#[doc = "0x5c - Control set register"]
#[inline (always)] pub const fn ct_set (& self) -> & CtSet { & self . ct_set }
#[doc = "0x60 - Control clear register"]
#[inline (always)] pub const fn ct_clr (& self) -> & CtClr { & self . ct_clr }
#[doc = "0x64 - FIFO threshold register"]
#[inline (always)] pub const fn fifo_threshold (& self) -> & FifoThreshold { & self . fifo_threshold }
#[doc = "0x68 - RX status register"]
#[inline (always)] pub const fn rx_sta (& self) -> & RxSta { & self . rx_sta }
#[doc = "0x6c - TX status register"]
#[inline (always)] pub const fn tx_sta (& self) -> & TxSta { & self . tx_sta }
#[doc = "0x78 - Data width register"]
#[inline (always)] pub const fn data_width_set (& self) -> & DataWidthSet { & self . data_width_set }
#[doc = "0x84 - Signed extension enable"]
#[inline (always)] pub const fn signed_ext (& self) -> & SignedExt { & self . signed_ext }
#[doc = "0x8c - Interrupt mask register"]
#[inline (always)] pub const fn intmask (& self) -> & Intmask { & self . intmask }
#[doc = "0x90 - I2S clock/reset generator"]
#[inline (always)] pub const fn i2s_crg (& self) -> & I2sCrg { & self . i2s_crg }
#[doc = "0x94 - BCLK divider number"]
#[inline (always)] pub const fn i2s_bclk_div_num (& self) -> & I2sBclkDivNum { & self . i2s_bclk_div_num }
#[doc = "0x98 - FS divider number"]
#[inline (always)] pub const fn i2s_fs_div_num (& self) -> & I2sFsDivNum { & self . i2s_fs_div_num }
#[doc = "0x9c - FS divider ratio number"]
#[inline (always)] pub const fn i2s_fs_div_ratio_num (& self) -> & I2sFsDivRatioNum { & self . i2s_fs_div_ratio_num } }
#[doc = "VERSION (rw) register accessor: Version and loopback register\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"]
#[doc (alias = "VERSION")] pub type Version = crate :: Reg < version :: VersionSpec > ;
#[doc = "Version and loopback register"] pub mod version {
#[doc = "Register `VERSION` reader"] pub type R = crate :: R < VersionSpec > ;
#[doc = "Register `VERSION` writer"] pub type W = crate :: W < VersionSpec > ;
#[doc = "Field `version` reader - IP version"] pub type VersionR = crate :: FieldReader ;
#[doc = "Field `loopback_mode` reader - Loopback mode enable"] pub type LoopbackModeR = crate :: BitReader ;
#[doc = "Field `loopback_mode` writer - Loopback mode enable"] pub type LoopbackModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:7 - IP version"]
#[inline (always)] pub fn version (& self) -> VersionR { VersionR :: new ((self . bits & 0xff) as u8) }
#[doc = "Bit 8 - Loopback mode enable"]
#[inline (always)] pub fn loopback_mode (& self) -> LoopbackModeR { LoopbackModeR :: new (((self . bits >> 8) & 1) != 0) } } impl W {
#[doc = "Bit 8 - Loopback mode enable"]
#[inline (always)] pub fn loopback_mode (& mut self) -> LoopbackModeW < '_ , VersionSpec > { LoopbackModeW :: new (self , 8) } }
#[doc = "Version and loopback register\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct VersionSpec ; impl crate :: RegisterSpec for VersionSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`version::R`](R) reader structure"] impl crate :: Readable for VersionSpec { }
#[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"] impl crate :: Writable for VersionSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets VERSION to value 0"] impl crate :: Resettable for VersionSpec { } }
#[doc = "MODE (rw) register accessor: I2S/PCM mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"]
#[doc (alias = "MODE")] pub type Mode = crate :: Reg < mode :: ModeSpec > ;
#[doc = "I2S/PCM mode register"] pub mod mode {
#[doc = "Register `MODE` reader"] pub type R = crate :: R < ModeSpec > ;
#[doc = "Register `MODE` writer"] pub type W = crate :: W < ModeSpec > ;
#[doc = "Field `channels` reader - Number of channels: 0=2ch; 1=4ch; 2=6ch; 3=8ch"] pub type ChannelsR = crate :: FieldReader ;
#[doc = "Field `channels` writer - Number of channels: 0=2ch; 1=4ch; 2=6ch; 3=8ch"] pub type ChannelsW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ;
#[doc = "Field `clk_edge` reader - Clock edge: 0=rising; 1=falling"] pub type ClkEdgeR = crate :: BitReader ;
#[doc = "Field `clk_edge` writer - Clock edge: 0=rising; 1=falling"] pub type ClkEdgeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `master_slave` reader - Mode: 0=slave; 1=master"] pub type MasterSlaveR = crate :: BitReader ;
#[doc = "Field `master_slave` writer - Mode: 0=slave; 1=master"] pub type MasterSlaveW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pcm_mode` reader - PCM mode: 0=I2S; 1=PCM"] pub type PcmModeR = crate :: BitReader ;
#[doc = "Field `pcm_mode` writer - PCM mode: 0=I2S; 1=PCM"] pub type PcmModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:1 - Number of channels: 0=2ch; 1=4ch; 2=6ch; 3=8ch"]
#[inline (always)] pub fn channels (& self) -> ChannelsR { ChannelsR :: new ((self . bits & 3) as u8) }
#[doc = "Bit 2 - Clock edge: 0=rising; 1=falling"]
#[inline (always)] pub fn clk_edge (& self) -> ClkEdgeR { ClkEdgeR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - Mode: 0=slave; 1=master"]
#[inline (always)] pub fn master_slave (& self) -> MasterSlaveR { MasterSlaveR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - PCM mode: 0=I2S; 1=PCM"]
#[inline (always)] pub fn pcm_mode (& self) -> PcmModeR { PcmModeR :: new (((self . bits >> 4) & 1) != 0) } } impl W {
#[doc = "Bits 0:1 - Number of channels: 0=2ch; 1=4ch; 2=6ch; 3=8ch"]
#[inline (always)] pub fn channels (& mut self) -> ChannelsW < '_ , ModeSpec > { ChannelsW :: new (self , 0) }
#[doc = "Bit 2 - Clock edge: 0=rising; 1=falling"]
#[inline (always)] pub fn clk_edge (& mut self) -> ClkEdgeW < '_ , ModeSpec > { ClkEdgeW :: new (self , 2) }
#[doc = "Bit 3 - Mode: 0=slave; 1=master"]
#[inline (always)] pub fn master_slave (& mut self) -> MasterSlaveW < '_ , ModeSpec > { MasterSlaveW :: new (self , 3) }
#[doc = "Bit 4 - PCM mode: 0=I2S; 1=PCM"]
#[inline (always)] pub fn pcm_mode (& mut self) -> PcmModeW < '_ , ModeSpec > { PcmModeW :: new (self , 4) } }
#[doc = "I2S/PCM mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ModeSpec ; impl crate :: RegisterSpec for ModeSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`mode::R`](R) reader structure"] impl crate :: Readable for ModeSpec { }
#[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"] impl crate :: Writable for ModeSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets MODE to value 0"] impl crate :: Resettable for ModeSpec { } }
#[doc = "INTSTATUS (rw) register accessor: Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intstatus`] module"]
#[doc (alias = "INTSTATUS")] pub type Intstatus = crate :: Reg < intstatus :: IntstatusSpec > ;
#[doc = "Interrupt status register"] pub mod intstatus {
#[doc = "Register `INTSTATUS` reader"] pub type R = crate :: R < IntstatusSpec > ;
#[doc = "Register `INTSTATUS` writer"] pub type W = crate :: W < IntstatusSpec > ;
#[doc = "Field `rx_int` reader - RX interrupt status"] pub type RxIntR = crate :: BitReader ;
#[doc = "Field `tx_int` reader - TX interrupt status"] pub type TxIntR = crate :: BitReader ;
#[doc = "Field `rx_overflow` reader - RX overflow status"] pub type RxOverflowR = crate :: BitReader ;
#[doc = "Field `tx_underflow` reader - TX underflow status"] pub type TxUnderflowR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - RX interrupt status"]
#[inline (always)] pub fn rx_int (& self) -> RxIntR { RxIntR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TX interrupt status"]
#[inline (always)] pub fn tx_int (& self) -> TxIntR { TxIntR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - RX overflow status"]
#[inline (always)] pub fn rx_overflow (& self) -> RxOverflowR { RxOverflowR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - TX underflow status"]
#[inline (always)] pub fn tx_underflow (& self) -> TxUnderflowR { TxUnderflowR :: new (((self . bits >> 3) & 1) != 0) } } impl W { }
#[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntstatusSpec ; impl crate :: RegisterSpec for IntstatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`intstatus::R`](R) reader structure"] impl crate :: Readable for IntstatusSpec { }
#[doc = "`write(|w| ..)` method takes [`intstatus::W`](W) writer structure"] impl crate :: Writable for IntstatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INTSTATUS to value 0"] impl crate :: Resettable for IntstatusSpec { } }
#[doc = "INTCLR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intclr`] module"]
#[doc (alias = "INTCLR")] pub type Intclr = crate :: Reg < intclr :: IntclrSpec > ;
#[doc = "Interrupt clear register"] pub mod intclr {
#[doc = "Register `INTCLR` reader"] pub type R = crate :: R < IntclrSpec > ;
#[doc = "Register `INTCLR` writer"] pub type W = crate :: W < IntclrSpec > ;
#[doc = "Field `rx_int_clr` writer - Clear RX interrupt"] pub type RxIntClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tx_int_clr` writer - Clear TX interrupt"] pub type TxIntClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rx_overflow_clr` writer - Clear RX overflow"] pub type RxOverflowClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tx_underflow_clr` writer - Clear TX underflow"] pub type TxUnderflowClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Clear RX interrupt"]
#[inline (always)] pub fn rx_int_clr (& mut self) -> RxIntClrW < '_ , IntclrSpec > { RxIntClrW :: new (self , 0) }
#[doc = "Bit 1 - Clear TX interrupt"]
#[inline (always)] pub fn tx_int_clr (& mut self) -> TxIntClrW < '_ , IntclrSpec > { TxIntClrW :: new (self , 1) }
#[doc = "Bit 2 - Clear RX overflow"]
#[inline (always)] pub fn rx_overflow_clr (& mut self) -> RxOverflowClrW < '_ , IntclrSpec > { RxOverflowClrW :: new (self , 2) }
#[doc = "Bit 3 - Clear TX underflow"]
#[inline (always)] pub fn tx_underflow_clr (& mut self) -> TxUnderflowClrW < '_ , IntclrSpec > { TxUnderflowClrW :: new (self , 3) } }
#[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`intclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntclrSpec ; impl crate :: RegisterSpec for IntclrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`intclr::R`](R) reader structure"] impl crate :: Readable for IntclrSpec { }
#[doc = "`write(|w| ..)` method takes [`intclr::W`](W) writer structure"] impl crate :: Writable for IntclrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INTCLR to value 0"] impl crate :: Resettable for IntclrSpec { } }
#[doc = "LEFT_TX (rw) register accessor: TX left channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`left_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`left_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@left_tx`] module"]
#[doc (alias = "LEFT_TX")] pub type LeftTx = crate :: Reg < left_tx :: LeftTxSpec > ;
#[doc = "TX left channel data"] pub mod left_tx {
#[doc = "Register `LEFT_TX` reader"] pub type R = crate :: R < LeftTxSpec > ;
#[doc = "Register `LEFT_TX` writer"] pub type W = crate :: W < LeftTxSpec > ;
#[doc = "Field `left_tx_data` reader - TX left channel data"] pub type LeftTxDataR = crate :: FieldReader < u32 > ;
#[doc = "Field `left_tx_data` writer - TX left channel data"] pub type LeftTxDataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - TX left channel data"]
#[inline (always)] pub fn left_tx_data (& self) -> LeftTxDataR { LeftTxDataR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - TX left channel data"]
#[inline (always)] pub fn left_tx_data (& mut self) -> LeftTxDataW < '_ , LeftTxSpec > { LeftTxDataW :: new (self , 0) } }
#[doc = "TX left channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`left_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`left_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LeftTxSpec ; impl crate :: RegisterSpec for LeftTxSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`left_tx::R`](R) reader structure"] impl crate :: Readable for LeftTxSpec { }
#[doc = "`write(|w| ..)` method takes [`left_tx::W`](W) writer structure"] impl crate :: Writable for LeftTxSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LEFT_TX to value 0"] impl crate :: Resettable for LeftTxSpec { } }
#[doc = "RIGHT_TX (rw) register accessor: TX right channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`right_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`right_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@right_tx`] module"]
#[doc (alias = "RIGHT_TX")] pub type RightTx = crate :: Reg < right_tx :: RightTxSpec > ;
#[doc = "TX right channel data"] pub mod right_tx {
#[doc = "Register `RIGHT_TX` reader"] pub type R = crate :: R < RightTxSpec > ;
#[doc = "Register `RIGHT_TX` writer"] pub type W = crate :: W < RightTxSpec > ;
#[doc = "Field `right_tx_data` reader - TX right channel data"] pub type RightTxDataR = crate :: FieldReader < u32 > ;
#[doc = "Field `right_tx_data` writer - TX right channel data"] pub type RightTxDataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - TX right channel data"]
#[inline (always)] pub fn right_tx_data (& self) -> RightTxDataR { RightTxDataR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - TX right channel data"]
#[inline (always)] pub fn right_tx_data (& mut self) -> RightTxDataW < '_ , RightTxSpec > { RightTxDataW :: new (self , 0) } }
#[doc = "TX right channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`right_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`right_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RightTxSpec ; impl crate :: RegisterSpec for RightTxSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`right_tx::R`](R) reader structure"] impl crate :: Readable for RightTxSpec { }
#[doc = "`write(|w| ..)` method takes [`right_tx::W`](W) writer structure"] impl crate :: Writable for RightTxSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RIGHT_TX to value 0"] impl crate :: Resettable for RightTxSpec { } }
#[doc = "LEFT_RX (rw) register accessor: RX left channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`left_rx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`left_rx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@left_rx`] module"]
#[doc (alias = "LEFT_RX")] pub type LeftRx = crate :: Reg < left_rx :: LeftRxSpec > ;
#[doc = "RX left channel data"] pub mod left_rx {
#[doc = "Register `LEFT_RX` reader"] pub type R = crate :: R < LeftRxSpec > ;
#[doc = "Register `LEFT_RX` writer"] pub type W = crate :: W < LeftRxSpec > ;
#[doc = "Field `left_rx_data` reader - RX left channel data"] pub type LeftRxDataR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - RX left channel data"]
#[inline (always)] pub fn left_rx_data (& self) -> LeftRxDataR { LeftRxDataR :: new (self . bits) } } impl W { }
#[doc = "RX left channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`left_rx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`left_rx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LeftRxSpec ; impl crate :: RegisterSpec for LeftRxSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`left_rx::R`](R) reader structure"] impl crate :: Readable for LeftRxSpec { }
#[doc = "`write(|w| ..)` method takes [`left_rx::W`](W) writer structure"] impl crate :: Writable for LeftRxSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LEFT_RX to value 0"] impl crate :: Resettable for LeftRxSpec { } }
#[doc = "RIGHT_RX (rw) register accessor: RX right channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`right_rx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`right_rx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@right_rx`] module"]
#[doc (alias = "RIGHT_RX")] pub type RightRx = crate :: Reg < right_rx :: RightRxSpec > ;
#[doc = "RX right channel data"] pub mod right_rx {
#[doc = "Register `RIGHT_RX` reader"] pub type R = crate :: R < RightRxSpec > ;
#[doc = "Register `RIGHT_RX` writer"] pub type W = crate :: W < RightRxSpec > ;
#[doc = "Field `right_rx_data` reader - RX right channel data"] pub type RightRxDataR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - RX right channel data"]
#[inline (always)] pub fn right_rx_data (& self) -> RightRxDataR { RightRxDataR :: new (self . bits) } } impl W { }
#[doc = "RX right channel data\n\nYou can [`read`](crate::Reg::read) this register and get [`right_rx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`right_rx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RightRxSpec ; impl crate :: RegisterSpec for RightRxSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`right_rx::R`](R) reader structure"] impl crate :: Readable for RightRxSpec { }
#[doc = "`write(|w| ..)` method takes [`right_rx::W`](W) writer structure"] impl crate :: Writable for RightRxSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RIGHT_RX to value 0"] impl crate :: Resettable for RightRxSpec { } }
#[doc = "CT_SET (rw) register accessor: Control set register\n\nYou can [`read`](crate::Reg::read) this register and get [`ct_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ct_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ct_set`] module"]
#[doc (alias = "CT_SET")] pub type CtSet = crate :: Reg < ct_set :: CtSetSpec > ;
#[doc = "Control set register"] pub mod ct_set {
#[doc = "Register `CT_SET` reader"] pub type R = crate :: R < CtSetSpec > ;
#[doc = "Register `CT_SET` writer"] pub type W = crate :: W < CtSetSpec > ;
#[doc = "Field `tx_en` writer - TX enable set"] pub type TxEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rx_en` writer - RX enable set"] pub type RxEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tx_rst` writer - TX reset set"] pub type TxRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rx_rst` writer - RX reset set"] pub type RxRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tx_intr_en` writer - TX interrupt enable set"] pub type TxIntrEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rx_intr_en` writer - RX interrupt enable set"] pub type RxIntrEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `merge_en` writer - Merge enable set"] pub type MergeEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - TX enable set"]
#[inline (always)] pub fn tx_en (& mut self) -> TxEnW < '_ , CtSetSpec > { TxEnW :: new (self , 0) }
#[doc = "Bit 1 - RX enable set"]
#[inline (always)] pub fn rx_en (& mut self) -> RxEnW < '_ , CtSetSpec > { RxEnW :: new (self , 1) }
#[doc = "Bit 2 - TX reset set"]
#[inline (always)] pub fn tx_rst (& mut self) -> TxRstW < '_ , CtSetSpec > { TxRstW :: new (self , 2) }
#[doc = "Bit 3 - RX reset set"]
#[inline (always)] pub fn rx_rst (& mut self) -> RxRstW < '_ , CtSetSpec > { RxRstW :: new (self , 3) }
#[doc = "Bit 4 - TX interrupt enable set"]
#[inline (always)] pub fn tx_intr_en (& mut self) -> TxIntrEnW < '_ , CtSetSpec > { TxIntrEnW :: new (self , 4) }
#[doc = "Bit 5 - RX interrupt enable set"]
#[inline (always)] pub fn rx_intr_en (& mut self) -> RxIntrEnW < '_ , CtSetSpec > { RxIntrEnW :: new (self , 5) }
#[doc = "Bit 6 - Merge enable set"]
#[inline (always)] pub fn merge_en (& mut self) -> MergeEnW < '_ , CtSetSpec > { MergeEnW :: new (self , 6) } }
#[doc = "Control set register\n\nYou can [`read`](crate::Reg::read) this register and get [`ct_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ct_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CtSetSpec ; impl crate :: RegisterSpec for CtSetSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`ct_set::R`](R) reader structure"] impl crate :: Readable for CtSetSpec { }
#[doc = "`write(|w| ..)` method takes [`ct_set::W`](W) writer structure"] impl crate :: Writable for CtSetSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CT_SET to value 0"] impl crate :: Resettable for CtSetSpec { } }
#[doc = "CT_CLR (rw) register accessor: Control clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`ct_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ct_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ct_clr`] module"]
#[doc (alias = "CT_CLR")] pub type CtClr = crate :: Reg < ct_clr :: CtClrSpec > ;
#[doc = "Control clear register"] pub mod ct_clr {
#[doc = "Register `CT_CLR` reader"] pub type R = crate :: R < CtClrSpec > ;
#[doc = "Register `CT_CLR` writer"] pub type W = crate :: W < CtClrSpec > ;
#[doc = "Field `tx_en` writer - TX enable clear"] pub type TxEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rx_en` writer - RX enable clear"] pub type RxEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tx_intr_en` writer - TX interrupt disable"] pub type TxIntrEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rx_intr_en` writer - RX interrupt disable"] pub type RxIntrEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `merge_en` writer - Merge disable"] pub type MergeEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - TX enable clear"]
#[inline (always)] pub fn tx_en (& mut self) -> TxEnW < '_ , CtClrSpec > { TxEnW :: new (self , 0) }
#[doc = "Bit 1 - RX enable clear"]
#[inline (always)] pub fn rx_en (& mut self) -> RxEnW < '_ , CtClrSpec > { RxEnW :: new (self , 1) }
#[doc = "Bit 4 - TX interrupt disable"]
#[inline (always)] pub fn tx_intr_en (& mut self) -> TxIntrEnW < '_ , CtClrSpec > { TxIntrEnW :: new (self , 4) }
#[doc = "Bit 5 - RX interrupt disable"]
#[inline (always)] pub fn rx_intr_en (& mut self) -> RxIntrEnW < '_ , CtClrSpec > { RxIntrEnW :: new (self , 5) }
#[doc = "Bit 6 - Merge disable"]
#[inline (always)] pub fn merge_en (& mut self) -> MergeEnW < '_ , CtClrSpec > { MergeEnW :: new (self , 6) } }
#[doc = "Control clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`ct_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ct_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CtClrSpec ; impl crate :: RegisterSpec for CtClrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`ct_clr::R`](R) reader structure"] impl crate :: Readable for CtClrSpec { }
#[doc = "`write(|w| ..)` method takes [`ct_clr::W`](W) writer structure"] impl crate :: Writable for CtClrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CT_CLR to value 0"] impl crate :: Resettable for CtClrSpec { } }
#[doc = "FIFO_THRESHOLD (rw) register accessor: FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_threshold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_threshold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_threshold`] module"]
#[doc (alias = "FIFO_THRESHOLD")] pub type FifoThreshold = crate :: Reg < fifo_threshold :: FifoThresholdSpec > ;
#[doc = "FIFO threshold register"] pub mod fifo_threshold {
#[doc = "Register `FIFO_THRESHOLD` reader"] pub type R = crate :: R < FifoThresholdSpec > ;
#[doc = "Register `FIFO_THRESHOLD` writer"] pub type W = crate :: W < FifoThresholdSpec > ;
#[doc = "Field `tx_threshold` reader - TX FIFO threshold"] pub type TxThresholdR = crate :: FieldReader ;
#[doc = "Field `tx_threshold` writer - TX FIFO threshold"] pub type TxThresholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ;
#[doc = "Field `rx_threshold` reader - RX FIFO threshold"] pub type RxThresholdR = crate :: FieldReader ;
#[doc = "Field `rx_threshold` writer - RX FIFO threshold"] pub type RxThresholdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - TX FIFO threshold"]
#[inline (always)] pub fn tx_threshold (& self) -> TxThresholdR { TxThresholdR :: new ((self . bits & 0xff) as u8) }
#[doc = "Bits 8:15 - RX FIFO threshold"]
#[inline (always)] pub fn rx_threshold (& self) -> RxThresholdR { RxThresholdR :: new (((self . bits >> 8) & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - TX FIFO threshold"]
#[inline (always)] pub fn tx_threshold (& mut self) -> TxThresholdW < '_ , FifoThresholdSpec > { TxThresholdW :: new (self , 0) }
#[doc = "Bits 8:15 - RX FIFO threshold"]
#[inline (always)] pub fn rx_threshold (& mut self) -> RxThresholdW < '_ , FifoThresholdSpec > { RxThresholdW :: new (self , 8) } }
#[doc = "FIFO threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_threshold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_threshold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FifoThresholdSpec ; impl crate :: RegisterSpec for FifoThresholdSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`fifo_threshold::R`](R) reader structure"] impl crate :: Readable for FifoThresholdSpec { }
#[doc = "`write(|w| ..)` method takes [`fifo_threshold::W`](W) writer structure"] impl crate :: Writable for FifoThresholdSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets FIFO_THRESHOLD to value 0"] impl crate :: Resettable for FifoThresholdSpec { } }
#[doc = "RX_STA (rw) register accessor: RX status register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_sta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_sta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_sta`] module"]
#[doc (alias = "RX_STA")] pub type RxSta = crate :: Reg < rx_sta :: RxStaSpec > ;
#[doc = "RX status register"] pub mod rx_sta {
#[doc = "Register `RX_STA` reader"] pub type R = crate :: R < RxStaSpec > ;
#[doc = "Register `RX_STA` writer"] pub type W = crate :: W < RxStaSpec > ;
#[doc = "Field `left_depth` reader - RX left FIFO depth"] pub type LeftDepthR = crate :: FieldReader ;
#[doc = "Field `right_depth` reader - RX right FIFO depth"] pub type RightDepthR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - RX left FIFO depth"]
#[inline (always)] pub fn left_depth (& self) -> LeftDepthR { LeftDepthR :: new ((self . bits & 0xff) as u8) }
#[doc = "Bits 8:15 - RX right FIFO depth"]
#[inline (always)] pub fn right_depth (& self) -> RightDepthR { RightDepthR :: new (((self . bits >> 8) & 0xff) as u8) } } impl W { }
#[doc = "RX status register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_sta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_sta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RxStaSpec ; impl crate :: RegisterSpec for RxStaSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rx_sta::R`](R) reader structure"] impl crate :: Readable for RxStaSpec { }
#[doc = "`write(|w| ..)` method takes [`rx_sta::W`](W) writer structure"] impl crate :: Writable for RxStaSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RX_STA to value 0"] impl crate :: Resettable for RxStaSpec { } }
#[doc = "TX_STA (rw) register accessor: TX status register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_sta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_sta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_sta`] module"]
#[doc (alias = "TX_STA")] pub type TxSta = crate :: Reg < tx_sta :: TxStaSpec > ;
#[doc = "TX status register"] pub mod tx_sta {
#[doc = "Register `TX_STA` reader"] pub type R = crate :: R < TxStaSpec > ;
#[doc = "Register `TX_STA` writer"] pub type W = crate :: W < TxStaSpec > ;
#[doc = "Field `left_depth` reader - TX left FIFO depth"] pub type LeftDepthR = crate :: FieldReader ;
#[doc = "Field `right_depth` reader - TX right FIFO depth"] pub type RightDepthR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:7 - TX left FIFO depth"]
#[inline (always)] pub fn left_depth (& self) -> LeftDepthR { LeftDepthR :: new ((self . bits & 0xff) as u8) }
#[doc = "Bits 8:15 - TX right FIFO depth"]
#[inline (always)] pub fn right_depth (& self) -> RightDepthR { RightDepthR :: new (((self . bits >> 8) & 0xff) as u8) } } impl W { }
#[doc = "TX status register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_sta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_sta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TxStaSpec ; impl crate :: RegisterSpec for TxStaSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tx_sta::R`](R) reader structure"] impl crate :: Readable for TxStaSpec { }
#[doc = "`write(|w| ..)` method takes [`tx_sta::W`](W) writer structure"] impl crate :: Writable for TxStaSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TX_STA to value 0"] impl crate :: Resettable for TxStaSpec { } }
#[doc = "DATA_WIDTH_SET (rw) register accessor: Data width register\n\nYou can [`read`](crate::Reg::read) this register and get [`data_width_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_width_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_width_set`] module"]
#[doc (alias = "DATA_WIDTH_SET")] pub type DataWidthSet = crate :: Reg < data_width_set :: DataWidthSetSpec > ;
#[doc = "Data width register"] pub mod data_width_set {
#[doc = "Register `DATA_WIDTH_SET` reader"] pub type R = crate :: R < DataWidthSetSpec > ;
#[doc = "Register `DATA_WIDTH_SET` writer"] pub type W = crate :: W < DataWidthSetSpec > ;
#[doc = "Field `tx_mode` reader - TX data width mode"] pub type TxModeR = crate :: FieldReader ;
#[doc = "Field `tx_mode` writer - TX data width mode"] pub type TxModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `rx_mode` reader - RX data width mode"] pub type RxModeR = crate :: FieldReader ;
#[doc = "Field `rx_mode` writer - RX data width mode"] pub type RxModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - TX data width mode"]
#[inline (always)] pub fn tx_mode (& self) -> TxModeR { TxModeR :: new ((self . bits & 7) as u8) }
#[doc = "Bits 8:10 - RX data width mode"]
#[inline (always)] pub fn rx_mode (& self) -> RxModeR { RxModeR :: new (((self . bits >> 8) & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - TX data width mode"]
#[inline (always)] pub fn tx_mode (& mut self) -> TxModeW < '_ , DataWidthSetSpec > { TxModeW :: new (self , 0) }
#[doc = "Bits 8:10 - RX data width mode"]
#[inline (always)] pub fn rx_mode (& mut self) -> RxModeW < '_ , DataWidthSetSpec > { RxModeW :: new (self , 8) } }
#[doc = "Data width register\n\nYou can [`read`](crate::Reg::read) this register and get [`data_width_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data_width_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DataWidthSetSpec ; impl crate :: RegisterSpec for DataWidthSetSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`data_width_set::R`](R) reader structure"] impl crate :: Readable for DataWidthSetSpec { }
#[doc = "`write(|w| ..)` method takes [`data_width_set::W`](W) writer structure"] impl crate :: Writable for DataWidthSetSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DATA_WIDTH_SET to value 0"] impl crate :: Resettable for DataWidthSetSpec { } }
#[doc = "SIGNED_EXT (rw) register accessor: Signed extension enable\n\nYou can [`read`](crate::Reg::read) this register and get [`signed_ext::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`signed_ext::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@signed_ext`] module"]
#[doc (alias = "SIGNED_EXT")] pub type SignedExt = crate :: Reg < signed_ext :: SignedExtSpec > ;
#[doc = "Signed extension enable"] pub mod signed_ext {
#[doc = "Register `SIGNED_EXT` reader"] pub type R = crate :: R < SignedExtSpec > ;
#[doc = "Register `SIGNED_EXT` writer"] pub type W = crate :: W < SignedExtSpec > ;
#[doc = "Field `signed_ext_en` reader - Signed extension enable"] pub type SignedExtEnR = crate :: BitReader ;
#[doc = "Field `signed_ext_en` writer - Signed extension enable"] pub type SignedExtEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Signed extension enable"]
#[inline (always)] pub fn signed_ext_en (& self) -> SignedExtEnR { SignedExtEnR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Signed extension enable"]
#[inline (always)] pub fn signed_ext_en (& mut self) -> SignedExtEnW < '_ , SignedExtSpec > { SignedExtEnW :: new (self , 0) } }
#[doc = "Signed extension enable\n\nYou can [`read`](crate::Reg::read) this register and get [`signed_ext::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`signed_ext::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SignedExtSpec ; impl crate :: RegisterSpec for SignedExtSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`signed_ext::R`](R) reader structure"] impl crate :: Readable for SignedExtSpec { }
#[doc = "`write(|w| ..)` method takes [`signed_ext::W`](W) writer structure"] impl crate :: Writable for SignedExtSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SIGNED_EXT to value 0"] impl crate :: Resettable for SignedExtSpec { } }
#[doc = "INTMASK (rw) register accessor: Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`intmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intmask`] module"]
#[doc (alias = "INTMASK")] pub type Intmask = crate :: Reg < intmask :: IntmaskSpec > ;
#[doc = "Interrupt mask register"] pub mod intmask {
#[doc = "Register `INTMASK` reader"] pub type R = crate :: R < IntmaskSpec > ;
#[doc = "Register `INTMASK` writer"] pub type W = crate :: W < IntmaskSpec > ;
#[doc = "Field `rx_int_mask` reader - RX interrupt mask"] pub type RxIntMaskR = crate :: BitReader ;
#[doc = "Field `rx_int_mask` writer - RX interrupt mask"] pub type RxIntMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tx_int_mask` reader - TX interrupt mask"] pub type TxIntMaskR = crate :: BitReader ;
#[doc = "Field `tx_int_mask` writer - TX interrupt mask"] pub type TxIntMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rx_overflow_mask` reader - RX overflow mask"] pub type RxOverflowMaskR = crate :: BitReader ;
#[doc = "Field `rx_overflow_mask` writer - RX overflow mask"] pub type RxOverflowMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tx_underflow_mask` reader - TX underflow mask"] pub type TxUnderflowMaskR = crate :: BitReader ;
#[doc = "Field `tx_underflow_mask` writer - TX underflow mask"] pub type TxUnderflowMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - RX interrupt mask"]
#[inline (always)] pub fn rx_int_mask (& self) -> RxIntMaskR { RxIntMaskR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TX interrupt mask"]
#[inline (always)] pub fn tx_int_mask (& self) -> TxIntMaskR { TxIntMaskR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - RX overflow mask"]
#[inline (always)] pub fn rx_overflow_mask (& self) -> RxOverflowMaskR { RxOverflowMaskR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - TX underflow mask"]
#[inline (always)] pub fn tx_underflow_mask (& self) -> TxUnderflowMaskR { TxUnderflowMaskR :: new (((self . bits >> 3) & 1) != 0) } } impl W {
#[doc = "Bit 0 - RX interrupt mask"]
#[inline (always)] pub fn rx_int_mask (& mut self) -> RxIntMaskW < '_ , IntmaskSpec > { RxIntMaskW :: new (self , 0) }
#[doc = "Bit 1 - TX interrupt mask"]
#[inline (always)] pub fn tx_int_mask (& mut self) -> TxIntMaskW < '_ , IntmaskSpec > { TxIntMaskW :: new (self , 1) }
#[doc = "Bit 2 - RX overflow mask"]
#[inline (always)] pub fn rx_overflow_mask (& mut self) -> RxOverflowMaskW < '_ , IntmaskSpec > { RxOverflowMaskW :: new (self , 2) }
#[doc = "Bit 3 - TX underflow mask"]
#[inline (always)] pub fn tx_underflow_mask (& mut self) -> TxUnderflowMaskW < '_ , IntmaskSpec > { TxUnderflowMaskW :: new (self , 3) } }
#[doc = "Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`intmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntmaskSpec ; impl crate :: RegisterSpec for IntmaskSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`intmask::R`](R) reader structure"] impl crate :: Readable for IntmaskSpec { }
#[doc = "`write(|w| ..)` method takes [`intmask::W`](W) writer structure"] impl crate :: Writable for IntmaskSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INTMASK to value 0"] impl crate :: Resettable for IntmaskSpec { } }
#[doc = "I2S_CRG (rw) register accessor: I2S clock/reset generator\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_crg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_crg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_crg`] module"]
#[doc (alias = "I2S_CRG")] pub type I2sCrg = crate :: Reg < i2s_crg :: I2sCrgSpec > ;
#[doc = "I2S clock/reset generator"] pub mod i2s_crg {
#[doc = "Register `I2S_CRG` reader"] pub type R = crate :: R < I2sCrgSpec > ;
#[doc = "Register `I2S_CRG` writer"] pub type W = crate :: W < I2sCrgSpec > ;
#[doc = "Field `bclk_div` reader - BCLK divider"] pub type BclkDivR = crate :: FieldReader ;
#[doc = "Field `bclk_div` writer - BCLK divider"] pub type BclkDivW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ;
#[doc = "Field `clk_en` reader - Clock enable"] pub type ClkEnR = crate :: BitReader ;
#[doc = "Field `clk_en` writer - Clock enable"] pub type ClkEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clk_sel` reader - Clock source select"] pub type ClkSelR = crate :: BitReader ;
#[doc = "Field `clk_sel` writer - Clock source select"] pub type ClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:7 - BCLK divider"]
#[inline (always)] pub fn bclk_div (& self) -> BclkDivR { BclkDivR :: new ((self . bits & 0xff) as u8) }
#[doc = "Bit 8 - Clock enable"]
#[inline (always)] pub fn clk_en (& self) -> ClkEnR { ClkEnR :: new (((self . bits >> 8) & 1) != 0) }
#[doc = "Bit 9 - Clock source select"]
#[inline (always)] pub fn clk_sel (& self) -> ClkSelR { ClkSelR :: new (((self . bits >> 9) & 1) != 0) } } impl W {
#[doc = "Bits 0:7 - BCLK divider"]
#[inline (always)] pub fn bclk_div (& mut self) -> BclkDivW < '_ , I2sCrgSpec > { BclkDivW :: new (self , 0) }
#[doc = "Bit 8 - Clock enable"]
#[inline (always)] pub fn clk_en (& mut self) -> ClkEnW < '_ , I2sCrgSpec > { ClkEnW :: new (self , 8) }
#[doc = "Bit 9 - Clock source select"]
#[inline (always)] pub fn clk_sel (& mut self) -> ClkSelW < '_ , I2sCrgSpec > { ClkSelW :: new (self , 9) } }
#[doc = "I2S clock/reset generator\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_crg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_crg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2sCrgSpec ; impl crate :: RegisterSpec for I2sCrgSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2s_crg::R`](R) reader structure"] impl crate :: Readable for I2sCrgSpec { }
#[doc = "`write(|w| ..)` method takes [`i2s_crg::W`](W) writer structure"] impl crate :: Writable for I2sCrgSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2S_CRG to value 0"] impl crate :: Resettable for I2sCrgSpec { } }
#[doc = "I2S_BCLK_DIV_NUM (rw) register accessor: BCLK divider number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_bclk_div_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_bclk_div_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_bclk_div_num`] module"]
#[doc (alias = "I2S_BCLK_DIV_NUM")] pub type I2sBclkDivNum = crate :: Reg < i2s_bclk_div_num :: I2sBclkDivNumSpec > ;
#[doc = "BCLK divider number"] pub mod i2s_bclk_div_num {
#[doc = "Register `I2S_BCLK_DIV_NUM` reader"] pub type R = crate :: R < I2sBclkDivNumSpec > ;
#[doc = "Register `I2S_BCLK_DIV_NUM` writer"] pub type W = crate :: W < I2sBclkDivNumSpec > ;
#[doc = "Field `bclk_div_num` reader - BCLK divider number"] pub type BclkDivNumR = crate :: FieldReader ;
#[doc = "Field `bclk_div_num` writer - BCLK divider number"] pub type BclkDivNumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R {
#[doc = "Bits 0:6 - BCLK divider number"]
#[inline (always)] pub fn bclk_div_num (& self) -> BclkDivNumR { BclkDivNumR :: new ((self . bits & 0x7f) as u8) } } impl W {
#[doc = "Bits 0:6 - BCLK divider number"]
#[inline (always)] pub fn bclk_div_num (& mut self) -> BclkDivNumW < '_ , I2sBclkDivNumSpec > { BclkDivNumW :: new (self , 0) } }
#[doc = "BCLK divider number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_bclk_div_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_bclk_div_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2sBclkDivNumSpec ; impl crate :: RegisterSpec for I2sBclkDivNumSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2s_bclk_div_num::R`](R) reader structure"] impl crate :: Readable for I2sBclkDivNumSpec { }
#[doc = "`write(|w| ..)` method takes [`i2s_bclk_div_num::W`](W) writer structure"] impl crate :: Writable for I2sBclkDivNumSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2S_BCLK_DIV_NUM to value 0"] impl crate :: Resettable for I2sBclkDivNumSpec { } }
#[doc = "I2S_FS_DIV_NUM (rw) register accessor: FS divider number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_fs_div_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_fs_div_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_fs_div_num`] module"]
#[doc (alias = "I2S_FS_DIV_NUM")] pub type I2sFsDivNum = crate :: Reg < i2s_fs_div_num :: I2sFsDivNumSpec > ;
#[doc = "FS divider number"] pub mod i2s_fs_div_num {
#[doc = "Register `I2S_FS_DIV_NUM` reader"] pub type R = crate :: R < I2sFsDivNumSpec > ;
#[doc = "Register `I2S_FS_DIV_NUM` writer"] pub type W = crate :: W < I2sFsDivNumSpec > ;
#[doc = "Field `fs_div_num` reader - FS divider number"] pub type FsDivNumR = crate :: FieldReader < u16 > ;
#[doc = "Field `fs_div_num` writer - FS divider number"] pub type FsDivNumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; impl R {
#[doc = "Bits 0:9 - FS divider number"]
#[inline (always)] pub fn fs_div_num (& self) -> FsDivNumR { FsDivNumR :: new ((self . bits & 0x03ff) as u16) } } impl W {
#[doc = "Bits 0:9 - FS divider number"]
#[inline (always)] pub fn fs_div_num (& mut self) -> FsDivNumW < '_ , I2sFsDivNumSpec > { FsDivNumW :: new (self , 0) } }
#[doc = "FS divider number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_fs_div_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_fs_div_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2sFsDivNumSpec ; impl crate :: RegisterSpec for I2sFsDivNumSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2s_fs_div_num::R`](R) reader structure"] impl crate :: Readable for I2sFsDivNumSpec { }
#[doc = "`write(|w| ..)` method takes [`i2s_fs_div_num::W`](W) writer structure"] impl crate :: Writable for I2sFsDivNumSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2S_FS_DIV_NUM to value 0"] impl crate :: Resettable for I2sFsDivNumSpec { } }
#[doc = "I2S_FS_DIV_RATIO_NUM (rw) register accessor: FS divider ratio number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_fs_div_ratio_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_fs_div_ratio_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_fs_div_ratio_num`] module"]
#[doc (alias = "I2S_FS_DIV_RATIO_NUM")] pub type I2sFsDivRatioNum = crate :: Reg < i2s_fs_div_ratio_num :: I2sFsDivRatioNumSpec > ;
#[doc = "FS divider ratio number"] pub mod i2s_fs_div_ratio_num {
#[doc = "Register `I2S_FS_DIV_RATIO_NUM` reader"] pub type R = crate :: R < I2sFsDivRatioNumSpec > ;
#[doc = "Register `I2S_FS_DIV_RATIO_NUM` writer"] pub type W = crate :: W < I2sFsDivRatioNumSpec > ;
#[doc = "Field `fs_div_ratio_num` reader - FS divider ratio number"] pub type FsDivRatioNumR = crate :: FieldReader < u16 > ;
#[doc = "Field `fs_div_ratio_num` writer - FS divider ratio number"] pub type FsDivRatioNumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 11 , u16 > ; impl R {
#[doc = "Bits 0:10 - FS divider ratio number"]
#[inline (always)] pub fn fs_div_ratio_num (& self) -> FsDivRatioNumR { FsDivRatioNumR :: new ((self . bits & 0x07ff) as u16) } } impl W {
#[doc = "Bits 0:10 - FS divider ratio number"]
#[inline (always)] pub fn fs_div_ratio_num (& mut self) -> FsDivRatioNumW < '_ , I2sFsDivRatioNumSpec > { FsDivRatioNumW :: new (self , 0) } }
#[doc = "FS divider ratio number\n\nYou can [`read`](crate::Reg::read) this register and get [`i2s_fs_div_ratio_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2s_fs_div_ratio_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct I2sFsDivRatioNumSpec ; impl crate :: RegisterSpec for I2sFsDivRatioNumSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`i2s_fs_div_ratio_num::R`](R) reader structure"] impl crate :: Readable for I2sFsDivRatioNumSpec { }
#[doc = "`write(|w| ..)` method takes [`i2s_fs_div_ratio_num::W`](W) writer structure"] impl crate :: Writable for I2sFsDivRatioNumSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets I2S_FS_DIV_RATIO_NUM to value 0"] impl crate :: Resettable for I2sFsDivRatioNumSpec { } } }
#[doc = "Low-speed ADC controller (12-bit SAR, 6 channels, v154)"] pub type Lsadc = crate :: Periph < lsadc :: RegisterBlock , 0x4400_c000 > ; impl core :: fmt :: Debug for Lsadc { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Lsadc") . finish () } }
#[doc = "Low-speed ADC controller (12-bit SAR, 6 channels, v154)"] pub mod lsadc {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { lsadc_ctrl_0 : LsadcCtrl0 , lsadc_ctrl_1 : LsadcCtrl1 , lsadc_ctrl_2 : LsadcCtrl2 , lsadc_ctrl_3 : LsadcCtrl3 , lsadc_ctrl_4 : LsadcCtrl4 , lsadc_ctrl_6 : LsadcCtrl6 , lsadc_ctrl_7 : LsadcCtrl7 , _reserved7 : [u8 ; 0xe4] , lsadc_fifo_data : LsadcFifoData , _reserved8 : [u8 ; 0xfc] , cfg_cic_filter_en : CfgCicFilterEn , cfg_cic_osr : CfgCicOsr , cfg_data_sel : CfgDataSel , cfg_offset : CfgOffset , cfg_gain : CfgGain , } impl RegisterBlock {
#[doc = "0x00 - ADC control register 0"]
#[inline (always)] pub const fn lsadc_ctrl_0 (& self) -> & LsadcCtrl0 { & self . lsadc_ctrl_0 }
#[doc = "0x04 - ADC control register 1"]
#[inline (always)] pub const fn lsadc_ctrl_1 (& self) -> & LsadcCtrl1 { & self . lsadc_ctrl_1 }
#[doc = "0x08 - ADC control register 2"]
#[inline (always)] pub const fn lsadc_ctrl_2 (& self) -> & LsadcCtrl2 { & self . lsadc_ctrl_2 }
#[doc = "0x0c - ADC control register 3"]
#[inline (always)] pub const fn lsadc_ctrl_3 (& self) -> & LsadcCtrl3 { & self . lsadc_ctrl_3 }
#[doc = "0x10 - ADC control register 4"]
#[inline (always)] pub const fn lsadc_ctrl_4 (& self) -> & LsadcCtrl4 { & self . lsadc_ctrl_4 }
#[doc = "0x14 - ADC scan start/stop register"]
#[inline (always)] pub const fn lsadc_ctrl_6 (& self) -> & LsadcCtrl6 { & self . lsadc_ctrl_6 }
#[doc = "0x18 - ADC enable register"]
#[inline (always)] pub const fn lsadc_ctrl_7 (& self) -> & LsadcCtrl7 { & self . lsadc_ctrl_7 }
#[doc = "0x100 - ADC FIFO data register"]
#[inline (always)] pub const fn lsadc_fifo_data (& self) -> & LsadcFifoData { & self . lsadc_fifo_data }
#[doc = "0x200 - CIC filter enable register"]
#[inline (always)] pub const fn cfg_cic_filter_en (& self) -> & CfgCicFilterEn { & self . cfg_cic_filter_en }
#[doc = "0x204 - CIC oversampling ratio register"]
#[inline (always)] pub const fn cfg_cic_osr (& self) -> & CfgCicOsr { & self . cfg_cic_osr }
#[doc = "0x208 - Data select register"]
#[inline (always)] pub const fn cfg_data_sel (& self) -> & CfgDataSel { & self . cfg_data_sel }
#[doc = "0x20c - Offset register"]
#[inline (always)] pub const fn cfg_offset (& self) -> & CfgOffset { & self . cfg_offset }
#[doc = "0x210 - Gain register"]
#[inline (always)] pub const fn cfg_gain (& self) -> & CfgGain { & self . cfg_gain } }
#[doc = "LSADC_CTRL_0 (rw) register accessor: ADC control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_0`] module"]
#[doc (alias = "LSADC_CTRL_0")] pub type LsadcCtrl0 = crate :: Reg < lsadc_ctrl_0 :: LsadcCtrl0Spec > ;
#[doc = "ADC control register 0"] pub mod lsadc_ctrl_0 {
#[doc = "Register `LSADC_CTRL_0` reader"] pub type R = crate :: R < LsadcCtrl0Spec > ;
#[doc = "Register `LSADC_CTRL_0` writer"] pub type W = crate :: W < LsadcCtrl0Spec > ;
#[doc = "Field `lsadc_ctrl_0` reader - ADC control 0 configuration"] pub type LsadcCtrl0R = crate :: FieldReader < u32 > ;
#[doc = "Field `lsadc_ctrl_0` writer - ADC control 0 configuration"] pub type LsadcCtrl0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - ADC control 0 configuration"]
#[inline (always)] pub fn lsadc_ctrl_0 (& self) -> LsadcCtrl0R { LsadcCtrl0R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - ADC control 0 configuration"]
#[inline (always)] pub fn lsadc_ctrl_0 (& mut self) -> LsadcCtrl0W < '_ , LsadcCtrl0Spec > { LsadcCtrl0W :: new (self , 0) } }
#[doc = "ADC control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LsadcCtrl0Spec ; impl crate :: RegisterSpec for LsadcCtrl0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lsadc_ctrl_0::R`](R) reader structure"] impl crate :: Readable for LsadcCtrl0Spec { }
#[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_0::W`](W) writer structure"] impl crate :: Writable for LsadcCtrl0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LSADC_CTRL_0 to value 0"] impl crate :: Resettable for LsadcCtrl0Spec { } }
#[doc = "LSADC_CTRL_1 (rw) register accessor: ADC control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_1`] module"]
#[doc (alias = "LSADC_CTRL_1")] pub type LsadcCtrl1 = crate :: Reg < lsadc_ctrl_1 :: LsadcCtrl1Spec > ;
#[doc = "ADC control register 1"] pub mod lsadc_ctrl_1 {
#[doc = "Register `LSADC_CTRL_1` reader"] pub type R = crate :: R < LsadcCtrl1Spec > ;
#[doc = "Register `LSADC_CTRL_1` writer"] pub type W = crate :: W < LsadcCtrl1Spec > ;
#[doc = "Field `equ_model_sel` reader - Equal model select (6-bit)"] pub type EquModelSelR = crate :: FieldReader ;
#[doc = "Field `equ_model_sel` writer - Equal model select (6-bit)"] pub type EquModelSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ;
#[doc = "Field `sample_cnt` reader - Sample count"] pub type SampleCntR = crate :: FieldReader ;
#[doc = "Field `sample_cnt` writer - Sample count"] pub type SampleCntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ;
#[doc = "Field `start_cnt` reader - Start count"] pub type StartCntR = crate :: FieldReader ;
#[doc = "Field `start_cnt` writer - Start count"] pub type StartCntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ;
#[doc = "Field `cast_cnt` reader - Cast count"] pub type CastCntR = crate :: FieldReader ;
#[doc = "Field `cast_cnt` writer - Cast count"] pub type CastCntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R {
#[doc = "Bits 1:6 - Equal model select (6-bit)"]
#[inline (always)] pub fn equ_model_sel (& self) -> EquModelSelR { EquModelSelR :: new (((self . bits >> 1) & 0x3f) as u8) }
#[doc = "Bits 8:11 - Sample count"]
#[inline (always)] pub fn sample_cnt (& self) -> SampleCntR { SampleCntR :: new (((self . bits >> 8) & 0x0f) as u8) }
#[doc = "Bits 16:19 - Start count"]
#[inline (always)] pub fn start_cnt (& self) -> StartCntR { StartCntR :: new (((self . bits >> 16) & 0x0f) as u8) }
#[doc = "Bits 24:27 - Cast count"]
#[inline (always)] pub fn cast_cnt (& self) -> CastCntR { CastCntR :: new (((self . bits >> 24) & 0x0f) as u8) } } impl W {
#[doc = "Bits 1:6 - Equal model select (6-bit)"]
#[inline (always)] pub fn equ_model_sel (& mut self) -> EquModelSelW < '_ , LsadcCtrl1Spec > { EquModelSelW :: new (self , 1) }
#[doc = "Bits 8:11 - Sample count"]
#[inline (always)] pub fn sample_cnt (& mut self) -> SampleCntW < '_ , LsadcCtrl1Spec > { SampleCntW :: new (self , 8) }
#[doc = "Bits 16:19 - Start count"]
#[inline (always)] pub fn start_cnt (& mut self) -> StartCntW < '_ , LsadcCtrl1Spec > { StartCntW :: new (self , 16) }
#[doc = "Bits 24:27 - Cast count"]
#[inline (always)] pub fn cast_cnt (& mut self) -> CastCntW < '_ , LsadcCtrl1Spec > { CastCntW :: new (self , 24) } }
#[doc = "ADC control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LsadcCtrl1Spec ; impl crate :: RegisterSpec for LsadcCtrl1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lsadc_ctrl_1::R`](R) reader structure"] impl crate :: Readable for LsadcCtrl1Spec { }
#[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_1::W`](W) writer structure"] impl crate :: Writable for LsadcCtrl1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LSADC_CTRL_1 to value 0"] impl crate :: Resettable for LsadcCtrl1Spec { } }
#[doc = "LSADC_CTRL_2 (rw) register accessor: ADC control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_2`] module"]
#[doc (alias = "LSADC_CTRL_2")] pub type LsadcCtrl2 = crate :: Reg < lsadc_ctrl_2 :: LsadcCtrl2Spec > ;
#[doc = "ADC control register 2"] pub mod lsadc_ctrl_2 {
#[doc = "Register `LSADC_CTRL_2` reader"] pub type R = crate :: R < LsadcCtrl2Spec > ;
#[doc = "Register `LSADC_CTRL_2` writer"] pub type W = crate :: W < LsadcCtrl2Spec > ;
#[doc = "Field `lsadc_ctrl_2` reader - ADC control 2 configuration"] pub type LsadcCtrl2R = crate :: FieldReader < u32 > ;
#[doc = "Field `lsadc_ctrl_2` writer - ADC control 2 configuration"] pub type LsadcCtrl2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - ADC control 2 configuration"]
#[inline (always)] pub fn lsadc_ctrl_2 (& self) -> LsadcCtrl2R { LsadcCtrl2R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - ADC control 2 configuration"]
#[inline (always)] pub fn lsadc_ctrl_2 (& mut self) -> LsadcCtrl2W < '_ , LsadcCtrl2Spec > { LsadcCtrl2W :: new (self , 0) } }
#[doc = "ADC control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LsadcCtrl2Spec ; impl crate :: RegisterSpec for LsadcCtrl2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lsadc_ctrl_2::R`](R) reader structure"] impl crate :: Readable for LsadcCtrl2Spec { }
#[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_2::W`](W) writer structure"] impl crate :: Writable for LsadcCtrl2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LSADC_CTRL_2 to value 0"] impl crate :: Resettable for LsadcCtrl2Spec { } }
#[doc = "LSADC_CTRL_3 (rw) register accessor: ADC control register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_3`] module"]
#[doc (alias = "LSADC_CTRL_3")] pub type LsadcCtrl3 = crate :: Reg < lsadc_ctrl_3 :: LsadcCtrl3Spec > ;
#[doc = "ADC control register 3"] pub mod lsadc_ctrl_3 {
#[doc = "Register `LSADC_CTRL_3` reader"] pub type R = crate :: R < LsadcCtrl3Spec > ;
#[doc = "Register `LSADC_CTRL_3` writer"] pub type W = crate :: W < LsadcCtrl3Spec > ;
#[doc = "Field `lsadc_ctrl_3` reader - ADC control 3 configuration"] pub type LsadcCtrl3R = crate :: FieldReader < u32 > ;
#[doc = "Field `lsadc_ctrl_3` writer - ADC control 3 configuration"] pub type LsadcCtrl3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - ADC control 3 configuration"]
#[inline (always)] pub fn lsadc_ctrl_3 (& self) -> LsadcCtrl3R { LsadcCtrl3R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - ADC control 3 configuration"]
#[inline (always)] pub fn lsadc_ctrl_3 (& mut self) -> LsadcCtrl3W < '_ , LsadcCtrl3Spec > { LsadcCtrl3W :: new (self , 0) } }
#[doc = "ADC control register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LsadcCtrl3Spec ; impl crate :: RegisterSpec for LsadcCtrl3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lsadc_ctrl_3::R`](R) reader structure"] impl crate :: Readable for LsadcCtrl3Spec { }
#[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_3::W`](W) writer structure"] impl crate :: Writable for LsadcCtrl3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LSADC_CTRL_3 to value 0"] impl crate :: Resettable for LsadcCtrl3Spec { } }
#[doc = "LSADC_CTRL_4 (rw) register accessor: ADC control register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_4`] module"]
#[doc (alias = "LSADC_CTRL_4")] pub type LsadcCtrl4 = crate :: Reg < lsadc_ctrl_4 :: LsadcCtrl4Spec > ;
#[doc = "ADC control register 4"] pub mod lsadc_ctrl_4 {
#[doc = "Register `LSADC_CTRL_4` reader"] pub type R = crate :: R < LsadcCtrl4Spec > ;
#[doc = "Register `LSADC_CTRL_4` writer"] pub type W = crate :: W < LsadcCtrl4Spec > ;
#[doc = "Field `lsadc_ctrl_4` reader - ADC control 4 configuration"] pub type LsadcCtrl4R = crate :: FieldReader < u32 > ;
#[doc = "Field `lsadc_ctrl_4` writer - ADC control 4 configuration"] pub type LsadcCtrl4W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - ADC control 4 configuration"]
#[inline (always)] pub fn lsadc_ctrl_4 (& self) -> LsadcCtrl4R { LsadcCtrl4R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - ADC control 4 configuration"]
#[inline (always)] pub fn lsadc_ctrl_4 (& mut self) -> LsadcCtrl4W < '_ , LsadcCtrl4Spec > { LsadcCtrl4W :: new (self , 0) } }
#[doc = "ADC control register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LsadcCtrl4Spec ; impl crate :: RegisterSpec for LsadcCtrl4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lsadc_ctrl_4::R`](R) reader structure"] impl crate :: Readable for LsadcCtrl4Spec { }
#[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_4::W`](W) writer structure"] impl crate :: Writable for LsadcCtrl4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LSADC_CTRL_4 to value 0"] impl crate :: Resettable for LsadcCtrl4Spec { } }
#[doc = "LSADC_CTRL_6 (rw) register accessor: ADC scan start/stop register\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_6`] module"]
#[doc (alias = "LSADC_CTRL_6")] pub type LsadcCtrl6 = crate :: Reg < lsadc_ctrl_6 :: LsadcCtrl6Spec > ;
#[doc = "ADC scan start/stop register"] pub mod lsadc_ctrl_6 {
#[doc = "Register `LSADC_CTRL_6` reader"] pub type R = crate :: R < LsadcCtrl6Spec > ;
#[doc = "Register `LSADC_CTRL_6` writer"] pub type W = crate :: W < LsadcCtrl6Spec > ;
#[doc = "Field `lsadc_start` writer - Start ADC scan: 1=start"] pub type LsadcStartW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `lsadc_stop` writer - Stop ADC scan: 1=stop"] pub type LsadcStopW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Start ADC scan: 1=start"]
#[inline (always)] pub fn lsadc_start (& mut self) -> LsadcStartW < '_ , LsadcCtrl6Spec > { LsadcStartW :: new (self , 0) }
#[doc = "Bit 1 - Stop ADC scan: 1=stop"]
#[inline (always)] pub fn lsadc_stop (& mut self) -> LsadcStopW < '_ , LsadcCtrl6Spec > { LsadcStopW :: new (self , 1) } }
#[doc = "ADC scan start/stop register\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LsadcCtrl6Spec ; impl crate :: RegisterSpec for LsadcCtrl6Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lsadc_ctrl_6::R`](R) reader structure"] impl crate :: Readable for LsadcCtrl6Spec { }
#[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_6::W`](W) writer structure"] impl crate :: Writable for LsadcCtrl6Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LSADC_CTRL_6 to value 0"] impl crate :: Resettable for LsadcCtrl6Spec { } }
#[doc = "LSADC_CTRL_7 (rw) register accessor: ADC enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_ctrl_7`] module"]
#[doc (alias = "LSADC_CTRL_7")] pub type LsadcCtrl7 = crate :: Reg < lsadc_ctrl_7 :: LsadcCtrl7Spec > ;
#[doc = "ADC enable register"] pub mod lsadc_ctrl_7 {
#[doc = "Register `LSADC_CTRL_7` reader"] pub type R = crate :: R < LsadcCtrl7Spec > ;
#[doc = "Register `LSADC_CTRL_7` writer"] pub type W = crate :: W < LsadcCtrl7Spec > ;
#[doc = "Field `da_lsadc_rstn` reader - ADC reset (active low)"] pub type DaLsadcRstnR = crate :: BitReader ;
#[doc = "Field `da_lsadc_rstn` writer - ADC reset (active low)"] pub type DaLsadcRstnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `da_lsadc_en` reader - ADC enable (16-bit, one per channel)"] pub type DaLsadcEnR = crate :: FieldReader < u16 > ;
#[doc = "Field `da_lsadc_en` writer - ADC enable (16-bit, one per channel)"] pub type DaLsadcEnW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bit 0 - ADC reset (active low)"]
#[inline (always)] pub fn da_lsadc_rstn (& self) -> DaLsadcRstnR { DaLsadcRstnR :: new ((self . bits & 1) != 0) }
#[doc = "Bits 16:31 - ADC enable (16-bit, one per channel)"]
#[inline (always)] pub fn da_lsadc_en (& self) -> DaLsadcEnR { DaLsadcEnR :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W {
#[doc = "Bit 0 - ADC reset (active low)"]
#[inline (always)] pub fn da_lsadc_rstn (& mut self) -> DaLsadcRstnW < '_ , LsadcCtrl7Spec > { DaLsadcRstnW :: new (self , 0) }
#[doc = "Bits 16:31 - ADC enable (16-bit, one per channel)"]
#[inline (always)] pub fn da_lsadc_en (& mut self) -> DaLsadcEnW < '_ , LsadcCtrl7Spec > { DaLsadcEnW :: new (self , 16) } }
#[doc = "ADC enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_ctrl_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_ctrl_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LsadcCtrl7Spec ; impl crate :: RegisterSpec for LsadcCtrl7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lsadc_ctrl_7::R`](R) reader structure"] impl crate :: Readable for LsadcCtrl7Spec { }
#[doc = "`write(|w| ..)` method takes [`lsadc_ctrl_7::W`](W) writer structure"] impl crate :: Writable for LsadcCtrl7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LSADC_CTRL_7 to value 0"] impl crate :: Resettable for LsadcCtrl7Spec { } }
#[doc = "LSADC_FIFO_DATA (rw) register accessor: ADC FIFO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_fifo_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_fifo_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsadc_fifo_data`] module"]
#[doc (alias = "LSADC_FIFO_DATA")] pub type LsadcFifoData = crate :: Reg < lsadc_fifo_data :: LsadcFifoDataSpec > ;
#[doc = "ADC FIFO data register"] pub mod lsadc_fifo_data {
#[doc = "Register `LSADC_FIFO_DATA` reader"] pub type R = crate :: R < LsadcFifoDataSpec > ;
#[doc = "Register `LSADC_FIFO_DATA` writer"] pub type W = crate :: W < LsadcFifoDataSpec > ;
#[doc = "Field `data` reader - ADC conversion data (14-bit)"] pub type DataR = crate :: FieldReader < u16 > ;
#[doc = "Field `channel` reader - Channel number (3-bit)"] pub type ChannelR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:13 - ADC conversion data (14-bit)"]
#[inline (always)] pub fn data (& self) -> DataR { DataR :: new ((self . bits & 0x3fff) as u16) }
#[doc = "Bits 14:16 - Channel number (3-bit)"]
#[inline (always)] pub fn channel (& self) -> ChannelR { ChannelR :: new (((self . bits >> 14) & 7) as u8) } } impl W { }
#[doc = "ADC FIFO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`lsadc_fifo_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lsadc_fifo_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LsadcFifoDataSpec ; impl crate :: RegisterSpec for LsadcFifoDataSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`lsadc_fifo_data::R`](R) reader structure"] impl crate :: Readable for LsadcFifoDataSpec { }
#[doc = "`write(|w| ..)` method takes [`lsadc_fifo_data::W`](W) writer structure"] impl crate :: Writable for LsadcFifoDataSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets LSADC_FIFO_DATA to value 0"] impl crate :: Resettable for LsadcFifoDataSpec { } }
#[doc = "CFG_CIC_FILTER_EN (rw) register accessor: CIC filter enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cic_filter_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cic_filter_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cic_filter_en`] module"]
#[doc (alias = "CFG_CIC_FILTER_EN")] pub type CfgCicFilterEn = crate :: Reg < cfg_cic_filter_en :: CfgCicFilterEnSpec > ;
#[doc = "CIC filter enable register"] pub mod cfg_cic_filter_en {
#[doc = "Register `CFG_CIC_FILTER_EN` reader"] pub type R = crate :: R < CfgCicFilterEnSpec > ;
#[doc = "Register `CFG_CIC_FILTER_EN` writer"] pub type W = crate :: W < CfgCicFilterEnSpec > ;
#[doc = "Field `cic_filter_en` reader - CIC filter enable"] pub type CicFilterEnR = crate :: BitReader ;
#[doc = "Field `cic_filter_en` writer - CIC filter enable"] pub type CicFilterEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - CIC filter enable"]
#[inline (always)] pub fn cic_filter_en (& self) -> CicFilterEnR { CicFilterEnR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - CIC filter enable"]
#[inline (always)] pub fn cic_filter_en (& mut self) -> CicFilterEnW < '_ , CfgCicFilterEnSpec > { CicFilterEnW :: new (self , 0) } }
#[doc = "CIC filter enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cic_filter_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cic_filter_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgCicFilterEnSpec ; impl crate :: RegisterSpec for CfgCicFilterEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_cic_filter_en::R`](R) reader structure"] impl crate :: Readable for CfgCicFilterEnSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_cic_filter_en::W`](W) writer structure"] impl crate :: Writable for CfgCicFilterEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_CIC_FILTER_EN to value 0"] impl crate :: Resettable for CfgCicFilterEnSpec { } }
#[doc = "CFG_CIC_OSR (rw) register accessor: CIC oversampling ratio register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cic_osr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cic_osr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cic_osr`] module"]
#[doc (alias = "CFG_CIC_OSR")] pub type CfgCicOsr = crate :: Reg < cfg_cic_osr :: CfgCicOsrSpec > ;
#[doc = "CIC oversampling ratio register"] pub mod cfg_cic_osr {
#[doc = "Register `CFG_CIC_OSR` reader"] pub type R = crate :: R < CfgCicOsrSpec > ;
#[doc = "Register `CFG_CIC_OSR` writer"] pub type W = crate :: W < CfgCicOsrSpec > ;
#[doc = "Field `cic_osr` reader - CIC oversampling ratio"] pub type CicOsrR = crate :: FieldReader ;
#[doc = "Field `cic_osr` writer - CIC oversampling ratio"] pub type CicOsrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - CIC oversampling ratio"]
#[inline (always)] pub fn cic_osr (& self) -> CicOsrR { CicOsrR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - CIC oversampling ratio"]
#[inline (always)] pub fn cic_osr (& mut self) -> CicOsrW < '_ , CfgCicOsrSpec > { CicOsrW :: new (self , 0) } }
#[doc = "CIC oversampling ratio register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cic_osr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cic_osr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgCicOsrSpec ; impl crate :: RegisterSpec for CfgCicOsrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_cic_osr::R`](R) reader structure"] impl crate :: Readable for CfgCicOsrSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_cic_osr::W`](W) writer structure"] impl crate :: Writable for CfgCicOsrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_CIC_OSR to value 0"] impl crate :: Resettable for CfgCicOsrSpec { } }
#[doc = "CFG_DATA_SEL (rw) register accessor: Data select register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_data_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_data_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_data_sel`] module"]
#[doc (alias = "CFG_DATA_SEL")] pub type CfgDataSel = crate :: Reg < cfg_data_sel :: CfgDataSelSpec > ;
#[doc = "Data select register"] pub mod cfg_data_sel {
#[doc = "Register `CFG_DATA_SEL` reader"] pub type R = crate :: R < CfgDataSelSpec > ;
#[doc = "Register `CFG_DATA_SEL` writer"] pub type W = crate :: W < CfgDataSelSpec > ;
#[doc = "Field `data_sel` reader - Data output select"] pub type DataSelR = crate :: BitReader ;
#[doc = "Field `data_sel` writer - Data output select"] pub type DataSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Data output select"]
#[inline (always)] pub fn data_sel (& self) -> DataSelR { DataSelR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Data output select"]
#[inline (always)] pub fn data_sel (& mut self) -> DataSelW < '_ , CfgDataSelSpec > { DataSelW :: new (self , 0) } }
#[doc = "Data select register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_data_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_data_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgDataSelSpec ; impl crate :: RegisterSpec for CfgDataSelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_data_sel::R`](R) reader structure"] impl crate :: Readable for CfgDataSelSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_data_sel::W`](W) writer structure"] impl crate :: Writable for CfgDataSelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_DATA_SEL to value 0"] impl crate :: Resettable for CfgDataSelSpec { } }
#[doc = "CFG_OFFSET (rw) register accessor: Offset register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_offset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_offset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_offset`] module"]
#[doc (alias = "CFG_OFFSET")] pub type CfgOffset = crate :: Reg < cfg_offset :: CfgOffsetSpec > ;
#[doc = "Offset register"] pub mod cfg_offset {
#[doc = "Register `CFG_OFFSET` reader"] pub type R = crate :: R < CfgOffsetSpec > ;
#[doc = "Register `CFG_OFFSET` writer"] pub type W = crate :: W < CfgOffsetSpec > ;
#[doc = "Field `offset` reader - ADC offset correction"] pub type OffsetR = crate :: FieldReader < u16 > ;
#[doc = "Field `offset` writer - ADC offset correction"] pub type OffsetW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - ADC offset correction"]
#[inline (always)] pub fn offset (& self) -> OffsetR { OffsetR :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - ADC offset correction"]
#[inline (always)] pub fn offset (& mut self) -> OffsetW < '_ , CfgOffsetSpec > { OffsetW :: new (self , 0) } }
#[doc = "Offset register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_offset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_offset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgOffsetSpec ; impl crate :: RegisterSpec for CfgOffsetSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_offset::R`](R) reader structure"] impl crate :: Readable for CfgOffsetSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_offset::W`](W) writer structure"] impl crate :: Writable for CfgOffsetSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_OFFSET to value 0"] impl crate :: Resettable for CfgOffsetSpec { } }
#[doc = "CFG_GAIN (rw) register accessor: Gain register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gain::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gain::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gain`] module"]
#[doc (alias = "CFG_GAIN")] pub type CfgGain = crate :: Reg < cfg_gain :: CfgGainSpec > ;
#[doc = "Gain register"] pub mod cfg_gain {
#[doc = "Register `CFG_GAIN` reader"] pub type R = crate :: R < CfgGainSpec > ;
#[doc = "Register `CFG_GAIN` writer"] pub type W = crate :: W < CfgGainSpec > ;
#[doc = "Field `gain` reader - ADC gain correction"] pub type GainR = crate :: FieldReader < u16 > ;
#[doc = "Field `gain` writer - ADC gain correction"] pub type GainW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - ADC gain correction"]
#[inline (always)] pub fn gain (& self) -> GainR { GainR :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - ADC gain correction"]
#[inline (always)] pub fn gain (& mut self) -> GainW < '_ , CfgGainSpec > { GainW :: new (self , 0) } }
#[doc = "Gain register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gain::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gain::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgGainSpec ; impl crate :: RegisterSpec for CfgGainSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_gain::R`](R) reader structure"] impl crate :: Readable for CfgGainSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_gain::W`](W) writer structure"] impl crate :: Writable for CfgGainSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_GAIN to value 0"] impl crate :: Resettable for CfgGainSpec { } } }
#[doc = "Temperature sensor controller (v151)"] pub type Tsensor = crate :: Periph < tsensor :: RegisterBlock , 0x4400_e000 > ; impl core :: fmt :: Debug for Tsensor { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Tsensor") . finish () } }
#[doc = "Temperature sensor controller (v151)"] pub mod tsensor {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { tsensor_ctl_id : TsensorCtlId , _reserved1 : [u8 ; 0x0c] , tsensor_reg0 : TsensorReg0 , tsensor_reg1 : TsensorReg1 , tsensor_reg2 : TsensorReg2 , tsensor_reg3 : TsensorReg3 , _reserved5 : [u8 ; 0x02e0] , tsensor_start : TsensorStart , tsensor_ctrl : TsensorCtrl , tsensor_sts : TsensorSts , _reserved8 : [u8 ; 0x04] , tsensor_ctrl1 : TsensorCtrl1 , tsensor_temp_high_limit : TsensorTempHighLimit , tsensor_temp_low_limit : TsensorTempLowLimit , tsensor_over_temp : TsensorOverTemp , tsensor_temp_int_en : TsensorTempIntEn , tsensor_temp_int_clr : TsensorTempIntClr , tsensor_temp_int_sts : TsensorTempIntSts , _reserved15 : [u8 ; 0x04] , tsensor_auto_refresh_period : TsensorAutoRefreshPeriod , tsensor_auto_refresh_cfg : TsensorAutoRefreshCfg , } impl RegisterBlock {
#[doc = "0x00 - Temperature sensor control ID"]
#[inline (always)] pub const fn tsensor_ctl_id (& self) -> & TsensorCtlId { & self . tsensor_ctl_id }
#[doc = "0x10 - Common register 0"]
#[inline (always)] pub const fn tsensor_reg0 (& self) -> & TsensorReg0 { & self . tsensor_reg0 }
#[doc = "0x14 - Common register 1"]
#[inline (always)] pub const fn tsensor_reg1 (& self) -> & TsensorReg1 { & self . tsensor_reg1 }
#[doc = "0x18 - Common register 2"]
#[inline (always)] pub const fn tsensor_reg2 (& self) -> & TsensorReg2 { & self . tsensor_reg2 }
#[doc = "0x1c - Common register 3"]
#[inline (always)] pub const fn tsensor_reg3 (& self) -> & TsensorReg3 { & self . tsensor_reg3 }
#[doc = "0x300 - Temperature sensor start register"]
#[inline (always)] pub const fn tsensor_start (& self) -> & TsensorStart { & self . tsensor_start }
#[doc = "0x304 - Temperature sensor control register"]
#[inline (always)] pub const fn tsensor_ctrl (& self) -> & TsensorCtrl { & self . tsensor_ctrl }
#[doc = "0x308 - Temperature sensor status register"]
#[inline (always)] pub const fn tsensor_sts (& self) -> & TsensorSts { & self . tsensor_sts }
#[doc = "0x310 - Temperature sensor control 1"]
#[inline (always)] pub const fn tsensor_ctrl1 (& self) -> & TsensorCtrl1 { & self . tsensor_ctrl1 }
#[doc = "0x314 - High temperature limit"]
#[inline (always)] pub const fn tsensor_temp_high_limit (& self) -> & TsensorTempHighLimit { & self . tsensor_temp_high_limit }
#[doc = "0x318 - Low temperature limit"]
#[inline (always)] pub const fn tsensor_temp_low_limit (& self) -> & TsensorTempLowLimit { & self . tsensor_temp_low_limit }
#[doc = "0x31c - Over-temperature threshold"]
#[inline (always)] pub const fn tsensor_over_temp (& self) -> & TsensorOverTemp { & self . tsensor_over_temp }
#[doc = "0x320 - Temperature interrupt enable"]
#[inline (always)] pub const fn tsensor_temp_int_en (& self) -> & TsensorTempIntEn { & self . tsensor_temp_int_en }
#[doc = "0x324 - Temperature interrupt clear"]
#[inline (always)] pub const fn tsensor_temp_int_clr (& self) -> & TsensorTempIntClr { & self . tsensor_temp_int_clr }
#[doc = "0x328 - Temperature interrupt status"]
#[inline (always)] pub const fn tsensor_temp_int_sts (& self) -> & TsensorTempIntSts { & self . tsensor_temp_int_sts }
#[doc = "0x330 - Auto refresh period"]
#[inline (always)] pub const fn tsensor_auto_refresh_period (& self) -> & TsensorAutoRefreshPeriod { & self . tsensor_auto_refresh_period }
#[doc = "0x334 - Auto refresh configuration"]
#[inline (always)] pub const fn tsensor_auto_refresh_cfg (& self) -> & TsensorAutoRefreshCfg { & self . tsensor_auto_refresh_cfg } }
#[doc = "TSENSOR_CTL_ID (rw) register accessor: Temperature sensor control ID\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctl_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctl_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_ctl_id`] module"]
#[doc (alias = "TSENSOR_CTL_ID")] pub type TsensorCtlId = crate :: Reg < tsensor_ctl_id :: TsensorCtlIdSpec > ;
#[doc = "Temperature sensor control ID"] pub mod tsensor_ctl_id {
#[doc = "Register `TSENSOR_CTL_ID` reader"] pub type R = crate :: R < TsensorCtlIdSpec > ;
#[doc = "Register `TSENSOR_CTL_ID` writer"] pub type W = crate :: W < TsensorCtlIdSpec > ;
#[doc = "Field `tsensor_ctl_id` reader - Control ID"] pub type TsensorCtlIdR = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Control ID"]
#[inline (always)] pub fn tsensor_ctl_id (& self) -> TsensorCtlIdR { TsensorCtlIdR :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "Temperature sensor control ID\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctl_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctl_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorCtlIdSpec ; impl crate :: RegisterSpec for TsensorCtlIdSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_ctl_id::R`](R) reader structure"] impl crate :: Readable for TsensorCtlIdSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_ctl_id::W`](W) writer structure"] impl crate :: Writable for TsensorCtlIdSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_CTL_ID to value 0"] impl crate :: Resettable for TsensorCtlIdSpec { } }
#[doc = "TSENSOR_REG0 (rw) register accessor: Common register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_reg0`] module"]
#[doc (alias = "TSENSOR_REG0")] pub type TsensorReg0 = crate :: Reg < tsensor_reg0 :: TsensorReg0Spec > ;
#[doc = "Common register 0"] pub mod tsensor_reg0 {
#[doc = "Register `TSENSOR_REG0` reader"] pub type R = crate :: R < TsensorReg0Spec > ;
#[doc = "Register `TSENSOR_REG0` writer"] pub type W = crate :: W < TsensorReg0Spec > ;
#[doc = "Field `tsensor_reg0` reader - Common configuration register 0"] pub type TsensorReg0R = crate :: FieldReader < u32 > ;
#[doc = "Field `tsensor_reg0` writer - Common configuration register 0"] pub type TsensorReg0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Common configuration register 0"]
#[inline (always)] pub fn tsensor_reg0 (& self) -> TsensorReg0R { TsensorReg0R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Common configuration register 0"]
#[inline (always)] pub fn tsensor_reg0 (& mut self) -> TsensorReg0W < '_ , TsensorReg0Spec > { TsensorReg0W :: new (self , 0) } }
#[doc = "Common register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorReg0Spec ; impl crate :: RegisterSpec for TsensorReg0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_reg0::R`](R) reader structure"] impl crate :: Readable for TsensorReg0Spec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_reg0::W`](W) writer structure"] impl crate :: Writable for TsensorReg0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_REG0 to value 0"] impl crate :: Resettable for TsensorReg0Spec { } }
#[doc = "TSENSOR_REG1 (rw) register accessor: Common register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_reg1`] module"]
#[doc (alias = "TSENSOR_REG1")] pub type TsensorReg1 = crate :: Reg < tsensor_reg1 :: TsensorReg1Spec > ;
#[doc = "Common register 1"] pub mod tsensor_reg1 {
#[doc = "Register `TSENSOR_REG1` reader"] pub type R = crate :: R < TsensorReg1Spec > ;
#[doc = "Register `TSENSOR_REG1` writer"] pub type W = crate :: W < TsensorReg1Spec > ;
#[doc = "Field `tsensor_reg1` reader - Common configuration register 1"] pub type TsensorReg1R = crate :: FieldReader < u32 > ;
#[doc = "Field `tsensor_reg1` writer - Common configuration register 1"] pub type TsensorReg1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Common configuration register 1"]
#[inline (always)] pub fn tsensor_reg1 (& self) -> TsensorReg1R { TsensorReg1R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Common configuration register 1"]
#[inline (always)] pub fn tsensor_reg1 (& mut self) -> TsensorReg1W < '_ , TsensorReg1Spec > { TsensorReg1W :: new (self , 0) } }
#[doc = "Common register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorReg1Spec ; impl crate :: RegisterSpec for TsensorReg1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_reg1::R`](R) reader structure"] impl crate :: Readable for TsensorReg1Spec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_reg1::W`](W) writer structure"] impl crate :: Writable for TsensorReg1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_REG1 to value 0"] impl crate :: Resettable for TsensorReg1Spec { } }
#[doc = "TSENSOR_REG2 (rw) register accessor: Common register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_reg2`] module"]
#[doc (alias = "TSENSOR_REG2")] pub type TsensorReg2 = crate :: Reg < tsensor_reg2 :: TsensorReg2Spec > ;
#[doc = "Common register 2"] pub mod tsensor_reg2 {
#[doc = "Register `TSENSOR_REG2` reader"] pub type R = crate :: R < TsensorReg2Spec > ;
#[doc = "Register `TSENSOR_REG2` writer"] pub type W = crate :: W < TsensorReg2Spec > ;
#[doc = "Field `tsensor_reg2` reader - Common configuration register 2"] pub type TsensorReg2R = crate :: FieldReader < u32 > ;
#[doc = "Field `tsensor_reg2` writer - Common configuration register 2"] pub type TsensorReg2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Common configuration register 2"]
#[inline (always)] pub fn tsensor_reg2 (& self) -> TsensorReg2R { TsensorReg2R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Common configuration register 2"]
#[inline (always)] pub fn tsensor_reg2 (& mut self) -> TsensorReg2W < '_ , TsensorReg2Spec > { TsensorReg2W :: new (self , 0) } }
#[doc = "Common register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorReg2Spec ; impl crate :: RegisterSpec for TsensorReg2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_reg2::R`](R) reader structure"] impl crate :: Readable for TsensorReg2Spec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_reg2::W`](W) writer structure"] impl crate :: Writable for TsensorReg2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_REG2 to value 0"] impl crate :: Resettable for TsensorReg2Spec { } }
#[doc = "TSENSOR_REG3 (rw) register accessor: Common register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_reg3`] module"]
#[doc (alias = "TSENSOR_REG3")] pub type TsensorReg3 = crate :: Reg < tsensor_reg3 :: TsensorReg3Spec > ;
#[doc = "Common register 3"] pub mod tsensor_reg3 {
#[doc = "Register `TSENSOR_REG3` reader"] pub type R = crate :: R < TsensorReg3Spec > ;
#[doc = "Register `TSENSOR_REG3` writer"] pub type W = crate :: W < TsensorReg3Spec > ;
#[doc = "Field `tsensor_reg3` reader - Common configuration register 3"] pub type TsensorReg3R = crate :: FieldReader < u32 > ;
#[doc = "Field `tsensor_reg3` writer - Common configuration register 3"] pub type TsensorReg3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Common configuration register 3"]
#[inline (always)] pub fn tsensor_reg3 (& self) -> TsensorReg3R { TsensorReg3R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Common configuration register 3"]
#[inline (always)] pub fn tsensor_reg3 (& mut self) -> TsensorReg3W < '_ , TsensorReg3Spec > { TsensorReg3W :: new (self , 0) } }
#[doc = "Common register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_reg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_reg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorReg3Spec ; impl crate :: RegisterSpec for TsensorReg3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_reg3::R`](R) reader structure"] impl crate :: Readable for TsensorReg3Spec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_reg3::W`](W) writer structure"] impl crate :: Writable for TsensorReg3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_REG3 to value 0"] impl crate :: Resettable for TsensorReg3Spec { } }
#[doc = "TSENSOR_START (rw) register accessor: Temperature sensor start register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_start`] module"]
#[doc (alias = "TSENSOR_START")] pub type TsensorStart = crate :: Reg < tsensor_start :: TsensorStartSpec > ;
#[doc = "Temperature sensor start register"] pub mod tsensor_start {
#[doc = "Register `TSENSOR_START` reader"] pub type R = crate :: R < TsensorStartSpec > ;
#[doc = "Register `TSENSOR_START` writer"] pub type W = crate :: W < TsensorStartSpec > ;
#[doc = "Field `tsensor_start` writer - Write 1 to refresh temperature reading"] pub type TsensorStartW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Write 1 to refresh temperature reading"]
#[inline (always)] pub fn tsensor_start (& mut self) -> TsensorStartW < '_ , TsensorStartSpec > { TsensorStartW :: new (self , 0) } }
#[doc = "Temperature sensor start register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorStartSpec ; impl crate :: RegisterSpec for TsensorStartSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_start::R`](R) reader structure"] impl crate :: Readable for TsensorStartSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_start::W`](W) writer structure"] impl crate :: Writable for TsensorStartSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_START to value 0"] impl crate :: Resettable for TsensorStartSpec { } }
#[doc = "TSENSOR_CTRL (rw) register accessor: Temperature sensor control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_ctrl`] module"]
#[doc (alias = "TSENSOR_CTRL")] pub type TsensorCtrl = crate :: Reg < tsensor_ctrl :: TsensorCtrlSpec > ;
#[doc = "Temperature sensor control register"] pub mod tsensor_ctrl {
#[doc = "Register `TSENSOR_CTRL` reader"] pub type R = crate :: R < TsensorCtrlSpec > ;
#[doc = "Register `TSENSOR_CTRL` writer"] pub type W = crate :: W < TsensorCtrlSpec > ;
#[doc = "Field `tsensor_enable` reader - Temperature sensor enable"] pub type TsensorEnableR = crate :: BitReader ;
#[doc = "Field `tsensor_enable` writer - Temperature sensor enable"] pub type TsensorEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tsensor_mode` reader - Temperature sensor mode"] pub type TsensorModeR = crate :: FieldReader ;
#[doc = "Field `tsensor_mode` writer - Temperature sensor mode"] pub type TsensorModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R {
#[doc = "Bit 0 - Temperature sensor enable"]
#[inline (always)] pub fn tsensor_enable (& self) -> TsensorEnableR { TsensorEnableR :: new ((self . bits & 1) != 0) }
#[doc = "Bits 1:2 - Temperature sensor mode"]
#[inline (always)] pub fn tsensor_mode (& self) -> TsensorModeR { TsensorModeR :: new (((self . bits >> 1) & 3) as u8) } } impl W {
#[doc = "Bit 0 - Temperature sensor enable"]
#[inline (always)] pub fn tsensor_enable (& mut self) -> TsensorEnableW < '_ , TsensorCtrlSpec > { TsensorEnableW :: new (self , 0) }
#[doc = "Bits 1:2 - Temperature sensor mode"]
#[inline (always)] pub fn tsensor_mode (& mut self) -> TsensorModeW < '_ , TsensorCtrlSpec > { TsensorModeW :: new (self , 1) } }
#[doc = "Temperature sensor control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorCtrlSpec ; impl crate :: RegisterSpec for TsensorCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_ctrl::R`](R) reader structure"] impl crate :: Readable for TsensorCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_ctrl::W`](W) writer structure"] impl crate :: Writable for TsensorCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_CTRL to value 0"] impl crate :: Resettable for TsensorCtrlSpec { } }
#[doc = "TSENSOR_STS (rw) register accessor: Temperature sensor status register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_sts`] module"]
#[doc (alias = "TSENSOR_STS")] pub type TsensorSts = crate :: Reg < tsensor_sts :: TsensorStsSpec > ;
#[doc = "Temperature sensor status register"] pub mod tsensor_sts {
#[doc = "Register `TSENSOR_STS` reader"] pub type R = crate :: R < TsensorStsSpec > ;
#[doc = "Register `TSENSOR_STS` writer"] pub type W = crate :: W < TsensorStsSpec > ;
#[doc = "Field `clr` reader - Clear status"] pub type ClrR = crate :: BitReader ;
#[doc = "Field `clr` writer - Clear status"] pub type ClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rdy` reader - Data ready flag"] pub type RdyR = crate :: BitReader ;
#[doc = "Field `data` reader - Temperature code (10-bit, range 114-896 for -40C to 125C)"] pub type DataR = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bit 0 - Clear status"]
#[inline (always)] pub fn clr (& self) -> ClrR { ClrR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Data ready flag"]
#[inline (always)] pub fn rdy (& self) -> RdyR { RdyR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bits 2:11 - Temperature code (10-bit, range 114-896 for -40C to 125C)"]
#[inline (always)] pub fn data (& self) -> DataR { DataR :: new (((self . bits >> 2) & 0x03ff) as u16) } } impl W {
#[doc = "Bit 0 - Clear status"]
#[inline (always)] pub fn clr (& mut self) -> ClrW < '_ , TsensorStsSpec > { ClrW :: new (self , 0) } }
#[doc = "Temperature sensor status register\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorStsSpec ; impl crate :: RegisterSpec for TsensorStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_sts::R`](R) reader structure"] impl crate :: Readable for TsensorStsSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_sts::W`](W) writer structure"] impl crate :: Writable for TsensorStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_STS to value 0"] impl crate :: Resettable for TsensorStsSpec { } }
#[doc = "TSENSOR_CTRL1 (rw) register accessor: Temperature sensor control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_ctrl1`] module"]
#[doc (alias = "TSENSOR_CTRL1")] pub type TsensorCtrl1 = crate :: Reg < tsensor_ctrl1 :: TsensorCtrl1Spec > ;
#[doc = "Temperature sensor control 1"] pub mod tsensor_ctrl1 {
#[doc = "Register `TSENSOR_CTRL1` reader"] pub type R = crate :: R < TsensorCtrl1Spec > ;
#[doc = "Register `TSENSOR_CTRL1` writer"] pub type W = crate :: W < TsensorCtrl1Spec > ;
#[doc = "Field `temp_calib` reader - Temperature calibration enable"] pub type TempCalibR = crate :: BitReader ;
#[doc = "Field `temp_calib` writer - Temperature calibration enable"] pub type TempCalibW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `temp_ct_sel` reader - Temperature CT select"] pub type TempCtSelR = crate :: FieldReader ;
#[doc = "Field `temp_ct_sel` writer - Temperature CT select"] pub type TempCtSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ;
#[doc = "Field `dft` reader - DFT mode enable"] pub type DftR = crate :: BitReader ;
#[doc = "Field `dft` writer - DFT mode enable"] pub type DftW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Temperature calibration enable"]
#[inline (always)] pub fn temp_calib (& self) -> TempCalibR { TempCalibR :: new ((self . bits & 1) != 0) }
#[doc = "Bits 1:2 - Temperature CT select"]
#[inline (always)] pub fn temp_ct_sel (& self) -> TempCtSelR { TempCtSelR :: new (((self . bits >> 1) & 3) as u8) }
#[doc = "Bit 4 - DFT mode enable"]
#[inline (always)] pub fn dft (& self) -> DftR { DftR :: new (((self . bits >> 4) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Temperature calibration enable"]
#[inline (always)] pub fn temp_calib (& mut self) -> TempCalibW < '_ , TsensorCtrl1Spec > { TempCalibW :: new (self , 0) }
#[doc = "Bits 1:2 - Temperature CT select"]
#[inline (always)] pub fn temp_ct_sel (& mut self) -> TempCtSelW < '_ , TsensorCtrl1Spec > { TempCtSelW :: new (self , 1) }
#[doc = "Bit 4 - DFT mode enable"]
#[inline (always)] pub fn dft (& mut self) -> DftW < '_ , TsensorCtrl1Spec > { DftW :: new (self , 4) } }
#[doc = "Temperature sensor control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorCtrl1Spec ; impl crate :: RegisterSpec for TsensorCtrl1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_ctrl1::R`](R) reader structure"] impl crate :: Readable for TsensorCtrl1Spec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_ctrl1::W`](W) writer structure"] impl crate :: Writable for TsensorCtrl1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_CTRL1 to value 0"] impl crate :: Resettable for TsensorCtrl1Spec { } }
#[doc = "TSENSOR_TEMP_HIGH_LIMIT (rw) register accessor: High temperature limit\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_high_limit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_high_limit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_temp_high_limit`] module"]
#[doc (alias = "TSENSOR_TEMP_HIGH_LIMIT")] pub type TsensorTempHighLimit = crate :: Reg < tsensor_temp_high_limit :: TsensorTempHighLimitSpec > ;
#[doc = "High temperature limit"] pub mod tsensor_temp_high_limit {
#[doc = "Register `TSENSOR_TEMP_HIGH_LIMIT` reader"] pub type R = crate :: R < TsensorTempHighLimitSpec > ;
#[doc = "Register `TSENSOR_TEMP_HIGH_LIMIT` writer"] pub type W = crate :: W < TsensorTempHighLimitSpec > ;
#[doc = "Field `temp_high_limit` reader - High temperature threshold (10-bit code)"] pub type TempHighLimitR = crate :: FieldReader < u16 > ;
#[doc = "Field `temp_high_limit` writer - High temperature threshold (10-bit code)"] pub type TempHighLimitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; impl R {
#[doc = "Bits 0:9 - High temperature threshold (10-bit code)"]
#[inline (always)] pub fn temp_high_limit (& self) -> TempHighLimitR { TempHighLimitR :: new ((self . bits & 0x03ff) as u16) } } impl W {
#[doc = "Bits 0:9 - High temperature threshold (10-bit code)"]
#[inline (always)] pub fn temp_high_limit (& mut self) -> TempHighLimitW < '_ , TsensorTempHighLimitSpec > { TempHighLimitW :: new (self , 0) } }
#[doc = "High temperature limit\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_high_limit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_high_limit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorTempHighLimitSpec ; impl crate :: RegisterSpec for TsensorTempHighLimitSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_temp_high_limit::R`](R) reader structure"] impl crate :: Readable for TsensorTempHighLimitSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_temp_high_limit::W`](W) writer structure"] impl crate :: Writable for TsensorTempHighLimitSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_TEMP_HIGH_LIMIT to value 0"] impl crate :: Resettable for TsensorTempHighLimitSpec { } }
#[doc = "TSENSOR_TEMP_LOW_LIMIT (rw) register accessor: Low temperature limit\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_low_limit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_low_limit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_temp_low_limit`] module"]
#[doc (alias = "TSENSOR_TEMP_LOW_LIMIT")] pub type TsensorTempLowLimit = crate :: Reg < tsensor_temp_low_limit :: TsensorTempLowLimitSpec > ;
#[doc = "Low temperature limit"] pub mod tsensor_temp_low_limit {
#[doc = "Register `TSENSOR_TEMP_LOW_LIMIT` reader"] pub type R = crate :: R < TsensorTempLowLimitSpec > ;
#[doc = "Register `TSENSOR_TEMP_LOW_LIMIT` writer"] pub type W = crate :: W < TsensorTempLowLimitSpec > ;
#[doc = "Field `temp_low_limit` reader - Low temperature threshold (10-bit code)"] pub type TempLowLimitR = crate :: FieldReader < u16 > ;
#[doc = "Field `temp_low_limit` writer - Low temperature threshold (10-bit code)"] pub type TempLowLimitW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; impl R {
#[doc = "Bits 0:9 - Low temperature threshold (10-bit code)"]
#[inline (always)] pub fn temp_low_limit (& self) -> TempLowLimitR { TempLowLimitR :: new ((self . bits & 0x03ff) as u16) } } impl W {
#[doc = "Bits 0:9 - Low temperature threshold (10-bit code)"]
#[inline (always)] pub fn temp_low_limit (& mut self) -> TempLowLimitW < '_ , TsensorTempLowLimitSpec > { TempLowLimitW :: new (self , 0) } }
#[doc = "Low temperature limit\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_low_limit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_low_limit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorTempLowLimitSpec ; impl crate :: RegisterSpec for TsensorTempLowLimitSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_temp_low_limit::R`](R) reader structure"] impl crate :: Readable for TsensorTempLowLimitSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_temp_low_limit::W`](W) writer structure"] impl crate :: Writable for TsensorTempLowLimitSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_TEMP_LOW_LIMIT to value 0"] impl crate :: Resettable for TsensorTempLowLimitSpec { } }
#[doc = "TSENSOR_OVER_TEMP (rw) register accessor: Over-temperature threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_over_temp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_over_temp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_over_temp`] module"]
#[doc (alias = "TSENSOR_OVER_TEMP")] pub type TsensorOverTemp = crate :: Reg < tsensor_over_temp :: TsensorOverTempSpec > ;
#[doc = "Over-temperature threshold"] pub mod tsensor_over_temp {
#[doc = "Register `TSENSOR_OVER_TEMP` reader"] pub type R = crate :: R < TsensorOverTempSpec > ;
#[doc = "Register `TSENSOR_OVER_TEMP` writer"] pub type W = crate :: W < TsensorOverTempSpec > ;
#[doc = "Field `over_temp` reader - Over-temperature threshold (10-bit code)"] pub type OverTempR = crate :: FieldReader < u16 > ;
#[doc = "Field `over_temp` writer - Over-temperature threshold (10-bit code)"] pub type OverTempW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ;
#[doc = "Field `over_temp_en` reader - Over-temperature interrupt enable"] pub type OverTempEnR = crate :: BitReader ;
#[doc = "Field `over_temp_en` writer - Over-temperature interrupt enable"] pub type OverTempEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:9 - Over-temperature threshold (10-bit code)"]
#[inline (always)] pub fn over_temp (& self) -> OverTempR { OverTempR :: new ((self . bits & 0x03ff) as u16) }
#[doc = "Bit 10 - Over-temperature interrupt enable"]
#[inline (always)] pub fn over_temp_en (& self) -> OverTempEnR { OverTempEnR :: new (((self . bits >> 10) & 1) != 0) } } impl W {
#[doc = "Bits 0:9 - Over-temperature threshold (10-bit code)"]
#[inline (always)] pub fn over_temp (& mut self) -> OverTempW < '_ , TsensorOverTempSpec > { OverTempW :: new (self , 0) }
#[doc = "Bit 10 - Over-temperature interrupt enable"]
#[inline (always)] pub fn over_temp_en (& mut self) -> OverTempEnW < '_ , TsensorOverTempSpec > { OverTempEnW :: new (self , 10) } }
#[doc = "Over-temperature threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_over_temp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_over_temp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorOverTempSpec ; impl crate :: RegisterSpec for TsensorOverTempSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_over_temp::R`](R) reader structure"] impl crate :: Readable for TsensorOverTempSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_over_temp::W`](W) writer structure"] impl crate :: Writable for TsensorOverTempSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_OVER_TEMP to value 0"] impl crate :: Resettable for TsensorOverTempSpec { } }
#[doc = "TSENSOR_TEMP_INT_EN (rw) register accessor: Temperature interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_temp_int_en`] module"]
#[doc (alias = "TSENSOR_TEMP_INT_EN")] pub type TsensorTempIntEn = crate :: Reg < tsensor_temp_int_en :: TsensorTempIntEnSpec > ;
#[doc = "Temperature interrupt enable"] pub mod tsensor_temp_int_en {
#[doc = "Register `TSENSOR_TEMP_INT_EN` reader"] pub type R = crate :: R < TsensorTempIntEnSpec > ;
#[doc = "Register `TSENSOR_TEMP_INT_EN` writer"] pub type W = crate :: W < TsensorTempIntEnSpec > ;
#[doc = "Field `done_int_en` reader - Conversion done interrupt enable"] pub type DoneIntEnR = crate :: BitReader ;
#[doc = "Field `done_int_en` writer - Conversion done interrupt enable"] pub type DoneIntEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `out_thresh_int_en` reader - Out-of-threshold interrupt enable"] pub type OutThreshIntEnR = crate :: BitReader ;
#[doc = "Field `out_thresh_int_en` writer - Out-of-threshold interrupt enable"] pub type OutThreshIntEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `overtemp_int_en` reader - Over-temperature interrupt enable"] pub type OvertempIntEnR = crate :: BitReader ;
#[doc = "Field `overtemp_int_en` writer - Over-temperature interrupt enable"] pub type OvertempIntEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Conversion done interrupt enable"]
#[inline (always)] pub fn done_int_en (& self) -> DoneIntEnR { DoneIntEnR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Out-of-threshold interrupt enable"]
#[inline (always)] pub fn out_thresh_int_en (& self) -> OutThreshIntEnR { OutThreshIntEnR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Over-temperature interrupt enable"]
#[inline (always)] pub fn overtemp_int_en (& self) -> OvertempIntEnR { OvertempIntEnR :: new (((self . bits >> 2) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Conversion done interrupt enable"]
#[inline (always)] pub fn done_int_en (& mut self) -> DoneIntEnW < '_ , TsensorTempIntEnSpec > { DoneIntEnW :: new (self , 0) }
#[doc = "Bit 1 - Out-of-threshold interrupt enable"]
#[inline (always)] pub fn out_thresh_int_en (& mut self) -> OutThreshIntEnW < '_ , TsensorTempIntEnSpec > { OutThreshIntEnW :: new (self , 1) }
#[doc = "Bit 2 - Over-temperature interrupt enable"]
#[inline (always)] pub fn overtemp_int_en (& mut self) -> OvertempIntEnW < '_ , TsensorTempIntEnSpec > { OvertempIntEnW :: new (self , 2) } }
#[doc = "Temperature interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorTempIntEnSpec ; impl crate :: RegisterSpec for TsensorTempIntEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_temp_int_en::R`](R) reader structure"] impl crate :: Readable for TsensorTempIntEnSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_temp_int_en::W`](W) writer structure"] impl crate :: Writable for TsensorTempIntEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_TEMP_INT_EN to value 0"] impl crate :: Resettable for TsensorTempIntEnSpec { } }
#[doc = "TSENSOR_TEMP_INT_CLR (rw) register accessor: Temperature interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_temp_int_clr`] module"]
#[doc (alias = "TSENSOR_TEMP_INT_CLR")] pub type TsensorTempIntClr = crate :: Reg < tsensor_temp_int_clr :: TsensorTempIntClrSpec > ;
#[doc = "Temperature interrupt clear"] pub mod tsensor_temp_int_clr {
#[doc = "Register `TSENSOR_TEMP_INT_CLR` reader"] pub type R = crate :: R < TsensorTempIntClrSpec > ;
#[doc = "Register `TSENSOR_TEMP_INT_CLR` writer"] pub type W = crate :: W < TsensorTempIntClrSpec > ;
#[doc = "Field `done_int_clr` writer - Clear done interrupt"] pub type DoneIntClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `out_thresh_int_clr` writer - Clear out-of-threshold interrupt"] pub type OutThreshIntClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `overtemp_int_clr` writer - Clear over-temperature interrupt"] pub type OvertempIntClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Clear done interrupt"]
#[inline (always)] pub fn done_int_clr (& mut self) -> DoneIntClrW < '_ , TsensorTempIntClrSpec > { DoneIntClrW :: new (self , 0) }
#[doc = "Bit 1 - Clear out-of-threshold interrupt"]
#[inline (always)] pub fn out_thresh_int_clr (& mut self) -> OutThreshIntClrW < '_ , TsensorTempIntClrSpec > { OutThreshIntClrW :: new (self , 1) }
#[doc = "Bit 2 - Clear over-temperature interrupt"]
#[inline (always)] pub fn overtemp_int_clr (& mut self) -> OvertempIntClrW < '_ , TsensorTempIntClrSpec > { OvertempIntClrW :: new (self , 2) } }
#[doc = "Temperature interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorTempIntClrSpec ; impl crate :: RegisterSpec for TsensorTempIntClrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_temp_int_clr::R`](R) reader structure"] impl crate :: Readable for TsensorTempIntClrSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_temp_int_clr::W`](W) writer structure"] impl crate :: Writable for TsensorTempIntClrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_TEMP_INT_CLR to value 0"] impl crate :: Resettable for TsensorTempIntClrSpec { } }
#[doc = "TSENSOR_TEMP_INT_STS (rw) register accessor: Temperature interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_temp_int_sts`] module"]
#[doc (alias = "TSENSOR_TEMP_INT_STS")] pub type TsensorTempIntSts = crate :: Reg < tsensor_temp_int_sts :: TsensorTempIntStsSpec > ;
#[doc = "Temperature interrupt status"] pub mod tsensor_temp_int_sts {
#[doc = "Register `TSENSOR_TEMP_INT_STS` reader"] pub type R = crate :: R < TsensorTempIntStsSpec > ;
#[doc = "Register `TSENSOR_TEMP_INT_STS` writer"] pub type W = crate :: W < TsensorTempIntStsSpec > ;
#[doc = "Field `done_int_sts` reader - Conversion done interrupt status"] pub type DoneIntStsR = crate :: BitReader ;
#[doc = "Field `out_thresh_int_sts` reader - Out-of-threshold interrupt status"] pub type OutThreshIntStsR = crate :: BitReader ;
#[doc = "Field `overtemp_int_sts` reader - Over-temperature interrupt status"] pub type OvertempIntStsR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Conversion done interrupt status"]
#[inline (always)] pub fn done_int_sts (& self) -> DoneIntStsR { DoneIntStsR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Out-of-threshold interrupt status"]
#[inline (always)] pub fn out_thresh_int_sts (& self) -> OutThreshIntStsR { OutThreshIntStsR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Over-temperature interrupt status"]
#[inline (always)] pub fn overtemp_int_sts (& self) -> OvertempIntStsR { OvertempIntStsR :: new (((self . bits >> 2) & 1) != 0) } } impl W { }
#[doc = "Temperature interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_temp_int_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_temp_int_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorTempIntStsSpec ; impl crate :: RegisterSpec for TsensorTempIntStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_temp_int_sts::R`](R) reader structure"] impl crate :: Readable for TsensorTempIntStsSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_temp_int_sts::W`](W) writer structure"] impl crate :: Writable for TsensorTempIntStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_TEMP_INT_STS to value 0"] impl crate :: Resettable for TsensorTempIntStsSpec { } }
#[doc = "TSENSOR_AUTO_REFRESH_PERIOD (rw) register accessor: Auto refresh period\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_auto_refresh_period::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_auto_refresh_period::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_auto_refresh_period`] module"]
#[doc (alias = "TSENSOR_AUTO_REFRESH_PERIOD")] pub type TsensorAutoRefreshPeriod = crate :: Reg < tsensor_auto_refresh_period :: TsensorAutoRefreshPeriodSpec > ;
#[doc = "Auto refresh period"] pub mod tsensor_auto_refresh_period {
#[doc = "Register `TSENSOR_AUTO_REFRESH_PERIOD` reader"] pub type R = crate :: R < TsensorAutoRefreshPeriodSpec > ;
#[doc = "Register `TSENSOR_AUTO_REFRESH_PERIOD` writer"] pub type W = crate :: W < TsensorAutoRefreshPeriodSpec > ;
#[doc = "Field `auto_refresh_period` reader - Auto refresh period in 32kHz clock cycles"] pub type AutoRefreshPeriodR = crate :: FieldReader < u16 > ;
#[doc = "Field `auto_refresh_period` writer - Auto refresh period in 32kHz clock cycles"] pub type AutoRefreshPeriodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R {
#[doc = "Bits 0:15 - Auto refresh period in 32kHz clock cycles"]
#[inline (always)] pub fn auto_refresh_period (& self) -> AutoRefreshPeriodR { AutoRefreshPeriodR :: new ((self . bits & 0xffff) as u16) } } impl W {
#[doc = "Bits 0:15 - Auto refresh period in 32kHz clock cycles"]
#[inline (always)] pub fn auto_refresh_period (& mut self) -> AutoRefreshPeriodW < '_ , TsensorAutoRefreshPeriodSpec > { AutoRefreshPeriodW :: new (self , 0) } }
#[doc = "Auto refresh period\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_auto_refresh_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_auto_refresh_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorAutoRefreshPeriodSpec ; impl crate :: RegisterSpec for TsensorAutoRefreshPeriodSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_auto_refresh_period::R`](R) reader structure"] impl crate :: Readable for TsensorAutoRefreshPeriodSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_auto_refresh_period::W`](W) writer structure"] impl crate :: Writable for TsensorAutoRefreshPeriodSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_AUTO_REFRESH_PERIOD to value 0"] impl crate :: Resettable for TsensorAutoRefreshPeriodSpec { } }
#[doc = "TSENSOR_AUTO_REFRESH_CFG (rw) register accessor: Auto refresh configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_auto_refresh_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_auto_refresh_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsensor_auto_refresh_cfg`] module"]
#[doc (alias = "TSENSOR_AUTO_REFRESH_CFG")] pub type TsensorAutoRefreshCfg = crate :: Reg < tsensor_auto_refresh_cfg :: TsensorAutoRefreshCfgSpec > ;
#[doc = "Auto refresh configuration"] pub mod tsensor_auto_refresh_cfg {
#[doc = "Register `TSENSOR_AUTO_REFRESH_CFG` reader"] pub type R = crate :: R < TsensorAutoRefreshCfgSpec > ;
#[doc = "Register `TSENSOR_AUTO_REFRESH_CFG` writer"] pub type W = crate :: W < TsensorAutoRefreshCfgSpec > ;
#[doc = "Field `auto_refresh_en` reader - Auto refresh enable"] pub type AutoRefreshEnR = crate :: BitReader ;
#[doc = "Field `auto_refresh_en` writer - Auto refresh enable"] pub type AutoRefreshEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Auto refresh enable"]
#[inline (always)] pub fn auto_refresh_en (& self) -> AutoRefreshEnR { AutoRefreshEnR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Auto refresh enable"]
#[inline (always)] pub fn auto_refresh_en (& mut self) -> AutoRefreshEnW < '_ , TsensorAutoRefreshCfgSpec > { AutoRefreshEnW :: new (self , 0) } }
#[doc = "Auto refresh configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`tsensor_auto_refresh_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsensor_auto_refresh_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TsensorAutoRefreshCfgSpec ; impl crate :: RegisterSpec for TsensorAutoRefreshCfgSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tsensor_auto_refresh_cfg::R`](R) reader structure"] impl crate :: Readable for TsensorAutoRefreshCfgSpec { }
#[doc = "`write(|w| ..)` method takes [`tsensor_auto_refresh_cfg::W`](W) writer structure"] impl crate :: Writable for TsensorAutoRefreshCfgSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TSENSOR_AUTO_REFRESH_CFG to value 0"] impl crate :: Resettable for TsensorAutoRefreshCfgSpec { } } }
#[doc = "Timer module with 3 independent 32-bit timers (v150)"] pub type Timer = crate :: Periph < timer :: RegisterBlock , 0x4400_2000 > ; impl core :: fmt :: Debug for Timer { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Timer") . finish () } }
#[doc = "Timer module with 3 independent 32-bit timers (v150)"] pub mod timer {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x60] , abnor_intr_raw : AbnorIntrRaw , abnor_imsk : AbnorImsk , abnor_intr_stat : AbnorIntrStat , _reserved3 : [u8 ; 0x0c] , eoi_ren : EoiRen , raw_intr_stat : RawIntrStat , intr_stat : IntrStat , _reserved6 : [u8 ; 0x7c] , timer0_load_count : () , _reserved7 : [u8 ; 0x08] , timer0_current_value : () , _reserved8 : [u8 ; 0x08] , timer0_control : () , _reserved9 : [u8 ; 0x04] , timer0_eoi : () , _reserved10 : [u8 ; 0x04] , timer0_raw_intr : () , } impl RegisterBlock {
#[doc = "0x60 - Abnormal interrupt raw status"]
#[inline (always)] pub const fn abnor_intr_raw (& self) -> & AbnorIntrRaw { & self . abnor_intr_raw }
#[doc = "0x64 - Abnormal interrupt mask"]
#[inline (always)] pub const fn abnor_imsk (& self) -> & AbnorImsk { & self . abnor_imsk }
#[doc = "0x68 - Abnormal interrupt status"]
#[inline (always)] pub const fn abnor_intr_stat (& self) -> & AbnorIntrStat { & self . abnor_intr_stat }
#[doc = "0x78 - End-of-interrupt register"]
#[inline (always)] pub const fn eoi_ren (& self) -> & EoiRen { & self . eoi_ren }
#[doc = "0x7c - Raw interrupt status"]
#[inline (always)] pub const fn raw_intr_stat (& self) -> & RawIntrStat { & self . raw_intr_stat }
#[doc = "0x80 - Interrupt status (masked)"]
#[inline (always)] pub const fn intr_stat (& self) -> & IntrStat { & self . intr_stat }
#[doc = "0x100..0x10c - Timer %s \\[dim=3\\] load count"]
#[inline (always)] pub const fn timer0_load_count (& self , n : usize) -> & TimerLoadCount {
#[allow (clippy :: no_effect)] [() ; 3] [n] ; unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (256) . add (256 * n) . cast () } }
#[doc = "Iterator for array of:"]
#[doc = "0x100..0x10c - Timer %s \\[dim=3\\] load count"]
#[inline (always)] pub fn timer0_load_count_iter (& self) -> impl Iterator < Item = & TimerLoadCount > { (0 .. 3) . map (move | n | unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (256) . add (256 * n) . cast () }) }
#[doc = "0x200 - Timer 1 \\[dim=3\\] load count"]
#[inline (always)] pub const fn timer1_load_count (& self) -> & TimerLoadCount { self . timer0_load_count (1) }
#[doc = "0x300 - Timer 2 \\[dim=3\\] load count"]
#[inline (always)] pub const fn timer2_load_count (& self) -> & TimerLoadCount { self . timer0_load_count (2) }
#[doc = "0x108..0x114 - Timer %s \\[dim=3\\] current value"]
#[inline (always)] pub const fn timer0_current_value (& self , n : usize) -> & TimerCurrentValue {
#[allow (clippy :: no_effect)] [() ; 3] [n] ; unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (264) . add (256 * n) . cast () } }
#[doc = "Iterator for array of:"]
#[doc = "0x108..0x114 - Timer %s \\[dim=3\\] current value"]
#[inline (always)] pub fn timer0_current_value_iter (& self) -> impl Iterator < Item = & TimerCurrentValue > { (0 .. 3) . map (move | n | unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (264) . add (256 * n) . cast () }) }
#[doc = "0x208 - Timer 1 \\[dim=3\\] current value"]
#[inline (always)] pub const fn timer1_current_value (& self) -> & TimerCurrentValue { self . timer0_current_value (1) }
#[doc = "0x308 - Timer 2 \\[dim=3\\] current value"]
#[inline (always)] pub const fn timer2_current_value (& self) -> & TimerCurrentValue { self . timer0_current_value (2) }
#[doc = "0x110..0x11c - Timer %s \\[dim=3\\] control register"]
#[inline (always)] pub const fn timer0_control (& self , n : usize) -> & TimerControl {
#[allow (clippy :: no_effect)] [() ; 3] [n] ; unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (272) . add (256 * n) . cast () } }
#[doc = "Iterator for array of:"]
#[doc = "0x110..0x11c - Timer %s \\[dim=3\\] control register"]
#[inline (always)] pub fn timer0_control_iter (& self) -> impl Iterator < Item = & TimerControl > { (0 .. 3) . map (move | n | unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (272) . add (256 * n) . cast () }) }
#[doc = "0x210 - Timer 1 \\[dim=3\\] control register"]
#[inline (always)] pub const fn timer1_control (& self) -> & TimerControl { self . timer0_control (1) }
#[doc = "0x310 - Timer 2 \\[dim=3\\] control register"]
#[inline (always)] pub const fn timer2_control (& self) -> & TimerControl { self . timer0_control (2) }
#[doc = "0x114..0x120 - Timer %s \\[dim=3\\] end-of-interrupt"]
#[inline (always)] pub const fn timer0_eoi (& self , n : usize) -> & TimerEoi {
#[allow (clippy :: no_effect)] [() ; 3] [n] ; unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (276) . add (256 * n) . cast () } }
#[doc = "Iterator for array of:"]
#[doc = "0x114..0x120 - Timer %s \\[dim=3\\] end-of-interrupt"]
#[inline (always)] pub fn timer0_eoi_iter (& self) -> impl Iterator < Item = & TimerEoi > { (0 .. 3) . map (move | n | unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (276) . add (256 * n) . cast () }) }
#[doc = "0x214 - Timer 1 \\[dim=3\\] end-of-interrupt"]
#[inline (always)] pub const fn timer1_eoi (& self) -> & TimerEoi { self . timer0_eoi (1) }
#[doc = "0x314 - Timer 2 \\[dim=3\\] end-of-interrupt"]
#[inline (always)] pub const fn timer2_eoi (& self) -> & TimerEoi { self . timer0_eoi (2) }
#[doc = "0x118..0x124 - Timer %s \\[dim=3\\] raw interrupt status"]
#[inline (always)] pub const fn timer0_raw_intr (& self , n : usize) -> & TimerRawIntr {
#[allow (clippy :: no_effect)] [() ; 3] [n] ; unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (280) . add (256 * n) . cast () } }
#[doc = "Iterator for array of:"]
#[doc = "0x118..0x124 - Timer %s \\[dim=3\\] raw interrupt status"]
#[inline (always)] pub fn timer0_raw_intr_iter (& self) -> impl Iterator < Item = & TimerRawIntr > { (0 .. 3) . map (move | n | unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (280) . add (256 * n) . cast () }) }
#[doc = "0x218 - Timer 1 \\[dim=3\\] raw interrupt status"]
#[inline (always)] pub const fn timer1_raw_intr (& self) -> & TimerRawIntr { self . timer0_raw_intr (1) }
#[doc = "0x318 - Timer 2 \\[dim=3\\] raw interrupt status"]
#[inline (always)] pub const fn timer2_raw_intr (& self) -> & TimerRawIntr { self . timer0_raw_intr (2) } }
#[doc = "ABNOR_INTR_RAW (rw) register accessor: Abnormal interrupt raw status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_intr_raw`] module"]
#[doc (alias = "ABNOR_INTR_RAW")] pub type AbnorIntrRaw = crate :: Reg < abnor_intr_raw :: AbnorIntrRawSpec > ;
#[doc = "Abnormal interrupt raw status"] pub mod abnor_intr_raw {
#[doc = "Register `ABNOR_INTR_RAW` reader"] pub type R = crate :: R < AbnorIntrRawSpec > ;
#[doc = "Register `ABNOR_INTR_RAW` writer"] pub type W = crate :: W < AbnorIntrRawSpec > ;
#[doc = "Field `abnor_intr_raw` reader - Abnormal interrupt raw status for all timers"] pub type AbnorIntrRawR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:2 - Abnormal interrupt raw status for all timers"]
#[inline (always)] pub fn abnor_intr_raw (& self) -> AbnorIntrRawR { AbnorIntrRawR :: new ((self . bits & 7) as u8) } } impl W { }
#[doc = "Abnormal interrupt raw status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AbnorIntrRawSpec ; impl crate :: RegisterSpec for AbnorIntrRawSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`abnor_intr_raw::R`](R) reader structure"] impl crate :: Readable for AbnorIntrRawSpec { }
#[doc = "`write(|w| ..)` method takes [`abnor_intr_raw::W`](W) writer structure"] impl crate :: Writable for AbnorIntrRawSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets ABNOR_INTR_RAW to value 0"] impl crate :: Resettable for AbnorIntrRawSpec { } }
#[doc = "ABNOR_IMSK (rw) register accessor: Abnormal interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_imsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_imsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_imsk`] module"]
#[doc (alias = "ABNOR_IMSK")] pub type AbnorImsk = crate :: Reg < abnor_imsk :: AbnorImskSpec > ;
#[doc = "Abnormal interrupt mask"] pub mod abnor_imsk {
#[doc = "Register `ABNOR_IMSK` reader"] pub type R = crate :: R < AbnorImskSpec > ;
#[doc = "Register `ABNOR_IMSK` writer"] pub type W = crate :: W < AbnorImskSpec > ;
#[doc = "Field `abnor_imsk` reader - Abnormal interrupt mask for all timers"] pub type AbnorImskR = crate :: FieldReader ;
#[doc = "Field `abnor_imsk` writer - Abnormal interrupt mask for all timers"] pub type AbnorImskW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - Abnormal interrupt mask for all timers"]
#[inline (always)] pub fn abnor_imsk (& self) -> AbnorImskR { AbnorImskR :: new ((self . bits & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - Abnormal interrupt mask for all timers"]
#[inline (always)] pub fn abnor_imsk (& mut self) -> AbnorImskW < '_ , AbnorImskSpec > { AbnorImskW :: new (self , 0) } }
#[doc = "Abnormal interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_imsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_imsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AbnorImskSpec ; impl crate :: RegisterSpec for AbnorImskSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`abnor_imsk::R`](R) reader structure"] impl crate :: Readable for AbnorImskSpec { }
#[doc = "`write(|w| ..)` method takes [`abnor_imsk::W`](W) writer structure"] impl crate :: Writable for AbnorImskSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets ABNOR_IMSK to value 0"] impl crate :: Resettable for AbnorImskSpec { } }
#[doc = "ABNOR_INTR_STAT (rw) register accessor: Abnormal interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_intr_stat`] module"]
#[doc (alias = "ABNOR_INTR_STAT")] pub type AbnorIntrStat = crate :: Reg < abnor_intr_stat :: AbnorIntrStatSpec > ;
#[doc = "Abnormal interrupt status"] pub mod abnor_intr_stat {
#[doc = "Register `ABNOR_INTR_STAT` reader"] pub type R = crate :: R < AbnorIntrStatSpec > ;
#[doc = "Register `ABNOR_INTR_STAT` writer"] pub type W = crate :: W < AbnorIntrStatSpec > ;
#[doc = "Field `abnor_intr_stat` reader - Abnormal interrupt status for all timers"] pub type AbnorIntrStatR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:2 - Abnormal interrupt status for all timers"]
#[inline (always)] pub fn abnor_intr_stat (& self) -> AbnorIntrStatR { AbnorIntrStatR :: new ((self . bits & 7) as u8) } } impl W { }
#[doc = "Abnormal interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AbnorIntrStatSpec ; impl crate :: RegisterSpec for AbnorIntrStatSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`abnor_intr_stat::R`](R) reader structure"] impl crate :: Readable for AbnorIntrStatSpec { }
#[doc = "`write(|w| ..)` method takes [`abnor_intr_stat::W`](W) writer structure"] impl crate :: Writable for AbnorIntrStatSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets ABNOR_INTR_STAT to value 0"] impl crate :: Resettable for AbnorIntrStatSpec { } }
#[doc = "EOI_REN (rw) register accessor: End-of-interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi_ren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi_ren`] module"]
#[doc (alias = "EOI_REN")] pub type EoiRen = crate :: Reg < eoi_ren :: EoiRenSpec > ;
#[doc = "End-of-interrupt register"] pub mod eoi_ren {
#[doc = "Register `EOI_REN` reader"] pub type R = crate :: R < EoiRenSpec > ;
#[doc = "Register `EOI_REN` writer"] pub type W = crate :: W < EoiRenSpec > ;
#[doc = "Field `eoi` reader - Clear interrupts for all timers (read to clear)"] pub type EoiR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:2 - Clear interrupts for all timers (read to clear)"]
#[inline (always)] pub fn eoi (& self) -> EoiR { EoiR :: new ((self . bits & 7) as u8) } } impl W { }
#[doc = "End-of-interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi_ren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EoiRenSpec ; impl crate :: RegisterSpec for EoiRenSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`eoi_ren::R`](R) reader structure"] impl crate :: Readable for EoiRenSpec { }
#[doc = "`write(|w| ..)` method takes [`eoi_ren::W`](W) writer structure"] impl crate :: Writable for EoiRenSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets EOI_REN to value 0"] impl crate :: Resettable for EoiRenSpec { } }
#[doc = "RAW_INTR_STAT (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"]
#[doc (alias = "RAW_INTR_STAT")] pub type RawIntrStat = crate :: Reg < raw_intr_stat :: RawIntrStatSpec > ;
#[doc = "Raw interrupt status"] pub mod raw_intr_stat {
#[doc = "Register `RAW_INTR_STAT` reader"] pub type R = crate :: R < RawIntrStatSpec > ;
#[doc = "Register `RAW_INTR_STAT` writer"] pub type W = crate :: W < RawIntrStatSpec > ;
#[doc = "Field `raw_intr` reader - Raw interrupt status for all timers"] pub type RawIntrR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:2 - Raw interrupt status for all timers"]
#[inline (always)] pub fn raw_intr (& self) -> RawIntrR { RawIntrR :: new ((self . bits & 7) as u8) } } impl W { }
#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RawIntrStatSpec ; impl crate :: RegisterSpec for RawIntrStatSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`raw_intr_stat::R`](R) reader structure"] impl crate :: Readable for RawIntrStatSpec { }
#[doc = "`write(|w| ..)` method takes [`raw_intr_stat::W`](W) writer structure"] impl crate :: Writable for RawIntrStatSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RAW_INTR_STAT to value 0"] impl crate :: Resettable for RawIntrStatSpec { } }
#[doc = "INTR_STAT (rw) register accessor: Interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"]
#[doc (alias = "INTR_STAT")] pub type IntrStat = crate :: Reg < intr_stat :: IntrStatSpec > ;
#[doc = "Interrupt status (masked)"] pub mod intr_stat {
#[doc = "Register `INTR_STAT` reader"] pub type R = crate :: R < IntrStatSpec > ;
#[doc = "Register `INTR_STAT` writer"] pub type W = crate :: W < IntrStatSpec > ;
#[doc = "Field `intr_stat` reader - Interrupt status for all timers (after mask)"] pub type IntrStatR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:2 - Interrupt status for all timers (after mask)"]
#[inline (always)] pub fn intr_stat (& self) -> IntrStatR { IntrStatR :: new ((self . bits & 7) as u8) } } impl W { }
#[doc = "Interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IntrStatSpec ; impl crate :: RegisterSpec for IntrStatSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`intr_stat::R`](R) reader structure"] impl crate :: Readable for IntrStatSpec { }
#[doc = "`write(|w| ..)` method takes [`intr_stat::W`](W) writer structure"] impl crate :: Writable for IntrStatSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets INTR_STAT to value 0"] impl crate :: Resettable for IntrStatSpec { } }
#[doc = "TIMER_LOAD_COUNT (rw) register accessor: Timer %s \\[dim=3\\] load count\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_load_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_load_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_load_count`] module"]
#[doc (alias = "TIMER_LOAD_COUNT")] pub type TimerLoadCount = crate :: Reg < timer_load_count :: TimerLoadCountSpec > ;
#[doc = "Timer %s \\[dim=3\\] load count"] pub mod timer_load_count {
#[doc = "Register `TIMER%s_LOAD_COUNT` reader"] pub type R = crate :: R < TimerLoadCountSpec > ;
#[doc = "Register `TIMER%s_LOAD_COUNT` writer"] pub type W = crate :: W < TimerLoadCountSpec > ;
#[doc = "Field `load_count` reader - Timer 0 load count value"] pub type LoadCountR = crate :: FieldReader < u32 > ;
#[doc = "Field `load_count` writer - Timer 0 load count value"] pub type LoadCountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Timer 0 load count value"]
#[inline (always)] pub fn load_count (& self) -> LoadCountR { LoadCountR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Timer 0 load count value"]
#[inline (always)] pub fn load_count (& mut self) -> LoadCountW < '_ , TimerLoadCountSpec > { LoadCountW :: new (self , 0) } }
#[doc = "Timer %s \\[dim=3\\] load count\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_load_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_load_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TimerLoadCountSpec ; impl crate :: RegisterSpec for TimerLoadCountSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`timer_load_count::R`](R) reader structure"] impl crate :: Readable for TimerLoadCountSpec { }
#[doc = "`write(|w| ..)` method takes [`timer_load_count::W`](W) writer structure"] impl crate :: Writable for TimerLoadCountSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TIMER%s_LOAD_COUNT to value 0"] impl crate :: Resettable for TimerLoadCountSpec { } }
#[doc = "TIMER_CURRENT_VALUE (rw) register accessor: Timer %s \\[dim=3\\] current value\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_current_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_current_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_current_value`] module"]
#[doc (alias = "TIMER_CURRENT_VALUE")] pub type TimerCurrentValue = crate :: Reg < timer_current_value :: TimerCurrentValueSpec > ;
#[doc = "Timer %s \\[dim=3\\] current value"] pub mod timer_current_value {
#[doc = "Register `TIMER%s_CURRENT_VALUE` reader"] pub type R = crate :: R < TimerCurrentValueSpec > ;
#[doc = "Register `TIMER%s_CURRENT_VALUE` writer"] pub type W = crate :: W < TimerCurrentValueSpec > ;
#[doc = "Field `current_value` reader - Timer 0 current count value"] pub type CurrentValueR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - Timer 0 current count value"]
#[inline (always)] pub fn current_value (& self) -> CurrentValueR { CurrentValueR :: new (self . bits) } } impl W { }
#[doc = "Timer %s \\[dim=3\\] current value\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_current_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_current_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TimerCurrentValueSpec ; impl crate :: RegisterSpec for TimerCurrentValueSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`timer_current_value::R`](R) reader structure"] impl crate :: Readable for TimerCurrentValueSpec { }
#[doc = "`write(|w| ..)` method takes [`timer_current_value::W`](W) writer structure"] impl crate :: Writable for TimerCurrentValueSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TIMER%s_CURRENT_VALUE to value 0"] impl crate :: Resettable for TimerCurrentValueSpec { } }
#[doc = "TIMER_CONTROL (rw) register accessor: Timer %s \\[dim=3\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_control`] module"]
#[doc (alias = "TIMER_CONTROL")] pub type TimerControl = crate :: Reg < timer_control :: TimerControlSpec > ;
#[doc = "Timer %s \\[dim=3\\] control register"] pub mod timer_control {
#[doc = "Register `TIMER%s_CONTROL` reader"] pub type R = crate :: R < TimerControlSpec > ;
#[doc = "Register `TIMER%s_CONTROL` writer"] pub type W = crate :: W < TimerControlSpec > ;
#[doc = "Field `enable` reader - Timer enable: 0=disabled; 1=enabled"] pub type EnableR = crate :: BitReader ;
#[doc = "Field `enable` writer - Timer enable: 0=disabled; 1=enabled"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Timer mode: 00=free running; 01=one-shot; 10=periodic\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum Mode {
#[doc = "0: Free-running mode"] FreeRunning = 0 ,
#[doc = "1: One-shot mode"] OneShot = 1 ,
#[doc = "2: Periodic mode"] Periodic = 2 , } impl From < Mode > for u8 {
#[inline (always)] fn from (variant : Mode) -> Self { variant as _ } } impl crate :: FieldSpec for Mode { type Ux = u8 ; } impl crate :: IsEnum for Mode { }
#[doc = "Field `mode` reader - Timer mode: 00=free running; 01=one-shot; 10=periodic"] pub type ModeR = crate :: FieldReader < Mode > ; impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < Mode > { match self . bits { 0 => Some (Mode :: FreeRunning) , 1 => Some (Mode :: OneShot) , 2 => Some (Mode :: Periodic) , _ => None , } }
#[doc = "Free-running mode"]
#[inline (always)] pub fn is_free_running (& self) -> bool { * self == Mode :: FreeRunning }
#[doc = "One-shot mode"]
#[inline (always)] pub fn is_one_shot (& self) -> bool { * self == Mode :: OneShot }
#[doc = "Periodic mode"]
#[inline (always)] pub fn is_periodic (& self) -> bool { * self == Mode :: Periodic } }
#[doc = "Field `mode` writer - Timer mode: 00=free running; 01=one-shot; 10=periodic"] pub type ModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , Mode > ; impl < 'a , REG > ModeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Free-running mode"]
#[inline (always)] pub fn free_running (self) -> & 'a mut crate :: W < REG > { self . variant (Mode :: FreeRunning) }
#[doc = "One-shot mode"]
#[inline (always)] pub fn one_shot (self) -> & 'a mut crate :: W < REG > { self . variant (Mode :: OneShot) }
#[doc = "Periodic mode"]
#[inline (always)] pub fn periodic (self) -> & 'a mut crate :: W < REG > { self . variant (Mode :: Periodic) } }
#[doc = "Field `int_mask` reader - Interrupt mask: 0=unmasked; 1=masked"] pub type IntMaskR = crate :: BitReader ;
#[doc = "Field `int_mask` writer - Interrupt mask: 0=unmasked; 1=masked"] pub type IntMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rstfsm` writer - Reset FSM: 1=reset timer FSM"] pub type RstfsmW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Timer enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 1) != 0) }
#[doc = "Bits 1:2 - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
#[inline (always)] pub fn mode (& self) -> ModeR { ModeR :: new (((self . bits >> 1) & 3) as u8) }
#[doc = "Bit 3 - Interrupt mask: 0=unmasked; 1=masked"]
#[inline (always)] pub fn int_mask (& self) -> IntMaskR { IntMaskR :: new (((self . bits >> 3) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Timer enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn enable (& mut self) -> EnableW < '_ , TimerControlSpec > { EnableW :: new (self , 0) }
#[doc = "Bits 1:2 - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
#[inline (always)] pub fn mode (& mut self) -> ModeW < '_ , TimerControlSpec > { ModeW :: new (self , 1) }
#[doc = "Bit 3 - Interrupt mask: 0=unmasked; 1=masked"]
#[inline (always)] pub fn int_mask (& mut self) -> IntMaskW < '_ , TimerControlSpec > { IntMaskW :: new (self , 3) }
#[doc = "Bit 4 - Reset FSM: 1=reset timer FSM"]
#[inline (always)] pub fn rstfsm (& mut self) -> RstfsmW < '_ , TimerControlSpec > { RstfsmW :: new (self , 4) } }
#[doc = "Timer %s \\[dim=3\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TimerControlSpec ; impl crate :: RegisterSpec for TimerControlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`timer_control::R`](R) reader structure"] impl crate :: Readable for TimerControlSpec { }
#[doc = "`write(|w| ..)` method takes [`timer_control::W`](W) writer structure"] impl crate :: Writable for TimerControlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TIMER%s_CONTROL to value 0"] impl crate :: Resettable for TimerControlSpec { } }
#[doc = "TIMER_EOI (rw) register accessor: Timer %s \\[dim=3\\] end-of-interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_eoi`] module"]
#[doc (alias = "TIMER_EOI")] pub type TimerEoi = crate :: Reg < timer_eoi :: TimerEoiSpec > ;
#[doc = "Timer %s \\[dim=3\\] end-of-interrupt"] pub mod timer_eoi {
#[doc = "Register `TIMER%s_EOI` reader"] pub type R = crate :: R < TimerEoiSpec > ;
#[doc = "Register `TIMER%s_EOI` writer"] pub type W = crate :: W < TimerEoiSpec > ;
#[doc = "Field `eoi` reader - Read to clear timer 0 interrupt"] pub type EoiR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Read to clear timer 0 interrupt"]
#[inline (always)] pub fn eoi (& self) -> EoiR { EoiR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "Timer %s \\[dim=3\\] end-of-interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TimerEoiSpec ; impl crate :: RegisterSpec for TimerEoiSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`timer_eoi::R`](R) reader structure"] impl crate :: Readable for TimerEoiSpec { }
#[doc = "`write(|w| ..)` method takes [`timer_eoi::W`](W) writer structure"] impl crate :: Writable for TimerEoiSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TIMER%s_EOI to value 0"] impl crate :: Resettable for TimerEoiSpec { } }
#[doc = "TIMER_RAW_INTR (rw) register accessor: Timer %s \\[dim=3\\] raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_raw_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_raw_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_raw_intr`] module"]
#[doc (alias = "TIMER_RAW_INTR")] pub type TimerRawIntr = crate :: Reg < timer_raw_intr :: TimerRawIntrSpec > ;
#[doc = "Timer %s \\[dim=3\\] raw interrupt status"] pub mod timer_raw_intr {
#[doc = "Register `TIMER%s_RAW_INTR` reader"] pub type R = crate :: R < TimerRawIntrSpec > ;
#[doc = "Register `TIMER%s_RAW_INTR` writer"] pub type W = crate :: W < TimerRawIntrSpec > ;
#[doc = "Field `raw_intr` reader - Raw interrupt status"] pub type RawIntrR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Raw interrupt status"]
#[inline (always)] pub fn raw_intr (& self) -> RawIntrR { RawIntrR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "Timer %s \\[dim=3\\] raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_raw_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_raw_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TimerRawIntrSpec ; impl crate :: RegisterSpec for TimerRawIntrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`timer_raw_intr::R`](R) reader structure"] impl crate :: Readable for TimerRawIntrSpec { }
#[doc = "`write(|w| ..)` method takes [`timer_raw_intr::W`](W) writer structure"] impl crate :: Writable for TimerRawIntrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TIMER%s_RAW_INTR to value 0"] impl crate :: Resettable for TimerRawIntrSpec { } } }
#[doc = "Watchdog timer (v151)"] pub type Wdt = crate :: Periph < wdt :: RegisterBlock , 0x4000_6000 > ; impl core :: fmt :: Debug for Wdt { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Wdt") . finish () } }
#[doc = "Watchdog timer (v151)"] pub mod wdt {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { wdt_lock : WdtLock , wdt_load : WdtLoad , wdt_restart : WdtRestart , wdt_eoi : WdtEoi , wdt_cr : WdtCr , wdt_cnt : WdtCnt , wdt_raw_intr : WdtRawIntr , wdt_intr : WdtIntr , wdt_lpif_state : WdtLpifState , wdt_status : WdtStatus , wdt_ccvr_en : WdtCcvrEn , } impl RegisterBlock {
#[doc = "0x00 - Watchdog lock register"]
#[inline (always)] pub const fn wdt_lock (& self) -> & WdtLock { & self . wdt_lock }
#[doc = "0x04 - Watchdog load value"]
#[inline (always)] pub const fn wdt_load (& self) -> & WdtLoad { & self . wdt_load }
#[doc = "0x08 - Watchdog restart register"]
#[inline (always)] pub const fn wdt_restart (& self) -> & WdtRestart { & self . wdt_restart }
#[doc = "0x0c - Watchdog interrupt clear (read to clear)"]
#[inline (always)] pub const fn wdt_eoi (& self) -> & WdtEoi { & self . wdt_eoi }
#[doc = "0x10 - Watchdog control register"]
#[inline (always)] pub const fn wdt_cr (& self) -> & WdtCr { & self . wdt_cr }
#[doc = "0x14 - Watchdog current counter value"]
#[inline (always)] pub const fn wdt_cnt (& self) -> & WdtCnt { & self . wdt_cnt }
#[doc = "0x18 - Watchdog raw interrupt status"]
#[inline (always)] pub const fn wdt_raw_intr (& self) -> & WdtRawIntr { & self . wdt_raw_intr }
#[doc = "0x1c - Watchdog interrupt status (masked)"]
#[inline (always)] pub const fn wdt_intr (& self) -> & WdtIntr { & self . wdt_intr }
#[doc = "0x20 - Watchdog low power state"]
#[inline (always)] pub const fn wdt_lpif_state (& self) -> & WdtLpifState { & self . wdt_lpif_state }
#[doc = "0x24 - Watchdog status"]
#[inline (always)] pub const fn wdt_status (& self) -> & WdtStatus { & self . wdt_status }
#[doc = "0x28 - Watchdog counter value request"]
#[inline (always)] pub const fn wdt_ccvr_en (& self) -> & WdtCcvrEn { & self . wdt_ccvr_en } }
#[doc = "WDT_LOCK (rw) register accessor: Watchdog lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_lock`] module"]
#[doc (alias = "WDT_LOCK")] pub type WdtLock = crate :: Reg < wdt_lock :: WdtLockSpec > ;
#[doc = "Watchdog lock register"] pub mod wdt_lock {
#[doc = "Register `WDT_LOCK` reader"] pub type R = crate :: R < WdtLockSpec > ;
#[doc = "Register `WDT_LOCK` writer"] pub type W = crate :: W < WdtLockSpec > ;
#[doc = "Field `wdt_lock` writer - Write 0x5A5A5A5A to unlock, other values lock"] pub type WdtLockW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl W {
#[doc = "Bits 0:31 - Write 0x5A5A5A5A to unlock, other values lock"]
#[inline (always)] pub fn wdt_lock (& mut self) -> WdtLockW < '_ , WdtLockSpec > { WdtLockW :: new (self , 0) } }
#[doc = "Watchdog lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtLockSpec ; impl crate :: RegisterSpec for WdtLockSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_lock::R`](R) reader structure"] impl crate :: Readable for WdtLockSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_lock::W`](W) writer structure"] impl crate :: Writable for WdtLockSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_LOCK to value 0"] impl crate :: Resettable for WdtLockSpec { } }
#[doc = "WDT_LOAD (rw) register accessor: Watchdog load value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_load::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_load::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_load`] module"]
#[doc (alias = "WDT_LOAD")] pub type WdtLoad = crate :: Reg < wdt_load :: WdtLoadSpec > ;
#[doc = "Watchdog load value"] pub mod wdt_load {
#[doc = "Register `WDT_LOAD` reader"] pub type R = crate :: R < WdtLoadSpec > ;
#[doc = "Register `WDT_LOAD` writer"] pub type W = crate :: W < WdtLoadSpec > ;
#[doc = "Field `wdt_load` reader - Load count value (24-bit, low 8 bits reserved)"] pub type WdtLoadR = crate :: FieldReader < u32 > ;
#[doc = "Field `wdt_load` writer - Load count value (24-bit, low 8 bits reserved)"] pub type WdtLoadW < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; impl R {
#[doc = "Bits 8:31 - Load count value (24-bit, low 8 bits reserved)"]
#[inline (always)] pub fn wdt_load (& self) -> WdtLoadR { WdtLoadR :: new ((self . bits >> 8) & 0x00ff_ffff) } } impl W {
#[doc = "Bits 8:31 - Load count value (24-bit, low 8 bits reserved)"]
#[inline (always)] pub fn wdt_load (& mut self) -> WdtLoadW < '_ , WdtLoadSpec > { WdtLoadW :: new (self , 8) } }
#[doc = "Watchdog load value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_load::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_load::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtLoadSpec ; impl crate :: RegisterSpec for WdtLoadSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_load::R`](R) reader structure"] impl crate :: Readable for WdtLoadSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_load::W`](W) writer structure"] impl crate :: Writable for WdtLoadSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_LOAD to value 0"] impl crate :: Resettable for WdtLoadSpec { } }
#[doc = "WDT_RESTART (rw) register accessor: Watchdog restart register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_restart::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_restart::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_restart`] module"]
#[doc (alias = "WDT_RESTART")] pub type WdtRestart = crate :: Reg < wdt_restart :: WdtRestartSpec > ;
#[doc = "Watchdog restart register"] pub mod wdt_restart {
#[doc = "Register `WDT_RESTART` reader"] pub type R = crate :: R < WdtRestartSpec > ;
#[doc = "Register `WDT_RESTART` writer"] pub type W = crate :: W < WdtRestartSpec > ;
#[doc = "Field `wdt_restart` writer - Write anything except 0x5A5A5A5A to restart counter"] pub type WdtRestartW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl W {
#[doc = "Bits 0:31 - Write anything except 0x5A5A5A5A to restart counter"]
#[inline (always)] pub fn wdt_restart (& mut self) -> WdtRestartW < '_ , WdtRestartSpec > { WdtRestartW :: new (self , 0) } }
#[doc = "Watchdog restart register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_restart::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_restart::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtRestartSpec ; impl crate :: RegisterSpec for WdtRestartSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_restart::R`](R) reader structure"] impl crate :: Readable for WdtRestartSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_restart::W`](W) writer structure"] impl crate :: Writable for WdtRestartSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_RESTART to value 0"] impl crate :: Resettable for WdtRestartSpec { } }
#[doc = "WDT_EOI (rw) register accessor: Watchdog interrupt clear (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_eoi`] module"]
#[doc (alias = "WDT_EOI")] pub type WdtEoi = crate :: Reg < wdt_eoi :: WdtEoiSpec > ;
#[doc = "Watchdog interrupt clear (read to clear)"] pub mod wdt_eoi {
#[doc = "Register `WDT_EOI` reader"] pub type R = crate :: R < WdtEoiSpec > ;
#[doc = "Register `WDT_EOI` writer"] pub type W = crate :: W < WdtEoiSpec > ;
#[doc = "Field `wdt_eoi` reader - Read to clear watchdog interrupt"] pub type WdtEoiR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Read to clear watchdog interrupt"]
#[inline (always)] pub fn wdt_eoi (& self) -> WdtEoiR { WdtEoiR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "Watchdog interrupt clear (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtEoiSpec ; impl crate :: RegisterSpec for WdtEoiSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_eoi::R`](R) reader structure"] impl crate :: Readable for WdtEoiSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_eoi::W`](W) writer structure"] impl crate :: Writable for WdtEoiSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_EOI to value 0"] impl crate :: Resettable for WdtEoiSpec { } }
#[doc = "WDT_CR (rw) register accessor: Watchdog control register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cr`] module"]
#[doc (alias = "WDT_CR")] pub type WdtCr = crate :: Reg < wdt_cr :: WdtCrSpec > ;
#[doc = "Watchdog control register"] pub mod wdt_cr {
#[doc = "Register `WDT_CR` reader"] pub type R = crate :: R < WdtCrSpec > ;
#[doc = "Register `WDT_CR` writer"] pub type W = crate :: W < WdtCrSpec > ;
#[doc = "Field `wdt_en` reader - Watchdog enable: 0=disabled; 1=enabled"] pub type WdtEnR = crate :: BitReader ;
#[doc = "Field `wdt_en` writer - Watchdog enable: 0=disabled; 1=enabled"] pub type WdtEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rst_en` reader - Reset enable: 0=no reset on timeout; 1=reset on timeout"] pub type RstEnR = crate :: BitReader ;
#[doc = "Field `rst_en` writer - Reset enable: 0=no reset on timeout; 1=reset on timeout"] pub type RstEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `rst_pl` reader - Reset pulse length: 000=2 clocks; up to 111=256 clocks"] pub type RstPlR = crate :: FieldReader ;
#[doc = "Field `rst_pl` writer - Reset pulse length: 000=2 clocks; up to 111=256 clocks"] pub type RstPlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `wdt_imsk` reader - Interrupt mask: 0=unmasked; 1=masked"] pub type WdtImskR = crate :: BitReader ;
#[doc = "Field `wdt_imsk` writer - Interrupt mask: 0=unmasked; 1=masked"] pub type WdtImskW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Mode: 0=one interrupt then reset; 1=two interrupts then reset\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum WdtMode {
#[doc = "0: Single interrupt then reset"] Mode1 = 0 ,
#[doc = "1: Two interrupts then reset"] Mode2 = 1 , } impl From < WdtMode > for bool {
#[inline (always)] fn from (variant : WdtMode) -> Self { variant as u8 != 0 } }
#[doc = "Field `wdt_mode` reader - Mode: 0=one interrupt then reset; 1=two interrupts then reset"] pub type WdtModeR = crate :: BitReader < WdtMode > ; impl WdtModeR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> WdtMode { match self . bits { false => WdtMode :: Mode1 , true => WdtMode :: Mode2 , } }
#[doc = "Single interrupt then reset"]
#[inline (always)] pub fn is_mode1 (& self) -> bool { * self == WdtMode :: Mode1 }
#[doc = "Two interrupts then reset"]
#[inline (always)] pub fn is_mode2 (& self) -> bool { * self == WdtMode :: Mode2 } }
#[doc = "Field `wdt_mode` writer - Mode: 0=one interrupt then reset; 1=two interrupts then reset"] pub type WdtModeW < 'a , REG > = crate :: BitWriter < 'a , REG , WdtMode > ; impl < 'a , REG > WdtModeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , {
#[doc = "Single interrupt then reset"]
#[inline (always)] pub fn mode1 (self) -> & 'a mut crate :: W < REG > { self . variant (WdtMode :: Mode1) }
#[doc = "Two interrupts then reset"]
#[inline (always)] pub fn mode2 (self) -> & 'a mut crate :: W < REG > { self . variant (WdtMode :: Mode2) } } impl R {
#[doc = "Bit 0 - Watchdog enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn wdt_en (& self) -> WdtEnR { WdtEnR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 2 - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
#[inline (always)] pub fn rst_en (& self) -> RstEnR { RstEnR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bits 3:5 - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
#[inline (always)] pub fn rst_pl (& self) -> RstPlR { RstPlR :: new (((self . bits >> 3) & 7) as u8) }
#[doc = "Bit 6 - Interrupt mask: 0=unmasked; 1=masked"]
#[inline (always)] pub fn wdt_imsk (& self) -> WdtImskR { WdtImskR :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 7 - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
#[inline (always)] pub fn wdt_mode (& self) -> WdtModeR { WdtModeR :: new (((self . bits >> 7) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Watchdog enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn wdt_en (& mut self) -> WdtEnW < '_ , WdtCrSpec > { WdtEnW :: new (self , 0) }
#[doc = "Bit 2 - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
#[inline (always)] pub fn rst_en (& mut self) -> RstEnW < '_ , WdtCrSpec > { RstEnW :: new (self , 2) }
#[doc = "Bits 3:5 - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
#[inline (always)] pub fn rst_pl (& mut self) -> RstPlW < '_ , WdtCrSpec > { RstPlW :: new (self , 3) }
#[doc = "Bit 6 - Interrupt mask: 0=unmasked; 1=masked"]
#[inline (always)] pub fn wdt_imsk (& mut self) -> WdtImskW < '_ , WdtCrSpec > { WdtImskW :: new (self , 6) }
#[doc = "Bit 7 - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
#[inline (always)] pub fn wdt_mode (& mut self) -> WdtModeW < '_ , WdtCrSpec > { WdtModeW :: new (self , 7) } }
#[doc = "Watchdog control register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtCrSpec ; impl crate :: RegisterSpec for WdtCrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_cr::R`](R) reader structure"] impl crate :: Readable for WdtCrSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_cr::W`](W) writer structure"] impl crate :: Writable for WdtCrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_CR to value 0"] impl crate :: Resettable for WdtCrSpec { } }
#[doc = "WDT_CNT (rw) register accessor: Watchdog current counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cnt`] module"]
#[doc (alias = "WDT_CNT")] pub type WdtCnt = crate :: Reg < wdt_cnt :: WdtCntSpec > ;
#[doc = "Watchdog current counter value"] pub mod wdt_cnt {
#[doc = "Register `WDT_CNT` reader"] pub type R = crate :: R < WdtCntSpec > ;
#[doc = "Register `WDT_CNT` writer"] pub type W = crate :: W < WdtCntSpec > ;
#[doc = "Field `wdt_cnt` reader - Current counter value"] pub type WdtCntR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - Current counter value"]
#[inline (always)] pub fn wdt_cnt (& self) -> WdtCntR { WdtCntR :: new (self . bits) } } impl W { }
#[doc = "Watchdog current counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtCntSpec ; impl crate :: RegisterSpec for WdtCntSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_cnt::R`](R) reader structure"] impl crate :: Readable for WdtCntSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_cnt::W`](W) writer structure"] impl crate :: Writable for WdtCntSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_CNT to value 0"] impl crate :: Resettable for WdtCntSpec { } }
#[doc = "WDT_RAW_INTR (rw) register accessor: Watchdog raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_raw_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_raw_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_raw_intr`] module"]
#[doc (alias = "WDT_RAW_INTR")] pub type WdtRawIntr = crate :: Reg < wdt_raw_intr :: WdtRawIntrSpec > ;
#[doc = "Watchdog raw interrupt status"] pub mod wdt_raw_intr {
#[doc = "Register `WDT_RAW_INTR` reader"] pub type R = crate :: R < WdtRawIntrSpec > ;
#[doc = "Register `WDT_RAW_INTR` writer"] pub type W = crate :: W < WdtRawIntrSpec > ;
#[doc = "Field `wdt_raw_intr` reader - Raw interrupt status"] pub type WdtRawIntrR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Raw interrupt status"]
#[inline (always)] pub fn wdt_raw_intr (& self) -> WdtRawIntrR { WdtRawIntrR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "Watchdog raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_raw_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_raw_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtRawIntrSpec ; impl crate :: RegisterSpec for WdtRawIntrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_raw_intr::R`](R) reader structure"] impl crate :: Readable for WdtRawIntrSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_raw_intr::W`](W) writer structure"] impl crate :: Writable for WdtRawIntrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_RAW_INTR to value 0"] impl crate :: Resettable for WdtRawIntrSpec { } }
#[doc = "WDT_INTR (rw) register accessor: Watchdog interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_intr`] module"]
#[doc (alias = "WDT_INTR")] pub type WdtIntr = crate :: Reg < wdt_intr :: WdtIntrSpec > ;
#[doc = "Watchdog interrupt status (masked)"] pub mod wdt_intr {
#[doc = "Register `WDT_INTR` reader"] pub type R = crate :: R < WdtIntrSpec > ;
#[doc = "Register `WDT_INTR` writer"] pub type W = crate :: W < WdtIntrSpec > ;
#[doc = "Field `wdt_intr` reader - Interrupt status after mask"] pub type WdtIntrR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Interrupt status after mask"]
#[inline (always)] pub fn wdt_intr (& self) -> WdtIntrR { WdtIntrR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "Watchdog interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtIntrSpec ; impl crate :: RegisterSpec for WdtIntrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_intr::R`](R) reader structure"] impl crate :: Readable for WdtIntrSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_intr::W`](W) writer structure"] impl crate :: Writable for WdtIntrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_INTR to value 0"] impl crate :: Resettable for WdtIntrSpec { } }
#[doc = "WDT_LPIF_STATE (rw) register accessor: Watchdog low power state\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lpif_state::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lpif_state::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_lpif_state`] module"]
#[doc (alias = "WDT_LPIF_STATE")] pub type WdtLpifState = crate :: Reg < wdt_lpif_state :: WdtLpifStateSpec > ;
#[doc = "Watchdog low power state"] pub mod wdt_lpif_state {
#[doc = "Register `WDT_LPIF_STATE` reader"] pub type R = crate :: R < WdtLpifStateSpec > ;
#[doc = "Register `WDT_LPIF_STATE` writer"] pub type W = crate :: W < WdtLpifStateSpec > ;
#[doc = "Field `wdt_lpif_state` reader - Low power interface state"] pub type WdtLpifStateR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:2 - Low power interface state"]
#[inline (always)] pub fn wdt_lpif_state (& self) -> WdtLpifStateR { WdtLpifStateR :: new ((self . bits & 7) as u8) } } impl W { }
#[doc = "Watchdog low power state\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lpif_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lpif_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtLpifStateSpec ; impl crate :: RegisterSpec for WdtLpifStateSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_lpif_state::R`](R) reader structure"] impl crate :: Readable for WdtLpifStateSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_lpif_state::W`](W) writer structure"] impl crate :: Writable for WdtLpifStateSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_LPIF_STATE to value 0"] impl crate :: Resettable for WdtLpifStateSpec { } }
#[doc = "WDT_STATUS (rw) register accessor: Watchdog status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_status`] module"]
#[doc (alias = "WDT_STATUS")] pub type WdtStatus = crate :: Reg < wdt_status :: WdtStatusSpec > ;
#[doc = "Watchdog status"] pub mod wdt_status {
#[doc = "Register `WDT_STATUS` reader"] pub type R = crate :: R < WdtStatusSpec > ;
#[doc = "Register `WDT_STATUS` writer"] pub type W = crate :: W < WdtStatusSpec > ;
#[doc = "Field `wdt_status` reader - Status: 0=busy; 1=free"] pub type WdtStatusR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Status: 0=busy; 1=free"]
#[inline (always)] pub fn wdt_status (& self) -> WdtStatusR { WdtStatusR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "Watchdog status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtStatusSpec ; impl crate :: RegisterSpec for WdtStatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_status::R`](R) reader structure"] impl crate :: Readable for WdtStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_status::W`](W) writer structure"] impl crate :: Writable for WdtStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_STATUS to value 0"] impl crate :: Resettable for WdtStatusSpec { } }
#[doc = "WDT_CCVR_EN (rw) register accessor: Watchdog counter value request\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_ccvr_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_ccvr_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_ccvr_en`] module"]
#[doc (alias = "WDT_CCVR_EN")] pub type WdtCcvrEn = crate :: Reg < wdt_ccvr_en :: WdtCcvrEnSpec > ;
#[doc = "Watchdog counter value request"] pub mod wdt_ccvr_en {
#[doc = "Register `WDT_CCVR_EN` reader"] pub type R = crate :: R < WdtCcvrEnSpec > ;
#[doc = "Register `WDT_CCVR_EN` writer"] pub type W = crate :: W < WdtCcvrEnSpec > ;
#[doc = "Field `ccvr_req` writer - Write 1 to request current counter value"] pub type CcvrReqW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `ccvr_ack` reader - Acknowledge: 1=counter value valid"] pub type CcvrAckR = crate :: BitReader ; impl R {
#[doc = "Bit 1 - Acknowledge: 1=counter value valid"]
#[inline (always)] pub fn ccvr_ack (& self) -> CcvrAckR { CcvrAckR :: new (((self . bits >> 1) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Write 1 to request current counter value"]
#[inline (always)] pub fn ccvr_req (& mut self) -> CcvrReqW < '_ , WdtCcvrEnSpec > { CcvrReqW :: new (self , 0) } }
#[doc = "Watchdog counter value request\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_ccvr_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_ccvr_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WdtCcvrEnSpec ; impl crate :: RegisterSpec for WdtCcvrEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`wdt_ccvr_en::R`](R) reader structure"] impl crate :: Readable for WdtCcvrEnSpec { }
#[doc = "`write(|w| ..)` method takes [`wdt_ccvr_en::W`](W) writer structure"] impl crate :: Writable for WdtCcvrEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets WDT_CCVR_EN to value 0"] impl crate :: Resettable for WdtCcvrEnSpec { } } }
#[doc = "Real-time clock (48-bit free-running counter, v100)"] pub type Rtc = crate :: Periph < rtc :: RegisterBlock , 0x5702_4000 > ; impl core :: fmt :: Debug for Rtc { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Rtc") . finish () } }
#[doc = "Real-time clock (48-bit free-running counter, v100)"] pub mod rtc {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { rtc_load_count : RtcLoadCount , rtc_current_value : RtcCurrentValue , rtc_control : RtcControl , rtc_eoi : RtcEoi , rtc_int_status : RtcIntStatus , } impl RegisterBlock {
#[doc = "0x00 - RTC load count register"]
#[inline (always)] pub const fn rtc_load_count (& self) -> & RtcLoadCount { & self . rtc_load_count }
#[doc = "0x04 - RTC current count value"]
#[inline (always)] pub const fn rtc_current_value (& self) -> & RtcCurrentValue { & self . rtc_current_value }
#[doc = "0x08 - RTC control register"]
#[inline (always)] pub const fn rtc_control (& self) -> & RtcControl { & self . rtc_control }
#[doc = "0x0c - RTC end-of-interrupt (read to clear)"]
#[inline (always)] pub const fn rtc_eoi (& self) -> & RtcEoi { & self . rtc_eoi }
#[doc = "0x10 - RTC interrupt status"]
#[inline (always)] pub const fn rtc_int_status (& self) -> & RtcIntStatus { & self . rtc_int_status } }
#[doc = "RTC_LOAD_COUNT (rw) register accessor: RTC load count register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_load_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_load_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_load_count`] module"]
#[doc (alias = "RTC_LOAD_COUNT")] pub type RtcLoadCount = crate :: Reg < rtc_load_count :: RtcLoadCountSpec > ;
#[doc = "RTC load count register"] pub mod rtc_load_count {
#[doc = "Register `RTC_LOAD_COUNT` reader"] pub type R = crate :: R < RtcLoadCountSpec > ;
#[doc = "Register `RTC_LOAD_COUNT` writer"] pub type W = crate :: W < RtcLoadCountSpec > ;
#[doc = "Field `load_count` reader - Load count value (threshold for interrupt)"] pub type LoadCountR = crate :: FieldReader < u32 > ;
#[doc = "Field `load_count` writer - Load count value (threshold for interrupt)"] pub type LoadCountW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Load count value (threshold for interrupt)"]
#[inline (always)] pub fn load_count (& self) -> LoadCountR { LoadCountR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Load count value (threshold for interrupt)"]
#[inline (always)] pub fn load_count (& mut self) -> LoadCountW < '_ , RtcLoadCountSpec > { LoadCountW :: new (self , 0) } }
#[doc = "RTC load count register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_load_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_load_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RtcLoadCountSpec ; impl crate :: RegisterSpec for RtcLoadCountSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rtc_load_count::R`](R) reader structure"] impl crate :: Readable for RtcLoadCountSpec { }
#[doc = "`write(|w| ..)` method takes [`rtc_load_count::W`](W) writer structure"] impl crate :: Writable for RtcLoadCountSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RTC_LOAD_COUNT to value 0"] impl crate :: Resettable for RtcLoadCountSpec { } }
#[doc = "RTC_CURRENT_VALUE (rw) register accessor: RTC current count value\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_current_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_current_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_current_value`] module"]
#[doc (alias = "RTC_CURRENT_VALUE")] pub type RtcCurrentValue = crate :: Reg < rtc_current_value :: RtcCurrentValueSpec > ;
#[doc = "RTC current count value"] pub mod rtc_current_value {
#[doc = "Register `RTC_CURRENT_VALUE` reader"] pub type R = crate :: R < RtcCurrentValueSpec > ;
#[doc = "Register `RTC_CURRENT_VALUE` writer"] pub type W = crate :: W < RtcCurrentValueSpec > ;
#[doc = "Field `current_value` reader - Current counter value"] pub type CurrentValueR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - Current counter value"]
#[inline (always)] pub fn current_value (& self) -> CurrentValueR { CurrentValueR :: new (self . bits) } } impl W { }
#[doc = "RTC current count value\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_current_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_current_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RtcCurrentValueSpec ; impl crate :: RegisterSpec for RtcCurrentValueSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rtc_current_value::R`](R) reader structure"] impl crate :: Readable for RtcCurrentValueSpec { }
#[doc = "`write(|w| ..)` method takes [`rtc_current_value::W`](W) writer structure"] impl crate :: Writable for RtcCurrentValueSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RTC_CURRENT_VALUE to value 0"] impl crate :: Resettable for RtcCurrentValueSpec { } }
#[doc = "RTC_CONTROL (rw) register accessor: RTC control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_control`] module"]
#[doc (alias = "RTC_CONTROL")] pub type RtcControl = crate :: Reg < rtc_control :: RtcControlSpec > ;
#[doc = "RTC control register"] pub mod rtc_control {
#[doc = "Register `RTC_CONTROL` reader"] pub type R = crate :: R < RtcControlSpec > ;
#[doc = "Register `RTC_CONTROL` writer"] pub type W = crate :: W < RtcControlSpec > ;
#[doc = "Field `enable` reader - RTC enable"] pub type EnableR = crate :: BitReader ;
#[doc = "Field `enable` writer - RTC enable"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `mode` reader - Mode: 0=free running; 1=periodic"] pub type ModeR = crate :: BitReader ;
#[doc = "Field `mode` writer - Mode: 0=free running; 1=periodic"] pub type ModeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `int_mask` reader - Interrupt mask: 0=unmasked; 1=masked"] pub type IntMaskR = crate :: BitReader ;
#[doc = "Field `int_mask` writer - Interrupt mask: 0=unmasked; 1=masked"] pub type IntMaskW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - RTC enable"]
#[inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Mode: 0=free running; 1=periodic"]
#[inline (always)] pub fn mode (& self) -> ModeR { ModeR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Interrupt mask: 0=unmasked; 1=masked"]
#[inline (always)] pub fn int_mask (& self) -> IntMaskR { IntMaskR :: new (((self . bits >> 2) & 1) != 0) } } impl W {
#[doc = "Bit 0 - RTC enable"]
#[inline (always)] pub fn enable (& mut self) -> EnableW < '_ , RtcControlSpec > { EnableW :: new (self , 0) }
#[doc = "Bit 1 - Mode: 0=free running; 1=periodic"]
#[inline (always)] pub fn mode (& mut self) -> ModeW < '_ , RtcControlSpec > { ModeW :: new (self , 1) }
#[doc = "Bit 2 - Interrupt mask: 0=unmasked; 1=masked"]
#[inline (always)] pub fn int_mask (& mut self) -> IntMaskW < '_ , RtcControlSpec > { IntMaskW :: new (self , 2) } }
#[doc = "RTC control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RtcControlSpec ; impl crate :: RegisterSpec for RtcControlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rtc_control::R`](R) reader structure"] impl crate :: Readable for RtcControlSpec { }
#[doc = "`write(|w| ..)` method takes [`rtc_control::W`](W) writer structure"] impl crate :: Writable for RtcControlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RTC_CONTROL to value 0"] impl crate :: Resettable for RtcControlSpec { } }
#[doc = "RTC_EOI (rw) register accessor: RTC end-of-interrupt (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_eoi`] module"]
#[doc (alias = "RTC_EOI")] pub type RtcEoi = crate :: Reg < rtc_eoi :: RtcEoiSpec > ;
#[doc = "RTC end-of-interrupt (read to clear)"] pub mod rtc_eoi {
#[doc = "Register `RTC_EOI` reader"] pub type R = crate :: R < RtcEoiSpec > ;
#[doc = "Register `RTC_EOI` writer"] pub type W = crate :: W < RtcEoiSpec > ;
#[doc = "Field `eoi` reader - Read to clear RTC interrupt"] pub type EoiR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Read to clear RTC interrupt"]
#[inline (always)] pub fn eoi (& self) -> EoiR { EoiR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "RTC end-of-interrupt (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RtcEoiSpec ; impl crate :: RegisterSpec for RtcEoiSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rtc_eoi::R`](R) reader structure"] impl crate :: Readable for RtcEoiSpec { }
#[doc = "`write(|w| ..)` method takes [`rtc_eoi::W`](W) writer structure"] impl crate :: Writable for RtcEoiSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RTC_EOI to value 0"] impl crate :: Resettable for RtcEoiSpec { } }
#[doc = "RTC_INT_STATUS (rw) register accessor: RTC interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_int_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_int_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_int_status`] module"]
#[doc (alias = "RTC_INT_STATUS")] pub type RtcIntStatus = crate :: Reg < rtc_int_status :: RtcIntStatusSpec > ;
#[doc = "RTC interrupt status"] pub mod rtc_int_status {
#[doc = "Register `RTC_INT_STATUS` reader"] pub type R = crate :: R < RtcIntStatusSpec > ;
#[doc = "Register `RTC_INT_STATUS` writer"] pub type W = crate :: W < RtcIntStatusSpec > ;
#[doc = "Field `int_status` reader - Interrupt status"] pub type IntStatusR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Interrupt status"]
#[inline (always)] pub fn int_status (& self) -> IntStatusR { IntStatusR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "RTC interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_int_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_int_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RtcIntStatusSpec ; impl crate :: RegisterSpec for RtcIntStatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rtc_int_status::R`](R) reader structure"] impl crate :: Readable for RtcIntStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`rtc_int_status::W`](W) writer structure"] impl crate :: Writable for RtcIntStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RTC_INT_STATUS to value 0"] impl crate :: Resettable for RtcIntStatusSpec { } } }
#[doc = "eFuse controller (OTP, v151)"] pub type Efuse = crate :: Periph < efuse :: RegisterBlock , 0x4400_8000 > ; impl core :: fmt :: Debug for Efuse { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Efuse") . finish () } }
#[doc = "eFuse controller (OTP, v151)"] pub mod efuse {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { efuse_ctl_data : EfuseCtlData , efuse_clk_period : EfuseClkPeriod , _reserved2 : [u8 ; 0x04] , efuse_avdd_ctl : EfuseAvddCtl , _reserved3 : [u8 ; 0x1c] , efuse_sts : EfuseSts , } impl RegisterBlock {
#[doc = "0x00 - eFuse control data register"]
#[inline (always)] pub const fn efuse_ctl_data (& self) -> & EfuseCtlData { & self . efuse_ctl_data }
#[doc = "0x04 - eFuse clock period register"]
#[inline (always)] pub const fn efuse_clk_period (& self) -> & EfuseClkPeriod { & self . efuse_clk_period }
#[doc = "0x0c - eFuse AVDD switch register"]
#[inline (always)] pub const fn efuse_avdd_ctl (& self) -> & EfuseAvddCtl { & self . efuse_avdd_ctl }
#[doc = "0x2c - eFuse status register (at offset 0x2C)"]
#[inline (always)] pub const fn efuse_sts (& self) -> & EfuseSts { & self . efuse_sts } }
#[doc = "EFUSE_CTL_DATA (rw) register accessor: eFuse control data register\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_ctl_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_ctl_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_ctl_data`] module"]
#[doc (alias = "EFUSE_CTL_DATA")] pub type EfuseCtlData = crate :: Reg < efuse_ctl_data :: EfuseCtlDataSpec > ;
#[doc = "eFuse control data register"] pub mod efuse_ctl_data {
#[doc = "Register `EFUSE_CTL_DATA` reader"] pub type R = crate :: R < EfuseCtlDataSpec > ;
#[doc = "Register `EFUSE_CTL_DATA` writer"] pub type W = crate :: W < EfuseCtlDataSpec > ;
#[doc = "Field `efuse_ctl` reader - eFuse control data"] pub type EfuseCtlR = crate :: FieldReader < u16 > ;
#[doc = "Field `efuse_ctl` writer - eFuse control data"] pub type EfuseCtlW < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ;
#[doc = "Field `wr_rd` reader - Write/Read control: 0=read; 1=write"] pub type WrRdR = crate :: BitReader ;
#[doc = "Field `wr_rd` writer - Write/Read control: 0=read; 1=write"] pub type WrRdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:15 - eFuse control data"]
#[inline (always)] pub fn efuse_ctl (& self) -> EfuseCtlR { EfuseCtlR :: new ((self . bits & 0xffff) as u16) }
#[doc = "Bit 16 - Write/Read control: 0=read; 1=write"]
#[inline (always)] pub fn wr_rd (& self) -> WrRdR { WrRdR :: new (((self . bits >> 16) & 1) != 0) } } impl W {
#[doc = "Bits 0:15 - eFuse control data"]
#[inline (always)] pub fn efuse_ctl (& mut self) -> EfuseCtlW < '_ , EfuseCtlDataSpec > { EfuseCtlW :: new (self , 0) }
#[doc = "Bit 16 - Write/Read control: 0=read; 1=write"]
#[inline (always)] pub fn wr_rd (& mut self) -> WrRdW < '_ , EfuseCtlDataSpec > { WrRdW :: new (self , 16) } }
#[doc = "eFuse control data register\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_ctl_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_ctl_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EfuseCtlDataSpec ; impl crate :: RegisterSpec for EfuseCtlDataSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`efuse_ctl_data::R`](R) reader structure"] impl crate :: Readable for EfuseCtlDataSpec { }
#[doc = "`write(|w| ..)` method takes [`efuse_ctl_data::W`](W) writer structure"] impl crate :: Writable for EfuseCtlDataSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets EFUSE_CTL_DATA to value 0"] impl crate :: Resettable for EfuseCtlDataSpec { } }
#[doc = "EFUSE_CLK_PERIOD (rw) register accessor: eFuse clock period register\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_clk_period::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_clk_period::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_clk_period`] module"]
#[doc (alias = "EFUSE_CLK_PERIOD")] pub type EfuseClkPeriod = crate :: Reg < efuse_clk_period :: EfuseClkPeriodSpec > ;
#[doc = "eFuse clock period register"] pub mod efuse_clk_period {
#[doc = "Register `EFUSE_CLK_PERIOD` reader"] pub type R = crate :: R < EfuseClkPeriodSpec > ;
#[doc = "Register `EFUSE_CLK_PERIOD` writer"] pub type W = crate :: W < EfuseClkPeriodSpec > ;
#[doc = "Field `clk_period` reader - Clock period value"] pub type ClkPeriodR = crate :: FieldReader ;
#[doc = "Field `clk_period` writer - Clock period value"] pub type ClkPeriodW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - Clock period value"]
#[inline (always)] pub fn clk_period (& self) -> ClkPeriodR { ClkPeriodR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - Clock period value"]
#[inline (always)] pub fn clk_period (& mut self) -> ClkPeriodW < '_ , EfuseClkPeriodSpec > { ClkPeriodW :: new (self , 0) } }
#[doc = "eFuse clock period register\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_clk_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_clk_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EfuseClkPeriodSpec ; impl crate :: RegisterSpec for EfuseClkPeriodSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`efuse_clk_period::R`](R) reader structure"] impl crate :: Readable for EfuseClkPeriodSpec { }
#[doc = "`write(|w| ..)` method takes [`efuse_clk_period::W`](W) writer structure"] impl crate :: Writable for EfuseClkPeriodSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets EFUSE_CLK_PERIOD to value 0"] impl crate :: Resettable for EfuseClkPeriodSpec { } }
#[doc = "EFUSE_AVDD_CTL (rw) register accessor: eFuse AVDD switch register\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_avdd_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_avdd_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_avdd_ctl`] module"]
#[doc (alias = "EFUSE_AVDD_CTL")] pub type EfuseAvddCtl = crate :: Reg < efuse_avdd_ctl :: EfuseAvddCtlSpec > ;
#[doc = "eFuse AVDD switch register"] pub mod efuse_avdd_ctl {
#[doc = "Register `EFUSE_AVDD_CTL` reader"] pub type R = crate :: R < EfuseAvddCtlSpec > ;
#[doc = "Register `EFUSE_AVDD_CTL` writer"] pub type W = crate :: W < EfuseAvddCtlSpec > ;
#[doc = "Field `avdd_ctl` reader - AVDD switch control"] pub type AvddCtlR = crate :: BitReader ;
#[doc = "Field `avdd_ctl` writer - AVDD switch control"] pub type AvddCtlW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - AVDD switch control"]
#[inline (always)] pub fn avdd_ctl (& self) -> AvddCtlR { AvddCtlR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - AVDD switch control"]
#[inline (always)] pub fn avdd_ctl (& mut self) -> AvddCtlW < '_ , EfuseAvddCtlSpec > { AvddCtlW :: new (self , 0) } }
#[doc = "eFuse AVDD switch register\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_avdd_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_avdd_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EfuseAvddCtlSpec ; impl crate :: RegisterSpec for EfuseAvddCtlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`efuse_avdd_ctl::R`](R) reader structure"] impl crate :: Readable for EfuseAvddCtlSpec { }
#[doc = "`write(|w| ..)` method takes [`efuse_avdd_ctl::W`](W) writer structure"] impl crate :: Writable for EfuseAvddCtlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets EFUSE_AVDD_CTL to value 0"] impl crate :: Resettable for EfuseAvddCtlSpec { } }
#[doc = "EFUSE_STS (rw) register accessor: eFuse status register (at offset 0x2C)\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_sts`] module"]
#[doc (alias = "EFUSE_STS")] pub type EfuseSts = crate :: Reg < efuse_sts :: EfuseStsSpec > ;
#[doc = "eFuse status register (at offset 0x2C)"] pub mod efuse_sts {
#[doc = "Register `EFUSE_STS` reader"] pub type R = crate :: R < EfuseStsSpec > ;
#[doc = "Register `EFUSE_STS` writer"] pub type W = crate :: W < EfuseStsSpec > ;
#[doc = "Field `man_sts` reader - Manufacturing status"] pub type ManStsR = crate :: FieldReader ;
#[doc = "Field `boot0_done` reader - Boot0 done flag"] pub type Boot0DoneR = crate :: BitReader ;
#[doc = "Field `boot1_done` reader - Boot1 done flag"] pub type Boot1DoneR = crate :: BitReader ;
#[doc = "Field `boot2_done` reader - Boot2 done flag"] pub type Boot2DoneR = crate :: BitReader ; impl R {
#[doc = "Bits 0:1 - Manufacturing status"]
#[inline (always)] pub fn man_sts (& self) -> ManStsR { ManStsR :: new ((self . bits & 3) as u8) }
#[doc = "Bit 2 - Boot0 done flag"]
#[inline (always)] pub fn boot0_done (& self) -> Boot0DoneR { Boot0DoneR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - Boot1 done flag"]
#[inline (always)] pub fn boot1_done (& self) -> Boot1DoneR { Boot1DoneR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Boot2 done flag"]
#[inline (always)] pub fn boot2_done (& self) -> Boot2DoneR { Boot2DoneR :: new (((self . bits >> 4) & 1) != 0) } } impl W { }
#[doc = "eFuse status register (at offset 0x2C)\n\nYou can [`read`](crate::Reg::read) this register and get [`efuse_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`efuse_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EfuseStsSpec ; impl crate :: RegisterSpec for EfuseStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`efuse_sts::R`](R) reader structure"] impl crate :: Readable for EfuseStsSpec { }
#[doc = "`write(|w| ..)` method takes [`efuse_sts::W`](W) writer structure"] impl crate :: Writable for EfuseStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets EFUSE_STS to value 0"] impl crate :: Resettable for EfuseStsSpec { } } }
#[doc = "System Control 0 - reset status, clock control, PLL config"] pub type SysCtl0 = crate :: Periph < sys_ctl0 :: RegisterBlock , 0x4000_0000 > ; impl core :: fmt :: Debug for SysCtl0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("SysCtl0") . finish () } }
#[doc = "System Control 0 - reset status, clock control, PLL config"] pub mod sys_ctl0 {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x08] , reset_count : ResetCount , _reserved1 : [u8 ; 0x08] , hw_ctl : HwCtl , _reserved2 : [u8 ; 0x80] , reg_sys_rst_record : RegSysRstRecord , _reserved3 : [u8 ; 0x04] , sys_rst_record_0 : SysRstRecord0 , sys_diag_clr_1 : SysDiagClr1 , } impl RegisterBlock {
#[doc = "0x08 - Reset count register"]
#[inline (always)] pub const fn reset_count (& self) -> & ResetCount { & self . reset_count }
#[doc = "0x14 - Hardware control register"]
#[inline (always)] pub const fn hw_ctl (& self) -> & HwCtl { & self . hw_ctl }
#[doc = "0x98 - System reset record register"]
#[inline (always)] pub const fn reg_sys_rst_record (& self) -> & RegSysRstRecord { & self . reg_sys_rst_record }
#[doc = "0xa0 - System reset history record 0"]
#[inline (always)] pub const fn sys_rst_record_0 (& self) -> & SysRstRecord0 { & self . sys_rst_record_0 }
#[doc = "0xa4 - System diagnostic clear 1"]
#[inline (always)] pub const fn sys_diag_clr_1 (& self) -> & SysDiagClr1 { & self . sys_diag_clr_1 } }
#[doc = "RESET_COUNT (rw) register accessor: Reset count register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_count`] module"]
#[doc (alias = "RESET_COUNT")] pub type ResetCount = crate :: Reg < reset_count :: ResetCountSpec > ;
#[doc = "Reset count register"] pub mod reset_count {
#[doc = "Register `RESET_COUNT` reader"] pub type R = crate :: R < ResetCountSpec > ;
#[doc = "Register `RESET_COUNT` writer"] pub type W = crate :: W < ResetCountSpec > ;
#[doc = "Field `reset_count` reader - Reset count value"] pub type ResetCountR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - Reset count value"]
#[inline (always)] pub fn reset_count (& self) -> ResetCountR { ResetCountR :: new (self . bits) } } impl W { }
#[doc = "Reset count register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ResetCountSpec ; impl crate :: RegisterSpec for ResetCountSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`reset_count::R`](R) reader structure"] impl crate :: Readable for ResetCountSpec { }
#[doc = "`write(|w| ..)` method takes [`reset_count::W`](W) writer structure"] impl crate :: Writable for ResetCountSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RESET_COUNT to value 0"] impl crate :: Resettable for ResetCountSpec { } }
#[doc = "HW_CTL (rw) register accessor: Hardware control register\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_ctl`] module"]
#[doc (alias = "HW_CTL")] pub type HwCtl = crate :: Reg < hw_ctl :: HwCtlSpec > ;
#[doc = "Hardware control register"] pub mod hw_ctl {
#[doc = "Register `HW_CTL` reader"] pub type R = crate :: R < HwCtlSpec > ;
#[doc = "Register `HW_CTL` writer"] pub type W = crate :: W < HwCtlSpec > ;
#[doc = "Field `refclk_freq_status` reader - REFCLK frequency status: 0=40MHz; 1=24MHz"] pub type RefclkFreqStatusR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - REFCLK frequency status: 0=40MHz; 1=24MHz"]
#[inline (always)] pub fn refclk_freq_status (& self) -> RefclkFreqStatusR { RefclkFreqStatusR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "Hardware control register\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HwCtlSpec ; impl crate :: RegisterSpec for HwCtlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`hw_ctl::R`](R) reader structure"] impl crate :: Readable for HwCtlSpec { }
#[doc = "`write(|w| ..)` method takes [`hw_ctl::W`](W) writer structure"] impl crate :: Writable for HwCtlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets HW_CTL to value 0"] impl crate :: Resettable for HwCtlSpec { } }
#[doc = "REG_SYS_RST_RECORD (rw) register accessor: System reset record register\n\nYou can [`read`](crate::Reg::read) this register and get [`reg_sys_rst_record::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg_sys_rst_record::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_sys_rst_record`] module"]
#[doc (alias = "REG_SYS_RST_RECORD")] pub type RegSysRstRecord = crate :: Reg < reg_sys_rst_record :: RegSysRstRecordSpec > ;
#[doc = "System reset record register"] pub mod reg_sys_rst_record {
#[doc = "Register `REG_SYS_RST_RECORD` reader"] pub type R = crate :: R < RegSysRstRecordSpec > ;
#[doc = "Register `REG_SYS_RST_RECORD` writer"] pub type W = crate :: W < RegSysRstRecordSpec > ;
#[doc = "Field `wdt_rst` reader - Watchdog reset record"] pub type WdtRstR = crate :: BitReader ;
#[doc = "Field `wdt_rst` writer - Watchdog reset record"] pub type WdtRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_rst` reader - Software reset record"] pub type SoftRstR = crate :: BitReader ;
#[doc = "Field `soft_rst` writer - Software reset record"] pub type SoftRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `hard_rst` reader - Hardware reset record"] pub type HardRstR = crate :: BitReader ;
#[doc = "Field `hard_rst` writer - Hardware reset record"] pub type HardRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Watchdog reset record"]
#[inline (always)] pub fn wdt_rst (& self) -> WdtRstR { WdtRstR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Software reset record"]
#[inline (always)] pub fn soft_rst (& self) -> SoftRstR { SoftRstR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Hardware reset record"]
#[inline (always)] pub fn hard_rst (& self) -> HardRstR { HardRstR :: new (((self . bits >> 2) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Watchdog reset record"]
#[inline (always)] pub fn wdt_rst (& mut self) -> WdtRstW < '_ , RegSysRstRecordSpec > { WdtRstW :: new (self , 0) }
#[doc = "Bit 1 - Software reset record"]
#[inline (always)] pub fn soft_rst (& mut self) -> SoftRstW < '_ , RegSysRstRecordSpec > { SoftRstW :: new (self , 1) }
#[doc = "Bit 2 - Hardware reset record"]
#[inline (always)] pub fn hard_rst (& mut self) -> HardRstW < '_ , RegSysRstRecordSpec > { HardRstW :: new (self , 2) } }
#[doc = "System reset record register\n\nYou can [`read`](crate::Reg::read) this register and get [`reg_sys_rst_record::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg_sys_rst_record::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RegSysRstRecordSpec ; impl crate :: RegisterSpec for RegSysRstRecordSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`reg_sys_rst_record::R`](R) reader structure"] impl crate :: Readable for RegSysRstRecordSpec { }
#[doc = "`write(|w| ..)` method takes [`reg_sys_rst_record::W`](W) writer structure"] impl crate :: Writable for RegSysRstRecordSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets REG_SYS_RST_RECORD to value 0"] impl crate :: Resettable for RegSysRstRecordSpec { } }
#[doc = "SYS_RST_RECORD_0 (rw) register accessor: System reset history record 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_rst_record_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_rst_record_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_rst_record_0`] module"]
#[doc (alias = "SYS_RST_RECORD_0")] pub type SysRstRecord0 = crate :: Reg < sys_rst_record_0 :: SysRstRecord0Spec > ;
#[doc = "System reset history record 0"] pub mod sys_rst_record_0 {
#[doc = "Register `SYS_RST_RECORD_0` reader"] pub type R = crate :: R < SysRstRecord0Spec > ;
#[doc = "Register `SYS_RST_RECORD_0` writer"] pub type W = crate :: W < SysRstRecord0Spec > ;
#[doc = "Field `sys_wdt_rst_his` reader - WDT reset history"] pub type SysWdtRstHisR = crate :: BitReader ;
#[doc = "Field `sys_soft_rst_his` reader - Software reset history"] pub type SysSoftRstHisR = crate :: BitReader ;
#[doc = "Field `por_rst_filter_his` reader - POR reset filter history"] pub type PorRstFilterHisR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - WDT reset history"]
#[inline (always)] pub fn sys_wdt_rst_his (& self) -> SysWdtRstHisR { SysWdtRstHisR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Software reset history"]
#[inline (always)] pub fn sys_soft_rst_his (& self) -> SysSoftRstHisR { SysSoftRstHisR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 3 - POR reset filter history"]
#[inline (always)] pub fn por_rst_filter_his (& self) -> PorRstFilterHisR { PorRstFilterHisR :: new (((self . bits >> 3) & 1) != 0) } } impl W { }
#[doc = "System reset history record 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_rst_record_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_rst_record_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SysRstRecord0Spec ; impl crate :: RegisterSpec for SysRstRecord0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`sys_rst_record_0::R`](R) reader structure"] impl crate :: Readable for SysRstRecord0Spec { }
#[doc = "`write(|w| ..)` method takes [`sys_rst_record_0::W`](W) writer structure"] impl crate :: Writable for SysRstRecord0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SYS_RST_RECORD_0 to value 0"] impl crate :: Resettable for SysRstRecord0Spec { } }
#[doc = "SYS_DIAG_CLR_1 (rw) register accessor: System diagnostic clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_diag_clr_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_diag_clr_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_diag_clr_1`] module"]
#[doc (alias = "SYS_DIAG_CLR_1")] pub type SysDiagClr1 = crate :: Reg < sys_diag_clr_1 :: SysDiagClr1Spec > ;
#[doc = "System diagnostic clear 1"] pub mod sys_diag_clr_1 {
#[doc = "Register `SYS_DIAG_CLR_1` reader"] pub type R = crate :: R < SysDiagClr1Spec > ;
#[doc = "Register `SYS_DIAG_CLR_1` writer"] pub type W = crate :: W < SysDiagClr1Spec > ;
#[doc = "Field `sys_diag_clr` writer - Write to clear reset history bits"] pub type SysDiagClrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl W {
#[doc = "Bits 0:31 - Write to clear reset history bits"]
#[inline (always)] pub fn sys_diag_clr (& mut self) -> SysDiagClrW < '_ , SysDiagClr1Spec > { SysDiagClrW :: new (self , 0) } }
#[doc = "System diagnostic clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_diag_clr_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_diag_clr_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SysDiagClr1Spec ; impl crate :: RegisterSpec for SysDiagClr1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`sys_diag_clr_1::R`](R) reader structure"] impl crate :: Readable for SysDiagClr1Spec { }
#[doc = "`write(|w| ..)` method takes [`sys_diag_clr_1::W`](W) writer structure"] impl crate :: Writable for SysDiagClr1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SYS_DIAG_CLR_1 to value 0"] impl crate :: Resettable for SysDiagClr1Spec { } } }
#[doc = "Main core global control - BCPU/MCPU reset status, chip reset, AON CRG"] pub type GlbCtlM = crate :: Periph < glb_ctl_m :: RegisterBlock , 0x4000_2000 > ; impl core :: fmt :: Debug for GlbCtlM { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("GlbCtlM") . finish () } }
#[doc = "Main core global control - BCPU/MCPU reset status, chip reset, AON CRG"] pub mod glb_ctl_m {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x30] , bcpu_reset_sts : BcpuResetSts , mcpu_reset_sts : McpuResetSts , _reserved2 : [u8 ; 0x04] , reset_sts_clear : ResetStsClear , _reserved3 : [u8 ; 0xc0] , aon_crg_cken_ctl : AonCrgCkenCtl , _reserved4 : [u8 ; 0x0c] , _reserved_4_chip_reset : [u8 ; 0x04] , } impl RegisterBlock {
#[doc = "0x30 - BCPU reset status register"]
#[inline (always)] pub const fn bcpu_reset_sts (& self) -> & BcpuResetSts { & self . bcpu_reset_sts }
#[doc = "0x34 - MCPU reset status register"]
#[inline (always)] pub const fn mcpu_reset_sts (& self) -> & McpuResetSts { & self . mcpu_reset_sts }
#[doc = "0x3c - Reset status clear register"]
#[inline (always)] pub const fn reset_sts_clear (& self) -> & ResetStsClear { & self . reset_sts_clear }
#[doc = "0x100 - AON CRG clock enable control"]
#[inline (always)] pub const fn aon_crg_cken_ctl (& self) -> & AonCrgCkenCtl { & self . aon_crg_cken_ctl }
#[doc = "0x110 - AON soft reset control"]
#[inline (always)] pub const fn aon_soft_rst_ctl (& self) -> & AonSoftRstCtl { unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (272) . cast () } }
#[doc = "0x110 - Chip reset control register"]
#[inline (always)] pub const fn chip_reset (& self) -> & ChipReset { unsafe { & * core :: ptr :: from_ref (self) . cast :: < u8 > () . add (272) . cast () } } }
#[doc = "BCPU_RESET_STS (rw) register accessor: BCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`bcpu_reset_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcpu_reset_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bcpu_reset_sts`] module"]
#[doc (alias = "BCPU_RESET_STS")] pub type BcpuResetSts = crate :: Reg < bcpu_reset_sts :: BcpuResetStsSpec > ;
#[doc = "BCPU reset status register"] pub mod bcpu_reset_sts {
#[doc = "Register `BCPU_RESET_STS` reader"] pub type R = crate :: R < BcpuResetStsSpec > ;
#[doc = "Register `BCPU_RESET_STS` writer"] pub type W = crate :: W < BcpuResetStsSpec > ;
#[doc = "Field `bcpu_reset_sts` reader - BCPU reset status"] pub type BcpuResetStsR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - BCPU reset status"]
#[inline (always)] pub fn bcpu_reset_sts (& self) -> BcpuResetStsR { BcpuResetStsR :: new (self . bits) } } impl W { }
#[doc = "BCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`bcpu_reset_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcpu_reset_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BcpuResetStsSpec ; impl crate :: RegisterSpec for BcpuResetStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`bcpu_reset_sts::R`](R) reader structure"] impl crate :: Readable for BcpuResetStsSpec { }
#[doc = "`write(|w| ..)` method takes [`bcpu_reset_sts::W`](W) writer structure"] impl crate :: Writable for BcpuResetStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets BCPU_RESET_STS to value 0"] impl crate :: Resettable for BcpuResetStsSpec { } }
#[doc = "MCPU_RESET_STS (rw) register accessor: MCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mcpu_reset_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcpu_reset_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcpu_reset_sts`] module"]
#[doc (alias = "MCPU_RESET_STS")] pub type McpuResetSts = crate :: Reg < mcpu_reset_sts :: McpuResetStsSpec > ;
#[doc = "MCPU reset status register"] pub mod mcpu_reset_sts {
#[doc = "Register `MCPU_RESET_STS` reader"] pub type R = crate :: R < McpuResetStsSpec > ;
#[doc = "Register `MCPU_RESET_STS` writer"] pub type W = crate :: W < McpuResetStsSpec > ;
#[doc = "Field `mcpu_reset_sts` reader - MCPU reset status"] pub type McpuResetStsR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - MCPU reset status"]
#[inline (always)] pub fn mcpu_reset_sts (& self) -> McpuResetStsR { McpuResetStsR :: new (self . bits) } } impl W { }
#[doc = "MCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mcpu_reset_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcpu_reset_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct McpuResetStsSpec ; impl crate :: RegisterSpec for McpuResetStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`mcpu_reset_sts::R`](R) reader structure"] impl crate :: Readable for McpuResetStsSpec { }
#[doc = "`write(|w| ..)` method takes [`mcpu_reset_sts::W`](W) writer structure"] impl crate :: Writable for McpuResetStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets MCPU_RESET_STS to value 0"] impl crate :: Resettable for McpuResetStsSpec { } }
#[doc = "RESET_STS_CLEAR (rw) register accessor: Reset status clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_sts_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_sts_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_sts_clear`] module"]
#[doc (alias = "RESET_STS_CLEAR")] pub type ResetStsClear = crate :: Reg < reset_sts_clear :: ResetStsClearSpec > ;
#[doc = "Reset status clear register"] pub mod reset_sts_clear {
#[doc = "Register `RESET_STS_CLEAR` reader"] pub type R = crate :: R < ResetStsClearSpec > ;
#[doc = "Register `RESET_STS_CLEAR` writer"] pub type W = crate :: W < ResetStsClearSpec > ;
#[doc = "Field `rst_sts_clear` writer - Write 0xFF to clear all reset status bits"] pub type RstStsClearW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl W {
#[doc = "Bits 0:31 - Write 0xFF to clear all reset status bits"]
#[inline (always)] pub fn rst_sts_clear (& mut self) -> RstStsClearW < '_ , ResetStsClearSpec > { RstStsClearW :: new (self , 0) } }
#[doc = "Reset status clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_sts_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_sts_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ResetStsClearSpec ; impl crate :: RegisterSpec for ResetStsClearSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`reset_sts_clear::R`](R) reader structure"] impl crate :: Readable for ResetStsClearSpec { }
#[doc = "`write(|w| ..)` method takes [`reset_sts_clear::W`](W) writer structure"] impl crate :: Writable for ResetStsClearSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RESET_STS_CLEAR to value 0"] impl crate :: Resettable for ResetStsClearSpec { } }
#[doc = "AON_CRG_CKEN_CTL (rw) register accessor: AON CRG clock enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_crg_cken_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_crg_cken_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_crg_cken_ctl`] module"]
#[doc (alias = "AON_CRG_CKEN_CTL")] pub type AonCrgCkenCtl = crate :: Reg < aon_crg_cken_ctl :: AonCrgCkenCtlSpec > ;
#[doc = "AON CRG clock enable control"] pub mod aon_crg_cken_ctl {
#[doc = "Register `AON_CRG_CKEN_CTL` reader"] pub type R = crate :: R < AonCrgCkenCtlSpec > ;
#[doc = "Register `AON_CRG_CKEN_CTL` writer"] pub type W = crate :: W < AonCrgCkenCtlSpec > ;
#[doc = "Field `wdt_gate` reader - WDT clock gate control at bit\\[4\\]"] pub type WdtGateR = crate :: BitReader ;
#[doc = "Field `wdt_gate` writer - WDT clock gate control at bit\\[4\\]"] pub type WdtGateW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 4 - WDT clock gate control at bit\\[4\\]"]
#[inline (always)] pub fn wdt_gate (& self) -> WdtGateR { WdtGateR :: new (((self . bits >> 4) & 1) != 0) } } impl W {
#[doc = "Bit 4 - WDT clock gate control at bit\\[4\\]"]
#[inline (always)] pub fn wdt_gate (& mut self) -> WdtGateW < '_ , AonCrgCkenCtlSpec > { WdtGateW :: new (self , 4) } }
#[doc = "AON CRG clock enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_crg_cken_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_crg_cken_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AonCrgCkenCtlSpec ; impl crate :: RegisterSpec for AonCrgCkenCtlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`aon_crg_cken_ctl::R`](R) reader structure"] impl crate :: Readable for AonCrgCkenCtlSpec { }
#[doc = "`write(|w| ..)` method takes [`aon_crg_cken_ctl::W`](W) writer structure"] impl crate :: Writable for AonCrgCkenCtlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets AON_CRG_CKEN_CTL to value 0"] impl crate :: Resettable for AonCrgCkenCtlSpec { } }
#[doc = "CHIP_RESET (rw) register accessor: Chip reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`chip_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chip_reset`] module"]
#[doc (alias = "CHIP_RESET")] pub type ChipReset = crate :: Reg < chip_reset :: ChipResetSpec > ;
#[doc = "Chip reset control register"] pub mod chip_reset {
#[doc = "Register `CHIP_RESET` reader"] pub type R = crate :: R < ChipResetSpec > ;
#[doc = "Register `CHIP_RESET` writer"] pub type W = crate :: W < ChipResetSpec > ;
#[doc = "Field `chip_reset_en` reader - Chip reset enable: 1=assert chip reset"] pub type ChipResetEnR = crate :: BitReader ;
#[doc = "Field `chip_reset_en` writer - Chip reset enable: 1=assert chip reset"] pub type ChipResetEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 2 - Chip reset enable: 1=assert chip reset"]
#[inline (always)] pub fn chip_reset_en (& self) -> ChipResetEnR { ChipResetEnR :: new (((self . bits >> 2) & 1) != 0) } } impl W {
#[doc = "Bit 2 - Chip reset enable: 1=assert chip reset"]
#[inline (always)] pub fn chip_reset_en (& mut self) -> ChipResetEnW < '_ , ChipResetSpec > { ChipResetEnW :: new (self , 2) } }
#[doc = "Chip reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`chip_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ChipResetSpec ; impl crate :: RegisterSpec for ChipResetSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`chip_reset::R`](R) reader structure"] impl crate :: Readable for ChipResetSpec { }
#[doc = "`write(|w| ..)` method takes [`chip_reset::W`](W) writer structure"] impl crate :: Writable for ChipResetSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CHIP_RESET to value 0"] impl crate :: Resettable for ChipResetSpec { } }
#[doc = "AON_SOFT_RST_CTL (rw) register accessor: AON soft reset control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_soft_rst_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_soft_rst_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_soft_rst_ctl`] module"]
#[doc (alias = "AON_SOFT_RST_CTL")] pub type AonSoftRstCtl = crate :: Reg < aon_soft_rst_ctl :: AonSoftRstCtlSpec > ;
#[doc = "AON soft reset control"] pub mod aon_soft_rst_ctl {
#[doc = "Register `AON_SOFT_RST_CTL` reader"] pub type R = crate :: R < AonSoftRstCtlSpec > ;
#[doc = "Register `AON_SOFT_RST_CTL` writer"] pub type W = crate :: W < AonSoftRstCtlSpec > ;
#[doc = "Field `wdt_soft_rst` reader - WDT soft reset at bit\\[1\\]"] pub type WdtSoftRstR = crate :: BitReader ;
#[doc = "Field `wdt_soft_rst` writer - WDT soft reset at bit\\[1\\]"] pub type WdtSoftRstW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 1 - WDT soft reset at bit\\[1\\]"]
#[inline (always)] pub fn wdt_soft_rst (& self) -> WdtSoftRstR { WdtSoftRstR :: new (((self . bits >> 1) & 1) != 0) } } impl W {
#[doc = "Bit 1 - WDT soft reset at bit\\[1\\]"]
#[inline (always)] pub fn wdt_soft_rst (& mut self) -> WdtSoftRstW < '_ , AonSoftRstCtlSpec > { WdtSoftRstW :: new (self , 1) } }
#[doc = "AON soft reset control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_soft_rst_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_soft_rst_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AonSoftRstCtlSpec ; impl crate :: RegisterSpec for AonSoftRstCtlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`aon_soft_rst_ctl::R`](R) reader structure"] impl crate :: Readable for AonSoftRstCtlSpec { }
#[doc = "`write(|w| ..)` method takes [`aon_soft_rst_ctl::W`](W) writer structure"] impl crate :: Writable for AonSoftRstCtlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets AON_SOFT_RST_CTL to value 0"] impl crate :: Resettable for AonSoftRstCtlSpec { } } }
#[doc = "Security accelerator - AES/SM4/LEA/TDES symmetric crypto, HASH/HMAC"] pub type Spacc = crate :: Periph < spacc :: RegisterBlock , 0x4410_0000 > ; impl core :: fmt :: Debug for Spacc { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Spacc") . finish () } }
#[doc = "Security accelerator - AES/SM4/LEA/TDES symmetric crypto, HASH/HMAC"] pub mod spacc {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x04] , spacc_ie : SpaccIe , spacc_int_raw_sym_clr_finish : SpaccIntRawSymClrFinish , _reserved2 : [u8 ; 0x14] , spacc_sym_chn_lock : SpaccSymChnLock , _reserved3 : [u8 ; 0x1c] , spacc_hash_chn_lock : SpaccHashChnLock , _reserved4 : [u8 ; 0x1c] , spacc_sym_chn_clear_req : SpaccSymChnClearReq , _reserved5 : [u8 ; 0x04] , spacc_hash_chn_clear_req : SpaccHashChnClearReq , _reserved6 : [u8 ; 0x0194] , spacc_bus_err : SpaccBusErr , _reserved7 : [u8 ; 0x3dfc] , in_sym_chn0_ctrl : InSymChn0Ctrl , in_sym_chn0_special_ctrl : InSymChn0SpecialCtrl , _reserved9 : [u8 ; 0x08] , in_sym_chn0_key_ctrl : InSymChn0KeyCtrl , _reserved10 : [u8 ; 0x1c] , in_sym_chn0_iv_data_ctrl : InSymChn0IvDataCtrl , _reserved11 : [u8 ; 0x0c] , in_sym_chn0_iv0 : InSymChn0Iv0 , in_sym_chn0_iv1 : InSymChn0Iv1 , in_sym_chn0_iv2 : InSymChn0Iv2 , in_sym_chn0_iv3 : InSymChn0Iv3 , in_sym_chn0_data0 : InSymChn0Data0 , _reserved16 : [u8 ; 0x45bc] , sym_chann_raw_int : SymChannRawInt , } impl RegisterBlock {
#[doc = "0x04 - SPACC interrupt enable"]
#[inline (always)] pub const fn spacc_ie (& self) -> & SpaccIe { & self . spacc_ie }
#[doc = "0x08 - Sym clear finish raw interrupt"]
#[inline (always)] pub const fn spacc_int_raw_sym_clr_finish (& self) -> & SpaccIntRawSymClrFinish { & self . spacc_int_raw_sym_clr_finish }
#[doc = "0x20 - Sym channel lock register"]
#[inline (always)] pub const fn spacc_sym_chn_lock (& self) -> & SpaccSymChnLock { & self . spacc_sym_chn_lock }
#[doc = "0x40 - Hash channel lock register"]
#[inline (always)] pub const fn spacc_hash_chn_lock (& self) -> & SpaccHashChnLock { & self . spacc_hash_chn_lock }
#[doc = "0x60 - Sym channel clear request"]
#[inline (always)] pub const fn spacc_sym_chn_clear_req (& self) -> & SpaccSymChnClearReq { & self . spacc_sym_chn_clear_req }
#[doc = "0x68 - Hash channel clear request"]
#[inline (always)] pub const fn spacc_hash_chn_clear_req (& self) -> & SpaccHashChnClearReq { & self . spacc_hash_chn_clear_req }
#[doc = "0x200 - Bus error register"]
#[inline (always)] pub const fn spacc_bus_err (& self) -> & SpaccBusErr { & self . spacc_bus_err }
#[doc = "0x4000 - Sym channel 0 control register (no-DMA mode)"]
#[inline (always)] pub const fn in_sym_chn0_ctrl (& self) -> & InSymChn0Ctrl { & self . in_sym_chn0_ctrl }
#[doc = "0x4004 - Sym channel 0 special control"]
#[inline (always)] pub const fn in_sym_chn0_special_ctrl (& self) -> & InSymChn0SpecialCtrl { & self . in_sym_chn0_special_ctrl }
#[doc = "0x4010 - Sym channel 0 key control (no-DMA mode)"]
#[inline (always)] pub const fn in_sym_chn0_key_ctrl (& self) -> & InSymChn0KeyCtrl { & self . in_sym_chn0_key_ctrl }
#[doc = "0x4030 - Sym channel 0 IV/data control (register mode)"]
#[inline (always)] pub const fn in_sym_chn0_iv_data_ctrl (& self) -> & InSymChn0IvDataCtrl { & self . in_sym_chn0_iv_data_ctrl }
#[doc = "0x4040 - Sym channel 0 IV word 0 (register mode)"]
#[inline (always)] pub const fn in_sym_chn0_iv0 (& self) -> & InSymChn0Iv0 { & self . in_sym_chn0_iv0 }
#[doc = "0x4044 - Sym channel 0 IV word 1"]
#[inline (always)] pub const fn in_sym_chn0_iv1 (& self) -> & InSymChn0Iv1 { & self . in_sym_chn0_iv1 }
#[doc = "0x4048 - Sym channel 0 IV word 2"]
#[inline (always)] pub const fn in_sym_chn0_iv2 (& self) -> & InSymChn0Iv2 { & self . in_sym_chn0_iv2 }
#[doc = "0x404c - Sym channel 0 IV word 3"]
#[inline (always)] pub const fn in_sym_chn0_iv3 (& self) -> & InSymChn0Iv3 { & self . in_sym_chn0_iv3 }
#[doc = "0x4050 - Sym channel 0 data word 0 (register mode)"]
#[inline (always)] pub const fn in_sym_chn0_data0 (& self) -> & InSymChn0Data0 { & self . in_sym_chn0_data0 }
#[doc = "0x8610 - Sym channel raw interrupt status"]
#[inline (always)] pub const fn sym_chann_raw_int (& self) -> & SymChannRawInt { & self . sym_chann_raw_int } }
#[doc = "SPACC_IE (rw) register accessor: SPACC interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_ie`] module"]
#[doc (alias = "SPACC_IE")] pub type SpaccIe = crate :: Reg < spacc_ie :: SpaccIeSpec > ;
#[doc = "SPACC interrupt enable"] pub mod spacc_ie {
#[doc = "Register `SPACC_IE` reader"] pub type R = crate :: R < SpaccIeSpec > ;
#[doc = "Register `SPACC_IE` writer"] pub type W = crate :: W < SpaccIeSpec > ;
#[doc = "Field `spacc_ie_ree` reader - REE interrupt enable"] pub type SpaccIeReeR = crate :: BitReader ;
#[doc = "Field `spacc_ie_ree` writer - REE interrupt enable"] pub type SpaccIeReeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `spacc_ie_tee` reader - TEE interrupt enable"] pub type SpaccIeTeeR = crate :: BitReader ;
#[doc = "Field `spacc_ie_tee` writer - TEE interrupt enable"] pub type SpaccIeTeeW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `spacc_ie_hpp` reader - HPP interrupt enable"] pub type SpaccIeHppR = crate :: BitReader ;
#[doc = "Field `spacc_ie_hpp` writer - HPP interrupt enable"] pub type SpaccIeHppW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - REE interrupt enable"]
#[inline (always)] pub fn spacc_ie_ree (& self) -> SpaccIeReeR { SpaccIeReeR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 4 - TEE interrupt enable"]
#[inline (always)] pub fn spacc_ie_tee (& self) -> SpaccIeTeeR { SpaccIeTeeR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 8 - HPP interrupt enable"]
#[inline (always)] pub fn spacc_ie_hpp (& self) -> SpaccIeHppR { SpaccIeHppR :: new (((self . bits >> 8) & 1) != 0) } } impl W {
#[doc = "Bit 0 - REE interrupt enable"]
#[inline (always)] pub fn spacc_ie_ree (& mut self) -> SpaccIeReeW < '_ , SpaccIeSpec > { SpaccIeReeW :: new (self , 0) }
#[doc = "Bit 4 - TEE interrupt enable"]
#[inline (always)] pub fn spacc_ie_tee (& mut self) -> SpaccIeTeeW < '_ , SpaccIeSpec > { SpaccIeTeeW :: new (self , 4) }
#[doc = "Bit 8 - HPP interrupt enable"]
#[inline (always)] pub fn spacc_ie_hpp (& mut self) -> SpaccIeHppW < '_ , SpaccIeSpec > { SpaccIeHppW :: new (self , 8) } }
#[doc = "SPACC interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpaccIeSpec ; impl crate :: RegisterSpec for SpaccIeSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spacc_ie::R`](R) reader structure"] impl crate :: Readable for SpaccIeSpec { }
#[doc = "`write(|w| ..)` method takes [`spacc_ie::W`](W) writer structure"] impl crate :: Writable for SpaccIeSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPACC_IE to value 0"] impl crate :: Resettable for SpaccIeSpec { } }
#[doc = "SPACC_INT_RAW_SYM_CLR_FINISH (rw) register accessor: Sym clear finish raw interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_int_raw_sym_clr_finish::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_int_raw_sym_clr_finish::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_int_raw_sym_clr_finish`] module"]
#[doc (alias = "SPACC_INT_RAW_SYM_CLR_FINISH")] pub type SpaccIntRawSymClrFinish = crate :: Reg < spacc_int_raw_sym_clr_finish :: SpaccIntRawSymClrFinishSpec > ;
#[doc = "Sym clear finish raw interrupt"] pub mod spacc_int_raw_sym_clr_finish {
#[doc = "Register `SPACC_INT_RAW_SYM_CLR_FINISH` reader"] pub type R = crate :: R < SpaccIntRawSymClrFinishSpec > ;
#[doc = "Register `SPACC_INT_RAW_SYM_CLR_FINISH` writer"] pub type W = crate :: W < SpaccIntRawSymClrFinishSpec > ;
#[doc = "Field `raw_sym_clr_finish_int` reader - Raw interrupt for sym clear finish"] pub type RawSymClrFinishIntR = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Raw interrupt for sym clear finish"]
#[inline (always)] pub fn raw_sym_clr_finish_int (& self) -> RawSymClrFinishIntR { RawSymClrFinishIntR :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "Sym clear finish raw interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_int_raw_sym_clr_finish::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_int_raw_sym_clr_finish::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpaccIntRawSymClrFinishSpec ; impl crate :: RegisterSpec for SpaccIntRawSymClrFinishSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spacc_int_raw_sym_clr_finish::R`](R) reader structure"] impl crate :: Readable for SpaccIntRawSymClrFinishSpec { }
#[doc = "`write(|w| ..)` method takes [`spacc_int_raw_sym_clr_finish::W`](W) writer structure"] impl crate :: Writable for SpaccIntRawSymClrFinishSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPACC_INT_RAW_SYM_CLR_FINISH to value 0"] impl crate :: Resettable for SpaccIntRawSymClrFinishSpec { } }
#[doc = "SPACC_SYM_CHN_LOCK (rw) register accessor: Sym channel lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_sym_chn_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_sym_chn_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_sym_chn_lock`] module"]
#[doc (alias = "SPACC_SYM_CHN_LOCK")] pub type SpaccSymChnLock = crate :: Reg < spacc_sym_chn_lock :: SpaccSymChnLockSpec > ;
#[doc = "Sym channel lock register"] pub mod spacc_sym_chn_lock {
#[doc = "Register `SPACC_SYM_CHN_LOCK` reader"] pub type R = crate :: R < SpaccSymChnLockSpec > ;
#[doc = "Register `SPACC_SYM_CHN_LOCK` writer"] pub type W = crate :: W < SpaccSymChnLockSpec > ;
#[doc = "Field `sym_chn_lock` reader - Symmetric channel lock status"] pub type SymChnLockR = crate :: FieldReader < u32 > ;
#[doc = "Field `sym_chn_lock` writer - Symmetric channel lock status"] pub type SymChnLockW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Symmetric channel lock status"]
#[inline (always)] pub fn sym_chn_lock (& self) -> SymChnLockR { SymChnLockR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Symmetric channel lock status"]
#[inline (always)] pub fn sym_chn_lock (& mut self) -> SymChnLockW < '_ , SpaccSymChnLockSpec > { SymChnLockW :: new (self , 0) } }
#[doc = "Sym channel lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_sym_chn_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_sym_chn_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpaccSymChnLockSpec ; impl crate :: RegisterSpec for SpaccSymChnLockSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spacc_sym_chn_lock::R`](R) reader structure"] impl crate :: Readable for SpaccSymChnLockSpec { }
#[doc = "`write(|w| ..)` method takes [`spacc_sym_chn_lock::W`](W) writer structure"] impl crate :: Writable for SpaccSymChnLockSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPACC_SYM_CHN_LOCK to value 0"] impl crate :: Resettable for SpaccSymChnLockSpec { } }
#[doc = "SPACC_HASH_CHN_LOCK (rw) register accessor: Hash channel lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_hash_chn_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_hash_chn_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_hash_chn_lock`] module"]
#[doc (alias = "SPACC_HASH_CHN_LOCK")] pub type SpaccHashChnLock = crate :: Reg < spacc_hash_chn_lock :: SpaccHashChnLockSpec > ;
#[doc = "Hash channel lock register"] pub mod spacc_hash_chn_lock {
#[doc = "Register `SPACC_HASH_CHN_LOCK` reader"] pub type R = crate :: R < SpaccHashChnLockSpec > ;
#[doc = "Register `SPACC_HASH_CHN_LOCK` writer"] pub type W = crate :: W < SpaccHashChnLockSpec > ;
#[doc = "Field `hash_chn_lock` reader - Hash channel lock status"] pub type HashChnLockR = crate :: FieldReader < u32 > ;
#[doc = "Field `hash_chn_lock` writer - Hash channel lock status"] pub type HashChnLockW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Hash channel lock status"]
#[inline (always)] pub fn hash_chn_lock (& self) -> HashChnLockR { HashChnLockR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Hash channel lock status"]
#[inline (always)] pub fn hash_chn_lock (& mut self) -> HashChnLockW < '_ , SpaccHashChnLockSpec > { HashChnLockW :: new (self , 0) } }
#[doc = "Hash channel lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_hash_chn_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_hash_chn_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpaccHashChnLockSpec ; impl crate :: RegisterSpec for SpaccHashChnLockSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spacc_hash_chn_lock::R`](R) reader structure"] impl crate :: Readable for SpaccHashChnLockSpec { }
#[doc = "`write(|w| ..)` method takes [`spacc_hash_chn_lock::W`](W) writer structure"] impl crate :: Writable for SpaccHashChnLockSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPACC_HASH_CHN_LOCK to value 0"] impl crate :: Resettable for SpaccHashChnLockSpec { } }
#[doc = "SPACC_SYM_CHN_CLEAR_REQ (rw) register accessor: Sym channel clear request\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_sym_chn_clear_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_sym_chn_clear_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_sym_chn_clear_req`] module"]
#[doc (alias = "SPACC_SYM_CHN_CLEAR_REQ")] pub type SpaccSymChnClearReq = crate :: Reg < spacc_sym_chn_clear_req :: SpaccSymChnClearReqSpec > ;
#[doc = "Sym channel clear request"] pub mod spacc_sym_chn_clear_req {
#[doc = "Register `SPACC_SYM_CHN_CLEAR_REQ` reader"] pub type R = crate :: R < SpaccSymChnClearReqSpec > ;
#[doc = "Register `SPACC_SYM_CHN_CLEAR_REQ` writer"] pub type W = crate :: W < SpaccSymChnClearReqSpec > ;
#[doc = "Field `sym_chn_clear_req` writer - Clear request for symmetric channels"] pub type SymChnClearReqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl W {
#[doc = "Bits 0:31 - Clear request for symmetric channels"]
#[inline (always)] pub fn sym_chn_clear_req (& mut self) -> SymChnClearReqW < '_ , SpaccSymChnClearReqSpec > { SymChnClearReqW :: new (self , 0) } }
#[doc = "Sym channel clear request\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_sym_chn_clear_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_sym_chn_clear_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpaccSymChnClearReqSpec ; impl crate :: RegisterSpec for SpaccSymChnClearReqSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spacc_sym_chn_clear_req::R`](R) reader structure"] impl crate :: Readable for SpaccSymChnClearReqSpec { }
#[doc = "`write(|w| ..)` method takes [`spacc_sym_chn_clear_req::W`](W) writer structure"] impl crate :: Writable for SpaccSymChnClearReqSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPACC_SYM_CHN_CLEAR_REQ to value 0"] impl crate :: Resettable for SpaccSymChnClearReqSpec { } }
#[doc = "SPACC_HASH_CHN_CLEAR_REQ (rw) register accessor: Hash channel clear request\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_hash_chn_clear_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_hash_chn_clear_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_hash_chn_clear_req`] module"]
#[doc (alias = "SPACC_HASH_CHN_CLEAR_REQ")] pub type SpaccHashChnClearReq = crate :: Reg < spacc_hash_chn_clear_req :: SpaccHashChnClearReqSpec > ;
#[doc = "Hash channel clear request"] pub mod spacc_hash_chn_clear_req {
#[doc = "Register `SPACC_HASH_CHN_CLEAR_REQ` reader"] pub type R = crate :: R < SpaccHashChnClearReqSpec > ;
#[doc = "Register `SPACC_HASH_CHN_CLEAR_REQ` writer"] pub type W = crate :: W < SpaccHashChnClearReqSpec > ;
#[doc = "Field `hash_chn_clear_req` writer - Clear request for hash channels"] pub type HashChnClearReqW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl W {
#[doc = "Bits 0:31 - Clear request for hash channels"]
#[inline (always)] pub fn hash_chn_clear_req (& mut self) -> HashChnClearReqW < '_ , SpaccHashChnClearReqSpec > { HashChnClearReqW :: new (self , 0) } }
#[doc = "Hash channel clear request\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_hash_chn_clear_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_hash_chn_clear_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpaccHashChnClearReqSpec ; impl crate :: RegisterSpec for SpaccHashChnClearReqSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spacc_hash_chn_clear_req::R`](R) reader structure"] impl crate :: Readable for SpaccHashChnClearReqSpec { }
#[doc = "`write(|w| ..)` method takes [`spacc_hash_chn_clear_req::W`](W) writer structure"] impl crate :: Writable for SpaccHashChnClearReqSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPACC_HASH_CHN_CLEAR_REQ to value 0"] impl crate :: Resettable for SpaccHashChnClearReqSpec { } }
#[doc = "SPACC_BUS_ERR (rw) register accessor: Bus error register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_bus_err::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_bus_err::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spacc_bus_err`] module"]
#[doc (alias = "SPACC_BUS_ERR")] pub type SpaccBusErr = crate :: Reg < spacc_bus_err :: SpaccBusErrSpec > ;
#[doc = "Bus error register"] pub mod spacc_bus_err {
#[doc = "Register `SPACC_BUS_ERR` reader"] pub type R = crate :: R < SpaccBusErrSpec > ;
#[doc = "Register `SPACC_BUS_ERR` writer"] pub type W = crate :: W < SpaccBusErrSpec > ;
#[doc = "Field `bus_err` reader - Bus error status"] pub type BusErrR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - Bus error status"]
#[inline (always)] pub fn bus_err (& self) -> BusErrR { BusErrR :: new (self . bits) } } impl W { }
#[doc = "Bus error register\n\nYou can [`read`](crate::Reg::read) this register and get [`spacc_bus_err::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spacc_bus_err::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SpaccBusErrSpec ; impl crate :: RegisterSpec for SpaccBusErrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`spacc_bus_err::R`](R) reader structure"] impl crate :: Readable for SpaccBusErrSpec { }
#[doc = "`write(|w| ..)` method takes [`spacc_bus_err::W`](W) writer structure"] impl crate :: Writable for SpaccBusErrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SPACC_BUS_ERR to value 0"] impl crate :: Resettable for SpaccBusErrSpec { } }
#[doc = "IN_SYM_CHN0_CTRL (rw) register accessor: Sym channel 0 control register (no-DMA mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_ctrl`] module"]
#[doc (alias = "IN_SYM_CHN0_CTRL")] pub type InSymChn0Ctrl = crate :: Reg < in_sym_chn0_ctrl :: InSymChn0CtrlSpec > ;
#[doc = "Sym channel 0 control register (no-DMA mode)"] pub mod in_sym_chn0_ctrl {
#[doc = "Register `IN_SYM_CHN0_CTRL` reader"] pub type R = crate :: R < InSymChn0CtrlSpec > ;
#[doc = "Register `IN_SYM_CHN0_CTRL` writer"] pub type W = crate :: W < InSymChn0CtrlSpec > ;
#[doc = "Field `sym_chn0_req` writer - Channel 0 start request"] pub type SymChn0ReqW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 31 - Channel 0 start request"]
#[inline (always)] pub fn sym_chn0_req (& mut self) -> SymChn0ReqW < '_ , InSymChn0CtrlSpec > { SymChn0ReqW :: new (self , 31) } }
#[doc = "Sym channel 0 control register (no-DMA mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct InSymChn0CtrlSpec ; impl crate :: RegisterSpec for InSymChn0CtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`in_sym_chn0_ctrl::R`](R) reader structure"] impl crate :: Readable for InSymChn0CtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`in_sym_chn0_ctrl::W`](W) writer structure"] impl crate :: Writable for InSymChn0CtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets IN_SYM_CHN0_CTRL to value 0"] impl crate :: Resettable for InSymChn0CtrlSpec { } }
#[doc = "IN_SYM_CHN0_KEY_CTRL (rw) register accessor: Sym channel 0 key control (no-DMA mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_key_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_key_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_key_ctrl`] module"]
#[doc (alias = "IN_SYM_CHN0_KEY_CTRL")] pub type InSymChn0KeyCtrl = crate :: Reg < in_sym_chn0_key_ctrl :: InSymChn0KeyCtrlSpec > ;
#[doc = "Sym channel 0 key control (no-DMA mode)"] pub mod in_sym_chn0_key_ctrl {
#[doc = "Register `IN_SYM_CHN0_KEY_CTRL` reader"] pub type R = crate :: R < InSymChn0KeyCtrlSpec > ;
#[doc = "Register `IN_SYM_CHN0_KEY_CTRL` writer"] pub type W = crate :: W < InSymChn0KeyCtrlSpec > ;
#[doc = "Field `key_chn_id` reader - Key channel ID"] pub type KeyChnIdR = crate :: FieldReader < u16 > ;
#[doc = "Field `key_chn_id` writer - Key channel ID"] pub type KeyChnIdW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ;
#[doc = "Algorithm: 2=AES; 4=LEA; 5=SM4; 6=GHASH; 7=TDES\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum AlgSel {
#[doc = "2: AES algorithm"] Aes = 2 ,
#[doc = "4: LEA (Lightweight Encryption Algorithm)"] Lea = 4 ,
#[doc = "5: SM4 (Chinese national standard)"] Sm4 = 5 ,
#[doc = "6: GHASH (GCM authentication)"] Ghash = 6 ,
#[doc = "7: Triple DES"] Tdes = 7 , } impl From < AlgSel > for u8 {
#[inline (always)] fn from (variant : AlgSel) -> Self { variant as _ } } impl crate :: FieldSpec for AlgSel { type Ux = u8 ; } impl crate :: IsEnum for AlgSel { }
#[doc = "Field `alg_sel` reader - Algorithm: 2=AES; 4=LEA; 5=SM4; 6=GHASH; 7=TDES"] pub type AlgSelR = crate :: FieldReader < AlgSel > ; impl AlgSelR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < AlgSel > { match self . bits { 2 => Some (AlgSel :: Aes) , 4 => Some (AlgSel :: Lea) , 5 => Some (AlgSel :: Sm4) , 6 => Some (AlgSel :: Ghash) , 7 => Some (AlgSel :: Tdes) , _ => None , } }
#[doc = "AES algorithm"]
#[inline (always)] pub fn is_aes (& self) -> bool { * self == AlgSel :: Aes }
#[doc = "LEA (Lightweight Encryption Algorithm)"]
#[inline (always)] pub fn is_lea (& self) -> bool { * self == AlgSel :: Lea }
#[doc = "SM4 (Chinese national standard)"]
#[inline (always)] pub fn is_sm4 (& self) -> bool { * self == AlgSel :: Sm4 }
#[doc = "GHASH (GCM authentication)"]
#[inline (always)] pub fn is_ghash (& self) -> bool { * self == AlgSel :: Ghash }
#[doc = "Triple DES"]
#[inline (always)] pub fn is_tdes (& self) -> bool { * self == AlgSel :: Tdes } }
#[doc = "Field `alg_sel` writer - Algorithm: 2=AES; 4=LEA; 5=SM4; 6=GHASH; 7=TDES"] pub type AlgSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , AlgSel > ; impl < 'a , REG > AlgSelW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "AES algorithm"]
#[inline (always)] pub fn aes (self) -> & 'a mut crate :: W < REG > { self . variant (AlgSel :: Aes) }
#[doc = "LEA (Lightweight Encryption Algorithm)"]
#[inline (always)] pub fn lea (self) -> & 'a mut crate :: W < REG > { self . variant (AlgSel :: Lea) }
#[doc = "SM4 (Chinese national standard)"]
#[inline (always)] pub fn sm4 (self) -> & 'a mut crate :: W < REG > { self . variant (AlgSel :: Sm4) }
#[doc = "GHASH (GCM authentication)"]
#[inline (always)] pub fn ghash (self) -> & 'a mut crate :: W < REG > { self . variant (AlgSel :: Ghash) }
#[doc = "Triple DES"]
#[inline (always)] pub fn tdes (self) -> & 'a mut crate :: W < REG > { self . variant (AlgSel :: Tdes) } }
#[doc = "Mode: 1=ECB; 3=CBC; 6=CTR; 0xA=GCM; 0xC=CMAC\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum AlgMode {
#[doc = "1: Electronic Codebook"] Ecb = 1 ,
#[doc = "3: Cipher Block Chaining"] Cbc = 3 ,
#[doc = "6: Counter mode"] Ctr = 6 ,
#[doc = "7: Output Feedback"] Ofb = 7 ,
#[doc = "8: Cipher Feedback"] Cfb = 8 ,
#[doc = "9: CCM authenticated encryption"] Ccm = 9 ,
#[doc = "10: Galois/Counter Mode"] Gcm = 10 ,
#[doc = "11: GCM CTR only"] Gctr = 11 ,
#[doc = "12: Cipher-based MAC"] Cmac = 12 , } impl From < AlgMode > for u8 {
#[inline (always)] fn from (variant : AlgMode) -> Self { variant as _ } } impl crate :: FieldSpec for AlgMode { type Ux = u8 ; } impl crate :: IsEnum for AlgMode { }
#[doc = "Field `alg_mode` reader - Mode: 1=ECB; 3=CBC; 6=CTR; 0xA=GCM; 0xC=CMAC"] pub type AlgModeR = crate :: FieldReader < AlgMode > ; impl AlgModeR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < AlgMode > { match self . bits { 1 => Some (AlgMode :: Ecb) , 3 => Some (AlgMode :: Cbc) , 6 => Some (AlgMode :: Ctr) , 7 => Some (AlgMode :: Ofb) , 8 => Some (AlgMode :: Cfb) , 9 => Some (AlgMode :: Ccm) , 10 => Some (AlgMode :: Gcm) , 11 => Some (AlgMode :: Gctr) , 12 => Some (AlgMode :: Cmac) , _ => None , } }
#[doc = "Electronic Codebook"]
#[inline (always)] pub fn is_ecb (& self) -> bool { * self == AlgMode :: Ecb }
#[doc = "Cipher Block Chaining"]
#[inline (always)] pub fn is_cbc (& self) -> bool { * self == AlgMode :: Cbc }
#[doc = "Counter mode"]
#[inline (always)] pub fn is_ctr (& self) -> bool { * self == AlgMode :: Ctr }
#[doc = "Output Feedback"]
#[inline (always)] pub fn is_ofb (& self) -> bool { * self == AlgMode :: Ofb }
#[doc = "Cipher Feedback"]
#[inline (always)] pub fn is_cfb (& self) -> bool { * self == AlgMode :: Cfb }
#[doc = "CCM authenticated encryption"]
#[inline (always)] pub fn is_ccm (& self) -> bool { * self == AlgMode :: Ccm }
#[doc = "Galois/Counter Mode"]
#[inline (always)] pub fn is_gcm (& self) -> bool { * self == AlgMode :: Gcm }
#[doc = "GCM CTR only"]
#[inline (always)] pub fn is_gctr (& self) -> bool { * self == AlgMode :: Gctr }
#[doc = "Cipher-based MAC"]
#[inline (always)] pub fn is_cmac (& self) -> bool { * self == AlgMode :: Cmac } }
#[doc = "Field `alg_mode` writer - Mode: 1=ECB; 3=CBC; 6=CTR; 0xA=GCM; 0xC=CMAC"] pub type AlgModeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , AlgMode > ; impl < 'a , REG > AlgModeW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Electronic Codebook"]
#[inline (always)] pub fn ecb (self) -> & 'a mut crate :: W < REG > { self . variant (AlgMode :: Ecb) }
#[doc = "Cipher Block Chaining"]
#[inline (always)] pub fn cbc (self) -> & 'a mut crate :: W < REG > { self . variant (AlgMode :: Cbc) }
#[doc = "Counter mode"]
#[inline (always)] pub fn ctr (self) -> & 'a mut crate :: W < REG > { self . variant (AlgMode :: Ctr) }
#[doc = "Output Feedback"]
#[inline (always)] pub fn ofb (self) -> & 'a mut crate :: W < REG > { self . variant (AlgMode :: Ofb) }
#[doc = "Cipher Feedback"]
#[inline (always)] pub fn cfb (self) -> & 'a mut crate :: W < REG > { self . variant (AlgMode :: Cfb) }
#[doc = "CCM authenticated encryption"]
#[inline (always)] pub fn ccm (self) -> & 'a mut crate :: W < REG > { self . variant (AlgMode :: Ccm) }
#[doc = "Galois/Counter Mode"]
#[inline (always)] pub fn gcm (self) -> & 'a mut crate :: W < REG > { self . variant (AlgMode :: Gcm) }
#[doc = "GCM CTR only"]
#[inline (always)] pub fn gctr (self) -> & 'a mut crate :: W < REG > { self . variant (AlgMode :: Gctr) }
#[doc = "Cipher-based MAC"]
#[inline (always)] pub fn cmac (self) -> & 'a mut crate :: W < REG > { self . variant (AlgMode :: Cmac) } }
#[doc = "Key length: 0=128bit; 1=192bit; 2=256bit\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum KeyLen {
#[doc = "0: 128-bit key"] Key128 = 0 ,
#[doc = "1: 192-bit key"] Key192 = 1 ,
#[doc = "2: 256-bit key"] Key256 = 2 , } impl From < KeyLen > for u8 {
#[inline (always)] fn from (variant : KeyLen) -> Self { variant as _ } } impl crate :: FieldSpec for KeyLen { type Ux = u8 ; } impl crate :: IsEnum for KeyLen { }
#[doc = "Field `key_len` reader - Key length: 0=128bit; 1=192bit; 2=256bit"] pub type KeyLenR = crate :: FieldReader < KeyLen > ; impl KeyLenR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < KeyLen > { match self . bits { 0 => Some (KeyLen :: Key128) , 1 => Some (KeyLen :: Key192) , 2 => Some (KeyLen :: Key256) , _ => None , } }
#[doc = "128-bit key"]
#[inline (always)] pub fn is_key128 (& self) -> bool { * self == KeyLen :: Key128 }
#[doc = "192-bit key"]
#[inline (always)] pub fn is_key192 (& self) -> bool { * self == KeyLen :: Key192 }
#[doc = "256-bit key"]
#[inline (always)] pub fn is_key256 (& self) -> bool { * self == KeyLen :: Key256 } }
#[doc = "Field `key_len` writer - Key length: 0=128bit; 1=192bit; 2=256bit"] pub type KeyLenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , KeyLen > ; impl < 'a , REG > KeyLenW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "128-bit key"]
#[inline (always)] pub fn key128 (self) -> & 'a mut crate :: W < REG > { self . variant (KeyLen :: Key128) }
#[doc = "192-bit key"]
#[inline (always)] pub fn key192 (self) -> & 'a mut crate :: W < REG > { self . variant (KeyLen :: Key192) }
#[doc = "256-bit key"]
#[inline (always)] pub fn key256 (self) -> & 'a mut crate :: W < REG > { self . variant (KeyLen :: Key256) } }
#[doc = "Data width: 0=128bit; 1=64bit; 2=32bit\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum DataWidth {
#[doc = "0: 128-bit data path"] Width128 = 0 ,
#[doc = "1: 64-bit data path"] Width64 = 1 ,
#[doc = "2: 32-bit data path"] Width32 = 2 , } impl From < DataWidth > for u8 {
#[inline (always)] fn from (variant : DataWidth) -> Self { variant as _ } } impl crate :: FieldSpec for DataWidth { type Ux = u8 ; } impl crate :: IsEnum for DataWidth { }
#[doc = "Field `data_width` reader - Data width: 0=128bit; 1=64bit; 2=32bit"] pub type DataWidthR = crate :: FieldReader < DataWidth > ; impl DataWidthR {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < DataWidth > { match self . bits { 0 => Some (DataWidth :: Width128) , 1 => Some (DataWidth :: Width64) , 2 => Some (DataWidth :: Width32) , _ => None , } }
#[doc = "128-bit data path"]
#[inline (always)] pub fn is_width128 (& self) -> bool { * self == DataWidth :: Width128 }
#[doc = "64-bit data path"]
#[inline (always)] pub fn is_width64 (& self) -> bool { * self == DataWidth :: Width64 }
#[doc = "32-bit data path"]
#[inline (always)] pub fn is_width32 (& self) -> bool { * self == DataWidth :: Width32 } }
#[doc = "Field `data_width` writer - Data width: 0=128bit; 1=64bit; 2=32bit"] pub type DataWidthW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 , DataWidth > ; impl < 'a , REG > DataWidthW < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "128-bit data path"]
#[inline (always)] pub fn width128 (self) -> & 'a mut crate :: W < REG > { self . variant (DataWidth :: Width128) }
#[doc = "64-bit data path"]
#[inline (always)] pub fn width64 (self) -> & 'a mut crate :: W < REG > { self . variant (DataWidth :: Width64) }
#[doc = "32-bit data path"]
#[inline (always)] pub fn width32 (self) -> & 'a mut crate :: W < REG > { self . variant (DataWidth :: Width32) } }
#[doc = "Field `decrypt` reader - Decrypt: 0=encrypt; 1=decrypt"] pub type DecryptR = crate :: BitReader ;
#[doc = "Field `decrypt` writer - Decrypt: 0=encrypt; 1=decrypt"] pub type DecryptW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:8 - Key channel ID"]
#[inline (always)] pub fn key_chn_id (& self) -> KeyChnIdR { KeyChnIdR :: new ((self . bits & 0x01ff) as u16) }
#[doc = "Bits 16:19 - Algorithm: 2=AES; 4=LEA; 5=SM4; 6=GHASH; 7=TDES"]
#[inline (always)] pub fn alg_sel (& self) -> AlgSelR { AlgSelR :: new (((self . bits >> 16) & 0x0f) as u8) }
#[doc = "Bits 20:23 - Mode: 1=ECB; 3=CBC; 6=CTR; 0xA=GCM; 0xC=CMAC"]
#[inline (always)] pub fn alg_mode (& self) -> AlgModeR { AlgModeR :: new (((self . bits >> 20) & 0x0f) as u8) }
#[doc = "Bits 24:25 - Key length: 0=128bit; 1=192bit; 2=256bit"]
#[inline (always)] pub fn key_len (& self) -> KeyLenR { KeyLenR :: new (((self . bits >> 24) & 3) as u8) }
#[doc = "Bits 26:27 - Data width: 0=128bit; 1=64bit; 2=32bit"]
#[inline (always)] pub fn data_width (& self) -> DataWidthR { DataWidthR :: new (((self . bits >> 26) & 3) as u8) }
#[doc = "Bit 28 - Decrypt: 0=encrypt; 1=decrypt"]
#[inline (always)] pub fn decrypt (& self) -> DecryptR { DecryptR :: new (((self . bits >> 28) & 1) != 0) } } impl W {
#[doc = "Bits 0:8 - Key channel ID"]
#[inline (always)] pub fn key_chn_id (& mut self) -> KeyChnIdW < '_ , InSymChn0KeyCtrlSpec > { KeyChnIdW :: new (self , 0) }
#[doc = "Bits 16:19 - Algorithm: 2=AES; 4=LEA; 5=SM4; 6=GHASH; 7=TDES"]
#[inline (always)] pub fn alg_sel (& mut self) -> AlgSelW < '_ , InSymChn0KeyCtrlSpec > { AlgSelW :: new (self , 16) }
#[doc = "Bits 20:23 - Mode: 1=ECB; 3=CBC; 6=CTR; 0xA=GCM; 0xC=CMAC"]
#[inline (always)] pub fn alg_mode (& mut self) -> AlgModeW < '_ , InSymChn0KeyCtrlSpec > { AlgModeW :: new (self , 20) }
#[doc = "Bits 24:25 - Key length: 0=128bit; 1=192bit; 2=256bit"]
#[inline (always)] pub fn key_len (& mut self) -> KeyLenW < '_ , InSymChn0KeyCtrlSpec > { KeyLenW :: new (self , 24) }
#[doc = "Bits 26:27 - Data width: 0=128bit; 1=64bit; 2=32bit"]
#[inline (always)] pub fn data_width (& mut self) -> DataWidthW < '_ , InSymChn0KeyCtrlSpec > { DataWidthW :: new (self , 26) }
#[doc = "Bit 28 - Decrypt: 0=encrypt; 1=decrypt"]
#[inline (always)] pub fn decrypt (& mut self) -> DecryptW < '_ , InSymChn0KeyCtrlSpec > { DecryptW :: new (self , 28) } }
#[doc = "Sym channel 0 key control (no-DMA mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_key_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_key_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct InSymChn0KeyCtrlSpec ; impl crate :: RegisterSpec for InSymChn0KeyCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`in_sym_chn0_key_ctrl::R`](R) reader structure"] impl crate :: Readable for InSymChn0KeyCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`in_sym_chn0_key_ctrl::W`](W) writer structure"] impl crate :: Writable for InSymChn0KeyCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets IN_SYM_CHN0_KEY_CTRL to value 0"] impl crate :: Resettable for InSymChn0KeyCtrlSpec { } }
#[doc = "IN_SYM_CHN0_SPECIAL_CTRL (rw) register accessor: Sym channel 0 special control\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_special_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_special_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_special_ctrl`] module"]
#[doc (alias = "IN_SYM_CHN0_SPECIAL_CTRL")] pub type InSymChn0SpecialCtrl = crate :: Reg < in_sym_chn0_special_ctrl :: InSymChn0SpecialCtrlSpec > ;
#[doc = "Sym channel 0 special control"] pub mod in_sym_chn0_special_ctrl {
#[doc = "Register `IN_SYM_CHN0_SPECIAL_CTRL` reader"] pub type R = crate :: R < InSymChn0SpecialCtrlSpec > ;
#[doc = "Register `IN_SYM_CHN0_SPECIAL_CTRL` writer"] pub type W = crate :: W < InSymChn0SpecialCtrlSpec > ;
#[doc = "Field `sym_chn0_odd_even` reader - Odd/even control for TDES"] pub type SymChn0OddEvenR = crate :: BitReader ;
#[doc = "Field `sym_chn0_odd_even` writer - Odd/even control for TDES"] pub type SymChn0OddEvenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Odd/even control for TDES"]
#[inline (always)] pub fn sym_chn0_odd_even (& self) -> SymChn0OddEvenR { SymChn0OddEvenR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Odd/even control for TDES"]
#[inline (always)] pub fn sym_chn0_odd_even (& mut self) -> SymChn0OddEvenW < '_ , InSymChn0SpecialCtrlSpec > { SymChn0OddEvenW :: new (self , 0) } }
#[doc = "Sym channel 0 special control\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_special_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_special_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct InSymChn0SpecialCtrlSpec ; impl crate :: RegisterSpec for InSymChn0SpecialCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`in_sym_chn0_special_ctrl::R`](R) reader structure"] impl crate :: Readable for InSymChn0SpecialCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`in_sym_chn0_special_ctrl::W`](W) writer structure"] impl crate :: Writable for InSymChn0SpecialCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets IN_SYM_CHN0_SPECIAL_CTRL to value 0"] impl crate :: Resettable for InSymChn0SpecialCtrlSpec { } }
#[doc = "IN_SYM_CHN0_IV_DATA_CTRL (rw) register accessor: Sym channel 0 IV/data control (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv_data_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv_data_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_iv_data_ctrl`] module"]
#[doc (alias = "IN_SYM_CHN0_IV_DATA_CTRL")] pub type InSymChn0IvDataCtrl = crate :: Reg < in_sym_chn0_iv_data_ctrl :: InSymChn0IvDataCtrlSpec > ;
#[doc = "Sym channel 0 IV/data control (register mode)"] pub mod in_sym_chn0_iv_data_ctrl {
#[doc = "Register `IN_SYM_CHN0_IV_DATA_CTRL` reader"] pub type R = crate :: R < InSymChn0IvDataCtrlSpec > ;
#[doc = "Register `IN_SYM_CHN0_IV_DATA_CTRL` writer"] pub type W = crate :: W < InSymChn0IvDataCtrlSpec > ;
#[doc = "Field `first_block` reader - First block flag"] pub type FirstBlockR = crate :: BitReader ;
#[doc = "Field `first_block` writer - First block flag"] pub type FirstBlockW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `last_block` reader - Last block flag"] pub type LastBlockR = crate :: BitReader ;
#[doc = "Field `last_block` writer - Last block flag"] pub type LastBlockW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `block_len` reader - Block length (in bytes)"] pub type BlockLenR = crate :: FieldReader ;
#[doc = "Field `block_len` writer - Block length (in bytes)"] pub type BlockLenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R {
#[doc = "Bit 0 - First block flag"]
#[inline (always)] pub fn first_block (& self) -> FirstBlockR { FirstBlockR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Last block flag"]
#[inline (always)] pub fn last_block (& self) -> LastBlockR { LastBlockR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bits 16:20 - Block length (in bytes)"]
#[inline (always)] pub fn block_len (& self) -> BlockLenR { BlockLenR :: new (((self . bits >> 16) & 0x1f) as u8) } } impl W {
#[doc = "Bit 0 - First block flag"]
#[inline (always)] pub fn first_block (& mut self) -> FirstBlockW < '_ , InSymChn0IvDataCtrlSpec > { FirstBlockW :: new (self , 0) }
#[doc = "Bit 1 - Last block flag"]
#[inline (always)] pub fn last_block (& mut self) -> LastBlockW < '_ , InSymChn0IvDataCtrlSpec > { LastBlockW :: new (self , 1) }
#[doc = "Bits 16:20 - Block length (in bytes)"]
#[inline (always)] pub fn block_len (& mut self) -> BlockLenW < '_ , InSymChn0IvDataCtrlSpec > { BlockLenW :: new (self , 16) } }
#[doc = "Sym channel 0 IV/data control (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv_data_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv_data_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct InSymChn0IvDataCtrlSpec ; impl crate :: RegisterSpec for InSymChn0IvDataCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`in_sym_chn0_iv_data_ctrl::R`](R) reader structure"] impl crate :: Readable for InSymChn0IvDataCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`in_sym_chn0_iv_data_ctrl::W`](W) writer structure"] impl crate :: Writable for InSymChn0IvDataCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets IN_SYM_CHN0_IV_DATA_CTRL to value 0"] impl crate :: Resettable for InSymChn0IvDataCtrlSpec { } }
#[doc = "IN_SYM_CHN0_IV0 (rw) register accessor: Sym channel 0 IV word 0 (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_iv0`] module"]
#[doc (alias = "IN_SYM_CHN0_IV0")] pub type InSymChn0Iv0 = crate :: Reg < in_sym_chn0_iv0 :: InSymChn0Iv0Spec > ;
#[doc = "Sym channel 0 IV word 0 (register mode)"] pub mod in_sym_chn0_iv0 {
#[doc = "Register `IN_SYM_CHN0_IV0` reader"] pub type R = crate :: R < InSymChn0Iv0Spec > ;
#[doc = "Register `IN_SYM_CHN0_IV0` writer"] pub type W = crate :: W < InSymChn0Iv0Spec > ;
#[doc = "Field `iv0` reader - IV\\[31:0\\]"] pub type Iv0R = crate :: FieldReader < u32 > ;
#[doc = "Field `iv0` writer - IV\\[31:0\\]"] pub type Iv0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - IV\\[31:0\\]"]
#[inline (always)] pub fn iv0 (& self) -> Iv0R { Iv0R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - IV\\[31:0\\]"]
#[inline (always)] pub fn iv0 (& mut self) -> Iv0W < '_ , InSymChn0Iv0Spec > { Iv0W :: new (self , 0) } }
#[doc = "Sym channel 0 IV word 0 (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct InSymChn0Iv0Spec ; impl crate :: RegisterSpec for InSymChn0Iv0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`in_sym_chn0_iv0::R`](R) reader structure"] impl crate :: Readable for InSymChn0Iv0Spec { }
#[doc = "`write(|w| ..)` method takes [`in_sym_chn0_iv0::W`](W) writer structure"] impl crate :: Writable for InSymChn0Iv0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets IN_SYM_CHN0_IV0 to value 0"] impl crate :: Resettable for InSymChn0Iv0Spec { } }
#[doc = "IN_SYM_CHN0_IV1 (rw) register accessor: Sym channel 0 IV word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_iv1`] module"]
#[doc (alias = "IN_SYM_CHN0_IV1")] pub type InSymChn0Iv1 = crate :: Reg < in_sym_chn0_iv1 :: InSymChn0Iv1Spec > ;
#[doc = "Sym channel 0 IV word 1"] pub mod in_sym_chn0_iv1 {
#[doc = "Register `IN_SYM_CHN0_IV1` reader"] pub type R = crate :: R < InSymChn0Iv1Spec > ;
#[doc = "Register `IN_SYM_CHN0_IV1` writer"] pub type W = crate :: W < InSymChn0Iv1Spec > ;
#[doc = "Field `iv1` reader - IV\\[63:32\\]"] pub type Iv1R = crate :: FieldReader < u32 > ;
#[doc = "Field `iv1` writer - IV\\[63:32\\]"] pub type Iv1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - IV\\[63:32\\]"]
#[inline (always)] pub fn iv1 (& self) -> Iv1R { Iv1R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - IV\\[63:32\\]"]
#[inline (always)] pub fn iv1 (& mut self) -> Iv1W < '_ , InSymChn0Iv1Spec > { Iv1W :: new (self , 0) } }
#[doc = "Sym channel 0 IV word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct InSymChn0Iv1Spec ; impl crate :: RegisterSpec for InSymChn0Iv1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`in_sym_chn0_iv1::R`](R) reader structure"] impl crate :: Readable for InSymChn0Iv1Spec { }
#[doc = "`write(|w| ..)` method takes [`in_sym_chn0_iv1::W`](W) writer structure"] impl crate :: Writable for InSymChn0Iv1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets IN_SYM_CHN0_IV1 to value 0"] impl crate :: Resettable for InSymChn0Iv1Spec { } }
#[doc = "IN_SYM_CHN0_IV2 (rw) register accessor: Sym channel 0 IV word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_iv2`] module"]
#[doc (alias = "IN_SYM_CHN0_IV2")] pub type InSymChn0Iv2 = crate :: Reg < in_sym_chn0_iv2 :: InSymChn0Iv2Spec > ;
#[doc = "Sym channel 0 IV word 2"] pub mod in_sym_chn0_iv2 {
#[doc = "Register `IN_SYM_CHN0_IV2` reader"] pub type R = crate :: R < InSymChn0Iv2Spec > ;
#[doc = "Register `IN_SYM_CHN0_IV2` writer"] pub type W = crate :: W < InSymChn0Iv2Spec > ;
#[doc = "Field `iv2` reader - IV\\[95:64\\]"] pub type Iv2R = crate :: FieldReader < u32 > ;
#[doc = "Field `iv2` writer - IV\\[95:64\\]"] pub type Iv2W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - IV\\[95:64\\]"]
#[inline (always)] pub fn iv2 (& self) -> Iv2R { Iv2R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - IV\\[95:64\\]"]
#[inline (always)] pub fn iv2 (& mut self) -> Iv2W < '_ , InSymChn0Iv2Spec > { Iv2W :: new (self , 0) } }
#[doc = "Sym channel 0 IV word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct InSymChn0Iv2Spec ; impl crate :: RegisterSpec for InSymChn0Iv2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`in_sym_chn0_iv2::R`](R) reader structure"] impl crate :: Readable for InSymChn0Iv2Spec { }
#[doc = "`write(|w| ..)` method takes [`in_sym_chn0_iv2::W`](W) writer structure"] impl crate :: Writable for InSymChn0Iv2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets IN_SYM_CHN0_IV2 to value 0"] impl crate :: Resettable for InSymChn0Iv2Spec { } }
#[doc = "IN_SYM_CHN0_IV3 (rw) register accessor: Sym channel 0 IV word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_iv3`] module"]
#[doc (alias = "IN_SYM_CHN0_IV3")] pub type InSymChn0Iv3 = crate :: Reg < in_sym_chn0_iv3 :: InSymChn0Iv3Spec > ;
#[doc = "Sym channel 0 IV word 3"] pub mod in_sym_chn0_iv3 {
#[doc = "Register `IN_SYM_CHN0_IV3` reader"] pub type R = crate :: R < InSymChn0Iv3Spec > ;
#[doc = "Register `IN_SYM_CHN0_IV3` writer"] pub type W = crate :: W < InSymChn0Iv3Spec > ;
#[doc = "Field `iv3` reader - IV\\[127:96\\]"] pub type Iv3R = crate :: FieldReader < u32 > ;
#[doc = "Field `iv3` writer - IV\\[127:96\\]"] pub type Iv3W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - IV\\[127:96\\]"]
#[inline (always)] pub fn iv3 (& self) -> Iv3R { Iv3R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - IV\\[127:96\\]"]
#[inline (always)] pub fn iv3 (& mut self) -> Iv3W < '_ , InSymChn0Iv3Spec > { Iv3W :: new (self , 0) } }
#[doc = "Sym channel 0 IV word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_iv3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_iv3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct InSymChn0Iv3Spec ; impl crate :: RegisterSpec for InSymChn0Iv3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`in_sym_chn0_iv3::R`](R) reader structure"] impl crate :: Readable for InSymChn0Iv3Spec { }
#[doc = "`write(|w| ..)` method takes [`in_sym_chn0_iv3::W`](W) writer structure"] impl crate :: Writable for InSymChn0Iv3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets IN_SYM_CHN0_IV3 to value 0"] impl crate :: Resettable for InSymChn0Iv3Spec { } }
#[doc = "IN_SYM_CHN0_DATA0 (rw) register accessor: Sym channel 0 data word 0 (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_data0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_data0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sym_chn0_data0`] module"]
#[doc (alias = "IN_SYM_CHN0_DATA0")] pub type InSymChn0Data0 = crate :: Reg < in_sym_chn0_data0 :: InSymChn0Data0Spec > ;
#[doc = "Sym channel 0 data word 0 (register mode)"] pub mod in_sym_chn0_data0 {
#[doc = "Register `IN_SYM_CHN0_DATA0` reader"] pub type R = crate :: R < InSymChn0Data0Spec > ;
#[doc = "Register `IN_SYM_CHN0_DATA0` writer"] pub type W = crate :: W < InSymChn0Data0Spec > ;
#[doc = "Field `data0` reader - Input data\\[31:0\\]"] pub type Data0R = crate :: FieldReader < u32 > ;
#[doc = "Field `data0` writer - Input data\\[31:0\\]"] pub type Data0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Input data\\[31:0\\]"]
#[inline (always)] pub fn data0 (& self) -> Data0R { Data0R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Input data\\[31:0\\]"]
#[inline (always)] pub fn data0 (& mut self) -> Data0W < '_ , InSymChn0Data0Spec > { Data0W :: new (self , 0) } }
#[doc = "Sym channel 0 data word 0 (register mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sym_chn0_data0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sym_chn0_data0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct InSymChn0Data0Spec ; impl crate :: RegisterSpec for InSymChn0Data0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`in_sym_chn0_data0::R`](R) reader structure"] impl crate :: Readable for InSymChn0Data0Spec { }
#[doc = "`write(|w| ..)` method takes [`in_sym_chn0_data0::W`](W) writer structure"] impl crate :: Writable for InSymChn0Data0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets IN_SYM_CHN0_DATA0 to value 0"] impl crate :: Resettable for InSymChn0Data0Spec { } }
#[doc = "SYM_CHANN_RAW_INT (rw) register accessor: Sym channel raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`sym_chann_raw_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sym_chann_raw_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sym_chann_raw_int`] module"]
#[doc (alias = "SYM_CHANN_RAW_INT")] pub type SymChannRawInt = crate :: Reg < sym_chann_raw_int :: SymChannRawIntSpec > ;
#[doc = "Sym channel raw interrupt status"] pub mod sym_chann_raw_int {
#[doc = "Register `SYM_CHANN_RAW_INT` reader"] pub type R = crate :: R < SymChannRawIntSpec > ;
#[doc = "Register `SYM_CHANN_RAW_INT` writer"] pub type W = crate :: W < SymChannRawIntSpec > ;
#[doc = "Field `sym_chann_raw_int` reader - Raw interrupt per channel \\[15:0\\]"] pub type SymChannRawIntR = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Raw interrupt per channel \\[15:0\\]"]
#[inline (always)] pub fn sym_chann_raw_int (& self) -> SymChannRawIntR { SymChannRawIntR :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "Sym channel raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`sym_chann_raw_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sym_chann_raw_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SymChannRawIntSpec ; impl crate :: RegisterSpec for SymChannRawIntSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`sym_chann_raw_int::R`](R) reader structure"] impl crate :: Readable for SymChannRawIntSpec { }
#[doc = "`write(|w| ..)` method takes [`sym_chann_raw_int::W`](W) writer structure"] impl crate :: Writable for SymChannRawIntSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SYM_CHANN_RAW_INT to value 0"] impl crate :: Resettable for SymChannRawIntSpec { } } }
#[doc = "Public Key Engine - modular arithmetic accelerator"] pub type Pke = crate :: Periph < pke :: RegisterBlock , 0x4411_0000 > ; impl core :: fmt :: Debug for Pke { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Pke") . finish () } }
#[doc = "Public Key Engine - modular arithmetic accelerator"] pub mod pke {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { pke_work_len : PkeWorkLen , pke_instr0 : PkeInstr0 , pke_instr1 : PkeInstr1 , pke_instr_addr_low : PkeInstrAddrLow , pke_instr_addr_hig : PkeInstrAddrHig , pke_instr_len : PkeInstrLen , pke_mask_rng_cfg : PkeMaskRngCfg , _reserved7 : [u8 ; 0x04] , pke_mont_para0 : PkeMontPara0 , pke_mont_para1 : PkeMontPara1 , _reserved9 : [u8 ; 0x18] , pke_start : PkeStart , pke_instr_rdy : PkeInstrRdy , pke_busy : PkeBusy , pke_noise_en : PkeNoiseEn , _reserved13 : [u8 ; 0x30] , pke_int_enable : PkeIntEnable , pke_int_nomask_status : PkeIntNomaskStatus , _reserved15 : [u8 ; 0x04] , pke_alarm_status : PkeAlarmStatus , pke_failure_flag : PkeFailureFlag , _reserved17 : [u8 ; 0x2c] , pke_dram_clr : PkeDramClr , _reserved18 : [u8 ; 0x074c] , pke_lock_ctrl : PkeLockCtrl , pke_lock_status : PkeLockStatus , } impl RegisterBlock {
#[doc = "0x00 - PKE work length register"]
#[inline (always)] pub const fn pke_work_len (& self) -> & PkeWorkLen { & self . pke_work_len }
#[doc = "0x04 - PKE instruction register 0"]
#[inline (always)] pub const fn pke_instr0 (& self) -> & PkeInstr0 { & self . pke_instr0 }
#[doc = "0x08 - PKE instruction register 1"]
#[inline (always)] pub const fn pke_instr1 (& self) -> & PkeInstr1 { & self . pke_instr1 }
#[doc = "0x0c - PKE instruction start address low"]
#[inline (always)] pub const fn pke_instr_addr_low (& self) -> & PkeInstrAddrLow { & self . pke_instr_addr_low }
#[doc = "0x10 - PKE instruction start address high"]
#[inline (always)] pub const fn pke_instr_addr_hig (& self) -> & PkeInstrAddrHig { & self . pke_instr_addr_hig }
#[doc = "0x14 - PKE instruction length"]
#[inline (always)] pub const fn pke_instr_len (& self) -> & PkeInstrLen { & self . pke_instr_len }
#[doc = "0x18 - PKE mask RNG configuration"]
#[inline (always)] pub const fn pke_mask_rng_cfg (& self) -> & PkeMaskRngCfg { & self . pke_mask_rng_cfg }
#[doc = "0x20 - PKE Montgomery parameter 0"]
#[inline (always)] pub const fn pke_mont_para0 (& self) -> & PkeMontPara0 { & self . pke_mont_para0 }
#[doc = "0x24 - PKE Montgomery parameter 1"]
#[inline (always)] pub const fn pke_mont_para1 (& self) -> & PkeMontPara1 { & self . pke_mont_para1 }
#[doc = "0x40 - PKE start control register"]
#[inline (always)] pub const fn pke_start (& self) -> & PkeStart { & self . pke_start }
#[doc = "0x44 - PKE instruction ready status"]
#[inline (always)] pub const fn pke_instr_rdy (& self) -> & PkeInstrRdy { & self . pke_instr_rdy }
#[doc = "0x48 - PKE busy status register"]
#[inline (always)] pub const fn pke_busy (& self) -> & PkeBusy { & self . pke_busy }
#[doc = "0x4c - PKE noise enable register"]
#[inline (always)] pub const fn pke_noise_en (& self) -> & PkeNoiseEn { & self . pke_noise_en }
#[doc = "0x80 - PKE interrupt enable"]
#[inline (always)] pub const fn pke_int_enable (& self) -> & PkeIntEnable { & self . pke_int_enable }
#[doc = "0x84 - PKE unmasked interrupt status"]
#[inline (always)] pub const fn pke_int_nomask_status (& self) -> & PkeIntNomaskStatus { & self . pke_int_nomask_status }
#[doc = "0x8c - PKE alarm status register"]
#[inline (always)] pub const fn pke_alarm_status (& self) -> & PkeAlarmStatus { & self . pke_alarm_status }
#[doc = "0x90 - PKE failure flag register"]
#[inline (always)] pub const fn pke_failure_flag (& self) -> & PkeFailureFlag { & self . pke_failure_flag }
#[doc = "0xc0 - PKE DRAM clear register"]
#[inline (always)] pub const fn pke_dram_clr (& self) -> & PkeDramClr { & self . pke_dram_clr }
#[doc = "0x810 - PKE lock control register"]
#[inline (always)] pub const fn pke_lock_ctrl (& self) -> & PkeLockCtrl { & self . pke_lock_ctrl }
#[doc = "0x814 - PKE lock status register"]
#[inline (always)] pub const fn pke_lock_status (& self) -> & PkeLockStatus { & self . pke_lock_status } }
#[doc = "PKE_WORK_LEN (rw) register accessor: PKE work length register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_work_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_work_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_work_len`] module"]
#[doc (alias = "PKE_WORK_LEN")] pub type PkeWorkLen = crate :: Reg < pke_work_len :: PkeWorkLenSpec > ;
#[doc = "PKE work length register"] pub mod pke_work_len {
#[doc = "Register `PKE_WORK_LEN` reader"] pub type R = crate :: R < PkeWorkLenSpec > ;
#[doc = "Register `PKE_WORK_LEN` writer"] pub type W = crate :: W < PkeWorkLenSpec > ;
#[doc = "Field `work_len` reader - Operand bit length for modular arithmetic"] pub type WorkLenR = crate :: FieldReader < u32 > ;
#[doc = "Field `work_len` writer - Operand bit length for modular arithmetic"] pub type WorkLenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Operand bit length for modular arithmetic"]
#[inline (always)] pub fn work_len (& self) -> WorkLenR { WorkLenR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Operand bit length for modular arithmetic"]
#[inline (always)] pub fn work_len (& mut self) -> WorkLenW < '_ , PkeWorkLenSpec > { WorkLenW :: new (self , 0) } }
#[doc = "PKE work length register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_work_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_work_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeWorkLenSpec ; impl crate :: RegisterSpec for PkeWorkLenSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_work_len::R`](R) reader structure"] impl crate :: Readable for PkeWorkLenSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_work_len::W`](W) writer structure"] impl crate :: Writable for PkeWorkLenSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_WORK_LEN to value 0"] impl crate :: Resettable for PkeWorkLenSpec { } }
#[doc = "PKE_INSTR0 (rw) register accessor: PKE instruction register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr0`] module"]
#[doc (alias = "PKE_INSTR0")] pub type PkeInstr0 = crate :: Reg < pke_instr0 :: PkeInstr0Spec > ;
#[doc = "PKE instruction register 0"] pub mod pke_instr0 {
#[doc = "Register `PKE_INSTR0` reader"] pub type R = crate :: R < PkeInstr0Spec > ;
#[doc = "Register `PKE_INSTR0` writer"] pub type W = crate :: W < PkeInstr0Spec > ;
#[doc = "Instruction code 0 (0=MUL_MOD, 1=ADD_MOD, 2=SUB_MOD)\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u32)] pub enum Instr0 {
#[doc = "0: Modular multiplication"] MulMod = 0 ,
#[doc = "1: Modular addition"] AddMod = 1 ,
#[doc = "2: Modular subtraction"] SubMod = 2 , } impl From < Instr0 > for u32 {
#[inline (always)] fn from (variant : Instr0) -> Self { variant as _ } } impl crate :: FieldSpec for Instr0 { type Ux = u32 ; } impl crate :: IsEnum for Instr0 { }
#[doc = "Field `instr0` reader - Instruction code 0 (0=MUL_MOD, 1=ADD_MOD, 2=SUB_MOD)"] pub type Instr0R = crate :: FieldReader < Instr0 > ; impl Instr0R {
#[doc = "Get enumerated values variant"]
#[inline (always)] pub const fn variant (& self) -> Option < Instr0 > { match self . bits { 0 => Some (Instr0 :: MulMod) , 1 => Some (Instr0 :: AddMod) , 2 => Some (Instr0 :: SubMod) , _ => None , } }
#[doc = "Modular multiplication"]
#[inline (always)] pub fn is_mul_mod (& self) -> bool { * self == Instr0 :: MulMod }
#[doc = "Modular addition"]
#[inline (always)] pub fn is_add_mod (& self) -> bool { * self == Instr0 :: AddMod }
#[doc = "Modular subtraction"]
#[inline (always)] pub fn is_sub_mod (& self) -> bool { * self == Instr0 :: SubMod } }
#[doc = "Field `instr0` writer - Instruction code 0 (0=MUL_MOD, 1=ADD_MOD, 2=SUB_MOD)"] pub type Instr0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , Instr0 > ; impl < 'a , REG > Instr0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u32 > {
#[doc = "Modular multiplication"]
#[inline (always)] pub fn mul_mod (self) -> & 'a mut crate :: W < REG > { self . variant (Instr0 :: MulMod) }
#[doc = "Modular addition"]
#[inline (always)] pub fn add_mod (self) -> & 'a mut crate :: W < REG > { self . variant (Instr0 :: AddMod) }
#[doc = "Modular subtraction"]
#[inline (always)] pub fn sub_mod (self) -> & 'a mut crate :: W < REG > { self . variant (Instr0 :: SubMod) } } impl R {
#[doc = "Bits 0:31 - Instruction code 0 (0=MUL_MOD, 1=ADD_MOD, 2=SUB_MOD)"]
#[inline (always)] pub fn instr0 (& self) -> Instr0R { Instr0R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Instruction code 0 (0=MUL_MOD, 1=ADD_MOD, 2=SUB_MOD)"]
#[inline (always)] pub fn instr0 (& mut self) -> Instr0W < '_ , PkeInstr0Spec > { Instr0W :: new (self , 0) } }
#[doc = "PKE instruction register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeInstr0Spec ; impl crate :: RegisterSpec for PkeInstr0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_instr0::R`](R) reader structure"] impl crate :: Readable for PkeInstr0Spec { }
#[doc = "`write(|w| ..)` method takes [`pke_instr0::W`](W) writer structure"] impl crate :: Writable for PkeInstr0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_INSTR0 to value 0"] impl crate :: Resettable for PkeInstr0Spec { } }
#[doc = "PKE_INSTR1 (rw) register accessor: PKE instruction register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr1`] module"]
#[doc (alias = "PKE_INSTR1")] pub type PkeInstr1 = crate :: Reg < pke_instr1 :: PkeInstr1Spec > ;
#[doc = "PKE instruction register 1"] pub mod pke_instr1 {
#[doc = "Register `PKE_INSTR1` reader"] pub type R = crate :: R < PkeInstr1Spec > ;
#[doc = "Register `PKE_INSTR1` writer"] pub type W = crate :: W < PkeInstr1Spec > ;
#[doc = "Field `instr1` reader - Instruction code 1"] pub type Instr1R = crate :: FieldReader < u32 > ;
#[doc = "Field `instr1` writer - Instruction code 1"] pub type Instr1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Instruction code 1"]
#[inline (always)] pub fn instr1 (& self) -> Instr1R { Instr1R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Instruction code 1"]
#[inline (always)] pub fn instr1 (& mut self) -> Instr1W < '_ , PkeInstr1Spec > { Instr1W :: new (self , 0) } }
#[doc = "PKE instruction register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeInstr1Spec ; impl crate :: RegisterSpec for PkeInstr1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_instr1::R`](R) reader structure"] impl crate :: Readable for PkeInstr1Spec { }
#[doc = "`write(|w| ..)` method takes [`pke_instr1::W`](W) writer structure"] impl crate :: Writable for PkeInstr1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_INSTR1 to value 0"] impl crate :: Resettable for PkeInstr1Spec { } }
#[doc = "PKE_INSTR_ADDR_LOW (rw) register accessor: PKE instruction start address low\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_addr_low::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_addr_low::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr_addr_low`] module"]
#[doc (alias = "PKE_INSTR_ADDR_LOW")] pub type PkeInstrAddrLow = crate :: Reg < pke_instr_addr_low :: PkeInstrAddrLowSpec > ;
#[doc = "PKE instruction start address low"] pub mod pke_instr_addr_low {
#[doc = "Register `PKE_INSTR_ADDR_LOW` reader"] pub type R = crate :: R < PkeInstrAddrLowSpec > ;
#[doc = "Register `PKE_INSTR_ADDR_LOW` writer"] pub type W = crate :: W < PkeInstrAddrLowSpec > ;
#[doc = "Field `instr_addr_low` reader - Instruction start address \\[31:0\\]"] pub type InstrAddrLowR = crate :: FieldReader < u32 > ;
#[doc = "Field `instr_addr_low` writer - Instruction start address \\[31:0\\]"] pub type InstrAddrLowW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Instruction start address \\[31:0\\]"]
#[inline (always)] pub fn instr_addr_low (& self) -> InstrAddrLowR { InstrAddrLowR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Instruction start address \\[31:0\\]"]
#[inline (always)] pub fn instr_addr_low (& mut self) -> InstrAddrLowW < '_ , PkeInstrAddrLowSpec > { InstrAddrLowW :: new (self , 0) } }
#[doc = "PKE instruction start address low\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_addr_low::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_addr_low::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeInstrAddrLowSpec ; impl crate :: RegisterSpec for PkeInstrAddrLowSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_instr_addr_low::R`](R) reader structure"] impl crate :: Readable for PkeInstrAddrLowSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_instr_addr_low::W`](W) writer structure"] impl crate :: Writable for PkeInstrAddrLowSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_INSTR_ADDR_LOW to value 0"] impl crate :: Resettable for PkeInstrAddrLowSpec { } }
#[doc = "PKE_INSTR_ADDR_HIG (rw) register accessor: PKE instruction start address high\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_addr_hig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_addr_hig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr_addr_hig`] module"]
#[doc (alias = "PKE_INSTR_ADDR_HIG")] pub type PkeInstrAddrHig = crate :: Reg < pke_instr_addr_hig :: PkeInstrAddrHigSpec > ;
#[doc = "PKE instruction start address high"] pub mod pke_instr_addr_hig {
#[doc = "Register `PKE_INSTR_ADDR_HIG` reader"] pub type R = crate :: R < PkeInstrAddrHigSpec > ;
#[doc = "Register `PKE_INSTR_ADDR_HIG` writer"] pub type W = crate :: W < PkeInstrAddrHigSpec > ;
#[doc = "Field `instr_addr_hig` reader - Instruction start address high bits"] pub type InstrAddrHigR = crate :: FieldReader < u32 > ;
#[doc = "Field `instr_addr_hig` writer - Instruction start address high bits"] pub type InstrAddrHigW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Instruction start address high bits"]
#[inline (always)] pub fn instr_addr_hig (& self) -> InstrAddrHigR { InstrAddrHigR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Instruction start address high bits"]
#[inline (always)] pub fn instr_addr_hig (& mut self) -> InstrAddrHigW < '_ , PkeInstrAddrHigSpec > { InstrAddrHigW :: new (self , 0) } }
#[doc = "PKE instruction start address high\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_addr_hig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_addr_hig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeInstrAddrHigSpec ; impl crate :: RegisterSpec for PkeInstrAddrHigSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_instr_addr_hig::R`](R) reader structure"] impl crate :: Readable for PkeInstrAddrHigSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_instr_addr_hig::W`](W) writer structure"] impl crate :: Writable for PkeInstrAddrHigSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_INSTR_ADDR_HIG to value 0"] impl crate :: Resettable for PkeInstrAddrHigSpec { } }
#[doc = "PKE_INSTR_LEN (rw) register accessor: PKE instruction length\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr_len`] module"]
#[doc (alias = "PKE_INSTR_LEN")] pub type PkeInstrLen = crate :: Reg < pke_instr_len :: PkeInstrLenSpec > ;
#[doc = "PKE instruction length"] pub mod pke_instr_len {
#[doc = "Register `PKE_INSTR_LEN` reader"] pub type R = crate :: R < PkeInstrLenSpec > ;
#[doc = "Register `PKE_INSTR_LEN` writer"] pub type W = crate :: W < PkeInstrLenSpec > ;
#[doc = "Field `instr_len` reader - Total instruction length in bytes"] pub type InstrLenR = crate :: FieldReader < u32 > ;
#[doc = "Field `instr_len` writer - Total instruction length in bytes"] pub type InstrLenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Total instruction length in bytes"]
#[inline (always)] pub fn instr_len (& self) -> InstrLenR { InstrLenR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Total instruction length in bytes"]
#[inline (always)] pub fn instr_len (& mut self) -> InstrLenW < '_ , PkeInstrLenSpec > { InstrLenW :: new (self , 0) } }
#[doc = "PKE instruction length\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeInstrLenSpec ; impl crate :: RegisterSpec for PkeInstrLenSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_instr_len::R`](R) reader structure"] impl crate :: Readable for PkeInstrLenSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_instr_len::W`](W) writer structure"] impl crate :: Writable for PkeInstrLenSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_INSTR_LEN to value 0"] impl crate :: Resettable for PkeInstrLenSpec { } }
#[doc = "PKE_MASK_RNG_CFG (rw) register accessor: PKE mask RNG configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mask_rng_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mask_rng_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_mask_rng_cfg`] module"]
#[doc (alias = "PKE_MASK_RNG_CFG")] pub type PkeMaskRngCfg = crate :: Reg < pke_mask_rng_cfg :: PkeMaskRngCfgSpec > ;
#[doc = "PKE mask RNG configuration"] pub mod pke_mask_rng_cfg {
#[doc = "Register `PKE_MASK_RNG_CFG` reader"] pub type R = crate :: R < PkeMaskRngCfgSpec > ;
#[doc = "Register `PKE_MASK_RNG_CFG` writer"] pub type W = crate :: W < PkeMaskRngCfgSpec > ;
#[doc = "Field `mask_rng_cfg` reader - Mask RNG enable: 0=disabled; 1=enabled"] pub type MaskRngCfgR = crate :: BitReader ;
#[doc = "Field `mask_rng_cfg` writer - Mask RNG enable: 0=disabled; 1=enabled"] pub type MaskRngCfgW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Mask RNG enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn mask_rng_cfg (& self) -> MaskRngCfgR { MaskRngCfgR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Mask RNG enable: 0=disabled; 1=enabled"]
#[inline (always)] pub fn mask_rng_cfg (& mut self) -> MaskRngCfgW < '_ , PkeMaskRngCfgSpec > { MaskRngCfgW :: new (self , 0) } }
#[doc = "PKE mask RNG configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mask_rng_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mask_rng_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeMaskRngCfgSpec ; impl crate :: RegisterSpec for PkeMaskRngCfgSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_mask_rng_cfg::R`](R) reader structure"] impl crate :: Readable for PkeMaskRngCfgSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_mask_rng_cfg::W`](W) writer structure"] impl crate :: Writable for PkeMaskRngCfgSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_MASK_RNG_CFG to value 0"] impl crate :: Resettable for PkeMaskRngCfgSpec { } }
#[doc = "PKE_MONT_PARA0 (rw) register accessor: PKE Montgomery parameter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mont_para0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mont_para0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_mont_para0`] module"]
#[doc (alias = "PKE_MONT_PARA0")] pub type PkeMontPara0 = crate :: Reg < pke_mont_para0 :: PkeMontPara0Spec > ;
#[doc = "PKE Montgomery parameter 0"] pub mod pke_mont_para0 {
#[doc = "Register `PKE_MONT_PARA0` reader"] pub type R = crate :: R < PkeMontPara0Spec > ;
#[doc = "Register `PKE_MONT_PARA0` writer"] pub type W = crate :: W < PkeMontPara0Spec > ;
#[doc = "Field `mont_para0` reader - Montgomery pre-computed parameter word 0"] pub type MontPara0R = crate :: FieldReader < u32 > ;
#[doc = "Field `mont_para0` writer - Montgomery pre-computed parameter word 0"] pub type MontPara0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Montgomery pre-computed parameter word 0"]
#[inline (always)] pub fn mont_para0 (& self) -> MontPara0R { MontPara0R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Montgomery pre-computed parameter word 0"]
#[inline (always)] pub fn mont_para0 (& mut self) -> MontPara0W < '_ , PkeMontPara0Spec > { MontPara0W :: new (self , 0) } }
#[doc = "PKE Montgomery parameter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mont_para0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mont_para0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeMontPara0Spec ; impl crate :: RegisterSpec for PkeMontPara0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_mont_para0::R`](R) reader structure"] impl crate :: Readable for PkeMontPara0Spec { }
#[doc = "`write(|w| ..)` method takes [`pke_mont_para0::W`](W) writer structure"] impl crate :: Writable for PkeMontPara0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_MONT_PARA0 to value 0"] impl crate :: Resettable for PkeMontPara0Spec { } }
#[doc = "PKE_MONT_PARA1 (rw) register accessor: PKE Montgomery parameter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mont_para1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mont_para1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_mont_para1`] module"]
#[doc (alias = "PKE_MONT_PARA1")] pub type PkeMontPara1 = crate :: Reg < pke_mont_para1 :: PkeMontPara1Spec > ;
#[doc = "PKE Montgomery parameter 1"] pub mod pke_mont_para1 {
#[doc = "Register `PKE_MONT_PARA1` reader"] pub type R = crate :: R < PkeMontPara1Spec > ;
#[doc = "Register `PKE_MONT_PARA1` writer"] pub type W = crate :: W < PkeMontPara1Spec > ;
#[doc = "Field `mont_para1` reader - Montgomery pre-computed parameter word 1"] pub type MontPara1R = crate :: FieldReader < u32 > ;
#[doc = "Field `mont_para1` writer - Montgomery pre-computed parameter word 1"] pub type MontPara1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Montgomery pre-computed parameter word 1"]
#[inline (always)] pub fn mont_para1 (& self) -> MontPara1R { MontPara1R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Montgomery pre-computed parameter word 1"]
#[inline (always)] pub fn mont_para1 (& mut self) -> MontPara1W < '_ , PkeMontPara1Spec > { MontPara1W :: new (self , 0) } }
#[doc = "PKE Montgomery parameter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_mont_para1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_mont_para1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeMontPara1Spec ; impl crate :: RegisterSpec for PkeMontPara1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_mont_para1::R`](R) reader structure"] impl crate :: Readable for PkeMontPara1Spec { }
#[doc = "`write(|w| ..)` method takes [`pke_mont_para1::W`](W) writer structure"] impl crate :: Writable for PkeMontPara1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_MONT_PARA1 to value 0"] impl crate :: Resettable for PkeMontPara1Spec { } }
#[doc = "PKE_START (rw) register accessor: PKE start control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_start`] module"]
#[doc (alias = "PKE_START")] pub type PkeStart = crate :: Reg < pke_start :: PkeStartSpec > ;
#[doc = "PKE start control register"] pub mod pke_start {
#[doc = "Register `PKE_START` reader"] pub type R = crate :: R < PkeStartSpec > ;
#[doc = "Register `PKE_START` writer"] pub type W = crate :: W < PkeStartSpec > ;
#[doc = "Start code 0 (write 0x5 to start)\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum PkeStart0 {
#[doc = "5: Must write 0x5 to start PKE operation"] StartCode = 5 , } impl From < PkeStart0 > for u8 {
#[inline (always)] fn from (variant : PkeStart0) -> Self { variant as _ } } impl crate :: FieldSpec for PkeStart0 { type Ux = u8 ; } impl crate :: IsEnum for PkeStart0 { }
#[doc = "Field `pke_start0` writer - Start code 0 (write 0x5 to start)"] pub type PkeStart0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , PkeStart0 > ; impl < 'a , REG > PkeStart0W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Must write 0x5 to start PKE operation"]
#[inline (always)] pub fn start_code (self) -> & 'a mut crate :: W < REG > { self . variant (PkeStart0 :: StartCode) } }
#[doc = "Start code 1 (write 0xA)\n\nValue on reset: 0"]
#[derive (Clone , Copy , Debug , PartialEq , Eq)]
#[repr (u8)] pub enum PkeStart1 {
#[doc = "10: Must write 0xA to start PKE operation"] StartCode = 10 , } impl From < PkeStart1 > for u8 {
#[inline (always)] fn from (variant : PkeStart1) -> Self { variant as _ } } impl crate :: FieldSpec for PkeStart1 { type Ux = u8 ; } impl crate :: IsEnum for PkeStart1 { }
#[doc = "Field `pke_start1` writer - Start code 1 (write 0xA)"] pub type PkeStart1W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 , PkeStart1 > ; impl < 'a , REG > PkeStart1W < 'a , REG > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > {
#[doc = "Must write 0xA to start PKE operation"]
#[inline (always)] pub fn start_code (self) -> & 'a mut crate :: W < REG > { self . variant (PkeStart1 :: StartCode) } }
#[doc = "Field `pke_batch_start` writer - Batch start code (write 0x5)"] pub type PkeBatchStartW < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl W {
#[doc = "Bits 0:3 - Start code 0 (write 0x5 to start)"]
#[inline (always)] pub fn pke_start0 (& mut self) -> PkeStart0W < '_ , PkeStartSpec > { PkeStart0W :: new (self , 0) }
#[doc = "Bits 4:7 - Start code 1 (write 0xA)"]
#[inline (always)] pub fn pke_start1 (& mut self) -> PkeStart1W < '_ , PkeStartSpec > { PkeStart1W :: new (self , 4) }
#[doc = "Bits 8:11 - Batch start code (write 0x5)"]
#[inline (always)] pub fn pke_batch_start (& mut self) -> PkeBatchStartW < '_ , PkeStartSpec > { PkeBatchStartW :: new (self , 8) } }
#[doc = "PKE start control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeStartSpec ; impl crate :: RegisterSpec for PkeStartSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_start::R`](R) reader structure"] impl crate :: Readable for PkeStartSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_start::W`](W) writer structure"] impl crate :: Writable for PkeStartSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_START to value 0"] impl crate :: Resettable for PkeStartSpec { } }
#[doc = "PKE_INSTR_RDY (rw) register accessor: PKE instruction ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_rdy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_rdy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_instr_rdy`] module"]
#[doc (alias = "PKE_INSTR_RDY")] pub type PkeInstrRdy = crate :: Reg < pke_instr_rdy :: PkeInstrRdySpec > ;
#[doc = "PKE instruction ready status"] pub mod pke_instr_rdy {
#[doc = "Register `PKE_INSTR_RDY` reader"] pub type R = crate :: R < PkeInstrRdySpec > ;
#[doc = "Register `PKE_INSTR_RDY` writer"] pub type W = crate :: W < PkeInstrRdySpec > ;
#[doc = "Field `instr0_rdy` reader - Instruction buffer 0 ready"] pub type Instr0RdyR = crate :: BitReader ;
#[doc = "Field `instr1_rdy` reader - Instruction buffer 1 ready"] pub type Instr1RdyR = crate :: BitReader ;
#[doc = "Field `batch_instr_rdy` reader - Batch instruction ready"] pub type BatchInstrRdyR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Instruction buffer 0 ready"]
#[inline (always)] pub fn instr0_rdy (& self) -> Instr0RdyR { Instr0RdyR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Instruction buffer 1 ready"]
#[inline (always)] pub fn instr1_rdy (& self) -> Instr1RdyR { Instr1RdyR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Batch instruction ready"]
#[inline (always)] pub fn batch_instr_rdy (& self) -> BatchInstrRdyR { BatchInstrRdyR :: new (((self . bits >> 2) & 1) != 0) } } impl W { }
#[doc = "PKE instruction ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_instr_rdy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_instr_rdy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeInstrRdySpec ; impl crate :: RegisterSpec for PkeInstrRdySpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_instr_rdy::R`](R) reader structure"] impl crate :: Readable for PkeInstrRdySpec { }
#[doc = "`write(|w| ..)` method takes [`pke_instr_rdy::W`](W) writer structure"] impl crate :: Writable for PkeInstrRdySpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_INSTR_RDY to value 0"] impl crate :: Resettable for PkeInstrRdySpec { } }
#[doc = "PKE_BUSY (rw) register accessor: PKE busy status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_busy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_busy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_busy`] module"]
#[doc (alias = "PKE_BUSY")] pub type PkeBusy = crate :: Reg < pke_busy :: PkeBusySpec > ;
#[doc = "PKE busy status register"] pub mod pke_busy {
#[doc = "Register `PKE_BUSY` reader"] pub type R = crate :: R < PkeBusySpec > ;
#[doc = "Register `PKE_BUSY` writer"] pub type W = crate :: W < PkeBusySpec > ;
#[doc = "Field `pke_busy` reader - PKE busy: 0=idle; 1=busy"] pub type PkeBusyR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - PKE busy: 0=idle; 1=busy"]
#[inline (always)] pub fn pke_busy (& self) -> PkeBusyR { PkeBusyR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "PKE busy status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_busy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_busy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeBusySpec ; impl crate :: RegisterSpec for PkeBusySpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_busy::R`](R) reader structure"] impl crate :: Readable for PkeBusySpec { }
#[doc = "`write(|w| ..)` method takes [`pke_busy::W`](W) writer structure"] impl crate :: Writable for PkeBusySpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_BUSY to value 0"] impl crate :: Resettable for PkeBusySpec { } }
#[doc = "PKE_NOISE_EN (rw) register accessor: PKE noise enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_noise_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_noise_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_noise_en`] module"]
#[doc (alias = "PKE_NOISE_EN")] pub type PkeNoiseEn = crate :: Reg < pke_noise_en :: PkeNoiseEnSpec > ;
#[doc = "PKE noise enable register"] pub mod pke_noise_en {
#[doc = "Register `PKE_NOISE_EN` reader"] pub type R = crate :: R < PkeNoiseEnSpec > ;
#[doc = "Register `PKE_NOISE_EN` writer"] pub type W = crate :: W < PkeNoiseEnSpec > ;
#[doc = "Field `noise_en` reader - Side-channel noise enable"] pub type NoiseEnR = crate :: BitReader ;
#[doc = "Field `noise_en` writer - Side-channel noise enable"] pub type NoiseEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Side-channel noise enable"]
#[inline (always)] pub fn noise_en (& self) -> NoiseEnR { NoiseEnR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Side-channel noise enable"]
#[inline (always)] pub fn noise_en (& mut self) -> NoiseEnW < '_ , PkeNoiseEnSpec > { NoiseEnW :: new (self , 0) } }
#[doc = "PKE noise enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_noise_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_noise_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeNoiseEnSpec ; impl crate :: RegisterSpec for PkeNoiseEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_noise_en::R`](R) reader structure"] impl crate :: Readable for PkeNoiseEnSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_noise_en::W`](W) writer structure"] impl crate :: Writable for PkeNoiseEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_NOISE_EN to value 0"] impl crate :: Resettable for PkeNoiseEnSpec { } }
#[doc = "PKE_INT_ENABLE (rw) register accessor: PKE interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_int_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_int_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_int_enable`] module"]
#[doc (alias = "PKE_INT_ENABLE")] pub type PkeIntEnable = crate :: Reg < pke_int_enable :: PkeIntEnableSpec > ;
#[doc = "PKE interrupt enable"] pub mod pke_int_enable {
#[doc = "Register `PKE_INT_ENABLE` reader"] pub type R = crate :: R < PkeIntEnableSpec > ;
#[doc = "Register `PKE_INT_ENABLE` writer"] pub type W = crate :: W < PkeIntEnableSpec > ;
#[doc = "Field `finish_int_enable` reader - Operation finish interrupt enable"] pub type FinishIntEnableR = crate :: BitReader ;
#[doc = "Field `finish_int_enable` writer - Operation finish interrupt enable"] pub type FinishIntEnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Operation finish interrupt enable"]
#[inline (always)] pub fn finish_int_enable (& self) -> FinishIntEnableR { FinishIntEnableR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - Operation finish interrupt enable"]
#[inline (always)] pub fn finish_int_enable (& mut self) -> FinishIntEnableW < '_ , PkeIntEnableSpec > { FinishIntEnableW :: new (self , 0) } }
#[doc = "PKE interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_int_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_int_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeIntEnableSpec ; impl crate :: RegisterSpec for PkeIntEnableSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_int_enable::R`](R) reader structure"] impl crate :: Readable for PkeIntEnableSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_int_enable::W`](W) writer structure"] impl crate :: Writable for PkeIntEnableSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_INT_ENABLE to value 0"] impl crate :: Resettable for PkeIntEnableSpec { } }
#[doc = "PKE_INT_NOMASK_STATUS (rw) register accessor: PKE unmasked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_int_nomask_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_int_nomask_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_int_nomask_status`] module"]
#[doc (alias = "PKE_INT_NOMASK_STATUS")] pub type PkeIntNomaskStatus = crate :: Reg < pke_int_nomask_status :: PkeIntNomaskStatusSpec > ;
#[doc = "PKE unmasked interrupt status"] pub mod pke_int_nomask_status {
#[doc = "Register `PKE_INT_NOMASK_STATUS` reader"] pub type R = crate :: R < PkeIntNomaskStatusSpec > ;
#[doc = "Register `PKE_INT_NOMASK_STATUS` writer"] pub type W = crate :: W < PkeIntNomaskStatusSpec > ;
#[doc = "Field `finish_int_nomask` reader - Finish interrupt status (expect 0x5 after completion)"] pub type FinishIntNomaskR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:3 - Finish interrupt status (expect 0x5 after completion)"]
#[inline (always)] pub fn finish_int_nomask (& self) -> FinishIntNomaskR { FinishIntNomaskR :: new ((self . bits & 0x0f) as u8) } } impl W { }
#[doc = "PKE unmasked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_int_nomask_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_int_nomask_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeIntNomaskStatusSpec ; impl crate :: RegisterSpec for PkeIntNomaskStatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_int_nomask_status::R`](R) reader structure"] impl crate :: Readable for PkeIntNomaskStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_int_nomask_status::W`](W) writer structure"] impl crate :: Writable for PkeIntNomaskStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_INT_NOMASK_STATUS to value 0"] impl crate :: Resettable for PkeIntNomaskStatusSpec { } }
#[doc = "PKE_ALARM_STATUS (rw) register accessor: PKE alarm status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_alarm_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_alarm_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_alarm_status`] module"]
#[doc (alias = "PKE_ALARM_STATUS")] pub type PkeAlarmStatus = crate :: Reg < pke_alarm_status :: PkeAlarmStatusSpec > ;
#[doc = "PKE alarm status register"] pub mod pke_alarm_status {
#[doc = "Register `PKE_ALARM_STATUS` reader"] pub type R = crate :: R < PkeAlarmStatusSpec > ;
#[doc = "Register `PKE_ALARM_STATUS` writer"] pub type W = crate :: W < PkeAlarmStatusSpec > ;
#[doc = "Field `alarm_int` reader - Security alarm interrupt"] pub type AlarmIntR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:3 - Security alarm interrupt"]
#[inline (always)] pub fn alarm_int (& self) -> AlarmIntR { AlarmIntR :: new ((self . bits & 0x0f) as u8) } } impl W { }
#[doc = "PKE alarm status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_alarm_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_alarm_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeAlarmStatusSpec ; impl crate :: RegisterSpec for PkeAlarmStatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_alarm_status::R`](R) reader structure"] impl crate :: Readable for PkeAlarmStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_alarm_status::W`](W) writer structure"] impl crate :: Writable for PkeAlarmStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_ALARM_STATUS to value 0"] impl crate :: Resettable for PkeAlarmStatusSpec { } }
#[doc = "PKE_FAILURE_FLAG (rw) register accessor: PKE failure flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_failure_flag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_failure_flag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_failure_flag`] module"]
#[doc (alias = "PKE_FAILURE_FLAG")] pub type PkeFailureFlag = crate :: Reg < pke_failure_flag :: PkeFailureFlagSpec > ;
#[doc = "PKE failure flag register"] pub mod pke_failure_flag {
#[doc = "Register `PKE_FAILURE_FLAG` reader"] pub type R = crate :: R < PkeFailureFlagSpec > ;
#[doc = "Register `PKE_FAILURE_FLAG` writer"] pub type W = crate :: W < PkeFailureFlagSpec > ;
#[doc = "Field `pke_failure_flag` reader - Operation failure status"] pub type PkeFailureFlagR = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:10 - Operation failure status"]
#[inline (always)] pub fn pke_failure_flag (& self) -> PkeFailureFlagR { PkeFailureFlagR :: new ((self . bits & 0x07ff) as u16) } } impl W { }
#[doc = "PKE failure flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_failure_flag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_failure_flag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeFailureFlagSpec ; impl crate :: RegisterSpec for PkeFailureFlagSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_failure_flag::R`](R) reader structure"] impl crate :: Readable for PkeFailureFlagSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_failure_flag::W`](W) writer structure"] impl crate :: Writable for PkeFailureFlagSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_FAILURE_FLAG to value 0"] impl crate :: Resettable for PkeFailureFlagSpec { } }
#[doc = "PKE_DRAM_CLR (rw) register accessor: PKE DRAM clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_dram_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_dram_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_dram_clr`] module"]
#[doc (alias = "PKE_DRAM_CLR")] pub type PkeDramClr = crate :: Reg < pke_dram_clr :: PkeDramClrSpec > ;
#[doc = "PKE DRAM clear register"] pub mod pke_dram_clr {
#[doc = "Register `PKE_DRAM_CLR` reader"] pub type R = crate :: R < PkeDramClrSpec > ;
#[doc = "Register `PKE_DRAM_CLR` writer"] pub type W = crate :: W < PkeDramClrSpec > ;
#[doc = "Field `dram_clr` writer - Clear PKE DRAM"] pub type DramClrW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W {
#[doc = "Bit 0 - Clear PKE DRAM"]
#[inline (always)] pub fn dram_clr (& mut self) -> DramClrW < '_ , PkeDramClrSpec > { DramClrW :: new (self , 0) } }
#[doc = "PKE DRAM clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_dram_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_dram_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeDramClrSpec ; impl crate :: RegisterSpec for PkeDramClrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_dram_clr::R`](R) reader structure"] impl crate :: Readable for PkeDramClrSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_dram_clr::W`](W) writer structure"] impl crate :: Writable for PkeDramClrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_DRAM_CLR to value 0"] impl crate :: Resettable for PkeDramClrSpec { } }
#[doc = "PKE_LOCK_CTRL (rw) register accessor: PKE lock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_lock_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_lock_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_lock_ctrl`] module"]
#[doc (alias = "PKE_LOCK_CTRL")] pub type PkeLockCtrl = crate :: Reg < pke_lock_ctrl :: PkeLockCtrlSpec > ;
#[doc = "PKE lock control register"] pub mod pke_lock_ctrl {
#[doc = "Register `PKE_LOCK_CTRL` reader"] pub type R = crate :: R < PkeLockCtrlSpec > ;
#[doc = "Register `PKE_LOCK_CTRL` writer"] pub type W = crate :: W < PkeLockCtrlSpec > ;
#[doc = "Field `pke_lock` reader - Lock request"] pub type PkeLockR = crate :: BitReader ;
#[doc = "Field `pke_lock` writer - Lock request"] pub type PkeLockW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pke_lock_type` reader - Lock type: 0=soft; 1=hard"] pub type PkeLockTypeR = crate :: BitReader ;
#[doc = "Field `pke_lock_type` writer - Lock type: 0=soft; 1=hard"] pub type PkeLockTypeW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Lock request"]
#[inline (always)] pub fn pke_lock (& self) -> PkeLockR { PkeLockR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Lock type: 0=soft; 1=hard"]
#[inline (always)] pub fn pke_lock_type (& self) -> PkeLockTypeR { PkeLockTypeR :: new (((self . bits >> 1) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Lock request"]
#[inline (always)] pub fn pke_lock (& mut self) -> PkeLockW < '_ , PkeLockCtrlSpec > { PkeLockW :: new (self , 0) }
#[doc = "Bit 1 - Lock type: 0=soft; 1=hard"]
#[inline (always)] pub fn pke_lock_type (& mut self) -> PkeLockTypeW < '_ , PkeLockCtrlSpec > { PkeLockTypeW :: new (self , 1) } }
#[doc = "PKE lock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_lock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_lock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeLockCtrlSpec ; impl crate :: RegisterSpec for PkeLockCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_lock_ctrl::R`](R) reader structure"] impl crate :: Readable for PkeLockCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_lock_ctrl::W`](W) writer structure"] impl crate :: Writable for PkeLockCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_LOCK_CTRL to value 0"] impl crate :: Resettable for PkeLockCtrlSpec { } }
#[doc = "PKE_LOCK_STATUS (rw) register accessor: PKE lock status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_lock_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_lock_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pke_lock_status`] module"]
#[doc (alias = "PKE_LOCK_STATUS")] pub type PkeLockStatus = crate :: Reg < pke_lock_status :: PkeLockStatusSpec > ;
#[doc = "PKE lock status register"] pub mod pke_lock_status {
#[doc = "Register `PKE_LOCK_STATUS` reader"] pub type R = crate :: R < PkeLockStatusSpec > ;
#[doc = "Register `PKE_LOCK_STATUS` writer"] pub type W = crate :: W < PkeLockStatusSpec > ;
#[doc = "Field `pke_lock_busy` reader - Lock busy flag"] pub type PkeLockBusyR = crate :: BitReader ;
#[doc = "Field `pke_unlock_fail` reader - Unlock failure flag"] pub type PkeUnlockFailR = crate :: BitReader ;
#[doc = "Field `pke_lock_cnt` reader - Lock count"] pub type PkeLockCntR = crate :: FieldReader ;
#[doc = "Field `pke_lock_stat` reader - Lock status: 0x6A=PCPU; 0x35=AIDSP; 0xA5=TEE; 0xAA=ACPU"] pub type PkeLockStatR = crate :: FieldReader ; impl R {
#[doc = "Bit 0 - Lock busy flag"]
#[inline (always)] pub fn pke_lock_busy (& self) -> PkeLockBusyR { PkeLockBusyR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Unlock failure flag"]
#[inline (always)] pub fn pke_unlock_fail (& self) -> PkeUnlockFailR { PkeUnlockFailR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bits 4:6 - Lock count"]
#[inline (always)] pub fn pke_lock_cnt (& self) -> PkeLockCntR { PkeLockCntR :: new (((self . bits >> 4) & 7) as u8) }
#[doc = "Bits 8:15 - Lock status: 0x6A=PCPU; 0x35=AIDSP; 0xA5=TEE; 0xAA=ACPU"]
#[inline (always)] pub fn pke_lock_stat (& self) -> PkeLockStatR { PkeLockStatR :: new (((self . bits >> 8) & 0xff) as u8) } } impl W { }
#[doc = "PKE lock status register\n\nYou can [`read`](crate::Reg::read) this register and get [`pke_lock_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pke_lock_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PkeLockStatusSpec ; impl crate :: RegisterSpec for PkeLockStatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`pke_lock_status::R`](R) reader structure"] impl crate :: Readable for PkeLockStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`pke_lock_status::W`](W) writer structure"] impl crate :: Writable for PkeLockStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets PKE_LOCK_STATUS to value 0"] impl crate :: Resettable for PkeLockStatusSpec { } } }
#[doc = "Key Management - KLAD key derivation, keyslot locking, RKP root key protection"] pub type Km = crate :: Periph < km :: RegisterBlock , 0x4411_2000 > ; impl core :: fmt :: Debug for Km { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Km") . finish () } }
#[doc = "Key Management - KLAD key derivation, keyslot locking, RKP root key protection"] pub mod km {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x1000] , kl_data_in_0 : KlDataIn0 , kl_data_in_1 : KlDataIn1 , kl_data_in_2 : KlDataIn2 , kl_data_in_3 : KlDataIn3 , kl_key_addr : KlKeyAddr , kl_key_cfg : KlKeyCfg , kl_key_sec_cfg : KlKeySecCfg , _reserved7 : [u8 ; 0x14] , kl_state : KlState , _reserved8 : [u8 ; 0x04] , kl_error : KlError , _reserved9 : [u8 ; 0x04] , kl_int_en : KlIntEn , _reserved10 : [u8 ; 0x04] , kl_int : KlInt , _reserved11 : [u8 ; 0x28] , kl_lock_ctrl : KlLockCtrl , _reserved12 : [u8 ; 0x0c] , kl_com_ctrl : KlComCtrl , kl_com_status : KlComStatus , _reserved14 : [u8 ; 0x0574] , kl_alarm_info : KlAlarmInfo , _reserved15 : [u8 ; 0x04fc] , kc_teecpu_lock_cmd : KcTeecpuLockCmd , _reserved16 : [u8 ; 0x30] , kc_rd_lock_status : KcRdLockStatus , } impl RegisterBlock {
#[doc = "0x1000 - Key data input word 0"]
#[inline (always)] pub const fn kl_data_in_0 (& self) -> & KlDataIn0 { & self . kl_data_in_0 }
#[doc = "0x1004 - Key data input word 1"]
#[inline (always)] pub const fn kl_data_in_1 (& self) -> & KlDataIn1 { & self . kl_data_in_1 }
#[doc = "0x1008 - Key data input word 2"]
#[inline (always)] pub const fn kl_data_in_2 (& self) -> & KlDataIn2 { & self . kl_data_in_2 }
#[doc = "0x100c - Key data input word 3"]
#[inline (always)] pub const fn kl_data_in_3 (& self) -> & KlDataIn3 { & self . kl_data_in_3 }
#[doc = "0x1010 - Key address register"]
#[inline (always)] pub const fn kl_key_addr (& self) -> & KlKeyAddr { & self . kl_key_addr }
#[doc = "0x1014 - Key configuration register"]
#[inline (always)] pub const fn kl_key_cfg (& self) -> & KlKeyCfg { & self . kl_key_cfg }
#[doc = "0x1018 - Key security configuration"]
#[inline (always)] pub const fn kl_key_sec_cfg (& self) -> & KlKeySecCfg { & self . kl_key_sec_cfg }
#[doc = "0x1030 - KLAD state register"]
#[inline (always)] pub const fn kl_state (& self) -> & KlState { & self . kl_state }
#[doc = "0x1038 - KLAD error register"]
#[inline (always)] pub const fn kl_error (& self) -> & KlError { & self . kl_error }
#[doc = "0x1040 - KLAD interrupt enable"]
#[inline (always)] pub const fn kl_int_en (& self) -> & KlIntEn { & self . kl_int_en }
#[doc = "0x1048 - KLAD interrupt status"]
#[inline (always)] pub const fn kl_int (& self) -> & KlInt { & self . kl_int }
#[doc = "0x1074 - KLAD lock control"]
#[inline (always)] pub const fn kl_lock_ctrl (& self) -> & KlLockCtrl { & self . kl_lock_ctrl }
#[doc = "0x1084 - KLAD common control"]
#[inline (always)] pub const fn kl_com_ctrl (& self) -> & KlComCtrl { & self . kl_com_ctrl }
#[doc = "0x1088 - KLAD common status"]
#[inline (always)] pub const fn kl_com_status (& self) -> & KlComStatus { & self . kl_com_status }
#[doc = "0x1600 - KLAD alarm info register"]
#[inline (always)] pub const fn kl_alarm_info (& self) -> & KlAlarmInfo { & self . kl_alarm_info }
#[doc = "0x1b00 - TEE CPU keyslot lock command"]
#[inline (always)] pub const fn kc_teecpu_lock_cmd (& self) -> & KcTeecpuLockCmd { & self . kc_teecpu_lock_cmd }
#[doc = "0x1b34 - Keyslot lock status readback"]
#[inline (always)] pub const fn kc_rd_lock_status (& self) -> & KcRdLockStatus { & self . kc_rd_lock_status } }
#[doc = "KL_DATA_IN_0 (rw) register accessor: Key data input word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_data_in_0`] module"]
#[doc (alias = "KL_DATA_IN_0")] pub type KlDataIn0 = crate :: Reg < kl_data_in_0 :: KlDataIn0Spec > ;
#[doc = "Key data input word 0"] pub mod kl_data_in_0 {
#[doc = "Register `KL_DATA_IN_0` reader"] pub type R = crate :: R < KlDataIn0Spec > ;
#[doc = "Register `KL_DATA_IN_0` writer"] pub type W = crate :: W < KlDataIn0Spec > ;
#[doc = "Field `data` reader - Key data\\[31:0\\]"] pub type DataR = crate :: FieldReader < u32 > ;
#[doc = "Field `data` writer - Key data\\[31:0\\]"] pub type DataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Key data\\[31:0\\]"]
#[inline (always)] pub fn data (& self) -> DataR { DataR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Key data\\[31:0\\]"]
#[inline (always)] pub fn data (& mut self) -> DataW < '_ , KlDataIn0Spec > { DataW :: new (self , 0) } }
#[doc = "Key data input word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlDataIn0Spec ; impl crate :: RegisterSpec for KlDataIn0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_data_in_0::R`](R) reader structure"] impl crate :: Readable for KlDataIn0Spec { }
#[doc = "`write(|w| ..)` method takes [`kl_data_in_0::W`](W) writer structure"] impl crate :: Writable for KlDataIn0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_DATA_IN_0 to value 0"] impl crate :: Resettable for KlDataIn0Spec { } }
#[doc = "KL_DATA_IN_1 (rw) register accessor: Key data input word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_data_in_1`] module"]
#[doc (alias = "KL_DATA_IN_1")] pub type KlDataIn1 = crate :: Reg < kl_data_in_1 :: KlDataIn1Spec > ;
#[doc = "Key data input word 1"] pub mod kl_data_in_1 {
#[doc = "Register `KL_DATA_IN_1` reader"] pub type R = crate :: R < KlDataIn1Spec > ;
#[doc = "Register `KL_DATA_IN_1` writer"] pub type W = crate :: W < KlDataIn1Spec > ;
#[doc = "Field `data` reader - Key data\\[63:32\\]"] pub type DataR = crate :: FieldReader < u32 > ;
#[doc = "Field `data` writer - Key data\\[63:32\\]"] pub type DataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Key data\\[63:32\\]"]
#[inline (always)] pub fn data (& self) -> DataR { DataR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Key data\\[63:32\\]"]
#[inline (always)] pub fn data (& mut self) -> DataW < '_ , KlDataIn1Spec > { DataW :: new (self , 0) } }
#[doc = "Key data input word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlDataIn1Spec ; impl crate :: RegisterSpec for KlDataIn1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_data_in_1::R`](R) reader structure"] impl crate :: Readable for KlDataIn1Spec { }
#[doc = "`write(|w| ..)` method takes [`kl_data_in_1::W`](W) writer structure"] impl crate :: Writable for KlDataIn1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_DATA_IN_1 to value 0"] impl crate :: Resettable for KlDataIn1Spec { } }
#[doc = "KL_DATA_IN_2 (rw) register accessor: Key data input word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_data_in_2`] module"]
#[doc (alias = "KL_DATA_IN_2")] pub type KlDataIn2 = crate :: Reg < kl_data_in_2 :: KlDataIn2Spec > ;
#[doc = "Key data input word 2"] pub mod kl_data_in_2 {
#[doc = "Register `KL_DATA_IN_2` reader"] pub type R = crate :: R < KlDataIn2Spec > ;
#[doc = "Register `KL_DATA_IN_2` writer"] pub type W = crate :: W < KlDataIn2Spec > ;
#[doc = "Field `data` reader - Key data\\[95:64\\]"] pub type DataR = crate :: FieldReader < u32 > ;
#[doc = "Field `data` writer - Key data\\[95:64\\]"] pub type DataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Key data\\[95:64\\]"]
#[inline (always)] pub fn data (& self) -> DataR { DataR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Key data\\[95:64\\]"]
#[inline (always)] pub fn data (& mut self) -> DataW < '_ , KlDataIn2Spec > { DataW :: new (self , 0) } }
#[doc = "Key data input word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlDataIn2Spec ; impl crate :: RegisterSpec for KlDataIn2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_data_in_2::R`](R) reader structure"] impl crate :: Readable for KlDataIn2Spec { }
#[doc = "`write(|w| ..)` method takes [`kl_data_in_2::W`](W) writer structure"] impl crate :: Writable for KlDataIn2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_DATA_IN_2 to value 0"] impl crate :: Resettable for KlDataIn2Spec { } }
#[doc = "KL_DATA_IN_3 (rw) register accessor: Key data input word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_data_in_3`] module"]
#[doc (alias = "KL_DATA_IN_3")] pub type KlDataIn3 = crate :: Reg < kl_data_in_3 :: KlDataIn3Spec > ;
#[doc = "Key data input word 3"] pub mod kl_data_in_3 {
#[doc = "Register `KL_DATA_IN_3` reader"] pub type R = crate :: R < KlDataIn3Spec > ;
#[doc = "Register `KL_DATA_IN_3` writer"] pub type W = crate :: W < KlDataIn3Spec > ;
#[doc = "Field `data` reader - Key data\\[127:96\\]"] pub type DataR = crate :: FieldReader < u32 > ;
#[doc = "Field `data` writer - Key data\\[127:96\\]"] pub type DataW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Key data\\[127:96\\]"]
#[inline (always)] pub fn data (& self) -> DataR { DataR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Key data\\[127:96\\]"]
#[inline (always)] pub fn data (& mut self) -> DataW < '_ , KlDataIn3Spec > { DataW :: new (self , 0) } }
#[doc = "Key data input word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_data_in_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_data_in_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlDataIn3Spec ; impl crate :: RegisterSpec for KlDataIn3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_data_in_3::R`](R) reader structure"] impl crate :: Readable for KlDataIn3Spec { }
#[doc = "`write(|w| ..)` method takes [`kl_data_in_3::W`](W) writer structure"] impl crate :: Writable for KlDataIn3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_DATA_IN_3 to value 0"] impl crate :: Resettable for KlDataIn3Spec { } }
#[doc = "KL_KEY_ADDR (rw) register accessor: Key address register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_key_addr`] module"]
#[doc (alias = "KL_KEY_ADDR")] pub type KlKeyAddr = crate :: Reg < kl_key_addr :: KlKeyAddrSpec > ;
#[doc = "Key address register"] pub mod kl_key_addr {
#[doc = "Register `KL_KEY_ADDR` reader"] pub type R = crate :: R < KlKeyAddrSpec > ;
#[doc = "Register `KL_KEY_ADDR` writer"] pub type W = crate :: W < KlKeyAddrSpec > ;
#[doc = "Field `key_addr` reader - Target key slot address"] pub type KeyAddrR = crate :: FieldReader < u16 > ;
#[doc = "Field `key_addr` writer - Target key slot address"] pub type KeyAddrW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; impl R {
#[doc = "Bits 0:9 - Target key slot address"]
#[inline (always)] pub fn key_addr (& self) -> KeyAddrR { KeyAddrR :: new ((self . bits & 0x03ff) as u16) } } impl W {
#[doc = "Bits 0:9 - Target key slot address"]
#[inline (always)] pub fn key_addr (& mut self) -> KeyAddrW < '_ , KlKeyAddrSpec > { KeyAddrW :: new (self , 0) } }
#[doc = "Key address register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlKeyAddrSpec ; impl crate :: RegisterSpec for KlKeyAddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_key_addr::R`](R) reader structure"] impl crate :: Readable for KlKeyAddrSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_key_addr::W`](W) writer structure"] impl crate :: Writable for KlKeyAddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_KEY_ADDR to value 0"] impl crate :: Resettable for KlKeyAddrSpec { } }
#[doc = "KL_KEY_CFG (rw) register accessor: Key configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_key_cfg`] module"]
#[doc (alias = "KL_KEY_CFG")] pub type KlKeyCfg = crate :: Reg < kl_key_cfg :: KlKeyCfgSpec > ;
#[doc = "Key configuration register"] pub mod kl_key_cfg {
#[doc = "Register `KL_KEY_CFG` reader"] pub type R = crate :: R < KlKeyCfgSpec > ;
#[doc = "Register `KL_KEY_CFG` writer"] pub type W = crate :: W < KlKeyCfgSpec > ;
#[doc = "Field `port_sel` reader - Port select"] pub type PortSelR = crate :: FieldReader ;
#[doc = "Field `port_sel` writer - Port select"] pub type PortSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `dsc_code` reader - Descriptor code"] pub type DscCodeR = crate :: FieldReader ;
#[doc = "Field `dsc_code` writer - Descriptor code"] pub type DscCodeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ;
#[doc = "Field `key_enc` reader - Key encrypt enable"] pub type KeyEncR = crate :: BitReader ;
#[doc = "Field `key_enc` writer - Key encrypt enable"] pub type KeyEncW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `key_dec` reader - Key decrypt enable"] pub type KeyDecR = crate :: BitReader ;
#[doc = "Field `key_dec` writer - Key decrypt enable"] pub type KeyDecW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `kl_flash_sel` reader - Flash key source select"] pub type KlFlashSelR = crate :: FieldReader ;
#[doc = "Field `kl_flash_sel` writer - Flash key source select"] pub type KlFlashSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R {
#[doc = "Bits 0:2 - Port select"]
#[inline (always)] pub fn port_sel (& self) -> PortSelR { PortSelR :: new ((self . bits & 7) as u8) }
#[doc = "Bits 4:11 - Descriptor code"]
#[inline (always)] pub fn dsc_code (& self) -> DscCodeR { DscCodeR :: new (((self . bits >> 4) & 0xff) as u8) }
#[doc = "Bit 16 - Key encrypt enable"]
#[inline (always)] pub fn key_enc (& self) -> KeyEncR { KeyEncR :: new (((self . bits >> 16) & 1) != 0) }
#[doc = "Bit 17 - Key decrypt enable"]
#[inline (always)] pub fn key_dec (& self) -> KeyDecR { KeyDecR :: new (((self . bits >> 17) & 1) != 0) }
#[doc = "Bits 18:19 - Flash key source select"]
#[inline (always)] pub fn kl_flash_sel (& self) -> KlFlashSelR { KlFlashSelR :: new (((self . bits >> 18) & 3) as u8) } } impl W {
#[doc = "Bits 0:2 - Port select"]
#[inline (always)] pub fn port_sel (& mut self) -> PortSelW < '_ , KlKeyCfgSpec > { PortSelW :: new (self , 0) }
#[doc = "Bits 4:11 - Descriptor code"]
#[inline (always)] pub fn dsc_code (& mut self) -> DscCodeW < '_ , KlKeyCfgSpec > { DscCodeW :: new (self , 4) }
#[doc = "Bit 16 - Key encrypt enable"]
#[inline (always)] pub fn key_enc (& mut self) -> KeyEncW < '_ , KlKeyCfgSpec > { KeyEncW :: new (self , 16) }
#[doc = "Bit 17 - Key decrypt enable"]
#[inline (always)] pub fn key_dec (& mut self) -> KeyDecW < '_ , KlKeyCfgSpec > { KeyDecW :: new (self , 17) }
#[doc = "Bits 18:19 - Flash key source select"]
#[inline (always)] pub fn kl_flash_sel (& mut self) -> KlFlashSelW < '_ , KlKeyCfgSpec > { KlFlashSelW :: new (self , 18) } }
#[doc = "Key configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlKeyCfgSpec ; impl crate :: RegisterSpec for KlKeyCfgSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_key_cfg::R`](R) reader structure"] impl crate :: Readable for KlKeyCfgSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_key_cfg::W`](W) writer structure"] impl crate :: Writable for KlKeyCfgSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_KEY_CFG to value 0"] impl crate :: Resettable for KlKeyCfgSpec { } }
#[doc = "KL_KEY_SEC_CFG (rw) register accessor: Key security configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_sec_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_sec_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_key_sec_cfg`] module"]
#[doc (alias = "KL_KEY_SEC_CFG")] pub type KlKeySecCfg = crate :: Reg < kl_key_sec_cfg :: KlKeySecCfgSpec > ;
#[doc = "Key security configuration"] pub mod kl_key_sec_cfg {
#[doc = "Register `KL_KEY_SEC_CFG` reader"] pub type R = crate :: R < KlKeySecCfgSpec > ;
#[doc = "Register `KL_KEY_SEC_CFG` writer"] pub type W = crate :: W < KlKeySecCfgSpec > ;
#[doc = "Field `key_sec` reader - Key security: 0=NS; 1=Secure"] pub type KeySecR = crate :: BitReader ;
#[doc = "Field `key_sec` writer - Key security: 0=NS; 1=Secure"] pub type KeySecW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `src_nsec` reader - Source non-secure: 0=secure; 1=NS"] pub type SrcNsecR = crate :: BitReader ;
#[doc = "Field `src_nsec` writer - Source non-secure: 0=secure; 1=NS"] pub type SrcNsecW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `src_sec` reader - Source secure: 0=NS; 1=Secure"] pub type SrcSecR = crate :: BitReader ;
#[doc = "Field `src_sec` writer - Source secure: 0=NS; 1=Secure"] pub type SrcSecW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dest_nsec` reader - Destination non-secure"] pub type DestNsecR = crate :: BitReader ;
#[doc = "Field `dest_nsec` writer - Destination non-secure"] pub type DestNsecW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `dest_sec` reader - Destination secure"] pub type DestSecR = crate :: BitReader ;
#[doc = "Field `dest_sec` writer - Destination secure"] pub type DestSecW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `master_only` reader - Master-only access"] pub type MasterOnlyR = crate :: BitReader ;
#[doc = "Field `master_only` writer - Master-only access"] pub type MasterOnlyW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - Key security: 0=NS; 1=Secure"]
#[inline (always)] pub fn key_sec (& self) -> KeySecR { KeySecR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Source non-secure: 0=secure; 1=NS"]
#[inline (always)] pub fn src_nsec (& self) -> SrcNsecR { SrcNsecR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - Source secure: 0=NS; 1=Secure"]
#[inline (always)] pub fn src_sec (& self) -> SrcSecR { SrcSecR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - Destination non-secure"]
#[inline (always)] pub fn dest_nsec (& self) -> DestNsecR { DestNsecR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - Destination secure"]
#[inline (always)] pub fn dest_sec (& self) -> DestSecR { DestSecR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - Master-only access"]
#[inline (always)] pub fn master_only (& self) -> MasterOnlyR { MasterOnlyR :: new (((self . bits >> 5) & 1) != 0) } } impl W {
#[doc = "Bit 0 - Key security: 0=NS; 1=Secure"]
#[inline (always)] pub fn key_sec (& mut self) -> KeySecW < '_ , KlKeySecCfgSpec > { KeySecW :: new (self , 0) }
#[doc = "Bit 1 - Source non-secure: 0=secure; 1=NS"]
#[inline (always)] pub fn src_nsec (& mut self) -> SrcNsecW < '_ , KlKeySecCfgSpec > { SrcNsecW :: new (self , 1) }
#[doc = "Bit 2 - Source secure: 0=NS; 1=Secure"]
#[inline (always)] pub fn src_sec (& mut self) -> SrcSecW < '_ , KlKeySecCfgSpec > { SrcSecW :: new (self , 2) }
#[doc = "Bit 3 - Destination non-secure"]
#[inline (always)] pub fn dest_nsec (& mut self) -> DestNsecW < '_ , KlKeySecCfgSpec > { DestNsecW :: new (self , 3) }
#[doc = "Bit 4 - Destination secure"]
#[inline (always)] pub fn dest_sec (& mut self) -> DestSecW < '_ , KlKeySecCfgSpec > { DestSecW :: new (self , 4) }
#[doc = "Bit 5 - Master-only access"]
#[inline (always)] pub fn master_only (& mut self) -> MasterOnlyW < '_ , KlKeySecCfgSpec > { MasterOnlyW :: new (self , 5) } }
#[doc = "Key security configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_key_sec_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_key_sec_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlKeySecCfgSpec ; impl crate :: RegisterSpec for KlKeySecCfgSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_key_sec_cfg::R`](R) reader structure"] impl crate :: Readable for KlKeySecCfgSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_key_sec_cfg::W`](W) writer structure"] impl crate :: Writable for KlKeySecCfgSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_KEY_SEC_CFG to value 0"] impl crate :: Resettable for KlKeySecCfgSpec { } }
#[doc = "KL_STATE (rw) register accessor: KLAD state register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_state::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_state::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_state`] module"]
#[doc (alias = "KL_STATE")] pub type KlState = crate :: Reg < kl_state :: KlStateSpec > ;
#[doc = "KLAD state register"] pub mod kl_state {
#[doc = "Register `KL_STATE` reader"] pub type R = crate :: R < KlStateSpec > ;
#[doc = "Register `KL_STATE` writer"] pub type W = crate :: W < KlStateSpec > ;
#[doc = "Field `state` reader - KLAD processing state"] pub type StateR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - KLAD processing state"]
#[inline (always)] pub fn state (& self) -> StateR { StateR :: new (self . bits) } } impl W { }
#[doc = "KLAD state register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlStateSpec ; impl crate :: RegisterSpec for KlStateSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_state::R`](R) reader structure"] impl crate :: Readable for KlStateSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_state::W`](W) writer structure"] impl crate :: Writable for KlStateSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_STATE to value 0"] impl crate :: Resettable for KlStateSpec { } }
#[doc = "KL_ERROR (rw) register accessor: KLAD error register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_error::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_error::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_error`] module"]
#[doc (alias = "KL_ERROR")] pub type KlError = crate :: Reg < kl_error :: KlErrorSpec > ;
#[doc = "KLAD error register"] pub mod kl_error {
#[doc = "Register `KL_ERROR` reader"] pub type R = crate :: R < KlErrorSpec > ;
#[doc = "Register `KL_ERROR` writer"] pub type W = crate :: W < KlErrorSpec > ;
#[doc = "Field `error` reader - KLAD error code"] pub type ErrorR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - KLAD error code"]
#[inline (always)] pub fn error (& self) -> ErrorR { ErrorR :: new (self . bits) } } impl W { }
#[doc = "KLAD error register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_error::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_error::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlErrorSpec ; impl crate :: RegisterSpec for KlErrorSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_error::R`](R) reader structure"] impl crate :: Readable for KlErrorSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_error::W`](W) writer structure"] impl crate :: Writable for KlErrorSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_ERROR to value 0"] impl crate :: Resettable for KlErrorSpec { } }
#[doc = "KL_INT_EN (rw) register accessor: KLAD interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_int_en`] module"]
#[doc (alias = "KL_INT_EN")] pub type KlIntEn = crate :: Reg < kl_int_en :: KlIntEnSpec > ;
#[doc = "KLAD interrupt enable"] pub mod kl_int_en {
#[doc = "Register `KL_INT_EN` reader"] pub type R = crate :: R < KlIntEnSpec > ;
#[doc = "Register `KL_INT_EN` writer"] pub type W = crate :: W < KlIntEnSpec > ;
#[doc = "Field `kl_int_en` reader - KLAD interrupt enable"] pub type KlIntEnR = crate :: BitReader ;
#[doc = "Field `kl_int_en` writer - KLAD interrupt enable"] pub type KlIntEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - KLAD interrupt enable"]
#[inline (always)] pub fn kl_int_en (& self) -> KlIntEnR { KlIntEnR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - KLAD interrupt enable"]
#[inline (always)] pub fn kl_int_en (& mut self) -> KlIntEnW < '_ , KlIntEnSpec > { KlIntEnW :: new (self , 0) } }
#[doc = "KLAD interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlIntEnSpec ; impl crate :: RegisterSpec for KlIntEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_int_en::R`](R) reader structure"] impl crate :: Readable for KlIntEnSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_int_en::W`](W) writer structure"] impl crate :: Writable for KlIntEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_INT_EN to value 0"] impl crate :: Resettable for KlIntEnSpec { } }
#[doc = "KL_INT (rw) register accessor: KLAD interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_int`] module"]
#[doc (alias = "KL_INT")] pub type KlInt = crate :: Reg < kl_int :: KlIntSpec > ;
#[doc = "KLAD interrupt status"] pub mod kl_int {
#[doc = "Register `KL_INT` reader"] pub type R = crate :: R < KlIntSpec > ;
#[doc = "Register `KL_INT` writer"] pub type W = crate :: W < KlIntSpec > ;
#[doc = "Field `kl_int` reader - KLAD interrupt flag"] pub type KlIntR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - KLAD interrupt flag"]
#[inline (always)] pub fn kl_int (& self) -> KlIntR { KlIntR :: new ((self . bits & 1) != 0) } } impl W { }
#[doc = "KLAD interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlIntSpec ; impl crate :: RegisterSpec for KlIntSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_int::R`](R) reader structure"] impl crate :: Readable for KlIntSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_int::W`](W) writer structure"] impl crate :: Writable for KlIntSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_INT to value 0"] impl crate :: Resettable for KlIntSpec { } }
#[doc = "KL_COM_CTRL (rw) register accessor: KLAD common control\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_com_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_com_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_com_ctrl`] module"]
#[doc (alias = "KL_COM_CTRL")] pub type KlComCtrl = crate :: Reg < kl_com_ctrl :: KlComCtrlSpec > ;
#[doc = "KLAD common control"] pub mod kl_com_ctrl {
#[doc = "Register `KL_COM_CTRL` reader"] pub type R = crate :: R < KlComCtrlSpec > ;
#[doc = "Register `KL_COM_CTRL` writer"] pub type W = crate :: W < KlComCtrlSpec > ;
#[doc = "Field `kl_com_start` writer - Common KDF start"] pub type KlComStartW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `kl_com_level_sel` reader - Level select"] pub type KlComLevelSelR = crate :: FieldReader ;
#[doc = "Field `kl_com_level_sel` writer - Level select"] pub type KlComLevelSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `kl_com_alg_sel` reader - Algorithm select"] pub type KlComAlgSelR = crate :: FieldReader ;
#[doc = "Field `kl_com_alg_sel` writer - Algorithm select"] pub type KlComAlgSelW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ;
#[doc = "Field `kl_com_key_size` reader - Key size select"] pub type KlComKeySizeR = crate :: FieldReader ;
#[doc = "Field `kl_com_key_size` writer - Key size select"] pub type KlComKeySizeW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ;
#[doc = "Field `rk_choose` reader - Root key select: 4=USD; 5=SBRK; 6=ABRK; 13=DRK; 18=PSK"] pub type RkChooseR = crate :: FieldReader ;
#[doc = "Field `rk_choose` writer - Root key select: 4=USD; 5=SBRK; 6=ABRK; 13=DRK; 18=PSK"] pub type RkChooseW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R {
#[doc = "Bits 1:3 - Level select"]
#[inline (always)] pub fn kl_com_level_sel (& self) -> KlComLevelSelR { KlComLevelSelR :: new (((self . bits >> 1) & 7) as u8) }
#[doc = "Bits 4:5 - Algorithm select"]
#[inline (always)] pub fn kl_com_alg_sel (& self) -> KlComAlgSelR { KlComAlgSelR :: new (((self . bits >> 4) & 3) as u8) }
#[doc = "Bits 6:7 - Key size select"]
#[inline (always)] pub fn kl_com_key_size (& self) -> KlComKeySizeR { KlComKeySizeR :: new (((self . bits >> 6) & 3) as u8) }
#[doc = "Bits 8:12 - Root key select: 4=USD; 5=SBRK; 6=ABRK; 13=DRK; 18=PSK"]
#[inline (always)] pub fn rk_choose (& self) -> RkChooseR { RkChooseR :: new (((self . bits >> 8) & 0x1f) as u8) } } impl W {
#[doc = "Bit 0 - Common KDF start"]
#[inline (always)] pub fn kl_com_start (& mut self) -> KlComStartW < '_ , KlComCtrlSpec > { KlComStartW :: new (self , 0) }
#[doc = "Bits 1:3 - Level select"]
#[inline (always)] pub fn kl_com_level_sel (& mut self) -> KlComLevelSelW < '_ , KlComCtrlSpec > { KlComLevelSelW :: new (self , 1) }
#[doc = "Bits 4:5 - Algorithm select"]
#[inline (always)] pub fn kl_com_alg_sel (& mut self) -> KlComAlgSelW < '_ , KlComCtrlSpec > { KlComAlgSelW :: new (self , 4) }
#[doc = "Bits 6:7 - Key size select"]
#[inline (always)] pub fn kl_com_key_size (& mut self) -> KlComKeySizeW < '_ , KlComCtrlSpec > { KlComKeySizeW :: new (self , 6) }
#[doc = "Bits 8:12 - Root key select: 4=USD; 5=SBRK; 6=ABRK; 13=DRK; 18=PSK"]
#[inline (always)] pub fn rk_choose (& mut self) -> RkChooseW < '_ , KlComCtrlSpec > { RkChooseW :: new (self , 8) } }
#[doc = "KLAD common control\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_com_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_com_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlComCtrlSpec ; impl crate :: RegisterSpec for KlComCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_com_ctrl::R`](R) reader structure"] impl crate :: Readable for KlComCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_com_ctrl::W`](W) writer structure"] impl crate :: Writable for KlComCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_COM_CTRL to value 0"] impl crate :: Resettable for KlComCtrlSpec { } }
#[doc = "KL_COM_STATUS (rw) register accessor: KLAD common status\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_com_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_com_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_com_status`] module"]
#[doc (alias = "KL_COM_STATUS")] pub type KlComStatus = crate :: Reg < kl_com_status :: KlComStatusSpec > ;
#[doc = "KLAD common status"] pub mod kl_com_status {
#[doc = "Register `KL_COM_STATUS` reader"] pub type R = crate :: R < KlComStatusSpec > ;
#[doc = "Register `KL_COM_STATUS` writer"] pub type W = crate :: W < KlComStatusSpec > ;
#[doc = "Field `kl_com_rk_rdy` reader - Root key ready"] pub type KlComRkRdyR = crate :: BitReader ;
#[doc = "Field `kl_com_lv1_rdy` reader - Level 1 key ready"] pub type KlComLv1RdyR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Root key ready"]
#[inline (always)] pub fn kl_com_rk_rdy (& self) -> KlComRkRdyR { KlComRkRdyR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Level 1 key ready"]
#[inline (always)] pub fn kl_com_lv1_rdy (& self) -> KlComLv1RdyR { KlComLv1RdyR :: new (((self . bits >> 1) & 1) != 0) } } impl W { }
#[doc = "KLAD common status\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_com_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_com_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlComStatusSpec ; impl crate :: RegisterSpec for KlComStatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_com_status::R`](R) reader structure"] impl crate :: Readable for KlComStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_com_status::W`](W) writer structure"] impl crate :: Writable for KlComStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_COM_STATUS to value 0"] impl crate :: Resettable for KlComStatusSpec { } }
#[doc = "KL_LOCK_CTRL (rw) register accessor: KLAD lock control\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_lock_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_lock_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_lock_ctrl`] module"]
#[doc (alias = "KL_LOCK_CTRL")] pub type KlLockCtrl = crate :: Reg < kl_lock_ctrl :: KlLockCtrlSpec > ;
#[doc = "KLAD lock control"] pub mod kl_lock_ctrl {
#[doc = "Register `KL_LOCK_CTRL` reader"] pub type R = crate :: R < KlLockCtrlSpec > ;
#[doc = "Register `KL_LOCK_CTRL` writer"] pub type W = crate :: W < KlLockCtrlSpec > ;
#[doc = "Field `kl_lock` writer - Lock request"] pub type KlLockW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `kl_lock_num` reader - Lock sequence number"] pub type KlLockNumR = crate :: FieldReader ;
#[doc = "Field `kl_lock_num` writer - Lock sequence number"] pub type KlLockNumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 4:6 - Lock sequence number"]
#[inline (always)] pub fn kl_lock_num (& self) -> KlLockNumR { KlLockNumR :: new (((self . bits >> 4) & 7) as u8) } } impl W {
#[doc = "Bit 0 - Lock request"]
#[inline (always)] pub fn kl_lock (& mut self) -> KlLockW < '_ , KlLockCtrlSpec > { KlLockW :: new (self , 0) }
#[doc = "Bits 4:6 - Lock sequence number"]
#[inline (always)] pub fn kl_lock_num (& mut self) -> KlLockNumW < '_ , KlLockCtrlSpec > { KlLockNumW :: new (self , 4) } }
#[doc = "KLAD lock control\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_lock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_lock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlLockCtrlSpec ; impl crate :: RegisterSpec for KlLockCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_lock_ctrl::R`](R) reader structure"] impl crate :: Readable for KlLockCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_lock_ctrl::W`](W) writer structure"] impl crate :: Writable for KlLockCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_LOCK_CTRL to value 0"] impl crate :: Resettable for KlLockCtrlSpec { } }
#[doc = "KL_ALARM_INFO (rw) register accessor: KLAD alarm info register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_alarm_info::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_alarm_info::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kl_alarm_info`] module"]
#[doc (alias = "KL_ALARM_INFO")] pub type KlAlarmInfo = crate :: Reg < kl_alarm_info :: KlAlarmInfoSpec > ;
#[doc = "KLAD alarm info register"] pub mod kl_alarm_info {
#[doc = "Register `KL_ALARM_INFO` reader"] pub type R = crate :: R < KlAlarmInfoSpec > ;
#[doc = "Register `KL_ALARM_INFO` writer"] pub type W = crate :: W < KlAlarmInfoSpec > ;
#[doc = "Field `kl_cfg_sig_alarm` reader - Config signature alarm"] pub type KlCfgSigAlarmR = crate :: BitReader ;
#[doc = "Field `kl_com_crc16_alarm` reader - Common CRC16 alarm"] pub type KlComCrc16AlarmR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Config signature alarm"]
#[inline (always)] pub fn kl_cfg_sig_alarm (& self) -> KlCfgSigAlarmR { KlCfgSigAlarmR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - Common CRC16 alarm"]
#[inline (always)] pub fn kl_com_crc16_alarm (& self) -> KlComCrc16AlarmR { KlComCrc16AlarmR :: new (((self . bits >> 1) & 1) != 0) } } impl W { }
#[doc = "KLAD alarm info register\n\nYou can [`read`](crate::Reg::read) this register and get [`kl_alarm_info::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kl_alarm_info::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KlAlarmInfoSpec ; impl crate :: RegisterSpec for KlAlarmInfoSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kl_alarm_info::R`](R) reader structure"] impl crate :: Readable for KlAlarmInfoSpec { }
#[doc = "`write(|w| ..)` method takes [`kl_alarm_info::W`](W) writer structure"] impl crate :: Writable for KlAlarmInfoSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KL_ALARM_INFO to value 0"] impl crate :: Resettable for KlAlarmInfoSpec { } }
#[doc = "KC_TEECPU_LOCK_CMD (rw) register accessor: TEE CPU keyslot lock command\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_teecpu_lock_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_teecpu_lock_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kc_teecpu_lock_cmd`] module"]
#[doc (alias = "KC_TEECPU_LOCK_CMD")] pub type KcTeecpuLockCmd = crate :: Reg < kc_teecpu_lock_cmd :: KcTeecpuLockCmdSpec > ;
#[doc = "TEE CPU keyslot lock command"] pub mod kc_teecpu_lock_cmd {
#[doc = "Register `KC_TEECPU_LOCK_CMD` reader"] pub type R = crate :: R < KcTeecpuLockCmdSpec > ;
#[doc = "Register `KC_TEECPU_LOCK_CMD` writer"] pub type W = crate :: W < KcTeecpuLockCmdSpec > ;
#[doc = "Field `key_slot_num` reader - Key slot number"] pub type KeySlotNumR = crate :: FieldReader < u16 > ;
#[doc = "Field `key_slot_num` writer - Key slot number"] pub type KeySlotNumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ;
#[doc = "Field `lock_cmd` writer - Lock command: 0x01=REE; 0x10=TEE; 0x100=PCPU; 0x110=AIDSP"] pub type LockCmdW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 0:9 - Key slot number"]
#[inline (always)] pub fn key_slot_num (& self) -> KeySlotNumR { KeySlotNumR :: new ((self . bits & 0x03ff) as u16) } } impl W {
#[doc = "Bits 0:9 - Key slot number"]
#[inline (always)] pub fn key_slot_num (& mut self) -> KeySlotNumW < '_ , KcTeecpuLockCmdSpec > { KeySlotNumW :: new (self , 0) }
#[doc = "Bit 20 - Lock command: 0x01=REE; 0x10=TEE; 0x100=PCPU; 0x110=AIDSP"]
#[inline (always)] pub fn lock_cmd (& mut self) -> LockCmdW < '_ , KcTeecpuLockCmdSpec > { LockCmdW :: new (self , 20) } }
#[doc = "TEE CPU keyslot lock command\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_teecpu_lock_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_teecpu_lock_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KcTeecpuLockCmdSpec ; impl crate :: RegisterSpec for KcTeecpuLockCmdSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kc_teecpu_lock_cmd::R`](R) reader structure"] impl crate :: Readable for KcTeecpuLockCmdSpec { }
#[doc = "`write(|w| ..)` method takes [`kc_teecpu_lock_cmd::W`](W) writer structure"] impl crate :: Writable for KcTeecpuLockCmdSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KC_TEECPU_LOCK_CMD to value 0"] impl crate :: Resettable for KcTeecpuLockCmdSpec { } }
#[doc = "KC_RD_LOCK_STATUS (rw) register accessor: Keyslot lock status readback\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_rd_lock_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_rd_lock_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@kc_rd_lock_status`] module"]
#[doc (alias = "KC_RD_LOCK_STATUS")] pub type KcRdLockStatus = crate :: Reg < kc_rd_lock_status :: KcRdLockStatusSpec > ;
#[doc = "Keyslot lock status readback"] pub mod kc_rd_lock_status {
#[doc = "Register `KC_RD_LOCK_STATUS` reader"] pub type R = crate :: R < KcRdLockStatusSpec > ;
#[doc = "Register `KC_RD_LOCK_STATUS` writer"] pub type W = crate :: W < KcRdLockStatusSpec > ;
#[doc = "Field `rd_lock_status` reader - Lock status: 0=unlock; 1=REE; 2=TEE; 4=PCPU; 6=AIDSP"] pub type RdLockStatusR = crate :: FieldReader ; impl R {
#[doc = "Bits 0:2 - Lock status: 0=unlock; 1=REE; 2=TEE; 4=PCPU; 6=AIDSP"]
#[inline (always)] pub fn rd_lock_status (& self) -> RdLockStatusR { RdLockStatusR :: new ((self . bits & 7) as u8) } } impl W { }
#[doc = "Keyslot lock status readback\n\nYou can [`read`](crate::Reg::read) this register and get [`kc_rd_lock_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`kc_rd_lock_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KcRdLockStatusSpec ; impl crate :: RegisterSpec for KcRdLockStatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`kc_rd_lock_status::R`](R) reader structure"] impl crate :: Readable for KcRdLockStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`kc_rd_lock_status::W`](W) writer structure"] impl crate :: Writable for KcRdLockStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets KC_RD_LOCK_STATUS to value 0"] impl crate :: Resettable for KcRdLockStatusSpec { } } }
#[doc = "True Random Number Generator"] pub type Trng = crate :: Periph < trng :: RegisterBlock , 0x4411_4000 > ; impl core :: fmt :: Debug for Trng { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Trng") . finish () } }
#[doc = "True Random Number Generator"] pub mod trng {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x0100] , trng_fifo_data : TrngFifoData , trng_fifo_ready : TrngFifoReady , trng_data_st : TrngDataSt , _reserved3 : [u8 ; 0x68] , trng_fro_sample_clk_sel : TrngFroSampleClkSel , trng_fro_div_cnt : TrngFroDivCnt , } impl RegisterBlock {
#[doc = "0x100 - TRNG FIFO data output register"]
#[inline (always)] pub const fn trng_fifo_data (& self) -> & TrngFifoData { & self . trng_fifo_data }
#[doc = "0x104 - TRNG FIFO ready status"]
#[inline (always)] pub const fn trng_fifo_ready (& self) -> & TrngFifoReady { & self . trng_fifo_ready }
#[doc = "0x108 - TRNG data status register"]
#[inline (always)] pub const fn trng_data_st (& self) -> & TrngDataSt { & self . trng_data_st }
#[doc = "0x174 - TRNG FRO sample clock select"]
#[inline (always)] pub const fn trng_fro_sample_clk_sel (& self) -> & TrngFroSampleClkSel { & self . trng_fro_sample_clk_sel }
#[doc = "0x178 - TRNG FRO divider count"]
#[inline (always)] pub const fn trng_fro_div_cnt (& self) -> & TrngFroDivCnt { & self . trng_fro_div_cnt } }
#[doc = "TRNG_FIFO_DATA (rw) register accessor: TRNG FIFO data output register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fifo_data`] module"]
#[doc (alias = "TRNG_FIFO_DATA")] pub type TrngFifoData = crate :: Reg < trng_fifo_data :: TrngFifoDataSpec > ;
#[doc = "TRNG FIFO data output register"] pub mod trng_fifo_data {
#[doc = "Register `TRNG_FIFO_DATA` reader"] pub type R = crate :: R < TrngFifoDataSpec > ;
#[doc = "Register `TRNG_FIFO_DATA` writer"] pub type W = crate :: W < TrngFifoDataSpec > ;
#[doc = "Field `trng_data` reader - Random data (read to get random number)"] pub type TrngDataR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - Random data (read to get random number)"]
#[inline (always)] pub fn trng_data (& self) -> TrngDataR { TrngDataR :: new (self . bits) } } impl W { }
#[doc = "TRNG FIFO data output register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TrngFifoDataSpec ; impl crate :: RegisterSpec for TrngFifoDataSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`trng_fifo_data::R`](R) reader structure"] impl crate :: Readable for TrngFifoDataSpec { }
#[doc = "`write(|w| ..)` method takes [`trng_fifo_data::W`](W) writer structure"] impl crate :: Writable for TrngFifoDataSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TRNG_FIFO_DATA to value 0"] impl crate :: Resettable for TrngFifoDataSpec { } }
#[doc = "TRNG_FIFO_READY (rw) register accessor: TRNG FIFO ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_ready::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_ready::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fifo_ready`] module"]
#[doc (alias = "TRNG_FIFO_READY")] pub type TrngFifoReady = crate :: Reg < trng_fifo_ready :: TrngFifoReadySpec > ;
#[doc = "TRNG FIFO ready status"] pub mod trng_fifo_ready {
#[doc = "Register `TRNG_FIFO_READY` reader"] pub type R = crate :: R < TrngFifoReadySpec > ;
#[doc = "Register `TRNG_FIFO_READY` writer"] pub type W = crate :: W < TrngFifoReadySpec > ;
#[doc = "Field `trng_data_ready` reader - Data ready: 1=data available in FIFO"] pub type TrngDataReadyR = crate :: BitReader ;
#[doc = "Field `trng_done` reader - TRNG generation done"] pub type TrngDoneR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - Data ready: 1=data available in FIFO"]
#[inline (always)] pub fn trng_data_ready (& self) -> TrngDataReadyR { TrngDataReadyR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TRNG generation done"]
#[inline (always)] pub fn trng_done (& self) -> TrngDoneR { TrngDoneR :: new (((self . bits >> 1) & 1) != 0) } } impl W { }
#[doc = "TRNG FIFO ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_ready::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_ready::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TrngFifoReadySpec ; impl crate :: RegisterSpec for TrngFifoReadySpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`trng_fifo_ready::R`](R) reader structure"] impl crate :: Readable for TrngFifoReadySpec { }
#[doc = "`write(|w| ..)` method takes [`trng_fifo_ready::W`](W) writer structure"] impl crate :: Writable for TrngFifoReadySpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TRNG_FIFO_READY to value 0"] impl crate :: Resettable for TrngFifoReadySpec { } }
#[doc = "TRNG_DATA_ST (rw) register accessor: TRNG data status register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_data_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_data_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_data_st`] module"]
#[doc (alias = "TRNG_DATA_ST")] pub type TrngDataSt = crate :: Reg < trng_data_st :: TrngDataStSpec > ;
#[doc = "TRNG data status register"] pub mod trng_data_st {
#[doc = "Register `TRNG_DATA_ST` reader"] pub type R = crate :: R < TrngDataStSpec > ;
#[doc = "Register `TRNG_DATA_ST` writer"] pub type W = crate :: W < TrngDataStSpec > ;
#[doc = "Field `data_st` reader - Data status"] pub type DataStR = crate :: FieldReader < u32 > ; impl R {
#[doc = "Bits 0:31 - Data status"]
#[inline (always)] pub fn data_st (& self) -> DataStR { DataStR :: new (self . bits) } } impl W { }
#[doc = "TRNG data status register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_data_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_data_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TrngDataStSpec ; impl crate :: RegisterSpec for TrngDataStSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`trng_data_st::R`](R) reader structure"] impl crate :: Readable for TrngDataStSpec { }
#[doc = "`write(|w| ..)` method takes [`trng_data_st::W`](W) writer structure"] impl crate :: Writable for TrngDataStSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TRNG_DATA_ST to value 0"] impl crate :: Resettable for TrngDataStSpec { } }
#[doc = "TRNG_FRO_SAMPLE_CLK_SEL (rw) register accessor: TRNG FRO sample clock select\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_sample_clk_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_sample_clk_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fro_sample_clk_sel`] module"]
#[doc (alias = "TRNG_FRO_SAMPLE_CLK_SEL")] pub type TrngFroSampleClkSel = crate :: Reg < trng_fro_sample_clk_sel :: TrngFroSampleClkSelSpec > ;
#[doc = "TRNG FRO sample clock select"] pub mod trng_fro_sample_clk_sel {
#[doc = "Register `TRNG_FRO_SAMPLE_CLK_SEL` reader"] pub type R = crate :: R < TrngFroSampleClkSelSpec > ;
#[doc = "Register `TRNG_FRO_SAMPLE_CLK_SEL` writer"] pub type W = crate :: W < TrngFroSampleClkSelSpec > ;
#[doc = "Field `fro_sample_clk_sel` reader - FRO sample clock select: 0=inner; 1=external"] pub type FroSampleClkSelR = crate :: BitReader ;
#[doc = "Field `fro_sample_clk_sel` writer - FRO sample clock select: 0=inner; 1=external"] pub type FroSampleClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - FRO sample clock select: 0=inner; 1=external"]
#[inline (always)] pub fn fro_sample_clk_sel (& self) -> FroSampleClkSelR { FroSampleClkSelR :: new ((self . bits & 1) != 0) } } impl W {
#[doc = "Bit 0 - FRO sample clock select: 0=inner; 1=external"]
#[inline (always)] pub fn fro_sample_clk_sel (& mut self) -> FroSampleClkSelW < '_ , TrngFroSampleClkSelSpec > { FroSampleClkSelW :: new (self , 0) } }
#[doc = "TRNG FRO sample clock select\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_sample_clk_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_sample_clk_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TrngFroSampleClkSelSpec ; impl crate :: RegisterSpec for TrngFroSampleClkSelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`trng_fro_sample_clk_sel::R`](R) reader structure"] impl crate :: Readable for TrngFroSampleClkSelSpec { }
#[doc = "`write(|w| ..)` method takes [`trng_fro_sample_clk_sel::W`](W) writer structure"] impl crate :: Writable for TrngFroSampleClkSelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TRNG_FRO_SAMPLE_CLK_SEL to value 0"] impl crate :: Resettable for TrngFroSampleClkSelSpec { } }
#[doc = "TRNG_FRO_DIV_CNT (rw) register accessor: TRNG FRO divider count\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_div_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_div_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fro_div_cnt`] module"]
#[doc (alias = "TRNG_FRO_DIV_CNT")] pub type TrngFroDivCnt = crate :: Reg < trng_fro_div_cnt :: TrngFroDivCntSpec > ;
#[doc = "TRNG FRO divider count"] pub mod trng_fro_div_cnt {
#[doc = "Register `TRNG_FRO_DIV_CNT` reader"] pub type R = crate :: R < TrngFroDivCntSpec > ;
#[doc = "Register `TRNG_FRO_DIV_CNT` writer"] pub type W = crate :: W < TrngFroDivCntSpec > ;
#[doc = "Field `fro_div_cnt` reader - FRO divider count (default 0x1b)"] pub type FroDivCntR = crate :: FieldReader ;
#[doc = "Field `fro_div_cnt` writer - FRO divider count (default 0x1b)"] pub type FroDivCntW < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R {
#[doc = "Bits 0:7 - FRO divider count (default 0x1b)"]
#[inline (always)] pub fn fro_div_cnt (& self) -> FroDivCntR { FroDivCntR :: new ((self . bits & 0xff) as u8) } } impl W {
#[doc = "Bits 0:7 - FRO divider count (default 0x1b)"]
#[inline (always)] pub fn fro_div_cnt (& mut self) -> FroDivCntW < '_ , TrngFroDivCntSpec > { FroDivCntW :: new (self , 0) } }
#[doc = "TRNG FRO divider count\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_div_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_div_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TrngFroDivCntSpec ; impl crate :: RegisterSpec for TrngFroDivCntSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`trng_fro_div_cnt::R`](R) reader structure"] impl crate :: Readable for TrngFroDivCntSpec { }
#[doc = "`write(|w| ..)` method takes [`trng_fro_div_cnt::W`](W) writer structure"] impl crate :: Writable for TrngFroDivCntSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TRNG_FRO_DIV_CNT to value 0"] impl crate :: Resettable for TrngFroDivCntSpec { } } }
#[doc = "TCXO 64-bit free-running counter (v150)"] pub type Tcxo = crate :: Periph < tcxo :: RegisterBlock , 0x4400_04c0 > ; impl core :: fmt :: Debug for Tcxo { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Tcxo") . finish () } }
#[doc = "TCXO 64-bit free-running counter (v150)"] pub mod tcxo {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { tcxo_status : TcxoStatus , tcxo_count0 : TcxoCount0 , tcxo_count1 : TcxoCount1 , tcxo_count2 : TcxoCount2 , tcxo_count3 : TcxoCount3 , } impl RegisterBlock {
#[doc = "0x00 - TCXO status and control register"]
#[inline (always)] pub const fn tcxo_status (& self) -> & TcxoStatus { & self . tcxo_status }
#[doc = "0x04 - TCXO count bits \\[15:0\\]"]
#[inline (always)] pub const fn tcxo_count0 (& self) -> & TcxoCount0 { & self . tcxo_count0 }
#[doc = "0x08 - TCXO count bits \\[31:16\\]"]
#[inline (always)] pub const fn tcxo_count1 (& self) -> & TcxoCount1 { & self . tcxo_count1 }
#[doc = "0x0c - TCXO count bits \\[47:32\\]"]
#[inline (always)] pub const fn tcxo_count2 (& self) -> & TcxoCount2 { & self . tcxo_count2 }
#[doc = "0x10 - TCXO count bits \\[63:48\\]"]
#[inline (always)] pub const fn tcxo_count3 (& self) -> & TcxoCount3 { & self . tcxo_count3 } }
#[doc = "TCXO_STATUS (rw) register accessor: TCXO status and control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_status`] module"]
#[doc (alias = "TCXO_STATUS")] pub type TcxoStatus = crate :: Reg < tcxo_status :: TcxoStatusSpec > ;
#[doc = "TCXO status and control register"] pub mod tcxo_status {
#[doc = "Register `TCXO_STATUS` reader"] pub type R = crate :: R < TcxoStatusSpec > ;
#[doc = "Register `TCXO_STATUS` writer"] pub type W = crate :: W < TcxoStatusSpec > ;
#[doc = "Field `refresh` reader - TCXO count refresh: 1=trigger count latch"] pub type RefreshR = crate :: BitReader ;
#[doc = "Field `refresh` writer - TCXO count refresh: 1=trigger count latch"] pub type RefreshW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `clear` reader - TCXO count clear: 1=clear counter"] pub type ClearR = crate :: BitReader ;
#[doc = "Field `clear` writer - TCXO count clear: 1=clear counter"] pub type ClearW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `enable` reader - TCXO count enable: 1=enable counting"] pub type EnableR = crate :: BitReader ;
#[doc = "Field `enable` writer - TCXO count enable: 1=enable counting"] pub type EnableW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `valid` reader - TCXO count value valid flag"] pub type ValidR = crate :: BitReader ; impl R {
#[doc = "Bit 0 - TCXO count refresh: 1=trigger count latch"]
#[inline (always)] pub fn refresh (& self) -> RefreshR { RefreshR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TCXO count clear: 1=clear counter"]
#[inline (always)] pub fn clear (& self) -> ClearR { ClearR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - TCXO count enable: 1=enable counting"]
#[inline (always)] pub fn enable (& self) -> EnableR { EnableR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 4 - TCXO count value valid flag"]
#[inline (always)] pub fn valid (& self) -> ValidR { ValidR :: new (((self . bits >> 4) & 1) != 0) } } impl W {
#[doc = "Bit 0 - TCXO count refresh: 1=trigger count latch"]
#[inline (always)] pub fn refresh (& mut self) -> RefreshW < '_ , TcxoStatusSpec > { RefreshW :: new (self , 0) }
#[doc = "Bit 1 - TCXO count clear: 1=clear counter"]
#[inline (always)] pub fn clear (& mut self) -> ClearW < '_ , TcxoStatusSpec > { ClearW :: new (self , 1) }
#[doc = "Bit 2 - TCXO count enable: 1=enable counting"]
#[inline (always)] pub fn enable (& mut self) -> EnableW < '_ , TcxoStatusSpec > { EnableW :: new (self , 2) } }
#[doc = "TCXO status and control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TcxoStatusSpec ; impl crate :: RegisterSpec for TcxoStatusSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tcxo_status::R`](R) reader structure"] impl crate :: Readable for TcxoStatusSpec { }
#[doc = "`write(|w| ..)` method takes [`tcxo_status::W`](W) writer structure"] impl crate :: Writable for TcxoStatusSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TCXO_STATUS to value 0"] impl crate :: Resettable for TcxoStatusSpec { } }
#[doc = "TCXO_COUNT0 (rw) register accessor: TCXO count bits \\[15:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count0`] module"]
#[doc (alias = "TCXO_COUNT0")] pub type TcxoCount0 = crate :: Reg < tcxo_count0 :: TcxoCount0Spec > ;
#[doc = "TCXO count bits \\[15:0\\]"] pub mod tcxo_count0 {
#[doc = "Register `TCXO_COUNT0` reader"] pub type R = crate :: R < TcxoCount0Spec > ;
#[doc = "Register `TCXO_COUNT0` writer"] pub type W = crate :: W < TcxoCount0Spec > ;
#[doc = "Field `count0` reader - Counter value bits \\[15:0\\]"] pub type Count0R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Counter value bits \\[15:0\\]"]
#[inline (always)] pub fn count0 (& self) -> Count0R { Count0R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "TCXO count bits \\[15:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TcxoCount0Spec ; impl crate :: RegisterSpec for TcxoCount0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tcxo_count0::R`](R) reader structure"] impl crate :: Readable for TcxoCount0Spec { }
#[doc = "`write(|w| ..)` method takes [`tcxo_count0::W`](W) writer structure"] impl crate :: Writable for TcxoCount0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TCXO_COUNT0 to value 0"] impl crate :: Resettable for TcxoCount0Spec { } }
#[doc = "TCXO_COUNT1 (rw) register accessor: TCXO count bits \\[31:16\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count1`] module"]
#[doc (alias = "TCXO_COUNT1")] pub type TcxoCount1 = crate :: Reg < tcxo_count1 :: TcxoCount1Spec > ;
#[doc = "TCXO count bits \\[31:16\\]"] pub mod tcxo_count1 {
#[doc = "Register `TCXO_COUNT1` reader"] pub type R = crate :: R < TcxoCount1Spec > ;
#[doc = "Register `TCXO_COUNT1` writer"] pub type W = crate :: W < TcxoCount1Spec > ;
#[doc = "Field `count1` reader - Counter value bits \\[31:16\\]"] pub type Count1R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Counter value bits \\[31:16\\]"]
#[inline (always)] pub fn count1 (& self) -> Count1R { Count1R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "TCXO count bits \\[31:16\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TcxoCount1Spec ; impl crate :: RegisterSpec for TcxoCount1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tcxo_count1::R`](R) reader structure"] impl crate :: Readable for TcxoCount1Spec { }
#[doc = "`write(|w| ..)` method takes [`tcxo_count1::W`](W) writer structure"] impl crate :: Writable for TcxoCount1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TCXO_COUNT1 to value 0"] impl crate :: Resettable for TcxoCount1Spec { } }
#[doc = "TCXO_COUNT2 (rw) register accessor: TCXO count bits \\[47:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count2`] module"]
#[doc (alias = "TCXO_COUNT2")] pub type TcxoCount2 = crate :: Reg < tcxo_count2 :: TcxoCount2Spec > ;
#[doc = "TCXO count bits \\[47:32\\]"] pub mod tcxo_count2 {
#[doc = "Register `TCXO_COUNT2` reader"] pub type R = crate :: R < TcxoCount2Spec > ;
#[doc = "Register `TCXO_COUNT2` writer"] pub type W = crate :: W < TcxoCount2Spec > ;
#[doc = "Field `count2` reader - Counter value bits \\[47:32\\]"] pub type Count2R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Counter value bits \\[47:32\\]"]
#[inline (always)] pub fn count2 (& self) -> Count2R { Count2R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "TCXO count bits \\[47:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TcxoCount2Spec ; impl crate :: RegisterSpec for TcxoCount2Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tcxo_count2::R`](R) reader structure"] impl crate :: Readable for TcxoCount2Spec { }
#[doc = "`write(|w| ..)` method takes [`tcxo_count2::W`](W) writer structure"] impl crate :: Writable for TcxoCount2Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TCXO_COUNT2 to value 0"] impl crate :: Resettable for TcxoCount2Spec { } }
#[doc = "TCXO_COUNT3 (rw) register accessor: TCXO count bits \\[63:48\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count3`] module"]
#[doc (alias = "TCXO_COUNT3")] pub type TcxoCount3 = crate :: Reg < tcxo_count3 :: TcxoCount3Spec > ;
#[doc = "TCXO count bits \\[63:48\\]"] pub mod tcxo_count3 {
#[doc = "Register `TCXO_COUNT3` reader"] pub type R = crate :: R < TcxoCount3Spec > ;
#[doc = "Register `TCXO_COUNT3` writer"] pub type W = crate :: W < TcxoCount3Spec > ;
#[doc = "Field `count3` reader - Counter value bits \\[63:48\\]"] pub type Count3R = crate :: FieldReader < u16 > ; impl R {
#[doc = "Bits 0:15 - Counter value bits \\[63:48\\]"]
#[inline (always)] pub fn count3 (& self) -> Count3R { Count3R :: new ((self . bits & 0xffff) as u16) } } impl W { }
#[doc = "TCXO count bits \\[63:48\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TcxoCount3Spec ; impl crate :: RegisterSpec for TcxoCount3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`tcxo_count3::R`](R) reader structure"] impl crate :: Readable for TcxoCount3Spec { }
#[doc = "`write(|w| ..)` method takes [`tcxo_count3::W`](W) writer structure"] impl crate :: Writable for TcxoCount3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets TCXO_COUNT3 to value 0"] impl crate :: Resettable for TcxoCount3Spec { } } }
#[doc = "CLDO Clock and Reset Generator - clock enables, dividers, clock selects, soft resets"] pub type CldoCrg = crate :: Periph < cldo_crg :: RegisterBlock , 0x4400_1100 > ; impl core :: fmt :: Debug for CldoCrg { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("CldoCrg") . finish () } }
#[doc = "CLDO Clock and Reset Generator - clock enables, dividers, clock selects, soft resets"] pub mod cldo_crg {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { cken_ctl0 : CkenCtl0 , cken_ctl1 : CkenCtl1 , div_ctl0 : DivCtl0 , _reserved3 : [u8 ; 0x08] , div_ctl3 : DivCtl3 , div_ctl4 : DivCtl4 , div_ctl5 : DivCtl5 , _reserved6 : [u8 ; 0x04] , div_ctl7 : DivCtl7 , _reserved7 : [u8 ; 0x04] , div_ctl9 : DivCtl9 , div_ctl10 : DivCtl10 , clk_sel : ClkSel , rst_soft_cfg0 : RstSoftCfg0 , rst_soft_cfg1 : RstSoftCfg1 , } impl RegisterBlock {
#[doc = "0x00 - Clock enable control register 0"]
#[inline (always)] pub const fn cken_ctl0 (& self) -> & CkenCtl0 { & self . cken_ctl0 }
#[doc = "0x04 - Clock enable control register 1"]
#[inline (always)] pub const fn cken_ctl1 (& self) -> & CkenCtl1 { & self . cken_ctl1 }
#[doc = "0x08 - Divider control register 0"]
#[inline (always)] pub const fn div_ctl0 (& self) -> & DivCtl0 { & self . div_ctl0 }
#[doc = "0x14 - Divider control 3 - PWM0, PWM1"]
#[inline (always)] pub const fn div_ctl3 (& self) -> & DivCtl3 { & self . div_ctl3 }
#[doc = "0x18 - Divider control 4 - PWM2, PWM3, PWM4"]
#[inline (always)] pub const fn div_ctl4 (& self) -> & DivCtl4 { & self . div_ctl4 }
#[doc = "0x1c - Divider control 5 - PWM5, PWM6, PWM7"]
#[inline (always)] pub const fn div_ctl5 (& self) -> & DivCtl5 { & self . div_ctl5 }
#[doc = "0x24 - Divider control 7 - tsensor, bus"]
#[inline (always)] pub const fn div_ctl7 (& self) -> & DivCtl7 { & self . div_ctl7 }
#[doc = "0x2c - Divider control 9 - TRNG"]
#[inline (always)] pub const fn div_ctl9 (& self) -> & DivCtl9 { & self . div_ctl9 }
#[doc = "0x30 - Divider control 10 - TCXO 120M, MAC main"]
#[inline (always)] pub const fn div_ctl10 (& self) -> & DivCtl10 { & self . div_ctl10 }
#[doc = "0x34 - Clock source select register"]
#[inline (always)] pub const fn clk_sel (& self) -> & ClkSel { & self . clk_sel }
#[doc = "0x38 - Soft reset configuration register 0"]
#[inline (always)] pub const fn rst_soft_cfg0 (& self) -> & RstSoftCfg0 { & self . rst_soft_cfg0 }
#[doc = "0x3c - Soft reset configuration register 1 (active low)"]
#[inline (always)] pub const fn rst_soft_cfg1 (& self) -> & RstSoftCfg1 { & self . rst_soft_cfg1 } }
#[doc = "CKEN_CTL0 (rw) register accessor: Clock enable control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cken_ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cken_ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cken_ctl0`] module"]
#[doc (alias = "CKEN_CTL0")] pub type CkenCtl0 = crate :: Reg < cken_ctl0 :: CkenCtl0Spec > ;
#[doc = "Clock enable control register 0"] pub mod cken_ctl0 {
#[doc = "Register `CKEN_CTL0` reader"] pub type R = crate :: R < CkenCtl0Spec > ;
#[doc = "Register `CKEN_CTL0` writer"] pub type W = crate :: W < CkenCtl0Spec > ;
#[doc = "Field `pwm_cken` reader - PWM clock gates: bits \\[10:2\\], 9 channels"] pub type PwmCkenR = crate :: FieldReader < u16 > ;
#[doc = "Field `pwm_cken` writer - PWM clock gates: bits \\[10:2\\], 9 channels"] pub type PwmCkenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ;
#[doc = "Field `gen_cken` reader - General clock gates: bits \\[27:18\\], 10 channels"] pub type GenCkenR = crate :: FieldReader < u16 > ;
#[doc = "Field `gen_cken` writer - General clock gates: bits \\[27:18\\], 10 channels"] pub type GenCkenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 10 , u16 > ; impl R {
#[doc = "Bits 2:10 - PWM clock gates: bits \\[10:2\\], 9 channels"]
#[inline (always)] pub fn pwm_cken (& self) -> PwmCkenR { PwmCkenR :: new (((self . bits >> 2) & 0x01ff) as u16) }
#[doc = "Bits 18:27 - General clock gates: bits \\[27:18\\], 10 channels"]
#[inline (always)] pub fn gen_cken (& self) -> GenCkenR { GenCkenR :: new (((self . bits >> 18) & 0x03ff) as u16) } } impl W {
#[doc = "Bits 2:10 - PWM clock gates: bits \\[10:2\\], 9 channels"]
#[inline (always)] pub fn pwm_cken (& mut self) -> PwmCkenW < '_ , CkenCtl0Spec > { PwmCkenW :: new (self , 2) }
#[doc = "Bits 18:27 - General clock gates: bits \\[27:18\\], 10 channels"]
#[inline (always)] pub fn gen_cken (& mut self) -> GenCkenW < '_ , CkenCtl0Spec > { GenCkenW :: new (self , 18) } }
#[doc = "Clock enable control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cken_ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cken_ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CkenCtl0Spec ; impl crate :: RegisterSpec for CkenCtl0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cken_ctl0::R`](R) reader structure"] impl crate :: Readable for CkenCtl0Spec { }
#[doc = "`write(|w| ..)` method takes [`cken_ctl0::W`](W) writer structure"] impl crate :: Writable for CkenCtl0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CKEN_CTL0 to value 0"] impl crate :: Resettable for CkenCtl0Spec { } }
#[doc = "CKEN_CTL1 (rw) register accessor: Clock enable control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cken_ctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cken_ctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cken_ctl1`] module"]
#[doc (alias = "CKEN_CTL1")] pub type CkenCtl1 = crate :: Reg < cken_ctl1 :: CkenCtl1Spec > ;
#[doc = "Clock enable control register 1"] pub mod cken_ctl1 {
#[doc = "Register `CKEN_CTL1` reader"] pub type R = crate :: R < CkenCtl1Spec > ;
#[doc = "Register `CKEN_CTL1` writer"] pub type W = crate :: W < CkenCtl1Spec > ;
#[doc = "Field `bt_cken` reader - BT clock gates: bits \\[12:8\\], 5 channels"] pub type BtCkenR = crate :: FieldReader ;
#[doc = "Field `bt_cken` writer - BT clock gates: bits \\[12:8\\], 5 channels"] pub type BtCkenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ;
#[doc = "Field `wifi_cken` reader - WIFI clock gates: bits \\[14:13\\], 2 channels"] pub type WifiCkenR = crate :: FieldReader ;
#[doc = "Field `wifi_cken` writer - WIFI clock gates: bits \\[14:13\\], 2 channels"] pub type WifiCkenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ;
#[doc = "Field `uart_cken` reader - UART clock gates: bits \\[20:18\\], 3 channels"] pub type UartCkenR = crate :: FieldReader ;
#[doc = "Field `uart_cken` writer - UART clock gates: bits \\[20:18\\], 3 channels"] pub type UartCkenW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `spi_cken` reader - SPI clock gate at bit 25"] pub type SpiCkenR = crate :: BitReader ;
#[doc = "Field `spi_cken` writer - SPI clock gate at bit 25"] pub type SpiCkenW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 8:12 - BT clock gates: bits \\[12:8\\], 5 channels"]
#[inline (always)] pub fn bt_cken (& self) -> BtCkenR { BtCkenR :: new (((self . bits >> 8) & 0x1f) as u8) }
#[doc = "Bits 13:14 - WIFI clock gates: bits \\[14:13\\], 2 channels"]
#[inline (always)] pub fn wifi_cken (& self) -> WifiCkenR { WifiCkenR :: new (((self . bits >> 13) & 3) as u8) }
#[doc = "Bits 18:20 - UART clock gates: bits \\[20:18\\], 3 channels"]
#[inline (always)] pub fn uart_cken (& self) -> UartCkenR { UartCkenR :: new (((self . bits >> 18) & 7) as u8) }
#[doc = "Bit 25 - SPI clock gate at bit 25"]
#[inline (always)] pub fn spi_cken (& self) -> SpiCkenR { SpiCkenR :: new (((self . bits >> 25) & 1) != 0) } } impl W {
#[doc = "Bits 8:12 - BT clock gates: bits \\[12:8\\], 5 channels"]
#[inline (always)] pub fn bt_cken (& mut self) -> BtCkenW < '_ , CkenCtl1Spec > { BtCkenW :: new (self , 8) }
#[doc = "Bits 13:14 - WIFI clock gates: bits \\[14:13\\], 2 channels"]
#[inline (always)] pub fn wifi_cken (& mut self) -> WifiCkenW < '_ , CkenCtl1Spec > { WifiCkenW :: new (self , 13) }
#[doc = "Bits 18:20 - UART clock gates: bits \\[20:18\\], 3 channels"]
#[inline (always)] pub fn uart_cken (& mut self) -> UartCkenW < '_ , CkenCtl1Spec > { UartCkenW :: new (self , 18) }
#[doc = "Bit 25 - SPI clock gate at bit 25"]
#[inline (always)] pub fn spi_cken (& mut self) -> SpiCkenW < '_ , CkenCtl1Spec > { SpiCkenW :: new (self , 25) } }
#[doc = "Clock enable control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cken_ctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cken_ctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CkenCtl1Spec ; impl crate :: RegisterSpec for CkenCtl1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cken_ctl1::R`](R) reader structure"] impl crate :: Readable for CkenCtl1Spec { }
#[doc = "`write(|w| ..)` method takes [`cken_ctl1::W`](W) writer structure"] impl crate :: Writable for CkenCtl1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CKEN_CTL1 to value 0"] impl crate :: Resettable for CkenCtl1Spec { } }
#[doc = "DIV_CTL0 (rw) register accessor: Divider control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl0`] module"]
#[doc (alias = "DIV_CTL0")] pub type DivCtl0 = crate :: Reg < div_ctl0 :: DivCtl0Spec > ;
#[doc = "Divider control register 0"] pub mod div_ctl0 {
#[doc = "Register `DIV_CTL0` reader"] pub type R = crate :: R < DivCtl0Spec > ;
#[doc = "Register `DIV_CTL0` writer"] pub type W = crate :: W < DivCtl0Spec > ;
#[doc = "Field `div_ctl0` reader - Clock divider control 0"] pub type DivCtl0R = crate :: FieldReader < u32 > ;
#[doc = "Field `div_ctl0` writer - Clock divider control 0"] pub type DivCtl0W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - Clock divider control 0"]
#[inline (always)] pub fn div_ctl0 (& self) -> DivCtl0R { DivCtl0R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - Clock divider control 0"]
#[inline (always)] pub fn div_ctl0 (& mut self) -> DivCtl0W < '_ , DivCtl0Spec > { DivCtl0W :: new (self , 0) } }
#[doc = "Divider control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DivCtl0Spec ; impl crate :: RegisterSpec for DivCtl0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`div_ctl0::R`](R) reader structure"] impl crate :: Readable for DivCtl0Spec { }
#[doc = "`write(|w| ..)` method takes [`div_ctl0::W`](W) writer structure"] impl crate :: Writable for DivCtl0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DIV_CTL0 to value 0"] impl crate :: Resettable for DivCtl0Spec { } }
#[doc = "DIV_CTL3 (rw) register accessor: Divider control 3 - PWM0, PWM1\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl3`] module"]
#[doc (alias = "DIV_CTL3")] pub type DivCtl3 = crate :: Reg < div_ctl3 :: DivCtl3Spec > ;
#[doc = "Divider control 3 - PWM0, PWM1"] pub mod div_ctl3 {
#[doc = "Register `DIV_CTL3` reader"] pub type R = crate :: R < DivCtl3Spec > ;
#[doc = "Register `DIV_CTL3` writer"] pub type W = crate :: W < DivCtl3Spec > ;
#[doc = "Field `div_pwm01` reader - PWM0/PWM1 clock divider"] pub type DivPwm01R = crate :: FieldReader < u32 > ;
#[doc = "Field `div_pwm01` writer - PWM0/PWM1 clock divider"] pub type DivPwm01W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - PWM0/PWM1 clock divider"]
#[inline (always)] pub fn div_pwm01 (& self) -> DivPwm01R { DivPwm01R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - PWM0/PWM1 clock divider"]
#[inline (always)] pub fn div_pwm01 (& mut self) -> DivPwm01W < '_ , DivCtl3Spec > { DivPwm01W :: new (self , 0) } }
#[doc = "Divider control 3 - PWM0, PWM1\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DivCtl3Spec ; impl crate :: RegisterSpec for DivCtl3Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`div_ctl3::R`](R) reader structure"] impl crate :: Readable for DivCtl3Spec { }
#[doc = "`write(|w| ..)` method takes [`div_ctl3::W`](W) writer structure"] impl crate :: Writable for DivCtl3Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DIV_CTL3 to value 0"] impl crate :: Resettable for DivCtl3Spec { } }
#[doc = "DIV_CTL4 (rw) register accessor: Divider control 4 - PWM2, PWM3, PWM4\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl4`] module"]
#[doc (alias = "DIV_CTL4")] pub type DivCtl4 = crate :: Reg < div_ctl4 :: DivCtl4Spec > ;
#[doc = "Divider control 4 - PWM2, PWM3, PWM4"] pub mod div_ctl4 {
#[doc = "Register `DIV_CTL4` reader"] pub type R = crate :: R < DivCtl4Spec > ;
#[doc = "Register `DIV_CTL4` writer"] pub type W = crate :: W < DivCtl4Spec > ;
#[doc = "Field `div_pwm234` reader - PWM2/PWM3/PWM4 clock divider"] pub type DivPwm234R = crate :: FieldReader < u32 > ;
#[doc = "Field `div_pwm234` writer - PWM2/PWM3/PWM4 clock divider"] pub type DivPwm234W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - PWM2/PWM3/PWM4 clock divider"]
#[inline (always)] pub fn div_pwm234 (& self) -> DivPwm234R { DivPwm234R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - PWM2/PWM3/PWM4 clock divider"]
#[inline (always)] pub fn div_pwm234 (& mut self) -> DivPwm234W < '_ , DivCtl4Spec > { DivPwm234W :: new (self , 0) } }
#[doc = "Divider control 4 - PWM2, PWM3, PWM4\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DivCtl4Spec ; impl crate :: RegisterSpec for DivCtl4Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`div_ctl4::R`](R) reader structure"] impl crate :: Readable for DivCtl4Spec { }
#[doc = "`write(|w| ..)` method takes [`div_ctl4::W`](W) writer structure"] impl crate :: Writable for DivCtl4Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DIV_CTL4 to value 0"] impl crate :: Resettable for DivCtl4Spec { } }
#[doc = "DIV_CTL5 (rw) register accessor: Divider control 5 - PWM5, PWM6, PWM7\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl5`] module"]
#[doc (alias = "DIV_CTL5")] pub type DivCtl5 = crate :: Reg < div_ctl5 :: DivCtl5Spec > ;
#[doc = "Divider control 5 - PWM5, PWM6, PWM7"] pub mod div_ctl5 {
#[doc = "Register `DIV_CTL5` reader"] pub type R = crate :: R < DivCtl5Spec > ;
#[doc = "Register `DIV_CTL5` writer"] pub type W = crate :: W < DivCtl5Spec > ;
#[doc = "Field `div_pwm567` reader - PWM5/PWM6/PWM7 clock divider"] pub type DivPwm567R = crate :: FieldReader < u32 > ;
#[doc = "Field `div_pwm567` writer - PWM5/PWM6/PWM7 clock divider"] pub type DivPwm567W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - PWM5/PWM6/PWM7 clock divider"]
#[inline (always)] pub fn div_pwm567 (& self) -> DivPwm567R { DivPwm567R :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - PWM5/PWM6/PWM7 clock divider"]
#[inline (always)] pub fn div_pwm567 (& mut self) -> DivPwm567W < '_ , DivCtl5Spec > { DivPwm567W :: new (self , 0) } }
#[doc = "Divider control 5 - PWM5, PWM6, PWM7\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DivCtl5Spec ; impl crate :: RegisterSpec for DivCtl5Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`div_ctl5::R`](R) reader structure"] impl crate :: Readable for DivCtl5Spec { }
#[doc = "`write(|w| ..)` method takes [`div_ctl5::W`](W) writer structure"] impl crate :: Writable for DivCtl5Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DIV_CTL5 to value 0"] impl crate :: Resettable for DivCtl5Spec { } }
#[doc = "DIV_CTL7 (rw) register accessor: Divider control 7 - tsensor, bus\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl7`] module"]
#[doc (alias = "DIV_CTL7")] pub type DivCtl7 = crate :: Reg < div_ctl7 :: DivCtl7Spec > ;
#[doc = "Divider control 7 - tsensor, bus"] pub mod div_ctl7 {
#[doc = "Register `DIV_CTL7` reader"] pub type R = crate :: R < DivCtl7Spec > ;
#[doc = "Register `DIV_CTL7` writer"] pub type W = crate :: W < DivCtl7Spec > ;
#[doc = "Field `div_tsensor_bus` reader - TSENSOR and bus clock dividers"] pub type DivTsensorBusR = crate :: FieldReader < u32 > ;
#[doc = "Field `div_tsensor_bus` writer - TSENSOR and bus clock dividers"] pub type DivTsensorBusW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - TSENSOR and bus clock dividers"]
#[inline (always)] pub fn div_tsensor_bus (& self) -> DivTsensorBusR { DivTsensorBusR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - TSENSOR and bus clock dividers"]
#[inline (always)] pub fn div_tsensor_bus (& mut self) -> DivTsensorBusW < '_ , DivCtl7Spec > { DivTsensorBusW :: new (self , 0) } }
#[doc = "Divider control 7 - tsensor, bus\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DivCtl7Spec ; impl crate :: RegisterSpec for DivCtl7Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`div_ctl7::R`](R) reader structure"] impl crate :: Readable for DivCtl7Spec { }
#[doc = "`write(|w| ..)` method takes [`div_ctl7::W`](W) writer structure"] impl crate :: Writable for DivCtl7Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DIV_CTL7 to value 0"] impl crate :: Resettable for DivCtl7Spec { } }
#[doc = "DIV_CTL9 (rw) register accessor: Divider control 9 - TRNG\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl9`] module"]
#[doc (alias = "DIV_CTL9")] pub type DivCtl9 = crate :: Reg < div_ctl9 :: DivCtl9Spec > ;
#[doc = "Divider control 9 - TRNG"] pub mod div_ctl9 {
#[doc = "Register `DIV_CTL9` reader"] pub type R = crate :: R < DivCtl9Spec > ;
#[doc = "Register `DIV_CTL9` writer"] pub type W = crate :: W < DivCtl9Spec > ;
#[doc = "Field `div_trng` reader - TRNG clock divider"] pub type DivTrngR = crate :: FieldReader < u32 > ;
#[doc = "Field `div_trng` writer - TRNG clock divider"] pub type DivTrngW < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R {
#[doc = "Bits 0:31 - TRNG clock divider"]
#[inline (always)] pub fn div_trng (& self) -> DivTrngR { DivTrngR :: new (self . bits) } } impl W {
#[doc = "Bits 0:31 - TRNG clock divider"]
#[inline (always)] pub fn div_trng (& mut self) -> DivTrngW < '_ , DivCtl9Spec > { DivTrngW :: new (self , 0) } }
#[doc = "Divider control 9 - TRNG\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DivCtl9Spec ; impl crate :: RegisterSpec for DivCtl9Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`div_ctl9::R`](R) reader structure"] impl crate :: Readable for DivCtl9Spec { }
#[doc = "`write(|w| ..)` method takes [`div_ctl9::W`](W) writer structure"] impl crate :: Writable for DivCtl9Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DIV_CTL9 to value 0"] impl crate :: Resettable for DivCtl9Spec { } }
#[doc = "DIV_CTL10 (rw) register accessor: Divider control 10 - TCXO 120M, MAC main\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_ctl10`] module"]
#[doc (alias = "DIV_CTL10")] pub type DivCtl10 = crate :: Reg < div_ctl10 :: DivCtl10Spec > ;
#[doc = "Divider control 10 - TCXO 120M, MAC main"] pub mod div_ctl10 {
#[doc = "Register `DIV_CTL10` reader"] pub type R = crate :: R < DivCtl10Spec > ;
#[doc = "Register `DIV_CTL10` writer"] pub type W = crate :: W < DivCtl10Spec > ;
#[doc = "Field `tcxo_120m_div1_num` reader - TCXO 120M divider 1 value (3-bit)"] pub type Tcxo120mDiv1NumR = crate :: FieldReader ;
#[doc = "Field `tcxo_120m_div1_num` writer - TCXO 120M divider 1 value (3-bit)"] pub type Tcxo120mDiv1NumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ;
#[doc = "Field `tcxo_120m_load_div_en` reader - TCXO 120M load divider enable"] pub type Tcxo120mLoadDivEnR = crate :: BitReader ;
#[doc = "Field `tcxo_120m_load_div_en` writer - TCXO 120M load divider enable"] pub type Tcxo120mLoadDivEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tcxo_120m_div_en` reader - TCXO 120M divider enable"] pub type Tcxo120mDivEnR = crate :: BitReader ;
#[doc = "Field `tcxo_120m_div_en` writer - TCXO 120M divider enable"] pub type Tcxo120mDivEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `mac_main_div_num` reader - MAC main divider value (6-bit)"] pub type MacMainDivNumR = crate :: FieldReader ;
#[doc = "Field `mac_main_div_num` writer - MAC main divider value (6-bit)"] pub type MacMainDivNumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ;
#[doc = "Field `wtop_div_en` reader - WTO divider enable"] pub type WtopDivEnR = crate :: BitReader ;
#[doc = "Field `wtop_div_en` writer - WTO divider enable"] pub type WtopDivEnW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `tcxo_120m_div2_num` reader - TCXO 120M divider 2 value (3-bit)"] pub type Tcxo120mDiv2NumR = crate :: FieldReader ;
#[doc = "Field `tcxo_120m_div2_num` writer - TCXO 120M divider 2 value (3-bit)"] pub type Tcxo120mDiv2NumW < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R {
#[doc = "Bits 0:2 - TCXO 120M divider 1 value (3-bit)"]
#[inline (always)] pub fn tcxo_120m_div1_num (& self) -> Tcxo120mDiv1NumR { Tcxo120mDiv1NumR :: new ((self . bits & 7) as u8) }
#[doc = "Bit 3 - TCXO 120M load divider enable"]
#[inline (always)] pub fn tcxo_120m_load_div_en (& self) -> Tcxo120mLoadDivEnR { Tcxo120mLoadDivEnR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - TCXO 120M divider enable"]
#[inline (always)] pub fn tcxo_120m_div_en (& self) -> Tcxo120mDivEnR { Tcxo120mDivEnR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bits 5:10 - MAC main divider value (6-bit)"]
#[inline (always)] pub fn mac_main_div_num (& self) -> MacMainDivNumR { MacMainDivNumR :: new (((self . bits >> 5) & 0x3f) as u8) }
#[doc = "Bit 11 - WTO divider enable"]
#[inline (always)] pub fn wtop_div_en (& self) -> WtopDivEnR { WtopDivEnR :: new (((self . bits >> 11) & 1) != 0) }
#[doc = "Bits 12:14 - TCXO 120M divider 2 value (3-bit)"]
#[inline (always)] pub fn tcxo_120m_div2_num (& self) -> Tcxo120mDiv2NumR { Tcxo120mDiv2NumR :: new (((self . bits >> 12) & 7) as u8) } } impl W {
#[doc = "Bits 0:2 - TCXO 120M divider 1 value (3-bit)"]
#[inline (always)] pub fn tcxo_120m_div1_num (& mut self) -> Tcxo120mDiv1NumW < '_ , DivCtl10Spec > { Tcxo120mDiv1NumW :: new (self , 0) }
#[doc = "Bit 3 - TCXO 120M load divider enable"]
#[inline (always)] pub fn tcxo_120m_load_div_en (& mut self) -> Tcxo120mLoadDivEnW < '_ , DivCtl10Spec > { Tcxo120mLoadDivEnW :: new (self , 3) }
#[doc = "Bit 4 - TCXO 120M divider enable"]
#[inline (always)] pub fn tcxo_120m_div_en (& mut self) -> Tcxo120mDivEnW < '_ , DivCtl10Spec > { Tcxo120mDivEnW :: new (self , 4) }
#[doc = "Bits 5:10 - MAC main divider value (6-bit)"]
#[inline (always)] pub fn mac_main_div_num (& mut self) -> MacMainDivNumW < '_ , DivCtl10Spec > { MacMainDivNumW :: new (self , 5) }
#[doc = "Bit 11 - WTO divider enable"]
#[inline (always)] pub fn wtop_div_en (& mut self) -> WtopDivEnW < '_ , DivCtl10Spec > { WtopDivEnW :: new (self , 11) }
#[doc = "Bits 12:14 - TCXO 120M divider 2 value (3-bit)"]
#[inline (always)] pub fn tcxo_120m_div2_num (& mut self) -> Tcxo120mDiv2NumW < '_ , DivCtl10Spec > { Tcxo120mDiv2NumW :: new (self , 12) } }
#[doc = "Divider control 10 - TCXO 120M, MAC main\n\nYou can [`read`](crate::Reg::read) this register and get [`div_ctl10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_ctl10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DivCtl10Spec ; impl crate :: RegisterSpec for DivCtl10Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`div_ctl10::R`](R) reader structure"] impl crate :: Readable for DivCtl10Spec { }
#[doc = "`write(|w| ..)` method takes [`div_ctl10::W`](W) writer structure"] impl crate :: Writable for DivCtl10Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets DIV_CTL10 to value 0"] impl crate :: Resettable for DivCtl10Spec { } }
#[doc = "CLK_SEL (rw) register accessor: Clock source select register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_sel`] module"]
#[doc (alias = "CLK_SEL")] pub type ClkSel = crate :: Reg < clk_sel :: ClkSelSpec > ;
#[doc = "Clock source select register"] pub mod clk_sel {
#[doc = "Register `CLK_SEL` reader"] pub type R = crate :: R < ClkSelSpec > ;
#[doc = "Register `CLK_SEL` writer"] pub type W = crate :: W < ClkSelSpec > ;
#[doc = "Field `rf_ctl_clk_sel` reader - RF_CTL clock: 0=TCXO; 1=PLL"] pub type RfCtlClkSelR = crate :: BitReader ;
#[doc = "Field `rf_ctl_clk_sel` writer - RF_CTL clock: 0=TCXO; 1=PLL"] pub type RfCtlClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `uart0_clk_sel` reader - UART0 clock: 0=TCXO; 1=PLL"] pub type Uart0ClkSelR = crate :: BitReader ;
#[doc = "Field `uart0_clk_sel` writer - UART0 clock: 0=TCXO; 1=PLL"] pub type Uart0ClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `uart1_clk_sel` reader - UART1 clock select"] pub type Uart1ClkSelR = crate :: BitReader ;
#[doc = "Field `uart1_clk_sel` writer - UART1 clock select"] pub type Uart1ClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `uart2_clk_sel` reader - UART2 clock select"] pub type Uart2ClkSelR = crate :: BitReader ;
#[doc = "Field `uart2_clk_sel` writer - UART2 clock select"] pub type Uart2ClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `spi_clk_sel` reader - SPI clock select"] pub type SpiClkSelR = crate :: BitReader ;
#[doc = "Field `spi_clk_sel` writer - SPI clock select"] pub type SpiClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `pwm_clk_sel` reader - PWM clock: 0=TCXO; 1=PLL"] pub type PwmClkSelR = crate :: BitReader ;
#[doc = "Field `pwm_clk_sel` writer - PWM clock: 0=TCXO; 1=PLL"] pub type PwmClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `bus_clk_sel` reader - Bus clock select"] pub type BusClkSelR = crate :: BitReader ;
#[doc = "Field `bus_clk_sel` writer - Bus clock select"] pub type BusClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `flash_clk_sel` reader - Flash clock: 0=TCXO; 1=PLL"] pub type FlashClkSelR = crate :: BitReader ;
#[doc = "Field `flash_clk_sel` writer - Flash clock: 0=TCXO; 1=PLL"] pub type FlashClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `wifi_phy_clk_sel` reader - WIFI_PHY clock select"] pub type WifiPhyClkSelR = crate :: BitReader ;
#[doc = "Field `wifi_phy_clk_sel` writer - WIFI_PHY clock select"] pub type WifiPhyClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `wifi_mac_clk_sel` reader - WIFI_MAC clock select"] pub type WifiMacClkSelR = crate :: BitReader ;
#[doc = "Field `wifi_mac_clk_sel` writer - WIFI_MAC clock select"] pub type WifiMacClkSelW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - RF_CTL clock: 0=TCXO; 1=PLL"]
#[inline (always)] pub fn rf_ctl_clk_sel (& self) -> RfCtlClkSelR { RfCtlClkSelR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - UART0 clock: 0=TCXO; 1=PLL"]
#[inline (always)] pub fn uart0_clk_sel (& self) -> Uart0ClkSelR { Uart0ClkSelR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - UART1 clock select"]
#[inline (always)] pub fn uart1_clk_sel (& self) -> Uart1ClkSelR { Uart1ClkSelR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - UART2 clock select"]
#[inline (always)] pub fn uart2_clk_sel (& self) -> Uart2ClkSelR { Uart2ClkSelR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 6 - SPI clock select"]
#[inline (always)] pub fn spi_clk_sel (& self) -> SpiClkSelR { SpiClkSelR :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 7 - PWM clock: 0=TCXO; 1=PLL"]
#[inline (always)] pub fn pwm_clk_sel (& self) -> PwmClkSelR { PwmClkSelR :: new (((self . bits >> 7) & 1) != 0) }
#[doc = "Bit 17 - Bus clock select"]
#[inline (always)] pub fn bus_clk_sel (& self) -> BusClkSelR { BusClkSelR :: new (((self . bits >> 17) & 1) != 0) }
#[doc = "Bit 18 - Flash clock: 0=TCXO; 1=PLL"]
#[inline (always)] pub fn flash_clk_sel (& self) -> FlashClkSelR { FlashClkSelR :: new (((self . bits >> 18) & 1) != 0) }
#[doc = "Bit 19 - WIFI_PHY clock select"]
#[inline (always)] pub fn wifi_phy_clk_sel (& self) -> WifiPhyClkSelR { WifiPhyClkSelR :: new (((self . bits >> 19) & 1) != 0) }
#[doc = "Bit 20 - WIFI_MAC clock select"]
#[inline (always)] pub fn wifi_mac_clk_sel (& self) -> WifiMacClkSelR { WifiMacClkSelR :: new (((self . bits >> 20) & 1) != 0) } } impl W {
#[doc = "Bit 0 - RF_CTL clock: 0=TCXO; 1=PLL"]
#[inline (always)] pub fn rf_ctl_clk_sel (& mut self) -> RfCtlClkSelW < '_ , ClkSelSpec > { RfCtlClkSelW :: new (self , 0) }
#[doc = "Bit 1 - UART0 clock: 0=TCXO; 1=PLL"]
#[inline (always)] pub fn uart0_clk_sel (& mut self) -> Uart0ClkSelW < '_ , ClkSelSpec > { Uart0ClkSelW :: new (self , 1) }
#[doc = "Bit 2 - UART1 clock select"]
#[inline (always)] pub fn uart1_clk_sel (& mut self) -> Uart1ClkSelW < '_ , ClkSelSpec > { Uart1ClkSelW :: new (self , 2) }
#[doc = "Bit 3 - UART2 clock select"]
#[inline (always)] pub fn uart2_clk_sel (& mut self) -> Uart2ClkSelW < '_ , ClkSelSpec > { Uart2ClkSelW :: new (self , 3) }
#[doc = "Bit 6 - SPI clock select"]
#[inline (always)] pub fn spi_clk_sel (& mut self) -> SpiClkSelW < '_ , ClkSelSpec > { SpiClkSelW :: new (self , 6) }
#[doc = "Bit 7 - PWM clock: 0=TCXO; 1=PLL"]
#[inline (always)] pub fn pwm_clk_sel (& mut self) -> PwmClkSelW < '_ , ClkSelSpec > { PwmClkSelW :: new (self , 7) }
#[doc = "Bit 17 - Bus clock select"]
#[inline (always)] pub fn bus_clk_sel (& mut self) -> BusClkSelW < '_ , ClkSelSpec > { BusClkSelW :: new (self , 17) }
#[doc = "Bit 18 - Flash clock: 0=TCXO; 1=PLL"]
#[inline (always)] pub fn flash_clk_sel (& mut self) -> FlashClkSelW < '_ , ClkSelSpec > { FlashClkSelW :: new (self , 18) }
#[doc = "Bit 19 - WIFI_PHY clock select"]
#[inline (always)] pub fn wifi_phy_clk_sel (& mut self) -> WifiPhyClkSelW < '_ , ClkSelSpec > { WifiPhyClkSelW :: new (self , 19) }
#[doc = "Bit 20 - WIFI_MAC clock select"]
#[inline (always)] pub fn wifi_mac_clk_sel (& mut self) -> WifiMacClkSelW < '_ , ClkSelSpec > { WifiMacClkSelW :: new (self , 20) } }
#[doc = "Clock source select register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ClkSelSpec ; impl crate :: RegisterSpec for ClkSelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`clk_sel::R`](R) reader structure"] impl crate :: Readable for ClkSelSpec { }
#[doc = "`write(|w| ..)` method takes [`clk_sel::W`](W) writer structure"] impl crate :: Writable for ClkSelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CLK_SEL to value 0"] impl crate :: Resettable for ClkSelSpec { } }
#[doc = "RST_SOFT_CFG0 (rw) register accessor: Soft reset configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_soft_cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_soft_cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_soft_cfg0`] module"]
#[doc (alias = "RST_SOFT_CFG0")] pub type RstSoftCfg0 = crate :: Reg < rst_soft_cfg0 :: RstSoftCfg0Spec > ;
#[doc = "Soft reset configuration register 0"] pub mod rst_soft_cfg0 {
#[doc = "Register `RST_SOFT_CFG0` reader"] pub type R = crate :: R < RstSoftCfg0Spec > ;
#[doc = "Register `RST_SOFT_CFG0` writer"] pub type W = crate :: W < RstSoftCfg0Spec > ;
#[doc = "Field `cfg0_b3_b15` reader - 13-bit soft reset control (bits \\[15:3\\])"] pub type Cfg0B3B15R = crate :: FieldReader < u16 > ;
#[doc = "Field `cfg0_b3_b15` writer - 13-bit soft reset control (bits \\[15:3\\])"] pub type Cfg0B3B15W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ;
#[doc = "Field `cfg0_b17_b24` reader - 8-bit soft reset control (bits \\[24:17\\])"] pub type Cfg0B17B24R = crate :: FieldReader ;
#[doc = "Field `cfg0_b17_b24` writer - 8-bit soft reset control (bits \\[24:17\\])"] pub type Cfg0B17B24W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ;
#[doc = "Field `cfg0_b27_b28` reader - 2-bit soft reset control (bits \\[28:27\\])"] pub type Cfg0B27B28R = crate :: FieldReader ;
#[doc = "Field `cfg0_b27_b28` writer - 2-bit soft reset control (bits \\[28:27\\])"] pub type Cfg0B27B28W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ;
#[doc = "Field `cfg0_b30` reader - Soft reset bit 30"] pub type Cfg0B30R = crate :: BitReader ;
#[doc = "Field `cfg0_b30` writer - Soft reset bit 30"] pub type Cfg0B30W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bits 3:15 - 13-bit soft reset control (bits \\[15:3\\])"]
#[inline (always)] pub fn cfg0_b3_b15 (& self) -> Cfg0B3B15R { Cfg0B3B15R :: new (((self . bits >> 3) & 0x1fff) as u16) }
#[doc = "Bits 17:24 - 8-bit soft reset control (bits \\[24:17\\])"]
#[inline (always)] pub fn cfg0_b17_b24 (& self) -> Cfg0B17B24R { Cfg0B17B24R :: new (((self . bits >> 17) & 0xff) as u8) }
#[doc = "Bits 27:28 - 2-bit soft reset control (bits \\[28:27\\])"]
#[inline (always)] pub fn cfg0_b27_b28 (& self) -> Cfg0B27B28R { Cfg0B27B28R :: new (((self . bits >> 27) & 3) as u8) }
#[doc = "Bit 30 - Soft reset bit 30"]
#[inline (always)] pub fn cfg0_b30 (& self) -> Cfg0B30R { Cfg0B30R :: new (((self . bits >> 30) & 1) != 0) } } impl W {
#[doc = "Bits 3:15 - 13-bit soft reset control (bits \\[15:3\\])"]
#[inline (always)] pub fn cfg0_b3_b15 (& mut self) -> Cfg0B3B15W < '_ , RstSoftCfg0Spec > { Cfg0B3B15W :: new (self , 3) }
#[doc = "Bits 17:24 - 8-bit soft reset control (bits \\[24:17\\])"]
#[inline (always)] pub fn cfg0_b17_b24 (& mut self) -> Cfg0B17B24W < '_ , RstSoftCfg0Spec > { Cfg0B17B24W :: new (self , 17) }
#[doc = "Bits 27:28 - 2-bit soft reset control (bits \\[28:27\\])"]
#[inline (always)] pub fn cfg0_b27_b28 (& mut self) -> Cfg0B27B28W < '_ , RstSoftCfg0Spec > { Cfg0B27B28W :: new (self , 27) }
#[doc = "Bit 30 - Soft reset bit 30"]
#[inline (always)] pub fn cfg0_b30 (& mut self) -> Cfg0B30W < '_ , RstSoftCfg0Spec > { Cfg0B30W :: new (self , 30) } }
#[doc = "Soft reset configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_soft_cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_soft_cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RstSoftCfg0Spec ; impl crate :: RegisterSpec for RstSoftCfg0Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rst_soft_cfg0::R`](R) reader structure"] impl crate :: Readable for RstSoftCfg0Spec { }
#[doc = "`write(|w| ..)` method takes [`rst_soft_cfg0::W`](W) writer structure"] impl crate :: Writable for RstSoftCfg0Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RST_SOFT_CFG0 to value 0"] impl crate :: Resettable for RstSoftCfg0Spec { } }
#[doc = "RST_SOFT_CFG1 (rw) register accessor: Soft reset configuration register 1 (active low)\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_soft_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_soft_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_soft_cfg1`] module"]
#[doc (alias = "RST_SOFT_CFG1")] pub type RstSoftCfg1 = crate :: Reg < rst_soft_cfg1 :: RstSoftCfg1Spec > ;
#[doc = "Soft reset configuration register 1 (active low)"] pub mod rst_soft_cfg1 {
#[doc = "Register `RST_SOFT_CFG1` reader"] pub type R = crate :: R < RstSoftCfg1Spec > ;
#[doc = "Register `RST_SOFT_CFG1` writer"] pub type W = crate :: W < RstSoftCfg1Spec > ;
#[doc = "Field `soft_rst_gpio_n` reader - GPIO module reset: 0=reset; 1=released"] pub type SoftRstGpioNR = crate :: BitReader ;
#[doc = "Field `soft_rst_gpio_n` writer - GPIO module reset: 0=reset; 1=released"] pub type SoftRstGpioNW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_rst_tglp_n` reader - TGLP (BT) reset: 0=reset; 1=released"] pub type SoftRstTglpNR = crate :: BitReader ;
#[doc = "Field `soft_rst_tglp_n` writer - TGLP (BT) reset: 0=reset; 1=released"] pub type SoftRstTglpNW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_rst_bsub_n` reader - BSUB (BT) reset: 0=reset; 1=released"] pub type SoftRstBsubNR = crate :: BitReader ;
#[doc = "Field `soft_rst_bsub_n` writer - BSUB (BT) reset: 0=reset; 1=released"] pub type SoftRstBsubNW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_rst_crg_bsub_n` reader - CRG BSUB (BT) reset: 0=reset; 1=released"] pub type SoftRstCrgBsubNR = crate :: BitReader ;
#[doc = "Field `soft_rst_crg_bsub_n` writer - CRG BSUB (BT) reset: 0=reset; 1=released"] pub type SoftRstCrgBsubNW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_rst_wifi_n` reader - WIFI subsystem reset: 0=reset; 1=released"] pub type SoftRstWifiNR = crate :: BitReader ;
#[doc = "Field `soft_rst_wifi_n` writer - WIFI subsystem reset: 0=reset; 1=released"] pub type SoftRstWifiNW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_rst_lsadc_n` reader - LSADC core reset: 0=reset; 1=released"] pub type SoftRstLsadcNR = crate :: BitReader ;
#[doc = "Field `soft_rst_lsadc_n` writer - LSADC core reset: 0=reset; 1=released"] pub type SoftRstLsadcNW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_rst_tcxo_cnt_n` reader - TCXO counter reset: 0=reset; 1=released"] pub type SoftRstTcxoCntNR = crate :: BitReader ;
#[doc = "Field `soft_rst_tcxo_cnt_n` writer - TCXO counter reset: 0=reset; 1=released"] pub type SoftRstTcxoCntNW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_rst_lsadc_bus_n` reader - LSADC bus interface reset: 0=reset; 1=released"] pub type SoftRstLsadcBusNR = crate :: BitReader ;
#[doc = "Field `soft_rst_lsadc_bus_n` writer - LSADC bus interface reset: 0=reset; 1=released"] pub type SoftRstLsadcBusNW < 'a , REG > = crate :: BitWriter < 'a , REG > ;
#[doc = "Field `soft_rst_wcpu_mem_ctl_n` reader - WCPU memory controller reset: 0=reset; 1=released"] pub type SoftRstWcpuMemCtlNR = crate :: BitReader ;
#[doc = "Field `soft_rst_wcpu_mem_ctl_n` writer - WCPU memory controller reset: 0=reset; 1=released"] pub type SoftRstWcpuMemCtlNW < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R {
#[doc = "Bit 0 - GPIO module reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_gpio_n (& self) -> SoftRstGpioNR { SoftRstGpioNR :: new ((self . bits & 1) != 0) }
#[doc = "Bit 1 - TGLP (BT) reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_tglp_n (& self) -> SoftRstTglpNR { SoftRstTglpNR :: new (((self . bits >> 1) & 1) != 0) }
#[doc = "Bit 2 - BSUB (BT) reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_bsub_n (& self) -> SoftRstBsubNR { SoftRstBsubNR :: new (((self . bits >> 2) & 1) != 0) }
#[doc = "Bit 3 - CRG BSUB (BT) reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_crg_bsub_n (& self) -> SoftRstCrgBsubNR { SoftRstCrgBsubNR :: new (((self . bits >> 3) & 1) != 0) }
#[doc = "Bit 4 - WIFI subsystem reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_wifi_n (& self) -> SoftRstWifiNR { SoftRstWifiNR :: new (((self . bits >> 4) & 1) != 0) }
#[doc = "Bit 5 - LSADC core reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_lsadc_n (& self) -> SoftRstLsadcNR { SoftRstLsadcNR :: new (((self . bits >> 5) & 1) != 0) }
#[doc = "Bit 6 - TCXO counter reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_tcxo_cnt_n (& self) -> SoftRstTcxoCntNR { SoftRstTcxoCntNR :: new (((self . bits >> 6) & 1) != 0) }
#[doc = "Bit 7 - LSADC bus interface reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_lsadc_bus_n (& self) -> SoftRstLsadcBusNR { SoftRstLsadcBusNR :: new (((self . bits >> 7) & 1) != 0) }
#[doc = "Bit 8 - WCPU memory controller reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_wcpu_mem_ctl_n (& self) -> SoftRstWcpuMemCtlNR { SoftRstWcpuMemCtlNR :: new (((self . bits >> 8) & 1) != 0) } } impl W {
#[doc = "Bit 0 - GPIO module reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_gpio_n (& mut self) -> SoftRstGpioNW < '_ , RstSoftCfg1Spec > { SoftRstGpioNW :: new (self , 0) }
#[doc = "Bit 1 - TGLP (BT) reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_tglp_n (& mut self) -> SoftRstTglpNW < '_ , RstSoftCfg1Spec > { SoftRstTglpNW :: new (self , 1) }
#[doc = "Bit 2 - BSUB (BT) reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_bsub_n (& mut self) -> SoftRstBsubNW < '_ , RstSoftCfg1Spec > { SoftRstBsubNW :: new (self , 2) }
#[doc = "Bit 3 - CRG BSUB (BT) reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_crg_bsub_n (& mut self) -> SoftRstCrgBsubNW < '_ , RstSoftCfg1Spec > { SoftRstCrgBsubNW :: new (self , 3) }
#[doc = "Bit 4 - WIFI subsystem reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_wifi_n (& mut self) -> SoftRstWifiNW < '_ , RstSoftCfg1Spec > { SoftRstWifiNW :: new (self , 4) }
#[doc = "Bit 5 - LSADC core reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_lsadc_n (& mut self) -> SoftRstLsadcNW < '_ , RstSoftCfg1Spec > { SoftRstLsadcNW :: new (self , 5) }
#[doc = "Bit 6 - TCXO counter reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_tcxo_cnt_n (& mut self) -> SoftRstTcxoCntNW < '_ , RstSoftCfg1Spec > { SoftRstTcxoCntNW :: new (self , 6) }
#[doc = "Bit 7 - LSADC bus interface reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_lsadc_bus_n (& mut self) -> SoftRstLsadcBusNW < '_ , RstSoftCfg1Spec > { SoftRstLsadcBusNW :: new (self , 7) }
#[doc = "Bit 8 - WCPU memory controller reset: 0=reset; 1=released"]
#[inline (always)] pub fn soft_rst_wcpu_mem_ctl_n (& mut self) -> SoftRstWcpuMemCtlNW < '_ , RstSoftCfg1Spec > { SoftRstWcpuMemCtlNW :: new (self , 8) } }
#[doc = "Soft reset configuration register 1 (active low)\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_soft_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_soft_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RstSoftCfg1Spec ; impl crate :: RegisterSpec for RstSoftCfg1Spec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rst_soft_cfg1::R`](R) reader structure"] impl crate :: Readable for RstSoftCfg1Spec { }
#[doc = "`write(|w| ..)` method takes [`rst_soft_cfg1::W`](W) writer structure"] impl crate :: Writable for RstSoftCfg1Spec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RST_SOFT_CFG1 to value 0xffff_ffff"] impl crate :: Resettable for RstSoftCfg1Spec { const RESET_VALUE : u32 = 0xffff_ffff ; } } }
#[doc = "Secure DMA controller (4 channels, same layout as MDMA v151). Channels logically mapped as 8-11."] pub type Sdma = crate :: Periph < dma :: RegisterBlock , 0x520a_0000 > ; impl core :: fmt :: Debug for Sdma { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("Sdma") . finish () } }
#[doc = "Secure DMA controller (4 channels, same layout as MDMA v151). Channels logically mapped as 8-11."] pub use self :: dma as sdma ;
#[doc = "Ultra-low-power GPIO controller (8 pins, GPIO\\[107:114\\]). Same register layout as GPIO0."] pub type UlpGpio = crate :: Periph < gpio0 :: RegisterBlock , 0x5703_0000 > ; impl core :: fmt :: Debug for UlpGpio { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("UlpGpio") . finish () } }
#[doc = "Ultra-low-power GPIO controller (8 pins, GPIO\\[107:114\\]). Same register layout as GPIO0."] pub use self :: gpio0 as ulp_gpio ;
#[doc = "SYS_CTL2 sub-block: RF Wideband Control Register Block - WL/BT RF analog interface control"] pub type RfWbCtl = crate :: Periph < rf_wb_ctl :: RegisterBlock , 0x4400_4000 > ; impl core :: fmt :: Debug for RfWbCtl { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("RfWbCtl") . finish () } }
#[doc = "SYS_CTL2 sub-block: RF Wideband Control Register Block - WL/BT RF analog interface control"] pub mod rf_wb_ctl {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { sys_ctl_id : SysCtlId , _reserved1 : [u8 ; 0x0c] , rf_wl_reg_clk_ctl : RfWlRegClkCtl , rf_wl_reg_soft_rstn : RfWlRegSoftRstn , rf_wl_reg_cmd_soft_rstn : RfWlRegCmdSoftRstn , rf_wl_reg_cmd_fifo_sts : RfWlRegCmdFifoSts , rf_wl_cbb_dis : RfWlCbbDis , rf_bt_cbb_dis : RfBtCbbDis , _reserved7 : [u8 ; 0x08] , abb_adc_ctrl : AbbAdcCtrl , abb_dac_ctrl : AbbDacCtrl , abb_en_ctrl : AbbEnCtrl , cfg_wl_adc_mux : CfgWlAdcMux , cfg_rf_man_en_ctrl : CfgRfManEnCtrl , cfg_trxen_ctrl : CfgTrxenCtrl , cfg_dcoc_iq_ctrl : CfgDcocIqCtrl , cfg_pa_idx_ctrl : CfgPaIdxCtrl , cfg_lpf_ctrl : CfgLpfCtrl , cfg_radar_ctrl : CfgRadarCtrl , cfg_ppa_code : CfgPpaCode , cfg_temp_lock_ctrl : CfgTempLockCtrl , cfg_temp_bank_sel_ctrl : CfgTempBankSelCtrl , cfg_rf_diag_mux : CfgRfDiagMux , } impl RegisterBlock {
#[doc = "0x00 - System control ID register"]
#[inline (always)] pub const fn sys_ctl_id (& self) -> & SysCtlId { & self . sys_ctl_id }
#[doc = "0x10 - RF WL register clock control"]
#[inline (always)] pub const fn rf_wl_reg_clk_ctl (& self) -> & RfWlRegClkCtl { & self . rf_wl_reg_clk_ctl }
#[doc = "0x14 - RF WL register soft reset"]
#[inline (always)] pub const fn rf_wl_reg_soft_rstn (& self) -> & RfWlRegSoftRstn { & self . rf_wl_reg_soft_rstn }
#[doc = "0x18 - RF WL command soft reset"]
#[inline (always)] pub const fn rf_wl_reg_cmd_soft_rstn (& self) -> & RfWlRegCmdSoftRstn { & self . rf_wl_reg_cmd_soft_rstn }
#[doc = "0x1c - RF WL command FIFO status"]
#[inline (always)] pub const fn rf_wl_reg_cmd_fifo_sts (& self) -> & RfWlRegCmdFifoSts { & self . rf_wl_reg_cmd_fifo_sts }
#[doc = "0x20 - RF WL CBB disable"]
#[inline (always)] pub const fn rf_wl_cbb_dis (& self) -> & RfWlCbbDis { & self . rf_wl_cbb_dis }
#[doc = "0x24 - RF BT CBB disable"]
#[inline (always)] pub const fn rf_bt_cbb_dis (& self) -> & RfBtCbbDis { & self . rf_bt_cbb_dis }
#[doc = "0x30 - ABB ADC control"]
#[inline (always)] pub const fn abb_adc_ctrl (& self) -> & AbbAdcCtrl { & self . abb_adc_ctrl }
#[doc = "0x34 - ABB DAC control"]
#[inline (always)] pub const fn abb_dac_ctrl (& self) -> & AbbDacCtrl { & self . abb_dac_ctrl }
#[doc = "0x38 - ABB enable control"]
#[inline (always)] pub const fn abb_en_ctrl (& self) -> & AbbEnCtrl { & self . abb_en_ctrl }
#[doc = "0x3c - WL ADC mux configuration"]
#[inline (always)] pub const fn cfg_wl_adc_mux (& self) -> & CfgWlAdcMux { & self . cfg_wl_adc_mux }
#[doc = "0x40 - RF manual enable control"]
#[inline (always)] pub const fn cfg_rf_man_en_ctrl (& self) -> & CfgRfManEnCtrl { & self . cfg_rf_man_en_ctrl }
#[doc = "0x44 - TRX enable control"]
#[inline (always)] pub const fn cfg_trxen_ctrl (& self) -> & CfgTrxenCtrl { & self . cfg_trxen_ctrl }
#[doc = "0x48 - DCOC IQ control"]
#[inline (always)] pub const fn cfg_dcoc_iq_ctrl (& self) -> & CfgDcocIqCtrl { & self . cfg_dcoc_iq_ctrl }
#[doc = "0x4c - PA index control"]
#[inline (always)] pub const fn cfg_pa_idx_ctrl (& self) -> & CfgPaIdxCtrl { & self . cfg_pa_idx_ctrl }
#[doc = "0x50 - LPF control"]
#[inline (always)] pub const fn cfg_lpf_ctrl (& self) -> & CfgLpfCtrl { & self . cfg_lpf_ctrl }
#[doc = "0x54 - Radar control"]
#[inline (always)] pub const fn cfg_radar_ctrl (& self) -> & CfgRadarCtrl { & self . cfg_radar_ctrl }
#[doc = "0x58 - PPA code register"]
#[inline (always)] pub const fn cfg_ppa_code (& self) -> & CfgPpaCode { & self . cfg_ppa_code }
#[doc = "0x5c - Temperature lock control"]
#[inline (always)] pub const fn cfg_temp_lock_ctrl (& self) -> & CfgTempLockCtrl { & self . cfg_temp_lock_ctrl }
#[doc = "0x60 - Temperature bank select control"]
#[inline (always)] pub const fn cfg_temp_bank_sel_ctrl (& self) -> & CfgTempBankSelCtrl { & self . cfg_temp_bank_sel_ctrl }
#[doc = "0x64 - RF diagnostic mux"]
#[inline (always)] pub const fn cfg_rf_diag_mux (& self) -> & CfgRfDiagMux { & self . cfg_rf_diag_mux } }
#[doc = "SYS_CTL_ID (rw) register accessor: System control ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_ctl_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_ctl_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_ctl_id`] module"]
#[doc (alias = "SYS_CTL_ID")] pub type SysCtlId = crate :: Reg < sys_ctl_id :: SysCtlIdSpec > ;
#[doc = "System control ID register"] pub mod sys_ctl_id {
#[doc = "Register `SYS_CTL_ID` reader"] pub type R = crate :: R < SysCtlIdSpec > ;
#[doc = "Register `SYS_CTL_ID` writer"] pub type W = crate :: W < SysCtlIdSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "System control ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_ctl_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_ctl_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SysCtlIdSpec ; impl crate :: RegisterSpec for SysCtlIdSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`sys_ctl_id::R`](R) reader structure"] impl crate :: Readable for SysCtlIdSpec { }
#[doc = "`write(|w| ..)` method takes [`sys_ctl_id::W`](W) writer structure"] impl crate :: Writable for SysCtlIdSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets SYS_CTL_ID to value 0"] impl crate :: Resettable for SysCtlIdSpec { } }
#[doc = "RF_WL_REG_CLK_CTL (rw) register accessor: RF WL register clock control\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_clk_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_clk_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_wl_reg_clk_ctl`] module"]
#[doc (alias = "RF_WL_REG_CLK_CTL")] pub type RfWlRegClkCtl = crate :: Reg < rf_wl_reg_clk_ctl :: RfWlRegClkCtlSpec > ;
#[doc = "RF WL register clock control"] pub mod rf_wl_reg_clk_ctl {
#[doc = "Register `RF_WL_REG_CLK_CTL` reader"] pub type R = crate :: R < RfWlRegClkCtlSpec > ;
#[doc = "Register `RF_WL_REG_CLK_CTL` writer"] pub type W = crate :: W < RfWlRegClkCtlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RF WL register clock control\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_clk_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_clk_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RfWlRegClkCtlSpec ; impl crate :: RegisterSpec for RfWlRegClkCtlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rf_wl_reg_clk_ctl::R`](R) reader structure"] impl crate :: Readable for RfWlRegClkCtlSpec { }
#[doc = "`write(|w| ..)` method takes [`rf_wl_reg_clk_ctl::W`](W) writer structure"] impl crate :: Writable for RfWlRegClkCtlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RF_WL_REG_CLK_CTL to value 0"] impl crate :: Resettable for RfWlRegClkCtlSpec { } }
#[doc = "RF_WL_REG_SOFT_RSTN (rw) register accessor: RF WL register soft reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_soft_rstn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_soft_rstn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_wl_reg_soft_rstn`] module"]
#[doc (alias = "RF_WL_REG_SOFT_RSTN")] pub type RfWlRegSoftRstn = crate :: Reg < rf_wl_reg_soft_rstn :: RfWlRegSoftRstnSpec > ;
#[doc = "RF WL register soft reset"] pub mod rf_wl_reg_soft_rstn {
#[doc = "Register `RF_WL_REG_SOFT_RSTN` reader"] pub type R = crate :: R < RfWlRegSoftRstnSpec > ;
#[doc = "Register `RF_WL_REG_SOFT_RSTN` writer"] pub type W = crate :: W < RfWlRegSoftRstnSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RF WL register soft reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_soft_rstn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_soft_rstn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RfWlRegSoftRstnSpec ; impl crate :: RegisterSpec for RfWlRegSoftRstnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rf_wl_reg_soft_rstn::R`](R) reader structure"] impl crate :: Readable for RfWlRegSoftRstnSpec { }
#[doc = "`write(|w| ..)` method takes [`rf_wl_reg_soft_rstn::W`](W) writer structure"] impl crate :: Writable for RfWlRegSoftRstnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RF_WL_REG_SOFT_RSTN to value 0"] impl crate :: Resettable for RfWlRegSoftRstnSpec { } }
#[doc = "RF_WL_REG_CMD_SOFT_RSTN (rw) register accessor: RF WL command soft reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_cmd_soft_rstn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_cmd_soft_rstn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_wl_reg_cmd_soft_rstn`] module"]
#[doc (alias = "RF_WL_REG_CMD_SOFT_RSTN")] pub type RfWlRegCmdSoftRstn = crate :: Reg < rf_wl_reg_cmd_soft_rstn :: RfWlRegCmdSoftRstnSpec > ;
#[doc = "RF WL command soft reset"] pub mod rf_wl_reg_cmd_soft_rstn {
#[doc = "Register `RF_WL_REG_CMD_SOFT_RSTN` reader"] pub type R = crate :: R < RfWlRegCmdSoftRstnSpec > ;
#[doc = "Register `RF_WL_REG_CMD_SOFT_RSTN` writer"] pub type W = crate :: W < RfWlRegCmdSoftRstnSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RF WL command soft reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_cmd_soft_rstn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_cmd_soft_rstn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RfWlRegCmdSoftRstnSpec ; impl crate :: RegisterSpec for RfWlRegCmdSoftRstnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rf_wl_reg_cmd_soft_rstn::R`](R) reader structure"] impl crate :: Readable for RfWlRegCmdSoftRstnSpec { }
#[doc = "`write(|w| ..)` method takes [`rf_wl_reg_cmd_soft_rstn::W`](W) writer structure"] impl crate :: Writable for RfWlRegCmdSoftRstnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RF_WL_REG_CMD_SOFT_RSTN to value 0"] impl crate :: Resettable for RfWlRegCmdSoftRstnSpec { } }
#[doc = "RF_WL_REG_CMD_FIFO_STS (rw) register accessor: RF WL command FIFO status\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_cmd_fifo_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_cmd_fifo_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_wl_reg_cmd_fifo_sts`] module"]
#[doc (alias = "RF_WL_REG_CMD_FIFO_STS")] pub type RfWlRegCmdFifoSts = crate :: Reg < rf_wl_reg_cmd_fifo_sts :: RfWlRegCmdFifoStsSpec > ;
#[doc = "RF WL command FIFO status"] pub mod rf_wl_reg_cmd_fifo_sts {
#[doc = "Register `RF_WL_REG_CMD_FIFO_STS` reader"] pub type R = crate :: R < RfWlRegCmdFifoStsSpec > ;
#[doc = "Register `RF_WL_REG_CMD_FIFO_STS` writer"] pub type W = crate :: W < RfWlRegCmdFifoStsSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RF WL command FIFO status\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_reg_cmd_fifo_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_reg_cmd_fifo_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RfWlRegCmdFifoStsSpec ; impl crate :: RegisterSpec for RfWlRegCmdFifoStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rf_wl_reg_cmd_fifo_sts::R`](R) reader structure"] impl crate :: Readable for RfWlRegCmdFifoStsSpec { }
#[doc = "`write(|w| ..)` method takes [`rf_wl_reg_cmd_fifo_sts::W`](W) writer structure"] impl crate :: Writable for RfWlRegCmdFifoStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RF_WL_REG_CMD_FIFO_STS to value 0"] impl crate :: Resettable for RfWlRegCmdFifoStsSpec { } }
#[doc = "RF_WL_CBB_DIS (rw) register accessor: RF WL CBB disable\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_cbb_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_cbb_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_wl_cbb_dis`] module"]
#[doc (alias = "RF_WL_CBB_DIS")] pub type RfWlCbbDis = crate :: Reg < rf_wl_cbb_dis :: RfWlCbbDisSpec > ;
#[doc = "RF WL CBB disable"] pub mod rf_wl_cbb_dis {
#[doc = "Register `RF_WL_CBB_DIS` reader"] pub type R = crate :: R < RfWlCbbDisSpec > ;
#[doc = "Register `RF_WL_CBB_DIS` writer"] pub type W = crate :: W < RfWlCbbDisSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RF WL CBB disable\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_wl_cbb_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_wl_cbb_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RfWlCbbDisSpec ; impl crate :: RegisterSpec for RfWlCbbDisSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rf_wl_cbb_dis::R`](R) reader structure"] impl crate :: Readable for RfWlCbbDisSpec { }
#[doc = "`write(|w| ..)` method takes [`rf_wl_cbb_dis::W`](W) writer structure"] impl crate :: Writable for RfWlCbbDisSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RF_WL_CBB_DIS to value 0"] impl crate :: Resettable for RfWlCbbDisSpec { } }
#[doc = "RF_BT_CBB_DIS (rw) register accessor: RF BT CBB disable\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_bt_cbb_dis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_bt_cbb_dis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_bt_cbb_dis`] module"]
#[doc (alias = "RF_BT_CBB_DIS")] pub type RfBtCbbDis = crate :: Reg < rf_bt_cbb_dis :: RfBtCbbDisSpec > ;
#[doc = "RF BT CBB disable"] pub mod rf_bt_cbb_dis {
#[doc = "Register `RF_BT_CBB_DIS` reader"] pub type R = crate :: R < RfBtCbbDisSpec > ;
#[doc = "Register `RF_BT_CBB_DIS` writer"] pub type W = crate :: W < RfBtCbbDisSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RF BT CBB disable\n\nYou can [`read`](crate::Reg::read) this register and get [`rf_bt_cbb_dis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rf_bt_cbb_dis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RfBtCbbDisSpec ; impl crate :: RegisterSpec for RfBtCbbDisSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`rf_bt_cbb_dis::R`](R) reader structure"] impl crate :: Readable for RfBtCbbDisSpec { }
#[doc = "`write(|w| ..)` method takes [`rf_bt_cbb_dis::W`](W) writer structure"] impl crate :: Writable for RfBtCbbDisSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RF_BT_CBB_DIS to value 0"] impl crate :: Resettable for RfBtCbbDisSpec { } }
#[doc = "ABB_ADC_CTRL (rw) register accessor: ABB ADC control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_adc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_adc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abb_adc_ctrl`] module"]
#[doc (alias = "ABB_ADC_CTRL")] pub type AbbAdcCtrl = crate :: Reg < abb_adc_ctrl :: AbbAdcCtrlSpec > ;
#[doc = "ABB ADC control"] pub mod abb_adc_ctrl {
#[doc = "Register `ABB_ADC_CTRL` reader"] pub type R = crate :: R < AbbAdcCtrlSpec > ;
#[doc = "Register `ABB_ADC_CTRL` writer"] pub type W = crate :: W < AbbAdcCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "ABB ADC control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_adc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_adc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AbbAdcCtrlSpec ; impl crate :: RegisterSpec for AbbAdcCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`abb_adc_ctrl::R`](R) reader structure"] impl crate :: Readable for AbbAdcCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`abb_adc_ctrl::W`](W) writer structure"] impl crate :: Writable for AbbAdcCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets ABB_ADC_CTRL to value 0"] impl crate :: Resettable for AbbAdcCtrlSpec { } }
#[doc = "ABB_DAC_CTRL (rw) register accessor: ABB DAC control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_dac_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_dac_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abb_dac_ctrl`] module"]
#[doc (alias = "ABB_DAC_CTRL")] pub type AbbDacCtrl = crate :: Reg < abb_dac_ctrl :: AbbDacCtrlSpec > ;
#[doc = "ABB DAC control"] pub mod abb_dac_ctrl {
#[doc = "Register `ABB_DAC_CTRL` reader"] pub type R = crate :: R < AbbDacCtrlSpec > ;
#[doc = "Register `ABB_DAC_CTRL` writer"] pub type W = crate :: W < AbbDacCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "ABB DAC control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_dac_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_dac_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AbbDacCtrlSpec ; impl crate :: RegisterSpec for AbbDacCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`abb_dac_ctrl::R`](R) reader structure"] impl crate :: Readable for AbbDacCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`abb_dac_ctrl::W`](W) writer structure"] impl crate :: Writable for AbbDacCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets ABB_DAC_CTRL to value 0"] impl crate :: Resettable for AbbDacCtrlSpec { } }
#[doc = "ABB_EN_CTRL (rw) register accessor: ABB enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_en_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_en_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abb_en_ctrl`] module"]
#[doc (alias = "ABB_EN_CTRL")] pub type AbbEnCtrl = crate :: Reg < abb_en_ctrl :: AbbEnCtrlSpec > ;
#[doc = "ABB enable control"] pub mod abb_en_ctrl {
#[doc = "Register `ABB_EN_CTRL` reader"] pub type R = crate :: R < AbbEnCtrlSpec > ;
#[doc = "Register `ABB_EN_CTRL` writer"] pub type W = crate :: W < AbbEnCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "ABB enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`abb_en_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abb_en_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AbbEnCtrlSpec ; impl crate :: RegisterSpec for AbbEnCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`abb_en_ctrl::R`](R) reader structure"] impl crate :: Readable for AbbEnCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`abb_en_ctrl::W`](W) writer structure"] impl crate :: Writable for AbbEnCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets ABB_EN_CTRL to value 0"] impl crate :: Resettable for AbbEnCtrlSpec { } }
#[doc = "CFG_WL_ADC_MUX (rw) register accessor: WL ADC mux configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wl_adc_mux::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wl_adc_mux::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_wl_adc_mux`] module"]
#[doc (alias = "CFG_WL_ADC_MUX")] pub type CfgWlAdcMux = crate :: Reg < cfg_wl_adc_mux :: CfgWlAdcMuxSpec > ;
#[doc = "WL ADC mux configuration"] pub mod cfg_wl_adc_mux {
#[doc = "Register `CFG_WL_ADC_MUX` reader"] pub type R = crate :: R < CfgWlAdcMuxSpec > ;
#[doc = "Register `CFG_WL_ADC_MUX` writer"] pub type W = crate :: W < CfgWlAdcMuxSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "WL ADC mux configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wl_adc_mux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wl_adc_mux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgWlAdcMuxSpec ; impl crate :: RegisterSpec for CfgWlAdcMuxSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_wl_adc_mux::R`](R) reader structure"] impl crate :: Readable for CfgWlAdcMuxSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_wl_adc_mux::W`](W) writer structure"] impl crate :: Writable for CfgWlAdcMuxSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_WL_ADC_MUX to value 0"] impl crate :: Resettable for CfgWlAdcMuxSpec { } }
#[doc = "CFG_RF_MAN_EN_CTRL (rw) register accessor: RF manual enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rf_man_en_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rf_man_en_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rf_man_en_ctrl`] module"]
#[doc (alias = "CFG_RF_MAN_EN_CTRL")] pub type CfgRfManEnCtrl = crate :: Reg < cfg_rf_man_en_ctrl :: CfgRfManEnCtrlSpec > ;
#[doc = "RF manual enable control"] pub mod cfg_rf_man_en_ctrl {
#[doc = "Register `CFG_RF_MAN_EN_CTRL` reader"] pub type R = crate :: R < CfgRfManEnCtrlSpec > ;
#[doc = "Register `CFG_RF_MAN_EN_CTRL` writer"] pub type W = crate :: W < CfgRfManEnCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RF manual enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rf_man_en_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rf_man_en_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgRfManEnCtrlSpec ; impl crate :: RegisterSpec for CfgRfManEnCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_rf_man_en_ctrl::R`](R) reader structure"] impl crate :: Readable for CfgRfManEnCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_rf_man_en_ctrl::W`](W) writer structure"] impl crate :: Writable for CfgRfManEnCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_RF_MAN_EN_CTRL to value 0"] impl crate :: Resettable for CfgRfManEnCtrlSpec { } }
#[doc = "CFG_TRXEN_CTRL (rw) register accessor: TRX enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_trxen_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_trxen_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_trxen_ctrl`] module"]
#[doc (alias = "CFG_TRXEN_CTRL")] pub type CfgTrxenCtrl = crate :: Reg < cfg_trxen_ctrl :: CfgTrxenCtrlSpec > ;
#[doc = "TRX enable control"] pub mod cfg_trxen_ctrl {
#[doc = "Register `CFG_TRXEN_CTRL` reader"] pub type R = crate :: R < CfgTrxenCtrlSpec > ;
#[doc = "Register `CFG_TRXEN_CTRL` writer"] pub type W = crate :: W < CfgTrxenCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "TRX enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_trxen_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_trxen_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgTrxenCtrlSpec ; impl crate :: RegisterSpec for CfgTrxenCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_trxen_ctrl::R`](R) reader structure"] impl crate :: Readable for CfgTrxenCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_trxen_ctrl::W`](W) writer structure"] impl crate :: Writable for CfgTrxenCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_TRXEN_CTRL to value 0"] impl crate :: Resettable for CfgTrxenCtrlSpec { } }
#[doc = "CFG_DCOC_IQ_CTRL (rw) register accessor: DCOC IQ control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_iq_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_iq_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_iq_ctrl`] module"]
#[doc (alias = "CFG_DCOC_IQ_CTRL")] pub type CfgDcocIqCtrl = crate :: Reg < cfg_dcoc_iq_ctrl :: CfgDcocIqCtrlSpec > ;
#[doc = "DCOC IQ control"] pub mod cfg_dcoc_iq_ctrl {
#[doc = "Register `CFG_DCOC_IQ_CTRL` reader"] pub type R = crate :: R < CfgDcocIqCtrlSpec > ;
#[doc = "Register `CFG_DCOC_IQ_CTRL` writer"] pub type W = crate :: W < CfgDcocIqCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "DCOC IQ control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_iq_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_iq_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgDcocIqCtrlSpec ; impl crate :: RegisterSpec for CfgDcocIqCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_dcoc_iq_ctrl::R`](R) reader structure"] impl crate :: Readable for CfgDcocIqCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_dcoc_iq_ctrl::W`](W) writer structure"] impl crate :: Writable for CfgDcocIqCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_DCOC_IQ_CTRL to value 0"] impl crate :: Resettable for CfgDcocIqCtrlSpec { } }
#[doc = "CFG_PA_IDX_CTRL (rw) register accessor: PA index control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_pa_idx_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_pa_idx_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_pa_idx_ctrl`] module"]
#[doc (alias = "CFG_PA_IDX_CTRL")] pub type CfgPaIdxCtrl = crate :: Reg < cfg_pa_idx_ctrl :: CfgPaIdxCtrlSpec > ;
#[doc = "PA index control"] pub mod cfg_pa_idx_ctrl {
#[doc = "Register `CFG_PA_IDX_CTRL` reader"] pub type R = crate :: R < CfgPaIdxCtrlSpec > ;
#[doc = "Register `CFG_PA_IDX_CTRL` writer"] pub type W = crate :: W < CfgPaIdxCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "PA index control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_pa_idx_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_pa_idx_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgPaIdxCtrlSpec ; impl crate :: RegisterSpec for CfgPaIdxCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_pa_idx_ctrl::R`](R) reader structure"] impl crate :: Readable for CfgPaIdxCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_pa_idx_ctrl::W`](W) writer structure"] impl crate :: Writable for CfgPaIdxCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_PA_IDX_CTRL to value 0"] impl crate :: Resettable for CfgPaIdxCtrlSpec { } }
#[doc = "CFG_LPF_CTRL (rw) register accessor: LPF control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_lpf_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_lpf_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_lpf_ctrl`] module"]
#[doc (alias = "CFG_LPF_CTRL")] pub type CfgLpfCtrl = crate :: Reg < cfg_lpf_ctrl :: CfgLpfCtrlSpec > ;
#[doc = "LPF control"] pub mod cfg_lpf_ctrl {
#[doc = "Register `CFG_LPF_CTRL` reader"] pub type R = crate :: R < CfgLpfCtrlSpec > ;
#[doc = "Register `CFG_LPF_CTRL` writer"] pub type W = crate :: W < CfgLpfCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "LPF control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_lpf_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_lpf_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgLpfCtrlSpec ; impl crate :: RegisterSpec for CfgLpfCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_lpf_ctrl::R`](R) reader structure"] impl crate :: Readable for CfgLpfCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_lpf_ctrl::W`](W) writer structure"] impl crate :: Writable for CfgLpfCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_LPF_CTRL to value 0"] impl crate :: Resettable for CfgLpfCtrlSpec { } }
#[doc = "CFG_RADAR_CTRL (rw) register accessor: Radar control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_radar_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_radar_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_radar_ctrl`] module"]
#[doc (alias = "CFG_RADAR_CTRL")] pub type CfgRadarCtrl = crate :: Reg < cfg_radar_ctrl :: CfgRadarCtrlSpec > ;
#[doc = "Radar control"] pub mod cfg_radar_ctrl {
#[doc = "Register `CFG_RADAR_CTRL` reader"] pub type R = crate :: R < CfgRadarCtrlSpec > ;
#[doc = "Register `CFG_RADAR_CTRL` writer"] pub type W = crate :: W < CfgRadarCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "Radar control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_radar_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_radar_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgRadarCtrlSpec ; impl crate :: RegisterSpec for CfgRadarCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_radar_ctrl::R`](R) reader structure"] impl crate :: Readable for CfgRadarCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_radar_ctrl::W`](W) writer structure"] impl crate :: Writable for CfgRadarCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_RADAR_CTRL to value 0"] impl crate :: Resettable for CfgRadarCtrlSpec { } }
#[doc = "CFG_PPA_CODE (rw) register accessor: PPA code register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ppa_code::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ppa_code::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_ppa_code`] module"]
#[doc (alias = "CFG_PPA_CODE")] pub type CfgPpaCode = crate :: Reg < cfg_ppa_code :: CfgPpaCodeSpec > ;
#[doc = "PPA code register"] pub mod cfg_ppa_code {
#[doc = "Register `CFG_PPA_CODE` reader"] pub type R = crate :: R < CfgPpaCodeSpec > ;
#[doc = "Register `CFG_PPA_CODE` writer"] pub type W = crate :: W < CfgPpaCodeSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "PPA code register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ppa_code::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ppa_code::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgPpaCodeSpec ; impl crate :: RegisterSpec for CfgPpaCodeSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_ppa_code::R`](R) reader structure"] impl crate :: Readable for CfgPpaCodeSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_ppa_code::W`](W) writer structure"] impl crate :: Writable for CfgPpaCodeSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_PPA_CODE to value 0"] impl crate :: Resettable for CfgPpaCodeSpec { } }
#[doc = "CFG_TEMP_LOCK_CTRL (rw) register accessor: Temperature lock control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_temp_lock_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_temp_lock_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_temp_lock_ctrl`] module"]
#[doc (alias = "CFG_TEMP_LOCK_CTRL")] pub type CfgTempLockCtrl = crate :: Reg < cfg_temp_lock_ctrl :: CfgTempLockCtrlSpec > ;
#[doc = "Temperature lock control"] pub mod cfg_temp_lock_ctrl {
#[doc = "Register `CFG_TEMP_LOCK_CTRL` reader"] pub type R = crate :: R < CfgTempLockCtrlSpec > ;
#[doc = "Register `CFG_TEMP_LOCK_CTRL` writer"] pub type W = crate :: W < CfgTempLockCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "Temperature lock control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_temp_lock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_temp_lock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgTempLockCtrlSpec ; impl crate :: RegisterSpec for CfgTempLockCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_temp_lock_ctrl::R`](R) reader structure"] impl crate :: Readable for CfgTempLockCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_temp_lock_ctrl::W`](W) writer structure"] impl crate :: Writable for CfgTempLockCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_TEMP_LOCK_CTRL to value 0"] impl crate :: Resettable for CfgTempLockCtrlSpec { } }
#[doc = "CFG_TEMP_BANK_SEL_CTRL (rw) register accessor: Temperature bank select control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_temp_bank_sel_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_temp_bank_sel_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_temp_bank_sel_ctrl`] module"]
#[doc (alias = "CFG_TEMP_BANK_SEL_CTRL")] pub type CfgTempBankSelCtrl = crate :: Reg < cfg_temp_bank_sel_ctrl :: CfgTempBankSelCtrlSpec > ;
#[doc = "Temperature bank select control"] pub mod cfg_temp_bank_sel_ctrl {
#[doc = "Register `CFG_TEMP_BANK_SEL_CTRL` reader"] pub type R = crate :: R < CfgTempBankSelCtrlSpec > ;
#[doc = "Register `CFG_TEMP_BANK_SEL_CTRL` writer"] pub type W = crate :: W < CfgTempBankSelCtrlSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "Temperature bank select control\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_temp_bank_sel_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_temp_bank_sel_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgTempBankSelCtrlSpec ; impl crate :: RegisterSpec for CfgTempBankSelCtrlSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_temp_bank_sel_ctrl::R`](R) reader structure"] impl crate :: Readable for CfgTempBankSelCtrlSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_temp_bank_sel_ctrl::W`](W) writer structure"] impl crate :: Writable for CfgTempBankSelCtrlSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_TEMP_BANK_SEL_CTRL to value 0"] impl crate :: Resettable for CfgTempBankSelCtrlSpec { } }
#[doc = "CFG_RF_DIAG_MUX (rw) register accessor: RF diagnostic mux\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rf_diag_mux::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rf_diag_mux::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rf_diag_mux`] module"]
#[doc (alias = "CFG_RF_DIAG_MUX")] pub type CfgRfDiagMux = crate :: Reg < cfg_rf_diag_mux :: CfgRfDiagMuxSpec > ;
#[doc = "RF diagnostic mux"] pub mod cfg_rf_diag_mux {
#[doc = "Register `CFG_RF_DIAG_MUX` reader"] pub type R = crate :: R < CfgRfDiagMuxSpec > ;
#[doc = "Register `CFG_RF_DIAG_MUX` writer"] pub type W = crate :: W < CfgRfDiagMuxSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RF diagnostic mux\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rf_diag_mux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rf_diag_mux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgRfDiagMuxSpec ; impl crate :: RegisterSpec for CfgRfDiagMuxSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_rf_diag_mux::R`](R) reader structure"] impl crate :: Readable for CfgRfDiagMuxSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_rf_diag_mux::W`](W) writer structure"] impl crate :: Writable for CfgRfDiagMuxSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_RF_DIAG_MUX to value 0"] impl crate :: Resettable for CfgRfDiagMuxSpec { } } }
#[doc = "SYS_CTL2 sub-block: Shared Memory Control - RAM config, RX/TX DMA descriptor rings for WiFi PHY↔Packet buffer"] pub type ShareMemCtl = crate :: Periph < share_mem_ctl :: RegisterBlock , 0x4400_6c00 > ; impl core :: fmt :: Debug for ShareMemCtl { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("ShareMemCtl") . finish () } }
#[doc = "SYS_CTL2 sub-block: Shared Memory Control - RAM config, RX/TX DMA descriptor rings for WiFi PHY↔Packet buffer"] pub mod share_mem_ctl {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { _reserved0 : [u8 ; 0x04] , cfg_ram_cken : CfgRamCken , cfg_ram_sel : CfgRamSel , ram_sw_conflict_clr : RamSwConflictClr , ram_sw_conflict_st : RamSwConflictSt , ramx_sw_conflict_base_addr : RamxSwConflictBaseAddr , _reserved5 : [u8 ; 0x38] , cfg_freq_busdmac : CfgFreqBusdmac , _reserved6 : [u8 ; 0x04] , cfg_rx_en : CfgRxEn , cfg_rx_start_addr : CfgRxStartAddr , cfg_rx_end_addr : CfgRxEndAddr , cfg_rx_done_sts : CfgRxDoneSts , cfg_rx_done_addr : CfgRxDoneAddr , cfg_wlphy2pkt_rx_ram_sts : CfgWlphy2pktRxRamSts , cfg_tx_en : CfgTxEn , cfg_tx_start_addr : CfgTxStartAddr , cfg_tx_end_addr : CfgTxEndAddr , cfg_tx_done_sts : CfgTxDoneSts , cfg_tx_done_addr : CfgTxDoneAddr , cfg_wlphy2pkt_tx_ram_sts : CfgWlphy2pktTxRamSts , } impl RegisterBlock {
#[doc = "0x04 - RAM clock enable"]
#[inline (always)] pub const fn cfg_ram_cken (& self) -> & CfgRamCken { & self . cfg_ram_cken }
#[doc = "0x08 - Share RAM control and RAM select"]
#[inline (always)] pub const fn cfg_ram_sel (& self) -> & CfgRamSel { & self . cfg_ram_sel }
#[doc = "0x0c - RAM software conflict clear"]
#[inline (always)] pub const fn ram_sw_conflict_clr (& self) -> & RamSwConflictClr { & self . ram_sw_conflict_clr }
#[doc = "0x10 - RAM software conflict status"]
#[inline (always)] pub const fn ram_sw_conflict_st (& self) -> & RamSwConflictSt { & self . ram_sw_conflict_st }
#[doc = "0x14 - RAMX software conflict base address"]
#[inline (always)] pub const fn ramx_sw_conflict_base_addr (& self) -> & RamxSwConflictBaseAddr { & self . ramx_sw_conflict_base_addr }
#[doc = "0x50 - Bus DMAC frequency configuration"]
#[inline (always)] pub const fn cfg_freq_busdmac (& self) -> & CfgFreqBusdmac { & self . cfg_freq_busdmac }
#[doc = "0x58 - RX enable"]
#[inline (always)] pub const fn cfg_rx_en (& self) -> & CfgRxEn { & self . cfg_rx_en }
#[doc = "0x5c - RX start address"]
#[inline (always)] pub const fn cfg_rx_start_addr (& self) -> & CfgRxStartAddr { & self . cfg_rx_start_addr }
#[doc = "0x60 - RX end address"]
#[inline (always)] pub const fn cfg_rx_end_addr (& self) -> & CfgRxEndAddr { & self . cfg_rx_end_addr }
#[doc = "0x64 - RX done status"]
#[inline (always)] pub const fn cfg_rx_done_sts (& self) -> & CfgRxDoneSts { & self . cfg_rx_done_sts }
#[doc = "0x68 - RX done address"]
#[inline (always)] pub const fn cfg_rx_done_addr (& self) -> & CfgRxDoneAddr { & self . cfg_rx_done_addr }
#[doc = "0x6c - WL PHY-to-packet RX RAM status"]
#[inline (always)] pub const fn cfg_wlphy2pkt_rx_ram_sts (& self) -> & CfgWlphy2pktRxRamSts { & self . cfg_wlphy2pkt_rx_ram_sts }
#[doc = "0x70 - TX enable"]
#[inline (always)] pub const fn cfg_tx_en (& self) -> & CfgTxEn { & self . cfg_tx_en }
#[doc = "0x74 - TX start address"]
#[inline (always)] pub const fn cfg_tx_start_addr (& self) -> & CfgTxStartAddr { & self . cfg_tx_start_addr }
#[doc = "0x78 - TX end address"]
#[inline (always)] pub const fn cfg_tx_end_addr (& self) -> & CfgTxEndAddr { & self . cfg_tx_end_addr }
#[doc = "0x7c - TX done status"]
#[inline (always)] pub const fn cfg_tx_done_sts (& self) -> & CfgTxDoneSts { & self . cfg_tx_done_sts }
#[doc = "0x80 - TX done address"]
#[inline (always)] pub const fn cfg_tx_done_addr (& self) -> & CfgTxDoneAddr { & self . cfg_tx_done_addr }
#[doc = "0x84 - WL PHY-to-packet TX RAM status"]
#[inline (always)] pub const fn cfg_wlphy2pkt_tx_ram_sts (& self) -> & CfgWlphy2pktTxRamSts { & self . cfg_wlphy2pkt_tx_ram_sts } }
#[doc = "CFG_RAM_CKEN (rw) register accessor: RAM clock enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ram_cken::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ram_cken::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_ram_cken`] module"]
#[doc (alias = "CFG_RAM_CKEN")] pub type CfgRamCken = crate :: Reg < cfg_ram_cken :: CfgRamCkenSpec > ;
#[doc = "RAM clock enable"] pub mod cfg_ram_cken {
#[doc = "Register `CFG_RAM_CKEN` reader"] pub type R = crate :: R < CfgRamCkenSpec > ;
#[doc = "Register `CFG_RAM_CKEN` writer"] pub type W = crate :: W < CfgRamCkenSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RAM clock enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ram_cken::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ram_cken::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgRamCkenSpec ; impl crate :: RegisterSpec for CfgRamCkenSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_ram_cken::R`](R) reader structure"] impl crate :: Readable for CfgRamCkenSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_ram_cken::W`](W) writer structure"] impl crate :: Writable for CfgRamCkenSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_RAM_CKEN to value 0"] impl crate :: Resettable for CfgRamCkenSpec { } }
#[doc = "CFG_RAM_SEL (rw) register accessor: Share RAM control and RAM select\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ram_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ram_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_ram_sel`] module"]
#[doc (alias = "CFG_RAM_SEL")] pub type CfgRamSel = crate :: Reg < cfg_ram_sel :: CfgRamSelSpec > ;
#[doc = "Share RAM control and RAM select"] pub mod cfg_ram_sel {
#[doc = "Register `CFG_RAM_SEL` reader"] pub type R = crate :: R < CfgRamSelSpec > ;
#[doc = "Register `CFG_RAM_SEL` writer"] pub type W = crate :: W < CfgRamSelSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "Share RAM control and RAM select\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_ram_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_ram_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgRamSelSpec ; impl crate :: RegisterSpec for CfgRamSelSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_ram_sel::R`](R) reader structure"] impl crate :: Readable for CfgRamSelSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_ram_sel::W`](W) writer structure"] impl crate :: Writable for CfgRamSelSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_RAM_SEL to value 0"] impl crate :: Resettable for CfgRamSelSpec { } }
#[doc = "RAM_SW_CONFLICT_CLR (rw) register accessor: RAM software conflict clear\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sw_conflict_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sw_conflict_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sw_conflict_clr`] module"]
#[doc (alias = "RAM_SW_CONFLICT_CLR")] pub type RamSwConflictClr = crate :: Reg < ram_sw_conflict_clr :: RamSwConflictClrSpec > ;
#[doc = "RAM software conflict clear"] pub mod ram_sw_conflict_clr {
#[doc = "Register `RAM_SW_CONFLICT_CLR` reader"] pub type R = crate :: R < RamSwConflictClrSpec > ;
#[doc = "Register `RAM_SW_CONFLICT_CLR` writer"] pub type W = crate :: W < RamSwConflictClrSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RAM software conflict clear\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sw_conflict_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sw_conflict_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RamSwConflictClrSpec ; impl crate :: RegisterSpec for RamSwConflictClrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`ram_sw_conflict_clr::R`](R) reader structure"] impl crate :: Readable for RamSwConflictClrSpec { }
#[doc = "`write(|w| ..)` method takes [`ram_sw_conflict_clr::W`](W) writer structure"] impl crate :: Writable for RamSwConflictClrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RAM_SW_CONFLICT_CLR to value 0"] impl crate :: Resettable for RamSwConflictClrSpec { } }
#[doc = "RAM_SW_CONFLICT_ST (rw) register accessor: RAM software conflict status\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sw_conflict_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sw_conflict_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sw_conflict_st`] module"]
#[doc (alias = "RAM_SW_CONFLICT_ST")] pub type RamSwConflictSt = crate :: Reg < ram_sw_conflict_st :: RamSwConflictStSpec > ;
#[doc = "RAM software conflict status"] pub mod ram_sw_conflict_st {
#[doc = "Register `RAM_SW_CONFLICT_ST` reader"] pub type R = crate :: R < RamSwConflictStSpec > ;
#[doc = "Register `RAM_SW_CONFLICT_ST` writer"] pub type W = crate :: W < RamSwConflictStSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RAM software conflict status\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sw_conflict_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sw_conflict_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RamSwConflictStSpec ; impl crate :: RegisterSpec for RamSwConflictStSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`ram_sw_conflict_st::R`](R) reader structure"] impl crate :: Readable for RamSwConflictStSpec { }
#[doc = "`write(|w| ..)` method takes [`ram_sw_conflict_st::W`](W) writer structure"] impl crate :: Writable for RamSwConflictStSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RAM_SW_CONFLICT_ST to value 0"] impl crate :: Resettable for RamSwConflictStSpec { } }
#[doc = "RAMX_SW_CONFLICT_BASE_ADDR (rw) register accessor: RAMX software conflict base address\n\nYou can [`read`](crate::Reg::read) this register and get [`ramx_sw_conflict_base_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ramx_sw_conflict_base_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ramx_sw_conflict_base_addr`] module"]
#[doc (alias = "RAMX_SW_CONFLICT_BASE_ADDR")] pub type RamxSwConflictBaseAddr = crate :: Reg < ramx_sw_conflict_base_addr :: RamxSwConflictBaseAddrSpec > ;
#[doc = "RAMX software conflict base address"] pub mod ramx_sw_conflict_base_addr {
#[doc = "Register `RAMX_SW_CONFLICT_BASE_ADDR` reader"] pub type R = crate :: R < RamxSwConflictBaseAddrSpec > ;
#[doc = "Register `RAMX_SW_CONFLICT_BASE_ADDR` writer"] pub type W = crate :: W < RamxSwConflictBaseAddrSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RAMX software conflict base address\n\nYou can [`read`](crate::Reg::read) this register and get [`ramx_sw_conflict_base_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ramx_sw_conflict_base_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RamxSwConflictBaseAddrSpec ; impl crate :: RegisterSpec for RamxSwConflictBaseAddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`ramx_sw_conflict_base_addr::R`](R) reader structure"] impl crate :: Readable for RamxSwConflictBaseAddrSpec { }
#[doc = "`write(|w| ..)` method takes [`ramx_sw_conflict_base_addr::W`](W) writer structure"] impl crate :: Writable for RamxSwConflictBaseAddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets RAMX_SW_CONFLICT_BASE_ADDR to value 0"] impl crate :: Resettable for RamxSwConflictBaseAddrSpec { } }
#[doc = "CFG_FREQ_BUSDMAC (rw) register accessor: Bus DMAC frequency configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_freq_busdmac::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_freq_busdmac::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_freq_busdmac`] module"]
#[doc (alias = "CFG_FREQ_BUSDMAC")] pub type CfgFreqBusdmac = crate :: Reg < cfg_freq_busdmac :: CfgFreqBusdmacSpec > ;
#[doc = "Bus DMAC frequency configuration"] pub mod cfg_freq_busdmac {
#[doc = "Register `CFG_FREQ_BUSDMAC` reader"] pub type R = crate :: R < CfgFreqBusdmacSpec > ;
#[doc = "Register `CFG_FREQ_BUSDMAC` writer"] pub type W = crate :: W < CfgFreqBusdmacSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "Bus DMAC frequency configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_freq_busdmac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_freq_busdmac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgFreqBusdmacSpec ; impl crate :: RegisterSpec for CfgFreqBusdmacSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_freq_busdmac::R`](R) reader structure"] impl crate :: Readable for CfgFreqBusdmacSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_freq_busdmac::W`](W) writer structure"] impl crate :: Writable for CfgFreqBusdmacSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_FREQ_BUSDMAC to value 0"] impl crate :: Resettable for CfgFreqBusdmacSpec { } }
#[doc = "CFG_RX_EN (rw) register accessor: RX enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rx_en`] module"]
#[doc (alias = "CFG_RX_EN")] pub type CfgRxEn = crate :: Reg < cfg_rx_en :: CfgRxEnSpec > ;
#[doc = "RX enable"] pub mod cfg_rx_en {
#[doc = "Register `CFG_RX_EN` reader"] pub type R = crate :: R < CfgRxEnSpec > ;
#[doc = "Register `CFG_RX_EN` writer"] pub type W = crate :: W < CfgRxEnSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RX enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgRxEnSpec ; impl crate :: RegisterSpec for CfgRxEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_rx_en::R`](R) reader structure"] impl crate :: Readable for CfgRxEnSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_rx_en::W`](W) writer structure"] impl crate :: Writable for CfgRxEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_RX_EN to value 0"] impl crate :: Resettable for CfgRxEnSpec { } }
#[doc = "CFG_RX_START_ADDR (rw) register accessor: RX start address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_start_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_start_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rx_start_addr`] module"]
#[doc (alias = "CFG_RX_START_ADDR")] pub type CfgRxStartAddr = crate :: Reg < cfg_rx_start_addr :: CfgRxStartAddrSpec > ;
#[doc = "RX start address"] pub mod cfg_rx_start_addr {
#[doc = "Register `CFG_RX_START_ADDR` reader"] pub type R = crate :: R < CfgRxStartAddrSpec > ;
#[doc = "Register `CFG_RX_START_ADDR` writer"] pub type W = crate :: W < CfgRxStartAddrSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RX start address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_start_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_start_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgRxStartAddrSpec ; impl crate :: RegisterSpec for CfgRxStartAddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_rx_start_addr::R`](R) reader structure"] impl crate :: Readable for CfgRxStartAddrSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_rx_start_addr::W`](W) writer structure"] impl crate :: Writable for CfgRxStartAddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_RX_START_ADDR to value 0"] impl crate :: Resettable for CfgRxStartAddrSpec { } }
#[doc = "CFG_RX_END_ADDR (rw) register accessor: RX end address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_end_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_end_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rx_end_addr`] module"]
#[doc (alias = "CFG_RX_END_ADDR")] pub type CfgRxEndAddr = crate :: Reg < cfg_rx_end_addr :: CfgRxEndAddrSpec > ;
#[doc = "RX end address"] pub mod cfg_rx_end_addr {
#[doc = "Register `CFG_RX_END_ADDR` reader"] pub type R = crate :: R < CfgRxEndAddrSpec > ;
#[doc = "Register `CFG_RX_END_ADDR` writer"] pub type W = crate :: W < CfgRxEndAddrSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RX end address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_end_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_end_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgRxEndAddrSpec ; impl crate :: RegisterSpec for CfgRxEndAddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_rx_end_addr::R`](R) reader structure"] impl crate :: Readable for CfgRxEndAddrSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_rx_end_addr::W`](W) writer structure"] impl crate :: Writable for CfgRxEndAddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_RX_END_ADDR to value 0"] impl crate :: Resettable for CfgRxEndAddrSpec { } }
#[doc = "CFG_RX_DONE_STS (rw) register accessor: RX done status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_done_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_done_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rx_done_sts`] module"]
#[doc (alias = "CFG_RX_DONE_STS")] pub type CfgRxDoneSts = crate :: Reg < cfg_rx_done_sts :: CfgRxDoneStsSpec > ;
#[doc = "RX done status"] pub mod cfg_rx_done_sts {
#[doc = "Register `CFG_RX_DONE_STS` reader"] pub type R = crate :: R < CfgRxDoneStsSpec > ;
#[doc = "Register `CFG_RX_DONE_STS` writer"] pub type W = crate :: W < CfgRxDoneStsSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RX done status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_done_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_done_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgRxDoneStsSpec ; impl crate :: RegisterSpec for CfgRxDoneStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_rx_done_sts::R`](R) reader structure"] impl crate :: Readable for CfgRxDoneStsSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_rx_done_sts::W`](W) writer structure"] impl crate :: Writable for CfgRxDoneStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_RX_DONE_STS to value 0"] impl crate :: Resettable for CfgRxDoneStsSpec { } }
#[doc = "CFG_RX_DONE_ADDR (rw) register accessor: RX done address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_done_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_done_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rx_done_addr`] module"]
#[doc (alias = "CFG_RX_DONE_ADDR")] pub type CfgRxDoneAddr = crate :: Reg < cfg_rx_done_addr :: CfgRxDoneAddrSpec > ;
#[doc = "RX done address"] pub mod cfg_rx_done_addr {
#[doc = "Register `CFG_RX_DONE_ADDR` reader"] pub type R = crate :: R < CfgRxDoneAddrSpec > ;
#[doc = "Register `CFG_RX_DONE_ADDR` writer"] pub type W = crate :: W < CfgRxDoneAddrSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "RX done address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rx_done_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rx_done_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgRxDoneAddrSpec ; impl crate :: RegisterSpec for CfgRxDoneAddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_rx_done_addr::R`](R) reader structure"] impl crate :: Readable for CfgRxDoneAddrSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_rx_done_addr::W`](W) writer structure"] impl crate :: Writable for CfgRxDoneAddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_RX_DONE_ADDR to value 0"] impl crate :: Resettable for CfgRxDoneAddrSpec { } }
#[doc = "CFG_WLPHY2PKT_RX_RAM_STS (rw) register accessor: WL PHY-to-packet RX RAM status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wlphy2pkt_rx_ram_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wlphy2pkt_rx_ram_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_wlphy2pkt_rx_ram_sts`] module"]
#[doc (alias = "CFG_WLPHY2PKT_RX_RAM_STS")] pub type CfgWlphy2pktRxRamSts = crate :: Reg < cfg_wlphy2pkt_rx_ram_sts :: CfgWlphy2pktRxRamStsSpec > ;
#[doc = "WL PHY-to-packet RX RAM status"] pub mod cfg_wlphy2pkt_rx_ram_sts {
#[doc = "Register `CFG_WLPHY2PKT_RX_RAM_STS` reader"] pub type R = crate :: R < CfgWlphy2pktRxRamStsSpec > ;
#[doc = "Register `CFG_WLPHY2PKT_RX_RAM_STS` writer"] pub type W = crate :: W < CfgWlphy2pktRxRamStsSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "WL PHY-to-packet RX RAM status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wlphy2pkt_rx_ram_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wlphy2pkt_rx_ram_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgWlphy2pktRxRamStsSpec ; impl crate :: RegisterSpec for CfgWlphy2pktRxRamStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_wlphy2pkt_rx_ram_sts::R`](R) reader structure"] impl crate :: Readable for CfgWlphy2pktRxRamStsSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_wlphy2pkt_rx_ram_sts::W`](W) writer structure"] impl crate :: Writable for CfgWlphy2pktRxRamStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_WLPHY2PKT_RX_RAM_STS to value 0"] impl crate :: Resettable for CfgWlphy2pktRxRamStsSpec { } }
#[doc = "CFG_TX_EN (rw) register accessor: TX enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tx_en`] module"]
#[doc (alias = "CFG_TX_EN")] pub type CfgTxEn = crate :: Reg < cfg_tx_en :: CfgTxEnSpec > ;
#[doc = "TX enable"] pub mod cfg_tx_en {
#[doc = "Register `CFG_TX_EN` reader"] pub type R = crate :: R < CfgTxEnSpec > ;
#[doc = "Register `CFG_TX_EN` writer"] pub type W = crate :: W < CfgTxEnSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "TX enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgTxEnSpec ; impl crate :: RegisterSpec for CfgTxEnSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_tx_en::R`](R) reader structure"] impl crate :: Readable for CfgTxEnSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_tx_en::W`](W) writer structure"] impl crate :: Writable for CfgTxEnSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_TX_EN to value 0"] impl crate :: Resettable for CfgTxEnSpec { } }
#[doc = "CFG_TX_START_ADDR (rw) register accessor: TX start address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_start_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_start_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tx_start_addr`] module"]
#[doc (alias = "CFG_TX_START_ADDR")] pub type CfgTxStartAddr = crate :: Reg < cfg_tx_start_addr :: CfgTxStartAddrSpec > ;
#[doc = "TX start address"] pub mod cfg_tx_start_addr {
#[doc = "Register `CFG_TX_START_ADDR` reader"] pub type R = crate :: R < CfgTxStartAddrSpec > ;
#[doc = "Register `CFG_TX_START_ADDR` writer"] pub type W = crate :: W < CfgTxStartAddrSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "TX start address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_start_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_start_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgTxStartAddrSpec ; impl crate :: RegisterSpec for CfgTxStartAddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_tx_start_addr::R`](R) reader structure"] impl crate :: Readable for CfgTxStartAddrSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_tx_start_addr::W`](W) writer structure"] impl crate :: Writable for CfgTxStartAddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_TX_START_ADDR to value 0"] impl crate :: Resettable for CfgTxStartAddrSpec { } }
#[doc = "CFG_TX_END_ADDR (rw) register accessor: TX end address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_end_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_end_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tx_end_addr`] module"]
#[doc (alias = "CFG_TX_END_ADDR")] pub type CfgTxEndAddr = crate :: Reg < cfg_tx_end_addr :: CfgTxEndAddrSpec > ;
#[doc = "TX end address"] pub mod cfg_tx_end_addr {
#[doc = "Register `CFG_TX_END_ADDR` reader"] pub type R = crate :: R < CfgTxEndAddrSpec > ;
#[doc = "Register `CFG_TX_END_ADDR` writer"] pub type W = crate :: W < CfgTxEndAddrSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "TX end address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_end_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_end_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgTxEndAddrSpec ; impl crate :: RegisterSpec for CfgTxEndAddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_tx_end_addr::R`](R) reader structure"] impl crate :: Readable for CfgTxEndAddrSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_tx_end_addr::W`](W) writer structure"] impl crate :: Writable for CfgTxEndAddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_TX_END_ADDR to value 0"] impl crate :: Resettable for CfgTxEndAddrSpec { } }
#[doc = "CFG_TX_DONE_STS (rw) register accessor: TX done status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_done_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_done_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tx_done_sts`] module"]
#[doc (alias = "CFG_TX_DONE_STS")] pub type CfgTxDoneSts = crate :: Reg < cfg_tx_done_sts :: CfgTxDoneStsSpec > ;
#[doc = "TX done status"] pub mod cfg_tx_done_sts {
#[doc = "Register `CFG_TX_DONE_STS` reader"] pub type R = crate :: R < CfgTxDoneStsSpec > ;
#[doc = "Register `CFG_TX_DONE_STS` writer"] pub type W = crate :: W < CfgTxDoneStsSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "TX done status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_done_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_done_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgTxDoneStsSpec ; impl crate :: RegisterSpec for CfgTxDoneStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_tx_done_sts::R`](R) reader structure"] impl crate :: Readable for CfgTxDoneStsSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_tx_done_sts::W`](W) writer structure"] impl crate :: Writable for CfgTxDoneStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_TX_DONE_STS to value 0"] impl crate :: Resettable for CfgTxDoneStsSpec { } }
#[doc = "CFG_TX_DONE_ADDR (rw) register accessor: TX done address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_done_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_done_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tx_done_addr`] module"]
#[doc (alias = "CFG_TX_DONE_ADDR")] pub type CfgTxDoneAddr = crate :: Reg < cfg_tx_done_addr :: CfgTxDoneAddrSpec > ;
#[doc = "TX done address"] pub mod cfg_tx_done_addr {
#[doc = "Register `CFG_TX_DONE_ADDR` reader"] pub type R = crate :: R < CfgTxDoneAddrSpec > ;
#[doc = "Register `CFG_TX_DONE_ADDR` writer"] pub type W = crate :: W < CfgTxDoneAddrSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "TX done address\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tx_done_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tx_done_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgTxDoneAddrSpec ; impl crate :: RegisterSpec for CfgTxDoneAddrSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_tx_done_addr::R`](R) reader structure"] impl crate :: Readable for CfgTxDoneAddrSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_tx_done_addr::W`](W) writer structure"] impl crate :: Writable for CfgTxDoneAddrSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_TX_DONE_ADDR to value 0"] impl crate :: Resettable for CfgTxDoneAddrSpec { } }
#[doc = "CFG_WLPHY2PKT_TX_RAM_STS (rw) register accessor: WL PHY-to-packet TX RAM status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wlphy2pkt_tx_ram_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wlphy2pkt_tx_ram_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_wlphy2pkt_tx_ram_sts`] module"]
#[doc (alias = "CFG_WLPHY2PKT_TX_RAM_STS")] pub type CfgWlphy2pktTxRamSts = crate :: Reg < cfg_wlphy2pkt_tx_ram_sts :: CfgWlphy2pktTxRamStsSpec > ;
#[doc = "WL PHY-to-packet TX RAM status"] pub mod cfg_wlphy2pkt_tx_ram_sts {
#[doc = "Register `CFG_WLPHY2PKT_TX_RAM_STS` reader"] pub type R = crate :: R < CfgWlphy2pktTxRamStsSpec > ;
#[doc = "Register `CFG_WLPHY2PKT_TX_RAM_STS` writer"] pub type W = crate :: W < CfgWlphy2pktTxRamStsSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "WL PHY-to-packet TX RAM status\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_wlphy2pkt_tx_ram_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_wlphy2pkt_tx_ram_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CfgWlphy2pktTxRamStsSpec ; impl crate :: RegisterSpec for CfgWlphy2pktTxRamStsSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`cfg_wlphy2pkt_tx_ram_sts::R`](R) reader structure"] impl crate :: Readable for CfgWlphy2pktTxRamStsSpec { }
#[doc = "`write(|w| ..)` method takes [`cfg_wlphy2pkt_tx_ram_sts::W`](W) writer structure"] impl crate :: Writable for CfgWlphy2pktTxRamStsSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets CFG_WLPHY2PKT_TX_RAM_STS to value 0"] impl crate :: Resettable for CfgWlphy2pktTxRamStsSpec { } } }
#[doc = "SYS_CTL2 sub-block: Flash Address Map Remap - up to 12 regions for boot-time address redirection"] pub type FamaRemap = crate :: Periph < fama_remap :: RegisterBlock , 0x4400_7800 > ; impl core :: fmt :: Debug for FamaRemap { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("FamaRemap") . finish () } }
#[doc = "SYS_CTL2 sub-block: Flash Address Map Remap - up to 12 regions for boot-time address redirection"] pub mod fama_remap {
#[repr (C)]
#[doc = "Register block"] pub struct RegisterBlock { remap_src_base : RemapSrcBase , _reserved1 : [u8 ; 0x1c] , remap_len : RemapLen , _reserved2 : [u8 ; 0x1c] , remap_dst_base : RemapDstBase , } impl RegisterBlock {
#[doc = "0x00 - Remap source base address (address >> 12). Up to 12 regions, offset 0x0 + 0x4*n"]
#[inline (always)] pub const fn remap_src_base (& self) -> & RemapSrcBase { & self . remap_src_base }
#[doc = "0x20 - Remap region length (end address >> 12). offset 0x20 + 0x4*n"]
#[inline (always)] pub const fn remap_len (& self) -> & RemapLen { & self . remap_len }
#[doc = "0x40 - Remap destination base offset (dest - src). offset 0x40 + 0x4*n"]
#[inline (always)] pub const fn remap_dst_base (& self) -> & RemapDstBase { & self . remap_dst_base } }
#[doc = "REMAP_SRC_BASE (rw) register accessor: Remap source base address (address >> 12). Up to 12 regions, offset 0x0 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_src_base::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_src_base::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap_src_base`] module"]
#[doc (alias = "REMAP_SRC_BASE")] pub type RemapSrcBase = crate :: Reg < remap_src_base :: RemapSrcBaseSpec > ;
#[doc = "Remap source base address (address >> 12). Up to 12 regions, offset 0x0 + 0x4*n"] pub mod remap_src_base {
#[doc = "Register `REMAP_SRC_BASE` reader"] pub type R = crate :: R < RemapSrcBaseSpec > ;
#[doc = "Register `REMAP_SRC_BASE` writer"] pub type W = crate :: W < RemapSrcBaseSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "Remap source base address (address >> 12). Up to 12 regions, offset 0x0 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_src_base::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_src_base::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RemapSrcBaseSpec ; impl crate :: RegisterSpec for RemapSrcBaseSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`remap_src_base::R`](R) reader structure"] impl crate :: Readable for RemapSrcBaseSpec { }
#[doc = "`write(|w| ..)` method takes [`remap_src_base::W`](W) writer structure"] impl crate :: Writable for RemapSrcBaseSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets REMAP_SRC_BASE to value 0"] impl crate :: Resettable for RemapSrcBaseSpec { } }
#[doc = "REMAP_LEN (rw) register accessor: Remap region length (end address >> 12). offset 0x20 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap_len`] module"]
#[doc (alias = "REMAP_LEN")] pub type RemapLen = crate :: Reg < remap_len :: RemapLenSpec > ;
#[doc = "Remap region length (end address >> 12). offset 0x20 + 0x4*n"] pub mod remap_len {
#[doc = "Register `REMAP_LEN` reader"] pub type R = crate :: R < RemapLenSpec > ;
#[doc = "Register `REMAP_LEN` writer"] pub type W = crate :: W < RemapLenSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "Remap region length (end address >> 12). offset 0x20 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RemapLenSpec ; impl crate :: RegisterSpec for RemapLenSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`remap_len::R`](R) reader structure"] impl crate :: Readable for RemapLenSpec { }
#[doc = "`write(|w| ..)` method takes [`remap_len::W`](W) writer structure"] impl crate :: Writable for RemapLenSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets REMAP_LEN to value 0"] impl crate :: Resettable for RemapLenSpec { } }
#[doc = "REMAP_DST_BASE (rw) register accessor: Remap destination base offset (dest - src). offset 0x40 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_dst_base::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_dst_base::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap_dst_base`] module"]
#[doc (alias = "REMAP_DST_BASE")] pub type RemapDstBase = crate :: Reg < remap_dst_base :: RemapDstBaseSpec > ;
#[doc = "Remap destination base offset (dest - src). offset 0x40 + 0x4*n"] pub mod remap_dst_base {
#[doc = "Register `REMAP_DST_BASE` reader"] pub type R = crate :: R < RemapDstBaseSpec > ;
#[doc = "Register `REMAP_DST_BASE` writer"] pub type W = crate :: W < RemapDstBaseSpec > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl W { }
#[doc = "Remap destination base offset (dest - src). offset 0x40 + 0x4*n\n\nYou can [`read`](crate::Reg::read) this register and get [`remap_dst_base::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap_dst_base::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RemapDstBaseSpec ; impl crate :: RegisterSpec for RemapDstBaseSpec { type Ux = u32 ; }
#[doc = "`read()` method returns [`remap_dst_base::R`](R) reader structure"] impl crate :: Readable for RemapDstBaseSpec { }
#[doc = "`write(|w| ..)` method takes [`remap_dst_base::W`](W) writer structure"] impl crate :: Writable for RemapDstBaseSpec { type Safety = crate :: Unsafe ; }
#[doc = "`reset()` method sets REMAP_DST_BASE to value 0"] impl crate :: Resettable for RemapDstBaseSpec { } } }
#[unsafe (no_mangle)] static mut DEVICE_PERIPHERALS : bool = false ;
#[doc = r" All the peripherals."]
#[allow (non_snake_case)] pub struct Peripherals {
#[doc = "SYS_CTL1"] pub sys_ctl1 : SysCtl1 ,
#[doc = "IO_CONFIG"] pub io_config : IoConfig ,
#[doc = "GPIO0"] pub gpio0 : Gpio0 ,
#[doc = "GPIO1"] pub gpio1 : Gpio1 ,
#[doc = "GPIO2"] pub gpio2 : Gpio2 ,
#[doc = "UART0"] pub uart0 : Uart0 ,
#[doc = "UART1"] pub uart1 : Uart1 ,
#[doc = "UART2"] pub uart2 : Uart2 ,
#[doc = "I2C0"] pub i2c0 : I2c0 ,
#[doc = "I2C1"] pub i2c1 : I2c1 ,
#[doc = "PWM"] pub pwm : Pwm ,
#[doc = "DMA"] pub dma : Dma ,
#[doc = "SFC_CFG"] pub sfc_cfg : SfcCfg ,
#[doc = "SPI0"] pub spi0 : Spi0 ,
#[doc = "SPI1"] pub spi1 : Spi1 ,
#[doc = "I2S"] pub i2s : I2s ,
#[doc = "LSADC"] pub lsadc : Lsadc ,
#[doc = "TSENSOR"] pub tsensor : Tsensor ,
#[doc = "TIMER"] pub timer : Timer ,
#[doc = "WDT"] pub wdt : Wdt ,
#[doc = "RTC"] pub rtc : Rtc ,
#[doc = "EFUSE"] pub efuse : Efuse ,
#[doc = "SYS_CTL0"] pub sys_ctl0 : SysCtl0 ,
#[doc = "GLB_CTL_M"] pub glb_ctl_m : GlbCtlM ,
#[doc = "SPACC"] pub spacc : Spacc ,
#[doc = "PKE"] pub pke : Pke ,
#[doc = "KM"] pub km : Km ,
#[doc = "TRNG"] pub trng : Trng ,
#[doc = "TCXO"] pub tcxo : Tcxo ,
#[doc = "CLDO_CRG"] pub cldo_crg : CldoCrg ,
#[doc = "SDMA"] pub sdma : Sdma ,
#[doc = "ULP_GPIO"] pub ulp_gpio : UlpGpio ,
#[doc = "RF_WB_CTL"] pub rf_wb_ctl : RfWbCtl ,
#[doc = "SHARE_MEM_CTL"] pub share_mem_ctl : ShareMemCtl ,
#[doc = "FAMA_REMAP"] pub fama_remap : FamaRemap , } impl Peripherals {
#[doc = r" Returns all the peripherals *once*."]
#[cfg (feature = "critical-section")]
#[inline] pub fn take () -> Option < Self > { critical_section :: with (| _ | { if unsafe { DEVICE_PERIPHERALS } { return None } Some (unsafe { Peripherals :: steal () }) }) }
#[doc = r" Unchecked version of `Peripherals::take`."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Each of the returned peripherals must be used at most once."]
#[inline] pub unsafe fn steal () -> Self { unsafe { DEVICE_PERIPHERALS = true } Peripherals { sys_ctl1 : unsafe { SysCtl1 :: steal () } , io_config : unsafe { IoConfig :: steal () } , gpio0 : unsafe { Gpio0 :: steal () } , gpio1 : unsafe { Gpio1 :: steal () } , gpio2 : unsafe { Gpio2 :: steal () } , uart0 : unsafe { Uart0 :: steal () } , uart1 : unsafe { Uart1 :: steal () } , uart2 : unsafe { Uart2 :: steal () } , i2c0 : unsafe { I2c0 :: steal () } , i2c1 : unsafe { I2c1 :: steal () } , pwm : unsafe { Pwm :: steal () } , dma : unsafe { Dma :: steal () } , sfc_cfg : unsafe { SfcCfg :: steal () } , spi0 : unsafe { Spi0 :: steal () } , spi1 : unsafe { Spi1 :: steal () } , i2s : unsafe { I2s :: steal () } , lsadc : unsafe { Lsadc :: steal () } , tsensor : unsafe { Tsensor :: steal () } , timer : unsafe { Timer :: steal () } , wdt : unsafe { Wdt :: steal () } , rtc : unsafe { Rtc :: steal () } , efuse : unsafe { Efuse :: steal () } , sys_ctl0 : unsafe { SysCtl0 :: steal () } , glb_ctl_m : unsafe { GlbCtlM :: steal () } , spacc : unsafe { Spacc :: steal () } , pke : unsafe { Pke :: steal () } , km : unsafe { Km :: steal () } , trng : unsafe { Trng :: steal () } , tcxo : unsafe { Tcxo :: steal () } , cldo_crg : unsafe { CldoCrg :: steal () } , sdma : unsafe { Sdma :: steal () } , ulp_gpio : unsafe { UlpGpio :: steal () } , rf_wb_ctl : unsafe { RfWbCtl :: steal () } , share_mem_ctl : unsafe { ShareMemCtl :: steal () } , fama_remap : unsafe { FamaRemap :: steal () } , } } }