Struct System 

pub struct System<'d> {
    pub sys_ctl0: SysCtl0<'d>,
    pub glb_ctl_m: GlbCtlM<'d>,
    pub cldo_crg: CldoCrg<'d>,
}

System control handle.

Holds the SYS_CTL0, GLB_CTL_M, and CLDO_CRG peripherals for clock and reset configuration.

Fields

sys_ctl0: SysCtl0<'d>

glb_ctl_m: GlbCtlM<'d>

cldo_crg: CldoCrg<'d>

Implementations

impl<'d> System<'d>

pub fn new( sys_ctl0: SysCtl0<'d>, glb_ctl_m: GlbCtlM<'d>, cldo_crg: CldoCrg<'d>, ) -> Self

impl System<'_>

pub fn reset_reason(&self) -> ResetReason

Read (and clear) the last reset reason from SYS_RST_RECORD_0.

Decodes the WS63 reset-history record (reboot_port_get_rst_reason): watchdog takes precedence over software over power-on. The matched bit is cleared via SYS_DIAG_CLR_1 so the next boot reports its own cause. Reasons this SoC’s record does not distinguish (ExternalPin, BrownOut) are never returned here. An empty record reads back as ResetReason::Unknown.

pub fn software_reset(&self) -> !

Trigger a full software reset of the chip and never return.

Sets the chip-reset enable bit (bit 2) of GLB_CTL_M + 0x110, the same register reboot_port_reboot_chip uses. The CPU is reset before the following spin loop completes.

pub fn software_reset_cpu(&self) -> !

Trigger a software reset and never return.

WS63’s porting layer exposes only a whole-chip reset, so this is an alias of software_reset.