{
"tests": [
{
"name": "value_picorv32_signals_1000",
"category": "value",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
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v32_core.is_lb_lh_lw_lbu_lhu,testbench.top.uut.picorv32_core.is_lbu_lhu_lw,testbench.top.uut.picorv32_core.is_lui_auipc_jal,testbench.top.uut.picorv32_core.is_lui_auipc_jal_jalr_addi_add_sub,testbench.top.uut.picorv32_core.is_rdcycle_rdcycleh_rdinstr_rdinstrh,testbench.top.uut.picorv32_core.is_sb_sh_sw,testbench.top.uut.picorv32_core.is_sll_srl_sra,testbench.top.uut.picorv32_core.is_slli_srli_srai,testbench.top.uut.picorv32_core.is_slti_blt_slt,testbench.top.uut.picorv32_core.is_sltiu_bltu_sltu,testbench.top.uut.picorv32_core.last_mem_valid,testbench.top.uut.picorv32_core.latched_branch,testbench.top.uut.picorv32_core.latched_compr,testbench.top.uut.picorv32_core.latched_is_lb,testbench.top.uut.picorv32_core.latched_is_lh,testbench.top.uut.picorv32_core.latched_is_lu,testbench.top.uut.picorv32_core.latched_rd,testbench.top.uut.picorv32_core.latched_stalu,testbench.top.uut.picorv32_core.latched_store,testbench.top.uut.picorv32_core.latched_trace,testbench.top.uut.picorv32_core.launch_next_insn,testbench.top.uut.picorv32_core.mem_16bit_buffer,testbench.top.uut.picorv32_core.mem_addr,testbench.top.uut.picorv32_core.mem_busy,testbench.top.uut.picorv32_core.mem_do_prefetch,testbench.top.uut.picorv32_core.mem_do_rdata,testbench.top.uut.picorv32_core.mem_do_rinst,testbench.top.uut.picorv32_core.mem_do_wdata,testbench.top.uut.picorv32_core.mem_done,testbench.top.uut.picorv32_core.mem_instr,testbench.top.uut.picorv32_core.mem_la_addr,testbench.top.uut.picorv32_core.mem_la_firstword,testbench.top.uut.picorv32_core.mem_la_firstword_reg,testbench.top.uut.picorv32_core.mem_la_firstword_xfer,testbench.top.uut.picorv32_core.mem_la_read,testbench.top.uut.picorv32_core.mem_la_secondword,testbench.top.uut.picorv32_core.mem_la_use_prefetched_high_word,testbench.top.uut.picorv32_core.mem_la_wdata,testbench.top.uut.picorv32_core.mem_la_write,testbench.top.uut.picorv32_core.mem_la_wstrb,testbench.top.uut.picorv32_core.mem_rdata,testbench.top.uut.picorv32_core.mem_rdata_latched,testbench.top.uut.picorv32_core.mem_rdata_latched_noshuffle,testbench.top.uut.picorv32_core.mem_rdata_q,testbench.top.uut.picorv32_core.mem_rdata_word,testbench.top.uut.picorv32_core.mem_ready,testbench.top.uut.picorv32_core.mem_state,testbench.top.uut.picorv32_core.mem_valid,testbench.top.uut.picorv32_core.mem_wdata,testbench.top.uut.picorv32_core.mem_wordsize,testbench.top.uut.picorv32_core.mem_wstrb,testbench.top.uut.picorv32_core.mem_xfer,testbench.top.uut.picorv32_core.new_ascii_instr,testbench.top.uut.picorv32_core.next_insn_opcode,testbench.top.uut.picorv32_core.next_irq_pending,testbench.top.uut.picorv32_core.next_pc,testbench.top.uut.picorv32_core.pcpi_div_rd,testbench.top.uut.picorv32_core.pcpi_div_ready,testbench.top.uut.picorv32_core.pcpi_div_wait,testbench.top.uut.picorv32_core.pcpi_div_wr,testbench.top.uut.picorv32_core.pcpi_insn,testbench.top.uut.picorv32_core.pcpi_int_rd,testbench.top.uut.picorv32_core.pcpi_int_ready,testbench.top.uut.picorv32_core.pcpi_int_wait,testbench.top.uut.picorv32_core.pcpi_int_wr,testbench.top.uut.picorv32_core.pcpi_mul_rd,testbench.top.uut.picorv32_core.pcpi_mul_ready,testbench.top.uut.picorv32_core.pcpi_mul_wait,testbench.top.uut.picorv32_core.pcpi_mul_wr,testbench.top.uut.picorv32_core.pcpi_rd,testbench.top.uut.picorv32_core.pcpi_ready,testbench.top.uut.picorv32_core.pcpi_rs1,testbench.top.uut.picorv32_core.pcpi_rs2,testbench.top.uut.picorv32_core.pcpi_timeout,testbench.top.uut.picorv32_core.pcpi_timeout_counter,testbench.top.uut.picorv32_core.pcpi_valid,testbench.top.uut.picorv32_core.pcpi_wait,testbench.top.uut.picorv32_core.pcpi_wr,testbench.top.uut.picorv32_core.prefetched_high_word,testbench.top.uut.picorv32_core.q_ascii_instr,testbench.top.uut.picorv32_core.q_insn_imm,testbench.top.uut.picorv32_core.q_insn_opcode,testbench.top.uut.picorv32_core.q_insn_rd,testbench.top.uut.picorv32_core.q_insn_rs1,testbench.top.uut.picorv32_core.q_insn_rs2,testbench.top.uut.picorv32_core.reg_next_pc,testbench.top.uut.picorv32_core.reg_op1,testbench.top.uut.picorv32_core.reg_op2,testbench.top.uut.picorv32_core.reg_out,testbench.top.uut.picorv32_core.reg_pc,testbench.top.uut.picorv32_core.reg_sh,testbench.top.uut.picorv32_core.resetn,testbench.top.uut.picorv32_core.set_mem_do_rdata,testbench.top.uut.picorv32_core.set_mem_do_rinst,testbench.top.uut.picorv32_core.set_mem_do_wdata,testbench.top.uut.picorv32_core.timer,testbench.top.uut.picorv32_core.trace_data,testbench.top.uut.picorv32_core.trace_valid,testbench.top.uut.picorv32_core.trap,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.clk,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.i,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_any_mul,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_any_mulh,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_mul,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_mulh,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_mulhsu,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_mulhu,testbench.top.uut.picorv3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picorv32_core.mem_rdata_word,testbench.top.uut.picorv32_core.mem_ready,testbench.top.uut.picorv32_core.mem_state,testbench.top.uut.picorv32_core.mem_valid,testbench.top.uut.picorv32_core.mem_wdata,testbench.top.uut.picorv32_core.mem_wordsize,testbench.top.uut.picorv32_core.mem_wstrb,testbench.top.uut.picorv32_core.mem_xfer,testbench.top.uut.picorv32_core.new_ascii_instr,testbench.top.uut.picorv32_core.next_insn_opcode,testbench.top.uut.picorv32_core.next_irq_pending,testbench.top.uut.picorv32_core.next_pc,testbench.top.uut.picorv32_core.pcpi_div_rd,testbench.top.uut.picorv32_core.pcpi_div_ready,testbench.top.uut.picorv32_core.pcpi_div_wait,testbench.top.uut.picorv32_core.pcpi_div_wr,testbench.top.uut.picorv32_core.pcpi_insn,testbench.top.uut.picorv32_core.pcpi_int_rd,testbench.top.uut.picorv32_core.pcpi_int_ready,testbench.top.uut.picorv32_core.pcpi_int_wait,testbench.top.uut.picorv32_core.pcpi_int_wr,testbench.top.uut.picorv32_core.pcpi_mul_rd,testbench.top.uut.picorv32_core.pcpi_mul_ready,testbench.top.uut.picorv32_core.pcpi_mul_wait,testbench.top.uut.picorv32_core.pcpi_mul_wr,testbench.top.uut.picorv32_core.pcpi_rd,testbench.top.uut.picorv32_core.pcpi_ready,testbench.top.uut.picorv32_core.pcpi_rs1,testbench.top.uut.picorv32_core.pcpi_rs2,testbench.top.uut.picorv32_core.pcpi_timeout,testbench.top.uut.picorv32_core.pcpi_timeout_counter,testbench.top.uut.picorv32_core.pcpi_valid,testbench.top.uut.picorv32_core.pcpi_wait,testbench.top.uut.picorv32_core.pcpi_wr,testbench.top.uut.picorv32_core.prefetched_high_word,testbench.top.uut.picorv32_core.q_ascii_instr,testbench.top.uut.picorv32_core.q_insn_imm,testbench.top.uut.picorv32_core.q_insn_opcode,testbench.top.uut.picorv32_core.q_insn_rd,testbench.top.uut.picorv32_core.q_insn_rs1,testbench.top.uut.picorv32_core.q_insn_rs2,testbench.top.uut.picorv32_core.reg_next_pc,testbench.top.uut.picorv32_core.reg_op1,testbench.top.uut.picorv32_core.reg_op2,testbench.top.uut.picorv32_core.reg_out,testbench.top.uut.picorv32_core.reg_pc,testbench.top.uut.picorv32_core.reg_sh,testbench.top.uut.picorv32_core.resetn,testbench.top.uut.picorv32_core.set_mem_do_rdata,testbench.top.uut.picorv32_core.set_mem_do_rinst,testbench.top.uut.picorv32_core.set_mem_do_wdata,testbench.top.uut.picorv32_core.timer,testbench.top.uut.picorv32_core.trace_data,testbench.top.uut.picorv32_core.trace_valid,testbench.top.uut.picorv32_core.trap,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.clk,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.i,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_any_mul,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_any_mulh,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_mul,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_mulh,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_mulhsu,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_mulhu,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_rs1_signed,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.instr_rs2_signed,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.j,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.mul_counter,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.mul_finish,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.mul_start,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.mul_waiting,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.next_rd,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.next_rdt,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.next_rdx,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.next_rs1,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.next_rs2,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.pcpi_insn,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.pcpi_rd,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.pcpi_ready,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.pcpi_rs1,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.pcpi_rs2,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.pcpi_valid,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.pcpi_wait,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.pcpi_wait_q,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.pcpi_wr,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.rd,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.rdx,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.resetn,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.rs1,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.rs2,testbench.top.uut.picorv32_core.genblk1.pcpi_mul.this_rs2,testbench.top.uut.picorv32_core.genblk2.pcpi_div.clk,testbench.top.uut.picorv32_core.genblk2.pcpi_div.dividend,testbench.top.uut.picorv32_core.genblk2.pcpi_div.divisor,testbench.top.uut.picorv32_core.genblk2.pcpi_div.instr_any_div_rem,testbench.top.uut.picorv32_core.genblk2.pcpi_div.instr_div,testbench.top.uut.picorv32_core.genblk2.pcpi_div.instr_divu,testbench.top.uut.picorv32_core.genblk2.pcpi_div.instr_rem,testbench.top.uut.picorv32_core.genblk2.pcpi_div.instr_remu,testbench.top.uut.picorv32_core.genblk2.pcpi_div.outsign,testbench.top.uut.picorv32_core.genblk2.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"--at",
"2455330000ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"signal_count": 1000
}
},
{
"name": "value_picorv32_signals_100",
"category": "value",
"runs": 10,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file,testbench.top.irq,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready,testbench.top.mem_axi_bvalid,testbench.top.mem_axi_rdata,testbench.top.mem_axi_rready,testbench.top.mem_axi_rvalid,testbench.top.mem_axi_wdata,testbench.top.mem_axi_wready,testbench.top.mem_axi_wstrb,testbench.top.mem_axi_wvalid,testbench.top.resetn,testbench.top.tests_passed,testbench.top.trace_data,testbench.top.trace_valid,testbench.top.trap,testbench.top.mem.async_axi_transaction,testbench.top.mem.axi_test,testbench.top.mem.clk,testbench.top.mem.delay_axi_transaction,testbench.top.mem.fast_axi_transaction,testbench.top.mem.fast_raddr,testbench.top.mem.fast_waddr,testbench.top.mem.fast_wdata,testbench.top.mem.latched_raddr,testbench.top.mem.latched_raddr_en,testbench.top.mem.latched_rinsn,testbench.top.mem.latched_waddr,testbench.top.mem.latched_waddr_en,testbench.top.mem.latched_wdata,testbench.top.mem.latched_wdata_en,testbench.top.mem.latched_wstrb,testbench.top.mem.mem_axi_araddr,testbench.top.mem.mem_axi_arprot,testbench.top.mem.mem_axi_arready,testbench.top.mem.mem_axi_arvalid,testbench.top.mem.mem_axi_awaddr,testbench.top.mem.mem_axi_awprot,testbench.top.mem.mem_axi_awready,testbench.top.mem.mem_axi_awvalid,testbench.top.mem.mem_axi_bready,testbench.top.mem.mem_axi_bvalid,testbench.top.mem.mem_axi_rdata,testbench.top.mem.mem_axi_rready,testbench.top.mem.mem_axi_rvalid,testbench.top.mem.mem_axi_wdata,testbench.top.mem.mem_axi_wready,testbench.top.mem.mem_axi_wstrb,testbench.top.mem.mem_axi_wvalid,testbench.top.mem.tests_passed,testbench.top.mem.verbose,testbench.top.mem.xorshift64_state,testbench.top.uut.clk,testbench.top.uut.eoi,testbench.top.uut.irq,testbench.top.uut.mem_addr,testbench.top.uut.mem_axi_araddr,testbench.top.uut.mem_axi_arprot,testbench.top.uut.mem_axi_arready,testbench.top.uut.mem_axi_arvalid,testbench.top.uut.mem_axi_awaddr,testbench.top.uut.mem_axi_awprot,testbench.top.uut.mem_axi_awready,testbench.top.uut.mem_axi_awvalid,testbench.top.uut.mem_axi_bready,testbench.top.uut.mem_axi_bvalid,testbench.top.uut.mem_axi_rdata,testbench.top.uut.mem_axi_rready,testbench.top.uut.mem_axi_rvalid,testbench.top.uut.mem_axi_wdata,testbench.top.uut.mem_axi_wready,testbench.top.uut.mem_axi_wstrb,testbench.top.uut.mem_axi_wvalid,testbench.top.uut.mem_instr,testbench.top.uut.mem_rdata,testbench.top.uut.mem_ready,testbench.top.uut.mem_valid,testbench.top.uut.mem_wdata,testbench.top.uut.mem_wstrb,testbench.top.uut.pcpi_insn,testbench.top.uut.pcpi_rd,testbench.top.uut.pcpi_ready,testbench.top.uut.pcpi_rs1",
"--at",
"2455330000ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"signal_count": 100
}
},
{
"name": "value_picorv32_signals_10",
"category": "value",
"runs": 15,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file",
"--at",
"2455330000ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"signal_count": 10
}
},
{
"name": "value_picorv32_signals_1",
"category": "value",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk",
"--at",
"2455330000ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"signal_count": 1
}
},
{
"name": "value_scr1_signals_1000",
"category": "value",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.$unit.SCR1_ARCH_MTVEC_BASE,TOP.$unit.SCR1_ARCH_RST_VECTOR,TOP.$unit.SCR1_CSR_ADDR_CYCLE,TOP.$unit.SCR1_CSR_ADDR_CYCLEH,TOP.$unit.SCR1_CSR_ADDR_HDU_MBASE,TOP.$unit.SCR1_CSR_ADDR_HDU_MSPAN,TOP.$unit.SCR1_CSR_ADDR_HPMCOUNTERH_MASK,TOP.$unit.SCR1_CSR_ADDR_HPMCOUNTER_MASK,TOP.$unit.SCR1_CSR_ADDR_INSTRET,TOP.$unit.SCR1_CSR_ADDR_INSTRETH,TOP.$unit.SCR1_CSR_ADDR_IPIC_BASE,TOP.$unit.SCR1_CSR_ADDR_IPIC_CICSR,TOP.$unit.SCR1_CSR_ADDR_IPIC_CISV,TOP.$unit.SCR1_CSR_ADDR_IPIC_EOI,TOP.$unit.SCR1_CSR_ADDR_IPIC_ICSR,TOP.$unit.SCR1_CSR_ADDR_IPIC_IDX,TOP.$unit.SCR1_CSR_ADDR_IPIC_IPR,TOP.$unit.SCR1_CSR_ADDR_IPIC_ISVR,TOP.$unit.SCR1_CSR_ADDR_IPIC_SOI,TOP.$unit.SCR1_CSR_ADDR_MARCHID,TOP.$unit.SCR1_CSR_ADDR_MCAUSE,TOP.$unit.SCR1_CSR_ADDR_MCOUNTEN,TOP.$unit.SCR1_CSR_ADDR_MCYCLE,TOP.$unit.SCR1_CSR_ADDR_MCYCLEH,TOP.$unit.SCR1_CSR_ADDR_MEPC,TOP.$unit.SCR1_CSR_ADDR_MHARTID,TOP.$unit.SCR1_CSR_ADDR_MHPMCOUNTERH_MASK,TOP.$unit.SCR1_CSR_ADDR_MHPMCOUNTER_MASK,TOP.$unit.SCR1_CSR_ADDR_MHPMEVENT_MASK,TOP.$unit.SCR1_CSR_ADDR_MIE,TOP.$unit.SCR1_CSR_ADDR_MIMPID,TOP.$unit.SCR1_CSR_ADDR_MINSTRET,TOP.$unit.SCR1_CSR_ADDR_MINSTRETH,TOP.$unit.SCR1_CSR_ADDR_MIP,TOP.$unit.SCR1_CSR_ADDR_MISA,TOP.$unit.SCR1_CSR_ADDR_MSCRATCH,TOP.$unit.SCR1_CSR_ADDR_MSTATUS,TOP.$unit.SCR1_CSR_ADDR_MTVAL,TOP.$unit.SCR1_CSR_ADDR_MTVEC,TOP.$unit.SCR1_CSR_ADDR_MVENDORID,TOP.$unit.SCR1_CSR_ADDR_TDU_MBASE,TOP.$unit.SCR1_CSR_ADDR_TDU_MSPAN,TOP.$unit.SCR1_CSR_ADDR_TDU_OFFS_TDATA1,TOP.$unit.SCR1_CSR_ADDR_TDU_OFFS_TDATA2,TOP.$unit.SCR1_CSR_ADDR_TDU_OFFS_TINFO,TOP.$unit.SCR1_CSR_ADDR_TDU_OFFS_TSELECT,TOP.$unit.SCR1_CSR_ADDR_TDU_OFFS_W,TOP.$unit.SCR1_CSR_ADDR_TDU_TDATA1,TOP.$unit.SCR1_CSR_ADDR_TDU_TDATA2,TOP.$unit.SCR1_CSR_ADDR_TDU_TINFO,TOP.$unit.SCR1_CSR_ADDR_TDU_TSELECT,TOP.$unit.SCR1_CSR_ADDR_TIME,TOP.$unit.SCR1_CSR_ADDR_TIMEH,TOP.$unit.SCR1_CSR_ADDR_WIDTH,TOP.$unit.SCR1_CSR_CMD_ALL_NUM_E,TOP.$unit.SCR1_CSR_CMD_WIDTH_E,TOP.$unit.SCR1_CSR_COUNTERS_WIDTH,TOP.$unit.SCR1_CSR_MARCHID,TOP.$unit.SCR1_CSR_MCOUNTEN_CY_OFFSET,TOP.$unit.SCR1_CSR_MCOUNTEN_IR_OFFSET,TOP.$unit.SCR1_CSR_MIE_MEIE_OFFSET,TOP.$unit.SCR1_CSR_MIE_MEIE_RST_VAL,TOP.$unit.SCR1_CSR_MIE_MSIE_OFFSET,TOP.$unit.SCR1_CSR_MIE_MSIE_RST_VAL,TOP.$unit.SCR1_CSR_MIE_MTIE_OFFSET,TOP.$unit.SCR1_CSR_MIE_MTIE_RST_VAL,TOP.$unit.SCR1_CSR_MIMPID,TOP.$unit.SCR1_CSR_MIP_MEIP_RST_VAL,TOP.$unit.SCR1_CSR_MIP_MSIP_RST_VAL,TOP.$unit.SCR1_CSR_MIP_MTIP_RST_VAL,TOP.$unit.SCR1_CSR_MISA,TOP.$unit.SCR1_CSR_MSTATUS_MIE_OFFSET,TOP.$unit.SCR1_CSR_MSTATUS_MIE_RST_VAL,TOP.$unit.SCR1_CSR_MSTATUS_MPIE_OFFSET,TOP.$unit.SCR1_CSR_MSTATUS_MPIE_RST_VAL,TOP.$unit.SCR1_CSR_MSTATUS_MPP,TOP.$unit.SCR1_CSR_MSTATUS_MPP_OFFSET,TOP.$unit.SCR1_CSR_MTVEC_BASE_RO_BITS,TOP.$unit.SCR1_CSR_MTVEC_BASE_RST_VAL,TOP.$unit.SCR1_CSR_MTVEC_BASE_VAL_BITS,TOP.$unit.SCR1_CSR_MTVEC_BASE_WR_RST_VAL,TOP.$unit.SCR1_CSR_MTVEC_BASE_ZERO_BITS,TOP.$unit.SCR1_CSR_MTVEC_MODE_DIRECT,TOP.$unit.SCR1_CSR_MTVEC_MODE_VECTORED,TOP.$unit.SCR1_CSR_MVENDORID,TOP.$unit.SCR1_CSR_OP_ALL_NUM_E,TOP.$unit.SCR1_CSR_OP_WIDTH_E,TOP.$unit.SCR1_DBG_ABSTRACTAUTO,TOP.$unit.SCR1_DBG_ABSTRACTCS,TOP.$unit.SCR1_DBG_ABSTRACTCS_BUSY,TOP.$unit.SCR1_DBG_ABSTRACTCS_CMDERR_HI,TOP.$unit.SCR1_DBG_ABSTRACTCS_CMDERR_LO,TOP.$unit.SCR1_DBG_ABSTRACTCS_CMDERR_WDTH,TOP.$unit.SCR1_DBG_ABSTRACTCS_DATACOUNT_HI,TOP.$unit.SCR1_DBG_ABSTRACTCS_DATACOUNT_LO,TOP.$unit.SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_HI,TOP.$unit.SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_LO,TOP.$unit.SCR1_DBG_ABSTRACTCS_RESERVEDA_HI,TOP.$unit.SCR1_DBG_ABSTRACTCS_RESERVEDA_LO,TOP.$unit.SCR1_DBG_ABSTRACTCS_RESERVEDB,TOP.$unit.SCR1_DBG_ABSTRACTCS_RESERVEDC_HI,TOP.$unit.SCR1_DBG_ABSTRACTCS_RESERVEDC_LO,TOP.$unit.SCR1_DBG_ABSTRACTCS_RESERVEDD_HI,TOP.$unit.SCR1_DBG_ABSTRACTCS_RESERVEDD_LO,TOP.$unit.SCR1_DBG_COMMAND,TOP.$unit.SCR1_DBG_COMMAND_ACCESSMEM_AAMPOSTINC,TOP.$unit.SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_HI,TOP.$unit.SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_LO,TOP.$unit.SCR1_DBG_COMMAND_ACCESSMEM_AAMVIRTUAL,TOP.$unit.SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_HI,TOP.$unit.SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_LO,TOP.$unit.SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_HI,TOP.$unit.SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_LO,TOP.$unit.SCR1_DBG_COMMAND_ACCESSMEM_WRITE,TOP.$unit.SCR1_DBG_COMMAND_ACCESSREG_POSTEXEC,TOP.$unit.SCR1_DBG_COMMAND_ACCESSREG_REGNO_HI,TOP.$unit.SCR1_DBG_COMMAND_ACCESSREG_REGNO_LO,TOP.$unit.SCR1_DBG_COMMAND_ACCESSREG_RESERVEDA,TOP.$unit.SCR1_DBG_COMMAND_ACCESSREG_RESERVEDB,TOP.$unit.SCR1_DBG_COMMAND_ACCESSREG_SIZE_HI,TOP.$unit.SCR1_DBG_COMMAND_ACCESSREG_SIZE_LO,TOP.$unit.SCR1_DBG_COMMAND_ACCESSREG_SIZE_WDTH,TOP.$unit.SCR1_DBG_COMMAND_ACCESSREG_TRANSFER,TOP.$unit.SCR1_DBG_COMMAND_ACCESSREG_WRITE,TOP.$unit.SCR1_DBG_COMMAND_TYPE_HI,TOP.$unit.SCR1_DBG_COMMAND_TYPE_LO,TOP.$unit.SCR1_DBG_COMMAND_TYPE_WDTH,TOP.$unit.SCR1_DBG_DATA0,TOP.$unit.SCR1_DBG_DATA1,TOP.$unit.SCR1_DBG_DMCONTROL,TOP.$unit.SCR1_DBG_DMCONTROL_ACKHAVERESET,TOP.$unit.SCR1_DBG_DMCONTROL_DMACTIVE,TOP.$unit.SCR1_DBG_DMCONTROL_HALTREQ,TOP.$unit.SCR1_DBG_DMCONTROL_HARTRESET,TOP.$unit.SCR1_DBG_DMCONTROL_HARTSELHI_HI,TOP.$unit.SCR1_DBG_DMCONTROL_HARTSELHI_LO,TOP.$unit.SCR1_DBG_DMCONTROL_HARTSELLO_HI,TOP.$unit.SCR1_DBG_DMCONTROL_HARTSELLO_LO,TOP.$unit.SCR1_DBG_DMCONTROL_HASEL,TOP.$unit.SCR1_DBG_DMCONTROL_NDMRESET,TOP.$unit.SCR1_DBG_DMCONTROL_RESERVEDA_HI,TOP.$unit.SCR1_DBG_DMCONTROL_RESERVEDA_LO,TOP.$unit.SCR1_DBG_DMCONTROL_RESERVEDB,TOP.$unit.SCR1_DBG_DMCONTROL_RESUMEREQ,TOP.$unit.SCR1_DBG_DMI_ADDR_WIDTH,TOP.$unit.SCR1_DBG_DMI_CH_ID_WIDTH,TOP.$unit.SCR1_DBG_DMI_DATA_WIDTH,TOP.$unit.SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH,TOP.$unit.SCR1_DBG_DMI_DR_DTMCS_WIDTH,TOP.$unit.SCR1_DBG_DMI_OP_WIDTH,TOP.$unit.SCR1_DBG_DMSTATUS,TOP.$unit.SCR1_DBG_DMSTATUS_ALLHALTED,TOP.$unit.SCR1_DBG_DMSTATUS_ALLHAVERESET,TOP.$unit.SCR1_DBG_DMSTATUS_ALLNONEXISTENT,TOP.$unit.SCR1_DBG_DMSTATUS_ALLRESUMEACK,TOP.$unit.SCR1_DBG_DMSTATUS_ALLRUNNING,TOP.$unit.SCR1_DBG_DMSTATUS_ALLUNAVAIL,TOP.$unit.SCR1_DBG_DMSTATUS_ANYHALTED,TOP.$unit.SCR1_DBG_DMSTATUS_ANYHAVERESET,TOP.$unit.SCR1_DBG_DMSTATUS_ANYNONEXISTENT,TOP.$unit.SCR1_DBG_DMSTATUS_ANYRESUMEACK,TOP.$unit.SCR1_DBG_DMSTATUS_ANYRUNNING,TOP.$unit.SCR1_DBG_DMSTATUS_ANYUNAVAIL,TOP.$unit.SCR1_DBG_DMSTATUS_AUTHBUSY,TOP.$unit.SCR1_DBG_DMSTATUS_AUTHENTICATED,TOP.$unit.SCR1_DBG_DMSTATUS_DEVTREEVALID,TOP.$unit.SCR1_DBG_DMSTATUS_IMPEBREAK,TOP.$unit.SCR1_DBG_DMSTATUS_RESERVEDA,TOP.$unit.SCR1_DBG_DMSTATUS_RESERVEDB_HI,TOP.$unit.SCR1_DBG_DMSTATUS_RESERVEDB_LO,TOP.$unit.SCR1_DBG_DMSTATUS_RESERVEDC_HI,TOP.$unit.SCR1_DBG_DMSTATUS_RESERVEDC_LO,TOP.$unit.SCR1_DBG_DMSTATUS_VERSION_HI,TOP.$unit.SCR1_DBG_DMSTATUS_VERSION_LO,TOP.$unit.SCR1_DBG_HALTSUM0,TOP.$unit.SCR1_DBG_HARTINFO,TOP.$unit.SCR1_DBG_HARTINFO_DATAACCESS,TOP.$unit.SCR1_DBG_HARTINFO_DATAADDR_HI,TOP.$unit.SCR1_DBG_HARTINFO_DATAADDR_LO,TOP.$unit.SCR1_DBG_HARTINFO_DATASIZE_HI,TOP.$unit.SCR1_DBG_HARTINFO_DATASIZE_LO,TOP.$unit.SCR1_DBG_HARTINFO_NSCRATCH_HI,TOP.$unit.SCR1_DBG_HARTINFO_NSCRATCH_LO,TOP.$unit.SCR1_DBG_HARTINFO_RESERVEDA_HI,TOP.$unit.SCR1_DBG_HARTINFO_RESERVEDA_LO,TOP.$unit.SCR1_DBG_HARTINFO_RESERVEDB_HI,TOP.$unit.SCR1_DBG_HARTINFO_RESERVEDB_LO,TOP.$unit.SCR1_DBG_PROGBUF0,TOP.$unit.SCR1_DBG_PROGBUF1,TOP.$unit.SCR1_DBG_PROGBUF2,TOP.$unit.SCR1_DBG_PROGBUF3,TOP.$unit.SCR1_DBG_PROGBUF4,TOP.$unit.SCR1_DBG_PROGBUF5,TOP.$unit.SCR1_EXC_CODE_IRQ_M_EXTERNAL,TOP.$unit.SCR1_EXC_CODE_IRQ_M_SOFTWARE,TOP.$unit.SCR1_EXC_CODE_IRQ_M_TIMER,TOP.$unit.SCR1_EXC_CODE_RESET,TOP.$unit.SCR1_EXC_CODE_WIDTH_E,TOP.$unit.SCR1_GPR_FIELD_WIDTH,TOP.$unit.SCR1_HDU_CORE_INSTR_WIDTH,TOP.$unit.SCR1_HDU_DATA_REG_WIDTH,TOP.$unit.SCR1_HDU_DBGCSR_ADDR_DCSR,TOP.$unit.SCR1_HDU_DBGCSR_ADDR_DPC,TOP.$unit.SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,TOP.$unit.SCR1_HDU_DBGCSR_ADDR_DSCRATCH1,TOP.$unit.SCR1_HDU_DBGCSR_OFFS_DCSR,TOP.$unit.SCR1_HDU_DBGCSR_OFFS_DPC,TOP.$unit.SCR1_HDU_DBGCSR_OFFS_DSCRATCH0,TOP.$unit.SCR1_HDU_DBGCSR_OFFS_DSCRATCH1,TOP.$unit.SCR1_HDU_DEBUGCSR_ADDR_SPAN,TOP.$unit.SCR1_HDU_DEBUGCSR_ADDR_WIDTH,TOP.$unit.SCR1_HDU_DEBUGCSR_DCSR_XDEBUGVER,TOP.$unit.SCR1_HDU_PBUF_ADDR_SPAN,TOP.$unit.SCR1_HDU_PBUF_ADDR_WIDTH,TOP.$unit.SCR1_IALU_CMD_ALL_NUM_E,TOP.$unit.SCR1_IALU_CMD_WIDTH_E,TOP.$unit.SCR1_IALU_OP_ALL_NUM_E,TOP.$unit.SCR1_IALU_OP_WIDTH_E,TOP.$unit.SCR1_IPIC_CICSR,TOP.$unit.SCR1_IPIC_CISV,TOP.$unit.SCR1_IPIC_EOI,TOP.$unit.SCR1_IPIC_ICSR,TOP.$unit.SCR1_IPIC_ICSR_IE,TOP.$unit.SCR1_IPIC_ICSR_IM,TOP.$unit.SCR1_IPIC_ICSR_INV,TOP.$unit.SCR1_IPIC_ICSR_IP,TOP.$unit.SCR1_IPIC_ICSR_IS,TOP.$unit.SCR1_IPIC_ICSR_LN_LSB,TOP.$unit.SCR1_IPIC_ICSR_LN_MSB,TOP.$unit.SCR1_IPIC_ICSR_PRV_LSB,TOP.$unit.SCR1_IPIC_ICSR_PRV_MSB,TOP.$unit.SCR1_IPIC_IDX,TOP.$unit.SCR1_IPIC_IPR,TOP.$unit.SCR1_IPIC_ISVR,TOP.$unit.SCR1_IPIC_PRV_M,TOP.$unit.SCR1_IPIC_SOI,TOP.$unit.SCR1_IRQ_IDX_WIDTH,TOP.$unit.SCR1_IRQ_LINES_NUM,TOP.$unit.SCR1_IRQ_LINES_WIDTH,TOP.$unit.SCR1_IRQ_VECT_NUM,TOP.$unit.SCR1_IRQ_VECT_WIDTH,TOP.$unit.SCR1_IRQ_VOID_VECT_NUM,TOP.$unit.SCR1_LSU_CMD_ALL_NUM_E,TOP.$unit.SCR1_LSU_CMD_WIDTH_E,TOP.$unit.SCR1_MISA_MXL_32,TOP.$unit.SCR1_MTVEC_BASE_WR_BITS,TOP.$unit.SCR1_RD_WB_ALL_NUM_E,TOP.$unit.SCR1_RD_WB_WIDTH_E,TOP.$unit.SCR1_RST_VECTOR,TOP.$unit.SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH,TOP.$unit.SCR1_SCU_DR_SYSCTRL_DATA_WIDTH,TOP.$unit.SCR1_SCU_DR_SYSCTRL_OP_WIDTH,TOP.$unit.SCR1_SIM_EXIT_ADDR,TOP.$unit.SCR1_SIM_EXT_IRQ_ADDR,TOP.$unit.SCR1_SIM_PRINT_ADDR,TOP.$unit.SCR1_SIM_SOFT_IRQ_ADDR,TOP.$unit.SCR1_SUM2_OP_ALL_NUM_E,TOP.$unit.SCR1_SUM2_OP_WIDTH_E,TOP.$unit.SCR1_TAP_BLD_ID_VALUE,TOP.$unit.SCR1_TAP_DR_BLD_ID_WIDTH,TOP.$unit.SCR1_TAP_DR_BYPASS_WIDTH,TOP.$unit.SCR1_TAP_DR_IDCODE_WIDTH,TOP.$unit.SCR1_TAP_INSTRUCTION_WIDTH,TOP.$unit.SCR1_TAP_STATE_WIDTH,TOP.$unit.SCR1_TCM_ADDR_MASK,TOP.$unit.SCR1_TCM_ADDR_PATTERN,TOP.$unit.SCR1_TDU_ADDR_W,TOP.$unit.SCR1_TDU_ALLTRIG_NUM,TOP.$unit.SCR1_TDU_DATA_W,TOP.$unit.SCR1_TDU_ICOUNT_ACTION_HI,TOP.$unit.SCR1_TDU_ICOUNT_ACTION_LO,TOP.$unit.SCR1_TDU_ICOUNT_COUNT_HI,TOP.$unit.SCR1_TDU_ICOUNT_COUNT_LO,TOP.$unit.SCR1_TDU_ICOUNT_DMODE,TOP.$unit.SCR1_TDU_ICOUNT_HIT,TOP.$unit.SCR1_TDU_ICOUNT_M,TOP.$unit.SCR1_TDU_ICOUNT_RESERVEDA,TOP.$unit.SCR1_TDU_ICOUNT_RESERVEDA_VAL,TOP.$unit.SCR1_TDU_ICOUNT_RESERVEDB_HI,TOP.$unit.SCR1_TDU_ICOUNT_RESERVEDB_LO,TOP.$unit.SCR1_TDU_ICOUNT_RESERVEDB_VAL,TOP.$unit.SCR1_TDU_ICOUNT_S,TOP.$unit.SCR1_TDU_ICOUNT_TYPE_VAL,TOP.$unit.SCR1_TDU_ICOUNT_U,TOP.$unit.SCR1_TDU_MCONTROL_ACTION_HI,TOP.$unit.SCR1_TDU_MCONTROL_ACTION_LO,TOP.$unit.SCR1_TDU_MCONTROL_CHAIN,TOP.$unit.SCR1_TDU_MCONTROL_EXECUTE,TOP.$unit.SCR1_TDU_MCONTROL_HIT,TOP.$unit.SCR1_TDU_MCONTROL_LOAD,TOP.$unit.SCR1_TDU_MCONTROL_M,TOP.$unit.SCR1_TDU_MCONTROL_MASKMAX_HI,TOP.$unit.SCR1_TDU_MCONTROL_MASKMAX_LO,TOP.$unit.SCR1_TDU_MCONTROL_MASKMAX_VAL,TOP.$unit.SCR1_TDU_MCONTROL_MATCH_HI,TOP.$unit.SCR1_TDU_MCONTROL_MATCH_LO,TOP.$unit.SCR1_TDU_MCONTROL_RESERVEDA,TOP.$unit.SCR1_TDU_MCONTROL_RESERVEDA_VAL,TOP.$unit.SCR1_TDU_MCONTROL_RESERVEDB_HI,TOP.$unit.SCR1_TDU_MCONTROL_RESERVEDB_LO,TOP.$unit.SCR1_TDU_MCONTROL_S,TOP.$unit.SCR1_TDU_MCONTROL_SELECT,TOP.$unit.SCR1_TDU_MCONTROL_SELECT_VAL,TOP.$unit.SCR1_TDU_MCONTROL_STORE,TOP.$unit.SCR1_TDU_MCONTROL_TIMING,TOP.$unit.SCR1_TDU_MCONTROL_TIMING_VAL,TOP.$unit.SCR1_TDU_MCONTROL_TYPE_VAL,TOP.$unit.SCR1_TDU_MCONTROL_U,TOP.$unit.SCR1_TDU_MTRIG_NUM,TOP.$unit.SCR1_TDU_TDATA1_DMODE,TOP.$unit.SCR1_TDU_TDATA1_DMODE_VAL,TOP.$unit.SCR1_TDU_TDATA1_TYPE_HI,TOP.$unit.SCR1_TDU_TDATA1_TYPE_LO,TOP.$unit.SCR1_TDU_TRIG_NUM,TOP.$unit.SCR1_TIMER_ADDR_MASK,TOP.$unit.SCR1_TIMER_ADDR_PATTERN,TOP.scr1_top_tb_axi.ADDR_START,TOP.scr1_top_tb_axi.ADDR_TRAP_DEFAULT,TOP.scr1_top_tb_axi.ADDR_TRAP_VECTOR,TOP.scr1_top_tb_axi.ARCH,TOP.scr1_top_tb_axi.COMPLIANCE,TOP.scr1_top_tb_axi.SCR1_MEM_SIZE,TOP.scr1_top_tb_axi.TIMEOUT,TOP.scr1_top_tb_axi.clk,TOP.scr1_top_tb_axi.dmem_req_ack_stall,TOP.scr1_top_tb_axi.f_info,TOP.scr1_top_tb_axi.f_results,TOP.scr1_top_tb_axi.fuse_mhartid,TOP.scr1_top_tb_axi.get_filename__Vstatic__i,TOP.scr1_top_tb_axi.get_filename__Vstatic__j,TOP.scr1_top_tb_axi.get_filename__Vstatic__res,TOP.scr1_top_tb_axi.get_ref_filename__Vstatic__i,TOP.scr1_top_tb_axi.get_ref_filename__Vstatic__j,TOP.scr1_top_tb_axi.get_ref_filename__Vstatic__pattern_arch,TOP.scr1_top_tb_axi.get_ref_filename__Vstatic__pattern_compliance,TOP.scr1_top_tb_axi.get_ref_filename__Vstatic__res,TOP.scr1_top_tb_axi.identify_test__Vstatic__pattern_arch,TOP.scr1_top_tb_axi.identify_test__Vstatic__pattern_compliance,TOP.scr1_top_tb_axi.identify_test__Vstatic__res,TOP.scr1_top_tb_axi.imem_req_ack_stall,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arcache,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.io_axi_dmem_awcache,TOP.scr1_top_tb_axi.io_axi_dmem_awid,TOP.scr1_top_tb_axi.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.io_axi_dmem_awready,TOP.scr1_top_tb_axi.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.io_axi_dmem_bid,TOP.scr1_top_tb_axi.io_axi_dmem_bready,TOP.scr1_top_tb_axi.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.io_axi_dmem_buser,TOP.scr1_top_tb_axi.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.io_axi_dmem_rid,TOP.scr1_top_tb_axi.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.io_axi_dmem_rready,TOP.scr1_top_tb_axi.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.io_axi_dmem_wready,TOP.scr1_top_tb_axi.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.io_axi_imem_araddr,TOP.scr1_top_tb_axi.io_axi_imem_arburst,TOP.scr1_top_tb_axi.io_axi_imem_arcache,TOP.scr1_top_tb_axi.io_axi_imem_arid,TOP.scr1_top_tb_axi.io_axi_imem_arlen,TOP.scr1_top_tb_axi.io_axi_imem_arlock,TOP.scr1_top_tb_axi.io_axi_imem_arprot,TOP.scr1_top_tb_axi.io_axi_imem_arqos,TOP.scr1_top_tb_axi.io_axi_imem_arready,TOP.scr1_top_tb_axi.io_axi_imem_arregion,TOP.scr1_top_tb_axi.io_axi_imem_arsize,TOP.scr1_top_tb_axi.io_axi_imem_aruser,TOP.scr1_top_tb_axi.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.io_axi_imem_awburst,TOP.scr1_top_tb_axi.io_axi_imem_awcache,TOP.scr1_top_tb_axi.io_axi_imem_awid,TOP.scr1_top_tb_axi.io_axi_imem_awlen,TOP.scr1_top_tb_axi.io_axi_imem_awlock,TOP.scr1_top_tb_axi.io_axi_imem_awprot,TOP.scr1_top_tb_axi.io_axi_imem_awqos,TOP.scr1_top_tb_axi.io_axi_imem_awready,TOP.scr1_top_tb_axi.io_axi_imem_awregion,TOP.scr1_top_tb_axi.io_axi_imem_awsize,TOP.scr1_top_tb_axi.io_axi_imem_awuser,TOP.scr1_top_tb_axi.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.io_axi_imem_bid,TOP.scr1_top_tb_axi.io_axi_imem_bready,TOP.scr1_top_tb_axi.io_axi_imem_bresp,TOP.scr1_top_tb_axi.io_axi_imem_buser,TOP.scr1_top_tb_axi.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.io_axi_imem_rdata,TOP.scr1_top_tb_axi.io_axi_imem_rid,TOP.scr1_top_tb_axi.io_axi_imem_rlast,TOP.scr1_top_tb_axi.io_axi_imem_rready,TOP.scr1_top_tb_axi.io_axi_imem_rresp,TOP.scr1_top_tb_axi.io_axi_imem_ruser,TOP.scr1_top_tb_axi.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.io_axi_imem_wdata,TOP.scr1_top_tb_axi.io_axi_imem_wlast,TOP.scr1_top_tb_axi.io_axi_imem_wready,TOP.scr1_top_tb_axi.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.io_axi_imem_wuser,TOP.scr1_top_tb_axi.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.irq_lines,TOP.scr1_top_tb_axi.remove_trailing_whitespaces__Vstatic__i,TOP.scr1_top_tb_axi.rst_cnt,TOP.scr1_top_tb_axi.rst_init,TOP.scr1_top_tb_axi.rst_n,TOP.scr1_top_tb_axi.rtc_clk,TOP.scr1_top_tb_axi.soft_irq,TOP.scr1_top_tb_axi.tck,TOP.scr1_top_tb_axi.tdi,TOP.scr1_top_tb_axi.tdo,TOP.scr1_top_tb_axi.tdo_en,TOP.scr1_top_tb_axi.test_file,TOP.scr1_top_tb_axi.test_running,TOP.scr1_top_tb_axi.tests_passed,TOP.scr1_top_tb_axi.tests_total,TOP.scr1_top_tb_axi.tms,TOP.scr1_top_tb_axi.trst_n,TOP.scr1_top_tb_axi.watchdogs_cnt,TOP.scr1_top_tb_axi.i_memory_tb.N_IF,TOP.scr1_top_tb_axi.i_memory_tb.SIZE,TOP.scr1_top_tb_axi.i_memory_tb.W_ADR,TOP.scr1_top_tb_axi.i_memory_tb.W_DATA,TOP.scr1_top_tb_axi.i_memory_tb.W_ID,TOP.scr1_top_tb_axi.i_memory_tb.arready,TOP.scr1_top_tb_axi.i_memory_tb.arvalid,TOP.scr1_top_tb_axi.i_memory_tb.awready,TOP.scr1_top_tb_axi.i_memory_tb.awvalid,TOP.scr1_top_tb_axi.i_memory_tb.bready,TOP.scr1_top_tb_axi.i_memory_tb.bvalid,TOP.scr1_top_tb_axi.i_memory_tb.clk,TOP.scr1_top_tb_axi.i_memory_tb.irq_lines,TOP.scr1_top_tb_axi.i_memory_tb.irq_lines_reg,TOP.scr1_top_tb_axi.i_memory_tb.rlast,TOP.scr1_top_tb_axi.i_memory_tb.rready,TOP.scr1_top_tb_axi.i_memory_tb.rst_n,TOP.scr1_top_tb_axi.i_memory_tb.rvalid,TOP.scr1_top_tb_axi.i_memory_tb.soft_irq,TOP.scr1_top_tb_axi.i_memory_tb.soft_irq_reg,TOP.scr1_top_tb_axi.i_memory_tb.test_file,TOP.scr1_top_tb_axi.i_memory_tb.test_file_init,TOP.scr1_top_tb_axi.i_memory_tb.wlast,TOP.scr1_top_tb_axi.i_memory_tb.wready,TOP.scr1_top_tb_axi.i_memory_tb.wvalid,TOP.scr1_top_tb_axi.i_memory_tb.araddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.araddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[0],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[1],TOP.scr1_top_tb_axi.i_memory_tb.arid.[0],TOP.scr1_top_tb_axi.i_memory_tb.arid.[1],TOP.scr1_top_tb_axi.i_memory_tb.arlen.[0],TOP.scr1_top_tb_axi.i_memory_tb.arlen.[1],TOP.scr1_top_tb_axi.i_memory_tb.arsize.[0],TOP.scr1_top_tb_axi.i_memory_tb.arsize.[1],TOP.scr1_top_tb_axi.i_memory_tb.awaddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.awaddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.awaddr_hold.[0],TOP.scr1_top_tb_axi.i_memory_tb.awaddr_hold.[1],TOP.scr1_top_tb_axi.i_memory_tb.awid.[0],TOP.scr1_top_tb_axi.i_memory_tb.awid.[1],TOP.scr1_top_tb_axi.i_memory_tb.awlen.[0],TOP.scr1_top_tb_axi.i_memory_tb.awlen.[1],TOP.scr1_top_tb_axi.i_memory_tb.awsize.[0],TOP.scr1_top_tb_axi.i_memory_tb.awsize.[1],TOP.scr1_top_tb_axi.i_memory_tb.awsize_hold.[0],TOP.scr1_top_tb_axi.i_memory_tb.awsize_hold.[1],TOP.scr1_top_tb_axi.i_memory_tb.bid.[0],TOP.scr1_top_tb_axi.i_memory_tb.bid.[1],TOP.scr1_top_tb_axi.i_memory_tb.bresp.[0],TOP.scr1_top_tb_axi.i_memory_tb.bresp.[1],TOP.scr1_top_tb_axi.i_memory_tb.rdata.[0],TOP.scr1_top_tb_axi.i_memory_tb.rdata.[1],TOP.scr1_top_tb_axi.i_memory_tb.rid.[0],TOP.scr1_top_tb_axi.i_memory_tb.rid.[1],TOP.scr1_top_tb_axi.i_memory_tb.rresp.[0],TOP.scr1_top_tb_axi.i_memory_tb.rresp.[1],TOP.scr1_top_tb_axi.i_memory_tb.wdata.[0],TOP.scr1_top_tb_axi.i_memory_tb.wdata.[1],TOP.scr1_top_tb_axi.i_memory_tb.wstrb.[0],TOP.scr1_top_tb_axi.i_memory_tb.wstrb.[1],TOP.scr1_top_tb_axi.i_top.SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM,TOP.scr1_top_tb_axi.i_top.axi_dmem_addr,TOP.scr1_top_tb_axi.i_top.axi_dmem_cmd,TOP.scr1_top_tb_axi.i_top.axi_dmem_idle,TOP.scr1_top_tb_axi.i_top.axi_dmem_rdata,TOP.scr1_top_tb_axi.i_top.axi_dmem_req,TOP.scr1_top_tb_axi.i_top.axi_dmem_req_ack,TOP.scr1_top_tb_axi.i_top.axi_dmem_resp,TOP.scr1_top_tb_axi.i_top.axi_dmem_wdata,TOP.scr1_top_tb_axi.i_top.axi_dmem_width,TOP.scr1_top_tb_axi.i_top.axi_imem_addr,TOP.scr1_top_tb_axi.i_top.axi_imem_cmd,TOP.scr1_top_tb_axi.i_top.axi_imem_idle,TOP.scr1_top_tb_axi.i_top.axi_imem_rdata,TOP.scr1_top_tb_axi.i_top.axi_imem_req,TOP.scr1_top_tb_axi.i_top.axi_imem_req_ack,TOP.scr1_top_tb_axi.i_top.axi_imem_resp,TOP.scr1_top_tb_axi.i_top.axi_reinit,TOP.scr1_top_tb_axi.i_top.axi_rst_n,TOP.scr1_top_tb_axi.i_top.clk,TOP.scr1_top_tb_axi.i_top.core_dmem_addr,TOP.scr1_top_tb_axi.i_top.core_dmem_cmd,TOP.scr1_top_tb_axi.i_top.core_dmem_rdata,TOP.scr1_top_tb_axi.i_top.core_dmem_req,TOP.scr1_top_tb_axi.i_top.core_dmem_req_ack,TOP.scr1_top_tb_axi.i_top.core_dmem_resp,TOP.scr1_top_tb_axi.i_top.core_dmem_wdata,TOP.scr1_top_tb_axi.i_top.core_dmem_width,TOP.scr1_top_tb_axi.i_top.core_imem_addr,TOP.scr1_top_tb_axi.i_top.core_imem_cmd,TOP.scr1_top_tb_axi.i_top.core_imem_rdata,TOP.scr1_top_tb_axi.i_top.core_imem_req,TOP.scr1_top_tb_axi.i_top.core_imem_req_ack,TOP.scr1_top_tb_axi.i_top.core_imem_resp,TOP.scr1_top_tb_axi.i_top.core_rst_n_local,TOP.scr1_top_tb_axi.i_top.cpu_rst_n,TOP.scr1_top_tb_axi.i_top.cpu_rst_n_sync,TOP.scr1_top_tb_axi.i_top.fuse_idcode,TOP.scr1_top_tb_axi.i_top.fuse_mhartid,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arcache,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arid,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arready,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awcache,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awid,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awready,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_bid,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_bready,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_buser,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_rid,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_rready,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_wready,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.i_top.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.i_top.io_axi_imem_araddr,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arburst,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arcache,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arid,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arlen,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arlock,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arprot,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arqos,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arready,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arregion,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arsize,TOP.scr1_top_tb_axi.i_top.io_axi_imem_aruser,TOP.scr1_top_tb_axi.i_top.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awburst,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awcache,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awid,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awlen,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awlock,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awprot,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awqos,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awready,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awregion,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awsize,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awuser,TOP.scr1_top_tb_axi.i_top.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.i_top.io_axi_imem_bid,TOP.scr1_top_tb_axi.i_top.io_axi_imem_bready,TOP.scr1_top_tb_axi.i_top.io_axi_imem_bresp,TOP.scr1_top_tb_axi.i_top.io_axi_imem_buser,TOP.scr1_top_tb_axi.i_top.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.i_top.io_axi_imem_rdata,TOP.scr1_top_tb_axi.i_top.io_axi_imem_rid,TOP.scr1_top_tb_axi.i_top.io_axi_imem_rlast,TOP.scr1_top_tb_axi.i_top.io_axi_imem_rready,TOP.scr1_top_tb_axi.i_top.io_axi_imem_rresp,TOP.scr1_top_tb_axi.i_top.io_axi_imem_ruser,TOP.scr1_top_tb_axi.i_top.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.i_top.io_axi_imem_wdata,TOP.scr1_top_tb_axi.i_top.io_axi_imem_wlast,TOP.scr1_top_tb_axi.i_top.io_axi_imem_wready,TOP.scr1_top_tb_axi.i_top.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.i_top.io_axi_imem_wuser,TOP.scr1_top_tb_axi.i_top.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.i_top.irq_lines,TOP.scr1_top_tb_axi.i_top.pwrup_rst_n,TOP.scr1_top_tb_axi.i_top.pwrup_rst_n_sync,TOP.scr1_top_tb_axi.i_top.rst_n,TOP.scr1_top_tb_axi.i_top.rst_n_sync,TOP.scr1_top_tb_axi.i_top.rtc_clk,TOP.scr1_top_tb_axi.i_top.soft_irq,TOP.scr1_top_tb_axi.i_top.sys_rdc_qlfy_o,TOP.scr1_top_tb_axi.i_top.sys_rst_n_o,TOP.scr1_top_tb_axi.i_top.tapc_trst_n,TOP.scr1_top_tb_axi.i_top.tck,TOP.scr1_top_tb_axi.i_top.tcm_dmem_addr,TOP.scr1_top_tb_axi.i_top.tcm_dmem_cmd,TOP.scr1_top_tb_axi.i_top.tcm_dmem_rdata,TOP.scr1_top_tb_axi.i_top.tcm_dmem_req,TOP.scr1_top_tb_axi.i_top.tcm_dmem_req_ack,TOP.scr1_top_tb_axi.i_top.tcm_dmem_resp,TOP.scr1_top_tb_axi.i_top.tcm_dmem_wdata,TOP.scr1_top_tb_axi.i_top.tcm_dmem_width,TOP.scr1_top_tb_axi.i_top.tcm_imem_addr,TOP.scr1_top_tb_axi.i_top.tcm_imem_cmd,TOP.scr1_top_tb_axi.i_top.tcm_imem_rdata,TOP.scr1_top_tb_axi.i_top.tcm_imem_req,TOP.scr1_top_tb_axi.i_top.tcm_imem_req_ack,TOP.scr1_top_tb_axi.i_top.tcm_imem_resp,TOP.scr1_top_tb_axi.i_top.tdi,TOP.scr1_top_tb_axi.i_top.tdo,TOP.scr1_top_tb_axi.i_top.tdo_en,TOP.scr1_top_tb_axi.i_top.test_mode,TOP.scr1_top_tb_axi.i_top.test_rst_n,TOP.scr1_top_tb_axi.i_top.timer_dmem_addr,TOP.scr1_top_tb_axi.i_top.timer_dmem_cmd,TOP.scr1_top_tb_axi.i_top.timer_dmem_rdata,TOP.scr1_top_tb_axi.i_top.timer_dmem_req,TOP.scr1_top_tb_axi.i_top.timer_dmem_req_ack,TOP.scr1_top_tb_axi.i_top.timer_dmem_resp,TOP.scr1_top_tb_axi.i_top.timer_dmem_wdata,TOP.scr1_top_tb_axi.i_top.timer_dmem_width,TOP.scr1_top_tb_axi.i_top.timer_irq,TOP.scr1_top_tb_axi.i_top.timer_val,TOP.scr1_top_tb_axi.i_top.tms,TOP.scr1_top_tb_axi.i_top.trst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.SCR1_CORE_TOP_RST_SYNC_STAGES_NUM,TOP.scr1_top_tb_axi.i_top.i_core_top.clk,TOP.scr1_top_tb_axi.i_top.i_core_top.core2dm_rdc_qlfy,TOP.scr1_top_tb_axi.i_top.i_core_top.core2dmem_addr_o,TOP.scr1_top_tb_axi.i_top.i_core_top.core2dmem_cmd_o,TOP.scr1_top_tb_axi.i_top.i_core_top.core2dmem_req_o,TOP.scr1_top_tb_axi.i_top.i_core_top.core2dmem_wdata_o,TOP.scr1_top_tb_axi.i_top.i_core_top.core2dmem_width_o,TOP.scr1_top_tb_axi.i_top.i_core_top.core2hdu_rdc_qlfy,TOP.scr1_top_tb_axi.i_top.i_core_top.core2imem_addr_o,TOP.scr1_top_tb_axi.i_top.i_core_top.core2imem_cmd_o,TOP.scr1_top_tb_axi.i_top.i_core_top.core2imem_req_o,TOP.scr1_top_tb_axi.i_top.i_core_top.core_fuse_mhartid_i,TOP.scr1_top_tb_axi.i_top.i_core_top.core_irq_lines_i,TOP.scr1_top_tb_axi.i_top.i_core_top.core_irq_mtimer_i,TOP.scr1_top_tb_axi.i_top.i_core_top.core_irq_soft_i,TOP.scr1_top_tb_axi.i_top.i_core_top.core_mtimer_val_i,TOP.scr1_top_tb_axi.i_top.i_core_top.core_rdc_qlfy_o,TOP.scr1_top_tb_axi.i_top.i_core_top.core_rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.core_rst_n_o,TOP.scr1_top_tb_axi.i_top.i_core_top.core_rst_n_status_sync,TOP.scr1_top_tb_axi.i_top.i_core_top.core_rst_status,TOP.scr1_top_tb_axi.i_top.i_core_top.cpu_rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.cpu_rst_n_sync,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_active,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_cmd,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_cmd_rcode,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_cmd_req,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_cmd_resp,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_cmd_resp_qlfy,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_dreg_fail,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_dreg_rdata,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_dreg_req,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_dreg_req_qlfy,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_dreg_resp,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_dreg_wdata,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_dreg_wr,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_hart_event,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_hart_event_qlfy,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_pbuf_addr,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_pbuf_addr_qlfy,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_pbuf_instr,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_pc_sample,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_pc_sample_qlfy,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.dmem2core_rdata_i,TOP.scr1_top_tb_axi.i_top.i_core_top.dmem2core_req_ack_i,TOP.scr1_top_tb_axi.i_top.i_core_top.dmem2core_resp_i,TOP.scr1_top_tb_axi.i_top.i_core_top.dmi_addr,TOP.scr1_top_tb_axi.i_top.i_core_top.dmi_rdata,TOP.scr1_top_tb_axi.i_top.i_core_top.dmi_req,TOP.scr1_top_tb_axi.i_top.i_core_top.dmi_resp,TOP.scr1_top_tb_axi.i_top.i_core_top.dmi_wdata,TOP.scr1_top_tb_axi.i_top.i_core_top.dmi_wr,TOP.scr1_top_tb_axi.i_top.i_core_top.hart_rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.hdu2dm_rdc_qlfy,TOP.scr1_top_tb_axi.i_top.i_core_top.hdu_rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.imem2core_rdata_i,TOP.scr1_top_tb_axi.i_top.i_core_top.imem2core_req_ack_i,TOP.scr1_top_tb_axi.i_top.i_core_top.imem2core_resp_i,TOP.scr1_top_tb_axi.i_top.i_core_top.ndm_rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.pwrup_rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.pwrup_rst_n_sync,TOP.scr1_top_tb_axi.i_top.i_core_top.rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.rst_n_sync,TOP.scr1_top_tb_axi.i_top.i_core_top.sys_rdc_qlfy_o,TOP.scr1_top_tb_axi.i_top.i_core_top.sys_rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.sys_rst_n_o,TOP.scr1_top_tb_axi.i_top.i_core_top.sys_rst_status,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_ch_tdo,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_capture,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_capture_tapout,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_id,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_id_tapout,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_sel,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_sel_tapout,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_shift,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_shift_tapout,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_tdi,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_tdi_tapout,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_tdo,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_tdo_tapin,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_update,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_dmi_ch_update_tapout,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_fuse_idcode_i,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_scu_ch_sel,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_scu_ch_sel_tapout,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_scu_ch_tdo,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_tck,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_tdi,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_tdo,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_tdo_en,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_tms,TOP.scr1_top_tb_axi.i_top.i_core_top.tapc_trst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.test_mode,TOP.scr1_top_tb_axi.i_top.i_core_top.test_rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_hart_status.dbg_state,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_hart_status.ebreak,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_hart_status.except,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_hart_status_qlfy.dbg_state,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_hart_status_qlfy.ebreak,TOP.scr1_top_tb_axi.i_top.i_core_top.dm_hart_status_qlfy.except,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABSTRACTCS_DATACOUNT,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABSTRACTCS_PROGBUFSIZE,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABSTRACTCS_RESERVEDA,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABSTRACTCS_RESERVEDB,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABSTRACTCS_RESERVEDC,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABSTRACTCS_RESERVEDD,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABS_CMD_HARTMEM,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABS_CMD_HARTREG,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABS_CMD_HARTREG_CSR,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABS_CMD_HARTREG_FPU,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABS_CMD_HARTREG_INT,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABS_CMD_HARTREG_INTFPU,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ABS_EXEC_EBREAK,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMCONTROL_HARTRESET,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMCONTROL_HARTSELHI,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMCONTROL_HARTSELLO,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMCONTROL_HASEL,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMCONTROL_RESERVEDA,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMCONTROL_RESERVEDB,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_ALLANYNONEXIST,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_ALLANYUNAVAIL,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_ALLUNAVAIL,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_ANYUNAVAIL,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_AUTHBUSY,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_AUTHENTICATED,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_DEVTREEVALID,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_IMPEBREAK,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_RESERVEDA,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_RESERVEDB,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_RESERVEDC,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.DMSTATUS_VERSION,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.HARTINFO_DATAACCESS,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.HARTINFO_DATAADDR,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.HARTINFO_DATASIZE,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.HARTINFO_NSCRATCH,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.HARTINFO_RESERVEDA,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.HARTINFO_RESERVEDB,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_FUNCT3_CSRRS,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_FUNCT3_CSRRW,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_FUNCT3_LBU,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_FUNCT3_LHU,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_FUNCT3_LW,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_FUNCT3_SB,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_FUNCT3_SH,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_FUNCT3_SW,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_OP_LOAD,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_OP_STORE,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.SCR1_OP_SYSTEM,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_autoexec_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_autoexec_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_csr_access_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_csr_ro,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_csr_ro_access_vd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_csr_rw_access_vd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_execprogbuf,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_execprogbuf_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_hartmem_vd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_hartreg_vd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_mem_access_vd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_memsize,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_memsize_vd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_memvalid,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_memwr,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_mprf_access_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_mprf_access_vd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_postexec_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_postexec_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_reg_access_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_regacs,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_regfile,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_regno,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_regno_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_regsize,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_regsize_vd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_regtype,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_regvalid,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_regwr,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_size_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_size_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_type,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_wr_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_cmd_wr_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_command_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_command_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_data0_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_data0_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_data1_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_data1_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_err_acc_busy_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_err_acc_busy_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_err_acc_busy_upd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_err_exc_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_err_exc_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_err_exc_upd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_exec_instr_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_exec_instr_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_exec_req_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_exec_req_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_fsm_csr_ro,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_fsm_err,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_fsm_exec,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_fsm_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_fsm_idle,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_fsm_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_fsm_use_addr,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_instr_mem_funct3,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_instr_rd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_instr_rs1,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_instr_rs2,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_progbuf0_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_progbuf1_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_progbuf2_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_progbuf3_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_progbuf4_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_progbuf5_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_reg_access_csr,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abs_reg_access_mprf,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abstractcs_busy,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abstractcs_cmderr_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abstractcs_cmderr_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abstractcs_ro_en,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.abstractcs_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.autoexec_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.clk,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.clk_en_abs,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.clk_en_dm,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.clk_en_dm_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.cmd_resp_ok,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.command_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.data0_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.data0_xreg_save,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.data1_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dhi_fsm_exec,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dhi_fsm_exec_halt,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dhi_fsm_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dhi_fsm_halt_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dhi_fsm_idle,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dhi_fsm_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dhi_fsm_resume_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dhi_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dhi_resp,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dhi_resp_exc,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dm2dmi_rdata_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dm2dmi_resp_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dm2pipe_active_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dm2pipe_cmd_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dm2pipe_cmd_req_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dm2pipe_dreg_fail_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dm2pipe_dreg_rdata_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dm2pipe_dreg_resp_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dm2pipe_pbuf_instr_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_ackhavereset_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_ackhavereset_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_dmactive_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_dmactive_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_haltreq_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_haltreq_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_ndmreset_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_ndmreset_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_resumereq_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_resumereq_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmcontrol_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi2dm_addr_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi2dm_req_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi2dm_wdata_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi2dm_wr_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_abstractauto,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_abstractcs,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_any,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_command,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_data0,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_data1,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_dmcontrol,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_progbuf0,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_progbuf1,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_progbuf2,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_progbuf3,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_progbuf4,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_req_progbuf5,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmi_rpt_command,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmstatus_allany_halted_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmstatus_allany_halted_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmstatus_allany_havereset_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmstatus_allany_havereset_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmstatus_allany_resumeack_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dmstatus_allany_resumeack_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.dreg_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.halt_req_vd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_cmd_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_cmd_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_cmd_req_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_cmd_req_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_pbuf_ebreak_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_pbuf_ebreak_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_rst_n_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_rst_unexp,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_state_dhalt,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_state_drun,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_state_reset,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.hart_state_run,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.havereset_skip_pwrup_ff,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.havereset_skip_pwrup_next,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.ndm_rst_n_o,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.pipe2dm_cmd_rcode_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.pipe2dm_cmd_resp_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.pipe2dm_dreg_req_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.pipe2dm_dreg_wdata_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.pipe2dm_dreg_wr_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.pipe2dm_hart_event_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.pipe2dm_pbuf_addr_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.pipe2dm_pc_sample_i,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.progbuf0_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.progbuf1_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.progbuf2_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.progbuf3_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.progbuf4_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.progbuf5_wr_req,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.resume_req_vd,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.rst_n,TOP.scr1_top_tb_axi.i_top.i_core_top.i_dm.soc2dm_fuse_mhartid_i",
"--at",
"940092ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "4M",
"signal_count": 1000
}
},
{
"name": "value_scr1_signals_100",
"category": "value",
"runs": 10,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.$unit.SCR1_ARCH_MTVEC_BASE,TOP.$unit.SCR1_ARCH_RST_VECTOR,TOP.$unit.SCR1_CSR_ADDR_CYCLE,TOP.$unit.SCR1_CSR_ADDR_CYCLEH,TOP.$unit.SCR1_CSR_ADDR_HDU_MBASE,TOP.$unit.SCR1_CSR_ADDR_HDU_MSPAN,TOP.$unit.SCR1_CSR_ADDR_HPMCOUNTERH_MASK,TOP.$unit.SCR1_CSR_ADDR_HPMCOUNTER_MASK,TOP.$unit.SCR1_CSR_ADDR_INSTRET,TOP.$unit.SCR1_CSR_ADDR_INSTRETH,TOP.$unit.SCR1_CSR_ADDR_IPIC_BASE,TOP.$unit.SCR1_CSR_ADDR_IPIC_CICSR,TOP.$unit.SCR1_CSR_ADDR_IPIC_CISV,TOP.$unit.SCR1_CSR_ADDR_IPIC_EOI,TOP.$unit.SCR1_CSR_ADDR_IPIC_ICSR,TOP.$unit.SCR1_CSR_ADDR_IPIC_IDX,TOP.$unit.SCR1_CSR_ADDR_IPIC_IPR,TOP.$unit.SCR1_CSR_ADDR_IPIC_ISVR,TOP.$unit.SCR1_CSR_ADDR_IPIC_SOI,TOP.$unit.SCR1_CSR_ADDR_MARCHID,TOP.$unit.SCR1_CSR_ADDR_MCAUSE,TOP.$unit.SCR1_CSR_ADDR_MCOUNTEN,TOP.$unit.SCR1_CSR_ADDR_MCYCLE,TOP.$unit.SCR1_CSR_ADDR_MCYCLEH,TOP.$unit.SCR1_CSR_ADDR_MEPC,TOP.$unit.SCR1_CSR_ADDR_MHARTID,TOP.$unit.SCR1_CSR_ADDR_MHPMCOUNTERH_MASK,TOP.$unit.SCR1_CSR_ADDR_MHPMCOUNTER_MASK,TOP.$unit.SCR1_CSR_ADDR_MHPMEVENT_MASK,TOP.$unit.SCR1_CSR_ADDR_MIE,TOP.$unit.SCR1_CSR_ADDR_MIMPID,TOP.$unit.SCR1_CSR_ADDR_MINSTRET,TOP.$unit.SCR1_CSR_ADDR_MINSTRETH,TOP.$unit.SCR1_CSR_ADDR_MIP,TOP.$unit.SCR1_CSR_ADDR_MISA,TOP.$unit.SCR1_CSR_ADDR_MSCRATCH,TOP.$unit.SCR1_CSR_ADDR_MSTATUS,TOP.$unit.SCR1_CSR_ADDR_MTVAL,TOP.$unit.SCR1_CSR_ADDR_MTVEC,TOP.$unit.SCR1_CSR_ADDR_MVENDORID,TOP.$unit.SCR1_CSR_ADDR_TDU_MBASE,TOP.$unit.SCR1_CSR_ADDR_TDU_MSPAN,TOP.$unit.SCR1_CSR_ADDR_TDU_OFFS_TDATA1,TOP.$unit.SCR1_CSR_ADDR_TDU_OFFS_TDATA2,TOP.$unit.SCR1_CSR_ADDR_TDU_OFFS_TINFO,TOP.$unit.SCR1_CSR_ADDR_TDU_OFFS_TSELECT,TOP.$unit.SCR1_CSR_ADDR_TDU_OFFS_W,TOP.$unit.SCR1_CSR_ADDR_TDU_TDATA1,TOP.$unit.SCR1_CSR_ADDR_TDU_TDATA2,TOP.$unit.SCR1_CSR_ADDR_TDU_TINFO,TOP.$unit.SCR1_CSR_ADDR_TDU_TSELECT,TOP.$unit.SCR1_CSR_ADDR_TIME,TOP.$unit.SCR1_CSR_ADDR_TIMEH,TOP.$unit.SCR1_CSR_ADDR_WIDTH,TOP.$unit.SCR1_CSR_CMD_ALL_NUM_E,TOP.$unit.SCR1_CSR_CMD_WIDTH_E,TOP.$unit.SCR1_CSR_COUNTERS_WIDTH,TOP.$unit.SCR1_CSR_MARCHID,TOP.$unit.SCR1_CSR_MCOUNTEN_CY_OFFSET,TOP.$unit.SCR1_CSR_MCOUNTEN_IR_OFFSET,TOP.$unit.SCR1_CSR_MIE_MEIE_OFFSET,TOP.$unit.SCR1_CSR_MIE_MEIE_RST_VAL,TOP.$unit.SCR1_CSR_MIE_MSIE_OFFSET,TOP.$unit.SCR1_CSR_MIE_MSIE_RST_VAL,TOP.$unit.SCR1_CSR_MIE_MTIE_OFFSET,TOP.$unit.SCR1_CSR_MIE_MTIE_RST_VAL,TOP.$unit.SCR1_CSR_MIMPID,TOP.$unit.SCR1_CSR_MIP_MEIP_RST_VAL,TOP.$unit.SCR1_CSR_MIP_MSIP_RST_VAL,TOP.$unit.SCR1_CSR_MIP_MTIP_RST_VAL,TOP.$unit.SCR1_CSR_MISA,TOP.$unit.SCR1_CSR_MSTATUS_MIE_OFFSET,TOP.$unit.SCR1_CSR_MSTATUS_MIE_RST_VAL,TOP.$unit.SCR1_CSR_MSTATUS_MPIE_OFFSET,TOP.$unit.SCR1_CSR_MSTATUS_MPIE_RST_VAL,TOP.$unit.SCR1_CSR_MSTATUS_MPP,TOP.$unit.SCR1_CSR_MSTATUS_MPP_OFFSET,TOP.$unit.SCR1_CSR_MTVEC_BASE_RO_BITS,TOP.$unit.SCR1_CSR_MTVEC_BASE_RST_VAL,TOP.$unit.SCR1_CSR_MTVEC_BASE_VAL_BITS,TOP.$unit.SCR1_CSR_MTVEC_BASE_WR_RST_VAL,TOP.$unit.SCR1_CSR_MTVEC_BASE_ZERO_BITS,TOP.$unit.SCR1_CSR_MTVEC_MODE_DIRECT,TOP.$unit.SCR1_CSR_MTVEC_MODE_VECTORED,TOP.$unit.SCR1_CSR_MVENDORID,TOP.$unit.SCR1_CSR_OP_ALL_NUM_E,TOP.$unit.SCR1_CSR_OP_WIDTH_E,TOP.$unit.SCR1_DBG_ABSTRACTAUTO,TOP.$unit.SCR1_DBG_ABSTRACTCS,TOP.$unit.SCR1_DBG_ABSTRACTCS_BUSY,TOP.$unit.SCR1_DBG_ABSTRACTCS_CMDERR_HI,TOP.$unit.SCR1_DBG_ABSTRACTCS_CMDERR_LO,TOP.$unit.SCR1_DBG_ABSTRACTCS_CMDERR_WDTH,TOP.$unit.SCR1_DBG_ABSTRACTCS_DATACOUNT_HI,TOP.$unit.SCR1_DBG_ABSTRACTCS_DATACOUNT_LO,TOP.$unit.SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_HI,TOP.$unit.SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_LO,TOP.$unit.SCR1_DBG_ABSTRACTCS_RESERVEDA_HI,TOP.$unit.SCR1_DBG_ABSTRACTCS_RESERVEDA_LO",
"--at",
"940092ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "4M",
"signal_count": 100
}
},
{
"name": "value_scr1_signals_10",
"category": "value",
"runs": 15,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.$unit.SCR1_ARCH_MTVEC_BASE,TOP.$unit.SCR1_ARCH_RST_VECTOR,TOP.$unit.SCR1_CSR_ADDR_CYCLE,TOP.$unit.SCR1_CSR_ADDR_CYCLEH,TOP.$unit.SCR1_CSR_ADDR_HDU_MBASE,TOP.$unit.SCR1_CSR_ADDR_HDU_MSPAN,TOP.$unit.SCR1_CSR_ADDR_HPMCOUNTERH_MASK,TOP.$unit.SCR1_CSR_ADDR_HPMCOUNTER_MASK,TOP.$unit.SCR1_CSR_ADDR_INSTRET",
"--at",
"940092ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "4M",
"signal_count": 10
}
},
{
"name": "value_scr1_signals_1",
"category": "value",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk",
"--at",
"940092ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "4M",
"signal_count": 1
}
},
{
"name": "value_chipyard_dualrocketconfig_dhrystone_signals_1000",
"category": "value",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
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iveAck_dmactiveAck.reset,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.clock,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.io_d,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.io_q,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.reset,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_0,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_1,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_2,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.en,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.en_latched,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.in,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.out,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.test_en,TOP.TestDriver.testHarness.chiptop0.iocell_clock_tap.o,TOP.TestDriver.testHarness.chiptop0.iocell_clock_tap.oe,TOP.TestDriver.testHarness.chiptop0.iocell_clock_tap.pad,TOP.TestDriver.testHarness.chiptop0.iocell_custom_boot.i,TOP.TestDriver.testHarness.chiptop0.iocell_custom_boot.ie,TOP.TestDriver.testHarness.chiptop0.iocell_custom_boot.pad,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TCK.i,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TCK.ie,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TCK.pad,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDI.i,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDI.ie,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDI.pad,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDO.o,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDO.oe,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDO.pad,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TMS.i,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TMS.ie,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TMS.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_clock_in.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_clock_in.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_clock_in.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_1.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_1.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_1.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_10.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_10.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_10.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_11.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_11.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_11.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_12.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_12.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_12.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_13.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_13.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_13.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_14.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_14.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_14.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_15.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_15.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_15.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_16.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_16.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_16.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_17.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_17.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_17.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_18.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_18.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_18.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_19.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_19.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_19.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_2.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_2.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_2.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_20.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_20.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_20.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_21.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_21.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_21.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_22.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_22.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_22.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_23.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_23.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_23.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_24.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_24.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_24.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_25.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_25.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_25.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_26.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_26.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_26.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_27.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_27.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_27.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_28.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_28.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_28.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_29.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_29.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_29.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_3.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_3.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_3.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_30.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_30.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_30.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_31.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_31.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_31.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_4.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_4.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_4.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_5.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_5.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_5.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_6.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_6.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_6.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_7.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_7.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_7.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_8.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_8.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_8.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_9.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_9.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_9.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_ready.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_ready.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_ready.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_valid.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_valid.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_valid.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_1.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_1.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_1.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_10.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_10.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_10.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_11.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_11.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_11.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_12.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_12.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_12.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_13.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_13.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_13.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_14.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_14.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_14.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_15.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_15.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_15.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_16.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_16.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_16.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_17.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_17.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_17.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_18.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_18.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_18.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_19.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_19.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_19.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_2.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_2.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_2.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_20.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_20.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_20.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_21.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_21.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_21.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_22.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_22.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_22.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_23.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_23.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_23.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_24.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_24.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_24.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_25.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_25.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_25.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_26.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_26.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_26.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_27.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_27.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_27.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_28.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_28.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_28.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_29.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_29.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_29.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_3.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_3.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_3.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_30.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_30.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_30.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_31.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_31.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_31.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_4.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_4.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_4.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_5.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_5.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_5.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_6.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_6.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_6.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_7.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_7.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_7.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_8.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_8.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_8.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_9.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_9.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_9.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_ready.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_ready.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_ready.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_valid.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_valid.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_valid.pad,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_rxd.i,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_rxd.ie,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_rxd.pad,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_txd.o,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_txd.oe,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_txd.pad,TOP.TestDriver.testHarness.chiptop0.system.auto_cbus_fixedClockNode_anon_out_clock,TOP.TestDriver.testHarness.chiptop0.system.auto_cbus_fixedClockNode_anon_out_reset,TOP.TestDriver.testHarness.chiptop0.system.auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock,TOP.TestDriver.testHarness.chiptop0.system.auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset,TOP.TestDriver.testHarness.chiptop0.system.auto_mbus_fixedClockNode_anon_out_clock,TOP.TestDriver.testHarness.chiptop0.system.clock_tap,TOP.TestDriver.testHarness.chiptop0.system.custom_boot,TOP.TestDriver.testHarness.chiptop0.system.debug_clock,TOP.TestDriver.testHarness.chiptop0.system.debug_dmactive,TOP.TestDriver.testHarness.chiptop0.system.debug_dmactiveAck,TOP.TestDriver.testHarness.chiptop0.system.debug_reset,TOP.TestDriver.testHarness.chiptop0.system.debug_systemjtag_jtag_TCK,TOP.TestDriver.testHarness.chiptop0.system.debug_systemjtag_jtag_TDI,TOP.TestDriver.testHarness.chiptop0.system.debug_systemjtag_jtag_TDO_data,TOP.TestDriver.testHarness.chiptop0.system.debug_systemjtag_jtag_TMS,TOP.TestDriver.testHarness.chiptop0.system.debug_systemjtag_reset,TOP.TestDriver.testHarness.chiptop0.system.int_rtc_tick,TOP.TestDriver.testHarness.chiptop0.system.int_rtc_tick_c_value,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.resetctrl_hartIsInReset_0,TOP.TestDriver.testHarness.chiptop0.system.resetctrl_hartIsInReset_1,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_clock_in,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_in_bits_phit,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_in_ready,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_in_valid,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_out_bits_phit,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_out_ready,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_out_valid,TOP.TestDriver.testHarness.chiptop0.system.uart_0_rxd,TOP.TestDriver.testHarness.chiptop0.system.uart_0_txd,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_cbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_cbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_clockTapNode_clock_tap_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_fbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_fbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_mbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_mbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_pbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_pbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_sbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_sbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_sbus_1_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_sbus_1_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_0_member_sbus_sbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_0_member_sbus_sbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_0_member_sbus_sbus_1_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_0_member_sbus_sbus_1_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_1_member_pbus_pbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_1_member_pbus_pbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_2_member_fbus_fbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_2_member_fbus_fbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_3_member_mbus_mbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_3_member_mbus_mbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_4_member_cbus_cbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_4_member_cbus_cbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_5_member_clockTapNode_clockTapNode_clock_tap_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_clock_in_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_clock_in_reset,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_denied,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_sink,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_denied,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_sink,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.a_first_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.a_first_counter,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.a_first_counter_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.a_set_wo_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_first_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_first_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_first_counter,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_first_counter_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_first_counter_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_release_ack,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.denied,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.inflight,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.inflight_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.inflight_opcodes,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.inflight_sizes,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.inflight_sizes_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_denied,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_sink,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_0_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_1_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_1_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_2_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_2_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_3_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_3_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_sub_1_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_sub_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_sub_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.opcode_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.param_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.same_cycle_resp,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.sink,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.size_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.source_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.watchdog,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.watchdog_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader.DEFAULT,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader.FORMAT,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader.WIDTH,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader.myplus,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader.out,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader_1.DEFAULT,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader_1.FORMAT,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader_1.WIDTH,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader_1.myplus,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader_1.out,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.unnamedblk1.i,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.do_deq,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.do_enq,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.empty,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.full,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_denied,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_sink,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_denied,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_sink,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.maybe_full,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ptr_match,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.wrap,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.wrap_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.R0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.R0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.R0_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.R0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.W0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.W0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.W0_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.W0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.Memory.[0],TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.Memory.[1],TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.unnamedblk1.i,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.unnamedblk1.unnamedblk2.j,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.do_deq,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.do_enq,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.empty,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.full,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.maybe_full,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ptr_match,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.wrap,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.wrap_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.R0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.R0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.R0_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.R0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.W0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.W0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.W0_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.W0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.Memory.[0],TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.Memory.[1],TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.unnamedblk1.i,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.unnamedblk1.unnamedblk2.j,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aFirst,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aFragnum,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.acknum,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.anonIn_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.anonIn_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.anonOut_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.dFirst,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.dFirst_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.dFirst_size_hi,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.dOrig,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.dToggle,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.drop,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.gennum,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.a_first_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.a_first_counter,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.a_first_counter_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.a_set_wo_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_first_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_first_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_first_counter,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_first_counter_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_first_counter_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_release_ack,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.inflight,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.inflight_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.inflight_opcodes,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.inflight_sizes,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.inflight_sizes_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_0_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_1_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_1_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_2_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_2_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_3_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_3_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_sub_1_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_sub_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_sub_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.opcode_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.same_cycle_resp,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.size_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.source_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.watchdog,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.watchdog_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader.DEFAULT,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader.FORMAT,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader.WIDTH,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader.myplus,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader.out,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_1.DEFAULT,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_1.FORMAT,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_1.WIDTH,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_1.myplus,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_1.out,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.unnamedblk1.i,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.full,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_valid_0,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_ready_0,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_full,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_repeat,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.unnamedblk1.i,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.REG,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.a_fire,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem_MPORT_1_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.nodeIn_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.nodeIn_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.ren,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.initvar,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_en_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_w_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_w_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_w_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_w_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.initvar,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_r_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_r_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_r_en_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_w_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_w_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_w_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_w_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.initvar,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_r_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_r_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_r_en_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_w_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_w_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_w_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_w_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.initvar,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_r_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_r_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_r_en_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_w_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_w_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_w_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_w_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.initvar,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.ram_RW_0_r_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.ram_RW_0_r_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.ram_RW_0_r_en_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.ram_RW_0_w_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.ram_RW_0_w_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.ram_RW_0_w_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.ram_RW_0_w_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5.RW0_clk",
"--at",
"803202750ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"signal_count": 1000
}
},
{
"name": "value_chipyard_dualrocketconfig_dhrystone_signals_100",
"category": "value",
"runs": 10,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.dump_start,TOP.TestDriver.failure,TOP.TestDriver.fsdbfile,TOP.TestDriver.max_cycles,TOP.TestDriver.printf_cond,TOP.TestDriver.rand_value,TOP.TestDriver.reason,TOP.TestDriver.reset,TOP.TestDriver.stderr,TOP.TestDriver.success,TOP.TestDriver.trace_count,TOP.TestDriver.vcdfile,TOP.TestDriver.vcdplusfile,TOP.TestDriver.verbose,TOP.TestDriver.testHarness.clock,TOP.TestDriver.testHarness.io_success,TOP.TestDriver.testHarness.reset,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.clock_en,TOP.TestDriver.testHarness.chiptop0.clock_tap,TOP.TestDriver.testHarness.chiptop0.clock_uncore,TOP.TestDriver.testHarness.chiptop0.custom_boot,TOP.TestDriver.testHarness.chiptop0.debug_reset,TOP.TestDriver.testHarness.chiptop0.jtag_TCK,TOP.TestDriver.testHarness.chiptop0.jtag_TDI,TOP.TestDriver.testHarness.chiptop0.jtag_TDO,TOP.TestDriver.testHarness.chiptop0.jtag_TMS,TOP.TestDriver.testHarness.chiptop0.reset_io,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_clock_in,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_in_bits_phit,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_in_ready,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_in_valid,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_out_bits_phit,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_out_ready,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_out_valid,TOP.TestDriver.testHarness.chiptop0.uart_0_rxd,TOP.TestDriver.testHarness.chiptop0.uart_0_txd,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.clock,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.io_d,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.io_q,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.reset,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.clock,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.io_d,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.io_q,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.reset,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.sync_0,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.sync_1,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.sync_2,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.clock,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.io_d,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.io_q,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.reset,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.clock,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.io_d,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.io_q,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.reset,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_0,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_1,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_2,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.en,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.en_latched,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.in",
"--at",
"803202750ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"signal_count": 100
}
},
{
"name": "value_chipyard_dualrocketconfig_dhrystone_signals_10",
"category": "value",
"runs": 15,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.dump_start,TOP.TestDriver.failure,TOP.TestDriver.fsdbfile,TOP.TestDriver.max_cycles,TOP.TestDriver.printf_cond,TOP.TestDriver.rand_value,TOP.TestDriver.reason,TOP.TestDriver.reset,TOP.TestDriver.stderr",
"--at",
"803202750ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"signal_count": 10
}
},
{
"name": "value_chipyard_dualrocketconfig_dhrystone_signals_1",
"category": "value",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock",
"--at",
"803202750ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"signal_count": 1
}
},
{
"name": "value_chipyard_clusteredrocketconfig_dhrystone_signals_1000",
"category": "value",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
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iveAck_dmactiveAck.reset,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.clock,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.io_d,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.io_q,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.reset,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_0,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_1,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_2,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.en,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.en_latched,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.in,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.out,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.test_en,TOP.TestDriver.testHarness.chiptop0.iocell_clock_tap.o,TOP.TestDriver.testHarness.chiptop0.iocell_clock_tap.oe,TOP.TestDriver.testHarness.chiptop0.iocell_clock_tap.pad,TOP.TestDriver.testHarness.chiptop0.iocell_custom_boot.i,TOP.TestDriver.testHarness.chiptop0.iocell_custom_boot.ie,TOP.TestDriver.testHarness.chiptop0.iocell_custom_boot.pad,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TCK.i,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TCK.ie,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TCK.pad,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDI.i,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDI.ie,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDI.pad,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDO.o,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDO.oe,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TDO.pad,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TMS.i,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TMS.ie,TOP.TestDriver.testHarness.chiptop0.iocell_jtag_TMS.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_clock_in.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_clock_in.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_clock_in.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_1.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_1.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_1.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_10.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_10.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_10.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_11.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_11.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_11.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_12.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_12.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_12.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_13.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_13.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_13.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_14.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_14.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_14.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_15.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_15.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_15.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_16.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_16.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_16.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_17.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_17.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_17.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_18.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_18.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_18.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_19.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_19.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_19.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_2.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_2.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_2.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_20.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_20.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_20.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_21.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_21.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_21.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_22.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_22.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_22.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_23.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_23.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_23.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_24.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_24.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_24.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_25.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_25.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_25.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_26.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_26.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_26.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_27.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_27.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_27.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_28.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_28.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_28.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_29.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_29.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_29.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_3.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_3.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_3.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_30.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_30.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_30.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_31.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_31.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_31.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_4.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_4.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_4.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_5.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_5.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_5.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_6.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_6.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_6.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_7.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_7.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_7.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_8.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_8.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_8.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_9.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_9.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_bits_phit_9.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_ready.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_ready.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_ready.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_valid.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_valid.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_in_valid.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_1.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_1.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_1.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_10.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_10.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_10.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_11.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_11.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_11.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_12.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_12.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_12.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_13.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_13.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_13.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_14.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_14.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_14.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_15.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_15.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_15.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_16.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_16.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_16.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_17.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_17.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_17.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_18.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_18.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_18.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_19.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_19.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_19.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_2.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_2.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_2.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_20.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_20.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_20.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_21.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_21.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_21.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_22.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_22.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_22.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_23.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_23.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_23.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_24.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_24.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_24.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_25.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_25.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_25.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_26.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_26.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_26.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_27.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_27.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_27.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_28.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_28.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_28.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_29.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_29.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_29.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_3.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_3.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_3.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_30.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_30.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_30.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_31.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_31.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_31.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_4.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_4.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_4.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_5.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_5.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_5.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_6.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_6.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_6.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_7.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_7.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_7.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_8.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_8.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_8.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_9.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_9.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_bits_phit_9.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_ready.i,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_ready.ie,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_ready.pad,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_valid.o,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_valid.oe,TOP.TestDriver.testHarness.chiptop0.iocell_serial_tl_0_out_valid.pad,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_rxd.i,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_rxd.ie,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_rxd.pad,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_txd.o,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_txd.oe,TOP.TestDriver.testHarness.chiptop0.iocell_uart_0_txd.pad,TOP.TestDriver.testHarness.chiptop0.system.auto_cbus_fixedClockNode_anon_out_clock,TOP.TestDriver.testHarness.chiptop0.system.auto_cbus_fixedClockNode_anon_out_reset,TOP.TestDriver.testHarness.chiptop0.system.auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock,TOP.TestDriver.testHarness.chiptop0.system.auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset,TOP.TestDriver.testHarness.chiptop0.system.auto_mbus_fixedClockNode_anon_out_clock,TOP.TestDriver.testHarness.chiptop0.system.clock_tap,TOP.TestDriver.testHarness.chiptop0.system.custom_boot,TOP.TestDriver.testHarness.chiptop0.system.debug_clock,TOP.TestDriver.testHarness.chiptop0.system.debug_dmactive,TOP.TestDriver.testHarness.chiptop0.system.debug_dmactiveAck,TOP.TestDriver.testHarness.chiptop0.system.debug_reset,TOP.TestDriver.testHarness.chiptop0.system.debug_systemjtag_jtag_TCK,TOP.TestDriver.testHarness.chiptop0.system.debug_systemjtag_jtag_TDI,TOP.TestDriver.testHarness.chiptop0.system.debug_systemjtag_jtag_TDO_data,TOP.TestDriver.testHarness.chiptop0.system.debug_systemjtag_jtag_TMS,TOP.TestDriver.testHarness.chiptop0.system.debug_systemjtag_reset,TOP.TestDriver.testHarness.chiptop0.system.int_rtc_tick,TOP.TestDriver.testHarness.chiptop0.system.int_rtc_tick_c_value,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.resetctrl_hartIsInReset_0,TOP.TestDriver.testHarness.chiptop0.system.resetctrl_hartIsInReset_1,TOP.TestDriver.testHarness.chiptop0.system.resetctrl_hartIsInReset_2,TOP.TestDriver.testHarness.chiptop0.system.resetctrl_hartIsInReset_3,TOP.TestDriver.testHarness.chiptop0.system.resetctrl_hartIsInReset_4,TOP.TestDriver.testHarness.chiptop0.system.resetctrl_hartIsInReset_5,TOP.TestDriver.testHarness.chiptop0.system.resetctrl_hartIsInReset_6,TOP.TestDriver.testHarness.chiptop0.system.resetctrl_hartIsInReset_7,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_clock_in,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_in_bits_phit,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_in_ready,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_in_valid,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_out_bits_phit,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_out_ready,TOP.TestDriver.testHarness.chiptop0.system.serial_tl_0_out_valid,TOP.TestDriver.testHarness.chiptop0.system.uart_0_rxd,TOP.TestDriver.testHarness.chiptop0.system.uart_0_txd,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_cbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_cbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_clockTapNode_clock_tap_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_csbus0_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_csbus0_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_csbus1_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_csbus1_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_fbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_fbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_mbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_mbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_pbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_pbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_sbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_sbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_sbus_1_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_in_member_allClocks_sbus_1_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_0_member_sbus_sbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_0_member_sbus_sbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_0_member_sbus_sbus_1_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_0_member_sbus_sbus_1_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_1_member_csbus0_csbus0_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_1_member_csbus0_csbus0_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_3_member_csbus1_csbus1_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_3_member_csbus1_csbus1_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_5_member_pbus_pbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_5_member_pbus_pbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_6_member_fbus_fbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_6_member_fbus_fbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_7_member_mbus_mbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_7_member_mbus_mbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_8_member_cbus_cbus_0_clock,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_8_member_cbus_cbus_0_reset,TOP.TestDriver.testHarness.chiptop0.system.aggregator.auto_out_9_member_clockTapNode_clockTapNode_clock_tap_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_clock_in_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_clock_in_reset,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_denied,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_sink,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.auto_xbar_anon_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_denied,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_sink,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.auto_out_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.a_first_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.a_first_counter,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.a_first_counter_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.a_set_wo_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_first_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_first_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_first_counter,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_first_counter_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_first_counter_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.d_release_ack,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.denied,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.inflight,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.inflight_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.inflight_opcodes,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.inflight_sizes,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.inflight_sizes_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_denied,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_sink,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.io_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_0_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_1_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_1_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_2_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_2_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_3_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_3_2,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_sub_1_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_sub_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.mask_sub_sub_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.opcode_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.param_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.same_cycle_resp,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.sink,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.size_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.source_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.watchdog,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.watchdog_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader.DEFAULT,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader.FORMAT,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader.WIDTH,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader.myplus,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader.out,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader_1.DEFAULT,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader_1.FORMAT,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader_1.WIDTH,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader_1.myplus,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.plusarg_reader_1.out,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.monitor.unnamedblk1.i,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.do_deq,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.do_enq,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.empty,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.full,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_denied,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_sink,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_deq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_denied,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_sink,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.io_enq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.maybe_full,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ptr_match,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.wrap,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.wrap_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.R0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.R0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.R0_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.R0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.W0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.W0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.W0_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.W0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.Memory.[0],TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.Memory.[1],TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.unnamedblk1.i,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeIn_d_q.ram_ext.unnamedblk1.unnamedblk2.j,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.do_deq,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.do_enq,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.empty,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.full,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_deq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.io_enq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.maybe_full,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ptr_match,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.wrap,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.wrap_1,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.R0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.R0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.R0_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.R0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.W0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.W0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.W0_data,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.W0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.Memory.[0],TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.Memory.[1],TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.unnamedblk1.i,TOP.TestDriver.testHarness.chiptop0.system.bank.buffer.nodeOut_a_q.ram_ext.unnamedblk1.unnamedblk2.j,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aFirst,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aFragnum,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.acknum,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.anonIn_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.anonIn_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.anonOut_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.auto_anon_out_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.dFirst,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.dFirst_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.dFirst_size_hi,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.dOrig,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.dToggle,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.drop,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.gennum,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.a_first_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.a_first_counter,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.a_first_counter_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.a_set_wo_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_first_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_first_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_first_counter,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_first_counter_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_first_counter_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.d_release_ack,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.inflight,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.inflight_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.inflight_opcodes,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.inflight_sizes,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.inflight_sizes_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.io_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_0_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_1_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_1_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_2_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_2_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_3_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_3_2,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_sub_1_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_sub_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.mask_sub_sub_sub_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.opcode_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.same_cycle_resp,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.size_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.source_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.watchdog,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.watchdog_1,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader.DEFAULT,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader.FORMAT,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader.WIDTH,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader.myplus,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader.out,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_1.DEFAULT,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_1.FORMAT,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_1.WIDTH,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_1.myplus,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.plusarg_reader_1.out,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.monitor.unnamedblk1.i,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.full,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_deq_valid_0,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_ready_0,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_enq_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_full,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.io_repeat,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_address,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_param,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_size,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.saved_source,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.repeater.unnamedblk1.i,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.REG,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.a_fire,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_address,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_corrupt,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_param,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_a_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_bits_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_bits_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_bits_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.auto_in_d_valid,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.clock,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem_MPORT_1_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.nodeIn_a_ready,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.nodeIn_d_bits_opcode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.ren,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.reset,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_rdata_0_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_5_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_6_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_7_RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.initvar,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_en_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_w_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_w_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_w_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_w_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.initvar,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_r_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_r_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_r_en_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_w_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_w_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_w_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_1.ram_RW_0_w_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.initvar,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_r_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_r_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_r_en_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_w_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_w_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_w_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_2.ram_RW_0_w_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_wdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_wmask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.RW0_wmode,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.initvar,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_r_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_r_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_r_en_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_w_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_w_data,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_w_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_3.ram_RW_0_w_mask,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_clk,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_en,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_rdata,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_4.RW0_wdata",
"--at",
"803912750ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"signal_count": 1000
}
},
{
"name": "value_chipyard_clusteredrocketconfig_dhrystone_signals_100",
"category": "value",
"runs": 10,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.dump_start,TOP.TestDriver.failure,TOP.TestDriver.fsdbfile,TOP.TestDriver.max_cycles,TOP.TestDriver.printf_cond,TOP.TestDriver.rand_value,TOP.TestDriver.reason,TOP.TestDriver.reset,TOP.TestDriver.stderr,TOP.TestDriver.success,TOP.TestDriver.trace_count,TOP.TestDriver.vcdfile,TOP.TestDriver.vcdplusfile,TOP.TestDriver.verbose,TOP.TestDriver.testHarness.clock,TOP.TestDriver.testHarness.io_success,TOP.TestDriver.testHarness.reset,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.clock_en,TOP.TestDriver.testHarness.chiptop0.clock_tap,TOP.TestDriver.testHarness.chiptop0.clock_uncore,TOP.TestDriver.testHarness.chiptop0.custom_boot,TOP.TestDriver.testHarness.chiptop0.debug_reset,TOP.TestDriver.testHarness.chiptop0.jtag_TCK,TOP.TestDriver.testHarness.chiptop0.jtag_TDI,TOP.TestDriver.testHarness.chiptop0.jtag_TDO,TOP.TestDriver.testHarness.chiptop0.jtag_TMS,TOP.TestDriver.testHarness.chiptop0.reset_io,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_clock_in,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_in_bits_phit,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_in_ready,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_in_valid,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_out_bits_phit,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_out_ready,TOP.TestDriver.testHarness.chiptop0.serial_tl_0_out_valid,TOP.TestDriver.testHarness.chiptop0.uart_0_rxd,TOP.TestDriver.testHarness.chiptop0.uart_0_txd,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.clock,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.io_d,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.io_q,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.reset,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.clock,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.io_d,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.io_q,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.reset,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.sync_0,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.sync_1,TOP.TestDriver.testHarness.chiptop0.debug_reset_syncd_debug_reset_sync.output_chain.sync_2,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.clock,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.io_d,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.io_q,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.reset,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.clock,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.io_d,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.io_q,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.reset,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_0,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_1,TOP.TestDriver.testHarness.chiptop0.dmactiveAck_dmactiveAck.output_chain.sync_2,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.en,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.en_latched,TOP.TestDriver.testHarness.chiptop0.gated_clock_debug_clock_gate.in",
"--at",
"803912750ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"signal_count": 100
}
},
{
"name": "value_chipyard_clusteredrocketconfig_dhrystone_signals_10",
"category": "value",
"runs": 15,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.dump_start,TOP.TestDriver.failure,TOP.TestDriver.fsdbfile,TOP.TestDriver.max_cycles,TOP.TestDriver.printf_cond,TOP.TestDriver.rand_value,TOP.TestDriver.reason,TOP.TestDriver.reset,TOP.TestDriver.stderr",
"--at",
"803912750ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"signal_count": 10
}
},
{
"name": "value_chipyard_clusteredrocketconfig_dhrystone_signals_1",
"category": "value",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"value",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock",
"--at",
"803912750ps"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"signal_count": 1
}
},
{
"name": "info_chipyard_clustered_dhrystone",
"category": "info",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"info",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M"
}
},
{
"name": "info_chipyard_clustered_mt_memcpy",
"category": "info",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"info",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_mt-memcpy.fst",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_mt-memcpy.fst",
"size": "411M"
}
},
{
"name": "info_chipyard_dualrocket_dhrystone",
"category": "info",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"info",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M"
}
},
{
"name": "info_picorv32",
"category": "info",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"info",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M"
}
},
{
"name": "info_picorv32_ez",
"category": "info",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"info",
"--waves",
"/opt/rtl-artifacts/picorv32_test_ez_vcd.fst",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_ez_vcd.fst",
"size": "17K"
}
},
{
"name": "info_scr1",
"category": "info",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"info",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_coremark.fst",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_coremark.fst",
"size": "21M"
}
},
{
"name": "info_scr1_isr_sample",
"category": "info",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"info",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_isr_sample.fst",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_isr_sample.fst",
"size": "69K"
}
},
{
"name": "info_scr1_riscv_compliance",
"category": "info",
"runs": 20,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"info",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "4M"
}
},
{
"name": "scope_scr1_all_depth7_json",
"category": "scope",
"runs": 15,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"scope",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--max",
"200000",
"--max-depth",
"7",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "4M",
"filter": ".*",
"max_depth": 7,
"scope_count": 136
}
},
{
"name": "scope_dualrocket_filter_frontend_depth12_json",
"category": "scope",
"runs": 10,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"scope",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--filter",
".*frontend.*",
"--max",
"200000",
"--max-depth",
"12",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"filter": ".*frontend.*",
"max_depth": 12,
"scope_count": 118
}
},
{
"name": "scope_clustered_all_depth13_json",
"category": "scope",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"scope",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_mt-memcpy.fst",
"--max",
"200000",
"--max-depth",
"13",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_mt-memcpy.fst",
"size": "411M",
"filter": ".*",
"max_depth": 13,
"scope_count": 4625
}
},
{
"name": "signal_scr1_top_recursive_all_json",
"category": "signal",
"runs": 10,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"signal",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--scope",
"TOP",
"--recursive",
"--max",
"200000",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"scope": "TOP",
"filter": ".*",
"recursive": true,
"max_depth": "default"
}
},
{
"name": "signal_scr1_top_recursive_filter_valid_json",
"category": "signal",
"runs": 10,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"signal",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--scope",
"TOP",
"--recursive",
"--filter",
"(?i).*valid.*",
"--max",
"200000",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"scope": "TOP",
"filter": "(?i).*valid.*",
"recursive": true,
"max_depth": "default"
}
},
{
"name": "signal_scr1_top_recursive_depth2_json",
"category": "signal",
"runs": 10,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"signal",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--scope",
"TOP",
"--recursive",
"--max-depth",
"2",
"--max",
"200000",
"--json"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"scope": "TOP",
"filter": ".*",
"recursive": true,
"max_depth": 2
}
},
{
"name": "change_picorv32_signals_100_window_2us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready,testbench.top.mem_axi_bvalid,testbench.top.mem_axi_rdata,testbench.top.mem_axi_rready,testbench.top.mem_axi_rvalid,testbench.top.mem_axi_wdata,testbench.top.mem_axi_wready,testbench.top.mem_axi_wstrb,testbench.top.mem_axi_wvalid,testbench.top.mem.mem_axi_araddr,testbench.top.mem.mem_axi_arprot,testbench.top.mem.mem_axi_arready,testbench.top.mem.mem_axi_arvalid,testbench.top.mem.mem_axi_awaddr,testbench.top.mem.mem_axi_awprot,testbench.top.mem.mem_axi_awready,testbench.top.mem.mem_axi_awvalid,testbench.top.mem.mem_axi_bready,testbench.top.mem.mem_axi_bvalid,testbench.top.mem.mem_axi_rdata,testbench.top.mem.mem_axi_rready,testbench.top.mem.mem_axi_rvalid,testbench.top.mem.mem_axi_wdata,testbench.top.mem.mem_axi_wready,testbench.top.mem.mem_axi_wstrb,testbench.top.mem.mem_axi_wvalid,testbench.top.uut.mem_axi_araddr,testbench.top.uut.mem_axi_arprot,testbench.top.uut.mem_axi_arready,testbench.top.uut.mem_axi_arvalid,testbench.top.uut.mem_axi_awaddr,testbench.top.uut.mem_axi_awprot,testbench.top.uut.mem_axi_awready,testbench.top.uut.mem_axi_awvalid,testbench.top.uut.mem_axi_bready,testbench.top.uut.mem_axi_bvalid,testbench.top.uut.mem_axi_rdata,testbench.top.uut.mem_axi_rready,testbench.top.uut.mem_axi_rvalid,testbench.top.uut.mem_axi_wdata,testbench.top.uut.mem_axi_wready,testbench.top.uut.mem_axi_wstrb,testbench.top.uut.mem_axi_wvalid,testbench.top.uut.axi_adapter.ack_arvalid,testbench.top.uut.axi_adapter.ack_awvalid,testbench.top.uut.axi_adapter.ack_wvalid,testbench.top.uut.axi_adapter.mem_axi_araddr,testbench.top.uut.axi_adapter.mem_axi_arprot,testbench.top.uut.axi_adapter.mem_axi_arready,testbench.top.uut.axi_adapter.mem_axi_arvalid,testbench.top.uut.axi_adapter.mem_axi_awaddr,testbench.top.uut.axi_adapter.mem_axi_awprot,testbench.top.uut.axi_adapter.mem_axi_awready,testbench.top.uut.axi_adapter.mem_axi_awvalid,testbench.top.uut.axi_adapter.mem_axi_bready,testbench.top.uut.axi_adapter.mem_axi_bvalid,testbench.top.uut.axi_adapter.mem_axi_rdata,testbench.top.uut.axi_adapter.mem_axi_rready,testbench.top.uut.axi_adapter.mem_axi_rvalid,testbench.top.uut.axi_adapter.mem_axi_wdata,testbench.top.uut.axi_adapter.mem_axi_wready,testbench.top.uut.axi_adapter.mem_axi_wstrb,testbench.top.uut.axi_adapter.mem_axi_wvalid,testbench.top.uut.axi_adapter.mem_rdata,testbench.top.uut.axi_adapter.mem_wdata,testbench.top.uut.axi_adapter.mem_wstrb,testbench.top.mem.async_axi_transaction,testbench.top.mem.axi_test,testbench.top.mem.delay_axi_transaction,testbench.top.mem.fast_axi_transaction,testbench.top.uut.axi_adapter.clk,testbench.top.uut.axi_adapter.mem_addr,testbench.top.uut.axi_adapter.mem_instr,testbench.top.uut.axi_adapter.mem_ready,testbench.top.uut.axi_adapter.mem_valid,testbench.top.uut.axi_adapter.resetn,testbench.top.uut.axi_adapter.xfer_done,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file",
"--from",
"2450000000ps",
"--to",
"2452000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "2us",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_picorv32_signals_100_window_2us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready,testbench.top.mem_axi_bvalid,testbench.top.mem_axi_rdata,testbench.top.mem_axi_rready,testbench.top.mem_axi_rvalid,testbench.top.mem_axi_wdata,testbench.top.mem_axi_wready,testbench.top.mem_axi_wstrb,testbench.top.mem_axi_wvalid,testbench.top.mem.mem_axi_araddr,testbench.top.mem.mem_axi_arprot,testbench.top.mem.mem_axi_arready,testbench.top.mem.mem_axi_arvalid,testbench.top.mem.mem_axi_awaddr,testbench.top.mem.mem_axi_awprot,testbench.top.mem.mem_axi_awready,testbench.top.mem.mem_axi_awvalid,testbench.top.mem.mem_axi_bready,testbench.top.mem.mem_axi_bvalid,testbench.top.mem.mem_axi_rdata,testbench.top.mem.mem_axi_rready,testbench.top.mem.mem_axi_rvalid,testbench.top.mem.mem_axi_wdata,testbench.top.mem.mem_axi_wready,testbench.top.mem.mem_axi_wstrb,testbench.top.mem.mem_axi_wvalid,testbench.top.uut.mem_axi_araddr,testbench.top.uut.mem_axi_arprot,testbench.top.uut.mem_axi_arready,testbench.top.uut.mem_axi_arvalid,testbench.top.uut.mem_axi_awaddr,testbench.top.uut.mem_axi_awprot,testbench.top.uut.mem_axi_awready,testbench.top.uut.mem_axi_awvalid,testbench.top.uut.mem_axi_bready,testbench.top.uut.mem_axi_bvalid,testbench.top.uut.mem_axi_rdata,testbench.top.uut.mem_axi_rready,testbench.top.uut.mem_axi_rvalid,testbench.top.uut.mem_axi_wdata,testbench.top.uut.mem_axi_wready,testbench.top.uut.mem_axi_wstrb,testbench.top.uut.mem_axi_wvalid,testbench.top.uut.axi_adapter.ack_arvalid,testbench.top.uut.axi_adapter.ack_awvalid,testbench.top.uut.axi_adapter.ack_wvalid,testbench.top.uut.axi_adapter.mem_axi_araddr,testbench.top.uut.axi_adapter.mem_axi_arprot,testbench.top.uut.axi_adapter.mem_axi_arready,testbench.top.uut.axi_adapter.mem_axi_arvalid,testbench.top.uut.axi_adapter.mem_axi_awaddr,testbench.top.uut.axi_adapter.mem_axi_awprot,testbench.top.uut.axi_adapter.mem_axi_awready,testbench.top.uut.axi_adapter.mem_axi_awvalid,testbench.top.uut.axi_adapter.mem_axi_bready,testbench.top.uut.axi_adapter.mem_axi_bvalid,testbench.top.uut.axi_adapter.mem_axi_rdata,testbench.top.uut.axi_adapter.mem_axi_rready,testbench.top.uut.axi_adapter.mem_axi_rvalid,testbench.top.uut.axi_adapter.mem_axi_wdata,testbench.top.uut.axi_adapter.mem_axi_wready,testbench.top.uut.axi_adapter.mem_axi_wstrb,testbench.top.uut.axi_adapter.mem_axi_wvalid,testbench.top.uut.axi_adapter.mem_rdata,testbench.top.uut.axi_adapter.mem_wdata,testbench.top.uut.axi_adapter.mem_wstrb,testbench.top.mem.async_axi_transaction,testbench.top.mem.axi_test,testbench.top.mem.delay_axi_transaction,testbench.top.mem.fast_axi_transaction,testbench.top.uut.axi_adapter.clk,testbench.top.uut.axi_adapter.mem_addr,testbench.top.uut.axi_adapter.mem_instr,testbench.top.uut.axi_adapter.mem_ready,testbench.top.uut.axi_adapter.mem_valid,testbench.top.uut.axi_adapter.resetn,testbench.top.uut.axi_adapter.xfer_done,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file",
"--from",
"2450000000ps",
"--to",
"2452000000ps",
"--on",
"posedge testbench.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "2us",
"signal_count": 100,
"trigger": "posedge testbench.clk"
}
},
{
"name": "change_picorv32_signals_100_window_2us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready,testbench.top.mem_axi_bvalid,testbench.top.mem_axi_rdata,testbench.top.mem_axi_rready,testbench.top.mem_axi_rvalid,testbench.top.mem_axi_wdata,testbench.top.mem_axi_wready,testbench.top.mem_axi_wstrb,testbench.top.mem_axi_wvalid,testbench.top.mem.mem_axi_araddr,testbench.top.mem.mem_axi_arprot,testbench.top.mem.mem_axi_arready,testbench.top.mem.mem_axi_arvalid,testbench.top.mem.mem_axi_awaddr,testbench.top.mem.mem_axi_awprot,testbench.top.mem.mem_axi_awready,testbench.top.mem.mem_axi_awvalid,testbench.top.mem.mem_axi_bready,testbench.top.mem.mem_axi_bvalid,testbench.top.mem.mem_axi_rdata,testbench.top.mem.mem_axi_rready,testbench.top.mem.mem_axi_rvalid,testbench.top.mem.mem_axi_wdata,testbench.top.mem.mem_axi_wready,testbench.top.mem.mem_axi_wstrb,testbench.top.mem.mem_axi_wvalid,testbench.top.uut.mem_axi_araddr,testbench.top.uut.mem_axi_arprot,testbench.top.uut.mem_axi_arready,testbench.top.uut.mem_axi_arvalid,testbench.top.uut.mem_axi_awaddr,testbench.top.uut.mem_axi_awprot,testbench.top.uut.mem_axi_awready,testbench.top.uut.mem_axi_awvalid,testbench.top.uut.mem_axi_bready,testbench.top.uut.mem_axi_bvalid,testbench.top.uut.mem_axi_rdata,testbench.top.uut.mem_axi_rready,testbench.top.uut.mem_axi_rvalid,testbench.top.uut.mem_axi_wdata,testbench.top.uut.mem_axi_wready,testbench.top.uut.mem_axi_wstrb,testbench.top.uut.mem_axi_wvalid,testbench.top.uut.axi_adapter.ack_arvalid,testbench.top.uut.axi_adapter.ack_awvalid,testbench.top.uut.axi_adapter.ack_wvalid,testbench.top.uut.axi_adapter.mem_axi_araddr,testbench.top.uut.axi_adapter.mem_axi_arprot,testbench.top.uut.axi_adapter.mem_axi_arready,testbench.top.uut.axi_adapter.mem_axi_arvalid,testbench.top.uut.axi_adapter.mem_axi_awaddr,testbench.top.uut.axi_adapter.mem_axi_awprot,testbench.top.uut.axi_adapter.mem_axi_awready,testbench.top.uut.axi_adapter.mem_axi_awvalid,testbench.top.uut.axi_adapter.mem_axi_bready,testbench.top.uut.axi_adapter.mem_axi_bvalid,testbench.top.uut.axi_adapter.mem_axi_rdata,testbench.top.uut.axi_adapter.mem_axi_rready,testbench.top.uut.axi_adapter.mem_axi_rvalid,testbench.top.uut.axi_adapter.mem_axi_wdata,testbench.top.uut.axi_adapter.mem_axi_wready,testbench.top.uut.axi_adapter.mem_axi_wstrb,testbench.top.uut.axi_adapter.mem_axi_wvalid,testbench.top.uut.axi_adapter.mem_rdata,testbench.top.uut.axi_adapter.mem_wdata,testbench.top.uut.axi_adapter.mem_wstrb,testbench.top.mem.async_axi_transaction,testbench.top.mem.axi_test,testbench.top.mem.delay_axi_transaction,testbench.top.mem.fast_axi_transaction,testbench.top.uut.axi_adapter.clk,testbench.top.uut.axi_adapter.mem_addr,testbench.top.uut.axi_adapter.mem_instr,testbench.top.uut.axi_adapter.mem_ready,testbench.top.uut.axi_adapter.mem_valid,testbench.top.uut.axi_adapter.resetn,testbench.top.uut.axi_adapter.xfer_done,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file",
"--from",
"2450000000ps",
"--to",
"2452000000ps",
"--on",
"testbench.top.mem_axi_arvalid"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "2us",
"signal_count": 100,
"trigger": "testbench.top.mem_axi_arvalid"
}
},
{
"name": "change_picorv32_signals_100_window_8us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready,testbench.top.mem_axi_bvalid,testbench.top.mem_axi_rdata,testbench.top.mem_axi_rready,testbench.top.mem_axi_rvalid,testbench.top.mem_axi_wdata,testbench.top.mem_axi_wready,testbench.top.mem_axi_wstrb,testbench.top.mem_axi_wvalid,testbench.top.mem.mem_axi_araddr,testbench.top.mem.mem_axi_arprot,testbench.top.mem.mem_axi_arready,testbench.top.mem.mem_axi_arvalid,testbench.top.mem.mem_axi_awaddr,testbench.top.mem.mem_axi_awprot,testbench.top.mem.mem_axi_awready,testbench.top.mem.mem_axi_awvalid,testbench.top.mem.mem_axi_bready,testbench.top.mem.mem_axi_bvalid,testbench.top.mem.mem_axi_rdata,testbench.top.mem.mem_axi_rready,testbench.top.mem.mem_axi_rvalid,testbench.top.mem.mem_axi_wdata,testbench.top.mem.mem_axi_wready,testbench.top.mem.mem_axi_wstrb,testbench.top.mem.mem_axi_wvalid,testbench.top.uut.mem_axi_araddr,testbench.top.uut.mem_axi_arprot,testbench.top.uut.mem_axi_arready,testbench.top.uut.mem_axi_arvalid,testbench.top.uut.mem_axi_awaddr,testbench.top.uut.mem_axi_awprot,testbench.top.uut.mem_axi_awready,testbench.top.uut.mem_axi_awvalid,testbench.top.uut.mem_axi_bready,testbench.top.uut.mem_axi_bvalid,testbench.top.uut.mem_axi_rdata,testbench.top.uut.mem_axi_rready,testbench.top.uut.mem_axi_rvalid,testbench.top.uut.mem_axi_wdata,testbench.top.uut.mem_axi_wready,testbench.top.uut.mem_axi_wstrb,testbench.top.uut.mem_axi_wvalid,testbench.top.uut.axi_adapter.ack_arvalid,testbench.top.uut.axi_adapter.ack_awvalid,testbench.top.uut.axi_adapter.ack_wvalid,testbench.top.uut.axi_adapter.mem_axi_araddr,testbench.top.uut.axi_adapter.mem_axi_arprot,testbench.top.uut.axi_adapter.mem_axi_arready,testbench.top.uut.axi_adapter.mem_axi_arvalid,testbench.top.uut.axi_adapter.mem_axi_awaddr,testbench.top.uut.axi_adapter.mem_axi_awprot,testbench.top.uut.axi_adapter.mem_axi_awready,testbench.top.uut.axi_adapter.mem_axi_awvalid,testbench.top.uut.axi_adapter.mem_axi_bready,testbench.top.uut.axi_adapter.mem_axi_bvalid,testbench.top.uut.axi_adapter.mem_axi_rdata,testbench.top.uut.axi_adapter.mem_axi_rready,testbench.top.uut.axi_adapter.mem_axi_rvalid,testbench.top.uut.axi_adapter.mem_axi_wdata,testbench.top.uut.axi_adapter.mem_axi_wready,testbench.top.uut.axi_adapter.mem_axi_wstrb,testbench.top.uut.axi_adapter.mem_axi_wvalid,testbench.top.uut.axi_adapter.mem_rdata,testbench.top.uut.axi_adapter.mem_wdata,testbench.top.uut.axi_adapter.mem_wstrb,testbench.top.mem.async_axi_transaction,testbench.top.mem.axi_test,testbench.top.mem.delay_axi_transaction,testbench.top.mem.fast_axi_transaction,testbench.top.uut.axi_adapter.clk,testbench.top.uut.axi_adapter.mem_addr,testbench.top.uut.axi_adapter.mem_instr,testbench.top.uut.axi_adapter.mem_ready,testbench.top.uut.axi_adapter.mem_valid,testbench.top.uut.axi_adapter.resetn,testbench.top.uut.axi_adapter.xfer_done,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file",
"--from",
"2450000000ps",
"--to",
"2458000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "8us",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_picorv32_signals_100_window_8us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready,testbench.top.mem_axi_bvalid,testbench.top.mem_axi_rdata,testbench.top.mem_axi_rready,testbench.top.mem_axi_rvalid,testbench.top.mem_axi_wdata,testbench.top.mem_axi_wready,testbench.top.mem_axi_wstrb,testbench.top.mem_axi_wvalid,testbench.top.mem.mem_axi_araddr,testbench.top.mem.mem_axi_arprot,testbench.top.mem.mem_axi_arready,testbench.top.mem.mem_axi_arvalid,testbench.top.mem.mem_axi_awaddr,testbench.top.mem.mem_axi_awprot,testbench.top.mem.mem_axi_awready,testbench.top.mem.mem_axi_awvalid,testbench.top.mem.mem_axi_bready,testbench.top.mem.mem_axi_bvalid,testbench.top.mem.mem_axi_rdata,testbench.top.mem.mem_axi_rready,testbench.top.mem.mem_axi_rvalid,testbench.top.mem.mem_axi_wdata,testbench.top.mem.mem_axi_wready,testbench.top.mem.mem_axi_wstrb,testbench.top.mem.mem_axi_wvalid,testbench.top.uut.mem_axi_araddr,testbench.top.uut.mem_axi_arprot,testbench.top.uut.mem_axi_arready,testbench.top.uut.mem_axi_arvalid,testbench.top.uut.mem_axi_awaddr,testbench.top.uut.mem_axi_awprot,testbench.top.uut.mem_axi_awready,testbench.top.uut.mem_axi_awvalid,testbench.top.uut.mem_axi_bready,testbench.top.uut.mem_axi_bvalid,testbench.top.uut.mem_axi_rdata,testbench.top.uut.mem_axi_rready,testbench.top.uut.mem_axi_rvalid,testbench.top.uut.mem_axi_wdata,testbench.top.uut.mem_axi_wready,testbench.top.uut.mem_axi_wstrb,testbench.top.uut.mem_axi_wvalid,testbench.top.uut.axi_adapter.ack_arvalid,testbench.top.uut.axi_adapter.ack_awvalid,testbench.top.uut.axi_adapter.ack_wvalid,testbench.top.uut.axi_adapter.mem_axi_araddr,testbench.top.uut.axi_adapter.mem_axi_arprot,testbench.top.uut.axi_adapter.mem_axi_arready,testbench.top.uut.axi_adapter.mem_axi_arvalid,testbench.top.uut.axi_adapter.mem_axi_awaddr,testbench.top.uut.axi_adapter.mem_axi_awprot,testbench.top.uut.axi_adapter.mem_axi_awready,testbench.top.uut.axi_adapter.mem_axi_awvalid,testbench.top.uut.axi_adapter.mem_axi_bready,testbench.top.uut.axi_adapter.mem_axi_bvalid,testbench.top.uut.axi_adapter.mem_axi_rdata,testbench.top.uut.axi_adapter.mem_axi_rready,testbench.top.uut.axi_adapter.mem_axi_rvalid,testbench.top.uut.axi_adapter.mem_axi_wdata,testbench.top.uut.axi_adapter.mem_axi_wready,testbench.top.uut.axi_adapter.mem_axi_wstrb,testbench.top.uut.axi_adapter.mem_axi_wvalid,testbench.top.uut.axi_adapter.mem_rdata,testbench.top.uut.axi_adapter.mem_wdata,testbench.top.uut.axi_adapter.mem_wstrb,testbench.top.mem.async_axi_transaction,testbench.top.mem.axi_test,testbench.top.mem.delay_axi_transaction,testbench.top.mem.fast_axi_transaction,testbench.top.uut.axi_adapter.clk,testbench.top.uut.axi_adapter.mem_addr,testbench.top.uut.axi_adapter.mem_instr,testbench.top.uut.axi_adapter.mem_ready,testbench.top.uut.axi_adapter.mem_valid,testbench.top.uut.axi_adapter.resetn,testbench.top.uut.axi_adapter.xfer_done,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file",
"--from",
"2450000000ps",
"--to",
"2458000000ps",
"--on",
"posedge testbench.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "8us",
"signal_count": 100,
"trigger": "posedge testbench.clk"
}
},
{
"name": "change_picorv32_signals_100_window_8us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready,testbench.top.mem_axi_bvalid,testbench.top.mem_axi_rdata,testbench.top.mem_axi_rready,testbench.top.mem_axi_rvalid,testbench.top.mem_axi_wdata,testbench.top.mem_axi_wready,testbench.top.mem_axi_wstrb,testbench.top.mem_axi_wvalid,testbench.top.mem.mem_axi_araddr,testbench.top.mem.mem_axi_arprot,testbench.top.mem.mem_axi_arready,testbench.top.mem.mem_axi_arvalid,testbench.top.mem.mem_axi_awaddr,testbench.top.mem.mem_axi_awprot,testbench.top.mem.mem_axi_awready,testbench.top.mem.mem_axi_awvalid,testbench.top.mem.mem_axi_bready,testbench.top.mem.mem_axi_bvalid,testbench.top.mem.mem_axi_rdata,testbench.top.mem.mem_axi_rready,testbench.top.mem.mem_axi_rvalid,testbench.top.mem.mem_axi_wdata,testbench.top.mem.mem_axi_wready,testbench.top.mem.mem_axi_wstrb,testbench.top.mem.mem_axi_wvalid,testbench.top.uut.mem_axi_araddr,testbench.top.uut.mem_axi_arprot,testbench.top.uut.mem_axi_arready,testbench.top.uut.mem_axi_arvalid,testbench.top.uut.mem_axi_awaddr,testbench.top.uut.mem_axi_awprot,testbench.top.uut.mem_axi_awready,testbench.top.uut.mem_axi_awvalid,testbench.top.uut.mem_axi_bready,testbench.top.uut.mem_axi_bvalid,testbench.top.uut.mem_axi_rdata,testbench.top.uut.mem_axi_rready,testbench.top.uut.mem_axi_rvalid,testbench.top.uut.mem_axi_wdata,testbench.top.uut.mem_axi_wready,testbench.top.uut.mem_axi_wstrb,testbench.top.uut.mem_axi_wvalid,testbench.top.uut.axi_adapter.ack_arvalid,testbench.top.uut.axi_adapter.ack_awvalid,testbench.top.uut.axi_adapter.ack_wvalid,testbench.top.uut.axi_adapter.mem_axi_araddr,testbench.top.uut.axi_adapter.mem_axi_arprot,testbench.top.uut.axi_adapter.mem_axi_arready,testbench.top.uut.axi_adapter.mem_axi_arvalid,testbench.top.uut.axi_adapter.mem_axi_awaddr,testbench.top.uut.axi_adapter.mem_axi_awprot,testbench.top.uut.axi_adapter.mem_axi_awready,testbench.top.uut.axi_adapter.mem_axi_awvalid,testbench.top.uut.axi_adapter.mem_axi_bready,testbench.top.uut.axi_adapter.mem_axi_bvalid,testbench.top.uut.axi_adapter.mem_axi_rdata,testbench.top.uut.axi_adapter.mem_axi_rready,testbench.top.uut.axi_adapter.mem_axi_rvalid,testbench.top.uut.axi_adapter.mem_axi_wdata,testbench.top.uut.axi_adapter.mem_axi_wready,testbench.top.uut.axi_adapter.mem_axi_wstrb,testbench.top.uut.axi_adapter.mem_axi_wvalid,testbench.top.uut.axi_adapter.mem_rdata,testbench.top.uut.axi_adapter.mem_wdata,testbench.top.uut.axi_adapter.mem_wstrb,testbench.top.mem.async_axi_transaction,testbench.top.mem.axi_test,testbench.top.mem.delay_axi_transaction,testbench.top.mem.fast_axi_transaction,testbench.top.uut.axi_adapter.clk,testbench.top.uut.axi_adapter.mem_addr,testbench.top.uut.axi_adapter.mem_instr,testbench.top.uut.axi_adapter.mem_ready,testbench.top.uut.axi_adapter.mem_valid,testbench.top.uut.axi_adapter.resetn,testbench.top.uut.axi_adapter.xfer_done,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file",
"--from",
"2450000000ps",
"--to",
"2458000000ps",
"--on",
"testbench.top.mem_axi_arvalid"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "8us",
"signal_count": 100,
"trigger": "testbench.top.mem_axi_arvalid"
}
},
{
"name": "change_picorv32_signals_100_window_32us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready,testbench.top.mem_axi_bvalid,testbench.top.mem_axi_rdata,testbench.top.mem_axi_rready,testbench.top.mem_axi_rvalid,testbench.top.mem_axi_wdata,testbench.top.mem_axi_wready,testbench.top.mem_axi_wstrb,testbench.top.mem_axi_wvalid,testbench.top.mem.mem_axi_araddr,testbench.top.mem.mem_axi_arprot,testbench.top.mem.mem_axi_arready,testbench.top.mem.mem_axi_arvalid,testbench.top.mem.mem_axi_awaddr,testbench.top.mem.mem_axi_awprot,testbench.top.mem.mem_axi_awready,testbench.top.mem.mem_axi_awvalid,testbench.top.mem.mem_axi_bready,testbench.top.mem.mem_axi_bvalid,testbench.top.mem.mem_axi_rdata,testbench.top.mem.mem_axi_rready,testbench.top.mem.mem_axi_rvalid,testbench.top.mem.mem_axi_wdata,testbench.top.mem.mem_axi_wready,testbench.top.mem.mem_axi_wstrb,testbench.top.mem.mem_axi_wvalid,testbench.top.uut.mem_axi_araddr,testbench.top.uut.mem_axi_arprot,testbench.top.uut.mem_axi_arready,testbench.top.uut.mem_axi_arvalid,testbench.top.uut.mem_axi_awaddr,testbench.top.uut.mem_axi_awprot,testbench.top.uut.mem_axi_awready,testbench.top.uut.mem_axi_awvalid,testbench.top.uut.mem_axi_bready,testbench.top.uut.mem_axi_bvalid,testbench.top.uut.mem_axi_rdata,testbench.top.uut.mem_axi_rready,testbench.top.uut.mem_axi_rvalid,testbench.top.uut.mem_axi_wdata,testbench.top.uut.mem_axi_wready,testbench.top.uut.mem_axi_wstrb,testbench.top.uut.mem_axi_wvalid,testbench.top.uut.axi_adapter.ack_arvalid,testbench.top.uut.axi_adapter.ack_awvalid,testbench.top.uut.axi_adapter.ack_wvalid,testbench.top.uut.axi_adapter.mem_axi_araddr,testbench.top.uut.axi_adapter.mem_axi_arprot,testbench.top.uut.axi_adapter.mem_axi_arready,testbench.top.uut.axi_adapter.mem_axi_arvalid,testbench.top.uut.axi_adapter.mem_axi_awaddr,testbench.top.uut.axi_adapter.mem_axi_awprot,testbench.top.uut.axi_adapter.mem_axi_awready,testbench.top.uut.axi_adapter.mem_axi_awvalid,testbench.top.uut.axi_adapter.mem_axi_bready,testbench.top.uut.axi_adapter.mem_axi_bvalid,testbench.top.uut.axi_adapter.mem_axi_rdata,testbench.top.uut.axi_adapter.mem_axi_rready,testbench.top.uut.axi_adapter.mem_axi_rvalid,testbench.top.uut.axi_adapter.mem_axi_wdata,testbench.top.uut.axi_adapter.mem_axi_wready,testbench.top.uut.axi_adapter.mem_axi_wstrb,testbench.top.uut.axi_adapter.mem_axi_wvalid,testbench.top.uut.axi_adapter.mem_rdata,testbench.top.uut.axi_adapter.mem_wdata,testbench.top.uut.axi_adapter.mem_wstrb,testbench.top.mem.async_axi_transaction,testbench.top.mem.axi_test,testbench.top.mem.delay_axi_transaction,testbench.top.mem.fast_axi_transaction,testbench.top.uut.axi_adapter.clk,testbench.top.uut.axi_adapter.mem_addr,testbench.top.uut.axi_adapter.mem_instr,testbench.top.uut.axi_adapter.mem_ready,testbench.top.uut.axi_adapter.mem_valid,testbench.top.uut.axi_adapter.resetn,testbench.top.uut.axi_adapter.xfer_done,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file",
"--from",
"2450000000ps",
"--to",
"2482000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "32us",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_picorv32_signals_100_window_32us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready,testbench.top.mem_axi_bvalid,testbench.top.mem_axi_rdata,testbench.top.mem_axi_rready,testbench.top.mem_axi_rvalid,testbench.top.mem_axi_wdata,testbench.top.mem_axi_wready,testbench.top.mem_axi_wstrb,testbench.top.mem_axi_wvalid,testbench.top.mem.mem_axi_araddr,testbench.top.mem.mem_axi_arprot,testbench.top.mem.mem_axi_arready,testbench.top.mem.mem_axi_arvalid,testbench.top.mem.mem_axi_awaddr,testbench.top.mem.mem_axi_awprot,testbench.top.mem.mem_axi_awready,testbench.top.mem.mem_axi_awvalid,testbench.top.mem.mem_axi_bready,testbench.top.mem.mem_axi_bvalid,testbench.top.mem.mem_axi_rdata,testbench.top.mem.mem_axi_rready,testbench.top.mem.mem_axi_rvalid,testbench.top.mem.mem_axi_wdata,testbench.top.mem.mem_axi_wready,testbench.top.mem.mem_axi_wstrb,testbench.top.mem.mem_axi_wvalid,testbench.top.uut.mem_axi_araddr,testbench.top.uut.mem_axi_arprot,testbench.top.uut.mem_axi_arready,testbench.top.uut.mem_axi_arvalid,testbench.top.uut.mem_axi_awaddr,testbench.top.uut.mem_axi_awprot,testbench.top.uut.mem_axi_awready,testbench.top.uut.mem_axi_awvalid,testbench.top.uut.mem_axi_bready,testbench.top.uut.mem_axi_bvalid,testbench.top.uut.mem_axi_rdata,testbench.top.uut.mem_axi_rready,testbench.top.uut.mem_axi_rvalid,testbench.top.uut.mem_axi_wdata,testbench.top.uut.mem_axi_wready,testbench.top.uut.mem_axi_wstrb,testbench.top.uut.mem_axi_wvalid,testbench.top.uut.axi_adapter.ack_arvalid,testbench.top.uut.axi_adapter.ack_awvalid,testbench.top.uut.axi_adapter.ack_wvalid,testbench.top.uut.axi_adapter.mem_axi_araddr,testbench.top.uut.axi_adapter.mem_axi_arprot,testbench.top.uut.axi_adapter.mem_axi_arready,testbench.top.uut.axi_adapter.mem_axi_arvalid,testbench.top.uut.axi_adapter.mem_axi_awaddr,testbench.top.uut.axi_adapter.mem_axi_awprot,testbench.top.uut.axi_adapter.mem_axi_awready,testbench.top.uut.axi_adapter.mem_axi_awvalid,testbench.top.uut.axi_adapter.mem_axi_bready,testbench.top.uut.axi_adapter.mem_axi_bvalid,testbench.top.uut.axi_adapter.mem_axi_rdata,testbench.top.uut.axi_adapter.mem_axi_rready,testbench.top.uut.axi_adapter.mem_axi_rvalid,testbench.top.uut.axi_adapter.mem_axi_wdata,testbench.top.uut.axi_adapter.mem_axi_wready,testbench.top.uut.axi_adapter.mem_axi_wstrb,testbench.top.uut.axi_adapter.mem_axi_wvalid,testbench.top.uut.axi_adapter.mem_rdata,testbench.top.uut.axi_adapter.mem_wdata,testbench.top.uut.axi_adapter.mem_wstrb,testbench.top.mem.async_axi_transaction,testbench.top.mem.axi_test,testbench.top.mem.delay_axi_transaction,testbench.top.mem.fast_axi_transaction,testbench.top.uut.axi_adapter.clk,testbench.top.uut.axi_adapter.mem_addr,testbench.top.uut.axi_adapter.mem_instr,testbench.top.uut.axi_adapter.mem_ready,testbench.top.uut.axi_adapter.mem_valid,testbench.top.uut.axi_adapter.resetn,testbench.top.uut.axi_adapter.xfer_done,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file",
"--from",
"2450000000ps",
"--to",
"2482000000ps",
"--on",
"posedge testbench.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "32us",
"signal_count": 100,
"trigger": "posedge testbench.clk"
}
},
{
"name": "change_picorv32_signals_100_window_32us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready,testbench.top.mem_axi_bvalid,testbench.top.mem_axi_rdata,testbench.top.mem_axi_rready,testbench.top.mem_axi_rvalid,testbench.top.mem_axi_wdata,testbench.top.mem_axi_wready,testbench.top.mem_axi_wstrb,testbench.top.mem_axi_wvalid,testbench.top.mem.mem_axi_araddr,testbench.top.mem.mem_axi_arprot,testbench.top.mem.mem_axi_arready,testbench.top.mem.mem_axi_arvalid,testbench.top.mem.mem_axi_awaddr,testbench.top.mem.mem_axi_awprot,testbench.top.mem.mem_axi_awready,testbench.top.mem.mem_axi_awvalid,testbench.top.mem.mem_axi_bready,testbench.top.mem.mem_axi_bvalid,testbench.top.mem.mem_axi_rdata,testbench.top.mem.mem_axi_rready,testbench.top.mem.mem_axi_rvalid,testbench.top.mem.mem_axi_wdata,testbench.top.mem.mem_axi_wready,testbench.top.mem.mem_axi_wstrb,testbench.top.mem.mem_axi_wvalid,testbench.top.uut.mem_axi_araddr,testbench.top.uut.mem_axi_arprot,testbench.top.uut.mem_axi_arready,testbench.top.uut.mem_axi_arvalid,testbench.top.uut.mem_axi_awaddr,testbench.top.uut.mem_axi_awprot,testbench.top.uut.mem_axi_awready,testbench.top.uut.mem_axi_awvalid,testbench.top.uut.mem_axi_bready,testbench.top.uut.mem_axi_bvalid,testbench.top.uut.mem_axi_rdata,testbench.top.uut.mem_axi_rready,testbench.top.uut.mem_axi_rvalid,testbench.top.uut.mem_axi_wdata,testbench.top.uut.mem_axi_wready,testbench.top.uut.mem_axi_wstrb,testbench.top.uut.mem_axi_wvalid,testbench.top.uut.axi_adapter.ack_arvalid,testbench.top.uut.axi_adapter.ack_awvalid,testbench.top.uut.axi_adapter.ack_wvalid,testbench.top.uut.axi_adapter.mem_axi_araddr,testbench.top.uut.axi_adapter.mem_axi_arprot,testbench.top.uut.axi_adapter.mem_axi_arready,testbench.top.uut.axi_adapter.mem_axi_arvalid,testbench.top.uut.axi_adapter.mem_axi_awaddr,testbench.top.uut.axi_adapter.mem_axi_awprot,testbench.top.uut.axi_adapter.mem_axi_awready,testbench.top.uut.axi_adapter.mem_axi_awvalid,testbench.top.uut.axi_adapter.mem_axi_bready,testbench.top.uut.axi_adapter.mem_axi_bvalid,testbench.top.uut.axi_adapter.mem_axi_rdata,testbench.top.uut.axi_adapter.mem_axi_rready,testbench.top.uut.axi_adapter.mem_axi_rvalid,testbench.top.uut.axi_adapter.mem_axi_wdata,testbench.top.uut.axi_adapter.mem_axi_wready,testbench.top.uut.axi_adapter.mem_axi_wstrb,testbench.top.uut.axi_adapter.mem_axi_wvalid,testbench.top.uut.axi_adapter.mem_rdata,testbench.top.uut.axi_adapter.mem_wdata,testbench.top.uut.axi_adapter.mem_wstrb,testbench.top.mem.async_axi_transaction,testbench.top.mem.axi_test,testbench.top.mem.delay_axi_transaction,testbench.top.mem.fast_axi_transaction,testbench.top.uut.axi_adapter.clk,testbench.top.uut.axi_adapter.mem_addr,testbench.top.uut.axi_adapter.mem_instr,testbench.top.uut.axi_adapter.mem_ready,testbench.top.uut.axi_adapter.mem_valid,testbench.top.uut.axi_adapter.resetn,testbench.top.uut.axi_adapter.xfer_done,testbench.resetn,testbench.trace_data,testbench.trace_file,testbench.trace_valid,testbench.trap,testbench.top.clk,testbench.top.count_cycle,testbench.top.cycle_counter,testbench.top.firmware_file",
"--from",
"2450000000ps",
"--to",
"2482000000ps",
"--on",
"testbench.top.mem_axi_arvalid"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "32us",
"signal_count": 100,
"trigger": "testbench.top.mem_axi_arvalid"
}
},
{
"name": "change_picorv32_signals_10_window_2us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready",
"--from",
"2450000000ps",
"--to",
"2452000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "2us",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_picorv32_signals_10_window_2us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready",
"--from",
"2450000000ps",
"--to",
"2452000000ps",
"--on",
"posedge testbench.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "2us",
"signal_count": 10,
"trigger": "posedge testbench.clk"
}
},
{
"name": "change_picorv32_signals_10_window_2us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready",
"--from",
"2450000000ps",
"--to",
"2452000000ps",
"--on",
"testbench.top.mem_axi_arvalid"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "2us",
"signal_count": 10,
"trigger": "testbench.top.mem_axi_arvalid"
}
},
{
"name": "change_picorv32_signals_10_window_8us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready",
"--from",
"2450000000ps",
"--to",
"2458000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "8us",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_picorv32_signals_10_window_8us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready",
"--from",
"2450000000ps",
"--to",
"2458000000ps",
"--on",
"posedge testbench.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "8us",
"signal_count": 10,
"trigger": "posedge testbench.clk"
}
},
{
"name": "change_picorv32_signals_10_window_8us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready",
"--from",
"2450000000ps",
"--to",
"2458000000ps",
"--on",
"testbench.top.mem_axi_arvalid"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "8us",
"signal_count": 10,
"trigger": "testbench.top.mem_axi_arvalid"
}
},
{
"name": "change_picorv32_signals_10_window_32us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready",
"--from",
"2450000000ps",
"--to",
"2482000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "32us",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_picorv32_signals_10_window_32us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready",
"--from",
"2450000000ps",
"--to",
"2482000000ps",
"--on",
"posedge testbench.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "32us",
"signal_count": 10,
"trigger": "posedge testbench.clk"
}
},
{
"name": "change_picorv32_signals_10_window_32us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.clk,testbench.top.mem_axi_araddr,testbench.top.mem_axi_arprot,testbench.top.mem_axi_arready,testbench.top.mem_axi_arvalid,testbench.top.mem_axi_awaddr,testbench.top.mem_axi_awprot,testbench.top.mem_axi_awready,testbench.top.mem_axi_awvalid,testbench.top.mem_axi_bready",
"--from",
"2450000000ps",
"--to",
"2482000000ps",
"--on",
"testbench.top.mem_axi_arvalid"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "32us",
"signal_count": 10,
"trigger": "testbench.top.mem_axi_arvalid"
}
},
{
"name": "change_picorv32_signals_1_window_2us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.top.mem_axi_araddr",
"--from",
"2450000000ps",
"--to",
"2452000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "2us",
"signal_count": 1,
"trigger": "*"
}
},
{
"name": "change_picorv32_signals_1_window_2us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.top.mem_axi_araddr",
"--from",
"2450000000ps",
"--to",
"2452000000ps",
"--on",
"posedge testbench.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "2us",
"signal_count": 1,
"trigger": "posedge testbench.clk"
}
},
{
"name": "change_picorv32_signals_1_window_2us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.top.mem_axi_araddr",
"--from",
"2450000000ps",
"--to",
"2452000000ps",
"--on",
"testbench.top.mem_axi_arvalid"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "2us",
"signal_count": 1,
"trigger": "testbench.top.mem_axi_arvalid"
}
},
{
"name": "change_picorv32_signals_1_window_8us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.top.mem_axi_araddr",
"--from",
"2450000000ps",
"--to",
"2458000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "8us",
"signal_count": 1,
"trigger": "*"
}
},
{
"name": "change_picorv32_signals_1_window_8us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.top.mem_axi_araddr",
"--from",
"2450000000ps",
"--to",
"2458000000ps",
"--on",
"posedge testbench.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "8us",
"signal_count": 1,
"trigger": "posedge testbench.clk"
}
},
{
"name": "change_picorv32_signals_1_window_8us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.top.mem_axi_araddr",
"--from",
"2450000000ps",
"--to",
"2458000000ps",
"--on",
"testbench.top.mem_axi_arvalid"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "8us",
"signal_count": 1,
"trigger": "testbench.top.mem_axi_arvalid"
}
},
{
"name": "change_picorv32_signals_1_window_32us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.top.mem_axi_araddr",
"--from",
"2450000000ps",
"--to",
"2482000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "32us",
"signal_count": 1,
"trigger": "*"
}
},
{
"name": "change_picorv32_signals_1_window_32us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.top.mem_axi_araddr",
"--from",
"2450000000ps",
"--to",
"2482000000ps",
"--on",
"posedge testbench.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "32us",
"signal_count": 1,
"trigger": "posedge testbench.clk"
}
},
{
"name": "change_picorv32_signals_1_window_32us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/picorv32_test_vcd.fst",
"--signals",
"testbench.top.mem_axi_araddr",
"--from",
"2450000000ps",
"--to",
"2482000000ps",
"--on",
"testbench.top.mem_axi_arvalid"
],
"meta": {
"waves": "/opt/rtl-artifacts/picorv32_test_vcd.fst",
"size": "13M",
"window_size": "32us",
"signal_count": 1,
"trigger": "testbench.top.mem_axi_arvalid"
}
},
{
"name": "change_scr1_coremark_imem_axi_2sig_to_1000ps",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_coremark.fst",
"--to",
"1000ps",
"--scope",
"TOP.scr1_top_tb_axi.i_top.i_imem_axi",
"--signals",
"araddr,arvalid",
"--max",
"1000"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_coremark.fst",
"scope": "TOP.scr1_top_tb_axi.i_top.i_imem_axi",
"signal_count": 2,
"window_to": "1000ps"
}
},
{
"name": "change_scr1_coremark_imem_axi_1sig_to_1000ps",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_coremark.fst",
"--to",
"1000ps",
"--scope",
"TOP.scr1_top_tb_axi.i_top.i_imem_axi",
"--signals",
"araddr",
"--max",
"1000"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_coremark.fst",
"scope": "TOP.scr1_top_tb_axi.i_top.i_imem_axi",
"signal_count": 1,
"window_to": "1000ps"
}
},
{
"name": "change_scr1_signals_100_pos_50_window_2ns_trigger_any",
"category": "change",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.io_axi_dmem_awid,TOP.scr1_top_tb_axi.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.io_axi_dmem_awready,TOP.scr1_top_tb_axi.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.io_axi_dmem_bid,TOP.scr1_top_tb_axi.io_axi_dmem_bready,TOP.scr1_top_tb_axi.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.io_axi_dmem_buser,TOP.scr1_top_tb_axi.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.io_axi_dmem_rid,TOP.scr1_top_tb_axi.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.io_axi_dmem_rready,TOP.scr1_top_tb_axi.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.io_axi_dmem_wready,TOP.scr1_top_tb_axi.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.io_axi_imem_araddr,TOP.scr1_top_tb_axi.io_axi_imem_arburst,TOP.scr1_top_tb_axi.io_axi_imem_arid,TOP.scr1_top_tb_axi.io_axi_imem_arlen,TOP.scr1_top_tb_axi.io_axi_imem_arlock,TOP.scr1_top_tb_axi.io_axi_imem_arprot,TOP.scr1_top_tb_axi.io_axi_imem_arqos,TOP.scr1_top_tb_axi.io_axi_imem_arready,TOP.scr1_top_tb_axi.io_axi_imem_arregion,TOP.scr1_top_tb_axi.io_axi_imem_arsize,TOP.scr1_top_tb_axi.io_axi_imem_aruser,TOP.scr1_top_tb_axi.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.io_axi_imem_awburst,TOP.scr1_top_tb_axi.io_axi_imem_awid,TOP.scr1_top_tb_axi.io_axi_imem_awlen,TOP.scr1_top_tb_axi.io_axi_imem_awlock,TOP.scr1_top_tb_axi.io_axi_imem_awprot,TOP.scr1_top_tb_axi.io_axi_imem_awqos,TOP.scr1_top_tb_axi.io_axi_imem_awready,TOP.scr1_top_tb_axi.io_axi_imem_awregion,TOP.scr1_top_tb_axi.io_axi_imem_awsize,TOP.scr1_top_tb_axi.io_axi_imem_awuser,TOP.scr1_top_tb_axi.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.io_axi_imem_bid,TOP.scr1_top_tb_axi.io_axi_imem_bready,TOP.scr1_top_tb_axi.io_axi_imem_bresp,TOP.scr1_top_tb_axi.io_axi_imem_buser,TOP.scr1_top_tb_axi.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.io_axi_imem_rdata,TOP.scr1_top_tb_axi.io_axi_imem_rid,TOP.scr1_top_tb_axi.io_axi_imem_rlast,TOP.scr1_top_tb_axi.io_axi_imem_rready,TOP.scr1_top_tb_axi.io_axi_imem_rresp,TOP.scr1_top_tb_axi.io_axi_imem_ruser,TOP.scr1_top_tb_axi.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.io_axi_imem_wdata,TOP.scr1_top_tb_axi.io_axi_imem_wlast,TOP.scr1_top_tb_axi.io_axi_imem_wready,TOP.scr1_top_tb_axi.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.io_axi_imem_wuser,TOP.scr1_top_tb_axi.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.i_memory_tb.arready,TOP.scr1_top_tb_axi.i_memory_tb.arvalid,TOP.scr1_top_tb_axi.i_memory_tb.awready,TOP.scr1_top_tb_axi.i_memory_tb.awvalid,TOP.scr1_top_tb_axi.i_memory_tb.bready,TOP.scr1_top_tb_axi.i_memory_tb.bvalid,TOP.scr1_top_tb_axi.i_memory_tb.rlast,TOP.scr1_top_tb_axi.i_memory_tb.rready,TOP.scr1_top_tb_axi.i_memory_tb.rvalid,TOP.scr1_top_tb_axi.i_memory_tb.wlast,TOP.scr1_top_tb_axi.i_memory_tb.wready,TOP.scr1_top_tb_axi.i_memory_tb.wvalid,TOP.scr1_top_tb_axi.i_memory_tb.araddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.araddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[0]",
"--from",
"939092ps",
"--to",
"941092ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "2ns",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_scr1_signals_100_window_2ns_trigger_posedge_clk",
"category": "change",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.io_axi_dmem_awid,TOP.scr1_top_tb_axi.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.io_axi_dmem_awready,TOP.scr1_top_tb_axi.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.io_axi_dmem_bid,TOP.scr1_top_tb_axi.io_axi_dmem_bready,TOP.scr1_top_tb_axi.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.io_axi_dmem_buser,TOP.scr1_top_tb_axi.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.io_axi_dmem_rid,TOP.scr1_top_tb_axi.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.io_axi_dmem_rready,TOP.scr1_top_tb_axi.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.io_axi_dmem_wready,TOP.scr1_top_tb_axi.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.io_axi_imem_araddr,TOP.scr1_top_tb_axi.io_axi_imem_arburst,TOP.scr1_top_tb_axi.io_axi_imem_arid,TOP.scr1_top_tb_axi.io_axi_imem_arlen,TOP.scr1_top_tb_axi.io_axi_imem_arlock,TOP.scr1_top_tb_axi.io_axi_imem_arprot,TOP.scr1_top_tb_axi.io_axi_imem_arqos,TOP.scr1_top_tb_axi.io_axi_imem_arready,TOP.scr1_top_tb_axi.io_axi_imem_arregion,TOP.scr1_top_tb_axi.io_axi_imem_arsize,TOP.scr1_top_tb_axi.io_axi_imem_aruser,TOP.scr1_top_tb_axi.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.io_axi_imem_awburst,TOP.scr1_top_tb_axi.io_axi_imem_awid,TOP.scr1_top_tb_axi.io_axi_imem_awlen,TOP.scr1_top_tb_axi.io_axi_imem_awlock,TOP.scr1_top_tb_axi.io_axi_imem_awprot,TOP.scr1_top_tb_axi.io_axi_imem_awqos,TOP.scr1_top_tb_axi.io_axi_imem_awready,TOP.scr1_top_tb_axi.io_axi_imem_awregion,TOP.scr1_top_tb_axi.io_axi_imem_awsize,TOP.scr1_top_tb_axi.io_axi_imem_awuser,TOP.scr1_top_tb_axi.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.io_axi_imem_bid,TOP.scr1_top_tb_axi.io_axi_imem_bready,TOP.scr1_top_tb_axi.io_axi_imem_bresp,TOP.scr1_top_tb_axi.io_axi_imem_buser,TOP.scr1_top_tb_axi.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.io_axi_imem_rdata,TOP.scr1_top_tb_axi.io_axi_imem_rid,TOP.scr1_top_tb_axi.io_axi_imem_rlast,TOP.scr1_top_tb_axi.io_axi_imem_rready,TOP.scr1_top_tb_axi.io_axi_imem_rresp,TOP.scr1_top_tb_axi.io_axi_imem_ruser,TOP.scr1_top_tb_axi.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.io_axi_imem_wdata,TOP.scr1_top_tb_axi.io_axi_imem_wlast,TOP.scr1_top_tb_axi.io_axi_imem_wready,TOP.scr1_top_tb_axi.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.io_axi_imem_wuser,TOP.scr1_top_tb_axi.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.i_memory_tb.arready,TOP.scr1_top_tb_axi.i_memory_tb.arvalid,TOP.scr1_top_tb_axi.i_memory_tb.awready,TOP.scr1_top_tb_axi.i_memory_tb.awvalid,TOP.scr1_top_tb_axi.i_memory_tb.bready,TOP.scr1_top_tb_axi.i_memory_tb.bvalid,TOP.scr1_top_tb_axi.i_memory_tb.rlast,TOP.scr1_top_tb_axi.i_memory_tb.rready,TOP.scr1_top_tb_axi.i_memory_tb.rvalid,TOP.scr1_top_tb_axi.i_memory_tb.wlast,TOP.scr1_top_tb_axi.i_memory_tb.wready,TOP.scr1_top_tb_axi.i_memory_tb.wvalid,TOP.scr1_top_tb_axi.i_memory_tb.araddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.araddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[0]",
"--from",
"939092ps",
"--to",
"941092ps",
"--on",
"posedge TOP.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "2ns",
"signal_count": 100,
"trigger": "posedge TOP.clk"
}
},
{
"name": "change_scr1_signals_100_window_2ns_trigger_signal",
"category": "change",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.io_axi_dmem_awid,TOP.scr1_top_tb_axi.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.io_axi_dmem_awready,TOP.scr1_top_tb_axi.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.io_axi_dmem_bid,TOP.scr1_top_tb_axi.io_axi_dmem_bready,TOP.scr1_top_tb_axi.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.io_axi_dmem_buser,TOP.scr1_top_tb_axi.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.io_axi_dmem_rid,TOP.scr1_top_tb_axi.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.io_axi_dmem_rready,TOP.scr1_top_tb_axi.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.io_axi_dmem_wready,TOP.scr1_top_tb_axi.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.io_axi_imem_araddr,TOP.scr1_top_tb_axi.io_axi_imem_arburst,TOP.scr1_top_tb_axi.io_axi_imem_arid,TOP.scr1_top_tb_axi.io_axi_imem_arlen,TOP.scr1_top_tb_axi.io_axi_imem_arlock,TOP.scr1_top_tb_axi.io_axi_imem_arprot,TOP.scr1_top_tb_axi.io_axi_imem_arqos,TOP.scr1_top_tb_axi.io_axi_imem_arready,TOP.scr1_top_tb_axi.io_axi_imem_arregion,TOP.scr1_top_tb_axi.io_axi_imem_arsize,TOP.scr1_top_tb_axi.io_axi_imem_aruser,TOP.scr1_top_tb_axi.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.io_axi_imem_awburst,TOP.scr1_top_tb_axi.io_axi_imem_awid,TOP.scr1_top_tb_axi.io_axi_imem_awlen,TOP.scr1_top_tb_axi.io_axi_imem_awlock,TOP.scr1_top_tb_axi.io_axi_imem_awprot,TOP.scr1_top_tb_axi.io_axi_imem_awqos,TOP.scr1_top_tb_axi.io_axi_imem_awready,TOP.scr1_top_tb_axi.io_axi_imem_awregion,TOP.scr1_top_tb_axi.io_axi_imem_awsize,TOP.scr1_top_tb_axi.io_axi_imem_awuser,TOP.scr1_top_tb_axi.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.io_axi_imem_bid,TOP.scr1_top_tb_axi.io_axi_imem_bready,TOP.scr1_top_tb_axi.io_axi_imem_bresp,TOP.scr1_top_tb_axi.io_axi_imem_buser,TOP.scr1_top_tb_axi.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.io_axi_imem_rdata,TOP.scr1_top_tb_axi.io_axi_imem_rid,TOP.scr1_top_tb_axi.io_axi_imem_rlast,TOP.scr1_top_tb_axi.io_axi_imem_rready,TOP.scr1_top_tb_axi.io_axi_imem_rresp,TOP.scr1_top_tb_axi.io_axi_imem_ruser,TOP.scr1_top_tb_axi.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.io_axi_imem_wdata,TOP.scr1_top_tb_axi.io_axi_imem_wlast,TOP.scr1_top_tb_axi.io_axi_imem_wready,TOP.scr1_top_tb_axi.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.io_axi_imem_wuser,TOP.scr1_top_tb_axi.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.i_memory_tb.arready,TOP.scr1_top_tb_axi.i_memory_tb.arvalid,TOP.scr1_top_tb_axi.i_memory_tb.awready,TOP.scr1_top_tb_axi.i_memory_tb.awvalid,TOP.scr1_top_tb_axi.i_memory_tb.bready,TOP.scr1_top_tb_axi.i_memory_tb.bvalid,TOP.scr1_top_tb_axi.i_memory_tb.rlast,TOP.scr1_top_tb_axi.i_memory_tb.rready,TOP.scr1_top_tb_axi.i_memory_tb.rvalid,TOP.scr1_top_tb_axi.i_memory_tb.wlast,TOP.scr1_top_tb_axi.i_memory_tb.wready,TOP.scr1_top_tb_axi.i_memory_tb.wvalid,TOP.scr1_top_tb_axi.i_memory_tb.araddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.araddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[0]",
"--from",
"939092ps",
"--to",
"941092ps",
"--on",
"TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "2ns",
"signal_count": 100,
"trigger": "TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
}
},
{
"name": "change_scr1_signals_100_window_4ns_trigger_any",
"category": "change",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.io_axi_dmem_awid,TOP.scr1_top_tb_axi.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.io_axi_dmem_awready,TOP.scr1_top_tb_axi.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.io_axi_dmem_bid,TOP.scr1_top_tb_axi.io_axi_dmem_bready,TOP.scr1_top_tb_axi.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.io_axi_dmem_buser,TOP.scr1_top_tb_axi.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.io_axi_dmem_rid,TOP.scr1_top_tb_axi.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.io_axi_dmem_rready,TOP.scr1_top_tb_axi.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.io_axi_dmem_wready,TOP.scr1_top_tb_axi.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.io_axi_imem_araddr,TOP.scr1_top_tb_axi.io_axi_imem_arburst,TOP.scr1_top_tb_axi.io_axi_imem_arid,TOP.scr1_top_tb_axi.io_axi_imem_arlen,TOP.scr1_top_tb_axi.io_axi_imem_arlock,TOP.scr1_top_tb_axi.io_axi_imem_arprot,TOP.scr1_top_tb_axi.io_axi_imem_arqos,TOP.scr1_top_tb_axi.io_axi_imem_arready,TOP.scr1_top_tb_axi.io_axi_imem_arregion,TOP.scr1_top_tb_axi.io_axi_imem_arsize,TOP.scr1_top_tb_axi.io_axi_imem_aruser,TOP.scr1_top_tb_axi.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.io_axi_imem_awburst,TOP.scr1_top_tb_axi.io_axi_imem_awid,TOP.scr1_top_tb_axi.io_axi_imem_awlen,TOP.scr1_top_tb_axi.io_axi_imem_awlock,TOP.scr1_top_tb_axi.io_axi_imem_awprot,TOP.scr1_top_tb_axi.io_axi_imem_awqos,TOP.scr1_top_tb_axi.io_axi_imem_awready,TOP.scr1_top_tb_axi.io_axi_imem_awregion,TOP.scr1_top_tb_axi.io_axi_imem_awsize,TOP.scr1_top_tb_axi.io_axi_imem_awuser,TOP.scr1_top_tb_axi.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.io_axi_imem_bid,TOP.scr1_top_tb_axi.io_axi_imem_bready,TOP.scr1_top_tb_axi.io_axi_imem_bresp,TOP.scr1_top_tb_axi.io_axi_imem_buser,TOP.scr1_top_tb_axi.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.io_axi_imem_rdata,TOP.scr1_top_tb_axi.io_axi_imem_rid,TOP.scr1_top_tb_axi.io_axi_imem_rlast,TOP.scr1_top_tb_axi.io_axi_imem_rready,TOP.scr1_top_tb_axi.io_axi_imem_rresp,TOP.scr1_top_tb_axi.io_axi_imem_ruser,TOP.scr1_top_tb_axi.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.io_axi_imem_wdata,TOP.scr1_top_tb_axi.io_axi_imem_wlast,TOP.scr1_top_tb_axi.io_axi_imem_wready,TOP.scr1_top_tb_axi.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.io_axi_imem_wuser,TOP.scr1_top_tb_axi.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.i_memory_tb.arready,TOP.scr1_top_tb_axi.i_memory_tb.arvalid,TOP.scr1_top_tb_axi.i_memory_tb.awready,TOP.scr1_top_tb_axi.i_memory_tb.awvalid,TOP.scr1_top_tb_axi.i_memory_tb.bready,TOP.scr1_top_tb_axi.i_memory_tb.bvalid,TOP.scr1_top_tb_axi.i_memory_tb.rlast,TOP.scr1_top_tb_axi.i_memory_tb.rready,TOP.scr1_top_tb_axi.i_memory_tb.rvalid,TOP.scr1_top_tb_axi.i_memory_tb.wlast,TOP.scr1_top_tb_axi.i_memory_tb.wready,TOP.scr1_top_tb_axi.i_memory_tb.wvalid,TOP.scr1_top_tb_axi.i_memory_tb.araddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.araddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[0]",
"--from",
"938092ps",
"--to",
"942092ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "4ns",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_scr1_signals_100_window_4ns_trigger_posedge_clk",
"category": "change",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.io_axi_dmem_awid,TOP.scr1_top_tb_axi.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.io_axi_dmem_awready,TOP.scr1_top_tb_axi.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.io_axi_dmem_bid,TOP.scr1_top_tb_axi.io_axi_dmem_bready,TOP.scr1_top_tb_axi.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.io_axi_dmem_buser,TOP.scr1_top_tb_axi.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.io_axi_dmem_rid,TOP.scr1_top_tb_axi.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.io_axi_dmem_rready,TOP.scr1_top_tb_axi.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.io_axi_dmem_wready,TOP.scr1_top_tb_axi.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.io_axi_imem_araddr,TOP.scr1_top_tb_axi.io_axi_imem_arburst,TOP.scr1_top_tb_axi.io_axi_imem_arid,TOP.scr1_top_tb_axi.io_axi_imem_arlen,TOP.scr1_top_tb_axi.io_axi_imem_arlock,TOP.scr1_top_tb_axi.io_axi_imem_arprot,TOP.scr1_top_tb_axi.io_axi_imem_arqos,TOP.scr1_top_tb_axi.io_axi_imem_arready,TOP.scr1_top_tb_axi.io_axi_imem_arregion,TOP.scr1_top_tb_axi.io_axi_imem_arsize,TOP.scr1_top_tb_axi.io_axi_imem_aruser,TOP.scr1_top_tb_axi.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.io_axi_imem_awburst,TOP.scr1_top_tb_axi.io_axi_imem_awid,TOP.scr1_top_tb_axi.io_axi_imem_awlen,TOP.scr1_top_tb_axi.io_axi_imem_awlock,TOP.scr1_top_tb_axi.io_axi_imem_awprot,TOP.scr1_top_tb_axi.io_axi_imem_awqos,TOP.scr1_top_tb_axi.io_axi_imem_awready,TOP.scr1_top_tb_axi.io_axi_imem_awregion,TOP.scr1_top_tb_axi.io_axi_imem_awsize,TOP.scr1_top_tb_axi.io_axi_imem_awuser,TOP.scr1_top_tb_axi.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.io_axi_imem_bid,TOP.scr1_top_tb_axi.io_axi_imem_bready,TOP.scr1_top_tb_axi.io_axi_imem_bresp,TOP.scr1_top_tb_axi.io_axi_imem_buser,TOP.scr1_top_tb_axi.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.io_axi_imem_rdata,TOP.scr1_top_tb_axi.io_axi_imem_rid,TOP.scr1_top_tb_axi.io_axi_imem_rlast,TOP.scr1_top_tb_axi.io_axi_imem_rready,TOP.scr1_top_tb_axi.io_axi_imem_rresp,TOP.scr1_top_tb_axi.io_axi_imem_ruser,TOP.scr1_top_tb_axi.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.io_axi_imem_wdata,TOP.scr1_top_tb_axi.io_axi_imem_wlast,TOP.scr1_top_tb_axi.io_axi_imem_wready,TOP.scr1_top_tb_axi.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.io_axi_imem_wuser,TOP.scr1_top_tb_axi.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.i_memory_tb.arready,TOP.scr1_top_tb_axi.i_memory_tb.arvalid,TOP.scr1_top_tb_axi.i_memory_tb.awready,TOP.scr1_top_tb_axi.i_memory_tb.awvalid,TOP.scr1_top_tb_axi.i_memory_tb.bready,TOP.scr1_top_tb_axi.i_memory_tb.bvalid,TOP.scr1_top_tb_axi.i_memory_tb.rlast,TOP.scr1_top_tb_axi.i_memory_tb.rready,TOP.scr1_top_tb_axi.i_memory_tb.rvalid,TOP.scr1_top_tb_axi.i_memory_tb.wlast,TOP.scr1_top_tb_axi.i_memory_tb.wready,TOP.scr1_top_tb_axi.i_memory_tb.wvalid,TOP.scr1_top_tb_axi.i_memory_tb.araddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.araddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[0]",
"--from",
"938092ps",
"--to",
"942092ps",
"--on",
"posedge TOP.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "4ns",
"signal_count": 100,
"trigger": "posedge TOP.clk"
}
},
{
"name": "change_scr1_signals_100_window_4ns_trigger_signal",
"category": "change",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.io_axi_dmem_awid,TOP.scr1_top_tb_axi.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.io_axi_dmem_awready,TOP.scr1_top_tb_axi.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.io_axi_dmem_bid,TOP.scr1_top_tb_axi.io_axi_dmem_bready,TOP.scr1_top_tb_axi.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.io_axi_dmem_buser,TOP.scr1_top_tb_axi.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.io_axi_dmem_rid,TOP.scr1_top_tb_axi.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.io_axi_dmem_rready,TOP.scr1_top_tb_axi.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.io_axi_dmem_wready,TOP.scr1_top_tb_axi.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.io_axi_imem_araddr,TOP.scr1_top_tb_axi.io_axi_imem_arburst,TOP.scr1_top_tb_axi.io_axi_imem_arid,TOP.scr1_top_tb_axi.io_axi_imem_arlen,TOP.scr1_top_tb_axi.io_axi_imem_arlock,TOP.scr1_top_tb_axi.io_axi_imem_arprot,TOP.scr1_top_tb_axi.io_axi_imem_arqos,TOP.scr1_top_tb_axi.io_axi_imem_arready,TOP.scr1_top_tb_axi.io_axi_imem_arregion,TOP.scr1_top_tb_axi.io_axi_imem_arsize,TOP.scr1_top_tb_axi.io_axi_imem_aruser,TOP.scr1_top_tb_axi.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.io_axi_imem_awburst,TOP.scr1_top_tb_axi.io_axi_imem_awid,TOP.scr1_top_tb_axi.io_axi_imem_awlen,TOP.scr1_top_tb_axi.io_axi_imem_awlock,TOP.scr1_top_tb_axi.io_axi_imem_awprot,TOP.scr1_top_tb_axi.io_axi_imem_awqos,TOP.scr1_top_tb_axi.io_axi_imem_awready,TOP.scr1_top_tb_axi.io_axi_imem_awregion,TOP.scr1_top_tb_axi.io_axi_imem_awsize,TOP.scr1_top_tb_axi.io_axi_imem_awuser,TOP.scr1_top_tb_axi.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.io_axi_imem_bid,TOP.scr1_top_tb_axi.io_axi_imem_bready,TOP.scr1_top_tb_axi.io_axi_imem_bresp,TOP.scr1_top_tb_axi.io_axi_imem_buser,TOP.scr1_top_tb_axi.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.io_axi_imem_rdata,TOP.scr1_top_tb_axi.io_axi_imem_rid,TOP.scr1_top_tb_axi.io_axi_imem_rlast,TOP.scr1_top_tb_axi.io_axi_imem_rready,TOP.scr1_top_tb_axi.io_axi_imem_rresp,TOP.scr1_top_tb_axi.io_axi_imem_ruser,TOP.scr1_top_tb_axi.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.io_axi_imem_wdata,TOP.scr1_top_tb_axi.io_axi_imem_wlast,TOP.scr1_top_tb_axi.io_axi_imem_wready,TOP.scr1_top_tb_axi.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.io_axi_imem_wuser,TOP.scr1_top_tb_axi.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.i_memory_tb.arready,TOP.scr1_top_tb_axi.i_memory_tb.arvalid,TOP.scr1_top_tb_axi.i_memory_tb.awready,TOP.scr1_top_tb_axi.i_memory_tb.awvalid,TOP.scr1_top_tb_axi.i_memory_tb.bready,TOP.scr1_top_tb_axi.i_memory_tb.bvalid,TOP.scr1_top_tb_axi.i_memory_tb.rlast,TOP.scr1_top_tb_axi.i_memory_tb.rready,TOP.scr1_top_tb_axi.i_memory_tb.rvalid,TOP.scr1_top_tb_axi.i_memory_tb.wlast,TOP.scr1_top_tb_axi.i_memory_tb.wready,TOP.scr1_top_tb_axi.i_memory_tb.wvalid,TOP.scr1_top_tb_axi.i_memory_tb.araddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.araddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[0]",
"--from",
"938092ps",
"--to",
"942092ps",
"--on",
"TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "4ns",
"signal_count": 100,
"trigger": "TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
}
},
{
"name": "change_scr1_signals_100_window_8ns_trigger_any",
"category": "change",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.io_axi_dmem_awid,TOP.scr1_top_tb_axi.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.io_axi_dmem_awready,TOP.scr1_top_tb_axi.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.io_axi_dmem_bid,TOP.scr1_top_tb_axi.io_axi_dmem_bready,TOP.scr1_top_tb_axi.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.io_axi_dmem_buser,TOP.scr1_top_tb_axi.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.io_axi_dmem_rid,TOP.scr1_top_tb_axi.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.io_axi_dmem_rready,TOP.scr1_top_tb_axi.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.io_axi_dmem_wready,TOP.scr1_top_tb_axi.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.io_axi_imem_araddr,TOP.scr1_top_tb_axi.io_axi_imem_arburst,TOP.scr1_top_tb_axi.io_axi_imem_arid,TOP.scr1_top_tb_axi.io_axi_imem_arlen,TOP.scr1_top_tb_axi.io_axi_imem_arlock,TOP.scr1_top_tb_axi.io_axi_imem_arprot,TOP.scr1_top_tb_axi.io_axi_imem_arqos,TOP.scr1_top_tb_axi.io_axi_imem_arready,TOP.scr1_top_tb_axi.io_axi_imem_arregion,TOP.scr1_top_tb_axi.io_axi_imem_arsize,TOP.scr1_top_tb_axi.io_axi_imem_aruser,TOP.scr1_top_tb_axi.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.io_axi_imem_awburst,TOP.scr1_top_tb_axi.io_axi_imem_awid,TOP.scr1_top_tb_axi.io_axi_imem_awlen,TOP.scr1_top_tb_axi.io_axi_imem_awlock,TOP.scr1_top_tb_axi.io_axi_imem_awprot,TOP.scr1_top_tb_axi.io_axi_imem_awqos,TOP.scr1_top_tb_axi.io_axi_imem_awready,TOP.scr1_top_tb_axi.io_axi_imem_awregion,TOP.scr1_top_tb_axi.io_axi_imem_awsize,TOP.scr1_top_tb_axi.io_axi_imem_awuser,TOP.scr1_top_tb_axi.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.io_axi_imem_bid,TOP.scr1_top_tb_axi.io_axi_imem_bready,TOP.scr1_top_tb_axi.io_axi_imem_bresp,TOP.scr1_top_tb_axi.io_axi_imem_buser,TOP.scr1_top_tb_axi.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.io_axi_imem_rdata,TOP.scr1_top_tb_axi.io_axi_imem_rid,TOP.scr1_top_tb_axi.io_axi_imem_rlast,TOP.scr1_top_tb_axi.io_axi_imem_rready,TOP.scr1_top_tb_axi.io_axi_imem_rresp,TOP.scr1_top_tb_axi.io_axi_imem_ruser,TOP.scr1_top_tb_axi.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.io_axi_imem_wdata,TOP.scr1_top_tb_axi.io_axi_imem_wlast,TOP.scr1_top_tb_axi.io_axi_imem_wready,TOP.scr1_top_tb_axi.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.io_axi_imem_wuser,TOP.scr1_top_tb_axi.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.i_memory_tb.arready,TOP.scr1_top_tb_axi.i_memory_tb.arvalid,TOP.scr1_top_tb_axi.i_memory_tb.awready,TOP.scr1_top_tb_axi.i_memory_tb.awvalid,TOP.scr1_top_tb_axi.i_memory_tb.bready,TOP.scr1_top_tb_axi.i_memory_tb.bvalid,TOP.scr1_top_tb_axi.i_memory_tb.rlast,TOP.scr1_top_tb_axi.i_memory_tb.rready,TOP.scr1_top_tb_axi.i_memory_tb.rvalid,TOP.scr1_top_tb_axi.i_memory_tb.wlast,TOP.scr1_top_tb_axi.i_memory_tb.wready,TOP.scr1_top_tb_axi.i_memory_tb.wvalid,TOP.scr1_top_tb_axi.i_memory_tb.araddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.araddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[0]",
"--from",
"936092ps",
"--to",
"944092ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "8ns",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_scr1_signals_100_window_8ns_trigger_posedge_clk",
"category": "change",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.io_axi_dmem_awid,TOP.scr1_top_tb_axi.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.io_axi_dmem_awready,TOP.scr1_top_tb_axi.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.io_axi_dmem_bid,TOP.scr1_top_tb_axi.io_axi_dmem_bready,TOP.scr1_top_tb_axi.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.io_axi_dmem_buser,TOP.scr1_top_tb_axi.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.io_axi_dmem_rid,TOP.scr1_top_tb_axi.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.io_axi_dmem_rready,TOP.scr1_top_tb_axi.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.io_axi_dmem_wready,TOP.scr1_top_tb_axi.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.io_axi_imem_araddr,TOP.scr1_top_tb_axi.io_axi_imem_arburst,TOP.scr1_top_tb_axi.io_axi_imem_arid,TOP.scr1_top_tb_axi.io_axi_imem_arlen,TOP.scr1_top_tb_axi.io_axi_imem_arlock,TOP.scr1_top_tb_axi.io_axi_imem_arprot,TOP.scr1_top_tb_axi.io_axi_imem_arqos,TOP.scr1_top_tb_axi.io_axi_imem_arready,TOP.scr1_top_tb_axi.io_axi_imem_arregion,TOP.scr1_top_tb_axi.io_axi_imem_arsize,TOP.scr1_top_tb_axi.io_axi_imem_aruser,TOP.scr1_top_tb_axi.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.io_axi_imem_awburst,TOP.scr1_top_tb_axi.io_axi_imem_awid,TOP.scr1_top_tb_axi.io_axi_imem_awlen,TOP.scr1_top_tb_axi.io_axi_imem_awlock,TOP.scr1_top_tb_axi.io_axi_imem_awprot,TOP.scr1_top_tb_axi.io_axi_imem_awqos,TOP.scr1_top_tb_axi.io_axi_imem_awready,TOP.scr1_top_tb_axi.io_axi_imem_awregion,TOP.scr1_top_tb_axi.io_axi_imem_awsize,TOP.scr1_top_tb_axi.io_axi_imem_awuser,TOP.scr1_top_tb_axi.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.io_axi_imem_bid,TOP.scr1_top_tb_axi.io_axi_imem_bready,TOP.scr1_top_tb_axi.io_axi_imem_bresp,TOP.scr1_top_tb_axi.io_axi_imem_buser,TOP.scr1_top_tb_axi.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.io_axi_imem_rdata,TOP.scr1_top_tb_axi.io_axi_imem_rid,TOP.scr1_top_tb_axi.io_axi_imem_rlast,TOP.scr1_top_tb_axi.io_axi_imem_rready,TOP.scr1_top_tb_axi.io_axi_imem_rresp,TOP.scr1_top_tb_axi.io_axi_imem_ruser,TOP.scr1_top_tb_axi.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.io_axi_imem_wdata,TOP.scr1_top_tb_axi.io_axi_imem_wlast,TOP.scr1_top_tb_axi.io_axi_imem_wready,TOP.scr1_top_tb_axi.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.io_axi_imem_wuser,TOP.scr1_top_tb_axi.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.i_memory_tb.arready,TOP.scr1_top_tb_axi.i_memory_tb.arvalid,TOP.scr1_top_tb_axi.i_memory_tb.awready,TOP.scr1_top_tb_axi.i_memory_tb.awvalid,TOP.scr1_top_tb_axi.i_memory_tb.bready,TOP.scr1_top_tb_axi.i_memory_tb.bvalid,TOP.scr1_top_tb_axi.i_memory_tb.rlast,TOP.scr1_top_tb_axi.i_memory_tb.rready,TOP.scr1_top_tb_axi.i_memory_tb.rvalid,TOP.scr1_top_tb_axi.i_memory_tb.wlast,TOP.scr1_top_tb_axi.i_memory_tb.wready,TOP.scr1_top_tb_axi.i_memory_tb.wvalid,TOP.scr1_top_tb_axi.i_memory_tb.araddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.araddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[0]",
"--from",
"936092ps",
"--to",
"944092ps",
"--on",
"posedge TOP.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "8ns",
"signal_count": 100,
"trigger": "posedge TOP.clk"
}
},
{
"name": "change_scr1_signals_100_window_8ns_trigger_signal",
"category": "change",
"runs": 6,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion,TOP.scr1_top_tb_axi.io_axi_dmem_arsize,TOP.scr1_top_tb_axi.io_axi_dmem_aruser,TOP.scr1_top_tb_axi.io_axi_dmem_arvalid,TOP.scr1_top_tb_axi.io_axi_dmem_awaddr,TOP.scr1_top_tb_axi.io_axi_dmem_awburst,TOP.scr1_top_tb_axi.io_axi_dmem_awid,TOP.scr1_top_tb_axi.io_axi_dmem_awlen,TOP.scr1_top_tb_axi.io_axi_dmem_awlock,TOP.scr1_top_tb_axi.io_axi_dmem_awprot,TOP.scr1_top_tb_axi.io_axi_dmem_awqos,TOP.scr1_top_tb_axi.io_axi_dmem_awready,TOP.scr1_top_tb_axi.io_axi_dmem_awregion,TOP.scr1_top_tb_axi.io_axi_dmem_awsize,TOP.scr1_top_tb_axi.io_axi_dmem_awuser,TOP.scr1_top_tb_axi.io_axi_dmem_awvalid,TOP.scr1_top_tb_axi.io_axi_dmem_bid,TOP.scr1_top_tb_axi.io_axi_dmem_bready,TOP.scr1_top_tb_axi.io_axi_dmem_bresp,TOP.scr1_top_tb_axi.io_axi_dmem_buser,TOP.scr1_top_tb_axi.io_axi_dmem_bvalid,TOP.scr1_top_tb_axi.io_axi_dmem_rdata,TOP.scr1_top_tb_axi.io_axi_dmem_rid,TOP.scr1_top_tb_axi.io_axi_dmem_rlast,TOP.scr1_top_tb_axi.io_axi_dmem_rready,TOP.scr1_top_tb_axi.io_axi_dmem_rresp,TOP.scr1_top_tb_axi.io_axi_dmem_ruser,TOP.scr1_top_tb_axi.io_axi_dmem_rvalid,TOP.scr1_top_tb_axi.io_axi_dmem_wdata,TOP.scr1_top_tb_axi.io_axi_dmem_wlast,TOP.scr1_top_tb_axi.io_axi_dmem_wready,TOP.scr1_top_tb_axi.io_axi_dmem_wstrb,TOP.scr1_top_tb_axi.io_axi_dmem_wuser,TOP.scr1_top_tb_axi.io_axi_dmem_wvalid,TOP.scr1_top_tb_axi.io_axi_imem_araddr,TOP.scr1_top_tb_axi.io_axi_imem_arburst,TOP.scr1_top_tb_axi.io_axi_imem_arid,TOP.scr1_top_tb_axi.io_axi_imem_arlen,TOP.scr1_top_tb_axi.io_axi_imem_arlock,TOP.scr1_top_tb_axi.io_axi_imem_arprot,TOP.scr1_top_tb_axi.io_axi_imem_arqos,TOP.scr1_top_tb_axi.io_axi_imem_arready,TOP.scr1_top_tb_axi.io_axi_imem_arregion,TOP.scr1_top_tb_axi.io_axi_imem_arsize,TOP.scr1_top_tb_axi.io_axi_imem_aruser,TOP.scr1_top_tb_axi.io_axi_imem_arvalid,TOP.scr1_top_tb_axi.io_axi_imem_awaddr,TOP.scr1_top_tb_axi.io_axi_imem_awburst,TOP.scr1_top_tb_axi.io_axi_imem_awid,TOP.scr1_top_tb_axi.io_axi_imem_awlen,TOP.scr1_top_tb_axi.io_axi_imem_awlock,TOP.scr1_top_tb_axi.io_axi_imem_awprot,TOP.scr1_top_tb_axi.io_axi_imem_awqos,TOP.scr1_top_tb_axi.io_axi_imem_awready,TOP.scr1_top_tb_axi.io_axi_imem_awregion,TOP.scr1_top_tb_axi.io_axi_imem_awsize,TOP.scr1_top_tb_axi.io_axi_imem_awuser,TOP.scr1_top_tb_axi.io_axi_imem_awvalid,TOP.scr1_top_tb_axi.io_axi_imem_bid,TOP.scr1_top_tb_axi.io_axi_imem_bready,TOP.scr1_top_tb_axi.io_axi_imem_bresp,TOP.scr1_top_tb_axi.io_axi_imem_buser,TOP.scr1_top_tb_axi.io_axi_imem_bvalid,TOP.scr1_top_tb_axi.io_axi_imem_rdata,TOP.scr1_top_tb_axi.io_axi_imem_rid,TOP.scr1_top_tb_axi.io_axi_imem_rlast,TOP.scr1_top_tb_axi.io_axi_imem_rready,TOP.scr1_top_tb_axi.io_axi_imem_rresp,TOP.scr1_top_tb_axi.io_axi_imem_ruser,TOP.scr1_top_tb_axi.io_axi_imem_rvalid,TOP.scr1_top_tb_axi.io_axi_imem_wdata,TOP.scr1_top_tb_axi.io_axi_imem_wlast,TOP.scr1_top_tb_axi.io_axi_imem_wready,TOP.scr1_top_tb_axi.io_axi_imem_wstrb,TOP.scr1_top_tb_axi.io_axi_imem_wuser,TOP.scr1_top_tb_axi.io_axi_imem_wvalid,TOP.scr1_top_tb_axi.i_memory_tb.arready,TOP.scr1_top_tb_axi.i_memory_tb.arvalid,TOP.scr1_top_tb_axi.i_memory_tb.awready,TOP.scr1_top_tb_axi.i_memory_tb.awvalid,TOP.scr1_top_tb_axi.i_memory_tb.bready,TOP.scr1_top_tb_axi.i_memory_tb.bvalid,TOP.scr1_top_tb_axi.i_memory_tb.rlast,TOP.scr1_top_tb_axi.i_memory_tb.rready,TOP.scr1_top_tb_axi.i_memory_tb.rvalid,TOP.scr1_top_tb_axi.i_memory_tb.wlast,TOP.scr1_top_tb_axi.i_memory_tb.wready,TOP.scr1_top_tb_axi.i_memory_tb.wvalid,TOP.scr1_top_tb_axi.i_memory_tb.araddr.[0],TOP.scr1_top_tb_axi.i_memory_tb.araddr.[1],TOP.scr1_top_tb_axi.i_memory_tb.arburst.[0]",
"--from",
"936092ps",
"--to",
"944092ps",
"--on",
"TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "8ns",
"signal_count": 100,
"trigger": "TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
}
},
{
"name": "change_scr1_signals_10_window_2ns_trigger_any",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion",
"--from",
"939092ps",
"--to",
"941092ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "2ns",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_scr1_signals_10_window_2ns_trigger_posedge_clk",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion",
"--from",
"939092ps",
"--to",
"941092ps",
"--on",
"posedge TOP.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "2ns",
"signal_count": 10,
"trigger": "posedge TOP.clk"
}
},
{
"name": "change_scr1_signals_10_window_2ns_trigger_signal",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion",
"--from",
"939092ps",
"--to",
"941092ps",
"--on",
"TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "2ns",
"signal_count": 10,
"trigger": "TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
}
},
{
"name": "change_scr1_signals_10_window_4ns_trigger_any",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion",
"--from",
"938092ps",
"--to",
"942092ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "4ns",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_scr1_signals_10_window_4ns_trigger_posedge_clk",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion",
"--from",
"938092ps",
"--to",
"942092ps",
"--on",
"posedge TOP.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "4ns",
"signal_count": 10,
"trigger": "posedge TOP.clk"
}
},
{
"name": "change_scr1_signals_10_window_4ns_trigger_signal",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion",
"--from",
"938092ps",
"--to",
"942092ps",
"--on",
"TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "4ns",
"signal_count": 10,
"trigger": "TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
}
},
{
"name": "change_scr1_signals_10_window_8ns_trigger_any",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion",
"--from",
"936092ps",
"--to",
"944092ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "8ns",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_scr1_signals_10_window_8ns_trigger_posedge_clk",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion",
"--from",
"936092ps",
"--to",
"944092ps",
"--on",
"posedge TOP.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "8ns",
"signal_count": 10,
"trigger": "posedge TOP.clk"
}
},
{
"name": "change_scr1_signals_10_window_8ns_trigger_signal",
"category": "change",
"runs": 9,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk,TOP.scr1_top_tb_axi.io_axi_dmem_araddr,TOP.scr1_top_tb_axi.io_axi_dmem_arburst,TOP.scr1_top_tb_axi.io_axi_dmem_arid,TOP.scr1_top_tb_axi.io_axi_dmem_arlen,TOP.scr1_top_tb_axi.io_axi_dmem_arlock,TOP.scr1_top_tb_axi.io_axi_dmem_arprot,TOP.scr1_top_tb_axi.io_axi_dmem_arqos,TOP.scr1_top_tb_axi.io_axi_dmem_arready,TOP.scr1_top_tb_axi.io_axi_dmem_arregion",
"--from",
"936092ps",
"--to",
"944092ps",
"--on",
"TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "8ns",
"signal_count": 10,
"trigger": "TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
}
},
{
"name": "change_scr1_signals_1_window_2ns_trigger_any",
"category": "change",
"runs": 12,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk",
"--from",
"939092ps",
"--to",
"941092ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "2ns",
"signal_count": 1,
"trigger": "*"
}
},
{
"name": "change_scr1_signals_1_window_2ns_trigger_posedge_clk",
"category": "change",
"runs": 12,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk",
"--from",
"939092ps",
"--to",
"941092ps",
"--on",
"posedge TOP.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "2ns",
"signal_count": 1,
"trigger": "posedge TOP.clk"
}
},
{
"name": "change_scr1_signals_1_window_2ns_trigger_signal",
"category": "change",
"runs": 12,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk",
"--from",
"939092ps",
"--to",
"941092ps",
"--on",
"TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "2ns",
"signal_count": 1,
"trigger": "TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
}
},
{
"name": "change_scr1_signals_1_window_4ns_trigger_any",
"category": "change",
"runs": 12,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk",
"--from",
"938092ps",
"--to",
"942092ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "4ns",
"signal_count": 1,
"trigger": "*"
}
},
{
"name": "change_scr1_signals_1_window_4ns_trigger_posedge_clk",
"category": "change",
"runs": 12,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk",
"--from",
"938092ps",
"--to",
"942092ps",
"--on",
"posedge TOP.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "4ns",
"signal_count": 1,
"trigger": "posedge TOP.clk"
}
},
{
"name": "change_scr1_signals_1_window_4ns_trigger_signal",
"category": "change",
"runs": 12,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk",
"--from",
"938092ps",
"--to",
"942092ps",
"--on",
"TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "4ns",
"signal_count": 1,
"trigger": "TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
}
},
{
"name": "change_scr1_signals_1_window_8ns_trigger_any",
"category": "change",
"runs": 12,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk",
"--from",
"936092ps",
"--to",
"944092ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "8ns",
"signal_count": 1,
"trigger": "*"
}
},
{
"name": "change_scr1_signals_1_window_8ns_trigger_posedge_clk",
"category": "change",
"runs": 12,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk",
"--from",
"936092ps",
"--to",
"944092ps",
"--on",
"posedge TOP.clk"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "8ns",
"signal_count": 1,
"trigger": "posedge TOP.clk"
}
},
{
"name": "change_scr1_signals_1_window_8ns_trigger_signal",
"category": "change",
"runs": 12,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"--signals",
"TOP.clk",
"--from",
"936092ps",
"--to",
"944092ps",
"--on",
"TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
],
"meta": {
"waves": "/opt/rtl-artifacts/scr1_max_axi_riscv_compliance.fst",
"size": "3.5M",
"window_size": "8ns",
"signal_count": 1,
"trigger": "TOP.scr1_top_tb_axi.io_axi_dmem_araddr"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_100_window_2us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "2us",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_100_window_2us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "2us",
"signal_count": 100,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_100_window_2us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "2us",
"signal_count": 100,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_100_window_8us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "8us",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_100_window_8us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "8us",
"signal_count": 100,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_100_window_8us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "8us",
"signal_count": 100,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_100_window_32us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "32us",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_100_window_32us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "32us",
"signal_count": 100,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_100_window_32us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mbus.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "32us",
"signal_count": 100,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_10_window_2us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "2us",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_10_window_2us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "2us",
"signal_count": 10,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_10_window_2us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "2us",
"signal_count": 10,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_10_window_8us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "8us",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_10_window_8us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "8us",
"signal_count": 10,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_10_window_8us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "8us",
"signal_count": 10,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_10_window_32us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "32us",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_10_window_32us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "32us",
"signal_count": 10,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_10_window_32us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "32us",
"signal_count": 10,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_1_window_2us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "2us",
"signal_count": 1,
"trigger": "*"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_1_window_2us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "2us",
"signal_count": 1,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_1_window_2us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "2us",
"signal_count": 1,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_1_window_8us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "8us",
"signal_count": 1,
"trigger": "*"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_1_window_8us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "8us",
"signal_count": 1,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_1_window_8us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "8us",
"signal_count": 1,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_1_window_32us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "32us",
"signal_count": 1,
"trigger": "*"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_1_window_32us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "32us",
"signal_count": 1,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_dualrocketconfig_dhrystone_signals_1_window_32us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_DualRocketConfig_dhrystone.fst",
"size": "76M",
"window_size": "32us",
"signal_count": 1,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_100_window_2us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "2us",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_100_window_2us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "2us",
"signal_count": 100,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_100_window_2us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "2us",
"signal_count": 100,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_100_window_8us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "8us",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_100_window_8us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "8us",
"signal_count": 100,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_100_window_8us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "8us",
"signal_count": 100,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_100_window_32us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "32us",
"signal_count": 100,
"trigger": "*"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_100_window_32us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "32us",
"signal_count": 100,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_100_window_32us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_aw_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_b_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_r_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_data,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_last,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_ready,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_w_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_ar_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_addr,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_burst,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_cache,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_len,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_lock,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_prot,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_qos,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_bits_size,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_aw_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_b_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_id,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_bits_resp,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_r_valid,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_data,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_last,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_bits_strb,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_ready,TOP.TestDriver.testHarness.chiptop0.system.mem_axi4_0_w_valid,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_clock,TOP.TestDriver.testHarness.chiptop0.system.bank.fragmenter.aToggle_r,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_full,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_1,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_2,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_3,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_4,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_5,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_6,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_raw_data_7,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_read,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_size,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.r_source,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_addr_pipe_0,TOP.TestDriver.testHarness.chiptop0.system.bank.ram.mem.mem_ext.mem_0_0.ram_RW_0_r_data",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "32us",
"signal_count": 100,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_10_window_2us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "2us",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_10_window_2us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "2us",
"signal_count": 10,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_10_window_2us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "2us",
"signal_count": 10,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_10_window_8us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "8us",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_10_window_8us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "8us",
"signal_count": 10,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_10_window_8us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"808000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "8us",
"signal_count": 10,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_10_window_32us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "32us",
"signal_count": 10,
"trigger": "*"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_10_window_32us_trigger_posedge_clk",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"posedge TOP.TestDriver.clock"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "32us",
"signal_count": 10,
"trigger": "posedge TOP.TestDriver.clock"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_10_window_32us_trigger_signal",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.clock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_burst,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_cache,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_id,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_len,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_lock,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_prot,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_qos,TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_size",
"--from",
"800000000ps",
"--to",
"832000000ps",
"--on",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"size": "165M",
"window_size": "32us",
"signal_count": 10,
"trigger": "TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_valid"
}
},
{
"name": "change_chipyard_clusteredrocketconfig_dhrystone_signals_1_window_2us_trigger_any",
"category": "change",
"runs": 5,
"warmup": 3,
"command": [
"{wavepeek_bin}",
"change",
"--waves",
"/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
"--signals",
"TOP.TestDriver.testHarness.chiptop0.axi4_mem_0_bits_ar_bits_addr",
"--from",
"800000000ps",
"--to",
"802000000ps",
"--on",
"*"
],
"meta": {
"waves": "/opt/rtl-artifacts/chipyard_ClusteredRocketConfig_dhrystone.fst",
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}