w7500x_pac/crg/
adcclk_pvsr.rs

1#[doc = "Register `ADCCLK_PVSR` reader"]
2pub struct R(crate::R<ADCCLK_PVSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ADCCLK_PVSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ADCCLK_PVSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ADCCLK_PVSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ADCCLK_PVSR` writer"]
17pub struct W(crate::W<ADCCLK_PVSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ADCCLK_PVSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ADCCLK_PVSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ADCCLK_PVSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "ADCCLK prescale value select bits\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum ADCCP_A {
41    #[doc = "0: 1/1"]
42    BYPASS = 0,
43    #[doc = "1: 1/2"]
44    HALF = 1,
45    #[doc = "2: 1/4"]
46    BY4 = 2,
47    #[doc = "3: 1/8"]
48    BY8 = 3,
49}
50impl From<ADCCP_A> for u8 {
51    #[inline(always)]
52    fn from(variant: ADCCP_A) -> Self {
53        variant as _
54    }
55}
56#[doc = "Field `ADCCP` reader - ADCCLK prescale value select bits"]
57pub struct ADCCP_R(crate::FieldReader<u8>);
58impl ADCCP_R {
59    #[inline(always)]
60    pub(crate) fn new(bits: u8) -> Self {
61        ADCCP_R(crate::FieldReader::new(bits))
62    }
63    #[doc = r"Get enumerated values variant"]
64    #[inline(always)]
65    pub fn variant(&self) -> ADCCP_A {
66        match self.bits {
67            0 => ADCCP_A::BYPASS,
68            1 => ADCCP_A::HALF,
69            2 => ADCCP_A::BY4,
70            3 => ADCCP_A::BY8,
71            _ => unreachable!(),
72        }
73    }
74    #[doc = "Checks if the value of the field is `BYPASS`"]
75    #[inline(always)]
76    pub fn is_bypass(&self) -> bool {
77        **self == ADCCP_A::BYPASS
78    }
79    #[doc = "Checks if the value of the field is `HALF`"]
80    #[inline(always)]
81    pub fn is_half(&self) -> bool {
82        **self == ADCCP_A::HALF
83    }
84    #[doc = "Checks if the value of the field is `BY4`"]
85    #[inline(always)]
86    pub fn is_by4(&self) -> bool {
87        **self == ADCCP_A::BY4
88    }
89    #[doc = "Checks if the value of the field is `BY8`"]
90    #[inline(always)]
91    pub fn is_by8(&self) -> bool {
92        **self == ADCCP_A::BY8
93    }
94}
95impl core::ops::Deref for ADCCP_R {
96    type Target = crate::FieldReader<u8>;
97    #[inline(always)]
98    fn deref(&self) -> &Self::Target {
99        &self.0
100    }
101}
102#[doc = "Field `ADCCP` writer - ADCCLK prescale value select bits"]
103pub struct ADCCP_W<'a> {
104    w: &'a mut W,
105}
106impl<'a> ADCCP_W<'a> {
107    #[doc = r"Writes `variant` to the field"]
108    #[inline(always)]
109    pub fn variant(self, variant: ADCCP_A) -> &'a mut W {
110        self.bits(variant.into())
111    }
112    #[doc = "1/1"]
113    #[inline(always)]
114    pub fn bypass(self) -> &'a mut W {
115        self.variant(ADCCP_A::BYPASS)
116    }
117    #[doc = "1/2"]
118    #[inline(always)]
119    pub fn half(self) -> &'a mut W {
120        self.variant(ADCCP_A::HALF)
121    }
122    #[doc = "1/4"]
123    #[inline(always)]
124    pub fn by4(self) -> &'a mut W {
125        self.variant(ADCCP_A::BY4)
126    }
127    #[doc = "1/8"]
128    #[inline(always)]
129    pub fn by8(self) -> &'a mut W {
130        self.variant(ADCCP_A::BY8)
131    }
132    #[doc = r"Writes raw bits to the field"]
133    #[inline(always)]
134    pub fn bits(self, value: u8) -> &'a mut W {
135        self.w.bits = (self.w.bits & !3) | (value as u32 & 3);
136        self.w
137    }
138}
139impl R {
140    #[doc = "Bits 0:1 - ADCCLK prescale value select bits"]
141    #[inline(always)]
142    pub fn adccp(&self) -> ADCCP_R {
143        ADCCP_R::new((self.bits & 3) as u8)
144    }
145}
146impl W {
147    #[doc = "Bits 0:1 - ADCCLK prescale value select bits"]
148    #[inline(always)]
149    pub fn adccp(&mut self) -> ADCCP_W {
150        ADCCP_W { w: self }
151    }
152    #[doc = "Writes raw bits to the register."]
153    #[inline(always)]
154    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
155        self.0.bits(bits);
156        self
157    }
158}
159#[doc = "ADCCLK prescale value select register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcclk_pvsr](index.html) module"]
160pub struct ADCCLK_PVSR_SPEC;
161impl crate::RegisterSpec for ADCCLK_PVSR_SPEC {
162    type Ux = u32;
163}
164#[doc = "`read()` method returns [adcclk_pvsr::R](R) reader structure"]
165impl crate::Readable for ADCCLK_PVSR_SPEC {
166    type Reader = R;
167}
168#[doc = "`write(|w| ..)` method takes [adcclk_pvsr::W](W) writer structure"]
169impl crate::Writable for ADCCLK_PVSR_SPEC {
170    type Writer = W;
171}
172#[doc = "`reset()` method sets ADCCLK_PVSR to value 0"]
173impl crate::Resettable for ADCCLK_PVSR_SPEC {
174    #[inline(always)]
175    fn reset_value() -> Self::Ux {
176        0
177    }
178}
w7500x_pac/crg/adcclk_pvsr.rs

w7500x_pac/crg/
adcclk_pvsr.rs
