w7500x_pac/rtc/
rtccon.rs

1#[doc = "Register `RTCCON` reader"]
2pub struct R(crate::R<RTCCON_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RTCCON_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RTCCON_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RTCCON_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RTCCON` writer"]
17pub struct W(crate::W<RTCCON_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RTCCON_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RTCCON_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RTCCON_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "RTC Interrupt Enable\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum INTEN_A {
40    #[doc = "0: `0`"]
41    DISABLE = 0,
42    #[doc = "1: `1`"]
43    ENABLE = 1,
44}
45impl From<INTEN_A> for bool {
46    #[inline(always)]
47    fn from(variant: INTEN_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `INTEN` reader - RTC Interrupt Enable"]
52pub struct INTEN_R(crate::FieldReader<bool>);
53impl INTEN_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        INTEN_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> INTEN_A {
61        match self.bits {
62            false => INTEN_A::DISABLE,
63            true => INTEN_A::ENABLE,
64        }
65    }
66    #[doc = "Checks if the value of the field is `DISABLE`"]
67    #[inline(always)]
68    pub fn is_disable(&self) -> bool {
69        **self == INTEN_A::DISABLE
70    }
71    #[doc = "Checks if the value of the field is `ENABLE`"]
72    #[inline(always)]
73    pub fn is_enable(&self) -> bool {
74        **self == INTEN_A::ENABLE
75    }
76}
77impl core::ops::Deref for INTEN_R {
78    type Target = crate::FieldReader<bool>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `INTEN` writer - RTC Interrupt Enable"]
85pub struct INTEN_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> INTEN_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: INTEN_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "`0`"]
95    #[inline(always)]
96    pub fn disable(self) -> &'a mut W {
97        self.variant(INTEN_A::DISABLE)
98    }
99    #[doc = "`1`"]
100    #[inline(always)]
101    pub fn enable(self) -> &'a mut W {
102        self.variant(INTEN_A::ENABLE)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !(1 << 5)) | ((value as u32 & 1) << 5);
118        self.w
119    }
120}
121#[doc = "RTC Divider Reset\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq)]
123pub enum DIVRST_A {
124    #[doc = "1: `1`"]
125    RESET = 1,
126}
127impl From<DIVRST_A> for bool {
128    #[inline(always)]
129    fn from(variant: DIVRST_A) -> Self {
130        variant as u8 != 0
131    }
132}
133#[doc = "Field `DIVRST` reader - RTC Divider Reset"]
134pub struct DIVRST_R(crate::FieldReader<bool>);
135impl DIVRST_R {
136    #[inline(always)]
137    pub(crate) fn new(bits: bool) -> Self {
138        DIVRST_R(crate::FieldReader::new(bits))
139    }
140    #[doc = r"Get enumerated values variant"]
141    #[inline(always)]
142    pub fn variant(&self) -> Option<DIVRST_A> {
143        match self.bits {
144            true => Some(DIVRST_A::RESET),
145            _ => None,
146        }
147    }
148    #[doc = "Checks if the value of the field is `RESET`"]
149    #[inline(always)]
150    pub fn is_reset(&self) -> bool {
151        **self == DIVRST_A::RESET
152    }
153}
154impl core::ops::Deref for DIVRST_R {
155    type Target = crate::FieldReader<bool>;
156    #[inline(always)]
157    fn deref(&self) -> &Self::Target {
158        &self.0
159    }
160}
161#[doc = "Field `DIVRST` writer - RTC Divider Reset"]
162pub struct DIVRST_W<'a> {
163    w: &'a mut W,
164}
165impl<'a> DIVRST_W<'a> {
166    #[doc = r"Writes `variant` to the field"]
167    #[inline(always)]
168    pub fn variant(self, variant: DIVRST_A) -> &'a mut W {
169        self.bit(variant.into())
170    }
171    #[doc = "`1`"]
172    #[inline(always)]
173    pub fn reset(self) -> &'a mut W {
174        self.variant(DIVRST_A::RESET)
175    }
176    #[doc = r"Sets the field bit"]
177    #[inline(always)]
178    pub fn set_bit(self) -> &'a mut W {
179        self.bit(true)
180    }
181    #[doc = r"Clears the field bit"]
182    #[inline(always)]
183    pub fn clear_bit(self) -> &'a mut W {
184        self.bit(false)
185    }
186    #[doc = r"Writes raw bits to the field"]
187    #[inline(always)]
188    pub fn bit(self, value: bool) -> &'a mut W {
189        self.w.bits = (self.w.bits & !(1 << 1)) | ((value as u32 & 1) << 1);
190        self.w
191    }
192}
193#[doc = "Clock Enable\n\nValue on reset: 0"]
194#[derive(Clone, Copy, Debug, PartialEq)]
195pub enum CLKEN_A {
196    #[doc = "0: `0`"]
197    DISABLE = 0,
198    #[doc = "1: `1`"]
199    ENABLE = 1,
200}
201impl From<CLKEN_A> for bool {
202    #[inline(always)]
203    fn from(variant: CLKEN_A) -> Self {
204        variant as u8 != 0
205    }
206}
207#[doc = "Field `CLKEN` reader - Clock Enable"]
208pub struct CLKEN_R(crate::FieldReader<bool>);
209impl CLKEN_R {
210    #[inline(always)]
211    pub(crate) fn new(bits: bool) -> Self {
212        CLKEN_R(crate::FieldReader::new(bits))
213    }
214    #[doc = r"Get enumerated values variant"]
215    #[inline(always)]
216    pub fn variant(&self) -> CLKEN_A {
217        match self.bits {
218            false => CLKEN_A::DISABLE,
219            true => CLKEN_A::ENABLE,
220        }
221    }
222    #[doc = "Checks if the value of the field is `DISABLE`"]
223    #[inline(always)]
224    pub fn is_disable(&self) -> bool {
225        **self == CLKEN_A::DISABLE
226    }
227    #[doc = "Checks if the value of the field is `ENABLE`"]
228    #[inline(always)]
229    pub fn is_enable(&self) -> bool {
230        **self == CLKEN_A::ENABLE
231    }
232}
233impl core::ops::Deref for CLKEN_R {
234    type Target = crate::FieldReader<bool>;
235    #[inline(always)]
236    fn deref(&self) -> &Self::Target {
237        &self.0
238    }
239}
240#[doc = "Field `CLKEN` writer - Clock Enable"]
241pub struct CLKEN_W<'a> {
242    w: &'a mut W,
243}
244impl<'a> CLKEN_W<'a> {
245    #[doc = r"Writes `variant` to the field"]
246    #[inline(always)]
247    pub fn variant(self, variant: CLKEN_A) -> &'a mut W {
248        self.bit(variant.into())
249    }
250    #[doc = "`0`"]
251    #[inline(always)]
252    pub fn disable(self) -> &'a mut W {
253        self.variant(CLKEN_A::DISABLE)
254    }
255    #[doc = "`1`"]
256    #[inline(always)]
257    pub fn enable(self) -> &'a mut W {
258        self.variant(CLKEN_A::ENABLE)
259    }
260    #[doc = r"Sets the field bit"]
261    #[inline(always)]
262    pub fn set_bit(self) -> &'a mut W {
263        self.bit(true)
264    }
265    #[doc = r"Clears the field bit"]
266    #[inline(always)]
267    pub fn clear_bit(self) -> &'a mut W {
268        self.bit(false)
269    }
270    #[doc = r"Writes raw bits to the field"]
271    #[inline(always)]
272    pub fn bit(self, value: bool) -> &'a mut W {
273        self.w.bits = (self.w.bits & !1) | (value as u32 & 1);
274        self.w
275    }
276}
277impl R {
278    #[doc = "Bit 5 - RTC Interrupt Enable"]
279    #[inline(always)]
280    pub fn inten(&self) -> INTEN_R {
281        INTEN_R::new(((self.bits >> 5) & 1) != 0)
282    }
283    #[doc = "Bit 1 - RTC Divider Reset"]
284    #[inline(always)]
285    pub fn divrst(&self) -> DIVRST_R {
286        DIVRST_R::new(((self.bits >> 1) & 1) != 0)
287    }
288    #[doc = "Bit 0 - Clock Enable"]
289    #[inline(always)]
290    pub fn clken(&self) -> CLKEN_R {
291        CLKEN_R::new((self.bits & 1) != 0)
292    }
293}
294impl W {
295    #[doc = "Bit 5 - RTC Interrupt Enable"]
296    #[inline(always)]
297    pub fn inten(&mut self) -> INTEN_W {
298        INTEN_W { w: self }
299    }
300    #[doc = "Bit 1 - RTC Divider Reset"]
301    #[inline(always)]
302    pub fn divrst(&mut self) -> DIVRST_W {
303        DIVRST_W { w: self }
304    }
305    #[doc = "Bit 0 - Clock Enable"]
306    #[inline(always)]
307    pub fn clken(&mut self) -> CLKEN_W {
308        CLKEN_W { w: self }
309    }
310    #[doc = "Writes raw bits to the register."]
311    #[inline(always)]
312    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
313        self.0.bits(bits);
314        self
315    }
316}
317#[doc = "control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtccon](index.html) module"]
318pub struct RTCCON_SPEC;
319impl crate::RegisterSpec for RTCCON_SPEC {
320    type Ux = u32;
321}
322#[doc = "`read()` method returns [rtccon::R](R) reader structure"]
323impl crate::Readable for RTCCON_SPEC {
324    type Reader = R;
325}
326#[doc = "`write(|w| ..)` method takes [rtccon::W](W) writer structure"]
327impl crate::Writable for RTCCON_SPEC {
328    type Writer = W;
329}
330#[doc = "`reset()` method sets RTCCON to value 0"]
331impl crate::Resettable for RTCCON_SPEC {
332    #[inline(always)]
333    fn reset_value() -> Self::Ux {
334        0
335    }
336}
w7500x_pac/rtc/rtccon.rs

w7500x_pac/rtc/
rtccon.rs
