# W65C816S Table 5-5 — Operation Codes and Status Register
`*` = new instruction added in W65C816 (not in 65C02)
Operator symbols: `&`=AND, `|`=OR, `^`=XOR, `~`=NOT, `+`=ADD, `-`=SUB
---
## Flag Notation
```
Bit: 7 6 5 4 3 2 1 0
N V M X D I Z C
(1)(B) <- emulation mode names for bits 5/4
```
In the flag columns below:
- `.` = not affected
- `N/V/Z/C` = modified per result
- `0` / `1` = forced to that value
- `M` = loaded from memory bit (BIT instruction only)
- `E` = exchange (XCE only)
- `•` = set (BRK/COP B-flag)
---
## Addressing Mode Key
| 1 | Absolute | `a` | 16-bit address, data bank |
| 2 | Accumulator | `A` | operates on accumulator |
| 3 | Abs Idx X | `a,x` | absolute + X |
| 4 | Abs Idx Y | `a,y` | absolute + Y |
| 5 | Abs Long | `al` | 24-bit address |
| 6 | Abs Long X | `al,x` | 24-bit address + X |
| 7 | Abs Indirect | `(a)` | jump through 16-bit pointer at `a` |
| 8 | Abs Idx Ind | `(a,x)` | jump through pointer at `a+X` |
| 9 | Direct | `d` | 8-bit offset from D register (bank 0)|
| 10 | Stack Rel | `d,s` | 8-bit offset from S |
| 11 | Direct Idx X | `d,x` | direct + X |
| 12 | Direct Idx Y | `d,y` | direct + Y |
| 13 | Dir Indirect | `(d)` | 16-bit pointer at direct page |
| 14 | Dir Ind Long | `[d]` | 24-bit pointer at direct page |
| 15 | SR Ind Idx Y | `(d,s),y` | stack-relative indirect + Y |
| 16 | Dir Idx Ind | `(d,x)` | 16-bit pointer at direct+X |
| 17 | Dir Ind Idx | `(d),y` | 16-bit indirect pointer + Y |
| 18 | Dir Ind Idx L| `[d],y` | 24-bit indirect pointer + Y |
| 19 | Implied | `i` | no operand |
| 20 | Relative | `r` | 8-bit signed PC offset |
| 21 | Relative Long| `rl` | 16-bit signed PC offset |
| 22 | Stack | `s` | stack-based instructions |
| 23 | Block Move | `xyc` | src bank, dst bank operands |
| 24 | Immediate | `#` | literal value |
---
## Instructions
---
### ADC — Add with Carry
```
A = A + M + C
```
Flags: `N V . . . . Z C`
```
a=6D a,x=7D a,y=79 al=6F al,x=7F
d=65 d,s=63 d,x=75
(d)=72 [d]=67 (d,s),y=73 (d,x)=61 (d),y=71 [d],y=77
#=69
```
---
### AND — Bitwise AND
```
A = A & M
```
Flags: `N . . . . . Z .`
```
a=2D a,x=3D a,y=39 al=2F al,x=3F
d=25 d,s=23 d,x=35
(d)=32 [d]=27 (d,s),y=33 (d,x)=21 (d),y=31 [d],y=37
#=29
```
> Note: Table 5-5 PDF text shows `3E` here (OCR/print artifact); Table 5-4 opcode matrix confirms `3D`=AND a,x and `3E`=ROL a,x.
---
### ASL — Arithmetic Shift Left
```
C = M[7/15]; M = M << 1; M[0] = 0
```
Flags: `N . . . . . Z C`
```
a=0E A=0A a,x=1E d=06 d,x=16
```
---
### BCC — Branch if Carry Clear
```
if C == 0: PC += sign_extend(r)
```
Flags: `. . . . . . . .`
```
r=90
```
---
### BCS — Branch if Carry Set
```
if C == 1: PC += sign_extend(r)
```
Flags: `. . . . . . . .`
```
r=B0
```
---
### BEQ — Branch if Equal (Zero Set)
```
if Z == 1: PC += sign_extend(r)
```
Flags: `. . . . . . . .`
```
r=F0
```
---
### BIT — Bit Test
```
Z = (A & M) == 0
-- non-immediate only: --
N = M[7] (or M[15] when M=0)
V = M[6] (or M[14] when M=0)
```
Flags: `M M . . . . Z .` (immediate `#`: only Z affected — N and V unchanged)
```
a=2C a,x=3C d=24 d,x=34 #=89
```
---
### BMI — Branch if Minus (Negative Set)
```
if N == 1: PC += sign_extend(r)
```
Flags: `. . . . . . . .`
```
r=30
```
> Note: Table 5-5 shows "Branch if N=0" for both BMI and BPL, making them identical — clear datasheet typo. BMI = Branch if **Mi**nus branches when N=1 (has been so since the original 6502).
---
### BNE — Branch if Not Equal (Zero Clear)
```
if Z == 0: PC += sign_extend(r)
```
Flags: `. . . . . . . .`
```
r=D0
```
---
### BPL — Branch if Plus (Negative Clear)
```
if N == 0: PC += sign_extend(r)
```
Flags: `. . . . . . . .`
```
r=10
```
---
### BRA — Branch Always
```
PC += sign_extend(r)
```
Flags: `. . . . . . . .`
```
r=80
```
---
### BRK — Software Break
```
push(PBR, PCH, PCL, P) -- native: 3 bytes; emulation: 2 bytes
P.D = 0; P.I = 1
-- emulation: P.B = 1 --
PC = vector[$FFFE/$FFE6]
```
Flags: `. . . • 0 1 . .` (B set in emulation, D cleared, I set)
```
s=00 (followed by signature byte)
```
---
### BRL\* — Branch Long Always
```
PC += sign_extend_16(rl)
```
Flags: `. . . . . . . .`
```
rl=82
```
---
### BVC — Branch if Overflow Clear
```
if V == 0: PC += sign_extend(r)
```
Flags: `. . . . . . . .`
```
r=50
```
---
### BVS — Branch if Overflow Set
```
if V == 1: PC += sign_extend(r)
```
Flags: `. . . . . . . .`
```
r=70
```
---
### CLC — Clear Carry
```
C = 0
```
Flags: `. . . . . . . 0`
```
i=18
```
---
### CLD — Clear Decimal
```
D = 0
```
Flags: `. . . . 0 . . .`
```
i=D8
```
---
### CLI — Clear Interrupt Disable
```
I = 0
```
Flags: `. . . . . 0 . .`
```
i=58
```
---
### CLV — Clear Overflow
```
V = 0
```
Flags: `. 0 . . . . . .`
```
i=B8
```
---
### CMP — Compare Accumulator with Memory
```
temp = A - M (result discarded; flags set)
```
Flags: `N . . . . . Z C`
```
a=CD a,x=DD a,y=D9 al=CF al,x=DF
d=C5 d,s=C3 d,x=D5
(d)=D2 [d]=C7 (d,s),y=D3 (d,x)=C1 (d),y=D1 [d],y=D7
#=C9
```
---
### COP\* — Co-Processor Interrupt
```
push(PBR, PCH, PCL, P)
P.D = 0; P.I = 1
PC = vector[$FFF4/$FFE4]
```
Flags: `. . . . 0 1 . .`
```
s=02 (followed by signature byte)
```
---
### CPX — Compare X with Memory
```
temp = X - M (result discarded; flags set)
```
Flags: `N . . . . . Z C`
```
a=EC d=E4 #=E0
```
---
### CPY — Compare Y with Memory
```
temp = Y - M (result discarded; flags set)
```
Flags: `N . . . . . Z C`
```
a=CC d=C4 #=C0
```
---
### DEC — Decrement
```
M = M - 1 (or A = A - 1 for accumulator mode)
```
Flags: `N . . . . . Z .`
```
a=CE A=3A a,x=DE d=C6 d,x=D6
```
---
### DEX — Decrement X
```
X = X - 1
```
Flags: `N . . . . . Z .`
```
i=CA
```
---
### DEY — Decrement Y
```
Y = Y - 1
```
Flags: `N . . . . . Z .`
```
i=88
```
---
### EOR — Exclusive OR
```
A = A ^ M
```
Flags: `N . . . . . Z .`
```
a=4D a,x=5D a,y=59 al=4F al,x=5F
d=45 d,s=43 d,x=55
(d)=52 [d]=47 (d,s),y=53 (d,x)=41 (d),y=51 [d],y=57
#=49
```
---
### INC — Increment
```
M = M + 1 (or A = A + 1 for accumulator mode)
```
Flags: `N . . . . . Z .`
```
a=EE A=1A a,x=FE d=E6 d,x=F6
```
---
### INX — Increment X
```
X = X + 1
```
Flags: `N . . . . . Z .`
```
i=E8
```
---
### INY — Increment Y
```
Y = Y + 1
```
Flags: `N . . . . . Z .`
```
i=C8
```
---
### JML\* — Jump Long (24-bit)
```
PBR:PC = [a] (reads 3-byte pointer from absolute indirect long)
```
Flags: `. . . . . . . .`
```
[a]=DC
```
---
### JMP — Jump
```
PC = target (PBR unchanged except for al form)
```
Flags: `. . . . . . . .`
```
a=4C al=5C (a)=6C (a,x)=7C
```
---
### JSL\* — Jump to Subroutine Long
```
push(PBR, PCH, PCL) -- pushes return address - 1
PBR:PC = al
```
Flags: `. . . . . . . .`
```
al=22
```
---
### JSR — Jump to Subroutine
```
push(PCH, PCL) -- pushes return address - 1
PC = target
```
Flags: `. . . . . . . .`
```
a=20 (a,x)=FC
```
---
### LDA — Load Accumulator
```
A = M
```
Flags: `N . . . . . Z .`
```
a=AD a,x=BD a,y=B9 al=AF al,x=BF
d=A5 d,s=A3 d,x=B5
(d)=B2 [d]=A7 (d,s),y=B3 (d,x)=A1 (d),y=B1 [d],y=B7
#=A9
```
---
### LDX — Load X Register
```
X = M
```
Flags: `N . . . . . Z .`
```
a=AE a,y=BE d=A6 d,y=B6 #=A2
```
---
### LDY — Load Y Register
```
Y = M
```
Flags: `N . . . . . Z .`
```
a=AC a,x=BC d=A4 d,x=B4 #=A0
```
---
### LSR — Logical Shift Right
```
C = M[0]; M = M >> 1; M[7/15] = 0
```
Flags: `0 . . . . . Z C` (N always cleared)
```
a=4E A=4A a,x=5E d=46 d,x=56
```
---
### MVN\* — Block Move Negative (copy ascending)
```
-- repeat while C != 0xFFFF: --
DBR = dst_bank
M[DBR:Y] = M[src_bank:X]
X++; Y++; C--
-- on completion: C = 0xFFFF, DBR = dst_bank --
```
Flags: `. . . . . . . .`
```
xyc=54 (operand bytes: dst_bank, src_bank)
```
---
### MVP\* — Block Move Positive (copy descending)
```
-- repeat while C != 0xFFFF: --
DBR = dst_bank
M[DBR:Y] = M[src_bank:X]
X--; Y--; C--
-- on completion: C = 0xFFFF, DBR = dst_bank --
```
Flags: `. . . . . . . .`
```
xyc=44 (operand bytes: dst_bank, src_bank)
```
---
### NOP — No Operation
```
(nothing)
```
Flags: `. . . . . . . .`
```
i=EA
```
---
### ORA — Bitwise OR
```
Flags: `N . . . . . Z .`
```
a=0D a,x=1D a,y=19 al=0F al,x=1F
d=05 d,s=03 d,x=15
(d)=12 [d]=07 (d,s),y=13 (d,x)=01 (d),y=11 [d],y=17
#=09
```
---
### PEA\* — Push Effective Absolute Address
```
push(imm16) -- pushes literal 16-bit operand; no indirection
S -= 2
```
Flags: `. . . . . . . .`
```
s=F4 (2-byte absolute address operand)
```
---
### PEI\* — Push Effective Indirect Address
```
push(M[D+d], M[D+d+1]) -- pushes 16-bit value from direct page
S -= 2
```
Flags: `. . . . . . . .`
```
d=D4
```
---
### PER\* — Push Effective PC-Relative Address
```
push(PC + 3 + sign_extend_16(rl))
S -= 2
```
Flags: `. . . . . . . .`
```
rl=62
```
---
### PHA — Push Accumulator
```
M[S] = A; S -= 1 (S -= 2 when M=0)
```
Flags: `. . . . . . . .`
```
s=48
```
---
### PHB\* — Push Data Bank Register
```
M[S] = DBR; S -= 1
```
Flags: `. . . . . . . .`
```
s=8B
```
---
### PHD\* — Push Direct Page Register
```
M[S] = D_high; M[S-1] = D_low; S -= 2
```
Flags: `. . . . . . . .`
```
s=0B
```
---
### PHK\* — Push Program Bank Register
```
M[S] = PBR; S -= 1
```
Flags: `. . . . . . . .`
```
s=4B
```
---
### PHP — Push Processor Status
```
M[S] = P; S -= 1
```
Flags: `. . . . . . . .`
```
s=08
```
---
### PHX — Push X Register
```
M[S] = X; S -= 1 (S -= 2 when X=0)
```
Flags: `. . . . . . . .`
```
s=DA
```
---
### PHY — Push Y Register
```
M[S] = Y; S -= 1 (S -= 2 when X=0)
```
Flags: `. . . . . . . .`
```
s=5A
```
---
### PLA — Pull Accumulator
```
S += 1; A = M[S] (S += 2 when M=0)
```
Flags: `N . . . . . Z .`
```
s=68
```
---
### PLB\* — Pull Data Bank Register
```
S += 1; DBR = M[S]
```
Flags: `N . . . . . Z .`
```
s=AB
```
---
### PLD\* — Pull Direct Page Register
```
S += 2; D = M[S-1]:M[S]
```
Flags: `N . . . . . Z .`
```
s=2B
```
---
### PLP — Pull Processor Status
```
S += 1; P = M[S] -- all flags restored
```
Flags: `N V M X D 1 Z C`
```
s=28
```
---
### PLX — Pull X Register
```
S += 1; X = M[S] (S += 2 when X=0)
```
Flags: `N . . . . . Z .`
```
s=FA
```
---
### PLY — Pull Y Register
```
S += 1; Y = M[S] (S += 2 when X=0)
```
Flags: `N . . . . . Z .`
```
s=7A
```
---
### REP\* — Reset Processor Status Bits
```
P = P & ~imm -- clears bits where imm bit = 1
```
Flags: `N V M X D 1 Z C` (per mask byte)
```
#=C2
```
---
### ROL — Rotate Left through Carry
```
new_C = M[7/15]; M = (M << 1) | C; C = new_C
```
Flags: `N . . . . . Z C`
```
a=2E A=2A a,x=3E d=26 d,x=36
```
---
### ROR — Rotate Right through Carry
```
new_C = M[0]; M = (C << 7/15) | (M >> 1); C = new_C
```
Flags: `N . . . . . Z C`
```
a=6E A=6A a,x=7E d=66 d,x=76
```
---
### RTI — Return from Interrupt
```
P = M[S+1]
PCL = M[S+2]; PCH = M[S+3]
-- native mode only: PBR = M[S+4] --
S += 3 (emulation) or 4 (native)
```
Flags: `N V M X D 1 Z C` (all restored from stack)
```
s=40
```
---
### RTL\* — Return from Subroutine Long
```
PCL = M[S+1]; PCH = M[S+2]; PBR = M[S+3]
PC += 1; S += 3
```
Flags: `. . . . . . . .`
```
s=6B
```
---
### RTS — Return from Subroutine
```
PCL = M[S+1]; PCH = M[S+2]; PC += 1; S += 2
```
Flags: `. . . . . . . .`
```
s=60
```
---
### SBC — Subtract with Borrow (Carry)
```
A = A - M - (1 - C)
```
Flags: `N V . . . . Z C`
```
a=ED a,x=FD a,y=F9 al=EF al,x=FF
d=E5 d,s=E3 d,x=F5
(d)=F2 [d]=E7 (d,s),y=F3 (d,x)=E1 (d),y=F1 [d],y=F7
#=E9
```
> Note: `al=EF` was missing from Table 5-5 PDF text; confirmed present in Table 5-4 opcode matrix (row E, col F).
---
### SEC — Set Carry
```
C = 1
```
Flags: `. . . . . . . 1`
```
i=38
```
---
### SED — Set Decimal
```
D = 1
```
Flags: `. . . . 1 . . .`
```
i=F8
```
---
### SEI — Set Interrupt Disable
```
I = 1
```
Flags: `. . . . . 1 . .`
```
i=78
```
---
### SEP\* — Set Processor Status Bits
```
Flags: `N V M X D 1 Z C` (per mask byte)
```
#=E2
```
---
### STA — Store Accumulator
```
M = A
```
Flags: `. . . . . . . .`
```
a=8D a,x=9D a,y=99 al=8F al,x=9F
d=85 d,s=83 d,x=95
(d)=92 [d]=87 (d,s),y=93 (d,x)=81 (d),y=91 [d],y=97
```
> Note: `a,y=99` was missing from Table 5-5 PDF text; confirmed present in Table 5-4 opcode matrix (row 9, col 9).
---
### STP — Stop the Clock
```
halt clock until RESB asserted
```
Flags: `. . . . . . . .`
```
i=DB
```
> Note: Table 5-5 PDF text shows `D8` here (D8 is CLD); Table 5-4 opcode matrix confirms `DB`=STP (row D, col B).
---
### STX — Store X Register
```
M = X
```
Flags: `. . . . . . . .`
```
a=8E d=86 d,y=96
```
---
### STY — Store Y Register
```
M = Y
```
Flags: `. . . . . . . .`
```
a=8C d=84 d,x=94
```
---
### STZ — Store Zero
```
M = 0
```
Flags: `. . . . . . . .`
```
a=9C a,x=9E d=64 d,x=74
```
---
### TAX — Transfer Accumulator to X
```
X = A
```
Flags: `N . . . . . Z .`
```
i=AA
```
---
### TAY — Transfer Accumulator to Y
```
Y = A
```
Flags: `N . . . . . Z .`
```
i=A8
```
> Note: Table 5-5 PDF text shows `AB` here (AB is PLB); Table 5-4 opcode matrix confirms `A8`=TAY (row A, col 8).
---
### TCD\* — Transfer 16-bit Accumulator (C) to Direct Page
```
D = C -- always 16-bit regardless of M flag
```
Flags: `N . . . . . Z .`
```
i=5B
```
---
### TCS\* — Transfer 16-bit Accumulator (C) to Stack Pointer
```
S = C -- always 16-bit; no flags affected
```
Flags: `. . . . . . . .`
```
i=1B
```
---
### TDC\* — Transfer Direct Page to 16-bit Accumulator
```
C = D -- always 16-bit regardless of M flag
```
Flags: `N . . . . . Z .`
```
i=7B
```
---
### TRB — Test and Reset Bits
```
Z = (A & M) == 0
M = M & ~A
```
Flags: `. . . . . . Z .`
```
a=1C d=14
```
---
### TSB — Test and Set Bits
```
Z = (A & M) == 0
Flags: `. . . . . . Z .`
```
a=0C d=04
```
---
### TSC\* — Transfer Stack Pointer to 16-bit Accumulator
```
C = S -- always 16-bit regardless of M flag
```
Flags: `N . . . . . Z .`
```
i=3B
```
---
### TSX — Transfer Stack Pointer to X
```
X = S -- width controlled by X flag
```
Flags: `N . . . . . Z .`
```
i=BA
```
---
### TXA — Transfer X to Accumulator
```
A = X -- width controlled by M/X flags
```
Flags: `N . . . . . Z .`
```
i=8A
```
---
### TXS — Transfer X to Stack Pointer
```
S = X -- no flags affected
-- native: S = X (16-bit); emulation: SH = 01, SL = XL
```
Flags: `. . . . . . . .`
```
i=9A
```
---
### TXY\* — Transfer X to Y
```
Y = X
```
Flags: `N . . . . . Z .`
```
i=9B
```
---
### TYA — Transfer Y to Accumulator
```
A = Y -- width controlled by M/X flags
```
Flags: `N . . . . . Z .`
```
i=98
```
---
### TYX\* — Transfer Y to X
```
X = Y
```
Flags: `N . . . . . Z .`
```
i=BB
```
---
### WAI — Wait for Interrupt
```
RDY = 0 -- halt until RESB/ABORTB/NMIB/IRQB asserted
```
Flags: `. . . . . . . .`
```
i=CB
```
---
### WDM\* — Reserved (No Operation)
```
(reserved for future use; behaves as NOP)
```
Flags: `. . . . . . . .`
```
i=42 (followed by 1 signature byte)
```
---
### XBA\* — Exchange B and A Accumulators
```
temp = A_low; A_low = A_high; A_high = temp
-- flags set based on new A_low (the old A_high) --
```
Flags: `N . . . . . Z .`
```
i=EB
```
---
### XCE\* — Exchange Carry and Emulation Bit
```
temp = C; C = E; E = temp
-- E=0: native mode; E=1: 6502 emulation mode --
-- switching to emulation forces M=1, X=1 --
```
Flags: `. . . . . . . E` (C becomes old E; shown in C column as `E`)
```
i=FB
```
---
## Quick Opcode Index (hex → mnemonic)
| 00 | BRK | s || 01 | ORA | (d,x) |
| 02 | COP* | s || 03 | ORA | d,s |
| 04 | TSB | d || 05 | ORA | d |
| 06 | ASL | d || 07 | ORA | [d] |
| 08 | PHP | s || 09 | ORA | # |
| 0A | ASL | A || 0B | PHD* | s |
| 0C | TSB | a || 0D | ORA | a |
| 0E | ASL | a || 0F | ORA | al |
| 10 | BPL | r || 11 | ORA | (d),y |
| 12 | ORA | (d) || 13 | ORA | (d,s),y |
| 14 | TRB | d || 15 | ORA | d,x |
| 16 | ASL | d,x || 17 | ORA | [d],y |
| 18 | CLC | i || 19 | ORA | a,y |
| 1A | INC | A || 1B | TCS* | i |
| 1C | TRB | a || 1D | ORA | a,x |
| 1E | ASL | a,x || 1F | ORA | al,x |
| 20 | JSR | a || 21 | AND | (d,x) |
| 22 | JSL* | al || 23 | AND | d,s |
| 24 | BIT | d || 25 | AND | d |
| 26 | ROL | d || 27 | AND | [d] |
| 28 | PLP | s || 29 | AND | # |
| 2A | ROL | A || 2B | PLD* | s |
| 2C | BIT | a || 2D | AND | a |
| 2E | ROL | a || 2F | AND | al |
| 30 | BMI | r || 31 | AND | (d),y |
| 32 | AND | (d) || 33 | AND | (d,s),y |
| 34 | BIT | d,x || 35 | AND | d,x |
| 36 | ROL | d,x || 37 | AND | [d],y |
| 38 | SEC | i || 39 | AND | a,y |
| 3A | DEC | A || 3B | TSC* | i |
| 3C | BIT | a,x || 3D | AND | a,x |
| 3E | ROL | a,x || 3F | AND | al,x |
| 40 | RTI | s || 41 | EOR | (d,x) |
| 42 | WDM* | i || 43 | EOR | d,s |
| 44 | MVP* | xyc || 45 | EOR | d |
| 46 | LSR | d || 47 | EOR | [d] |
| 48 | PHA | s || 49 | EOR | # |
| 4A | LSR | A || 4B | PHK* | s |
| 4C | JMP | a || 4D | EOR | a |
| 4E | LSR | a || 4F | EOR | al |
| 50 | BVC | r || 51 | EOR | (d),y |
| 52 | EOR | (d) || 53 | EOR | (d,s),y |
| 54 | MVN* | xyc || 55 | EOR | d,x |
| 56 | LSR | d,x || 57 | EOR | [d],y |
| 58 | CLI | i || 59 | EOR | a,y |
| 5A | PHY | s || 5B | TCD* | i |
| 5C | JMP | al || 5D | EOR | a,x |
| 5E | LSR | a,x || 5F | EOR | al,x |
| 60 | RTS | s || 61 | ADC | (d,x) |
| 62 | PER* | rl || 63 | ADC | d,s |
| 64 | STZ | d || 65 | ADC | d |
| 66 | ROR | d || 67 | ADC | [d] |
| 68 | PLA | s || 69 | ADC | # |
| 6A | ROR | A || 6B | RTL* | s |
| 6C | JMP | (a) || 6D | ADC | a |
| 6E | ROR | a || 6F | ADC | al |
| 70 | BVS | r || 71 | ADC | (d),y |
| 72 | ADC | (d) || 73 | ADC | (d,s),y |
| 74 | STZ | d,x || 75 | ADC | d,x |
| 76 | ROR | d,x || 77 | ADC | [d],y |
| 78 | SEI | i || 79 | ADC | a,y |
| 7A | PLY | s || 7B | TDC* | i |
| 7C | JMP | (a,x) || 7D | ADC | a,x |
| 7E | ROR | a,x || 7F | ADC | al,x |
| 80 | BRA | r || 81 | STA | (d,x) |
| 82 | BRL* | rl || 83 | STA | d,s |
| 84 | STY | d || 85 | STA | d |
| 86 | STX | d || 87 | STA | [d] |
| 88 | DEY | i || 89 | BIT | # |
| 8A | TXA | i || 8B | PHB* | s |
| 8C | STY | a || 8D | STA | a |
| 8E | STX | a || 8F | STA | al |
| 90 | BCC | r || 91 | STA | (d),y |
| 92 | STA | (d) || 93 | STA | (d,s),y |
| 94 | STY | d,x || 95 | STA | d,x |
| 96 | STX | d,y || 97 | STA | [d],y |
| 98 | TYA | i || 99 | STA | a,y |
| 9A | TXS | i || 9B | TXY* | i |
| 9C | STZ | a || 9D | STA | a,x |
| 9E | STZ | a,x || 9F | STA | al,x |
| A0 | LDY | # || A1 | LDA | (d,x) |
| A2 | LDX | # || A3 | LDA | d,s |
| A4 | LDY | d || A5 | LDA | d |
| A6 | LDX | d || A7 | LDA | [d] |
| A8 | TAY | i || A9 | LDA | # |
| AA | TAX | i || AB | PLB* | s |
| AC | LDY | a || AD | LDA | a |
| AE | LDX | a || AF | LDA | al |
| B0 | BCS | r || B1 | LDA | (d),y |
| B2 | LDA | (d) || B3 | LDA | (d,s),y |
| B4 | LDY | d,x || B5 | LDA | d,x |
| B6 | LDX | d,y || B7 | LDA | [d],y |
| B8 | CLV | i || B9 | LDA | a,y |
| BA | TSX | i || BB | TYX* | i |
| BC | LDY | a,x || BD | LDA | a,x |
| BE | LDX | a,y || BF | LDA | al,x |
| C0 | CPY | # || C1 | CMP | (d,x) |
| C2 | REP* | # || C3 | CMP | d,s |
| C4 | CPY | d || C5 | CMP | d |
| C6 | DEC | d || C7 | CMP | [d] |
| C8 | INY | i || C9 | CMP | # |
| CA | DEX | i || CB | WAI | i |
| CC | CPY | a || CD | CMP | a |
| CE | DEC | a || CF | CMP | al |
| D0 | BNE | r || D1 | CMP | (d),y |
| D2 | CMP | (d) || D3 | CMP | (d,s),y |
| D4 | PEI* | d || D5 | CMP | d,x |
| D6 | DEC | d,x || D7 | CMP | [d],y |
| D8 | CLD | i || D9 | CMP | a,y |
| DA | PHX | s || DB | STP | i |
| DC | JML* | [a] || DD | CMP | a,x |
| DE | DEC | a,x || DF | CMP | al,x |
| E0 | CPX | # || E1 | SBC | (d,x) |
| E2 | SEP* | # || E3 | SBC | d,s |
| E4 | CPX | d || E5 | SBC | d |
| E6 | INC | d || E7 | SBC | [d] |
| E8 | INX | i || E9 | SBC | # |
| EA | NOP | i || EB | XBA* | i |
| EC | CPX | a || ED | SBC | a |
| EE | INC | a || EF | SBC | al |
| F0 | BEQ | r || F1 | SBC | (d),y |
| F2 | SBC | (d) || F3 | SBC | (d,s),y |
| F4 | PEA* | s || F5 | SBC | d,x |
| F6 | INC | d,x || F7 | SBC | [d],y |
| F8 | SED | i || F9 | SBC | a,y |
| FA | PLX | s || FB | XCE* | i |
| FC | JSR | (a,x) || FD | SBC | a,x |
| FE | INC | a,x || FF | SBC | al,x |