vj 0.2.0

vj: a SystemVerilog (IEEE 1800-2023) simulator built on slang and LLVM.
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//! VPI (IEEE 1800-2023 Clauses 36-39), as `vj run` sees it.
//!
//! The runtime half (handle table, callbacks, value access, system tasks, the
//! exported `vpi_*` entry points, the object model) lives in the slang-free
//! `vj-vpi` crate, which an AOT-built `.so` links too; it is re-exported
//! here under its historical paths. Only [`build`], which fills the model from
//! the elaborated design, needs slang and stays in this crate.

pub use vj_vpi::*;

pub mod build;

/// [`systf::prepare`] with the declarations in the frontend's own types.
pub fn prepare_systf(
    src: &str,
) -> (
    String,
    Vec<vj_codegen::frontend::SystfDeclaration>,
    Vec<vj_exec::vpi_data::SysTfDecl>,
) {
    use sv_lang::SystemFunctionType;
    use systf::RetType;
    use vj_codegen::frontend::SystfReturn;
    let (src, decls, codegen) = systf::prepare(src);
    let decls = decls
        .into_iter()
        .map(|(name, ret, arity)| {
            let ret = match ret {
                RetType::Void => SystfReturn::Typed(SystemFunctionType::Void),
                RetType::Real => SystfReturn::Typed(SystemFunctionType::Real),
                RetType::Integer => SystfReturn::Typed(SystemFunctionType::Integer),
                RetType::Time => SystfReturn::Typed(SystemFunctionType::Time),
                RetType::Sized { width, signed } => SystfReturn::Sized { width, signed },
            };
            (name, ret, arity)
        })
        .collect();
    (src, decls, codegen)
}