vj-sim 0.3.0

Netlist, scheduler and process model of the vj SystemVerilog simulator.
Documentation 
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//! The engine's host hook: what an embedder (VPI, `vj`'s `vpi`)
//! needs to run its own code at the scheduling points of IEEE 1800-2023
//! 4.4 / 38.36.2 -- the start of a time slot, after activity inside it, when
//! its active/NBA loop settles (read-write synch, with a loop back if the
//! host wrote something), and at its read-only end -- plus timers that make
//! time advance to a tick with no design event.
//!
//! Every hook gets the engine's own [`SchedulerOps`], also installed as the
//! current ops for its duration, so a host write (`commit_blocking_write`)
//! wakes processes exactly as a compiled process's write does. With no host
//! installed every hook point is a single `Option` check.

use super::SchedulerOps;

pub trait Host {
    /// The earliest tick the host needs the run to reach (a pending timer),
    /// if any. Time advances to it even when no design event is due.
    fn next_wakeup(&self) -> Option<u64>;
    /// A time slot begins (also the run's first slot), before its Active
    /// region runs.
    fn slot_begin(&mut self, ops: &dyn SchedulerOps);
    /// After a batch of activity in the current slot (an Active/Inactive
    /// dispatch or an NBA commit): value changes are reported here.
    fn activity(&mut self, ops: &dyn SchedulerOps);
    /// Just before the NBA region commits.
    fn nba_synch(&mut self, ops: &dyn SchedulerOps);
    /// The slot's active/NBA loop settled. Returns `true` when the host did
    /// something that may wake processes; the loop then runs again.
    fn rw_synch(&mut self, ops: &dyn SchedulerOps) -> bool;
    /// The slot is over except for its read-only end: end of time slot,
    /// then the read-only synch point (no writes allowed).
    fn slot_end(&mut self, ops: &dyn SchedulerOps);
}