vj-sim 0.3.0

Netlist, scheduler and process model of the vj SystemVerilog simulator.
Documentation 
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//! Functional coverage (IEEE 1800-2023 Clause 19): the pure model.
//!
//! This module knows nothing about the simulator, LLVM or sv-lang. It is the
//! executable form of the clause: a covergroup *declaration* (bins, options,
//! crosses) is instantiated with constructor arguments into an *instance* that
//! counts samples and answers coverage queries. Everything design-dependent is
//! reached through the [`value::Eval`] trait, so every rule of 19.5-19.11 is
//! unit-testable here with no design at all. The codegen/runtime wiring that
//! feeds real sampled values in lives in `vj-codegen`/`vj-runtime`
//! (see `docs/superpowers/plans/2026-10-04-coverage.md`).
//!
//! Named `covergroup` (not `coverage`) to stay clear of construct coverage.

pub mod bins;
pub mod compute;
pub mod coverpoint;
pub mod cross;
pub mod db;
pub mod decl;
pub mod instance;
pub mod intset;
pub mod options;
pub mod registry;
pub mod trans;
pub mod value;

#[cfg(test)]
mod tests;
#[cfg(test)]
mod tests_compute;
#[cfg(test)]
mod tests_cross;
#[cfg(test)]
mod tests_db;
#[cfg(test)]
mod tests_trans;