vj-sim 0.2.0

Netlist, scheduler and process model of the vj SystemVerilog simulator.
Documentation
//! SVA (concurrent assertions, Clause 16/17) runtime support
//! (`docs/superpowers/plans/2026-10-03-sva.md`).
//!
//! Task 4: [`ir`] is the automaton IR skeleton -- the static transition-table
//! shape plan §1.2 decided on (a dedicated, interpreted automaton per
//! assertion, not a second CPS lowering) -- types only, no builder yet.
//! `vj-codegen::sva` (T3's `ranges`, T4's `op`) is this module's
//! frontend-facing sibling: it recovers the data (delay/repetition bounds,
//! the operator mirror, positional children) that a later task's builder
//! (T9/T10 onward) will consult to actually populate an [`ir::Transition`]
//! table. This module itself has no `sv-lang` dependency at all -- unlike
//! `vj-codegen::sva`, which is frontend-only by construction, these IR
//! types are the pure, elaboration-independent shape the automaton engine
//! (`vj-runtime::sva_engine`, not yet built) interprets, so they need
//! no `#[cfg(feature = "frontend")]` gate.
//!
//! Task 7: [`clock`] *does* need `sv-lang` (it queries `sv_lang::Analysis`/
//! `AnalyzedAssertion` directly, per plan §1.1/§1.6) -- gated behind this
//! crate's `frontend` feature, the same split `crate::analysis` already
//! uses for its own `sv-lang`-dependent submodules.
pub mod codec;
pub mod engine;
pub mod future;
pub mod incremental;
pub mod ir;
pub mod property;
pub mod trace;
pub mod wide;

#[cfg(feature = "frontend")]
pub mod endpoint;
#[cfg(feature = "frontend")]
pub mod global_clock;
#[cfg(feature = "frontend")]
pub mod sampled;

#[cfg(feature = "frontend")]
mod clock;
#[cfg(feature = "frontend")]
pub use clock::{clock_of, has_no_clock_error, has_non_unique_clock_error, semantic_leading_clock};