vj-sim 0.2.0

Netlist, scheduler and process model of the vj SystemVerilog simulator.
Documentation
//! `vj-sim`: the netlist/analysis/state/scheduler/process/determinism kernel
//! (ARCHITECTURE.md §3, §6.2-6.5).
//!
//! This wave materializes only the cross-track contract surface each module
//! exposes to the others and to `vj-codegen`/`vj-runtime`/`vj-debug`
//! (types, traits, `#[repr(C)]` ABI-adjacent shapes) — the tracks that own each
//! module (state, sched, netlist, A2-process, and the determinism face-off winner)
//! fill in the real elaboration/scheduling/rollback logic in later waves. See
//! `docs/CONTRACTS.md` for the full item -> owning-track -> consumer -> ledger-id
//! table.

pub mod analysis;
pub mod collections;
pub mod constraints;
pub mod covergroup;
pub mod determinism;
pub mod dpi_task;
pub mod driver_counts;
pub mod fiber;
pub mod image;
pub mod netlist;
// Classes plan (`docs/superpowers/plans/2026-10-03-classes.md`) Task 3: the
// object heap runtime. Pure Rust, no sv-lang dependency (like `collections`
// just above) — unconditional, not behind the `frontend` feature, so
// `vj-runtime` (which depends on this crate with `default-features =
// false`) can use it once Tasks 5+ wire codegen's calls to it.
pub mod objects;
pub mod process;
pub mod winref;
// Pattern matching (LRM 12.6): the pattern-variable discovery the declared-locals
// scans share.
#[cfg(feature = "frontend")]
pub mod patterns;
pub mod sched;
pub mod state;
pub mod strings;
pub mod sva;
pub mod symid;
pub mod timing_types;