vj-codegen 0.1.0

LLVM code generator of the vj SystemVerilog simulator.
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//! sv-sim codegen: SV -> LLVM lowering (P0: leaf functions, 4-state, JIT).
pub mod accessor;
pub mod aot;
pub(crate) mod array_methods;
pub(crate) mod arrays;
pub mod assert_site;
pub(crate) mod class_events;
pub mod classes;
pub mod classes_randomize;
pub(crate) mod collections;
pub mod counter_fixture;
pub mod coverage;
pub mod covergroup;
pub mod dedup;
pub mod deferred_call;
pub mod dpi;
pub mod error;
pub(crate) mod events;
pub mod expr;
pub mod fileio;
pub mod force;
pub mod frontend;
pub mod func;
pub mod huge;
pub mod jit;
pub mod jit_split;
pub mod kind_counts;
pub mod let_order;
pub mod mangle;
pub mod module;
pub mod nettype;
pub mod ops;
pub mod orc;
pub mod pipeline;
pub mod pla;
pub mod process_lower;
pub(crate) mod rand_mode;
pub mod randomize_scope;
pub mod real;
pub(crate) mod sampled;
pub(crate) mod scope_randomize;
pub mod select;
pub mod session;
pub mod stmt_shared;
pub mod stmtcov;
pub mod stream;
pub(crate) mod stream_with;
pub mod strings;
pub(crate) mod sva;
/// The compiled halves of the static concurrent assertions (plan T29).
pub use sva::emit as assertion;
/// The assertion-expression decoders the VPI model reuses to describe a
/// property's structure (37.52): operators, child splits, ranges.
pub mod sva_shape {
    pub use super::sva::{op, ranges, trees};
}
pub(crate) mod sysfunc;
pub mod systask;
pub(crate) mod tagged;
pub mod timescale;
pub mod timing;
pub mod types;
pub mod value;
pub mod vif;
pub mod vpi_dyn;
pub mod vpi_systf;