veryl-std 0.20.3

A modern hardware description language
Documentation 
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pub proto module synchronizer #(
    param WIDTH        : u32        = 8 ,
    param INITIAL_VALUE: bit<WIDTH> = '0,
    param STAGES       : u32        = 2 ,
) (
    i_clk: input  'd clock       ,
    i_rst: input  'd reset       ,
    i_d  : input  's logic<WIDTH>,
    o_d  : output 'd logic<WIDTH>,
);