veryl-std 0.20.3

A modern hardware description language
Documentation 
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#[test(test_binary_mux)]
module test_binary_mux {
    inst u_clock: $tb::clock_gen;

    var s: logic<4>    ;
    var a: logic<16, 4>;
    var b: logic<4>    ;
    var c: logic<16, 4>;

    inst u_mux: mux #(
        WIDTH  : 4                                  ,
        ENTRIES: 16                                 ,
        KIND   : selector_pkg::selector_kind::BINARY,
    ) (
        i_select: s,
        i_data  : a,
        o_data  : b,
    );

    inst u_demux: demux #(
        WIDTH  : 4                                  ,
        ENTRIES: 16                                 ,
        KIND   : selector_pkg::selector_kind::BINARY,
    ) (
        i_select: s,
        i_data  : b,
        o_data  : c,
    );

    initial {
        for i in 0..16 {
            a[i] = (i + 1) as 4;
        }

        for i in 0..16 {
            s = i;
            u_clock.next(1);

            for j in 0..16 {
                let exp: logic<4> = if j == i ? a[j] : 0;
                $assert(c[j] == exp);
            }
        }

        $finish();
    }
}

#[test(test_vector_mux)]
module test_vector_mux {
    inst u_clock: $tb::clock_gen;

    var s: logic<16>   ;
    var a: logic<16, 4>;
    var b: logic<4>    ;
    var c: logic<16, 4>;

    inst u_mux: mux #(
        WIDTH  : 4                                  ,
        ENTRIES: 16                                 ,
        KIND   : selector_pkg::selector_kind::VECTOR,
    ) (
        i_select: s,
        i_data  : a,
        o_data  : b,
    );

    inst u_demux: demux #(
        WIDTH  : 4                                  ,
        ENTRIES: 16                                 ,
        KIND   : selector_pkg::selector_kind::VECTOR,
    ) (
        i_select: s,
        i_data  : b,
        o_data  : c,
    );

    initial {
        for i in 0..16 {
            a[i] = (i + 1) as 4;
        }

        for i in 0..16 {
            s = 1 << i;
            u_clock.next(1);

            for j in 0..16 {
                let exp: logic<4> = if j == i ? a[j] : 0;
                $assert(c[j] == exp);
            }
        }

        $finish();
    }
}

#[test(test_onehot_mux)]
module test_onehot_mux {
    inst u_clock: $tb::clock_gen;

    var s: logic<16>   ;
    var a: logic<16, 4>;
    var b: logic<4>    ;
    var c: logic<16, 4>;

    inst u_mux: mux #(
        WIDTH  : 4                                  ,
        ENTRIES: 16                                 ,
        KIND   : selector_pkg::selector_kind::ONEHOT,
    ) (
        i_select: s,
        i_data  : a,
        o_data  : b,
    );

    inst u_demux: demux #(
        WIDTH  : 4                                  ,
        ENTRIES: 16                                 ,
        KIND   : selector_pkg::selector_kind::ONEHOT,
    ) (
        i_select: s,
        i_data  : b,
        o_data  : c,
    );

    initial {
        for i in 0..16 {
            a[i] = (i + 1) as 4;
        }

        for i in 0..16 {
            s = 1 << i;
            u_clock.next(1);

            for j in 0..16 {
                let exp: logic<4> = if j == i ? a[j] : 0;
                $assert(c[j] == exp);
            }
        }

        $finish();
    }
}