///### AXI4 bus package prototype
pub proto package axi4_prototype {
const ADDRESS_WIDTH : u32;
const DATA_WIDTH_BYTES: u32;
const NUM_BURSTS_LEN : u32;
const LOCK_LEN : u32;
const QOS_LEN : u32;
const REGION_LEN : u32;
const ID_LENGTH : u32;
const AWUSER_LENGTH : u32;
const WUSER_LENGTH : u32;
const BUSER_LENGTH : u32;
const ARUSER_LENGTH : u32;
const RUSER_LENGTH : u32;
type addr_t ;
type data_t ;
type strb_t ;
type num_bursts_t;
type lock_t ;
type qos_t ;
type region_t ;
type id_t ;
type awuser_t ;
type wuser_t ;
type buser_t ;
type aruser_t ;
type ruser_t ;
type size_t ;
type burst_t ;
type wcache_t;
type rcache_t;
type proto_t ;
type resp_t ;
}
///### AXI3 bus package prototype
pub proto package axi3_prototype {
const ADDRESS_WIDTH : u32;
const DATA_WIDTH_BYTES: u32;
const NUM_BURSTS_LEN : u32;
const LOCK_LEN : u32;
const ID_LENGTH : u32;
type addr_t ;
type data_t ;
type strb_t ;
type num_bursts_t;
type lock_t ;
type id_t ;
type size_t ;
type burst_t;
type cache_t;
type proto_t;
type resp_t ;
}
///### AXI4-Lite bus package prototype
pub proto package axi4_lite_prototype {
const ADDRESS_WIDTH : u32;
const DATA_WIDTH_BYTES: u32;
type addr_t ;
type data_t ;
type strb_t ;
type id_t ;
type proto_t ;
type resp_t ;
}
///### AXI4-Stream bus package prototype
pub proto package axi4_stream_prototype {
const TDATA_WIDTH : u32;
const TDATA_WIDTH_BYTES: u32;
const TDEST_WIDTH : u32;
const TID_WIDTH : u32;
const TUSER_WIDTH : u32;
type data_t ;
type dest_t ;
type id_t ;
type keep_t ;
type strb_t ;
type user_t ;
}
///### AXI4 configuration definitions
pub package axi4_config {
enum axsize_variants: logic<3> {
BYTES_PER_TRANSFER_1 = 3'b000,
BYTES_PER_TRANSFER_2 = 3'b001,
BYTES_PER_TRANSFER_4 = 3'b010,
BYTES_PER_TRANSFER_8 = 3'b011,
BYTES_PER_TRANSFER_16 = 3'b100,
BYTES_PER_TRANSFER_32 = 3'b101,
BYTES_PER_TRANSFER_64 = 3'b110,
BYTES_PER_TRANSFER_128 = 3'b111,
}
enum axburst_variants: logic<2> {
FIXED_BURST = 2'b00,
INCREMENTING_BURST = 2'b01,
WRAPPING_BURST = 2'b10,
}
struct awcache_bits {
allocate : logic,
other_allocate: logic,
modifiable : logic,
bufferable : logic,
}
struct arcache_bits {
other_allocate: logic,
allocate : logic,
modifiable : logic,
bufferable : logic,
}
struct axprot_bits {
instruction_access: logic,
non_secure : logic,
privileged : logic,
}
enum resp_variants: logic<2> {
OKAY = 2'b00,
EXOKAY = 2'b01,
SLVERR = 2'b10,
DECERR = 2'b11,
}
}
///### AXI4 bus package
pub package axi4_pkg::<
ADDR_W : u32,
DATA_W_BYTES: u32,
ID_W : u32,
AWUSER_W : u32,
WUSER_W : u32,
BUSER_W : u32,
ARUSER_W : u32,
RUSER_W : u32,
> for axi4_prototype {
const ADDRESS_WIDTH : u32 = ADDR_W;
const DATA_WIDTH_BYTES: u32 = DATA_W_BYTES;
const NUM_BURSTS_LEN : u32 = 8;
const LOCK_LEN : u32 = 1;
const QOS_LEN : u32 = 4;
const REGION_LEN : u32 = 4;
const ID_LENGTH : u32 = ID_W;
const AWUSER_LENGTH : u32 = AWUSER_W;
const WUSER_LENGTH : u32 = WUSER_W;
const BUSER_LENGTH : u32 = BUSER_W;
const ARUSER_LENGTH : u32 = ARUSER_W;
const RUSER_LENGTH : u32 = RUSER_W;
type addr_t = logic<ADDRESS_WIDTH> ;
type data_t = logic<(DATA_WIDTH_BYTES * 8)>;
type strb_t = logic<DATA_WIDTH_BYTES> ;
type num_bursts_t = logic<NUM_BURSTS_LEN> ;
type lock_t = logic<LOCK_LEN> ;
type qos_t = logic<QOS_LEN> ;
type region_t = logic<REGION_LEN> ;
type id_t = logic<ID_LENGTH> ;
type awuser_t = logic<AWUSER_LENGTH> ;
type wuser_t = logic<WUSER_LENGTH> ;
type buser_t = logic<BUSER_LENGTH> ;
type aruser_t = logic<ARUSER_LENGTH> ;
type ruser_t = logic<RUSER_LENGTH> ;
type size_t = axi4_config::axsize_variants ;
type burst_t = axi4_config::axburst_variants;
type wcache_t = axi4_config::awcache_bits ;
type rcache_t = axi4_config::arcache_bits ;
type proto_t = axi4_config::axprot_bits ;
type resp_t = axi4_config::resp_variants ;
}
///### AXI3 configuration definitions
pub package axi3_config {
enum axsize_variants: logic<3> {
BYTES_PER_TRANSFER_1 = 3'b000,
BYTES_PER_TRANSFER_2 = 3'b001,
BYTES_PER_TRANSFER_4 = 3'b010,
BYTES_PER_TRANSFER_8 = 3'b011,
BYTES_PER_TRANSFER_16 = 3'b100,
BYTES_PER_TRANSFER_32 = 3'b101,
BYTES_PER_TRANSFER_64 = 3'b110,
BYTES_PER_TRANSFER_128 = 3'b111,
}
enum axburst_variants: logic<2> {
FIXED_BURST = 2'b00,
INCREMENTING_BURST = 2'b01,
WRAPPING_BURST = 2'b10,
}
struct axcache_bits {
write_allocate: logic,
read_allocate : logic,
cacheable : logic,
bufferable : logic,
}
struct axprot_bits {
instruction_access: logic,
non_secure : logic,
privileged : logic,
}
enum resp_variants: logic<2> {
OKAY = 2'b00,
EXOKAY = 2'b01,
SLVERR = 2'b10,
DECERR = 2'b11,
}
}
///### AXI3 bus package
pub package axi3_pkg::<ADDR_W: u32, DATA_W_BYTES: u32, ID_W: u32> for axi3_prototype {
const ADDRESS_WIDTH : u32 = ADDR_W;
const DATA_WIDTH_BYTES: u32 = DATA_W_BYTES;
const NUM_BURSTS_LEN : u32 = 4;
const LOCK_LEN : u32 = 2;
const ID_LENGTH : u32 = ID_W;
type addr_t = logic<ADDRESS_WIDTH> ;
type data_t = logic<(DATA_WIDTH_BYTES * 8)>;
type strb_t = logic<DATA_WIDTH_BYTES> ;
type num_bursts_t = logic<NUM_BURSTS_LEN> ;
type lock_t = logic<LOCK_LEN> ;
type id_t = logic<ID_LENGTH> ;
type size_t = axi3_config::axsize_variants ;
type burst_t = axi3_config::axburst_variants;
type cache_t = axi3_config::axcache_bits ;
type proto_t = axi3_config::axprot_bits ;
type resp_t = axi3_config::resp_variants ;
}
///### AXI4-Lite configuration definitions
pub package axi4_lite_config {
struct axprot_bits {
instruction_access: logic,
non_secure : logic,
privileged : logic,
}
enum resp_variants: logic<2> {
OKAY = 2'b00,
EXOKAY = 2'b01,
SLVERR = 2'b10,
DECERR = 2'b11,
}
}
///### AXI4-Lite bus package
pub package axi4_lite_pkg::<ADDR_W: u32, DATA_W_BYTES: u32, ID_W: u32> for axi4_lite_prototype {
const ADDRESS_WIDTH : u32 = ADDR_W;
const DATA_WIDTH_BYTES: u32 = DATA_W_BYTES;
const ID_LENGTH : u32 = ID_W;
type addr_t = logic<ADDRESS_WIDTH> ;
type data_t = logic<(DATA_WIDTH_BYTES * 8)>;
type strb_t = logic<DATA_WIDTH_BYTES> ;
type id_t = logic<ID_LENGTH>;
type proto_t = axi4_lite_config::axprot_bits ;
type resp_t = axi4_lite_config::resp_variants;
}
///### AXI4-Stream bus package
pub package axi4_stream_pkg::<DATA_W_BYTES: u32, DEST_W: u32, ID_W: u32, USER_W: u32> for axi4_stream_prototype {
const TDATA_WIDTH : u32 = (DATA_W_BYTES * 8);
const TDATA_WIDTH_BYTES: u32 = DATA_W_BYTES;
const TDEST_WIDTH : u32 = DEST_W;
const TID_WIDTH : u32 = ID_W;
const TUSER_WIDTH : u32 = USER_W;
type data_t = logic<TDATA_WIDTH> ;
type dest_t = logic<TDEST_WIDTH> ;
type id_t = logic<TID_WIDTH> ;
type keep_t = logic<TDATA_WIDTH_BYTES>;
type strb_t = logic<TDATA_WIDTH_BYTES>;
type user_t = logic<TUSER_WIDTH> ;
}