///### AXI4 bus interface
///
///#### Modports:
///* master - AXI Master IP
///
///* slave - AXI slave IP
///
///* monitor - Debugging - All signals are declared as input
///
///* write_master - Reduced signal count for master IP that only writes to slave
///
///* read_master - Reduced signal count for master IP that only reads from slave
///
///* write_slave - Reduced signal count for slave IP that only receives writes from master
///
///* read_slave - Reduced signal count for slave IP that only replies to read requests from master
///
///#### Convenience functions:
///* awaddr_ack() = awready && awvalid
///
///* wdata_ack() = wready && wvalid
///
///* bresp_ack() = bready && bvalid
///
///* araddr_ack() = arready && arvalid
///
///* rdata_ack() = rready && rvalid
///
///#### Instantiation:
///```
///inst a: axi4_if::< axi4_pkg::< ADDR_W, DATA_W_BYTES, ID_W,
/// AWUSER_W, WUSER_W, BUSER_W,
/// ARUSER_W, RUSER_W > >;
///```
///#### Usage in module definition with modport:
///```
///module my_axi4_slave ( aclk: input clock_posedge,
/// aresetn: input reset_sync_low,
/// axi: modport axi4_if::<axi4_pkg::<32, 4, 8,
/// 8, 8, 8,
/// 8, 8>>::slave ) {
///
///}
///```
pub interface axi4_if::<PKG: axi4_prototype> {
import PKG::*;
//Write address channel
var awvalid : logic ;
var awready : logic ;
var awaddr : addr_t ;
var awsize : size_t ;
var awburst : burst_t ;
var awcache : wcache_t ;
var awprot : proto_t ;
var awid : id_t ;
var awlen : num_bursts_t; //AXI3: 4 bits, AXI4: 8 bits
var awlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
var awqos : qos_t ; //Only AXI4
var awregion: region_t ; //Only AXI4
var awuser : awuser_t ; //Only AXI4
//Write data channel
var wvalid: logic ;
var wready: logic ;
var wlast : logic ;
var wdata : data_t ;
var wstrb : strb_t ;
var wuser : wuser_t; //Only AXI4
//Write response channel
var bvalid: logic ;
var bready: logic ;
var bresp : resp_t ;
var bid : id_t ;
var buser : buser_t; //Only AXI4
//Read address channel
var arvalid : logic ;
var arready : logic ;
var araddr : addr_t ;
var arsize : size_t ;
var arburst : burst_t ;
var arcache : rcache_t ;
var arprot : proto_t ;
var arid : id_t ;
var arlen : num_bursts_t; //AXI3: 4 bits, AXI4: 8 bits
var arlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
var arqos : qos_t ; //Only AXI4
var arregion: region_t ; //Only AXI4
var aruser : aruser_t ; //Only AXI4
//Read data channel
var rvalid: logic ;
var rready: logic ;
var rlast : logic ;
var rdata : data_t ;
var rresp : resp_t ;
var rid : id_t ;
var ruser : ruser_t; //Only AXI4
function awaddr_ack () -> logic {
return awready && awvalid;
}
function wdata_ack () -> logic {
return wready && wvalid;
}
function bresp_ack () -> logic {
return bready && bvalid;
}
function araddr_ack () -> logic {
return arready && arvalid;
}
function rdata_ack () -> logic {
return rready && rvalid;
}
modport master {
awvalid : output,
awready : input ,
awaddr : output,
awsize : output,
awburst : output,
awcache : output,
awprot : output,
awid : output,
awlen : output,
awlock : output,
awqos : output,
awregion: output,
awuser : output,
wvalid: output,
wready: input ,
wlast : output,
wdata : output,
wstrb : output,
wuser : output,
bvalid: input ,
bready: output,
bresp : input ,
bid : input ,
buser : input ,
arvalid : output,
arready : input ,
araddr : output,
arsize : output,
arburst : output,
arcache : output,
arprot : output,
arid : output,
arlen : output,
arlock : output,
arqos : output,
arregion: output,
aruser : output,
rvalid: input ,
rready: output,
rlast : input ,
rdata : input ,
rresp : input ,
rid : input ,
ruser : input ,
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
araddr_ack: import,
rdata_ack : import,
}
modport slave {
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
araddr_ack: import,
rdata_ack : import,
..converse(master)
}
modport monitor {
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
araddr_ack: import,
rdata_ack : import,
..input
}
modport write_master {
awvalid : output,
awready : input ,
awaddr : output,
awsize : output,
awburst : output,
awcache : output,
awprot : output,
awid : output,
awlen : output,
awlock : output,
awqos : output,
awregion: output,
awuser : output,
wvalid: output,
wready: input ,
wlast : output,
wdata : output,
wstrb : output,
wuser : output,
bvalid: input ,
bready: output,
bresp : input ,
bid : input ,
buser : input ,
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
}
modport read_master {
arvalid : output,
arready : input ,
araddr : output,
arsize : output,
arburst : output,
arcache : output,
arprot : output,
arid : output,
arlen : output,
arlock : output,
arqos : output,
arregion: output,
aruser : output,
rvalid: input ,
rready: output,
rlast : input ,
rdata : input ,
rresp : input ,
rid : input ,
ruser : input ,
araddr_ack: import,
rdata_ack : import,
}
modport write_slave {
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
..converse(write_master)
}
modport read_slave {
araddr_ack: import,
rdata_ack : import,
..converse(read_master)
}
}
///### AXI3 bus interface
///
///#### Modports:
///* master - AXI Master IP
///
///* slave - AXI slave IP
///
///* monitor - Debugging - All signals are declared as input
///
///* write_master - Reduced signal count for master IP that only writes to slave
///
///* read_master - Reduced signal count for master IP that only reads from slave
///
///* write_slave - Reduced signal count for slave IP that only receives writes from master
///
///* read_slave - Reduced signal count for slave IP that only replies to read requests from master
///
///#### Convenience functions:
///* awaddr_ack() = awready && awvalid
///
///* wdata_ack() = wready && wvalid
///
///* bresp_ack() = bready && bvalid
///
///* araddr_ack() = arready && arvalid
///
///* rdata_ack() = rready && rvalid
///
///#### Instantiation:
///```
///inst b: axi3_if::< axi3_pkg::< ADDR_W, DATA_W_BYTES, ID_W > >;
///```
///#### Usage in module definition with modport:
///```
///module my_axi3_slave ( aclk: input clock_posedge,
/// aresetn: input reset_sync_low,
/// axi: modport axi3_if::<axi3_pkg::<32, 4, 8>>::slave ) {
///
///}
///```
pub interface axi3_if::<PKG: axi3_prototype> {
import PKG::*;
//Write address channel
var awvalid: logic ;
var awready: logic ;
var awaddr : addr_t ;
var awsize : size_t ;
var awburst: burst_t ;
var awcache: cache_t ;
var awprot : proto_t ;
var awid : id_t ;
var awlen : num_bursts_t; //AXI3: 4 bits, AXI4: 8 bits
var awlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
//Write data channel
var wvalid: logic ;
var wready: logic ;
var wlast : logic ;
var wdata : data_t;
var wstrb : strb_t;
var wid : id_t ; //Only AXI3
//Write response channel
var bvalid: logic ;
var bready: logic ;
var bresp : resp_t;
var bid : id_t ;
//Read address channel
var arvalid: logic ;
var arready: logic ;
var araddr : addr_t ;
var arsize : size_t ;
var arburst: burst_t ;
var arcache: cache_t ;
var arprot : proto_t ;
var arid : id_t ;
var arlen : num_bursts_t; //AXI3: 4 bits, AXI4: 8 bits
var arlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
//Read data channel
var rvalid: logic ;
var rready: logic ;
var rlast : logic ;
var rdata : data_t;
var rresp : resp_t;
var rid : id_t ;
function awaddr_ack () -> logic {
return awready && awvalid;
}
function wdata_ack () -> logic {
return wready && wvalid;
}
function bresp_ack () -> logic {
return bready && bvalid;
}
function araddr_ack () -> logic {
return arready && arvalid;
}
function rdata_ack () -> logic {
return rready && rvalid;
}
modport master {
awvalid: output,
awready: input ,
awaddr : output,
awsize : output,
awburst: output,
awcache: output,
awprot : output,
awid : output,
awlen : output,
awlock : output,
wvalid: output,
wready: input ,
wlast : output,
wdata : output,
wstrb : output,
wid : output,
bvalid: input ,
bready: output,
bresp : input ,
bid : input ,
arvalid: output,
arready: input ,
araddr : output,
arsize : output,
arburst: output,
arcache: output,
arprot : output,
arid : output,
arlen : output,
arlock : output,
rvalid: input ,
rready: output,
rlast : input ,
rdata : input ,
rresp : input ,
rid : input ,
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
araddr_ack: import,
rdata_ack : import,
}
modport slave {
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
araddr_ack: import,
rdata_ack : import,
..converse(master)
}
modport monitor {
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
araddr_ack: import,
rdata_ack : import,
..input
}
modport write_master {
awvalid: output,
awready: input ,
awaddr : output,
awsize : output,
awburst: output,
awcache: output,
awprot : output,
awid : output,
awlen : output,
awlock : output,
wvalid: output,
wready: input ,
wlast : output,
wdata : output,
wstrb : output,
wid : output,
bvalid: input ,
bready: output,
bresp : input ,
bid : input ,
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
}
modport read_master {
arvalid: output,
arready: input ,
araddr : output,
arsize : output,
arburst: output,
arcache: output,
arprot : output,
arid : output,
arlen : output,
arlock : output,
rvalid: input ,
rready: output,
rlast : input ,
rdata : input ,
rresp : input ,
rid : input ,
araddr_ack: import,
rdata_ack : import,
}
modport write_slave {
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
..converse(write_master)
}
modport read_slave {
araddr_ack: import,
rdata_ack : import,
..converse(read_master)
}
}
///### AXI4-Lite bus interface
///
///#### Modports:
///* master - AXI Master IP
///
///* slave - AXI slave IP
///
///* monitor - Debugging - All signals are declared as input
///
///* write_master - Reduced signal count for master IP that only writes to slave
///
///* read_master - Reduced signal count for master IP that only reads from slave
///
///* write_slave - Reduced signal count for slave IP that only receives writes from master
///
///* read_slave - Reduced signal count for slave IP that only replies to read requests from master
///
///#### Convenience functions:
///* awaddr_ack() = awready && awvalid
///
///* wdata_ack() = wready && wvalid
///
///* bresp_ack() = bready && bvalid
///
///* araddr_ack() = arready && arvalid
///
///* rdata_ack() = rready && rvalid
///
///#### Instantiation:
///```
///inst c: axi4_lite_if::< axi4_lite_pkg::< ADDR_W, DATA_W_BYTES, ID_W > >;
///```
///#### Usage in module definition with modport:
///```
///module my_axi4_lite_slave ( aclk: input clock_posedge,
/// aresetn: input reset_sync_low,
/// axi: modport axi4_lite_if::<axi4_lite_pkg::<32, 4, 8>>::slave )
///{
///
///}
///```
///#### Note:
///The awid, arid, bid and rid signals on the slave* modports are optional.
///These and are used to connect compatible AXI4-Lite slaves to a full AXI4 interface (AXI ID reflection on slave required).
pub interface axi4_lite_if::<PKG: axi4_lite_prototype> {
import PKG::*;
//Write address channel
var awvalid: logic ;
var awready: logic ;
var awaddr : addr_t ;
var awprot : proto_t;
var awid : id_t ;
//Write data channel
var wvalid: logic ;
var wready: logic ;
var wdata : data_t;
var wstrb : strb_t;
//Write response channel
var bvalid: logic ;
var bready: logic ;
var bresp : resp_t;
var bid : id_t ;
//Read address channel
var arvalid: logic ;
var arready: logic ;
var araddr : addr_t ;
var arprot : proto_t;
var arid : id_t ;
//Read data channel
var rvalid: logic ;
var rready: logic ;
var rdata : data_t;
var rresp : resp_t;
var rid : id_t ;
function awaddr_ack () -> logic {
return awready && awvalid;
}
function wdata_ack () -> logic {
return wready && wvalid;
}
function bresp_ack () -> logic {
return bready && bvalid;
}
function araddr_ack () -> logic {
return arready && arvalid;
}
function rdata_ack () -> logic {
return rready && rvalid;
}
modport master {
awvalid: output,
awready: input ,
awaddr : output,
awprot : output,
wvalid: output,
wready: input ,
wdata : output,
wstrb : output,
bvalid: input ,
bready: output,
bresp : input ,
arvalid: output,
arready: input ,
araddr : output,
arprot : output,
rvalid: input ,
rready: output,
rdata : input ,
rresp : input ,
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
araddr_ack: import,
rdata_ack : import,
}
modport slave {
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
araddr_ack: import,
rdata_ack : import,
awid: input ,
arid: input ,
bid : output,
rid : output,
..converse(master)
}
modport monitor {
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
araddr_ack: import,
rdata_ack : import,
..input
}
modport write_master {
awvalid: output,
awready: input ,
awaddr : output,
awprot : output,
awid : output,
wvalid: output,
wready: input ,
wdata : output,
wstrb : output,
bvalid: input ,
bready: output,
bresp : input ,
bid : input ,
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
}
modport read_master {
arvalid: output,
arready: input ,
araddr : output,
arprot : output,
arid : output,
rvalid: input ,
rready: output,
rdata : input ,
rresp : input ,
rid : input ,
araddr_ack: import,
rdata_ack : import,
}
modport write_slave {
awaddr_ack: import,
wdata_ack : import,
bresp_ack : import,
awid: input ,
bid : output,
..converse(write_master)
}
modport read_slave {
araddr_ack: import,
rdata_ack : import,
arid: input ,
rid : output,
..converse(read_master)
}
}
///### AXI4-Stream bus interface
///
///#### Modports:
///* transmitter - AXI4-Stream Transmitter IP
///
///* receiver - AXI4-Stream Receiver IP
///
///#### Convenience functions:
///* t_ack() = tready && tvalid
///
///#### Instantiation:
///```
///inst c: axi4_stream_if::< axi4_stream_pkg::< DATA_W_BYTES, DEST_W, ID_W, USER_W > >;
///```
///#### Usage in module definition with modport:
///```
///module my_axi4_stream_receiver ( aclk: input clock_posedge,
/// aresetn: input reset_sync_low,
/// axi: modport axi4_stream_if::<axi4_stream_pkg::<4, 2, 8, 5>>::receiver )
///{
///
///}
///```
pub interface axi4_stream_if::<PKG: axi4_stream_prototype> {
import PKG::*;
var tvalid: logic ;
var tready: logic ;
var tdata : data_t;
var tstrb : strb_t;
var tkeep : keep_t;
var tlast : logic ;
var tid : id_t ;
var tdest : dest_t;
var tuser : user_t;
function t_ack () -> logic {
return tready && tvalid;
}
modport transmitter {
t_ack: import,
tvalid: output,
tready: input ,
tdata : output,
tstrb : output,
tkeep : output,
tlast : output,
tid : output,
tdest : output,
tuser : output,
}
modport receiver {
t_ack: import,
..converse(transmitter)
}
}