veryl_analyzer/ir/
ir.rs

1use crate::conv::Context;
2use crate::ir::{AssignDestination, Interface, Module};
3use std::fmt;
4use veryl_parser::resource_table::StrId;
5use veryl_parser::token_range::TokenRange;
6
7#[derive(Clone, Default)]
8pub struct Ir {
9    pub components: Vec<Component>,
10}
11
12impl Ir {
13    pub fn append(&mut self, x: &mut Ir) {
14        self.components.append(&mut x.components);
15    }
16
17    pub fn eval_assign(&self, context: &mut Context) {
18        for x in &self.components {
19            x.eval_assign(context);
20        }
21    }
22}
23
24impl fmt::Display for Ir {
25    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
26        let mut ret = String::new();
27        for x in &self.components {
28            ret.push_str(&format!("{}\n", x));
29        }
30        ret.fmt(f)
31    }
32}
33
34#[derive(Clone, Debug)]
35pub struct IrError {
36    pub token: TokenRange,
37    pub code: String,
38}
39
40#[macro_export]
41macro_rules! ir_error {
42    ($x:expr) => {
43        Box::new($crate::ir::IrError {
44            token: $x,
45            code: format!("{}:{}:{}", file!(), line!(), column!()),
46        })
47    };
48}
49
50pub type IrResult<T> = Result<T, Box<IrError>>;
51
52#[derive(Clone)]
53pub enum Component {
54    Module(Module),
55    Interface(Interface),
56    SystemVerilog(SystemVerilog),
57}
58
59impl Component {
60    pub fn eval_assign(&self, context: &mut Context) {
61        match self {
62            Component::Module(x) => x.eval_assign(context),
63            Component::Interface(_) => (),
64            Component::SystemVerilog(_) => (),
65        }
66    }
67}
68
69impl fmt::Display for Component {
70    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
71        match self {
72            Component::Module(x) => x.fmt(f),
73            Component::Interface(x) => x.fmt(f),
74            Component::SystemVerilog(_) => "".fmt(f),
75        }
76    }
77}
78
79#[derive(Clone)]
80pub struct SystemVerilog {
81    pub name: StrId,
82    pub connects: Vec<AssignDestination>,
83}
veryl_analyzer/ir/ir.rs

veryl_analyzer/ir/
ir.rs
