vcpu 0.2.0

A virtual cpu, modeled after the 6502
Documentation 
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use std::ops::RangeInclusive;

// TODO: Try invert the dependency on bus so Cpu and Ram hold channels to/from
// Bus

#[derive(Default)]
pub struct Bus {
  items: Vec<Box<dyn BusItem>>,
}

impl Bus {
  pub fn new() -> Self {
    let items = Default::default();

    Self { items }
  }

  pub fn read(&mut self, address: u16, read_only: bool) -> u8 {
    for item in self.items.iter_mut() {
      if item.address_range().contains(&address) {
        return item.read(address, read_only);
      }
    }

    0
  }

  pub fn write(&mut self, address: u16, value: u8) {
    for item in self.items.iter_mut() {
      if item.address_range().contains(&address) {
        return item.write(address, value);
      }
    }
  }

  pub fn connect(&mut self, item: impl BusItem + 'static) {
    self.items.push(Box::new(item));
  }
}

pub trait BusItem {
  fn address_range(&self) -> &RangeInclusive<u16>;

  fn read(&mut self, address: u16, read_only: bool) -> u8;

  fn write(&mut self, address: u16, value: u8);
}