Module va416xx::dac0

Digital to Analog Converter Peripheral

Modules

• ctrl0
  Control Register 0
• ctrl1
  Control Register 1
• fifo_clr
  FIFO Clear
• fifo_data
  FIFO data
• irq_clr
  Clear Interrupt
• irq_enb
  Interrupt Enable
• irq_end
  Enabled Interrupt Status
• irq_raw
  Raw Interrupt Status
• perid
  Peripheral ID Register
• status
  Status
• txfifoirqtrg
  Receive FIFO Interrupt Trigger Value

Structs

• RegisterBlock
  Register block

Type Aliases

• Ctrl0
  CTRL0 (rw) register accessor: Control Register 0
• Ctrl1
  CTRL1 (rw) register accessor: Control Register 1
• FifoClr
  FIFO_CLR (rw) register accessor: FIFO Clear
• FifoData
  FIFO_DATA (rw) register accessor: FIFO data
• IrqClr
  IRQ_CLR (w) register accessor: Clear Interrupt
• IrqEnb
  IRQ_ENB (rw) register accessor: Interrupt Enable
• IrqEnd
  IRQ_END (r) register accessor: Enabled Interrupt Status
• IrqRaw
  IRQ_RAW (r) register accessor: Raw Interrupt Status
• Perid
  PERID (r) register accessor: Peripheral ID Register
• Status
  STATUS (r) register accessor: Status
• Txfifoirqtrg
  TXFIFOIRQTRG (rw) register accessor: Receive FIFO Interrupt Trigger Value