1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 porta: [Porta; 32],
5 portb: [Portb; 32],
6 tim: [Tim; 32],
7 uart: [Uart; 4],
8 spi: [Spi; 4],
9 i2c_ms: [I2cMs; 4],
10 i2c_sl: [I2cSl; 4],
11 int_ram_sbe: IntRamSbe,
12 int_ram_mbe: IntRamMbe,
13 int_rom_sbe: IntRomSbe,
14 int_rom_mbe: IntRomMbe,
15 txev: Txev,
16 _reserved12: [u8; 0x062c],
17 irqs: [Irqs; 32],
18 _reserved13: [u8; 0x68],
19 edbgrq: Edbgrq,
20 mereset: Mereset,
21 watchdog: Watchdog,
22 rxev: Rxev,
23 nmi: Nmi,
24 _reserved18: [u8; 0x0700],
25 perid: Perid,
26}
27impl RegisterBlock {
28 #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
29 #[inline(always)]
30 pub const fn porta(&self, n: usize) -> &Porta {
31 &self.porta[n]
32 }
33 #[doc = "Iterator for array of:"]
34 #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
35 #[inline(always)]
36 pub fn porta_iter(&self) -> impl Iterator<Item = &Porta> {
37 self.porta.iter()
38 }
39 #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
40 #[inline(always)]
41 pub const fn portb(&self, n: usize) -> &Portb {
42 &self.portb[n]
43 }
44 #[doc = "Iterator for array of:"]
45 #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
46 #[inline(always)]
47 pub fn portb_iter(&self) -> impl Iterator<Item = &Portb> {
48 self.portb.iter()
49 }
50 #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
51 #[inline(always)]
52 pub const fn tim(&self, n: usize) -> &Tim {
53 &self.tim[n]
54 }
55 #[doc = "Iterator for array of:"]
56 #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
57 #[inline(always)]
58 pub fn tim_iter(&self) -> impl Iterator<Item = &Tim> {
59 self.tim.iter()
60 }
61 #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
62 #[inline(always)]
63 pub const fn uart(&self, n: usize) -> &Uart {
64 &self.uart[n]
65 }
66 #[doc = "Iterator for array of:"]
67 #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
68 #[inline(always)]
69 pub fn uart_iter(&self) -> impl Iterator<Item = &Uart> {
70 self.uart.iter()
71 }
72 #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
73 #[inline(always)]
74 pub const fn spi(&self, n: usize) -> &Spi {
75 &self.spi[n]
76 }
77 #[doc = "Iterator for array of:"]
78 #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
79 #[inline(always)]
80 pub fn spi_iter(&self) -> impl Iterator<Item = &Spi> {
81 self.spi.iter()
82 }
83 #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
84 #[inline(always)]
85 pub const fn i2c_ms(&self, n: usize) -> &I2cMs {
86 &self.i2c_ms[n]
87 }
88 #[doc = "Iterator for array of:"]
89 #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
90 #[inline(always)]
91 pub fn i2c_ms_iter(&self) -> impl Iterator<Item = &I2cMs> {
92 self.i2c_ms.iter()
93 }
94 #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
95 #[inline(always)]
96 pub const fn i2c_sl(&self, n: usize) -> &I2cSl {
97 &self.i2c_sl[n]
98 }
99 #[doc = "Iterator for array of:"]
100 #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
101 #[inline(always)]
102 pub fn i2c_sl_iter(&self) -> impl Iterator<Item = &I2cSl> {
103 self.i2c_sl.iter()
104 }
105 #[doc = "0x1c0 - Internal Memory RAM SBE Interrupt Redirect Selection"]
106 #[inline(always)]
107 pub const fn int_ram_sbe(&self) -> &IntRamSbe {
108 &self.int_ram_sbe
109 }
110 #[doc = "0x1c4 - Internal Memory RAM MBE Interrupt Redirect Selection"]
111 #[inline(always)]
112 pub const fn int_ram_mbe(&self) -> &IntRamMbe {
113 &self.int_ram_mbe
114 }
115 #[doc = "0x1c8 - Internal Memory ROM SBE Interrupt Redirect Selection"]
116 #[inline(always)]
117 pub const fn int_rom_sbe(&self) -> &IntRomSbe {
118 &self.int_rom_sbe
119 }
120 #[doc = "0x1cc - Internal Memory ROM MBE Interrupt Redirect Selection"]
121 #[inline(always)]
122 pub const fn int_rom_mbe(&self) -> &IntRomMbe {
123 &self.int_rom_mbe
124 }
125 #[doc = "0x1d0 - Processor TXEV Interrupt Redirect Selection"]
126 #[inline(always)]
127 pub const fn txev(&self) -> &Txev {
128 &self.txev
129 }
130 #[doc = "0x800..0x880 - Interrupt Status Register"]
131 #[inline(always)]
132 pub const fn irqs(&self, n: usize) -> &Irqs {
133 &self.irqs[n]
134 }
135 #[doc = "Iterator for array of:"]
136 #[doc = "0x800..0x880 - Interrupt Status Register"]
137 #[inline(always)]
138 pub fn irqs_iter(&self) -> impl Iterator<Item = &Irqs> {
139 self.irqs.iter()
140 }
141 #[doc = "0x8e8 - EDBGRQ Status Register"]
142 #[inline(always)]
143 pub const fn edbgrq(&self) -> &Edbgrq {
144 &self.edbgrq
145 }
146 #[doc = "0x8ec - MERESET Status Register"]
147 #[inline(always)]
148 pub const fn mereset(&self) -> &Mereset {
149 &self.mereset
150 }
151 #[doc = "0x8f0 - WATCHDOG Status Register"]
152 #[inline(always)]
153 pub const fn watchdog(&self) -> &Watchdog {
154 &self.watchdog
155 }
156 #[doc = "0x8f4 - RXEV Status Register"]
157 #[inline(always)]
158 pub const fn rxev(&self) -> &Rxev {
159 &self.rxev
160 }
161 #[doc = "0x8f8 - NMI Status Register"]
162 #[inline(always)]
163 pub const fn nmi(&self) -> &Nmi {
164 &self.nmi
165 }
166 #[doc = "0xffc - Peripheral ID Register"]
167 #[inline(always)]
168 pub const fn perid(&self) -> &Perid {
169 &self.perid
170 }
171}
172#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`] module"]
173#[doc(alias = "INT_RAM_SBE")]
174pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>;
175#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection"]
176pub mod int_ram_sbe;
177pub use int_ram_sbe as porta;
178pub use int_ram_sbe as portb;
179pub use int_ram_sbe as tim;
180pub use int_ram_sbe as uart;
181pub use int_ram_sbe as spi;
182pub use int_ram_sbe as i2c_ms;
183pub use int_ram_sbe as i2c_sl;
184pub use int_ram_sbe as int_ram_mbe;
185pub use int_ram_sbe as int_rom_sbe;
186pub use int_ram_sbe as int_rom_mbe;
187pub use int_ram_sbe as txev;
188pub use IntRamSbe as Porta;
189pub use IntRamSbe as Portb;
190pub use IntRamSbe as Tim;
191pub use IntRamSbe as Uart;
192pub use IntRamSbe as Spi;
193pub use IntRamSbe as I2cMs;
194pub use IntRamSbe as I2cSl;
195pub use IntRamSbe as IntRamMbe;
196pub use IntRamSbe as IntRomSbe;
197pub use IntRamSbe as IntRomMbe;
198pub use IntRamSbe as Txev;
199#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`] module"]
200#[doc(alias = "NMI")]
201pub type Nmi = crate::Reg<nmi::NmiSpec>;
202#[doc = "NMI Status Register"]
203pub mod nmi;
204pub use nmi as rxev;
205pub use nmi as watchdog;
206pub use nmi as mereset;
207pub use nmi as edbgrq;
208pub use nmi as irqs;
209pub use Nmi as Rxev;
210pub use Nmi as Watchdog;
211pub use Nmi as Mereset;
212pub use Nmi as Edbgrq;
213pub use Nmi as Irqs;
214#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
215#[doc(alias = "PERID")]
216pub type Perid = crate::Reg<perid::PeridSpec>;
217#[doc = "Peripheral ID Register"]
218pub mod perid;