1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 rst_stat: RstStat,
5 rst_cntl_rom: RstCntlRom,
6 rst_cntl_ram: RstCntlRam,
7 rom_prot: RomProt,
8 rom_scrub: RomScrub,
9 ram_scrub: RamScrub,
10 rom_trap_addr: RomTrapAddr,
11 rom_trap_synd: RomTrapSynd,
12 ram_trap_addr: RamTrapAddr,
13 ram_trap_synd: RamTrapSynd,
14 irq_enb: IrqEnb,
15 irq_raw: IrqRaw,
16 irq_end: IrqEnd,
17 irq_clr: IrqClr,
18 ram_sbe: RamSbe,
19 ram_mbe: RamMbe,
20 rom_sbe: RomSbe,
21 rom_mbe: RomMbe,
22 ioconfig_clkdiv0: IoconfigClkdiv0,
23 ioconfig_clkdiv: [IoconfigClkdiv; 7],
24 rom_retries: RomRetries,
25 refresh_config: RefreshConfig,
26 tim_reset: TimReset,
27 tim_clk_enable: TimClkEnable,
28 peripheral_reset: PeripheralReset,
29 peripheral_clk_enable: PeripheralClkEnable,
30 lockup_reset: LockupReset,
31 _reserved27: [u8; 0x0f6c],
32 ef_config: EfConfig,
33 ef_id: EfId,
34 procid: Procid,
35 perid: Perid,
36}
37impl RegisterBlock {
38 #[doc = "0x00 - System Reset Status"]
39 #[inline(always)]
40 pub const fn rst_stat(&self) -> &RstStat {
41 &self.rst_stat
42 }
43 #[doc = "0x04 - ROM Reset Control"]
44 #[inline(always)]
45 pub const fn rst_cntl_rom(&self) -> &RstCntlRom {
46 &self.rst_cntl_rom
47 }
48 #[doc = "0x08 - RAM Reset Control"]
49 #[inline(always)]
50 pub const fn rst_cntl_ram(&self) -> &RstCntlRam {
51 &self.rst_cntl_ram
52 }
53 #[doc = "0x0c - ROM Protection Configuration"]
54 #[inline(always)]
55 pub const fn rom_prot(&self) -> &RomProt {
56 &self.rom_prot
57 }
58 #[doc = "0x10 - ROM Scrub Period Configuration"]
59 #[inline(always)]
60 pub const fn rom_scrub(&self) -> &RomScrub {
61 &self.rom_scrub
62 }
63 #[doc = "0x14 - RAM Scrub Period Configuration"]
64 #[inline(always)]
65 pub const fn ram_scrub(&self) -> &RamScrub {
66 &self.ram_scrub
67 }
68 #[doc = "0x18 - ROM Trap Address"]
69 #[inline(always)]
70 pub const fn rom_trap_addr(&self) -> &RomTrapAddr {
71 &self.rom_trap_addr
72 }
73 #[doc = "0x1c - ROM Trap Syndrome"]
74 #[inline(always)]
75 pub const fn rom_trap_synd(&self) -> &RomTrapSynd {
76 &self.rom_trap_synd
77 }
78 #[doc = "0x20 - RAM Trap Address"]
79 #[inline(always)]
80 pub const fn ram_trap_addr(&self) -> &RamTrapAddr {
81 &self.ram_trap_addr
82 }
83 #[doc = "0x24 - RAM Trap Syndrome"]
84 #[inline(always)]
85 pub const fn ram_trap_synd(&self) -> &RamTrapSynd {
86 &self.ram_trap_synd
87 }
88 #[doc = "0x28 - Enable EDAC Error Interrupt Register"]
89 #[inline(always)]
90 pub const fn irq_enb(&self) -> &IrqEnb {
91 &self.irq_enb
92 }
93 #[doc = "0x2c - Raw EDAC Error Interrupt Status"]
94 #[inline(always)]
95 pub const fn irq_raw(&self) -> &IrqRaw {
96 &self.irq_raw
97 }
98 #[doc = "0x30 - Enabled EDAC Error Interrupt Status"]
99 #[inline(always)]
100 pub const fn irq_end(&self) -> &IrqEnd {
101 &self.irq_end
102 }
103 #[doc = "0x34 - Clear EDAC Error Interrupt Status"]
104 #[inline(always)]
105 pub const fn irq_clr(&self) -> &IrqClr {
106 &self.irq_clr
107 }
108 #[doc = "0x38 - Count of RAM EDAC Single Bit Errors"]
109 #[inline(always)]
110 pub const fn ram_sbe(&self) -> &RamSbe {
111 &self.ram_sbe
112 }
113 #[doc = "0x3c - Count of RAM EDAC Multi Bit Errors"]
114 #[inline(always)]
115 pub const fn ram_mbe(&self) -> &RamMbe {
116 &self.ram_mbe
117 }
118 #[doc = "0x40 - Count of ROM EDAC Single Bit Errors"]
119 #[inline(always)]
120 pub const fn rom_sbe(&self) -> &RomSbe {
121 &self.rom_sbe
122 }
123 #[doc = "0x44 - Count of ROM EDAC Multi Bit Errors"]
124 #[inline(always)]
125 pub const fn rom_mbe(&self) -> &RomMbe {
126 &self.rom_mbe
127 }
128 #[doc = "0x48 - IO Configuration Clock Divider Register"]
129 #[inline(always)]
130 pub const fn ioconfig_clkdiv0(&self) -> &IoconfigClkdiv0 {
131 &self.ioconfig_clkdiv0
132 }
133 #[doc = "0x4c..0x68 - IO Configuration Clock Divider Register"]
134 #[doc = ""]
135 #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `IOCONFIG_CLKDIV1` register.</div>"]
136 #[inline(always)]
137 pub const fn ioconfig_clkdiv(&self, n: usize) -> &IoconfigClkdiv {
138 &self.ioconfig_clkdiv[n]
139 }
140 #[doc = "Iterator for array of:"]
141 #[doc = "0x4c..0x68 - IO Configuration Clock Divider Register"]
142 #[inline(always)]
143 pub fn ioconfig_clkdiv_iter(&self) -> impl Iterator<Item = &IoconfigClkdiv> {
144 self.ioconfig_clkdiv.iter()
145 }
146 #[doc = "0x4c - IO Configuration Clock Divider Register"]
147 #[inline(always)]
148 pub const fn ioconfig_clkdiv1(&self) -> &IoconfigClkdiv {
149 self.ioconfig_clkdiv(0)
150 }
151 #[doc = "0x50 - IO Configuration Clock Divider Register"]
152 #[inline(always)]
153 pub const fn ioconfig_clkdiv2(&self) -> &IoconfigClkdiv {
154 self.ioconfig_clkdiv(1)
155 }
156 #[doc = "0x54 - IO Configuration Clock Divider Register"]
157 #[inline(always)]
158 pub const fn ioconfig_clkdiv3(&self) -> &IoconfigClkdiv {
159 self.ioconfig_clkdiv(2)
160 }
161 #[doc = "0x58 - IO Configuration Clock Divider Register"]
162 #[inline(always)]
163 pub const fn ioconfig_clkdiv4(&self) -> &IoconfigClkdiv {
164 self.ioconfig_clkdiv(3)
165 }
166 #[doc = "0x5c - IO Configuration Clock Divider Register"]
167 #[inline(always)]
168 pub const fn ioconfig_clkdiv5(&self) -> &IoconfigClkdiv {
169 self.ioconfig_clkdiv(4)
170 }
171 #[doc = "0x60 - IO Configuration Clock Divider Register"]
172 #[inline(always)]
173 pub const fn ioconfig_clkdiv6(&self) -> &IoconfigClkdiv {
174 self.ioconfig_clkdiv(5)
175 }
176 #[doc = "0x64 - IO Configuration Clock Divider Register"]
177 #[inline(always)]
178 pub const fn ioconfig_clkdiv7(&self) -> &IoconfigClkdiv {
179 self.ioconfig_clkdiv(6)
180 }
181 #[doc = "0x68 - ROM BOOT Retry count"]
182 #[inline(always)]
183 pub const fn rom_retries(&self) -> &RomRetries {
184 &self.rom_retries
185 }
186 #[doc = "0x6c - Register Refresh Control"]
187 #[inline(always)]
188 pub const fn refresh_config(&self) -> &RefreshConfig {
189 &self.refresh_config
190 }
191 #[doc = "0x70 - TIM Reset Control"]
192 #[inline(always)]
193 pub const fn tim_reset(&self) -> &TimReset {
194 &self.tim_reset
195 }
196 #[doc = "0x74 - TIM Enable Control"]
197 #[inline(always)]
198 pub const fn tim_clk_enable(&self) -> &TimClkEnable {
199 &self.tim_clk_enable
200 }
201 #[doc = "0x78 - Peripheral Reset Control"]
202 #[inline(always)]
203 pub const fn peripheral_reset(&self) -> &PeripheralReset {
204 &self.peripheral_reset
205 }
206 #[doc = "0x7c - Peripheral Enable Control"]
207 #[inline(always)]
208 pub const fn peripheral_clk_enable(&self) -> &PeripheralClkEnable {
209 &self.peripheral_clk_enable
210 }
211 #[doc = "0x80 - Lockup Reset Configuration"]
212 #[inline(always)]
213 pub const fn lockup_reset(&self) -> &LockupReset {
214 &self.lockup_reset
215 }
216 #[doc = "0xff0 - EFuse Config Register"]
217 #[inline(always)]
218 pub const fn ef_config(&self) -> &EfConfig {
219 &self.ef_config
220 }
221 #[doc = "0xff4 - EFuse ID Register"]
222 #[inline(always)]
223 pub const fn ef_id(&self) -> &EfId {
224 &self.ef_id
225 }
226 #[doc = "0xff8 - Processor ID Register"]
227 #[inline(always)]
228 pub const fn procid(&self) -> &Procid {
229 &self.procid
230 }
231 #[doc = "0xffc - Peripheral ID Register"]
232 #[inline(always)]
233 pub const fn perid(&self) -> &Perid {
234 &self.perid
235 }
236}
237#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`] module"]
238#[doc(alias = "RST_STAT")]
239pub type RstStat = crate::Reg<rst_stat::RstStatSpec>;
240#[doc = "System Reset Status"]
241pub mod rst_stat;
242pub use rst_stat as rst_cntl_rom;
243pub use rst_stat as rst_cntl_ram;
244pub use RstStat as RstCntlRom;
245pub use RstStat as RstCntlRam;
246#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`] module"]
247#[doc(alias = "ROM_PROT")]
248pub type RomProt = crate::Reg<rom_prot::RomProtSpec>;
249#[doc = "ROM Protection Configuration"]
250pub mod rom_prot;
251#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`] module"]
252#[doc(alias = "ROM_SCRUB")]
253pub type RomScrub = crate::Reg<rom_scrub::RomScrubSpec>;
254#[doc = "ROM Scrub Period Configuration"]
255pub mod rom_scrub;
256pub use rom_scrub as ram_scrub;
257pub use RomScrub as RamScrub;
258#[doc = "ROM_TRAP_ADDR (rw) register accessor: ROM Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_addr`] module"]
259#[doc(alias = "ROM_TRAP_ADDR")]
260pub type RomTrapAddr = crate::Reg<rom_trap_addr::RomTrapAddrSpec>;
261#[doc = "ROM Trap Address"]
262pub mod rom_trap_addr;
263#[doc = "ROM_TRAP_SYND (rw) register accessor: ROM Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`] module"]
264#[doc(alias = "ROM_TRAP_SYND")]
265pub type RomTrapSynd = crate::Reg<rom_trap_synd::RomTrapSyndSpec>;
266#[doc = "ROM Trap Syndrome"]
267pub mod rom_trap_synd;
268pub use rom_trap_addr as ram_trap_addr;
269pub use rom_trap_synd as ram_trap_synd;
270pub use RomTrapAddr as RamTrapAddr;
271pub use RomTrapSynd as RamTrapSynd;
272#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
273#[doc(alias = "IRQ_ENB")]
274pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
275#[doc = "Enable EDAC Error Interrupt Register"]
276pub mod irq_enb;
277pub use irq_enb as irq_raw;
278pub use irq_enb as irq_end;
279pub use irq_enb as irq_clr;
280pub use IrqEnb as IrqRaw;
281pub use IrqEnb as IrqEnd;
282pub use IrqEnb as IrqClr;
283#[doc = "RAM_SBE (rw) register accessor: Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sbe`] module"]
284#[doc(alias = "RAM_SBE")]
285pub type RamSbe = crate::Reg<ram_sbe::RamSbeSpec>;
286#[doc = "Count of RAM EDAC Single Bit Errors"]
287pub mod ram_sbe;
288pub use ram_sbe as ram_mbe;
289pub use ram_sbe as rom_sbe;
290pub use ram_sbe as rom_mbe;
291pub use RamSbe as RamMbe;
292pub use RamSbe as RomSbe;
293pub use RamSbe as RomMbe;
294#[doc = "IOCONFIG_CLKDIV0 (r) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv0`] module"]
295#[doc(alias = "IOCONFIG_CLKDIV0")]
296pub type IoconfigClkdiv0 = crate::Reg<ioconfig_clkdiv0::IoconfigClkdiv0Spec>;
297#[doc = "IO Configuration Clock Divider Register"]
298pub mod ioconfig_clkdiv0;
299#[doc = "IOCONFIG_CLKDIV (rw) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv`] module"]
300#[doc(alias = "IOCONFIG_CLKDIV")]
301pub type IoconfigClkdiv = crate::Reg<ioconfig_clkdiv::IoconfigClkdivSpec>;
302#[doc = "IO Configuration Clock Divider Register"]
303pub mod ioconfig_clkdiv;
304#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`] module"]
305#[doc(alias = "ROM_RETRIES")]
306pub type RomRetries = crate::Reg<rom_retries::RomRetriesSpec>;
307#[doc = "ROM BOOT Retry count"]
308pub mod rom_retries;
309#[doc = "REFRESH_CONFIG (rw) register accessor: Register Refresh Control\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config`] module"]
310#[doc(alias = "REFRESH_CONFIG")]
311pub type RefreshConfig = crate::Reg<refresh_config::RefreshConfigSpec>;
312#[doc = "Register Refresh Control"]
313pub mod refresh_config;
314#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`] module"]
315#[doc(alias = "TIM_RESET")]
316pub type TimReset = crate::Reg<tim_reset::TimResetSpec>;
317#[doc = "TIM Reset Control"]
318pub mod tim_reset;
319#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`] module"]
320#[doc(alias = "TIM_CLK_ENABLE")]
321pub type TimClkEnable = crate::Reg<tim_clk_enable::TimClkEnableSpec>;
322#[doc = "TIM Enable Control"]
323pub mod tim_clk_enable;
324#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`] module"]
325#[doc(alias = "PERIPHERAL_RESET")]
326pub type PeripheralReset = crate::Reg<peripheral_reset::PeripheralResetSpec>;
327#[doc = "Peripheral Reset Control"]
328pub mod peripheral_reset;
329#[doc = "PERIPHERAL_CLK_ENABLE (rw) register accessor: Peripheral Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_clk_enable`] module"]
330#[doc(alias = "PERIPHERAL_CLK_ENABLE")]
331pub type PeripheralClkEnable = crate::Reg<peripheral_clk_enable::PeripheralClkEnableSpec>;
332#[doc = "Peripheral Enable Control"]
333pub mod peripheral_clk_enable;
334#[doc = "LOCKUP_RESET (rw) register accessor: Lockup Reset Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lockup_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockup_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lockup_reset`] module"]
335#[doc(alias = "LOCKUP_RESET")]
336pub type LockupReset = crate::Reg<lockup_reset::LockupResetSpec>;
337#[doc = "Lockup Reset Configuration"]
338pub mod lockup_reset;
339#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`] module"]
340#[doc(alias = "EF_CONFIG")]
341pub type EfConfig = crate::Reg<ef_config::EfConfigSpec>;
342#[doc = "EFuse Config Register"]
343pub mod ef_config;
344#[doc = "EF_ID (r) register accessor: EFuse ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id`] module"]
345#[doc(alias = "EF_ID")]
346pub type EfId = crate::Reg<ef_id::EfIdSpec>;
347#[doc = "EFuse ID Register"]
348pub mod ef_id;
349#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`] module"]
350#[doc(alias = "PROCID")]
351pub type Procid = crate::Reg<procid::ProcidSpec>;
352#[doc = "Processor ID Register"]
353pub mod procid;
354#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
355#[doc(alias = "PERID")]
356pub type Perid = crate::Reg<perid::PeridSpec>;
357#[doc = "Peripheral ID Register"]
358pub mod perid;