unicorn/
arm_const.rs

1#![allow(non_camel_case_types)]
2
3// ARM registers
4#[repr(C)]
5#[derive(PartialEq, Debug, Clone, Copy)]
6pub enum RegisterARM {
7    INVALID = 0,
8    APSR = 1,
9    APSR_NZCV = 2,
10    CPSR = 3,
11    FPEXC = 4,
12    FPINST = 5,
13    FPSCR = 6,
14    FPSCR_NZCV = 7,
15    FPSID = 8,
16    ITSTATE = 9,
17    LR = 10,
18    PC = 11,
19    SP = 12,
20    SPSR = 13,
21    D0 = 14,
22    D1 = 15,
23    D2 = 16,
24    D3 = 17,
25    D4 = 18,
26    D5 = 19,
27    D6 = 20,
28    D7 = 21,
29    D8 = 22,
30    D9 = 23,
31    D10 = 24,
32    D11 = 25,
33    D12 = 26,
34    D13 = 27,
35    D14 = 28,
36    D15 = 29,
37    D16 = 30,
38    D17 = 31,
39    D18 = 32,
40    D19 = 33,
41    D20 = 34,
42    D21 = 35,
43    D22 = 36,
44    D23 = 37,
45    D24 = 38,
46    D25 = 39,
47    D26 = 40,
48    D27 = 41,
49    D28 = 42,
50    D29 = 43,
51    D30 = 44,
52    D31 = 45,
53    FPINST2 = 46,
54    MVFR0 = 47,
55    MVFR1 = 48,
56    MVFR2 = 49,
57    Q0 = 50,
58    Q1 = 51,
59    Q2 = 52,
60    Q3 = 53,
61    Q4 = 54,
62    Q5 = 55,
63    Q6 = 56,
64    Q7 = 57,
65    Q8 = 58,
66    Q9 = 59,
67    Q10 = 60,
68    Q11 = 61,
69    Q12 = 62,
70    Q13 = 63,
71    Q14 = 64,
72    Q15 = 65,
73    R0 = 66,
74    R1 = 67,
75    R2 = 68,
76    R3 = 69,
77    R4 = 70,
78    R5 = 71,
79    R6 = 72,
80    R7 = 73,
81    R8 = 74,
82    SB = 75,
83    SL = 76,
84    FP = 77,
85    IP = 78,
86    S0 = 79,
87    S1 = 80,
88    S2 = 81,
89    S3 = 82,
90    S4 = 83,
91    S5 = 84,
92    S6 = 85,
93    S7 = 86,
94    S8 = 87,
95    S9 = 88,
96    S10 = 89,
97    S11 = 90,
98    S12 = 91,
99    S13 = 92,
100    S14 = 93,
101    S15 = 94,
102    S16 = 95,
103    S17 = 96,
104    S18 = 97,
105    S19 = 98,
106    S20 = 99,
107    S21 = 100,
108    S22 = 101,
109    S23 = 102,
110    S24 = 103,
111    S25 = 104,
112    S26 = 105,
113    S27 = 106,
114    S28 = 107,
115    S29 = 108,
116    S30 = 109,
117    S31 = 110,
118}
unicorn/arm_const.rs

unicorn/
arm_const.rs
