ud-arch-x86 0.2.0

x86 (16/32/64-bit) decode + encode backend with byte-identical round-trip.
Documentation

x86 architecture backend.

Phase 1 scope: decode an x86 byte sequence into structured instructions (via [iced_x86]), and provide two distinct emission paths:

  • [emit_preserved] — concatenate each instruction's original bytes captured at decode time. This is byte-identical by construction and is what the round-trip contract is built on.
  • [reencode_via_iced] — feed the structured [Instruction]s back through BlockEncoder. This is not byte-identical for all real inputs: iced canonicalizes redundant prefixes (e.g. drops a 66 data16 override on a NOP that doesn't need it), so for compiler- emitted alignment NOPs and .plt padding the bytes will differ. Useful for "I edited an instruction" workflows in later phases, not for round-trip.

16- and 32-bit modes are exposed through [Bitness] and the same API; the round-trip property is identical.