use super::Kernel;
use crate::ptx::builder::{PtxArithmetic, PtxComparison, PtxControl, PtxMemory};
use crate::ptx::{PtxKernel, PtxType};
#[derive(Debug, Clone)]
pub struct LongRowSoftmaxKernel {
pub row_size: u32,
}
impl LongRowSoftmaxKernel {
#[must_use]
pub fn new(row_size: u32) -> Self {
Self { row_size }
}
}
impl Kernel for LongRowSoftmaxKernel {
fn name(&self) -> &str {
"softmax_long_row"
}
fn build_ptx(&self) -> PtxKernel {
let block_size = 256_u32;
let n_warps = block_size / 32;
let smem_size = (n_warps * 2 + 2) * 4;
PtxKernel::new("softmax_long_row")
.param(PtxType::U64, "input_ptr")
.param(PtxType::U64, "output_ptr")
.param(PtxType::U32, "row_size")
.shared_memory(smem_size as usize)
.build(|ctx| {
let tid = ctx.special_reg(crate::ptx::PtxReg::TidX);
let ctaid = ctx.special_reg(crate::ptx::PtxReg::CtaIdX);
let ntid = ctx.special_reg(crate::ptx::PtxReg::NtidX);
let row_size = ctx.load_param_u32("row_size");
let input_ptr = ctx.load_param_u64("input_ptr");
let output_ptr = ctx.load_param_u64("output_ptr");
let lane_mask = ctx.mov_u32_imm(31);
let lane_id = ctx.and_u32(tid, lane_mask);
let warp_id = ctx.shr_u32_imm(tid, 5);
let row_offset = ctx.mul_lo_u32(ctaid, row_size);
let row_offset_bytes = ctx.mul_wide_u32(row_offset, 4);
let row_in_ptr = ctx.add_u64(input_ptr, row_offset_bytes);
let row_out_ptr = ctx.add_u64(output_ptr, row_offset_bytes);
let neg_inf = ctx.mov_f32_imm(f32::NEG_INFINITY);
let local_max = neg_inf;
let idx = ctx.add_u32(tid, 0);
ctx.label("max_loop");
let done_max = ctx.setp_ge_u32(idx, row_size);
ctx.branch_if(done_max, "max_loop_done");
let byte_offset = ctx.mul_wide_u32(idx, 4);
let load_addr = ctx.add_u64(row_in_ptr, byte_offset);
let val = ctx.ld_global_f32(load_addr);
ctx.max_f32_inplace(local_max, val);
ctx.add_u32_reg_inplace(idx, ntid);
ctx.branch("max_loop");
ctx.label("max_loop_done");
let shuffled_16 = ctx.shfl_down_f32(local_max, 16, 0xFFFF_FFFF);
let warp_max_1 = ctx.max_f32(local_max, shuffled_16);
let shuffled_8 = ctx.shfl_down_f32(warp_max_1, 8, 0xFFFF_FFFF);
let warp_max_2 = ctx.max_f32(warp_max_1, shuffled_8);
let shuffled_4 = ctx.shfl_down_f32(warp_max_2, 4, 0xFFFF_FFFF);
let warp_max_3 = ctx.max_f32(warp_max_2, shuffled_4);
let shuffled_2 = ctx.shfl_down_f32(warp_max_3, 2, 0xFFFF_FFFF);
let warp_max_4 = ctx.max_f32(warp_max_3, shuffled_2);
let shuffled_1 = ctx.shfl_down_f32(warp_max_4, 1, 0xFFFF_FFFF);
let warp_max = ctx.max_f32(warp_max_4, shuffled_1);
let zero = ctx.mov_u32_imm(0);
let is_lane_0 = ctx.setp_eq_u32(lane_id, zero);
ctx.branch_if_not(is_lane_0, "skip_store_warp_max");
let smem_offset = ctx.mul_u32(warp_id, 4);
let smem_offset_64 = ctx.cvt_u64_u32(smem_offset);
ctx.st_shared_f32(smem_offset_64, warp_max);
ctx.label("skip_store_warp_max");
ctx.bar_sync(0);
let is_warp_0 = ctx.setp_eq_u32(warp_id, zero);
ctx.branch_if_not(is_warp_0, "skip_inter_warp_max");
let seven = ctx.mov_u32_imm(7);
let lane_id_clamped = ctx.and_u32(lane_id, seven);
let lane_smem_offset = ctx.mul_u32(lane_id_clamped, 4);
let lane_smem_64 = ctx.cvt_u64_u32(lane_smem_offset);
let loaded_warp_max = ctx.ld_shared_f32(lane_smem_64);
let inter_4 = ctx.shfl_down_f32(loaded_warp_max, 4, 0xFFFF_FFFF);
let inter_max_1 = ctx.max_f32(loaded_warp_max, inter_4);
let inter_2 = ctx.shfl_down_f32(inter_max_1, 2, 0xFFFF_FFFF);
let inter_max_2 = ctx.max_f32(inter_max_1, inter_2);
let inter_1 = ctx.shfl_down_f32(inter_max_2, 1, 0xFFFF_FFFF);
let global_max = ctx.max_f32(inter_max_2, inter_1);
let is_lane_0_check = ctx.setp_eq_u32(lane_id, zero);
ctx.branch_if_not(is_lane_0_check, "skip_store_global_max");
let global_max_offset = ctx.mov_u32_imm(32); let global_max_offset_64 = ctx.cvt_u64_u32(global_max_offset);
ctx.st_shared_f32(global_max_offset_64, global_max);
ctx.label("skip_store_global_max");
ctx.label("skip_inter_warp_max");
ctx.bar_sync(1);
let global_max_read_offset = ctx.mov_u32_imm(32);
let global_max_read_64 = ctx.cvt_u64_u32(global_max_read_offset);
let global_max_val = ctx.ld_shared_f32(global_max_read_64);
let local_sum = ctx.mov_f32_imm(0.0);
let log2_e = ctx.mov_f32_imm(std::f32::consts::LOG2_E);
let idx2 = ctx.add_u32(tid, 0);
ctx.label("sum_loop");
let done_sum = ctx.setp_ge_u32(idx2, row_size);
ctx.branch_if(done_sum, "sum_loop_done");
let byte_offset2 = ctx.mul_wide_u32(idx2, 4);
let load_addr2 = ctx.add_u64(row_in_ptr, byte_offset2);
let val2 = ctx.ld_global_f32(load_addr2);
let shifted = ctx.sub_f32(val2, global_max_val);
let scaled = ctx.mul_f32(shifted, log2_e);
let exp_val = ctx.ex2_f32(scaled);
ctx.add_f32_inplace(local_sum, exp_val);
ctx.add_u32_reg_inplace(idx2, ntid);
ctx.branch("sum_loop");
ctx.label("sum_loop_done");
let sum_shuffled_16 = ctx.shfl_down_f32(local_sum, 16, 0xFFFF_FFFF);
let warp_sum_1 = ctx.add_f32(local_sum, sum_shuffled_16);
let sum_shuffled_8 = ctx.shfl_down_f32(warp_sum_1, 8, 0xFFFF_FFFF);
let warp_sum_2 = ctx.add_f32(warp_sum_1, sum_shuffled_8);
let sum_shuffled_4 = ctx.shfl_down_f32(warp_sum_2, 4, 0xFFFF_FFFF);
let warp_sum_3 = ctx.add_f32(warp_sum_2, sum_shuffled_4);
let sum_shuffled_2 = ctx.shfl_down_f32(warp_sum_3, 2, 0xFFFF_FFFF);
let warp_sum_4 = ctx.add_f32(warp_sum_3, sum_shuffled_2);
let sum_shuffled_1 = ctx.shfl_down_f32(warp_sum_4, 1, 0xFFFF_FFFF);
let warp_sum = ctx.add_f32(warp_sum_4, sum_shuffled_1);
ctx.branch_if_not(is_lane_0, "skip_store_warp_sum");
let sum_smem_base = ctx.mov_u32_imm(36); let four = ctx.mov_u32_imm(4);
let sum_smem_offset = ctx.mad_lo_u32(warp_id, four, sum_smem_base);
let sum_smem_64 = ctx.cvt_u64_u32(sum_smem_offset);
ctx.st_shared_f32(sum_smem_64, warp_sum);
ctx.label("skip_store_warp_sum");
ctx.bar_sync(2);
ctx.branch_if_not(is_warp_0, "skip_inter_warp_sum");
let seven2 = ctx.mov_u32_imm(7);
let lane_id_clamped2 = ctx.and_u32(lane_id, seven2);
let sum_base2 = ctx.mov_u32_imm(36);
let four2 = ctx.mov_u32_imm(4);
let sum_lane_offset = ctx.mad_lo_u32(lane_id_clamped2, four2, sum_base2);
let sum_lane_64 = ctx.cvt_u64_u32(sum_lane_offset);
let loaded_warp_sum = ctx.ld_shared_f32(sum_lane_64);
let sum_inter_4 = ctx.shfl_down_f32(loaded_warp_sum, 4, 0xFFFF_FFFF);
let inter_sum_1 = ctx.add_f32(loaded_warp_sum, sum_inter_4);
let sum_inter_2 = ctx.shfl_down_f32(inter_sum_1, 2, 0xFFFF_FFFF);
let inter_sum_2 = ctx.add_f32(inter_sum_1, sum_inter_2);
let sum_inter_1 = ctx.shfl_down_f32(inter_sum_2, 1, 0xFFFF_FFFF);
let global_sum = ctx.add_f32(inter_sum_2, sum_inter_1);
let is_lane_0_sum = ctx.setp_eq_u32(lane_id, zero);
ctx.branch_if_not(is_lane_0_sum, "skip_store_global_sum");
let global_sum_offset = ctx.mov_u32_imm(68);
let global_sum_offset_64 = ctx.cvt_u64_u32(global_sum_offset);
ctx.st_shared_f32(global_sum_offset_64, global_sum);
ctx.label("skip_store_global_sum");
ctx.label("skip_inter_warp_sum");
ctx.bar_sync(3);
let global_sum_read_offset = ctx.mov_u32_imm(68);
let global_sum_read_64 = ctx.cvt_u64_u32(global_sum_read_offset);
let global_sum_val = ctx.ld_shared_f32(global_sum_read_64);
let idx3 = ctx.add_u32(tid, 0);
ctx.label("write_loop");
let done_write = ctx.setp_ge_u32(idx3, row_size);
ctx.branch_if(done_write, "write_loop_done");
let byte_offset3 = ctx.mul_wide_u32(idx3, 4);
let load_addr3 = ctx.add_u64(row_in_ptr, byte_offset3);
let val3 = ctx.ld_global_f32(load_addr3);
let shifted3 = ctx.sub_f32(val3, global_max_val);
let scaled3 = ctx.mul_f32(shifted3, log2_e);
let exp_val3 = ctx.ex2_f32(scaled3);
let softmax_val = ctx.div_f32(exp_val3, global_sum_val);
let out_addr = ctx.add_u64(row_out_ptr, byte_offset3);
ctx.st_global_f32(out_addr, softmax_val);
ctx.add_u32_reg_inplace(idx3, ntid);
ctx.branch("write_loop");
ctx.label("write_loop_done");
ctx.ret();
})
}
}