pub macro wait_for {
($cond:expr) => {
while !$cond {
core::hint::spin_loop()
}
}
}
bitflags!{
struct LineStatusFlags: u8 {
const INPUT_FULL = 1;
const OUTPUT_EMPTY = 1 << 5;
}
}
bitflags!{
struct InterruptEnableFlags: u8 {
const RECEIVED = 1;
const SENT = 1 << 1;
const ERRORED = 1 << 2;
const STATUS_CHANGE = 1 << 3;
}
}
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
#[derive(Debug)]
pub struct SerialPort(u16);
impl SerialPort {
fn base_port(&self) -> u16 {
self.0
}
fn interrupt_enable(&self) -> u16 {
return self.base_port() + 1;
}
fn fifo_control(&self) -> u16 {
return self.base_port() + 2;
}
fn line_control(&self) -> u16 {
return self.base_port() + 3;
}
fn modem_control(&self) -> u16 {
return self.base_port() + 4;
}
fn line_status_port(&self) -> u16 {
return self.base_port() + 5;
}
fn line_status(&self) -> LineStatusFlags {
return unsafe {
LineStatusFlags::from_bits_truncate(x86::io::inb(self.line_status_port()))
};
}
pub const unsafe fn new(base: u16) -> Self {
return SerialPort(base);
}
pub fn init(&mut self) {
unsafe {
x86::io::outb(self.interrupt_enable(), 0x00);
x86::io::outb(self.line_control(), 0x80);
x86::io::outb(self.base_port(), 0x03);
x86::io::outb(self.interrupt_enable(), 0x00);
x86::io::outb(self.line_control(), 0x03);
x86::io::outb(self.fifo_control(), 0xc7);
x86::io::outb(self.modem_control(), 0x0b);
x86::io::outb(self.interrupt_enable(), 0x01);
}
}
pub fn send(&mut self, data: u8) {
unsafe {
match data {
8 | 0x7F => {
wait_for!(self.line_status().contains(LineStatusFlags::OUTPUT_EMPTY));
x86::io::outb(self.base_port(), 8);
wait_for!(self.line_status().contains(LineStatusFlags::OUTPUT_EMPTY));
x86::io::outb(self.base_port(), b' ');
wait_for!(self.line_status().contains(LineStatusFlags::OUTPUT_EMPTY));
x86::io::outb(self.base_port(), 8);
}
_ => {
wait_for!(self.line_status().contains(LineStatusFlags::OUTPUT_EMPTY));
x86::io::outb(self.base_port(), data);
}
}
}
}
pub fn send_raw(&mut self, data: u8) {
unsafe {
wait_for!(self.line_status().contains(LineStatusFlags::OUTPUT_EMPTY));
x86::io::outb(self.base_port(), data);
}
}
pub fn receive(&mut self) -> u8 {
unsafe {
wait_for!(self.line_status().contains(LineStatusFlags::INPUT_FULL));
x86::io::inb(self.base_port())
}
}
}
impl fmt::Write for SerialPort {
fn write_str(&mut self, s: &str) -> fmt::Result {
for byte in s.bytes() {
self.send(byte);
}
Ok(())
}
}
#[derive(Debug)]
pub struct MmioPort {
data: AtomicPtr<u8>,
interrupt_enable: AtomicPtr<u8>,
fifo_control: AtomicPtr<u8>,
line_control: AtomicPtr<u8>,
modem_control: AtomicPtr<u8>,
line_status: AtomicPtr<u8>,
}
impl MmioPort {
#[rustversion::attr(since(1.61), const)]
pub unsafe fn new(base: usize) -> Self {
let base_pointer = base as *mut u8;
return MmioPort{
data: AtomicPtr::new(base_pointer),
interrupt_enable: AtomicPtr::new(base_pointer.add(1)),
fifo_control: AtomicPtr::new(base_pointer.add(2)),
line_control: AtomicPtr::new(base_pointer.add(3)),
modem_control: AtomicPtr::new(base_pointer.add(4)),
line_status: AtomicPtr::new(base_pointer.add(5)),
};
}
pub fn init(&mut self) {
let self_interrupt_enable = self.interrupt_enable.load(Ordering::Relaxed);
let self_line_control = self.line_control.load(Ordering::Relaxed);
let self_data = self.data.load(Ordering::Relaxed);
let self_fifo_control = self.fifo_control.load(Ordering::Relaxed);
let self_modem_control = self.modem_control.load(Ordering::Relaxed);
unsafe {
self_interrupt_enable.write(0x00);
self_line_control.write(0x80);
self_data.write(0x03);
self_interrupt_enable.write(0x00);
self_line_control.write(0x03);
self_fifo_control.write(0xC7);
self_modem_control.write(0x0B);
self_interrupt_enable.write(0x01);
}
}
fn line_status(&mut self) -> LineStatusFlags {
unsafe { LineStatusFlags::from_bits_truncate(*self.line_status.load(Ordering::Relaxed)) }
}
pub fn send(&mut self, data: u8) {
let self_data = self.data.load(Ordering::Relaxed);
unsafe {
match data {
8 | 0x7F => {
wait_for!(self.line_status().contains(LineStatusFlags::OUTPUT_EMPTY));
self_data.write(8);
wait_for!(self.line_status().contains(LineStatusFlags::OUTPUT_EMPTY));
self_data.write(b' ');
wait_for!(self.line_status().contains(LineStatusFlags::OUTPUT_EMPTY));
self_data.write(8)
}
_ => {
wait_for!(self.line_status().contains(LineStatusFlags::OUTPUT_EMPTY));
self_data.write(data);
}
}
}
}
pub fn receive(&mut self) -> u8 {
let self_data = self.data.load(Ordering::Relaxed);
unsafe {
wait_for!(self.line_status().contains(LineStatusFlags::INPUT_FULL));
self_data.read()
}
}
}
impl fmt::Write for MmioPort {
fn write_str(&mut self, s: &str) -> fmt::Result {
for byte in s.bytes() {
self.send(byte);
}
Ok(())
}
}
use {
bitflags::bitflags,
core::{
fmt,
sync::atomic::{
AtomicPtr, Ordering,
},
},
};