topstitch 0.96.0

Stitch together Verilog modules with Rust
Documentation 
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// SPDX-License-Identifier: Apache-2.0

use num_bigint::BigInt;

use crate::{ConvertibleToPortSlice, Port};

impl Port {
    /// Ties off this port to the given constant value, specified as a `BigInt`
    /// or type that can be converted to a `BigInt`.
    pub fn tieoff<T: Into<BigInt>>(&self, value: T) {
        self.to_port_slice().tieoff(value);
    }

    /// Marks this port as unused, meaning that if it is a module instance
    /// output or module definition input, validation will not fail if the port
    /// drives nothing. In fact, validation will fail if the port drives
    /// anything.
    pub fn unused(&self) {
        self.to_port_slice().unused();
    }

    /// Marks this Port as unused or ties it off to the given value, depending
    /// on the directionality of the port. ModDef Input and InOut ports are
    /// marked as unused, as well as ModInst Output and InOut ports. ModDef
    /// Output and ModInst Input ports are tied off.
    pub fn unused_or_tieoff<T: Into<BigInt>>(&self, value: T) {
        self.to_port_slice().unused_or_tieoff(value);
    }
}