topstitch 0.96.0

Stitch together Verilog modules with Rust
Documentation 
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// SPDX-License-Identifier: Apache-2.0

use crate::Intf;

impl Intf {
    pub fn width(&self) -> usize {
        self.get_port_slices()
            .values()
            .map(|slice| slice.width())
            .sum()
    }
}