topstitch 0.96.0

Stitch together Verilog modules with Rust
Documentation 
1
2
3
4
5
6
7
8
9
10
11

// SPDX-License-Identifier: Apache-2.0

module adder #(
    parameter W=8
) (
    input wire [W-1:0] a,
    input wire [W-1:0] b,
    output wire [W:0] sum
);
    assign sum = a + b;
endmodule