topstitch 0.95.1

Stitch together Verilog modules with Rust
Documentation 
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// SPDX-License-Identifier: Apache-2.0

pub const WEST_EDGE_INDEX: usize = 0;
pub const LEFT_EDGE_INDEX: usize = 0;
pub const NORTH_EDGE_INDEX: usize = 1;
pub const TOP_EDGE_INDEX: usize = 1;
pub const EAST_EDGE_INDEX: usize = 2;
pub const RIGHT_EDGE_INDEX: usize = 2;
pub const SOUTH_EDGE_INDEX: usize = 3;
pub const BOTTOM_EDGE_INDEX: usize = 3;