tm4c129x/sysctl/
pcephy.rs

1#[doc = "Reader of register PCEPHY"]
2pub type R = crate::R<u32, super::PCEPHY>;
3#[doc = "Writer for register PCEPHY"]
4pub type W = crate::W<u32, super::PCEPHY>;
5#[doc = "Register PCEPHY `reset()`'s with value 0"]
6impl crate::ResetValue for super::PCEPHY {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `P0`"]
14pub type P0_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `P0`"]
16pub struct P0_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> P0_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37impl R {
38    #[doc = "Bit 0 - Ethernet PHY Module Power Control"]
39    #[inline(always)]
40    pub fn p0(&self) -> P0_R {
41        P0_R::new((self.bits & 0x01) != 0)
42    }
43}
44impl W {
45    #[doc = "Bit 0 - Ethernet PHY Module Power Control"]
46    #[inline(always)]
47    pub fn p0(&mut self) -> P0_W {
48        P0_W { w: self }
49    }
50}
tm4c129x/sysctl/pcephy.rs

tm4c129x/sysctl/
pcephy.rs
