tm4c129x/usb0/
dmactl5.rs

1#[doc = "Reader of register DMACTL5"]
2pub type R = crate::R<u16, super::DMACTL5>;
3#[doc = "Writer for register DMACTL5"]
4pub type W = crate::W<u16, super::DMACTL5>;
5#[doc = "Register DMACTL5 `reset()`'s with value 0"]
6impl crate::ResetValue for super::DMACTL5 {
7    type Type = u16;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `ENABLE`"]
14pub type ENABLE_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `ENABLE`"]
16pub struct ENABLE_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> ENABLE_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u16) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `DIR`"]
38pub type DIR_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `DIR`"]
40pub struct DIR_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> DIR_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u16) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `MODE`"]
62pub type MODE_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `MODE`"]
64pub struct MODE_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> MODE_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u16) & 0x01) << 2);
82        self.w
83    }
84}
85#[doc = "Reader of field `IE`"]
86pub type IE_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `IE`"]
88pub struct IE_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> IE_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u16) & 0x01) << 3);
106        self.w
107    }
108}
109#[doc = "Reader of field `EP`"]
110pub type EP_R = crate::R<u8, u8>;
111#[doc = "Write proxy for field `EP`"]
112pub struct EP_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> EP_W<'a> {
116    #[doc = r"Writes raw bits to the field"]
117    #[inline(always)]
118    pub unsafe fn bits(self, value: u8) -> &'a mut W {
119        self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u16) & 0x0f) << 4);
120        self.w
121    }
122}
123#[doc = "Reader of field `ERR`"]
124pub type ERR_R = crate::R<bool, bool>;
125#[doc = "Write proxy for field `ERR`"]
126pub struct ERR_W<'a> {
127    w: &'a mut W,
128}
129impl<'a> ERR_W<'a> {
130    #[doc = r"Sets the field bit"]
131    #[inline(always)]
132    pub fn set_bit(self) -> &'a mut W {
133        self.bit(true)
134    }
135    #[doc = r"Clears the field bit"]
136    #[inline(always)]
137    pub fn clear_bit(self) -> &'a mut W {
138        self.bit(false)
139    }
140    #[doc = r"Writes raw bits to the field"]
141    #[inline(always)]
142    pub fn bit(self, value: bool) -> &'a mut W {
143        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
144        self.w
145    }
146}
147#[doc = "Burst Mode\n\nValue on reset: 0"]
148#[derive(Clone, Copy, Debug, PartialEq)]
149#[repr(u8)]
150pub enum BRSTM_A {
151    #[doc = "0: Bursts of unspecified length"]
152    ANY = 0,
153    #[doc = "1: INCR4 or unspecified length"]
154    INC4 = 1,
155    #[doc = "2: INCR8, INCR4 or unspecified length"]
156    INC8 = 2,
157    #[doc = "3: INCR16, INCR8, INCR4 or unspecified length"]
158    INC16 = 3,
159}
160impl From<BRSTM_A> for u8 {
161    #[inline(always)]
162    fn from(variant: BRSTM_A) -> Self {
163        variant as _
164    }
165}
166#[doc = "Reader of field `BRSTM`"]
167pub type BRSTM_R = crate::R<u8, BRSTM_A>;
168impl BRSTM_R {
169    #[doc = r"Get enumerated values variant"]
170    #[inline(always)]
171    pub fn variant(&self) -> BRSTM_A {
172        match self.bits {
173            0 => BRSTM_A::ANY,
174            1 => BRSTM_A::INC4,
175            2 => BRSTM_A::INC8,
176            3 => BRSTM_A::INC16,
177            _ => unreachable!(),
178        }
179    }
180    #[doc = "Checks if the value of the field is `ANY`"]
181    #[inline(always)]
182    pub fn is_any(&self) -> bool {
183        *self == BRSTM_A::ANY
184    }
185    #[doc = "Checks if the value of the field is `INC4`"]
186    #[inline(always)]
187    pub fn is_inc4(&self) -> bool {
188        *self == BRSTM_A::INC4
189    }
190    #[doc = "Checks if the value of the field is `INC8`"]
191    #[inline(always)]
192    pub fn is_inc8(&self) -> bool {
193        *self == BRSTM_A::INC8
194    }
195    #[doc = "Checks if the value of the field is `INC16`"]
196    #[inline(always)]
197    pub fn is_inc16(&self) -> bool {
198        *self == BRSTM_A::INC16
199    }
200}
201#[doc = "Write proxy for field `BRSTM`"]
202pub struct BRSTM_W<'a> {
203    w: &'a mut W,
204}
205impl<'a> BRSTM_W<'a> {
206    #[doc = r"Writes `variant` to the field"]
207    #[inline(always)]
208    pub fn variant(self, variant: BRSTM_A) -> &'a mut W {
209        {
210            self.bits(variant.into())
211        }
212    }
213    #[doc = "Bursts of unspecified length"]
214    #[inline(always)]
215    pub fn any(self) -> &'a mut W {
216        self.variant(BRSTM_A::ANY)
217    }
218    #[doc = "INCR4 or unspecified length"]
219    #[inline(always)]
220    pub fn inc4(self) -> &'a mut W {
221        self.variant(BRSTM_A::INC4)
222    }
223    #[doc = "INCR8, INCR4 or unspecified length"]
224    #[inline(always)]
225    pub fn inc8(self) -> &'a mut W {
226        self.variant(BRSTM_A::INC8)
227    }
228    #[doc = "INCR16, INCR8, INCR4 or unspecified length"]
229    #[inline(always)]
230    pub fn inc16(self) -> &'a mut W {
231        self.variant(BRSTM_A::INC16)
232    }
233    #[doc = r"Writes raw bits to the field"]
234    #[inline(always)]
235    pub fn bits(self, value: u8) -> &'a mut W {
236        self.w.bits = (self.w.bits & !(0x03 << 9)) | (((value as u16) & 0x03) << 9);
237        self.w
238    }
239}
240impl R {
241    #[doc = "Bit 0 - DMA Transfer Enable"]
242    #[inline(always)]
243    pub fn enable(&self) -> ENABLE_R {
244        ENABLE_R::new((self.bits & 0x01) != 0)
245    }
246    #[doc = "Bit 1 - DMA Direction"]
247    #[inline(always)]
248    pub fn dir(&self) -> DIR_R {
249        DIR_R::new(((self.bits >> 1) & 0x01) != 0)
250    }
251    #[doc = "Bit 2 - DMA Transfer Mode"]
252    #[inline(always)]
253    pub fn mode(&self) -> MODE_R {
254        MODE_R::new(((self.bits >> 2) & 0x01) != 0)
255    }
256    #[doc = "Bit 3 - DMA Interrupt Enable"]
257    #[inline(always)]
258    pub fn ie(&self) -> IE_R {
259        IE_R::new(((self.bits >> 3) & 0x01) != 0)
260    }
261    #[doc = "Bits 4:7 - Endpoint number"]
262    #[inline(always)]
263    pub fn ep(&self) -> EP_R {
264        EP_R::new(((self.bits >> 4) & 0x0f) as u8)
265    }
266    #[doc = "Bit 8 - Bus Error Bit"]
267    #[inline(always)]
268    pub fn err(&self) -> ERR_R {
269        ERR_R::new(((self.bits >> 8) & 0x01) != 0)
270    }
271    #[doc = "Bits 9:10 - Burst Mode"]
272    #[inline(always)]
273    pub fn brstm(&self) -> BRSTM_R {
274        BRSTM_R::new(((self.bits >> 9) & 0x03) as u8)
275    }
276}
277impl W {
278    #[doc = "Bit 0 - DMA Transfer Enable"]
279    #[inline(always)]
280    pub fn enable(&mut self) -> ENABLE_W {
281        ENABLE_W { w: self }
282    }
283    #[doc = "Bit 1 - DMA Direction"]
284    #[inline(always)]
285    pub fn dir(&mut self) -> DIR_W {
286        DIR_W { w: self }
287    }
288    #[doc = "Bit 2 - DMA Transfer Mode"]
289    #[inline(always)]
290    pub fn mode(&mut self) -> MODE_W {
291        MODE_W { w: self }
292    }
293    #[doc = "Bit 3 - DMA Interrupt Enable"]
294    #[inline(always)]
295    pub fn ie(&mut self) -> IE_W {
296        IE_W { w: self }
297    }
298    #[doc = "Bits 4:7 - Endpoint number"]
299    #[inline(always)]
300    pub fn ep(&mut self) -> EP_W {
301        EP_W { w: self }
302    }
303    #[doc = "Bit 8 - Bus Error Bit"]
304    #[inline(always)]
305    pub fn err(&mut self) -> ERR_W {
306        ERR_W { w: self }
307    }
308    #[doc = "Bits 9:10 - Burst Mode"]
309    #[inline(always)]
310    pub fn brstm(&mut self) -> BRSTM_W {
311        BRSTM_W { w: self }
312    }
313}