tm4c129x/sysctl/
dcgci2c.rs

1#[doc = "Reader of register DCGCI2C"]
2pub type R = crate::R<u32, super::DCGCI2C>;
3#[doc = "Writer for register DCGCI2C"]
4pub type W = crate::W<u32, super::DCGCI2C>;
5#[doc = "Register DCGCI2C `reset()`'s with value 0"]
6impl crate::ResetValue for super::DCGCI2C {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `D0`"]
14pub type D0_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `D0`"]
16pub struct D0_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> D0_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `D1`"]
38pub type D1_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `D1`"]
40pub struct D1_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> D1_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `D2`"]
62pub type D2_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `D2`"]
64pub struct D2_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> D2_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82        self.w
83    }
84}
85#[doc = "Reader of field `D3`"]
86pub type D3_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `D3`"]
88pub struct D3_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> D3_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
106        self.w
107    }
108}
109#[doc = "Reader of field `D4`"]
110pub type D4_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `D4`"]
112pub struct D4_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> D4_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
130        self.w
131    }
132}
133#[doc = "Reader of field `D5`"]
134pub type D5_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `D5`"]
136pub struct D5_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> D5_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
154        self.w
155    }
156}
157#[doc = "Reader of field `D6`"]
158pub type D6_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `D6`"]
160pub struct D6_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> D6_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
178        self.w
179    }
180}
181#[doc = "Reader of field `D7`"]
182pub type D7_R = crate::R<bool, bool>;
183#[doc = "Write proxy for field `D7`"]
184pub struct D7_W<'a> {
185    w: &'a mut W,
186}
187impl<'a> D7_W<'a> {
188    #[doc = r"Sets the field bit"]
189    #[inline(always)]
190    pub fn set_bit(self) -> &'a mut W {
191        self.bit(true)
192    }
193    #[doc = r"Clears the field bit"]
194    #[inline(always)]
195    pub fn clear_bit(self) -> &'a mut W {
196        self.bit(false)
197    }
198    #[doc = r"Writes raw bits to the field"]
199    #[inline(always)]
200    pub fn bit(self, value: bool) -> &'a mut W {
201        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
202        self.w
203    }
204}
205#[doc = "Reader of field `D8`"]
206pub type D8_R = crate::R<bool, bool>;
207#[doc = "Write proxy for field `D8`"]
208pub struct D8_W<'a> {
209    w: &'a mut W,
210}
211impl<'a> D8_W<'a> {
212    #[doc = r"Sets the field bit"]
213    #[inline(always)]
214    pub fn set_bit(self) -> &'a mut W {
215        self.bit(true)
216    }
217    #[doc = r"Clears the field bit"]
218    #[inline(always)]
219    pub fn clear_bit(self) -> &'a mut W {
220        self.bit(false)
221    }
222    #[doc = r"Writes raw bits to the field"]
223    #[inline(always)]
224    pub fn bit(self, value: bool) -> &'a mut W {
225        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
226        self.w
227    }
228}
229#[doc = "Reader of field `D9`"]
230pub type D9_R = crate::R<bool, bool>;
231#[doc = "Write proxy for field `D9`"]
232pub struct D9_W<'a> {
233    w: &'a mut W,
234}
235impl<'a> D9_W<'a> {
236    #[doc = r"Sets the field bit"]
237    #[inline(always)]
238    pub fn set_bit(self) -> &'a mut W {
239        self.bit(true)
240    }
241    #[doc = r"Clears the field bit"]
242    #[inline(always)]
243    pub fn clear_bit(self) -> &'a mut W {
244        self.bit(false)
245    }
246    #[doc = r"Writes raw bits to the field"]
247    #[inline(always)]
248    pub fn bit(self, value: bool) -> &'a mut W {
249        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
250        self.w
251    }
252}
253impl R {
254    #[doc = "Bit 0 - I2C Module 0 Deep-Sleep Mode Clock Gating Control"]
255    #[inline(always)]
256    pub fn d0(&self) -> D0_R {
257        D0_R::new((self.bits & 0x01) != 0)
258    }
259    #[doc = "Bit 1 - I2C Module 1 Deep-Sleep Mode Clock Gating Control"]
260    #[inline(always)]
261    pub fn d1(&self) -> D1_R {
262        D1_R::new(((self.bits >> 1) & 0x01) != 0)
263    }
264    #[doc = "Bit 2 - I2C Module 2 Deep-Sleep Mode Clock Gating Control"]
265    #[inline(always)]
266    pub fn d2(&self) -> D2_R {
267        D2_R::new(((self.bits >> 2) & 0x01) != 0)
268    }
269    #[doc = "Bit 3 - I2C Module 3 Deep-Sleep Mode Clock Gating Control"]
270    #[inline(always)]
271    pub fn d3(&self) -> D3_R {
272        D3_R::new(((self.bits >> 3) & 0x01) != 0)
273    }
274    #[doc = "Bit 4 - I2C Module 4 Deep-Sleep Mode Clock Gating Control"]
275    #[inline(always)]
276    pub fn d4(&self) -> D4_R {
277        D4_R::new(((self.bits >> 4) & 0x01) != 0)
278    }
279    #[doc = "Bit 5 - I2C Module 5 Deep-Sleep Mode Clock Gating Control"]
280    #[inline(always)]
281    pub fn d5(&self) -> D5_R {
282        D5_R::new(((self.bits >> 5) & 0x01) != 0)
283    }
284    #[doc = "Bit 6 - I2C Module 6 Deep-Sleep Mode Clock Gating Control"]
285    #[inline(always)]
286    pub fn d6(&self) -> D6_R {
287        D6_R::new(((self.bits >> 6) & 0x01) != 0)
288    }
289    #[doc = "Bit 7 - I2C Module 7 Deep-Sleep Mode Clock Gating Control"]
290    #[inline(always)]
291    pub fn d7(&self) -> D7_R {
292        D7_R::new(((self.bits >> 7) & 0x01) != 0)
293    }
294    #[doc = "Bit 8 - I2C Module 8 Deep-Sleep Mode Clock Gating Control"]
295    #[inline(always)]
296    pub fn d8(&self) -> D8_R {
297        D8_R::new(((self.bits >> 8) & 0x01) != 0)
298    }
299    #[doc = "Bit 9 - I2C Module 9 Deep-Sleep Mode Clock Gating Control"]
300    #[inline(always)]
301    pub fn d9(&self) -> D9_R {
302        D9_R::new(((self.bits >> 9) & 0x01) != 0)
303    }
304}
305impl W {
306    #[doc = "Bit 0 - I2C Module 0 Deep-Sleep Mode Clock Gating Control"]
307    #[inline(always)]
308    pub fn d0(&mut self) -> D0_W {
309        D0_W { w: self }
310    }
311    #[doc = "Bit 1 - I2C Module 1 Deep-Sleep Mode Clock Gating Control"]
312    #[inline(always)]
313    pub fn d1(&mut self) -> D1_W {
314        D1_W { w: self }
315    }
316    #[doc = "Bit 2 - I2C Module 2 Deep-Sleep Mode Clock Gating Control"]
317    #[inline(always)]
318    pub fn d2(&mut self) -> D2_W {
319        D2_W { w: self }
320    }
321    #[doc = "Bit 3 - I2C Module 3 Deep-Sleep Mode Clock Gating Control"]
322    #[inline(always)]
323    pub fn d3(&mut self) -> D3_W {
324        D3_W { w: self }
325    }
326    #[doc = "Bit 4 - I2C Module 4 Deep-Sleep Mode Clock Gating Control"]
327    #[inline(always)]
328    pub fn d4(&mut self) -> D4_W {
329        D4_W { w: self }
330    }
331    #[doc = "Bit 5 - I2C Module 5 Deep-Sleep Mode Clock Gating Control"]
332    #[inline(always)]
333    pub fn d5(&mut self) -> D5_W {
334        D5_W { w: self }
335    }
336    #[doc = "Bit 6 - I2C Module 6 Deep-Sleep Mode Clock Gating Control"]
337    #[inline(always)]
338    pub fn d6(&mut self) -> D6_W {
339        D6_W { w: self }
340    }
341    #[doc = "Bit 7 - I2C Module 7 Deep-Sleep Mode Clock Gating Control"]
342    #[inline(always)]
343    pub fn d7(&mut self) -> D7_W {
344        D7_W { w: self }
345    }
346    #[doc = "Bit 8 - I2C Module 8 Deep-Sleep Mode Clock Gating Control"]
347    #[inline(always)]
348    pub fn d8(&mut self) -> D8_W {
349        D8_W { w: self }
350    }
351    #[doc = "Bit 9 - I2C Module 9 Deep-Sleep Mode Clock Gating Control"]
352    #[inline(always)]
353    pub fn d9(&mut self) -> D9_W {
354        D9_W { w: self }
355    }
356}
tm4c129x/sysctl/dcgci2c.rs

tm4c129x/sysctl/
dcgci2c.rs
