tm4c129x/adc0/
ssmux1.rs

1#[doc = "Reader of register SSMUX1"]
2pub type R = crate::R<u32, super::SSMUX1>;
3#[doc = "Writer for register SSMUX1"]
4pub type W = crate::W<u32, super::SSMUX1>;
5#[doc = "Register SSMUX1 `reset()`'s with value 0"]
6impl crate::ResetValue for super::SSMUX1 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `MUX0`"]
14pub type MUX0_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `MUX0`"]
16pub struct MUX0_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> MUX0_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
24        self.w
25    }
26}
27#[doc = "Reader of field `MUX1`"]
28pub type MUX1_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `MUX1`"]
30pub struct MUX1_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> MUX1_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
38        self.w
39    }
40}
41#[doc = "Reader of field `MUX2`"]
42pub type MUX2_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `MUX2`"]
44pub struct MUX2_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> MUX2_W<'a> {
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub unsafe fn bits(self, value: u8) -> &'a mut W {
51        self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
52        self.w
53    }
54}
55#[doc = "Reader of field `MUX3`"]
56pub type MUX3_R = crate::R<u8, u8>;
57#[doc = "Write proxy for field `MUX3`"]
58pub struct MUX3_W<'a> {
59    w: &'a mut W,
60}
61impl<'a> MUX3_W<'a> {
62    #[doc = r"Writes raw bits to the field"]
63    #[inline(always)]
64    pub unsafe fn bits(self, value: u8) -> &'a mut W {
65        self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
66        self.w
67    }
68}
69impl R {
70    #[doc = "Bits 0:3 - 1st Sample Input Select"]
71    #[inline(always)]
72    pub fn mux0(&self) -> MUX0_R {
73        MUX0_R::new((self.bits & 0x0f) as u8)
74    }
75    #[doc = "Bits 4:7 - 2nd Sample Input Select"]
76    #[inline(always)]
77    pub fn mux1(&self) -> MUX1_R {
78        MUX1_R::new(((self.bits >> 4) & 0x0f) as u8)
79    }
80    #[doc = "Bits 8:11 - 3rd Sample Input Select"]
81    #[inline(always)]
82    pub fn mux2(&self) -> MUX2_R {
83        MUX2_R::new(((self.bits >> 8) & 0x0f) as u8)
84    }
85    #[doc = "Bits 12:15 - 4th Sample Input Select"]
86    #[inline(always)]
87    pub fn mux3(&self) -> MUX3_R {
88        MUX3_R::new(((self.bits >> 12) & 0x0f) as u8)
89    }
90}
91impl W {
92    #[doc = "Bits 0:3 - 1st Sample Input Select"]
93    #[inline(always)]
94    pub fn mux0(&mut self) -> MUX0_W {
95        MUX0_W { w: self }
96    }
97    #[doc = "Bits 4:7 - 2nd Sample Input Select"]
98    #[inline(always)]
99    pub fn mux1(&mut self) -> MUX1_W {
100        MUX1_W { w: self }
101    }
102    #[doc = "Bits 8:11 - 3rd Sample Input Select"]
103    #[inline(always)]
104    pub fn mux2(&mut self) -> MUX2_W {
105        MUX2_W { w: self }
106    }
107    #[doc = "Bits 12:15 - 4th Sample Input Select"]
108    #[inline(always)]
109    pub fn mux3(&mut self) -> MUX3_W {
110        MUX3_W { w: self }
111    }
112}
tm4c129x/adc0/ssmux1.rs

tm4c129x/adc0/
ssmux1.rs
