1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - DMA Status"]
5 pub stat: STAT,
6 #[doc = "0x04 - DMA Configuration"]
7 pub cfg: CFG,
8 #[doc = "0x08 - DMA Channel Control Base Pointer"]
9 pub ctlbase: CTLBASE,
10 #[doc = "0x0c - DMA Alternate Channel Control Base Pointer"]
11 pub altbase: ALTBASE,
12 #[doc = "0x10 - DMA Channel Wait-on-Request Status"]
13 pub waitstat: WAITSTAT,
14 #[doc = "0x14 - DMA Channel Software Request"]
15 pub swreq: SWREQ,
16 #[doc = "0x18 - DMA Channel Useburst Set"]
17 pub useburstset: USEBURSTSET,
18 #[doc = "0x1c - DMA Channel Useburst Clear"]
19 pub useburstclr: USEBURSTCLR,
20 #[doc = "0x20 - DMA Channel Request Mask Set"]
21 pub reqmaskset: REQMASKSET,
22 #[doc = "0x24 - DMA Channel Request Mask Clear"]
23 pub reqmaskclr: REQMASKCLR,
24 #[doc = "0x28 - DMA Channel Enable Set"]
25 pub enaset: ENASET,
26 #[doc = "0x2c - DMA Channel Enable Clear"]
27 pub enaclr: ENACLR,
28 #[doc = "0x30 - DMA Channel Primary Alternate Set"]
29 pub altset: ALTSET,
30 #[doc = "0x34 - DMA Channel Primary Alternate Clear"]
31 pub altclr: ALTCLR,
32 #[doc = "0x38 - DMA Channel Priority Set"]
33 pub prioset: PRIOSET,
34 #[doc = "0x3c - DMA Channel Priority Clear"]
35 pub prioclr: PRIOCLR,
36 _reserved16: [u8; 12usize],
37 #[doc = "0x4c - DMA Bus Error Clear"]
38 pub errclr: ERRCLR,
39 _reserved17: [u8; 1200usize],
40 #[doc = "0x500 - DMA Channel Assignment"]
41 pub chasgn: CHASGN,
42 #[doc = "0x504 - DMA Channel Interrupt Status"]
43 pub chis: CHIS,
44 _reserved19: [u8; 8usize],
45 #[doc = "0x510 - DMA Channel Map Select 0"]
46 pub chmap0: CHMAP0,
47 #[doc = "0x514 - DMA Channel Map Select 1"]
48 pub chmap1: CHMAP1,
49 #[doc = "0x518 - DMA Channel Map Select 2"]
50 pub chmap2: CHMAP2,
51 #[doc = "0x51c - DMA Channel Map Select 3"]
52 pub chmap3: CHMAP3,
53}
54#[doc = "DMA Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](stat) module"]
55pub type STAT = crate::Reg<u32, _STAT>;
56#[allow(missing_docs)]
57#[doc(hidden)]
58pub struct _STAT;
59#[doc = "`read()` method returns [stat::R](stat::R) reader structure"]
60impl crate::Readable for STAT {}
61#[doc = "DMA Status"]
62pub mod stat;
63#[doc = "DMA Configuration\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
64pub type CFG = crate::Reg<u32, _CFG>;
65#[allow(missing_docs)]
66#[doc(hidden)]
67pub struct _CFG;
68#[doc = "`write(|w| ..)` method takes [cfg::W](cfg::W) writer structure"]
69impl crate::Writable for CFG {}
70#[doc = "DMA Configuration"]
71pub mod cfg;
72#[doc = "DMA Channel Control Base Pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctlbase](ctlbase) module"]
73pub type CTLBASE = crate::Reg<u32, _CTLBASE>;
74#[allow(missing_docs)]
75#[doc(hidden)]
76pub struct _CTLBASE;
77#[doc = "`read()` method returns [ctlbase::R](ctlbase::R) reader structure"]
78impl crate::Readable for CTLBASE {}
79#[doc = "`write(|w| ..)` method takes [ctlbase::W](ctlbase::W) writer structure"]
80impl crate::Writable for CTLBASE {}
81#[doc = "DMA Channel Control Base Pointer"]
82pub mod ctlbase;
83#[doc = "DMA Alternate Channel Control Base Pointer\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [altbase](altbase) module"]
84pub type ALTBASE = crate::Reg<u32, _ALTBASE>;
85#[allow(missing_docs)]
86#[doc(hidden)]
87pub struct _ALTBASE;
88#[doc = "`read()` method returns [altbase::R](altbase::R) reader structure"]
89impl crate::Readable for ALTBASE {}
90#[doc = "DMA Alternate Channel Control Base Pointer"]
91pub mod altbase;
92#[doc = "DMA Channel Wait-on-Request Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [waitstat](waitstat) module"]
93pub type WAITSTAT = crate::Reg<u32, _WAITSTAT>;
94#[allow(missing_docs)]
95#[doc(hidden)]
96pub struct _WAITSTAT;
97#[doc = "`read()` method returns [waitstat::R](waitstat::R) reader structure"]
98impl crate::Readable for WAITSTAT {}
99#[doc = "DMA Channel Wait-on-Request Status"]
100pub mod waitstat;
101#[doc = "DMA Channel Software Request\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swreq](swreq) module"]
102pub type SWREQ = crate::Reg<u32, _SWREQ>;
103#[allow(missing_docs)]
104#[doc(hidden)]
105pub struct _SWREQ;
106#[doc = "`write(|w| ..)` method takes [swreq::W](swreq::W) writer structure"]
107impl crate::Writable for SWREQ {}
108#[doc = "DMA Channel Software Request"]
109pub mod swreq;
110#[doc = "DMA Channel Useburst Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [useburstset](useburstset) module"]
111pub type USEBURSTSET = crate::Reg<u32, _USEBURSTSET>;
112#[allow(missing_docs)]
113#[doc(hidden)]
114pub struct _USEBURSTSET;
115#[doc = "`read()` method returns [useburstset::R](useburstset::R) reader structure"]
116impl crate::Readable for USEBURSTSET {}
117#[doc = "`write(|w| ..)` method takes [useburstset::W](useburstset::W) writer structure"]
118impl crate::Writable for USEBURSTSET {}
119#[doc = "DMA Channel Useburst Set"]
120pub mod useburstset;
121#[doc = "DMA Channel Useburst Clear\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [useburstclr](useburstclr) module"]
122pub type USEBURSTCLR = crate::Reg<u32, _USEBURSTCLR>;
123#[allow(missing_docs)]
124#[doc(hidden)]
125pub struct _USEBURSTCLR;
126#[doc = "`write(|w| ..)` method takes [useburstclr::W](useburstclr::W) writer structure"]
127impl crate::Writable for USEBURSTCLR {}
128#[doc = "DMA Channel Useburst Clear"]
129pub mod useburstclr;
130#[doc = "DMA Channel Request Mask Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reqmaskset](reqmaskset) module"]
131pub type REQMASKSET = crate::Reg<u32, _REQMASKSET>;
132#[allow(missing_docs)]
133#[doc(hidden)]
134pub struct _REQMASKSET;
135#[doc = "`read()` method returns [reqmaskset::R](reqmaskset::R) reader structure"]
136impl crate::Readable for REQMASKSET {}
137#[doc = "`write(|w| ..)` method takes [reqmaskset::W](reqmaskset::W) writer structure"]
138impl crate::Writable for REQMASKSET {}
139#[doc = "DMA Channel Request Mask Set"]
140pub mod reqmaskset;
141#[doc = "DMA Channel Request Mask Clear\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reqmaskclr](reqmaskclr) module"]
142pub type REQMASKCLR = crate::Reg<u32, _REQMASKCLR>;
143#[allow(missing_docs)]
144#[doc(hidden)]
145pub struct _REQMASKCLR;
146#[doc = "`write(|w| ..)` method takes [reqmaskclr::W](reqmaskclr::W) writer structure"]
147impl crate::Writable for REQMASKCLR {}
148#[doc = "DMA Channel Request Mask Clear"]
149pub mod reqmaskclr;
150#[doc = "DMA Channel Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enaset](enaset) module"]
151pub type ENASET = crate::Reg<u32, _ENASET>;
152#[allow(missing_docs)]
153#[doc(hidden)]
154pub struct _ENASET;
155#[doc = "`read()` method returns [enaset::R](enaset::R) reader structure"]
156impl crate::Readable for ENASET {}
157#[doc = "`write(|w| ..)` method takes [enaset::W](enaset::W) writer structure"]
158impl crate::Writable for ENASET {}
159#[doc = "DMA Channel Enable Set"]
160pub mod enaset;
161#[doc = "DMA Channel Enable Clear\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enaclr](enaclr) module"]
162pub type ENACLR = crate::Reg<u32, _ENACLR>;
163#[allow(missing_docs)]
164#[doc(hidden)]
165pub struct _ENACLR;
166#[doc = "`write(|w| ..)` method takes [enaclr::W](enaclr::W) writer structure"]
167impl crate::Writable for ENACLR {}
168#[doc = "DMA Channel Enable Clear"]
169pub mod enaclr;
170#[doc = "DMA Channel Primary Alternate Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [altset](altset) module"]
171pub type ALTSET = crate::Reg<u32, _ALTSET>;
172#[allow(missing_docs)]
173#[doc(hidden)]
174pub struct _ALTSET;
175#[doc = "`read()` method returns [altset::R](altset::R) reader structure"]
176impl crate::Readable for ALTSET {}
177#[doc = "`write(|w| ..)` method takes [altset::W](altset::W) writer structure"]
178impl crate::Writable for ALTSET {}
179#[doc = "DMA Channel Primary Alternate Set"]
180pub mod altset;
181#[doc = "DMA Channel Primary Alternate Clear\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [altclr](altclr) module"]
182pub type ALTCLR = crate::Reg<u32, _ALTCLR>;
183#[allow(missing_docs)]
184#[doc(hidden)]
185pub struct _ALTCLR;
186#[doc = "`write(|w| ..)` method takes [altclr::W](altclr::W) writer structure"]
187impl crate::Writable for ALTCLR {}
188#[doc = "DMA Channel Primary Alternate Clear"]
189pub mod altclr;
190#[doc = "DMA Channel Priority Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prioset](prioset) module"]
191pub type PRIOSET = crate::Reg<u32, _PRIOSET>;
192#[allow(missing_docs)]
193#[doc(hidden)]
194pub struct _PRIOSET;
195#[doc = "`read()` method returns [prioset::R](prioset::R) reader structure"]
196impl crate::Readable for PRIOSET {}
197#[doc = "`write(|w| ..)` method takes [prioset::W](prioset::W) writer structure"]
198impl crate::Writable for PRIOSET {}
199#[doc = "DMA Channel Priority Set"]
200pub mod prioset;
201#[doc = "DMA Channel Priority Clear\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prioclr](prioclr) module"]
202pub type PRIOCLR = crate::Reg<u32, _PRIOCLR>;
203#[allow(missing_docs)]
204#[doc(hidden)]
205pub struct _PRIOCLR;
206#[doc = "`write(|w| ..)` method takes [prioclr::W](prioclr::W) writer structure"]
207impl crate::Writable for PRIOCLR {}
208#[doc = "DMA Channel Priority Clear"]
209pub mod prioclr;
210#[doc = "DMA Bus Error Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [errclr](errclr) module"]
211pub type ERRCLR = crate::Reg<u32, _ERRCLR>;
212#[allow(missing_docs)]
213#[doc(hidden)]
214pub struct _ERRCLR;
215#[doc = "`read()` method returns [errclr::R](errclr::R) reader structure"]
216impl crate::Readable for ERRCLR {}
217#[doc = "`write(|w| ..)` method takes [errclr::W](errclr::W) writer structure"]
218impl crate::Writable for ERRCLR {}
219#[doc = "DMA Bus Error Clear"]
220pub mod errclr;
221#[doc = "DMA Channel Assignment\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chasgn](chasgn) module"]
222pub type CHASGN = crate::Reg<u32, _CHASGN>;
223#[allow(missing_docs)]
224#[doc(hidden)]
225pub struct _CHASGN;
226#[doc = "`read()` method returns [chasgn::R](chasgn::R) reader structure"]
227impl crate::Readable for CHASGN {}
228#[doc = "`write(|w| ..)` method takes [chasgn::W](chasgn::W) writer structure"]
229impl crate::Writable for CHASGN {}
230#[doc = "DMA Channel Assignment"]
231pub mod chasgn;
232#[doc = "DMA Channel Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chis](chis) module"]
233pub type CHIS = crate::Reg<u32, _CHIS>;
234#[allow(missing_docs)]
235#[doc(hidden)]
236pub struct _CHIS;
237#[doc = "`read()` method returns [chis::R](chis::R) reader structure"]
238impl crate::Readable for CHIS {}
239#[doc = "`write(|w| ..)` method takes [chis::W](chis::W) writer structure"]
240impl crate::Writable for CHIS {}
241#[doc = "DMA Channel Interrupt Status"]
242pub mod chis;
243#[doc = "DMA Channel Map Select 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chmap0](chmap0) module"]
244pub type CHMAP0 = crate::Reg<u32, _CHMAP0>;
245#[allow(missing_docs)]
246#[doc(hidden)]
247pub struct _CHMAP0;
248#[doc = "`read()` method returns [chmap0::R](chmap0::R) reader structure"]
249impl crate::Readable for CHMAP0 {}
250#[doc = "`write(|w| ..)` method takes [chmap0::W](chmap0::W) writer structure"]
251impl crate::Writable for CHMAP0 {}
252#[doc = "DMA Channel Map Select 0"]
253pub mod chmap0;
254#[doc = "DMA Channel Map Select 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chmap1](chmap1) module"]
255pub type CHMAP1 = crate::Reg<u32, _CHMAP1>;
256#[allow(missing_docs)]
257#[doc(hidden)]
258pub struct _CHMAP1;
259#[doc = "`read()` method returns [chmap1::R](chmap1::R) reader structure"]
260impl crate::Readable for CHMAP1 {}
261#[doc = "`write(|w| ..)` method takes [chmap1::W](chmap1::W) writer structure"]
262impl crate::Writable for CHMAP1 {}
263#[doc = "DMA Channel Map Select 1"]
264pub mod chmap1;
265#[doc = "DMA Channel Map Select 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chmap2](chmap2) module"]
266pub type CHMAP2 = crate::Reg<u32, _CHMAP2>;
267#[allow(missing_docs)]
268#[doc(hidden)]
269pub struct _CHMAP2;
270#[doc = "`read()` method returns [chmap2::R](chmap2::R) reader structure"]
271impl crate::Readable for CHMAP2 {}
272#[doc = "`write(|w| ..)` method takes [chmap2::W](chmap2::W) writer structure"]
273impl crate::Writable for CHMAP2 {}
274#[doc = "DMA Channel Map Select 2"]
275pub mod chmap2;
276#[doc = "DMA Channel Map Select 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chmap3](chmap3) module"]
277pub type CHMAP3 = crate::Reg<u32, _CHMAP3>;
278#[allow(missing_docs)]
279#[doc(hidden)]
280pub struct _CHMAP3;
281#[doc = "`read()` method returns [chmap3::R](chmap3::R) reader structure"]
282impl crate::Readable for CHMAP3 {}
283#[doc = "`write(|w| ..)` method takes [chmap3::W](chmap3::W) writer structure"]
284impl crate::Writable for CHMAP3 {}
285#[doc = "DMA Channel Map Select 3"]
286pub mod chmap3;