thermite 0.2.1

//! Organized target-feature intrinsics

#![allow(unused_imports)]

macro_rules! import_intrinsics {
    ($($name:ident),+ $(,)?) => {
        #[cfg(target_arch = "x86_64")]
        pub use core::arch::x86_64::{$($name),+};

        #[cfg(target_arch = "x86")]
        pub use core::arch::x86::{$($name),+};
    };
}

pub mod sse {
    import_intrinsics! { __m128, __m128d, __m128i }

    import_intrinsics! {
        _CMP_EQ_OQ, _CMP_EQ_OS, _CMP_EQ_UQ, _CMP_EQ_US, _CMP_FALSE_OQ, _CMP_FALSE_OS, _CMP_GE_OQ, _CMP_GE_OS,
        _CMP_GT_OQ, _CMP_GT_OS, _CMP_LE_OQ, _CMP_LE_OS, _CMP_LT_OQ, _CMP_LT_OS, _CMP_NEQ_OQ, _CMP_NEQ_OS,
        _CMP_NEQ_UQ, _CMP_NEQ_US, _CMP_NGE_UQ, _CMP_NGE_US, _CMP_NGT_UQ, _CMP_NGT_US, _CMP_NLE_UQ, _CMP_NLE_US,
        _CMP_NLT_UQ, _CMP_NLT_US, _CMP_ORD_Q, _CMP_ORD_S, _CMP_TRUE_UQ, _CMP_TRUE_US, _CMP_UNORD_Q, _CMP_UNORD_S,

        _MM_FROUND_CEIL, _MM_FROUND_CUR_DIRECTION, _MM_FROUND_FLOOR, _MM_FROUND_NEARBYINT, _MM_FROUND_NINT,
        _MM_FROUND_NO_EXC, _MM_FROUND_RAISE_EXC, _MM_FROUND_RINT, _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF,
        _MM_FROUND_TO_POS_INF, _MM_FROUND_TO_ZERO, _MM_FROUND_TRUNC,

        _MM_HINT_ET0, _MM_HINT_ET1, _MM_HINT_NTA, _MM_HINT_T0, _MM_HINT_T1, _MM_HINT_T2
    }

    // Software prefetch is the same instruction at every x86 tier, so it lives in
    // the shared, target-generic module; re-exported here so register/ISA code can
    // reach it through the usual `arch::` namespace.
    pub use crate::backend::prefetch::{HAS_PREFETCH, prefetch};

    import_intrinsics! {
        _mm_add_ps, _mm_add_ss, _mm_and_ps, _mm_andnot_ps, _mm_cmpeq_ps, _mm_cmpeq_ss, _mm_cmpge_ps, _mm_cmpge_ss,
        _mm_cmpgt_ps, _mm_cmpgt_ss, _mm_cmple_ps, _mm_cmple_ss, _mm_cmplt_ps, _mm_cmplt_ss, _mm_cmpneq_ps,
        _mm_cmpneq_ss, _mm_cmpnge_ps, _mm_cmpnge_ss, _mm_cmpngt_ps, _mm_cmpngt_ss, _mm_cmpnle_ps, _mm_cmpnle_ss,
        _mm_cmpnlt_ps, _mm_cmpnlt_ss, _mm_cmpord_ps, _mm_cmpord_ss, _mm_cmpunord_ps, _mm_cmpunord_ss, _mm_comieq_ss,
        _mm_comige_ss, _mm_comigt_ss, _mm_comile_ss, _mm_comilt_ss, _mm_comineq_ss, _mm_cvt_si2ss, _mm_cvt_ss2si,
        _mm_cvtsi32_ss, _mm_cvtss_f32, _mm_cvtss_si32, _mm_cvtt_ss2si, _mm_cvttss_si32, _mm_div_ps, _mm_div_ss,
        _mm_load_ps, _mm_load_ps1, _mm_load_ss, _mm_load1_ps, _mm_loadr_ps, _mm_loadu_ps, _mm_max_ps, _mm_max_ss,
        _mm_min_ps, _mm_min_ss, _mm_move_ss, _mm_movehl_ps, _mm_movelh_ps, _mm_movemask_ps, _mm_mul_ps, _mm_mul_ss,
        _mm_or_ps, _mm_prefetch, _mm_rcp_ps, _mm_rcp_ss, _mm_rsqrt_ps, _mm_rsqrt_ss, _mm_set_ps, _mm_set_ps1,
        _mm_set_ss, _mm_set1_ps, _mm_setr_ps, _mm_setzero_ps, _mm_sfence, _mm_shuffle_ps, _mm_sqrt_ps,
        _mm_sqrt_ss, _mm_store_ps, _mm_store_ps1, _mm_store_ss, _mm_store1_ps, _mm_storer_ps, _mm_storeu_ps,
        _mm_stream_ps, _mm_sub_ps, _mm_sub_ss, _mm_ucomieq_ss, _mm_ucomige_ss, _mm_ucomigt_ss, _mm_ucomile_ss,
        _mm_ucomilt_ss, _mm_ucomineq_ss, _mm_undefined_ps, _mm_unpackhi_ps, _mm_unpacklo_ps, _mm_xor_ps, _mm_cvtsi64_ss,
        _mm_cvtss_si64, _mm_cvttss_si64, _mm_loadu_si64
    }
}

pub mod sse2 {
    pub use super::sse::*;
    import_intrinsics! {
        _mm_add_epi16, _mm_add_epi32, _mm_add_epi64, _mm_add_epi8, _mm_add_pd, _mm_add_sd, _mm_adds_epi16, _mm_adds_epi8,
        _mm_adds_epu16, _mm_adds_epu8, _mm_and_pd, _mm_and_si128, _mm_andnot_pd, _mm_andnot_si128, _mm_avg_epu16,
        _mm_avg_epu8, _mm_bslli_si128, _mm_bsrli_si128, _mm_castpd_ps, _mm_castpd_si128, _mm_castps_pd, _mm_castps_si128,
        _mm_castsi128_pd, _mm_castsi128_ps, _mm_clflush, _mm_cmpeq_epi16, _mm_cmpeq_epi32, _mm_cmpeq_epi8, _mm_cmpeq_pd,
        _mm_cmpeq_sd, _mm_cmpge_pd, _mm_cmpge_sd, _mm_cmpgt_epi16, _mm_cmpgt_epi32, _mm_cmpgt_epi8, _mm_cmpgt_pd,
        _mm_cmpgt_sd, _mm_cmple_pd, _mm_cmple_sd, _mm_cmplt_epi16, _mm_cmplt_epi32, _mm_cmplt_epi8, _mm_cmplt_pd,
        _mm_cmplt_sd, _mm_cmpneq_pd, _mm_cmpneq_sd, _mm_cmpnge_pd, _mm_cmpnge_sd, _mm_cmpngt_pd, _mm_cmpngt_sd,
        _mm_cmpnle_pd, _mm_cmpnle_sd, _mm_cmpnlt_pd, _mm_cmpnlt_sd, _mm_cmpord_pd, _mm_cmpord_sd, _mm_cmpunord_pd,
        _mm_cmpunord_sd, _mm_comieq_sd, _mm_comige_sd, _mm_comigt_sd, _mm_comile_sd, _mm_comilt_sd, _mm_comineq_sd,
        _mm_cvtepi32_pd, _mm_cvtepi32_ps, _mm_cvtpd_epi32, _mm_cvtpd_ps, _mm_cvtps_epi32, _mm_cvtps_pd, _mm_cvtsd_f64,
        _mm_cvtsd_si32, _mm_cvtsd_ss, _mm_cvtsi128_si32, _mm_cvtsi128_si64, _mm_cvtsi128_si64x, _mm_cvtsi32_sd,
        _mm_cvtsi32_si128, _mm_cvtsi64x_si128, _mm_cvtss_sd, _mm_cvttpd_epi32, _mm_cvttps_epi32, _mm_cvttsd_si32,
        _mm_cvttsd_si64, _mm_cvttsd_si64x, _mm_div_pd, _mm_div_sd, _mm_extract_epi16, _mm_insert_epi16, _mm_lfence,
        _mm_load_pd, _mm_load_pd1, _mm_load_sd, _mm_load_si128, _mm_load1_pd, _mm_loadh_pd, _mm_loadl_epi64, _mm_loadl_pd,
        _mm_loadr_pd, _mm_loadu_pd, _mm_loadu_si128, _mm_madd_epi16, _mm_maskmoveu_si128, _mm_max_epi16, _mm_max_epu8,
        _mm_max_pd, _mm_max_sd, _mm_mfence, _mm_min_epi16, _mm_min_epu8, _mm_min_pd, _mm_min_sd, _mm_move_epi64,
        _mm_move_sd, _mm_movemask_epi8, _mm_movemask_pd, _mm_mul_epu32, _mm_mul_pd, _mm_mul_sd, _mm_mulhi_epi16,
        _mm_mulhi_epu16, _mm_mullo_epi16, _mm_or_pd, _mm_or_si128, _mm_packs_epi16, _mm_packs_epi32, _mm_packus_epi16,
        _mm_pause, _mm_sad_epu8, _mm_set_epi16, _mm_set_epi32, _mm_set_epi64x, _mm_set_epi8, _mm_set_pd, _mm_set_pd1,
        _mm_set_sd, _mm_set1_epi16, _mm_set1_epi32, _mm_set1_epi64x, _mm_set1_epi8, _mm_set1_pd, _mm_setr_epi16,
        _mm_setr_epi32, _mm_setr_epi8, _mm_setr_pd, _mm_setzero_pd, _mm_setzero_si128, _mm_shuffle_epi32, _mm_shuffle_pd,
        _mm_shufflehi_epi16, _mm_shufflelo_epi16, _mm_sll_epi16, _mm_sll_epi32, _mm_sll_epi64, _mm_slli_epi16,
        _mm_slli_epi32, _mm_slli_epi64, _mm_slli_si128, _mm_sqrt_pd, _mm_sqrt_sd, _mm_sra_epi16, _mm_sra_epi32,
        _mm_srai_epi16, _mm_srai_epi32, _mm_srl_epi16, _mm_srl_epi32, _mm_srl_epi64, _mm_srli_epi16, _mm_srli_epi32,
        _mm_srli_epi64, _mm_srli_si128, _mm_store_pd, _mm_store_pd1, _mm_store_sd, _mm_store_si128, _mm_store1_pd,
        _mm_storeh_pd, _mm_storel_epi64, _mm_storel_pd, _mm_storer_pd, _mm_storeu_pd, _mm_storeu_si128, _mm_stream_pd,
        _mm_stream_si128, _mm_stream_si32, _mm_stream_si64, _mm_sub_epi16, _mm_sub_epi32, _mm_sub_epi64, _mm_sub_epi8,
        _mm_sub_pd, _mm_sub_sd, _mm_subs_epi16, _mm_subs_epi8, _mm_subs_epu16, _mm_subs_epu8, _mm_ucomieq_sd,
        _mm_ucomige_sd, _mm_ucomigt_sd, _mm_ucomile_sd, _mm_ucomilt_sd, _mm_ucomineq_sd, _mm_undefined_pd,
        _mm_undefined_si128, _mm_unpackhi_epi16, _mm_unpackhi_epi32, _mm_unpackhi_epi64, _mm_unpackhi_epi8,
        _mm_unpackhi_pd, _mm_unpacklo_epi16, _mm_unpacklo_epi32, _mm_unpacklo_epi64, _mm_unpacklo_epi8, _mm_unpacklo_pd,
        _mm_xor_pd, _mm_xor_si128
    }

    const DAZ: u32 = 0x0040;
    const FTZ: u32 = 0x8000;

    const DAZ_FTZ: u32 = DAZ | FTZ;

    #[rustfmt::skip] #[inline(always)] #[allow(clippy::missing_safety_doc)]
    pub unsafe fn disable_denormals() -> bool {
        let mut mxcsr: u32 = 0;

        unsafe { core::arch::asm!(
            "stmxcsr [{ptr}]",
            ptr = in(reg) &mut mxcsr,
            options(nostack, preserves_flags)
        ) };

        let was_enabled = (mxcsr & DAZ_FTZ) == 0; // if the flags were not present before

        mxcsr |= DAZ_FTZ;

        unsafe { core::arch::asm!(
            "ldmxcsr [{ptr}]",
            ptr = in(reg) &mxcsr,
            options(nostack, readonly, preserves_flags)
        ) };

        was_enabled
    }

    #[rustfmt::skip] #[inline(always)] #[allow(clippy::missing_safety_doc)]
    pub unsafe fn enable_denormals() {

        let mut mxcsr: u32 = 0;

        unsafe { core::arch::asm!(
            "stmxcsr [{ptr}]",
            ptr = in(reg) &mut mxcsr,
            options(nostack, preserves_flags)
        ) };

        mxcsr &= !DAZ_FTZ;

        unsafe { core::arch::asm!(
            "ldmxcsr [{ptr}]",
            ptr = in(reg) &mxcsr,
            options(nostack, readonly, preserves_flags)
        ) };
    }
}

pub mod sse3 {
    pub use super::sse2::*;
    import_intrinsics! {
        _mm_addsub_pd, _mm_addsub_ps, _mm_hadd_pd, _mm_hadd_ps, _mm_hsub_pd, _mm_hsub_ps, _mm_lddqu_si128,
        _mm_loaddup_pd, _mm_movedup_pd, _mm_movehdup_ps, _mm_moveldup_ps
    }
}

pub mod ssse3 {
    pub use super::sse3::*;
    import_intrinsics! {
        _mm_abs_epi16, _mm_abs_epi32, _mm_abs_epi8, _mm_alignr_epi8, _mm_hadd_epi16, _mm_hadd_epi32,
        _mm_hadds_epi16, _mm_hsub_epi16, _mm_hsub_epi32, _mm_hsubs_epi16, _mm_maddubs_epi16, _mm_mulhrs_epi16,
        _mm_shuffle_epi8, _mm_sign_epi16, _mm_sign_epi32, _mm_sign_epi8
    }
}

pub mod sse41 {
    pub use super::ssse3::*;
    import_intrinsics! {
        _mm_blend_epi16, _mm_blend_pd, _mm_blend_ps, _mm_blendv_epi8, _mm_blendv_pd, _mm_blendv_ps, _mm_ceil_pd,
        _mm_ceil_ps, _mm_ceil_sd, _mm_ceil_ss, _mm_cmpeq_epi64, _mm_cvtepi16_epi32, _mm_cvtepi16_epi64,
        _mm_cvtepi32_epi64, _mm_cvtepi8_epi16, _mm_cvtepi8_epi32, _mm_cvtepi8_epi64, _mm_cvtepu16_epi32,
        _mm_cvtepu16_epi64, _mm_cvtepu32_epi64, _mm_cvtepu8_epi16, _mm_cvtepu8_epi32, _mm_cvtepu8_epi64, _mm_dp_pd,
        _mm_dp_ps, _mm_extract_epi32, _mm_extract_epi64, _mm_extract_epi8, _mm_extract_ps, _mm_floor_pd, _mm_floor_ps,
        _mm_floor_sd, _mm_floor_ss, _mm_insert_epi32, _mm_insert_epi64, _mm_insert_epi8, _mm_insert_ps, _mm_max_epi32,
        _mm_max_epi8, _mm_max_epu16, _mm_max_epu32, _mm_min_epi32, _mm_min_epi8, _mm_min_epu16, _mm_min_epu32,
        _mm_minpos_epu16, _mm_mpsadbw_epu8, _mm_mul_epi32, _mm_mullo_epi32, _mm_packus_epi32, _mm_round_pd,
        _mm_round_ps, _mm_round_sd, _mm_round_ss, _mm_test_all_ones, _mm_test_all_zeros, _mm_test_mix_ones_zeros,
        _mm_testc_si128, _mm_testnzc_si128, _mm_testz_si128, _mm_stream_load_si128
    }
}

pub mod sse42 {
    pub use super::sse41::*;

    import_intrinsics! {
        _mm_cmpestra, _mm_cmpestrc, _mm_cmpestri, _mm_cmpestrm, _mm_cmpestro, _mm_cmpestrs, _mm_cmpestrz,
        _mm_cmpgt_epi64, _mm_cmpistra, _mm_cmpistrc, _mm_cmpistri, _mm_cmpistrm, _mm_cmpistro, _mm_cmpistrs,
        _mm_cmpistrz, _mm_crc32_u16, _mm_crc32_u32, _mm_crc32_u64, _mm_crc32_u8
    }
}

pub mod f16c {
    import_intrinsics! { _mm256_cvtph_ps, _mm256_cvtps_ph, _mm_cvtph_ps, _mm_cvtps_ph }
}

pub mod avx {
    pub use super::f16c::*;
    pub use super::sse42::*;

    import_intrinsics! { __m256, __m256d, __m256i }

    import_intrinsics! {
        _mm256_add_pd, _mm256_add_ps, _mm256_addsub_pd, _mm256_addsub_ps, _mm256_and_pd, _mm256_and_ps,
        _mm256_andnot_pd, _mm256_andnot_ps, _mm256_blend_pd, _mm256_blend_ps, _mm256_blendv_pd, _mm256_blendv_ps,
        _mm256_broadcast_pd, _mm256_broadcast_ps, _mm256_broadcast_sd, _mm_broadcast_ss, _mm256_broadcast_ss,
        _mm256_castpd_ps, _mm256_castpd_si256, _mm256_castpd128_pd256, _mm256_castpd256_pd128, _mm256_castps_pd,
        _mm256_castps_si256, _mm256_castps128_ps256, _mm256_castps256_ps128, _mm256_castsi128_si256,
        _mm256_castsi256_pd, _mm256_castsi256_ps, _mm256_castsi256_si128, _mm256_ceil_pd, _mm256_ceil_ps,
        _mm_cmp_pd, _mm256_cmp_pd, _mm_cmp_ps, _mm256_cmp_ps, _mm_cmp_sd, _mm_cmp_ss, _mm256_cvtepi32_pd,
        _mm256_cvtepi32_ps, _mm256_cvtpd_epi32, _mm256_cvtpd_ps, _mm256_cvtps_epi32, _mm256_cvtps_pd,
        _mm256_cvtsd_f64, _mm256_cvtsi256_si32, _mm256_cvtss_f32, _mm256_cvttpd_epi32, _mm256_cvttps_epi32,
        _mm256_div_pd, _mm256_div_ps, _mm256_dp_ps, _mm256_extract_epi32, _mm256_extract_epi64,
        _mm256_extractf128_pd, _mm256_extractf128_ps, _mm256_extractf128_si256, _mm256_floor_pd, _mm256_floor_ps,
        _mm256_hadd_pd, _mm256_hadd_ps, _mm256_hsub_pd, _mm256_hsub_ps, _mm256_insert_epi16, _mm256_insert_epi32,
        _mm256_insert_epi64, _mm256_insert_epi8, _mm256_insertf128_pd, _mm256_insertf128_ps,
        _mm256_insertf128_si256, _mm256_lddqu_si256, _mm256_load_pd, _mm256_load_ps, _mm256_load_si256,
        _mm256_loadu_pd, _mm256_loadu_ps, _mm256_loadu_si256, _mm256_loadu2_m128, _mm256_loadu2_m128d,
        _mm256_loadu2_m128i, _mm_maskload_pd, _mm256_maskload_pd, _mm_maskload_ps, _mm256_maskload_ps,
        _mm_maskstore_pd, _mm256_maskstore_pd, _mm_maskstore_ps, _mm256_maskstore_ps, _mm256_max_pd, _mm256_max_ps,
        _mm256_min_pd, _mm256_min_ps, _mm256_movedup_pd, _mm256_movehdup_ps, _mm256_moveldup_ps, _mm256_movemask_pd,
        _mm256_movemask_ps, _mm256_mul_pd, _mm256_mul_ps, _mm256_or_pd, _mm256_or_ps, _mm_permute_pd,
        _mm256_permute_pd, _mm_permute_ps, _mm256_permute_ps, _mm256_permute2f128_pd, _mm256_permute2f128_ps,
        _mm256_permute2f128_si256, _mm_permutevar_pd, _mm256_permutevar_pd, _mm_permutevar_ps, _mm256_permutevar_ps,
        _mm256_rcp_ps, _mm256_round_pd, _mm256_round_ps, _mm256_rsqrt_ps, _mm256_set_epi16, _mm256_set_epi32,
        _mm256_set_epi64x, _mm256_set_epi8, _mm256_set_m128, _mm256_set_m128d, _mm256_set_m128i, _mm256_set_pd,
        _mm256_set_ps, _mm256_set1_epi16, _mm256_set1_epi32, _mm256_set1_epi64x, _mm256_set1_epi8, _mm256_set1_pd,
        _mm256_set1_ps, _mm256_setr_epi16, _mm256_setr_epi32, _mm256_setr_epi64x, _mm256_setr_epi8, _mm256_setr_m128,
        _mm256_setr_m128d, _mm256_setr_m128i, _mm256_setr_pd, _mm256_setr_ps, _mm256_setzero_pd, _mm256_setzero_ps,
        _mm256_setzero_si256, _mm256_shuffle_pd, _mm256_shuffle_ps, _mm256_sqrt_pd, _mm256_sqrt_ps, _mm256_store_pd,
        _mm256_store_ps, _mm256_store_si256, _mm256_storeu_pd, _mm256_storeu_ps, _mm256_storeu_si256,
        _mm256_storeu2_m128, _mm256_storeu2_m128d, _mm256_storeu2_m128i, _mm256_stream_pd, _mm256_stream_ps,
        _mm256_stream_si256, _mm256_sub_pd, _mm256_sub_ps, _mm_testc_pd, _mm256_testc_pd, _mm_testc_ps,
        _mm256_testc_ps, _mm256_testc_si256, _mm_testnzc_pd, _mm256_testnzc_pd, _mm_testnzc_ps, _mm256_testnzc_ps,
        _mm256_testnzc_si256, _mm_testz_pd, _mm256_testz_pd, _mm_testz_ps, _mm256_testz_ps, _mm256_testz_si256,
        _mm256_undefined_pd, _mm256_undefined_ps, _mm256_undefined_si256, _mm256_unpackhi_pd, _mm256_unpackhi_ps,
        _mm256_unpacklo_pd, _mm256_unpacklo_ps, _mm256_xor_pd, _mm256_xor_ps, _mm256_zeroall, _mm256_zeroupper,
        _mm256_zextpd128_pd256, _mm256_zextps128_ps256, _mm256_zextsi128_si256
    }
}

pub mod fma {
    import_intrinsics! {
        _mm_fmadd_pd, _mm256_fmadd_pd, _mm_fmadd_ps, _mm256_fmadd_ps, _mm_fmadd_sd, _mm_fmadd_ss, _mm_fmaddsub_pd,
        _mm256_fmaddsub_pd, _mm_fmaddsub_ps, _mm256_fmaddsub_ps, _mm_fmsub_pd, _mm256_fmsub_pd, _mm_fmsub_ps,
        _mm256_fmsub_ps, _mm_fmsub_sd, _mm_fmsub_ss, _mm_fmsubadd_pd, _mm256_fmsubadd_pd, _mm_fmsubadd_ps,
        _mm256_fmsubadd_ps, _mm_fnmadd_pd, _mm256_fnmadd_pd, _mm_fnmadd_ps, _mm256_fnmadd_ps, _mm_fnmadd_sd,
        _mm_fnmadd_ss, _mm_fnmsub_pd, _mm256_fnmsub_pd, _mm_fnmsub_ps, _mm256_fnmsub_ps, _mm_fnmsub_sd, _mm_fnmsub_ss
    }
}

pub mod avx2 {
    pub use super::avx::*;
    pub use super::fma::*;

    import_intrinsics! {
        _mm256_abs_epi16, _mm256_abs_epi32, _mm256_abs_epi8, _mm256_add_epi16, _mm256_add_epi32, _mm256_add_epi64,
        _mm256_add_epi8, _mm256_adds_epi16, _mm256_adds_epi8, _mm256_adds_epu16, _mm256_adds_epu8, _mm256_alignr_epi8,
        _mm256_and_si256, _mm256_andnot_si256, _mm256_avg_epu16, _mm256_avg_epu8, _mm256_blend_epi16, _mm_blend_epi32,
        _mm256_blend_epi32, _mm256_blendv_epi8, _mm_broadcastb_epi8, _mm256_broadcastb_epi8, _mm_broadcastd_epi32,
        _mm256_broadcastd_epi32, _mm_broadcastq_epi64, _mm256_broadcastq_epi64, _mm_broadcastsd_pd, _mm256_broadcastsd_pd,
        _mm256_broadcastsi128_si256, _mm_broadcastss_ps, _mm256_broadcastss_ps, _mm_broadcastw_epi16,
        _mm256_broadcastw_epi16, _mm256_bslli_epi128, _mm256_bsrli_epi128, _mm256_cmpeq_epi16, _mm256_cmpeq_epi32,
        _mm256_cmpeq_epi64, _mm256_cmpeq_epi8, _mm256_cmpgt_epi16, _mm256_cmpgt_epi32, _mm256_cmpgt_epi64,
        _mm256_cmpgt_epi8, _mm256_cvtepi16_epi32, _mm256_cvtepi16_epi64, _mm256_cvtepi32_epi64, _mm256_cvtepi8_epi16,
        _mm256_cvtepi8_epi32, _mm256_cvtepi8_epi64, _mm256_cvtepu16_epi32, _mm256_cvtepu16_epi64, _mm256_cvtepu32_epi64,
        _mm256_cvtepu8_epi16, _mm256_cvtepu8_epi32, _mm256_cvtepu8_epi64, _mm256_extract_epi16, _mm256_extract_epi8,
        _mm256_extracti128_si256, _mm256_hadd_epi16, _mm256_hadd_epi32, _mm256_hadds_epi16, _mm256_hsub_epi16,
        _mm256_hsub_epi32, _mm256_hsubs_epi16, _mm_i32gather_epi32, _mm_mask_i32gather_epi32, _mm256_i32gather_epi32,
        _mm256_mask_i32gather_epi32, _mm_i32gather_epi64, _mm_mask_i32gather_epi64, _mm256_i32gather_epi64,
        _mm256_mask_i32gather_epi64, _mm_i32gather_pd, _mm_mask_i32gather_pd, _mm256_i32gather_pd,
        _mm256_mask_i32gather_pd, _mm_i32gather_ps, _mm_mask_i32gather_ps, _mm256_i32gather_ps, _mm256_mask_i32gather_ps,
        _mm_i64gather_epi32, _mm_mask_i64gather_epi32, _mm256_i64gather_epi32, _mm256_mask_i64gather_epi32,
        _mm_i64gather_epi64, _mm_mask_i64gather_epi64, _mm256_i64gather_epi64, _mm256_mask_i64gather_epi64,
        _mm_i64gather_pd, _mm_mask_i64gather_pd, _mm256_i64gather_pd, _mm256_mask_i64gather_pd, _mm_i64gather_ps,
        _mm_mask_i64gather_ps, _mm256_i64gather_ps, _mm256_mask_i64gather_ps, _mm256_inserti128_si256, _mm256_madd_epi16,
        _mm256_maddubs_epi16, _mm_maskload_epi32, _mm256_maskload_epi32, _mm_maskload_epi64, _mm256_maskload_epi64,
        _mm_maskstore_epi32, _mm256_maskstore_epi32, _mm_maskstore_epi64, _mm256_maskstore_epi64, _mm256_max_epi16,
        _mm256_max_epi32, _mm256_max_epi8, _mm256_max_epu16, _mm256_max_epu32, _mm256_max_epu8, _mm256_min_epi16,
        _mm256_min_epi32, _mm256_min_epi8, _mm256_min_epu16, _mm256_min_epu32, _mm256_min_epu8, _mm256_movemask_epi8,
        _mm256_mpsadbw_epu8, _mm256_mul_epi32, _mm256_mul_epu32, _mm256_mulhi_epi16, _mm256_mulhi_epu16, _mm256_mulhrs_epi16,
        _mm256_mullo_epi16, _mm256_mullo_epi32, _mm256_or_si256, _mm256_packs_epi16, _mm256_packs_epi32, _mm256_packus_epi16,
        _mm256_packus_epi32, _mm256_permute2x128_si256, _mm256_permute4x64_epi64, _mm256_permute4x64_pd,
        _mm256_permutevar8x32_epi32, _mm256_permutevar8x32_ps, _mm256_sad_epu8, _mm256_shuffle_epi32, _mm256_shuffle_epi8,
        _mm256_shufflehi_epi16, _mm256_shufflelo_epi16, _mm256_sign_epi16, _mm256_sign_epi32, _mm256_sign_epi8,
        _mm256_sll_epi16, _mm256_sll_epi32, _mm256_sll_epi64, _mm256_slli_epi16, _mm256_slli_epi32, _mm256_slli_epi64,
        _mm256_slli_si256, _mm_sllv_epi32, _mm256_sllv_epi32, _mm_sllv_epi64, _mm256_sllv_epi64, _mm256_sra_epi16,
        _mm256_sra_epi32, _mm256_srai_epi16, _mm256_srai_epi32, _mm_srav_epi32, _mm256_srav_epi32, _mm256_srl_epi16,
        _mm256_srl_epi32, _mm256_srl_epi64, _mm256_srli_epi16, _mm256_srli_epi32, _mm256_srli_epi64, _mm256_srli_si256,
        _mm_srlv_epi32, _mm256_srlv_epi32, _mm_srlv_epi64, _mm256_srlv_epi64, _mm256_sub_epi16, _mm256_sub_epi32,
        _mm256_sub_epi64, _mm256_sub_epi8, _mm256_subs_epi16, _mm256_subs_epi8, _mm256_subs_epu16, _mm256_subs_epu8,
        _mm256_unpackhi_epi16, _mm256_unpackhi_epi32, _mm256_unpackhi_epi64, _mm256_unpackhi_epi8, _mm256_unpacklo_epi16,
        _mm256_unpacklo_epi32, _mm256_unpacklo_epi64, _mm256_unpacklo_epi8, _mm256_xor_si256, _mm256_stream_load_si256
    }

    // 128-bit carry-less multiply (PCLMULQDQ). Strictly a separate CPU feature from AVX2,
    // but present on every AVX2 CPU (it shipped with Westmere, 2010). The `avx2-pclmul`
    // feature adds `pclmulqdq` to the dispatched `#[target_feature]` set so this is callable;
    // it powers the CLMUL-based 2D Morton fast path.
    #[cfg(feature = "avx2-pclmul")]
    import_intrinsics! { _mm_clmulepi64_si128 }
}

/// AVX-512 Foundation (F)
///
/// The baseline instruction set for AVX-512. This module provides intrinsics for
/// the fundamental 512-bit ZMM registers, opmask registers (`k0`-`k7`), and EVEX
/// encoding support.
#[rustfmt::skip]
pub mod avx512f {
    pub use super::avx2::*;

    import_intrinsics! { __m512, __m512d, __m512i, __mmask8, __mmask16, __mmask32, __mmask64 }

    import_intrinsics! { _MM_CMPINT_ENUM, _MM_MANTISSA_NORM_ENUM, _MM_MANTISSA_SIGN_ENUM, _MM_PERM_ENUM }

    /// AVX512 instructions, organized into support tiers
    pub mod tiers {
        pub(super) use super::*;

        /// Oldest AVX512 CPUs
        ///
        /// F + CD: exactly the Knights Landing set. 512-bit only -- without VL
        /// (tier 2) there are no EVEX encodings at 128/256-bit, so nothing here
        /// can accelerate the existing `f32x4`/`f32x8` registers.
        pub mod tier1 {
            pub use super::*;
            pub use super::avx512cd::*;
        }

        /// Common AVX512 CPUs
        ///
        /// Tier 1 + BW + DQ + **VL**. Skylake-SP introduced the three together
        /// and no CPU has BW/DQ without VL, so they form one rung.
        ///
        /// VL contributes no module of its own: it is not new operations but the
        /// EVEX encodings (masking, zero-masking, embedded broadcast, registers
        /// 16-31) applied to XMM/YMM instead of ZMM only. In practice that means
        /// the 128/256-bit masked intrinsics, which `core::arch` gates on
        /// `avx512vl,avx512f` -- so a backend built on this tier MUST put
        /// `avx512vl` in its `#[target_feature]` set, and importing those
        /// intrinsics here without it will not compile.
        ///
        /// This is the rung that matters most for this crate: it is what turns
        /// the `_c`/`_m`/`_z` variants into single masked instructions at the
        /// register widths thermite already uses.
        pub mod tier2 {
            pub use super::tier1::*;

            pub use super::avx512bw::*;
            pub use super::avx512dq::*;
        }

        /// Very modern CPUs
        pub mod tier3 {
            pub use super::tier2::*;

            pub use super::avx512vbmi::*;
            pub use super::avx512vbmi2::*;
            pub use super::avx512vnni::*;
            pub use super::avx512bitalg::*;
            pub use super::avx512vpopcntdq::*;
            pub use super::avx512ifma::*;
            pub use super::gfni::*;
            pub use super::vaes::*;
            pub use super::vpclmulqdq::*;
        }

        /// Cutting-edge
        pub mod tier4 {
            pub use super::tier3::*;

            pub use super::bf16::*;
        }
    }

    /// Vector AES (VAES)
    ///
    /// Extension of AES-NI to support EVEX encoding and wider vector registers.
    pub mod vaes {
        import_intrinsics! {
            _mm512_aesdec_epi128,
            _mm512_aesdeclast_epi128,
            _mm512_aesenc_epi128,
            _mm512_aesenclast_epi128
        }
    }

    /// Galois Field New Instructions (GFNI)
    ///
    /// Acceleration for affine transformations over finite fields, specifically
    /// $GF(2^8)$.
    pub mod gfni {
        import_intrinsics! {
            _mm256_mask_gf2p8affine_epi64_epi8,
            _mm256_mask_gf2p8affineinv_epi64_epi8,
            _mm256_mask_gf2p8mul_epi8,
            _mm256_maskz_gf2p8affine_epi64_epi8,
            _mm256_maskz_gf2p8affineinv_epi64_epi8,
            _mm256_maskz_gf2p8mul_epi8,
            _mm512_gf2p8affine_epi64_epi8,
            _mm512_gf2p8affineinv_epi64_epi8,
            _mm512_gf2p8mul_epi8,
            _mm512_mask_gf2p8affine_epi64_epi8,
            _mm512_mask_gf2p8affineinv_epi64_epi8,
            _mm512_mask_gf2p8mul_epi8,
            _mm512_maskz_gf2p8affine_epi64_epi8,
            _mm512_maskz_gf2p8affineinv_epi64_epi8,
            _mm512_maskz_gf2p8mul_epi8,
            _mm_mask_gf2p8affine_epi64_epi8,
            _mm_mask_gf2p8affineinv_epi64_epi8,
            _mm_mask_gf2p8mul_epi8,
            _mm_maskz_gf2p8affine_epi64_epi8,
            _mm_maskz_gf2p8affineinv_epi64_epi8,
            _mm_maskz_gf2p8mul_epi8
        }
    }

    /// Vector Carry-less Multiplication (VPCLMULQDQ)
    ///
    /// Extension of the legacy PCLMULQDQ instruction to EVEX encoding.
    pub mod vpclmulqdq {
        import_intrinsics! {
            _mm256_clmulepi64_epi128,
            _mm512_clmulepi64_epi128
        }
    }

    /// AVX-512 BFloat16 (BF16)
    ///
    /// Support for the Brain Floating Point (BFloat16) format, optimized for deep
    /// learning training and inference.
    pub mod bf16 {
        import_intrinsics! { __m128bh, __m256bh, __m512bh }

        import_intrinsics! {
            _mm256_cvtne2ps_pbh,
            _mm256_cvtneps_pbh,
            _mm256_cvtpbh_ps,
            _mm256_dpbf16_ps,
            _mm256_mask_cvtne2ps_pbh,
            _mm256_mask_cvtneps_pbh,
            _mm256_mask_cvtpbh_ps,
            _mm256_mask_dpbf16_ps,
            _mm256_maskz_cvtne2ps_pbh,
            _mm256_maskz_cvtneps_pbh,
            _mm256_maskz_cvtpbh_ps,
            _mm256_maskz_dpbf16_ps,
            _mm512_cvtne2ps_pbh,
            _mm512_cvtneps_pbh,
            _mm512_cvtpbh_ps,
            _mm512_dpbf16_ps,
            _mm512_mask_cvtne2ps_pbh,
            _mm512_mask_cvtneps_pbh,
            _mm512_mask_cvtpbh_ps,
            _mm512_mask_dpbf16_ps,
            _mm512_maskz_cvtne2ps_pbh,
            _mm512_maskz_cvtneps_pbh,
            _mm512_maskz_cvtpbh_ps,
            _mm512_maskz_dpbf16_ps,
            _mm_cvtne2ps_pbh,
            _mm_cvtneps_pbh,
            // _mm_cvtness_sbh Experimental,
            _mm_cvtpbh_ps,
            // _mm_cvtsbh_ss Experimental,
            _mm_dpbf16_ps,
            _mm_mask_cvtne2ps_pbh,
            _mm_mask_cvtneps_pbh,
            _mm_mask_cvtpbh_ps,
            _mm_mask_dpbf16_ps,
            _mm_maskz_cvtne2ps_pbh,
            _mm_maskz_cvtneps_pbh,
            _mm_maskz_cvtpbh_ps,
            _mm_maskz_dpbf16_ps
        }
    }

    /// AVX-512 Bit Algorithms (BITALG)
    ///
    /// Extensions for bit manipulation at byte and word granularity.
    pub mod avx512bitalg {
        import_intrinsics! {
            _mm256_bitshuffle_epi64_mask,
            _mm256_mask_bitshuffle_epi64_mask,
            _mm256_mask_popcnt_epi16,
            _mm256_mask_popcnt_epi8,
            _mm256_maskz_popcnt_epi16,
            _mm256_maskz_popcnt_epi8,
            _mm256_popcnt_epi16,
            _mm256_popcnt_epi8,
            _mm512_bitshuffle_epi64_mask,
            _mm512_mask_bitshuffle_epi64_mask,
            _mm512_mask_popcnt_epi16,
            _mm512_mask_popcnt_epi8,
            _mm512_maskz_popcnt_epi16,
            _mm512_maskz_popcnt_epi8,
            _mm512_popcnt_epi16,
            _mm512_popcnt_epi8,
            _mm_bitshuffle_epi64_mask,
            _mm_mask_bitshuffle_epi64_mask,
            _mm_mask_popcnt_epi16,
            _mm_mask_popcnt_epi8,
            _mm_maskz_popcnt_epi16,
            _mm_maskz_popcnt_epi8,
            _mm_popcnt_epi16,
            _mm_popcnt_epi8,
        }
    }

    /// AVX-512 Byte and Word (BW)
    ///
    /// Extends AVX-512 vector operations to 8-bit (`u8`/`i8`) and 16-bit (`u16`/`i16`)
    /// integer types.
    pub mod avx512bw {
        import_intrinsics! {
            _mm256_cmp_epi16_mask,
            _mm256_cmp_epi8_mask,
            _mm256_cmp_epu16_mask,
            _mm256_cmp_epu8_mask,
            _mm256_cmpeq_epi16_mask,
            _mm256_cmpeq_epi8_mask,
            _mm256_cmpeq_epu16_mask,
            _mm256_cmpeq_epu8_mask,
            _mm256_cmpge_epi16_mask,
            _mm256_cmpge_epi8_mask,
            _mm256_cmpge_epu16_mask,
            _mm256_cmpge_epu8_mask,
            _mm256_cmpgt_epi16_mask,
            _mm256_cmpgt_epi8_mask,
            _mm256_cmpgt_epu16_mask,
            _mm256_cmpgt_epu8_mask,
            _mm256_cmple_epi16_mask,
            _mm256_cmple_epi8_mask,
            _mm256_cmple_epu16_mask,
            _mm256_cmple_epu8_mask,
            _mm256_cmplt_epi16_mask,
            _mm256_cmplt_epi8_mask,
            _mm256_cmplt_epu16_mask,
            _mm256_cmplt_epu8_mask,
            _mm256_cmpneq_epi16_mask,
            _mm256_cmpneq_epi8_mask,
            _mm256_cmpneq_epu16_mask,
            _mm256_cmpneq_epu8_mask,
            _mm256_cvtepi16_epi8,
            _mm256_cvtsepi16_epi8,
            _mm256_cvtusepi16_epi8,
            _mm256_dbsad_epu8,
            _mm256_loadu_epi16,
            _mm256_loadu_epi8,
            _mm256_mask2_permutex2var_epi16,
            _mm256_mask_abs_epi16,
            _mm256_mask_abs_epi8,
            _mm256_mask_add_epi16,
            _mm256_mask_add_epi8,
            _mm256_mask_adds_epi16,
            _mm256_mask_adds_epi8,
            _mm256_mask_adds_epu16,
            _mm256_mask_adds_epu8,
            _mm256_mask_alignr_epi8,
            _mm256_mask_avg_epu16,
            _mm256_mask_avg_epu8,
            _mm256_mask_blend_epi16,
            _mm256_mask_blend_epi8,
            _mm256_mask_broadcastb_epi8,
            _mm256_mask_broadcastw_epi16,
            _mm256_mask_cmp_epi16_mask,
            _mm256_mask_cmp_epi8_mask,
            _mm256_mask_cmp_epu16_mask,
            _mm256_mask_cmp_epu8_mask,
            _mm256_mask_cmpeq_epi16_mask,
            _mm256_mask_cmpeq_epi8_mask,
            _mm256_mask_cmpeq_epu16_mask,
            _mm256_mask_cmpeq_epu8_mask,
            _mm256_mask_cmpge_epi16_mask,
            _mm256_mask_cmpge_epi8_mask,
            _mm256_mask_cmpge_epu16_mask,
            _mm256_mask_cmpge_epu8_mask,
            _mm256_mask_cmpgt_epi16_mask,
            _mm256_mask_cmpgt_epi8_mask,
            _mm256_mask_cmpgt_epu16_mask,
            _mm256_mask_cmpgt_epu8_mask,
            _mm256_mask_cmple_epi16_mask,
            _mm256_mask_cmple_epi8_mask,
            _mm256_mask_cmple_epu16_mask,
            _mm256_mask_cmple_epu8_mask,
            _mm256_mask_cmplt_epi16_mask,
            _mm256_mask_cmplt_epi8_mask,
            _mm256_mask_cmplt_epu16_mask,
            _mm256_mask_cmplt_epu8_mask,
            _mm256_mask_cmpneq_epi16_mask,
            _mm256_mask_cmpneq_epi8_mask,
            _mm256_mask_cmpneq_epu16_mask,
            _mm256_mask_cmpneq_epu8_mask,
            _mm256_mask_cvtepi16_epi8,
            _mm256_mask_cvtepi16_storeu_epi8,
            _mm256_mask_cvtepi8_epi16,
            _mm256_mask_cvtepu8_epi16,
            _mm256_mask_cvtsepi16_epi8,
            _mm256_mask_cvtsepi16_storeu_epi8,
            _mm256_mask_cvtusepi16_epi8,
            _mm256_mask_cvtusepi16_storeu_epi8,
            _mm256_mask_dbsad_epu8,
            _mm256_mask_loadu_epi16,
            _mm256_mask_loadu_epi8,
            _mm256_mask_madd_epi16,
            _mm256_mask_maddubs_epi16,
            _mm256_mask_max_epi16,
            _mm256_mask_max_epi8,
            _mm256_mask_max_epu16,
            _mm256_mask_max_epu8,
            _mm256_mask_min_epi16,
            _mm256_mask_min_epi8,
            _mm256_mask_min_epu16,
            _mm256_mask_min_epu8,
            _mm256_mask_mov_epi16,
            _mm256_mask_mov_epi8,
            _mm256_mask_mulhi_epi16,
            _mm256_mask_mulhi_epu16,
            _mm256_mask_mulhrs_epi16,
            _mm256_mask_mullo_epi16,
            _mm256_mask_packs_epi16,
            _mm256_mask_packs_epi32,
            _mm256_mask_packus_epi16,
            _mm256_mask_packus_epi32,
            _mm256_mask_permutex2var_epi16,
            _mm256_mask_permutexvar_epi16,
            _mm256_mask_reduce_add_epi16,
            _mm256_mask_reduce_add_epi8,
            _mm256_mask_reduce_and_epi16,
            _mm256_mask_reduce_and_epi8,
            _mm256_mask_reduce_max_epi16,
            _mm256_mask_reduce_max_epi8,
            _mm256_mask_reduce_max_epu16,
            _mm256_mask_reduce_max_epu8,
            _mm256_mask_reduce_min_epi16,
            _mm256_mask_reduce_min_epi8,
            _mm256_mask_reduce_min_epu16,
            _mm256_mask_reduce_min_epu8,
            _mm256_mask_reduce_mul_epi16,
            _mm256_mask_reduce_mul_epi8,
            _mm256_mask_reduce_or_epi16,
            _mm256_mask_reduce_or_epi8,
            _mm256_mask_set1_epi16,
            _mm256_mask_set1_epi8,
            _mm256_mask_shuffle_epi8,
            _mm256_mask_shufflehi_epi16,
            _mm256_mask_shufflelo_epi16,
            _mm256_mask_sll_epi16,
            _mm256_mask_slli_epi16,
            _mm256_mask_sllv_epi16,
            _mm256_mask_sra_epi16,
            _mm256_mask_srai_epi16,
            _mm256_mask_srav_epi16,
            _mm256_mask_srl_epi16,
            _mm256_mask_srli_epi16,
            _mm256_mask_srlv_epi16,
            _mm256_mask_storeu_epi16,
            _mm256_mask_storeu_epi8,
            _mm256_mask_sub_epi16,
            _mm256_mask_sub_epi8,
            _mm256_mask_subs_epi16,
            _mm256_mask_subs_epi8,
            _mm256_mask_subs_epu16,
            _mm256_mask_subs_epu8,
            _mm256_mask_test_epi16_mask,
            _mm256_mask_test_epi8_mask,
            _mm256_mask_testn_epi16_mask,
            _mm256_mask_testn_epi8_mask,
            _mm256_mask_unpackhi_epi16,
            _mm256_mask_unpackhi_epi8,
            _mm256_mask_unpacklo_epi16,
            _mm256_mask_unpacklo_epi8,
            _mm256_maskz_abs_epi16,
            _mm256_maskz_abs_epi8,
            _mm256_maskz_add_epi16,
            _mm256_maskz_add_epi8,
            _mm256_maskz_adds_epi16,
            _mm256_maskz_adds_epi8,
            _mm256_maskz_adds_epu16,
            _mm256_maskz_adds_epu8,
            _mm256_maskz_alignr_epi8,
            _mm256_maskz_avg_epu16,
            _mm256_maskz_avg_epu8,
            _mm256_maskz_broadcastb_epi8,
            _mm256_maskz_broadcastw_epi16,
            _mm256_maskz_cvtepi16_epi8,
            _mm256_maskz_cvtepi8_epi16,
            _mm256_maskz_cvtepu8_epi16,
            _mm256_maskz_cvtsepi16_epi8,
            _mm256_maskz_cvtusepi16_epi8,
            _mm256_maskz_dbsad_epu8,
            _mm256_maskz_loadu_epi16,
            _mm256_maskz_loadu_epi8,
            _mm256_maskz_madd_epi16,
            _mm256_maskz_maddubs_epi16,
            _mm256_maskz_max_epi16,
            _mm256_maskz_max_epi8,
            _mm256_maskz_max_epu16,
            _mm256_maskz_max_epu8,
            _mm256_maskz_min_epi16,
            _mm256_maskz_min_epi8,
            _mm256_maskz_min_epu16,
            _mm256_maskz_min_epu8,
            _mm256_maskz_mov_epi16,
            _mm256_maskz_mov_epi8,
            _mm256_maskz_mulhi_epi16,
            _mm256_maskz_mulhi_epu16,
            _mm256_maskz_mulhrs_epi16,
            _mm256_maskz_mullo_epi16,
            _mm256_maskz_packs_epi16,
            _mm256_maskz_packs_epi32,
            _mm256_maskz_packus_epi16,
            _mm256_maskz_packus_epi32,
            _mm256_maskz_permutex2var_epi16,
            _mm256_maskz_permutexvar_epi16,
            _mm256_maskz_set1_epi16,
            _mm256_maskz_set1_epi8,
            _mm256_maskz_shuffle_epi8,
            _mm256_maskz_shufflehi_epi16,
            _mm256_maskz_shufflelo_epi16,
            _mm256_maskz_sll_epi16,
            _mm256_maskz_slli_epi16,
            _mm256_maskz_sllv_epi16,
            _mm256_maskz_sra_epi16,
            _mm256_maskz_srai_epi16,
            _mm256_maskz_srav_epi16,
            _mm256_maskz_srl_epi16,
            _mm256_maskz_srli_epi16,
            _mm256_maskz_srlv_epi16,
            _mm256_maskz_sub_epi16,
            _mm256_maskz_sub_epi8,
            _mm256_maskz_subs_epi16,
            _mm256_maskz_subs_epi8,
            _mm256_maskz_subs_epu16,
            _mm256_maskz_subs_epu8,
            _mm256_maskz_unpackhi_epi16,
            _mm256_maskz_unpackhi_epi8,
            _mm256_maskz_unpacklo_epi16,
            _mm256_maskz_unpacklo_epi8,
            _mm256_movepi16_mask,
            _mm256_movepi8_mask,
            _mm256_movm_epi16,
            _mm256_movm_epi8,
            _mm256_permutex2var_epi16,
            _mm256_permutexvar_epi16,
            _mm256_reduce_add_epi16,
            _mm256_reduce_add_epi8,
            _mm256_reduce_and_epi16,
            _mm256_reduce_and_epi8,
            _mm256_reduce_max_epi16,
            _mm256_reduce_max_epi8,
            _mm256_reduce_max_epu16,
            _mm256_reduce_max_epu8,
            _mm256_reduce_min_epi16,
            _mm256_reduce_min_epi8,
            _mm256_reduce_min_epu16,
            _mm256_reduce_min_epu8,
            _mm256_reduce_mul_epi16,
            _mm256_reduce_mul_epi8,
            _mm256_reduce_or_epi16,
            _mm256_reduce_or_epi8,
            _mm256_sllv_epi16,
            _mm256_srav_epi16,
            _mm256_srlv_epi16,
            _mm256_storeu_epi16,
            _mm256_storeu_epi8,
            _mm256_test_epi16_mask,
            _mm256_test_epi8_mask,
            _mm256_testn_epi16_mask,
            _mm256_testn_epi8_mask,
            _mm512_abs_epi16,
            _mm512_abs_epi8,
            _mm512_add_epi16,
            _mm512_add_epi8,
            _mm512_adds_epi16,
            _mm512_adds_epi8,
            _mm512_adds_epu16,
            _mm512_adds_epu8,
            _mm512_alignr_epi8,
            _mm512_avg_epu16,
            _mm512_avg_epu8,
            _mm512_broadcastb_epi8,
            _mm512_broadcastw_epi16,
            _mm512_bslli_epi128,
            _mm512_bsrli_epi128,
            _mm512_cmp_epi16_mask,
            _mm512_cmp_epi8_mask,
            _mm512_cmp_epu16_mask,
            _mm512_cmp_epu8_mask,
            _mm512_cmpeq_epi16_mask,
            _mm512_cmpeq_epi8_mask,
            _mm512_cmpeq_epu16_mask,
            _mm512_cmpeq_epu8_mask,
            _mm512_cmpge_epi16_mask,
            _mm512_cmpge_epi8_mask,
            _mm512_cmpge_epu16_mask,
            _mm512_cmpge_epu8_mask,
            _mm512_cmpgt_epi16_mask,
            _mm512_cmpgt_epi8_mask,
            _mm512_cmpgt_epu16_mask,
            _mm512_cmpgt_epu8_mask,
            _mm512_cmple_epi16_mask,
            _mm512_cmple_epi8_mask,
            _mm512_cmple_epu16_mask,
            _mm512_cmple_epu8_mask,
            _mm512_cmplt_epi16_mask,
            _mm512_cmplt_epi8_mask,
            _mm512_cmplt_epu16_mask,
            _mm512_cmplt_epu8_mask,
            _mm512_cmpneq_epi16_mask,
            _mm512_cmpneq_epi8_mask,
            _mm512_cmpneq_epu16_mask,
            _mm512_cmpneq_epu8_mask,
            _mm512_cvtepi16_epi8,
            _mm512_cvtepi8_epi16,
            _mm512_cvtepu8_epi16,
            _mm512_cvtsepi16_epi8,
            _mm512_cvtusepi16_epi8,
            _mm512_dbsad_epu8,
            _mm512_kunpackd,
            _mm512_kunpackw,
            _mm512_loadu_epi16,
            _mm512_loadu_epi8,
            _mm512_madd_epi16,
            _mm512_maddubs_epi16,
            _mm512_mask2_permutex2var_epi16,
            _mm512_mask_abs_epi16,
            _mm512_mask_abs_epi8,
            _mm512_mask_add_epi16,
            _mm512_mask_add_epi8,
            _mm512_mask_adds_epi16,
            _mm512_mask_adds_epi8,
            _mm512_mask_adds_epu16,
            _mm512_mask_adds_epu8,
            _mm512_mask_alignr_epi8,
            _mm512_mask_avg_epu16,
            _mm512_mask_avg_epu8,
            _mm512_mask_blend_epi16,
            _mm512_mask_blend_epi8,
            _mm512_mask_broadcastb_epi8,
            _mm512_mask_broadcastw_epi16,
            _mm512_mask_cmp_epi16_mask,
            _mm512_mask_cmp_epi8_mask,
            _mm512_mask_cmp_epu16_mask,
            _mm512_mask_cmp_epu8_mask,
            _mm512_mask_cmpeq_epi16_mask,
            _mm512_mask_cmpeq_epi8_mask,
            _mm512_mask_cmpeq_epu16_mask,
            _mm512_mask_cmpeq_epu8_mask,
            _mm512_mask_cmpge_epi16_mask,
            _mm512_mask_cmpge_epi8_mask,
            _mm512_mask_cmpge_epu16_mask,
            _mm512_mask_cmpge_epu8_mask,
            _mm512_mask_cmpgt_epi16_mask,
            _mm512_mask_cmpgt_epi8_mask,
            _mm512_mask_cmpgt_epu16_mask,
            _mm512_mask_cmpgt_epu8_mask,
            _mm512_mask_cmple_epi16_mask,
            _mm512_mask_cmple_epi8_mask,
            _mm512_mask_cmple_epu16_mask,
            _mm512_mask_cmple_epu8_mask,
            _mm512_mask_cmplt_epi16_mask,
            _mm512_mask_cmplt_epi8_mask,
            _mm512_mask_cmplt_epu16_mask,
            _mm512_mask_cmplt_epu8_mask,
            _mm512_mask_cmpneq_epi16_mask,
            _mm512_mask_cmpneq_epi8_mask,
            _mm512_mask_cmpneq_epu16_mask,
            _mm512_mask_cmpneq_epu8_mask,
            _mm512_mask_cvtepi16_epi8,
            _mm512_mask_cvtepi16_storeu_epi8,
            _mm512_mask_cvtepi8_epi16,
            _mm512_mask_cvtepu8_epi16,
            _mm512_mask_cvtsepi16_epi8,
            _mm512_mask_cvtsepi16_storeu_epi8,
            _mm512_mask_cvtusepi16_epi8,
            _mm512_mask_cvtusepi16_storeu_epi8,
            _mm512_mask_dbsad_epu8,
            _mm512_mask_loadu_epi16,
            _mm512_mask_loadu_epi8,
            _mm512_mask_madd_epi16,
            _mm512_mask_maddubs_epi16,
            _mm512_mask_max_epi16,
            _mm512_mask_max_epi8,
            _mm512_mask_max_epu16,
            _mm512_mask_max_epu8,
            _mm512_mask_min_epi16,
            _mm512_mask_min_epi8,
            _mm512_mask_min_epu16,
            _mm512_mask_min_epu8,
            _mm512_mask_mov_epi16,
            _mm512_mask_mov_epi8,
            _mm512_mask_mulhi_epi16,
            _mm512_mask_mulhi_epu16,
            _mm512_mask_mulhrs_epi16,
            _mm512_mask_mullo_epi16,
            _mm512_mask_packs_epi16,
            _mm512_mask_packs_epi32,
            _mm512_mask_packus_epi16,
            _mm512_mask_packus_epi32,
            _mm512_mask_permutex2var_epi16,
            _mm512_mask_permutexvar_epi16,
            _mm512_mask_set1_epi16,
            _mm512_mask_set1_epi8,
            _mm512_mask_shuffle_epi8,
            _mm512_mask_shufflehi_epi16,
            _mm512_mask_shufflelo_epi16,
            _mm512_mask_sll_epi16,
            _mm512_mask_slli_epi16,
            _mm512_mask_sllv_epi16,
            _mm512_mask_sra_epi16,
            _mm512_mask_srai_epi16,
            _mm512_mask_srav_epi16,
            _mm512_mask_srl_epi16,
            _mm512_mask_srli_epi16,
            _mm512_mask_srlv_epi16,
            _mm512_mask_storeu_epi16,
            _mm512_mask_storeu_epi8,
            _mm512_mask_sub_epi16,
            _mm512_mask_sub_epi8,
            _mm512_mask_subs_epi16,
            _mm512_mask_subs_epi8,
            _mm512_mask_subs_epu16,
            _mm512_mask_subs_epu8,
            _mm512_mask_test_epi16_mask,
            _mm512_mask_test_epi8_mask,
            _mm512_mask_testn_epi16_mask,
            _mm512_mask_testn_epi8_mask,
            _mm512_mask_unpackhi_epi16,
            _mm512_mask_unpackhi_epi8,
            _mm512_mask_unpacklo_epi16,
            _mm512_mask_unpacklo_epi8,
            _mm512_maskz_abs_epi16,
            _mm512_maskz_abs_epi8,
            _mm512_maskz_add_epi16,
            _mm512_maskz_add_epi8,
            _mm512_maskz_adds_epi16,
            _mm512_maskz_adds_epi8,
            _mm512_maskz_adds_epu16,
            _mm512_maskz_adds_epu8,
            _mm512_maskz_alignr_epi8,
            _mm512_maskz_avg_epu16,
            _mm512_maskz_avg_epu8,
            _mm512_maskz_broadcastb_epi8,
            _mm512_maskz_broadcastw_epi16,
            _mm512_maskz_cvtepi16_epi8,
            _mm512_maskz_cvtepi8_epi16,
            _mm512_maskz_cvtepu8_epi16,
            _mm512_maskz_cvtsepi16_epi8,
            _mm512_maskz_cvtusepi16_epi8,
            _mm512_maskz_dbsad_epu8,
            _mm512_maskz_loadu_epi16,
            _mm512_maskz_loadu_epi8,
            _mm512_maskz_madd_epi16,
            _mm512_maskz_maddubs_epi16,
            _mm512_maskz_max_epi16,
            _mm512_maskz_max_epi8,
            _mm512_maskz_max_epu16,
            _mm512_maskz_max_epu8,
            _mm512_maskz_min_epi16,
            _mm512_maskz_min_epi8,
            _mm512_maskz_min_epu16,
            _mm512_maskz_min_epu8,
            _mm512_maskz_mov_epi16,
            _mm512_maskz_mov_epi8,
            _mm512_maskz_mulhi_epi16,
            _mm512_maskz_mulhi_epu16,
            _mm512_maskz_mulhrs_epi16,
            _mm512_maskz_mullo_epi16,
            _mm512_maskz_packs_epi16,
            _mm512_maskz_packs_epi32,
            _mm512_maskz_packus_epi16,
            _mm512_maskz_packus_epi32,
            _mm512_maskz_permutex2var_epi16,
            _mm512_maskz_permutexvar_epi16,
            _mm512_maskz_set1_epi16,
            _mm512_maskz_set1_epi8,
            _mm512_maskz_shuffle_epi8,
            _mm512_maskz_shufflehi_epi16,
            _mm512_maskz_shufflelo_epi16,
            _mm512_maskz_sll_epi16,
            _mm512_maskz_slli_epi16,
            _mm512_maskz_sllv_epi16,
            _mm512_maskz_sra_epi16,
            _mm512_maskz_srai_epi16,
            _mm512_maskz_srav_epi16,
            _mm512_maskz_srl_epi16,
            _mm512_maskz_srli_epi16,
            _mm512_maskz_srlv_epi16,
            _mm512_maskz_sub_epi16,
            _mm512_maskz_sub_epi8,
            _mm512_maskz_subs_epi16,
            _mm512_maskz_subs_epi8,
            _mm512_maskz_subs_epu16,
            _mm512_maskz_subs_epu8,
            _mm512_maskz_unpackhi_epi16,
            _mm512_maskz_unpackhi_epi8,
            _mm512_maskz_unpacklo_epi16,
            _mm512_maskz_unpacklo_epi8,
            _mm512_max_epi16,
            _mm512_max_epi8,
            _mm512_max_epu16,
            _mm512_max_epu8,
            _mm512_min_epi16,
            _mm512_min_epi8,
            _mm512_min_epu16,
            _mm512_min_epu8,
            _mm512_movepi16_mask,
            _mm512_movepi8_mask,
            _mm512_movm_epi16,
            _mm512_movm_epi8,
            _mm512_mulhi_epi16,
            _mm512_mulhi_epu16,
            _mm512_mulhrs_epi16,
            _mm512_mullo_epi16,
            _mm512_packs_epi16,
            _mm512_packs_epi32,
            _mm512_packus_epi16,
            _mm512_packus_epi32,
            _mm512_permutex2var_epi16,
            _mm512_permutexvar_epi16,
            _mm512_sad_epu8,
            _mm512_shuffle_epi8,
            _mm512_shufflehi_epi16,
            _mm512_shufflelo_epi16,
            _mm512_sll_epi16,
            _mm512_slli_epi16,
            _mm512_sllv_epi16,
            _mm512_sra_epi16,
            _mm512_srai_epi16,
            _mm512_srav_epi16,
            _mm512_srl_epi16,
            _mm512_srli_epi16,
            _mm512_srlv_epi16,
            _mm512_storeu_epi16,
            _mm512_storeu_epi8,
            _mm512_sub_epi16,
            _mm512_sub_epi8,
            _mm512_subs_epi16,
            _mm512_subs_epi8,
            _mm512_subs_epu16,
            _mm512_subs_epu8,
            _mm512_test_epi16_mask,
            _mm512_test_epi8_mask,
            _mm512_testn_epi16_mask,
            _mm512_testn_epi8_mask,
            _mm512_unpackhi_epi16,
            _mm512_unpackhi_epi8,
            _mm512_unpacklo_epi16,
            _mm512_unpacklo_epi8,
            _mm_cmp_epi16_mask,
            _mm_cmp_epi8_mask,
            _mm_cmp_epu16_mask,
            _mm_cmp_epu8_mask,
            _mm_cmpeq_epi16_mask,
            _mm_cmpeq_epi8_mask,
            _mm_cmpeq_epu16_mask,
            _mm_cmpeq_epu8_mask,
            _mm_cmpge_epi16_mask,
            _mm_cmpge_epi8_mask,
            _mm_cmpge_epu16_mask,
            _mm_cmpge_epu8_mask,
            _mm_cmpgt_epi16_mask,
            _mm_cmpgt_epi8_mask,
            _mm_cmpgt_epu16_mask,
            _mm_cmpgt_epu8_mask,
            _mm_cmple_epi16_mask,
            _mm_cmple_epi8_mask,
            _mm_cmple_epu16_mask,
            _mm_cmple_epu8_mask,
            _mm_cmplt_epi16_mask,
            _mm_cmplt_epi8_mask,
            _mm_cmplt_epu16_mask,
            _mm_cmplt_epu8_mask,
            _mm_cmpneq_epi16_mask,
            _mm_cmpneq_epi8_mask,
            _mm_cmpneq_epu16_mask,
            _mm_cmpneq_epu8_mask,
            _mm_cvtepi16_epi8,
            _mm_cvtsepi16_epi8,
            _mm_cvtusepi16_epi8,
            _mm_dbsad_epu8,
            _mm_loadu_epi16,
            _mm_loadu_epi8,
            _mm_mask2_permutex2var_epi16,
            _mm_mask_abs_epi16,
            _mm_mask_abs_epi8,
            _mm_mask_add_epi16,
            _mm_mask_add_epi8,
            _mm_mask_adds_epi16,
            _mm_mask_adds_epi8,
            _mm_mask_adds_epu16,
            _mm_mask_adds_epu8,
            _mm_mask_alignr_epi8,
            _mm_mask_avg_epu16,
            _mm_mask_avg_epu8,
            _mm_mask_blend_epi16,
            _mm_mask_blend_epi8,
            _mm_mask_broadcastb_epi8,
            _mm_mask_broadcastw_epi16,
            _mm_mask_cmp_epi16_mask,
            _mm_mask_cmp_epi8_mask,
            _mm_mask_cmp_epu16_mask,
            _mm_mask_cmp_epu8_mask,
            _mm_mask_cmpeq_epi16_mask,
            _mm_mask_cmpeq_epi8_mask,
            _mm_mask_cmpeq_epu16_mask,
            _mm_mask_cmpeq_epu8_mask,
            _mm_mask_cmpge_epi16_mask,
            _mm_mask_cmpge_epi8_mask,
            _mm_mask_cmpge_epu16_mask,
            _mm_mask_cmpge_epu8_mask,
            _mm_mask_cmpgt_epi16_mask,
            _mm_mask_cmpgt_epi8_mask,
            _mm_mask_cmpgt_epu16_mask,
            _mm_mask_cmpgt_epu8_mask,
            _mm_mask_cmple_epi16_mask,
            _mm_mask_cmple_epi8_mask,
            _mm_mask_cmple_epu16_mask,
            _mm_mask_cmple_epu8_mask,
            _mm_mask_cmplt_epi16_mask,
            _mm_mask_cmplt_epi8_mask,
            _mm_mask_cmplt_epu16_mask,
            _mm_mask_cmplt_epu8_mask,
            _mm_mask_cmpneq_epi16_mask,
            _mm_mask_cmpneq_epi8_mask,
            _mm_mask_cmpneq_epu16_mask,
            _mm_mask_cmpneq_epu8_mask,
            _mm_mask_cvtepi16_epi8,
            _mm_mask_cvtepi16_storeu_epi8,
            _mm_mask_cvtepi8_epi16,
            _mm_mask_cvtepu8_epi16,
            _mm_mask_cvtsepi16_epi8,
            _mm_mask_cvtsepi16_storeu_epi8,
            _mm_mask_cvtusepi16_epi8,
            _mm_mask_cvtusepi16_storeu_epi8,
            _mm_mask_dbsad_epu8,
            _mm_mask_loadu_epi16,
            _mm_mask_loadu_epi8,
            _mm_mask_madd_epi16,
            _mm_mask_maddubs_epi16,
            _mm_mask_max_epi16,
            _mm_mask_max_epi8,
            _mm_mask_max_epu16,
            _mm_mask_max_epu8,
            _mm_mask_min_epi16,
            _mm_mask_min_epi8,
            _mm_mask_min_epu16,
            _mm_mask_min_epu8,
            _mm_mask_mov_epi16,
            _mm_mask_mov_epi8,
            _mm_mask_mulhi_epi16,
            _mm_mask_mulhi_epu16,
            _mm_mask_mulhrs_epi16,
            _mm_mask_mullo_epi16,
            _mm_mask_packs_epi16,
            _mm_mask_packs_epi32,
            _mm_mask_packus_epi16,
            _mm_mask_packus_epi32,
            _mm_mask_permutex2var_epi16,
            _mm_mask_permutexvar_epi16,
            _mm_mask_reduce_add_epi16,
            _mm_mask_reduce_add_epi8,
            _mm_mask_reduce_and_epi16,
            _mm_mask_reduce_and_epi8,
            _mm_mask_reduce_max_epi16,
            _mm_mask_reduce_max_epi8,
            _mm_mask_reduce_max_epu16,
            _mm_mask_reduce_max_epu8,
            _mm_mask_reduce_min_epi16,
            _mm_mask_reduce_min_epi8,
            _mm_mask_reduce_min_epu16,
            _mm_mask_reduce_min_epu8,
            _mm_mask_reduce_mul_epi16,
            _mm_mask_reduce_mul_epi8,
            _mm_mask_reduce_or_epi16,
            _mm_mask_reduce_or_epi8,
            _mm_mask_set1_epi16,
            _mm_mask_set1_epi8,
            _mm_mask_shuffle_epi8,
            _mm_mask_shufflehi_epi16,
            _mm_mask_shufflelo_epi16,
            _mm_mask_sll_epi16,
            _mm_mask_slli_epi16,
            _mm_mask_sllv_epi16,
            _mm_mask_sra_epi16,
            _mm_mask_srai_epi16,
            _mm_mask_srav_epi16,
            _mm_mask_srl_epi16,
            _mm_mask_srli_epi16,
            _mm_mask_srlv_epi16,
            _mm_mask_storeu_epi16,
            _mm_mask_storeu_epi8,
            _mm_mask_sub_epi16,
            _mm_mask_sub_epi8,
            _mm_mask_subs_epi16,
            _mm_mask_subs_epi8,
            _mm_mask_subs_epu16,
            _mm_mask_subs_epu8,
            _mm_mask_test_epi16_mask,
            _mm_mask_test_epi8_mask,
            _mm_mask_testn_epi16_mask,
            _mm_mask_testn_epi8_mask,
            _mm_mask_unpackhi_epi16,
            _mm_mask_unpackhi_epi8,
            _mm_mask_unpacklo_epi16,
            _mm_mask_unpacklo_epi8,
            _mm_maskz_abs_epi16,
            _mm_maskz_abs_epi8,
            _mm_maskz_add_epi16,
            _mm_maskz_add_epi8,
            _mm_maskz_adds_epi16,
            _mm_maskz_adds_epi8,
            _mm_maskz_adds_epu16,
            _mm_maskz_adds_epu8,
            _mm_maskz_alignr_epi8,
            _mm_maskz_avg_epu16,
            _mm_maskz_avg_epu8,
            _mm_maskz_broadcastb_epi8,
            _mm_maskz_broadcastw_epi16,
            _mm_maskz_cvtepi16_epi8,
            _mm_maskz_cvtepi8_epi16,
            _mm_maskz_cvtepu8_epi16,
            _mm_maskz_cvtsepi16_epi8,
            _mm_maskz_cvtusepi16_epi8,
            _mm_maskz_dbsad_epu8,
            _mm_maskz_loadu_epi16,
            _mm_maskz_loadu_epi8,
            _mm_maskz_madd_epi16,
            _mm_maskz_maddubs_epi16,
            _mm_maskz_max_epi16,
            _mm_maskz_max_epi8,
            _mm_maskz_max_epu16,
            _mm_maskz_max_epu8,
            _mm_maskz_min_epi16,
            _mm_maskz_min_epi8,
            _mm_maskz_min_epu16,
            _mm_maskz_min_epu8,
            _mm_maskz_mov_epi16,
            _mm_maskz_mov_epi8,
            _mm_maskz_mulhi_epi16,
            _mm_maskz_mulhi_epu16,
            _mm_maskz_mulhrs_epi16,
            _mm_maskz_mullo_epi16,
            _mm_maskz_packs_epi16,
            _mm_maskz_packs_epi32,
            _mm_maskz_packus_epi16,
            _mm_maskz_packus_epi32,
            _mm_maskz_permutex2var_epi16,
            _mm_maskz_permutexvar_epi16,
            _mm_maskz_set1_epi16,
            _mm_maskz_set1_epi8,
            _mm_maskz_shuffle_epi8,
            _mm_maskz_shufflehi_epi16,
            _mm_maskz_shufflelo_epi16,
            _mm_maskz_sll_epi16,
            _mm_maskz_slli_epi16,
            _mm_maskz_sllv_epi16,
            _mm_maskz_sra_epi16,
            _mm_maskz_srai_epi16,
            _mm_maskz_srav_epi16,
            _mm_maskz_srl_epi16,
            _mm_maskz_srli_epi16,
            _mm_maskz_srlv_epi16,
            _mm_maskz_sub_epi16,
            _mm_maskz_sub_epi8,
            _mm_maskz_subs_epi16,
            _mm_maskz_subs_epi8,
            _mm_maskz_subs_epu16,
            _mm_maskz_subs_epu8,
            _mm_maskz_unpackhi_epi16,
            _mm_maskz_unpackhi_epi8,
            _mm_maskz_unpacklo_epi16,
            _mm_maskz_unpacklo_epi8,
            _mm_movepi16_mask,
            _mm_movepi8_mask,
            _mm_movm_epi16,
            _mm_movm_epi8,
            _mm_permutex2var_epi16,
            _mm_permutexvar_epi16,
            _mm_reduce_add_epi16,
            _mm_reduce_add_epi8,
            _mm_reduce_and_epi16,
            _mm_reduce_and_epi8,
            _mm_reduce_max_epi16,
            _mm_reduce_max_epi8,
            _mm_reduce_max_epu16,
            _mm_reduce_max_epu8,
            _mm_reduce_min_epi16,
            _mm_reduce_min_epi8,
            _mm_reduce_min_epu16,
            _mm_reduce_min_epu8,
            _mm_reduce_mul_epi16,
            _mm_reduce_mul_epi8,
            _mm_reduce_or_epi16,
            _mm_reduce_or_epi8,
            _mm_sllv_epi16,
            _mm_srav_epi16,
            _mm_srlv_epi16,
            _mm_storeu_epi16,
            _mm_storeu_epi8,
            _mm_test_epi16_mask,
            _mm_test_epi8_mask,
            _mm_testn_epi16_mask,
            _mm_testn_epi8_mask,
        }
    }

    /// AVX-512 Conflict Detection (CD)
    ///
    /// Intrinsics for detecting duplicate data elements within a vector to handle
    /// data dependencies during vectorization.
    pub mod avx512cd {
        import_intrinsics! {
            _mm256_broadcastmb_epi64,
            _mm256_broadcastmw_epi32,
            _mm256_conflict_epi32,
            _mm256_conflict_epi64,
            _mm256_lzcnt_epi32,
            _mm256_lzcnt_epi64,
            _mm256_mask_conflict_epi32,
            _mm256_mask_conflict_epi64,
            _mm256_mask_lzcnt_epi32,
            _mm256_mask_lzcnt_epi64,
            _mm256_maskz_conflict_epi32,
            _mm256_maskz_conflict_epi64,
            _mm256_maskz_lzcnt_epi32,
            _mm256_maskz_lzcnt_epi64,
            _mm512_broadcastmb_epi64,
            _mm512_broadcastmw_epi32,
            _mm512_conflict_epi32,
            _mm512_conflict_epi64,
            _mm512_lzcnt_epi32,
            _mm512_lzcnt_epi64,
            _mm512_mask_conflict_epi32,
            _mm512_mask_conflict_epi64,
            _mm512_mask_lzcnt_epi32,
            _mm512_mask_lzcnt_epi64,
            _mm512_maskz_conflict_epi32,
            _mm512_maskz_conflict_epi64,
            _mm512_maskz_lzcnt_epi32,
            _mm512_maskz_lzcnt_epi64,
            _mm_broadcastmb_epi64,
            _mm_broadcastmw_epi32,
            _mm_conflict_epi32,
            _mm_conflict_epi64,
            _mm_lzcnt_epi32,
            _mm_lzcnt_epi64,
            _mm_mask_conflict_epi32,
            _mm_mask_conflict_epi64,
            _mm_mask_lzcnt_epi32,
            _mm_mask_lzcnt_epi64,
            _mm_maskz_conflict_epi32,
            _mm_maskz_conflict_epi64,
            _mm_maskz_lzcnt_epi32,
            _mm_maskz_lzcnt_epi64,
        }
    }

    /// AVX-512 Doubleword and Quadword (DQ)
    ///
    /// Additional instructions for 32-bit (Doubleword) and 64-bit (Quadword) elements
    /// that are not included in the Foundation extension.
    pub mod avx512dq {
        import_intrinsics! {
            _mm256_broadcast_f32x2,
            _mm256_broadcast_f64x2,
            _mm256_broadcast_i32x2,
            _mm256_broadcast_i64x2,
            _mm256_cvtepi64_pd,
            _mm256_cvtepi64_ps,
            _mm256_cvtepu64_pd,
            _mm256_cvtepu64_ps,
            _mm256_cvtpd_epi64,
            _mm256_cvtpd_epu64,
            _mm256_cvtps_epi64,
            _mm256_cvtps_epu64,
            _mm256_cvttpd_epi64,
            _mm256_cvttpd_epu64,
            _mm256_cvttps_epi64,
            _mm256_cvttps_epu64,
            _mm256_extractf64x2_pd,
            _mm256_extracti64x2_epi64,
            _mm256_fpclass_pd_mask,
            _mm256_fpclass_ps_mask,
            _mm256_insertf64x2,
            _mm256_inserti64x2,
            _mm256_mask_and_pd,
            _mm256_mask_and_ps,
            _mm256_mask_andnot_pd,
            _mm256_mask_andnot_ps,
            _mm256_mask_broadcast_f32x2,
            _mm256_mask_broadcast_f64x2,
            _mm256_mask_broadcast_i32x2,
            _mm256_mask_broadcast_i64x2,
            _mm256_mask_cvtepi64_pd,
            _mm256_mask_cvtepi64_ps,
            _mm256_mask_cvtepu64_pd,
            _mm256_mask_cvtepu64_ps,
            _mm256_mask_cvtpd_epi64,
            _mm256_mask_cvtpd_epu64,
            _mm256_mask_cvtps_epi64,
            _mm256_mask_cvtps_epu64,
            _mm256_mask_cvttpd_epi64,
            _mm256_mask_cvttpd_epu64,
            _mm256_mask_cvttps_epi64,
            _mm256_mask_cvttps_epu64,
            _mm256_mask_extractf64x2_pd,
            _mm256_mask_extracti64x2_epi64,
            _mm256_mask_fpclass_pd_mask,
            _mm256_mask_fpclass_ps_mask,
            _mm256_mask_insertf64x2,
            _mm256_mask_inserti64x2,
            _mm256_mask_mullo_epi64,
            _mm256_mask_or_pd,
            _mm256_mask_or_ps,
            _mm256_mask_range_pd,
            _mm256_mask_range_ps,
            _mm256_mask_reduce_pd,
            _mm256_mask_reduce_ps,
            _mm256_mask_xor_pd,
            _mm256_mask_xor_ps,
            _mm256_maskz_and_pd,
            _mm256_maskz_and_ps,
            _mm256_maskz_andnot_pd,
            _mm256_maskz_andnot_ps,
            _mm256_maskz_broadcast_f32x2,
            _mm256_maskz_broadcast_f64x2,
            _mm256_maskz_broadcast_i32x2,
            _mm256_maskz_broadcast_i64x2,
            _mm256_maskz_cvtepi64_pd,
            _mm256_maskz_cvtepi64_ps,
            _mm256_maskz_cvtepu64_pd,
            _mm256_maskz_cvtepu64_ps,
            _mm256_maskz_cvtpd_epi64,
            _mm256_maskz_cvtpd_epu64,
            _mm256_maskz_cvtps_epi64,
            _mm256_maskz_cvtps_epu64,
            _mm256_maskz_cvttpd_epi64,
            _mm256_maskz_cvttpd_epu64,
            _mm256_maskz_cvttps_epi64,
            _mm256_maskz_cvttps_epu64,
            _mm256_maskz_extractf64x2_pd,
            _mm256_maskz_extracti64x2_epi64,
            _mm256_maskz_insertf64x2,
            _mm256_maskz_inserti64x2,
            _mm256_maskz_mullo_epi64,
            _mm256_maskz_or_pd,
            _mm256_maskz_or_ps,
            _mm256_maskz_range_pd,
            _mm256_maskz_range_ps,
            _mm256_maskz_reduce_pd,
            _mm256_maskz_reduce_ps,
            _mm256_maskz_xor_pd,
            _mm256_maskz_xor_ps,
            _mm256_movepi32_mask,
            _mm256_movepi64_mask,
            _mm256_movm_epi32,
            _mm256_movm_epi64,
            _mm256_mullo_epi64,
            _mm256_range_pd,
            _mm256_range_ps,
            _mm256_reduce_pd,
            _mm256_reduce_ps,
            _mm512_and_pd,
            _mm512_and_ps,
            _mm512_andnot_pd,
            _mm512_andnot_ps,
            _mm512_broadcast_f32x2,
            _mm512_broadcast_f32x8,
            _mm512_broadcast_f64x2,
            _mm512_broadcast_i32x2,
            _mm512_broadcast_i32x8,
            _mm512_broadcast_i64x2,
            _mm512_cvt_roundepi64_pd,
            _mm512_cvt_roundepi64_ps,
            _mm512_cvt_roundepu64_pd,
            _mm512_cvt_roundepu64_ps,
            _mm512_cvt_roundpd_epi64,
            _mm512_cvt_roundpd_epu64,
            _mm512_cvt_roundps_epi64,
            _mm512_cvt_roundps_epu64,
            _mm512_cvtepi64_pd,
            _mm512_cvtepi64_ps,
            _mm512_cvtepu64_pd,
            _mm512_cvtepu64_ps,
            _mm512_cvtpd_epi64,
            _mm512_cvtpd_epu64,
            _mm512_cvtps_epi64,
            _mm512_cvtps_epu64,
            _mm512_cvtt_roundpd_epi64,
            _mm512_cvtt_roundpd_epu64,
            _mm512_cvtt_roundps_epi64,
            _mm512_cvtt_roundps_epu64,
            _mm512_cvttpd_epi64,
            _mm512_cvttpd_epu64,
            _mm512_cvttps_epi64,
            _mm512_cvttps_epu64,
            _mm512_extractf32x8_ps,
            _mm512_extractf64x2_pd,
            _mm512_extracti32x8_epi32,
            _mm512_extracti64x2_epi64,
            _mm512_fpclass_pd_mask,
            _mm512_fpclass_ps_mask,
            _mm512_insertf32x8,
            _mm512_insertf64x2,
            _mm512_inserti32x8,
            _mm512_inserti64x2,
            _mm512_mask_and_pd,
            _mm512_mask_and_ps,
            _mm512_mask_andnot_pd,
            _mm512_mask_andnot_ps,
            _mm512_mask_broadcast_f32x2,
            _mm512_mask_broadcast_f32x8,
            _mm512_mask_broadcast_f64x2,
            _mm512_mask_broadcast_i32x2,
            _mm512_mask_broadcast_i32x8,
            _mm512_mask_broadcast_i64x2,
            _mm512_mask_cvt_roundepi64_pd,
            _mm512_mask_cvt_roundepi64_ps,
            _mm512_mask_cvt_roundepu64_pd,
            _mm512_mask_cvt_roundepu64_ps,
            _mm512_mask_cvt_roundpd_epi64,
            _mm512_mask_cvt_roundpd_epu64,
            _mm512_mask_cvt_roundps_epi64,
            _mm512_mask_cvt_roundps_epu64,
            _mm512_mask_cvtepi64_pd,
            _mm512_mask_cvtepi64_ps,
            _mm512_mask_cvtepu64_pd,
            _mm512_mask_cvtepu64_ps,
            _mm512_mask_cvtpd_epi64,
            _mm512_mask_cvtpd_epu64,
            _mm512_mask_cvtps_epi64,
            _mm512_mask_cvtps_epu64,
            _mm512_mask_cvtt_roundpd_epi64,
            _mm512_mask_cvtt_roundpd_epu64,
            _mm512_mask_cvtt_roundps_epi64,
            _mm512_mask_cvtt_roundps_epu64,
            _mm512_mask_cvttpd_epi64,
            _mm512_mask_cvttpd_epu64,
            _mm512_mask_cvttps_epi64,
            _mm512_mask_cvttps_epu64,
            _mm512_mask_extractf32x8_ps,
            _mm512_mask_extractf64x2_pd,
            _mm512_mask_extracti32x8_epi32,
            _mm512_mask_extracti64x2_epi64,
            _mm512_mask_fpclass_pd_mask,
            _mm512_mask_fpclass_ps_mask,
            _mm512_mask_insertf32x8,
            _mm512_mask_insertf64x2,
            _mm512_mask_inserti32x8,
            _mm512_mask_inserti64x2,
            _mm512_mask_mullo_epi64,
            _mm512_mask_or_pd,
            _mm512_mask_or_ps,
            _mm512_mask_range_pd,
            _mm512_mask_range_ps,
            _mm512_mask_range_round_pd,
            _mm512_mask_range_round_ps,
            _mm512_mask_reduce_pd,
            _mm512_mask_reduce_ps,
            _mm512_mask_reduce_round_pd,
            _mm512_mask_reduce_round_ps,
            _mm512_mask_xor_pd,
            _mm512_mask_xor_ps,
            _mm512_maskz_and_pd,
            _mm512_maskz_and_ps,
            _mm512_maskz_andnot_pd,
            _mm512_maskz_andnot_ps,
            _mm512_maskz_broadcast_f32x2,
            _mm512_maskz_broadcast_f32x8,
            _mm512_maskz_broadcast_f64x2,
            _mm512_maskz_broadcast_i32x2,
            _mm512_maskz_broadcast_i32x8,
            _mm512_maskz_broadcast_i64x2,
            _mm512_maskz_cvt_roundepi64_pd,
            _mm512_maskz_cvt_roundepi64_ps,
            _mm512_maskz_cvt_roundepu64_pd,
            _mm512_maskz_cvt_roundepu64_ps,
            _mm512_maskz_cvt_roundpd_epi64,
            _mm512_maskz_cvt_roundpd_epu64,
            _mm512_maskz_cvt_roundps_epi64,
            _mm512_maskz_cvt_roundps_epu64,
            _mm512_maskz_cvtepi64_pd,
            _mm512_maskz_cvtepi64_ps,
            _mm512_maskz_cvtepu64_pd,
            _mm512_maskz_cvtepu64_ps,
            _mm512_maskz_cvtpd_epi64,
            _mm512_maskz_cvtpd_epu64,
            _mm512_maskz_cvtps_epi64,
            _mm512_maskz_cvtps_epu64,
            _mm512_maskz_cvtt_roundpd_epi64,
            _mm512_maskz_cvtt_roundpd_epu64,
            _mm512_maskz_cvtt_roundps_epi64,
            _mm512_maskz_cvtt_roundps_epu64,
            _mm512_maskz_cvttpd_epi64,
            _mm512_maskz_cvttpd_epu64,
            _mm512_maskz_cvttps_epi64,
            _mm512_maskz_cvttps_epu64,
            _mm512_maskz_extractf32x8_ps,
            _mm512_maskz_extractf64x2_pd,
            _mm512_maskz_extracti32x8_epi32,
            _mm512_maskz_extracti64x2_epi64,
            _mm512_maskz_insertf32x8,
            _mm512_maskz_insertf64x2,
            _mm512_maskz_inserti32x8,
            _mm512_maskz_inserti64x2,
            _mm512_maskz_mullo_epi64,
            _mm512_maskz_or_pd,
            _mm512_maskz_or_ps,
            _mm512_maskz_range_pd,
            _mm512_maskz_range_ps,
            _mm512_maskz_range_round_pd,
            _mm512_maskz_range_round_ps,
            _mm512_maskz_reduce_pd,
            _mm512_maskz_reduce_ps,
            _mm512_maskz_reduce_round_pd,
            _mm512_maskz_reduce_round_ps,
            _mm512_maskz_xor_pd,
            _mm512_maskz_xor_ps,
            _mm512_movepi32_mask,
            _mm512_movepi64_mask,
            _mm512_movm_epi32,
            _mm512_movm_epi64,
            _mm512_mullo_epi64,
            _mm512_or_pd,
            _mm512_or_ps,
            _mm512_range_pd,
            _mm512_range_ps,
            _mm512_range_round_pd,
            _mm512_range_round_ps,
            _mm512_reduce_pd,
            _mm512_reduce_ps,
            _mm512_reduce_round_pd,
            _mm512_reduce_round_ps,
            _mm512_xor_pd,
            _mm512_xor_ps,
            _mm_broadcast_i32x2,
            _mm_cvtepi64_pd,
            _mm_cvtepi64_ps,
            _mm_cvtepu64_pd,
            _mm_cvtepu64_ps,
            _mm_cvtpd_epi64,
            _mm_cvtpd_epu64,
            _mm_cvtps_epi64,
            _mm_cvtps_epu64,
            _mm_cvttpd_epi64,
            _mm_cvttpd_epu64,
            _mm_cvttps_epi64,
            _mm_cvttps_epu64,
            _mm_fpclass_pd_mask,
            _mm_fpclass_ps_mask,
            _mm_fpclass_sd_mask,
            _mm_fpclass_ss_mask,
            _mm_mask_and_pd,
            _mm_mask_and_ps,
            _mm_mask_andnot_pd,
            _mm_mask_andnot_ps,
            _mm_mask_broadcast_i32x2,
            _mm_mask_cvtepi64_pd,
            _mm_mask_cvtepi64_ps,
            _mm_mask_cvtepu64_pd,
            _mm_mask_cvtepu64_ps,
            _mm_mask_cvtpd_epi64,
            _mm_mask_cvtpd_epu64,
            _mm_mask_cvtps_epi64,
            _mm_mask_cvtps_epu64,
            _mm_mask_cvttpd_epi64,
            _mm_mask_cvttpd_epu64,
            _mm_mask_cvttps_epi64,
            _mm_mask_cvttps_epu64,
            _mm_mask_fpclass_pd_mask,
            _mm_mask_fpclass_ps_mask,
            _mm_mask_fpclass_sd_mask,
            _mm_mask_fpclass_ss_mask,
            _mm_mask_mullo_epi64,
            _mm_mask_or_pd,
            _mm_mask_or_ps,
            _mm_mask_range_pd,
            _mm_mask_range_ps,
            _mm_mask_range_round_sd,
            _mm_mask_range_round_ss,
            _mm_mask_range_sd,
            _mm_mask_range_ss,
            _mm_mask_reduce_pd,
            _mm_mask_reduce_ps,
            _mm_mask_reduce_round_sd,
            _mm_mask_reduce_round_ss,
            _mm_mask_reduce_sd,
            _mm_mask_reduce_ss,
            _mm_mask_xor_pd,
            _mm_mask_xor_ps,
            _mm_maskz_and_pd,
            _mm_maskz_and_ps,
            _mm_maskz_andnot_pd,
            _mm_maskz_andnot_ps,
            _mm_maskz_broadcast_i32x2,
            _mm_maskz_cvtepi64_pd,
            _mm_maskz_cvtepi64_ps,
            _mm_maskz_cvtepu64_pd,
            _mm_maskz_cvtepu64_ps,
            _mm_maskz_cvtpd_epi64,
            _mm_maskz_cvtpd_epu64,
            _mm_maskz_cvtps_epi64,
            _mm_maskz_cvtps_epu64,
            _mm_maskz_cvttpd_epi64,
            _mm_maskz_cvttpd_epu64,
            _mm_maskz_cvttps_epi64,
            _mm_maskz_cvttps_epu64,
            _mm_maskz_mullo_epi64,
            _mm_maskz_or_pd,
            _mm_maskz_or_ps,
            _mm_maskz_range_pd,
            _mm_maskz_range_ps,
            _mm_maskz_range_round_sd,
            _mm_maskz_range_round_ss,
            _mm_maskz_range_sd,
            _mm_maskz_range_ss,
            _mm_maskz_reduce_pd,
            _mm_maskz_reduce_ps,
            _mm_maskz_reduce_round_sd,
            _mm_maskz_reduce_round_ss,
            _mm_maskz_reduce_sd,
            _mm_maskz_reduce_ss,
            _mm_maskz_xor_pd,
            _mm_maskz_xor_ps,
            _mm_movepi32_mask,
            _mm_movepi64_mask,
            _mm_movm_epi32,
            _mm_movm_epi64,
            _mm_mullo_epi64,
            _mm_range_pd,
            _mm_range_ps,
            _mm_range_round_sd,
            _mm_range_round_ss,
            _mm_reduce_pd,
            _mm_reduce_ps,
            _mm_reduce_round_sd,
            _mm_reduce_round_ss,
            _mm_reduce_sd,
            _mm_reduce_ss,
        }
    }

    #[cfg(false)] // Experimental even on stable
    pub mod avx512fp16 {
        import_intrinsics! { __m128h, __m256h, __m128h }

        import_intrinsics! {
            _mm256_abs_ph,
            _mm256_add_ph,
            _mm256_castpd_ph,
            _mm256_castph128_ph256,
            _mm256_castph256_ph128,
            _mm256_castph_pd,
            _mm256_castph_ps,
            _mm256_castph_si256,
            _mm256_castps_ph,
            _mm256_castsi256_ph,
            _mm256_cmp_ph_mask,
            _mm256_cmul_pch,
            _mm256_conj_pch,
            _mm256_cvtepi16_ph,
            _mm256_cvtepi32_ph,
            _mm256_cvtepi64_ph,
            _mm256_cvtepu16_ph,
            _mm256_cvtepu32_ph,
            _mm256_cvtepu64_ph,
            _mm256_cvtpd_ph,
            _mm256_cvtph_epi16,
            _mm256_cvtph_epi32,
            _mm256_cvtph_epi64,
            _mm256_cvtph_epu16,
            _mm256_cvtph_epu32,
            _mm256_cvtph_epu64,
            _mm256_cvtph_pd,
            // _mm256_cvtsh_hExperimental,
            _mm256_cvttph_epi16,
            _mm256_cvttph_epi32,
            _mm256_cvttph_epi64,
            _mm256_cvttph_epu16,
            _mm256_cvttph_epu32,
            _mm256_cvttph_epu64,
            _mm256_cvtxph_ps,
            _mm256_cvtxps_ph,
            _mm256_div_ph,
            _mm256_fcmadd_pch,
            _mm256_fcmul_pch,
            _mm256_fmadd_pch,
            _mm256_fmadd_ph,
            _mm256_fmaddsub_ph,
            _mm256_fmsub_ph,
            _mm256_fmsubadd_ph,
            _mm256_fmul_pch,
            _mm256_fnmadd_ph,
            _mm256_fnmsub_ph,
            _mm256_fpclass_ph_mask,
            _mm256_getexp_ph,
            _mm256_getmant_ph,
            // _mm256_load_phExperimental,
            // _mm256_loadu_phExperimental,
            _mm256_mask3_fcmadd_pch,
            _mm256_mask3_fmadd_pch,
            _mm256_mask3_fmadd_ph,
            _mm256_mask3_fmaddsub_ph,
            _mm256_mask3_fmsub_ph,
            _mm256_mask3_fmsubadd_ph,
            _mm256_mask3_fnmadd_ph,
            _mm256_mask3_fnmsub_ph,
            _mm256_mask_add_ph,
            _mm256_mask_blend_ph,
            _mm256_mask_cmp_ph_mask,
            _mm256_mask_cmul_pch,
            _mm256_mask_conj_pch,
            _mm256_mask_cvtepi16_ph,
            _mm256_mask_cvtepi32_ph,
            _mm256_mask_cvtepi64_ph,
            _mm256_mask_cvtepu16_ph,
            _mm256_mask_cvtepu32_ph,
            _mm256_mask_cvtepu64_ph,
            _mm256_mask_cvtpd_ph,
            _mm256_mask_cvtph_epi16,
            _mm256_mask_cvtph_epi32,
            _mm256_mask_cvtph_epi64,
            _mm256_mask_cvtph_epu16,
            _mm256_mask_cvtph_epu32,
            _mm256_mask_cvtph_epu64,
            _mm256_mask_cvtph_pd,
            _mm256_mask_cvttph_epi16,
            _mm256_mask_cvttph_epi32,
            _mm256_mask_cvttph_epi64,
            _mm256_mask_cvttph_epu16,
            _mm256_mask_cvttph_epu32,
            _mm256_mask_cvttph_epu64,
            _mm256_mask_cvtxph_ps,
            _mm256_mask_cvtxps_ph,
            _mm256_mask_div_ph,
            _mm256_mask_fcmadd_pch,
            _mm256_mask_fcmul_pch,
            _mm256_mask_fmadd_pch,
            _mm256_mask_fmadd_ph,
            _mm256_mask_fmaddsub_ph,
            _mm256_mask_fmsub_ph,
            _mm256_mask_fmsubadd_ph,
            _mm256_mask_fmul_pch,
            _mm256_mask_fnmadd_ph,
            _mm256_mask_fnmsub_ph,
            _mm256_mask_fpclass_ph_mask,
            _mm256_mask_getexp_ph,
            _mm256_mask_getmant_ph,
            _mm256_mask_max_ph,
            _mm256_mask_min_ph,
            _mm256_mask_mul_pch,
            _mm256_mask_mul_ph,
            _mm256_mask_rcp_ph,
            _mm256_mask_reduce_ph,
            _mm256_mask_roundscale_ph,
            _mm256_mask_rsqrt_ph,
            _mm256_mask_scalef_ph,
            _mm256_mask_sqrt_ph,
            _mm256_mask_sub_ph,
            _mm256_maskz_add_ph,
            _mm256_maskz_cmul_pch,
            _mm256_maskz_conj_pch,
            _mm256_maskz_cvtepi16_ph,
            _mm256_maskz_cvtepi32_ph,
            _mm256_maskz_cvtepi64_ph,
            _mm256_maskz_cvtepu16_ph,
            _mm256_maskz_cvtepu32_ph,
            _mm256_maskz_cvtepu64_ph,
            _mm256_maskz_cvtpd_ph,
            _mm256_maskz_cvtph_epi16,
            _mm256_maskz_cvtph_epi32,
            _mm256_maskz_cvtph_epi64,
            _mm256_maskz_cvtph_epu16,
            _mm256_maskz_cvtph_epu32,
            _mm256_maskz_cvtph_epu64,
            _mm256_maskz_cvtph_pd,
            _mm256_maskz_cvttph_epi16,
            _mm256_maskz_cvttph_epi32,
            _mm256_maskz_cvttph_epi64,
            _mm256_maskz_cvttph_epu16,
            _mm256_maskz_cvttph_epu32,
            _mm256_maskz_cvttph_epu64,
            _mm256_maskz_cvtxph_ps,
            _mm256_maskz_cvtxps_ph,
            _mm256_maskz_div_ph,
            _mm256_maskz_fcmadd_pch,
            _mm256_maskz_fcmul_pch,
            _mm256_maskz_fmadd_pch,
            _mm256_maskz_fmadd_ph,
            _mm256_maskz_fmaddsub_ph,
            _mm256_maskz_fmsub_ph,
            _mm256_maskz_fmsubadd_ph,
            _mm256_maskz_fmul_pch,
            _mm256_maskz_fnmadd_ph,
            _mm256_maskz_fnmsub_ph,
            _mm256_maskz_getexp_ph,
            _mm256_maskz_getmant_ph,
            _mm256_maskz_max_ph,
            _mm256_maskz_min_ph,
            _mm256_maskz_mul_pch,
            _mm256_maskz_mul_ph,
            _mm256_maskz_rcp_ph,
            _mm256_maskz_reduce_ph,
            _mm256_maskz_roundscale_ph,
            _mm256_maskz_rsqrt_ph,
            _mm256_maskz_scalef_ph,
            _mm256_maskz_sqrt_ph,
            _mm256_maskz_sub_ph,
            _mm256_max_ph,
            _mm256_min_ph,
            _mm256_mul_pch,
            _mm256_mul_ph,
            _mm256_permutex2var_ph,
            _mm256_permutexvar_ph,
            _mm256_rcp_ph,
            // _mm256_reduce_add_phExperimental,
            // _mm256_reduce_max_phExperimental,
            // _mm256_reduce_min_phExperimental,
            // _mm256_reduce_mul_phExperimental,
            _mm256_reduce_ph,
            _mm256_roundscale_ph,
            _mm256_rsqrt_ph,
            _mm256_scalef_ph,
            // _mm256_set1_phExperimental,
            // _mm256_set_phExperimental,
            // _mm256_setr_phExperimental,
            _mm256_setzero_ph,
            _mm256_sqrt_ph,
            // _mm256_store_phExperimental,
            // _mm256_storeu_phExperimental,
            _mm256_sub_ph,
            _mm256_undefined_ph,
            _mm256_zextph128_ph256,
            _mm512_abs_ph,
            _mm512_add_ph,
            _mm512_add_round_ph,
            _mm512_castpd_ph,
            _mm512_castph128_ph512,
            _mm512_castph256_ph512,
            _mm512_castph512_ph128,
            _mm512_castph512_ph256,
            _mm512_castph_pd,
            _mm512_castph_ps,
            _mm512_castph_si512,
            _mm512_castps_ph,
            _mm512_castsi512_ph,
            _mm512_cmp_ph_mask,
            _mm512_cmp_round_ph_mask,
            _mm512_cmul_pch,
            _mm512_cmul_round_pch,
            _mm512_conj_pch,
            _mm512_cvt_roundepi16_ph,
            _mm512_cvt_roundepi32_ph,
            _mm512_cvt_roundepi64_ph,
            _mm512_cvt_roundepu16_ph,
            _mm512_cvt_roundepu32_ph,
            _mm512_cvt_roundepu64_ph,
            _mm512_cvt_roundpd_ph,
            _mm512_cvt_roundph_epi16,
            _mm512_cvt_roundph_epi32,
            _mm512_cvt_roundph_epi64,
            _mm512_cvt_roundph_epu16,
            _mm512_cvt_roundph_epu32,
            _mm512_cvt_roundph_epu64,
            _mm512_cvt_roundph_pd,
            _mm512_cvtepi16_ph,
            _mm512_cvtepi32_ph,
            _mm512_cvtepi64_ph,
            _mm512_cvtepu16_ph,
            _mm512_cvtepu32_ph,
            _mm512_cvtepu64_ph,
            _mm512_cvtpd_ph,
            _mm512_cvtph_epi16,
            _mm512_cvtph_epi32,
            _mm512_cvtph_epi64,
            _mm512_cvtph_epu16,
            _mm512_cvtph_epu32,
            _mm512_cvtph_epu64,
            _mm512_cvtph_pd,
            // _mm512_cvtsh_hExperimental,
            _mm512_cvtt_roundph_epi16,
            _mm512_cvtt_roundph_epi32,
            _mm512_cvtt_roundph_epi64,
            _mm512_cvtt_roundph_epu16,
            _mm512_cvtt_roundph_epu32,
            _mm512_cvtt_roundph_epu64,
            _mm512_cvttph_epi16,
            _mm512_cvttph_epi32,
            _mm512_cvttph_epi64,
            _mm512_cvttph_epu16,
            _mm512_cvttph_epu32,
            _mm512_cvttph_epu64,
            _mm512_cvtx_roundph_ps,
            _mm512_cvtx_roundps_ph,
            _mm512_cvtxph_ps,
            _mm512_cvtxps_ph,
            _mm512_div_ph,
            _mm512_div_round_ph,
            _mm512_fcmadd_pch,
            _mm512_fcmadd_round_pch,
            _mm512_fcmul_pch,
            _mm512_fcmul_round_pch,
            _mm512_fmadd_pch,
            _mm512_fmadd_ph,
            _mm512_fmadd_round_pch,
            _mm512_fmadd_round_ph,
            _mm512_fmaddsub_ph,
            _mm512_fmaddsub_round_ph,
            _mm512_fmsub_ph,
            _mm512_fmsub_round_ph,
            _mm512_fmsubadd_ph,
            _mm512_fmsubadd_round_ph,
            _mm512_fmul_pch,
            _mm512_fmul_round_pch,
            _mm512_fnmadd_ph,
            _mm512_fnmadd_round_ph,
            _mm512_fnmsub_ph,
            _mm512_fnmsub_round_ph,
            _mm512_fpclass_ph_mask,
            _mm512_getexp_ph,
            _mm512_getexp_round_ph,
            _mm512_getmant_ph,
            _mm512_getmant_round_ph,
            // _mm512_load_phExperimental,
            // _mm512_loadu_phExperimental,
            _mm512_mask3_fcmadd_pch,
            _mm512_mask3_fcmadd_round_pch,
            _mm512_mask3_fmadd_pch,
            _mm512_mask3_fmadd_ph,
            _mm512_mask3_fmadd_round_pch,
            _mm512_mask3_fmadd_round_ph,
            _mm512_mask3_fmaddsub_ph,
            _mm512_mask3_fmaddsub_round_ph,
            _mm512_mask3_fmsub_ph,
            _mm512_mask3_fmsub_round_ph,
            _mm512_mask3_fmsubadd_ph,
            _mm512_mask3_fmsubadd_round_ph,
            _mm512_mask3_fnmadd_ph,
            _mm512_mask3_fnmadd_round_ph,
            _mm512_mask3_fnmsub_ph,
            _mm512_mask3_fnmsub_round_ph,
            _mm512_mask_add_ph,
            _mm512_mask_add_round_ph,
            _mm512_mask_blend_ph,
            _mm512_mask_cmp_ph_mask,
            _mm512_mask_cmp_round_ph_mask,
            _mm512_mask_cmul_pch,
            _mm512_mask_cmul_round_pch,
            _mm512_mask_conj_pch,
            _mm512_mask_cvt_roundepi16_ph,
            _mm512_mask_cvt_roundepi32_ph,
            _mm512_mask_cvt_roundepi64_ph,
            _mm512_mask_cvt_roundepu16_ph,
            _mm512_mask_cvt_roundepu32_ph,
            _mm512_mask_cvt_roundepu64_ph,
            _mm512_mask_cvt_roundpd_ph,
            _mm512_mask_cvt_roundph_epi16,
            _mm512_mask_cvt_roundph_epi32,
            _mm512_mask_cvt_roundph_epi64,
            _mm512_mask_cvt_roundph_epu16,
            _mm512_mask_cvt_roundph_epu32,
            _mm512_mask_cvt_roundph_epu64,
            _mm512_mask_cvt_roundph_pd,
            _mm512_mask_cvtepi16_ph,
            _mm512_mask_cvtepi32_ph,
            _mm512_mask_cvtepi64_ph,
            _mm512_mask_cvtepu16_ph,
            _mm512_mask_cvtepu32_ph,
            _mm512_mask_cvtepu64_ph,
            _mm512_mask_cvtpd_ph,
            _mm512_mask_cvtph_epi16,
            _mm512_mask_cvtph_epi32,
            _mm512_mask_cvtph_epi64,
            _mm512_mask_cvtph_epu16,
            _mm512_mask_cvtph_epu32,
            _mm512_mask_cvtph_epu64,
            _mm512_mask_cvtph_pd,
            _mm512_mask_cvtt_roundph_epi16,
            _mm512_mask_cvtt_roundph_epi32,
            _mm512_mask_cvtt_roundph_epi64,
            _mm512_mask_cvtt_roundph_epu16,
            _mm512_mask_cvtt_roundph_epu32,
            _mm512_mask_cvtt_roundph_epu64,
            _mm512_mask_cvttph_epi16,
            _mm512_mask_cvttph_epi32,
            _mm512_mask_cvttph_epi64,
            _mm512_mask_cvttph_epu16,
            _mm512_mask_cvttph_epu32,
            _mm512_mask_cvttph_epu64,
            _mm512_mask_cvtx_roundph_ps,
            _mm512_mask_cvtx_roundps_ph,
            _mm512_mask_cvtxph_ps,
            _mm512_mask_cvtxps_ph,
            _mm512_mask_div_ph,
            _mm512_mask_div_round_ph,
            _mm512_mask_fcmadd_pch,
            _mm512_mask_fcmadd_round_pch,
            _mm512_mask_fcmul_pch,
            _mm512_mask_fcmul_round_pch,
            _mm512_mask_fmadd_pch,
            _mm512_mask_fmadd_ph,
            _mm512_mask_fmadd_round_pch,
            _mm512_mask_fmadd_round_ph,
            _mm512_mask_fmaddsub_ph,
            _mm512_mask_fmaddsub_round_ph,
            _mm512_mask_fmsub_ph,
            _mm512_mask_fmsub_round_ph,
            _mm512_mask_fmsubadd_ph,
            _mm512_mask_fmsubadd_round_ph,
            _mm512_mask_fmul_pch,
            _mm512_mask_fmul_round_pch,
            _mm512_mask_fnmadd_ph,
            _mm512_mask_fnmadd_round_ph,
            _mm512_mask_fnmsub_ph,
            _mm512_mask_fnmsub_round_ph,
            _mm512_mask_fpclass_ph_mask,
            _mm512_mask_getexp_ph,
            _mm512_mask_getexp_round_ph,
            _mm512_mask_getmant_ph,
            _mm512_mask_getmant_round_ph,
            _mm512_mask_max_ph,
            _mm512_mask_max_round_ph,
            _mm512_mask_min_ph,
            _mm512_mask_min_round_ph,
            _mm512_mask_mul_pch,
            _mm512_mask_mul_ph,
            _mm512_mask_mul_round_pch,
            _mm512_mask_mul_round_ph,
            _mm512_mask_rcp_ph,
            _mm512_mask_reduce_ph,
            _mm512_mask_reduce_round_ph,
            _mm512_mask_roundscale_ph,
            _mm512_mask_roundscale_round_ph,
            _mm512_mask_rsqrt_ph,
            _mm512_mask_scalef_ph,
            _mm512_mask_scalef_round_ph,
            _mm512_mask_sqrt_ph,
            _mm512_mask_sqrt_round_ph,
            _mm512_mask_sub_ph,
            _mm512_mask_sub_round_ph,
            _mm512_maskz_add_ph,
            _mm512_maskz_add_round_ph,
            _mm512_maskz_cmul_pch,
            _mm512_maskz_cmul_round_pch,
            _mm512_maskz_conj_pch,
            _mm512_maskz_cvt_roundepi16_ph,
            _mm512_maskz_cvt_roundepi32_ph,
            _mm512_maskz_cvt_roundepi64_ph,
            _mm512_maskz_cvt_roundepu16_ph,
            _mm512_maskz_cvt_roundepu32_ph,
            _mm512_maskz_cvt_roundepu64_ph,
            _mm512_maskz_cvt_roundpd_ph,
            _mm512_maskz_cvt_roundph_epi16,
            _mm512_maskz_cvt_roundph_epi32,
            _mm512_maskz_cvt_roundph_epi64,
            _mm512_maskz_cvt_roundph_epu16,
            _mm512_maskz_cvt_roundph_epu32,
            _mm512_maskz_cvt_roundph_epu64,
            _mm512_maskz_cvt_roundph_pd,
            _mm512_maskz_cvtepi16_ph,
            _mm512_maskz_cvtepi32_ph,
            _mm512_maskz_cvtepi64_ph,
            _mm512_maskz_cvtepu16_ph,
            _mm512_maskz_cvtepu32_ph,
            _mm512_maskz_cvtepu64_ph,
            _mm512_maskz_cvtpd_ph,
            _mm512_maskz_cvtph_epi16,
            _mm512_maskz_cvtph_epi32,
            _mm512_maskz_cvtph_epi64,
            _mm512_maskz_cvtph_epu16,
            _mm512_maskz_cvtph_epu32,
            _mm512_maskz_cvtph_epu64,
            _mm512_maskz_cvtph_pd,
            _mm512_maskz_cvtt_roundph_epi16,
            _mm512_maskz_cvtt_roundph_epi32,
            _mm512_maskz_cvtt_roundph_epi64,
            _mm512_maskz_cvtt_roundph_epu16,
            _mm512_maskz_cvtt_roundph_epu32,
            _mm512_maskz_cvtt_roundph_epu64,
            _mm512_maskz_cvttph_epi16,
            _mm512_maskz_cvttph_epi32,
            _mm512_maskz_cvttph_epi64,
            _mm512_maskz_cvttph_epu16,
            _mm512_maskz_cvttph_epu32,
            _mm512_maskz_cvttph_epu64,
            _mm512_maskz_cvtx_roundph_ps,
            _mm512_maskz_cvtx_roundps_ph,
            _mm512_maskz_cvtxph_ps,
            _mm512_maskz_cvtxps_ph,
            _mm512_maskz_div_ph,
            _mm512_maskz_div_round_ph,
            _mm512_maskz_fcmadd_pch,
            _mm512_maskz_fcmadd_round_pch,
            _mm512_maskz_fcmul_pch,
            _mm512_maskz_fcmul_round_pch,
            _mm512_maskz_fmadd_pch,
            _mm512_maskz_fmadd_ph,
            _mm512_maskz_fmadd_round_pch,
            _mm512_maskz_fmadd_round_ph,
            _mm512_maskz_fmaddsub_ph,
            _mm512_maskz_fmaddsub_round_ph,
            _mm512_maskz_fmsub_ph,
            _mm512_maskz_fmsub_round_ph,
            _mm512_maskz_fmsubadd_ph,
            _mm512_maskz_fmsubadd_round_ph,
            _mm512_maskz_fmul_pch,
            _mm512_maskz_fmul_round_pch,
            _mm512_maskz_fnmadd_ph,
            _mm512_maskz_fnmadd_round_ph,
            _mm512_maskz_fnmsub_ph,
            _mm512_maskz_fnmsub_round_ph,
            _mm512_maskz_getexp_ph,
            _mm512_maskz_getexp_round_ph,
            _mm512_maskz_getmant_ph,
            _mm512_maskz_getmant_round_ph,
            _mm512_maskz_max_ph,
            _mm512_maskz_max_round_ph,
            _mm512_maskz_min_ph,
            _mm512_maskz_min_round_ph,
            _mm512_maskz_mul_pch,
            _mm512_maskz_mul_ph,
            _mm512_maskz_mul_round_pch,
            _mm512_maskz_mul_round_ph,
            _mm512_maskz_rcp_ph,
            _mm512_maskz_reduce_ph,
            _mm512_maskz_reduce_round_ph,
            _mm512_maskz_roundscale_ph,
            _mm512_maskz_roundscale_round_ph,
            _mm512_maskz_rsqrt_ph,
            _mm512_maskz_scalef_ph,
            _mm512_maskz_scalef_round_ph,
            _mm512_maskz_sqrt_ph,
            _mm512_maskz_sqrt_round_ph,
            _mm512_maskz_sub_ph,
            _mm512_maskz_sub_round_ph,
            _mm512_max_ph,
            _mm512_max_round_ph,
            _mm512_min_ph,
            _mm512_min_round_ph,
            _mm512_mul_pch,
            _mm512_mul_ph,
            _mm512_mul_round_pch,
            _mm512_mul_round_ph,
            _mm512_permutex2var_ph,
            _mm512_permutexvar_ph,
            _mm512_rcp_ph,
            // _mm512_reduce_add_phExperimental,
            // _mm512_reduce_max_phExperimental,
            // _mm512_reduce_min_phExperimental,
            // _mm512_reduce_mul_phExperimental,
            _mm512_reduce_ph,
            _mm512_reduce_round_ph,
            _mm512_roundscale_ph,
            _mm512_roundscale_round_ph,
            _mm512_rsqrt_ph,
            _mm512_scalef_ph,
            _mm512_scalef_round_ph,
            // _mm512_set1_phExperimental,
            // _mm512_set_phExperimental,
            // _mm512_setr_phExperimental,
            _mm512_setzero_ph,
            _mm512_sqrt_ph,
            _mm512_sqrt_round_ph,
            // _mm512_store_phExperimental,
            // _mm512_storeu_phExperimental,
            _mm512_sub_ph,
            _mm512_sub_round_ph,
            _mm512_undefined_ph,
            _mm512_zextph128_ph512,
            _mm512_zextph256_ph512,
            _mm_abs_ph,
            _mm_add_ph,
            _mm_add_round_sh,
            _mm_add_sh,
            _mm_castpd_ph,
            _mm_castph_pd,
            _mm_castph_ps,
            _mm_castph_si128,
            _mm_castps_ph,
            _mm_castsi128_ph,
            _mm_cmp_ph_mask,
            _mm_cmp_round_sh_mask,
            _mm_cmp_sh_mask,
            _mm_cmul_pch,
            _mm_cmul_round_sch,
            _mm_cmul_sch,
            _mm_comi_round_sh,
            _mm_comi_sh,
            _mm_comieq_sh,
            _mm_comige_sh,
            _mm_comigt_sh,
            _mm_comile_sh,
            _mm_comilt_sh,
            _mm_comineq_sh,
            _mm_conj_pch,
            _mm_cvt_roundi32_sh,
            _mm_cvt_roundi64_sh,
            _mm_cvt_roundsd_sh,
            _mm_cvt_roundsh_i32,
            _mm_cvt_roundsh_i64,
            _mm_cvt_roundsh_sd,
            _mm_cvt_roundsh_ss,
            _mm_cvt_roundsh_u32,
            _mm_cvt_roundsh_u64,
            _mm_cvt_roundss_sh,
            _mm_cvt_roundu32_sh,
            _mm_cvt_roundu64_sh,
            _mm_cvtepi16_ph,
            _mm_cvtepi32_ph,
            _mm_cvtepi64_ph,
            _mm_cvtepu16_ph,
            _mm_cvtepu32_ph,
            _mm_cvtepu64_ph,
            _mm_cvti32_sh,
            _mm_cvti64_sh,
            _mm_cvtpd_ph,
            _mm_cvtph_epi16,
            _mm_cvtph_epi32,
            _mm_cvtph_epi64,
            _mm_cvtph_epu16,
            _mm_cvtph_epu32,
            _mm_cvtph_epu64,
            _mm_cvtph_pd,
            _mm_cvtsd_sh,
            // _mm_cvtsh_hExperimental,
            _mm_cvtsh_i32,
            _mm_cvtsh_i64,
            _mm_cvtsh_sd,
            _mm_cvtsh_ss,
            _mm_cvtsh_u32,
            _mm_cvtsh_u64,
            _mm_cvtsi128_si16,
            _mm_cvtsi16_si128,
            _mm_cvtss_sh,
            _mm_cvtt_roundsh_i32,
            _mm_cvtt_roundsh_i64,
            _mm_cvtt_roundsh_u32,
            _mm_cvtt_roundsh_u64,
            _mm_cvttph_epi16,
            _mm_cvttph_epi32,
            _mm_cvttph_epi64,
            _mm_cvttph_epu16,
            _mm_cvttph_epu32,
            _mm_cvttph_epu64,
            _mm_cvttsh_i32,
            _mm_cvttsh_i64,
            _mm_cvttsh_u32,
            _mm_cvttsh_u64,
            _mm_cvtu32_sh,
            _mm_cvtu64_sh,
            _mm_cvtxph_ps,
            _mm_cvtxps_ph,
            _mm_div_ph,
            _mm_div_round_sh,
            _mm_div_sh,
            _mm_fcmadd_pch,
            _mm_fcmadd_round_sch,
            _mm_fcmadd_sch,
            _mm_fcmul_pch,
            _mm_fcmul_round_sch,
            _mm_fcmul_sch,
            _mm_fmadd_pch,
            _mm_fmadd_ph,
            _mm_fmadd_round_sch,
            _mm_fmadd_round_sh,
            _mm_fmadd_sch,
            _mm_fmadd_sh,
            _mm_fmaddsub_ph,
            _mm_fmsub_ph,
            _mm_fmsub_round_sh,
            _mm_fmsub_sh,
            _mm_fmsubadd_ph,
            _mm_fmul_pch,
            _mm_fmul_round_sch,
            _mm_fmul_sch,
            _mm_fnmadd_ph,
            _mm_fnmadd_round_sh,
            _mm_fnmadd_sh,
            _mm_fnmsub_ph,
            _mm_fnmsub_round_sh,
            _mm_fnmsub_sh,
            _mm_fpclass_ph_mask,
            _mm_fpclass_sh_mask,
            _mm_getexp_ph,
            _mm_getexp_round_sh,
            _mm_getexp_sh,
            _mm_getmant_ph,
            _mm_getmant_round_sh,
            _mm_getmant_sh,
            // _mm_load_phExperimental,
            // _mm_load_shExperimental,
            // _mm_loadu_phExperimental,
            _mm_mask3_fcmadd_pch,
            _mm_mask3_fcmadd_round_sch,
            _mm_mask3_fcmadd_sch,
            _mm_mask3_fmadd_pch,
            _mm_mask3_fmadd_ph,
            _mm_mask3_fmadd_round_sch,
            _mm_mask3_fmadd_round_sh,
            _mm_mask3_fmadd_sch,
            _mm_mask3_fmadd_sh,
            _mm_mask3_fmaddsub_ph,
            _mm_mask3_fmsub_ph,
            _mm_mask3_fmsub_round_sh,
            _mm_mask3_fmsub_sh,
            _mm_mask3_fmsubadd_ph,
            _mm_mask3_fnmadd_ph,
            _mm_mask3_fnmadd_round_sh,
            _mm_mask3_fnmadd_sh,
            _mm_mask3_fnmsub_ph,
            _mm_mask3_fnmsub_round_sh,
            _mm_mask3_fnmsub_sh,
            _mm_mask_add_ph,
            _mm_mask_add_round_sh,
            _mm_mask_add_sh,
            _mm_mask_blend_ph,
            _mm_mask_cmp_ph_mask,
            _mm_mask_cmp_round_sh_mask,
            _mm_mask_cmp_sh_mask,
            _mm_mask_cmul_pch,
            _mm_mask_cmul_round_sch,
            _mm_mask_cmul_sch,
            _mm_mask_conj_pch,
            _mm_mask_cvt_roundsd_sh,
            _mm_mask_cvt_roundsh_sd,
            _mm_mask_cvt_roundsh_ss,
            _mm_mask_cvt_roundss_sh,
            _mm_mask_cvtepi16_ph,
            _mm_mask_cvtepi32_ph,
            _mm_mask_cvtepi64_ph,
            _mm_mask_cvtepu16_ph,
            _mm_mask_cvtepu32_ph,
            _mm_mask_cvtepu64_ph,
            _mm_mask_cvtpd_ph,
            _mm_mask_cvtph_epi16,
            _mm_mask_cvtph_epi32,
            _mm_mask_cvtph_epi64,
            _mm_mask_cvtph_epu16,
            _mm_mask_cvtph_epu32,
            _mm_mask_cvtph_epu64,
            _mm_mask_cvtph_pd,
            _mm_mask_cvtsd_sh,
            _mm_mask_cvtsh_sd,
            _mm_mask_cvtsh_ss,
            _mm_mask_cvtss_sh,
            _mm_mask_cvttph_epi16,
            _mm_mask_cvttph_epi32,
            _mm_mask_cvttph_epi64,
            _mm_mask_cvttph_epu16,
            _mm_mask_cvttph_epu32,
            _mm_mask_cvttph_epu64,
            _mm_mask_cvtxph_ps,
            _mm_mask_cvtxps_ph,
            _mm_mask_div_ph,
            _mm_mask_div_round_sh,
            _mm_mask_div_sh,
            _mm_mask_fcmadd_pch,
            _mm_mask_fcmadd_round_sch,
            _mm_mask_fcmadd_sch,
            _mm_mask_fcmul_pch,
            _mm_mask_fcmul_round_sch,
            _mm_mask_fcmul_sch,
            _mm_mask_fmadd_pch,
            _mm_mask_fmadd_ph,
            _mm_mask_fmadd_round_sch,
            _mm_mask_fmadd_round_sh,
            _mm_mask_fmadd_sch,
            _mm_mask_fmadd_sh,
            _mm_mask_fmaddsub_ph,
            _mm_mask_fmsub_ph,
            _mm_mask_fmsub_round_sh,
            _mm_mask_fmsub_sh,
            _mm_mask_fmsubadd_ph,
            _mm_mask_fmul_pch,
            _mm_mask_fmul_round_sch,
            _mm_mask_fmul_sch,
            _mm_mask_fnmadd_ph,
            _mm_mask_fnmadd_round_sh,
            _mm_mask_fnmadd_sh,
            _mm_mask_fnmsub_ph,
            _mm_mask_fnmsub_round_sh,
            _mm_mask_fnmsub_sh,
            _mm_mask_fpclass_ph_mask,
            _mm_mask_fpclass_sh_mask,
            _mm_mask_getexp_ph,
            _mm_mask_getexp_round_sh,
            _mm_mask_getexp_sh,
            _mm_mask_getmant_ph,
            _mm_mask_getmant_round_sh,
            _mm_mask_getmant_sh,
            // _mm_mask_load_shExperimental,
            _mm_mask_max_ph,
            _mm_mask_max_round_sh,
            _mm_mask_max_sh,
            _mm_mask_min_ph,
            _mm_mask_min_round_sh,
            _mm_mask_min_sh,
            _mm_mask_move_sh,
            _mm_mask_mul_pch,
            _mm_mask_mul_ph,
            _mm_mask_mul_round_sch,
            _mm_mask_mul_round_sh,
            _mm_mask_mul_sch,
            _mm_mask_mul_sh,
            _mm_mask_rcp_ph,
            _mm_mask_rcp_sh,
            _mm_mask_reduce_ph,
            _mm_mask_reduce_round_sh,
            _mm_mask_reduce_sh,
            _mm_mask_roundscale_ph,
            _mm_mask_roundscale_round_sh,
            _mm_mask_roundscale_sh,
            _mm_mask_rsqrt_ph,
            _mm_mask_rsqrt_sh,
            _mm_mask_scalef_ph,
            _mm_mask_scalef_round_sh,
            _mm_mask_scalef_sh,
            _mm_mask_sqrt_ph,
            _mm_mask_sqrt_round_sh,
            _mm_mask_sqrt_sh,
            // _mm_mask_store_shExperimental,
            _mm_mask_sub_ph,
            _mm_mask_sub_round_sh,
            _mm_mask_sub_sh,
            _mm_maskz_add_ph,
            _mm_maskz_add_round_sh,
            _mm_maskz_add_sh,
            _mm_maskz_cmul_pch,
            _mm_maskz_cmul_round_sch,
            _mm_maskz_cmul_sch,
            _mm_maskz_conj_pch,
            _mm_maskz_cvt_roundsd_sh,
            _mm_maskz_cvt_roundsh_sd,
            _mm_maskz_cvt_roundsh_ss,
            _mm_maskz_cvt_roundss_sh,
            _mm_maskz_cvtepi16_ph,
            _mm_maskz_cvtepi32_ph,
            _mm_maskz_cvtepi64_ph,
            _mm_maskz_cvtepu16_ph,
            _mm_maskz_cvtepu32_ph,
            _mm_maskz_cvtepu64_ph,
            _mm_maskz_cvtpd_ph,
            _mm_maskz_cvtph_epi16,
            _mm_maskz_cvtph_epi32,
            _mm_maskz_cvtph_epi64,
            _mm_maskz_cvtph_epu16,
            _mm_maskz_cvtph_epu32,
            _mm_maskz_cvtph_epu64,
            _mm_maskz_cvtph_pd,
            _mm_maskz_cvtsd_sh,
            _mm_maskz_cvtsh_sd,
            _mm_maskz_cvtsh_ss,
            _mm_maskz_cvtss_sh,
            _mm_maskz_cvttph_epi16,
            _mm_maskz_cvttph_epi32,
            _mm_maskz_cvttph_epi64,
            _mm_maskz_cvttph_epu16,
            _mm_maskz_cvttph_epu32,
            _mm_maskz_cvttph_epu64,
            _mm_maskz_cvtxph_ps,
            _mm_maskz_cvtxps_ph,
            _mm_maskz_div_ph,
            _mm_maskz_div_round_sh,
            _mm_maskz_div_sh,
            _mm_maskz_fcmadd_pch,
            _mm_maskz_fcmadd_round_sch,
            _mm_maskz_fcmadd_sch,
            _mm_maskz_fcmul_pch,
            _mm_maskz_fcmul_round_sch,
            _mm_maskz_fcmul_sch,
            _mm_maskz_fmadd_pch,
            _mm_maskz_fmadd_ph,
            _mm_maskz_fmadd_round_sch,
            _mm_maskz_fmadd_round_sh,
            _mm_maskz_fmadd_sch,
            _mm_maskz_fmadd_sh,
            _mm_maskz_fmaddsub_ph,
            _mm_maskz_fmsub_ph,
            _mm_maskz_fmsub_round_sh,
            _mm_maskz_fmsub_sh,
            _mm_maskz_fmsubadd_ph,
            _mm_maskz_fmul_pch,
            _mm_maskz_fmul_round_sch,
            _mm_maskz_fmul_sch,
            _mm_maskz_fnmadd_ph,
            _mm_maskz_fnmadd_round_sh,
            _mm_maskz_fnmadd_sh,
            _mm_maskz_fnmsub_ph,
            _mm_maskz_fnmsub_round_sh,
            _mm_maskz_fnmsub_sh,
            _mm_maskz_getexp_ph,
            _mm_maskz_getexp_round_sh,
            _mm_maskz_getexp_sh,
            _mm_maskz_getmant_ph,
            _mm_maskz_getmant_round_sh,
            _mm_maskz_getmant_sh,
            // _mm_maskz_load_shExperimental,
            _mm_maskz_max_ph,
            _mm_maskz_max_round_sh,
            _mm_maskz_max_sh,
            _mm_maskz_min_ph,
            _mm_maskz_min_round_sh,
            _mm_maskz_min_sh,
            _mm_maskz_move_sh,
            _mm_maskz_mul_pch,
            _mm_maskz_mul_ph,
            _mm_maskz_mul_round_sch,
            _mm_maskz_mul_round_sh,
            _mm_maskz_mul_sch,
            _mm_maskz_mul_sh,
            _mm_maskz_rcp_ph,
            _mm_maskz_rcp_sh,
            _mm_maskz_reduce_ph,
            _mm_maskz_reduce_round_sh,
            _mm_maskz_reduce_sh,
            _mm_maskz_roundscale_ph,
            _mm_maskz_roundscale_round_sh,
            _mm_maskz_roundscale_sh,
            _mm_maskz_rsqrt_ph,
            _mm_maskz_rsqrt_sh,
            _mm_maskz_scalef_ph,
            _mm_maskz_scalef_round_sh,
            _mm_maskz_scalef_sh,
            _mm_maskz_sqrt_ph,
            _mm_maskz_sqrt_round_sh,
            _mm_maskz_sqrt_sh,
            _mm_maskz_sub_ph,
            _mm_maskz_sub_round_sh,
            _mm_maskz_sub_sh,
            _mm_max_ph,
            _mm_max_round_sh,
            _mm_max_sh,
            _mm_min_ph,
            _mm_min_round_sh,
            _mm_min_sh,
            _mm_move_sh,
            _mm_mul_pch,
            _mm_mul_ph,
            _mm_mul_round_sch,
            _mm_mul_round_sh,
            _mm_mul_sch,
            _mm_mul_sh,
            _mm_permutex2var_ph,
            _mm_permutexvar_ph,
            _mm_rcp_ph,
            _mm_rcp_sh,
            // _mm_reduce_add_phExperimental,
            // _mm_reduce_max_phExperimental,
            // _mm_reduce_min_phExperimental,
            // _mm_reduce_mul_phExperimental,
            _mm_reduce_ph,
            _mm_reduce_round_sh,
            _mm_reduce_sh,
            _mm_roundscale_ph,
            _mm_roundscale_round_sh,
            _mm_roundscale_sh,
            _mm_rsqrt_ph,
            _mm_rsqrt_sh,
            _mm_scalef_ph,
            _mm_scalef_round_sh,
            _mm_scalef_sh,
            // _mm_set1_phExperimental,
            // _mm_set_phExperimental,
            // _mm_set_shExperimental,
            // _mm_setr_phExperimental,
            _mm_setzero_ph,
            _mm_sqrt_ph,
            _mm_sqrt_round_sh,
            _mm_sqrt_sh,
            // _mm_store_phExperimental,
            // _mm_store_shExperimental,
            // _mm_storeu_phExperimental,
            _mm_sub_ph,
            _mm_sub_round_sh,
            _mm_sub_sh,
            _mm_ucomieq_sh,
            _mm_ucomige_sh,
            _mm_ucomigt_sh,
            _mm_ucomile_sh,
            _mm_ucomilt_sh,
            _mm_ucomineq_sh,
            _mm_undefined_ph,
        }
    }

    /// AVX-512 Integer Fused Multiply-Add (IFMA)
    ///
    /// Specialized arithmetic for high-precision integer operations, commonly used in
    /// public-key cryptography (e.g., RSA).
    pub mod avx512ifma {
        import_intrinsics! {
            _mm256_madd52hi_epu64,
            _mm256_madd52lo_epu64,
            _mm256_mask_madd52hi_epu64,
            _mm256_mask_madd52lo_epu64,
            _mm256_maskz_madd52hi_epu64,
            _mm256_maskz_madd52lo_epu64,
            _mm512_madd52hi_epu64,
            _mm512_madd52lo_epu64,
            _mm512_mask_madd52hi_epu64,
            _mm512_mask_madd52lo_epu64,
            _mm512_maskz_madd52hi_epu64,
            _mm512_maskz_madd52lo_epu64,
            _mm_madd52hi_epu64,
            _mm_madd52lo_epu64,
            _mm_mask_madd52hi_epu64,
            _mm_mask_madd52lo_epu64,
            _mm_maskz_madd52hi_epu64,
            _mm_maskz_madd52lo_epu64,
        }
    }

    /// AVX-512 Vector Byte Manipulation Instructions (VBMI)
    ///
    /// Advanced byte-level permutation capabilities.
    pub mod avx512vbmi {
        import_intrinsics! {
            _mm256_mask2_permutex2var_epi8,
            _mm256_mask_multishift_epi64_epi8,
            _mm256_mask_permutex2var_epi8,
            _mm256_mask_permutexvar_epi8,
            _mm256_maskz_multishift_epi64_epi8,
            _mm256_maskz_permutex2var_epi8,
            _mm256_maskz_permutexvar_epi8,
            _mm256_multishift_epi64_epi8,
            _mm256_permutex2var_epi8,
            _mm256_permutexvar_epi8,
            _mm512_mask2_permutex2var_epi8,
            _mm512_mask_multishift_epi64_epi8,
            _mm512_mask_permutex2var_epi8,
            _mm512_mask_permutexvar_epi8,
            _mm512_maskz_multishift_epi64_epi8,
            _mm512_maskz_permutex2var_epi8,
            _mm512_maskz_permutexvar_epi8,
            _mm512_multishift_epi64_epi8,
            _mm512_permutex2var_epi8,
            _mm512_permutexvar_epi8,
            _mm_mask2_permutex2var_epi8,
            _mm_mask_multishift_epi64_epi8,
            _mm_mask_permutex2var_epi8,
            _mm_mask_permutexvar_epi8,
            _mm_maskz_multishift_epi64_epi8,
            _mm_maskz_permutex2var_epi8,
            _mm_maskz_permutexvar_epi8,
            _mm_multishift_epi64_epi8,
            _mm_permutex2var_epi8,
            _mm_permutexvar_epi8,
        }
    }

    /// AVX-512 Vector Byte Manipulation Instructions 2 (VBMI2)
    ///
    /// Extensions for data compression and expansion within registers.
    pub mod avx512vbmi2 {
        import_intrinsics! {
            _mm256_mask_compress_epi16,
            _mm256_mask_compress_epi8,
            _mm256_mask_compressstoreu_epi16,
            _mm256_mask_compressstoreu_epi8,
            _mm256_mask_expand_epi16,
            _mm256_mask_expand_epi8,
            _mm256_mask_expandloadu_epi16,
            _mm256_mask_expandloadu_epi8,
            _mm256_mask_shldi_epi16,
            _mm256_mask_shldi_epi32,
            _mm256_mask_shldi_epi64,
            _mm256_mask_shldv_epi16,
            _mm256_mask_shldv_epi32,
            _mm256_mask_shldv_epi64,
            _mm256_mask_shrdi_epi16,
            _mm256_mask_shrdi_epi32,
            _mm256_mask_shrdi_epi64,
            _mm256_mask_shrdv_epi16,
            _mm256_mask_shrdv_epi32,
            _mm256_mask_shrdv_epi64,
            _mm256_maskz_compress_epi16,
            _mm256_maskz_compress_epi8,
            _mm256_maskz_expand_epi16,
            _mm256_maskz_expand_epi8,
            _mm256_maskz_expandloadu_epi16,
            _mm256_maskz_expandloadu_epi8,
            _mm256_maskz_shldi_epi16,
            _mm256_maskz_shldi_epi32,
            _mm256_maskz_shldi_epi64,
            _mm256_maskz_shldv_epi16,
            _mm256_maskz_shldv_epi32,
            _mm256_maskz_shldv_epi64,
            _mm256_maskz_shrdi_epi16,
            _mm256_maskz_shrdi_epi32,
            _mm256_maskz_shrdi_epi64,
            _mm256_maskz_shrdv_epi16,
            _mm256_maskz_shrdv_epi32,
            _mm256_maskz_shrdv_epi64,
            _mm256_shldi_epi16,
            _mm256_shldi_epi32,
            _mm256_shldi_epi64,
            _mm256_shldv_epi16,
            _mm256_shldv_epi32,
            _mm256_shldv_epi64,
            _mm256_shrdi_epi16,
            _mm256_shrdi_epi32,
            _mm256_shrdi_epi64,
            _mm256_shrdv_epi16,
            _mm256_shrdv_epi32,
            _mm256_shrdv_epi64,
            _mm512_mask_compress_epi16,
            _mm512_mask_compress_epi8,
            _mm512_mask_compressstoreu_epi16,
            _mm512_mask_compressstoreu_epi8,
            _mm512_mask_expand_epi16,
            _mm512_mask_expand_epi8,
            _mm512_mask_expandloadu_epi16,
            _mm512_mask_expandloadu_epi8,
            _mm512_mask_shldi_epi16,
            _mm512_mask_shldi_epi32,
            _mm512_mask_shldi_epi64,
            _mm512_mask_shldv_epi16,
            _mm512_mask_shldv_epi32,
            _mm512_mask_shldv_epi64,
            _mm512_mask_shrdi_epi16,
            _mm512_mask_shrdi_epi32,
            _mm512_mask_shrdi_epi64,
            _mm512_mask_shrdv_epi16,
            _mm512_mask_shrdv_epi32,
            _mm512_mask_shrdv_epi64,
            _mm512_maskz_compress_epi16,
            _mm512_maskz_compress_epi8,
            _mm512_maskz_expand_epi16,
            _mm512_maskz_expand_epi8,
            _mm512_maskz_expandloadu_epi16,
            _mm512_maskz_expandloadu_epi8,
            _mm512_maskz_shldi_epi16,
            _mm512_maskz_shldi_epi32,
            _mm512_maskz_shldi_epi64,
            _mm512_maskz_shldv_epi16,
            _mm512_maskz_shldv_epi32,
            _mm512_maskz_shldv_epi64,
            _mm512_maskz_shrdi_epi16,
            _mm512_maskz_shrdi_epi32,
            _mm512_maskz_shrdi_epi64,
            _mm512_maskz_shrdv_epi16,
            _mm512_maskz_shrdv_epi32,
            _mm512_maskz_shrdv_epi64,
            _mm512_shldi_epi16,
            _mm512_shldi_epi32,
            _mm512_shldi_epi64,
            _mm512_shldv_epi16,
            _mm512_shldv_epi32,
            _mm512_shldv_epi64,
            _mm512_shrdi_epi16,
            _mm512_shrdi_epi32,
            _mm512_shrdi_epi64,
            _mm512_shrdv_epi16,
            _mm512_shrdv_epi32,
            _mm512_shrdv_epi64,
            _mm_mask_compress_epi16,
            _mm_mask_compress_epi8,
            _mm_mask_compressstoreu_epi16,
            _mm_mask_compressstoreu_epi8,
            _mm_mask_expand_epi16,
            _mm_mask_expand_epi8,
            _mm_mask_expandloadu_epi16,
            _mm_mask_expandloadu_epi8,
            _mm_mask_shldi_epi16,
            _mm_mask_shldi_epi32,
            _mm_mask_shldi_epi64,
            _mm_mask_shldv_epi16,
            _mm_mask_shldv_epi32,
            _mm_mask_shldv_epi64,
            _mm_mask_shrdi_epi16,
            _mm_mask_shrdi_epi32,
            _mm_mask_shrdi_epi64,
            _mm_mask_shrdv_epi16,
            _mm_mask_shrdv_epi32,
            _mm_mask_shrdv_epi64,
            _mm_maskz_compress_epi16,
            _mm_maskz_compress_epi8,
            _mm_maskz_expand_epi16,
            _mm_maskz_expand_epi8,
            _mm_maskz_expandloadu_epi16,
            _mm_maskz_expandloadu_epi8,
            _mm_maskz_shldi_epi16,
            _mm_maskz_shldi_epi32,
            _mm_maskz_shldi_epi64,
            _mm_maskz_shldv_epi16,
            _mm_maskz_shldv_epi32,
            _mm_maskz_shldv_epi64,
            _mm_maskz_shrdi_epi16,
            _mm_maskz_shrdi_epi32,
            _mm_maskz_shrdi_epi64,
            _mm_maskz_shrdv_epi16,
            _mm_maskz_shrdv_epi32,
            _mm_maskz_shrdv_epi64,
            _mm_shldi_epi16,
            _mm_shldi_epi32,
            _mm_shldi_epi64,
            _mm_shldv_epi16,
            _mm_shldv_epi32,
            _mm_shldv_epi64,
            _mm_shrdi_epi16,
            _mm_shrdi_epi32,
            _mm_shrdi_epi64,
            _mm_shrdv_epi16,
            _mm_shrdv_epi32,
            _mm_shrdv_epi64,
        }
    }

    /// AVX-512 Vector Neural Network Instructions (VNNI)
    ///
    /// Instructions designed to accelerate convolutional neural network inference
    /// using lower-precision arithmetic.
    pub mod avx512vnni {
        import_intrinsics! {
            _mm256_dpbusd_epi32,
            _mm256_dpbusds_epi32,
            _mm256_dpwssd_epi32,
            _mm256_dpwssds_epi32,
            _mm256_mask_dpbusd_epi32,
            _mm256_mask_dpbusds_epi32,
            _mm256_mask_dpwssd_epi32,
            _mm256_mask_dpwssds_epi32,
            _mm256_maskz_dpbusd_epi32,
            _mm256_maskz_dpbusds_epi32,
            _mm256_maskz_dpwssd_epi32,
            _mm256_maskz_dpwssds_epi32,
            _mm512_dpbusd_epi32,
            _mm512_dpbusds_epi32,
            _mm512_dpwssd_epi32,
            _mm512_dpwssds_epi32,
            _mm512_mask_dpbusd_epi32,
            _mm512_mask_dpbusds_epi32,
            _mm512_mask_dpwssd_epi32,
            _mm512_mask_dpwssds_epi32,
            _mm512_maskz_dpbusd_epi32,
            _mm512_maskz_dpbusds_epi32,
            _mm512_maskz_dpwssd_epi32,
            _mm512_maskz_dpwssds_epi32,
            _mm_dpbusd_epi32,
            _mm_dpbusds_epi32,
            _mm_dpwssd_epi32,
            _mm_dpwssds_epi32,
            _mm_mask_dpbusd_epi32,
            _mm_mask_dpbusds_epi32,
            _mm_mask_dpwssd_epi32,
            _mm_mask_dpwssds_epi32,
            _mm_maskz_dpbusd_epi32,
            _mm_maskz_dpbusds_epi32,
            _mm_maskz_dpwssd_epi32,
            _mm_maskz_dpwssds_epi32,
        }
    }

    /// AVX-512 Vector Population Count (VPOPCNTDQ)
    ///
    /// Dedicated instructions for calculating the Hamming weight (population count)
    /// of 32-bit and 64-bit integers.
    pub mod avx512vpopcntdq {
        import_intrinsics! {
            _mm256_mask_popcnt_epi32,
            _mm256_mask_popcnt_epi64,
            _mm256_maskz_popcnt_epi32,
            _mm256_maskz_popcnt_epi64,
            _mm256_popcnt_epi32,
            _mm256_popcnt_epi64,
            _mm512_mask_popcnt_epi32,
            _mm512_mask_popcnt_epi64,
            _mm512_maskz_popcnt_epi32,
            _mm512_maskz_popcnt_epi64,
            _mm512_popcnt_epi32,
            _mm512_popcnt_epi64,
            _mm_mask_popcnt_epi32,
            _mm_mask_popcnt_epi64,
            _mm_maskz_popcnt_epi32,
            _mm_maskz_popcnt_epi64,
            _mm_popcnt_epi32,
            _mm_popcnt_epi64,
        }
    }

    import_intrinsics! {
        _mm256_abs_epi64,
        _mm256_alignr_epi32,
        _mm256_alignr_epi64,
        _mm256_broadcast_f32x4,
        _mm256_broadcast_i32x4,
        _mm256_cmp_epi32_mask,
        _mm256_cmp_epi64_mask,
        _mm256_cmp_epu32_mask,
        _mm256_cmp_epu64_mask,
        _mm256_cmp_pd_mask,
        _mm256_cmp_ps_mask,
        _mm256_cmpeq_epi32_mask,
        _mm256_cmpeq_epi64_mask,
        _mm256_cmpeq_epu32_mask,
        _mm256_cmpeq_epu64_mask,
        _mm256_cmpge_epi32_mask,
        _mm256_cmpge_epi64_mask,
        _mm256_cmpge_epu32_mask,
        _mm256_cmpge_epu64_mask,
        _mm256_cmpgt_epi32_mask,
        _mm256_cmpgt_epi64_mask,
        _mm256_cmpgt_epu32_mask,
        _mm256_cmpgt_epu64_mask,
        _mm256_cmple_epi32_mask,
        _mm256_cmple_epi64_mask,
        _mm256_cmple_epu32_mask,
        _mm256_cmple_epu64_mask,
        _mm256_cmplt_epi32_mask,
        _mm256_cmplt_epi64_mask,
        _mm256_cmplt_epu32_mask,
        _mm256_cmplt_epu64_mask,
        _mm256_cmpneq_epi32_mask,
        _mm256_cmpneq_epi64_mask,
        _mm256_cmpneq_epu32_mask,
        _mm256_cmpneq_epu64_mask,
        _mm256_cvtepi32_epi16,
        _mm256_cvtepi32_epi8,
        _mm256_cvtepi64_epi16,
        _mm256_cvtepi64_epi32,
        _mm256_cvtepi64_epi8,
        _mm256_cvtepu32_pd,
        _mm256_cvtpd_epu32,
        _mm256_cvtps_epu32,
        _mm256_cvtsepi32_epi16,
        _mm256_cvtsepi32_epi8,
        _mm256_cvtsepi64_epi16,
        _mm256_cvtsepi64_epi32,
        _mm256_cvtsepi64_epi8,
        _mm256_cvttpd_epu32,
        _mm256_cvttps_epu32,
        _mm256_cvtusepi32_epi16,
        _mm256_cvtusepi32_epi8,
        _mm256_cvtusepi64_epi16,
        _mm256_cvtusepi64_epi32,
        _mm256_cvtusepi64_epi8,
        _mm256_extractf32x4_ps,
        _mm256_extracti32x4_epi32,
        _mm256_fixupimm_pd,
        _mm256_fixupimm_ps,
        _mm256_getexp_pd,
        _mm256_getexp_ps,
        _mm256_getmant_pd,
        _mm256_getmant_ps,
        _mm256_i32scatter_epi32,
        _mm256_i32scatter_epi64,
        _mm256_i32scatter_pd,
        _mm256_i32scatter_ps,
        _mm256_i64scatter_epi32,
        _mm256_i64scatter_epi64,
        _mm256_i64scatter_pd,
        _mm256_i64scatter_ps,
        _mm256_insertf32x4,
        _mm256_inserti32x4,
        _mm256_load_epi32,
        _mm256_load_epi64,
        _mm256_loadu_epi32,
        _mm256_loadu_epi64,
        _mm256_mask2_permutex2var_epi32,
        _mm256_mask2_permutex2var_epi64,
        _mm256_mask2_permutex2var_pd,
        _mm256_mask2_permutex2var_ps,
        _mm256_mask3_fmadd_pd,
        _mm256_mask3_fmadd_ps,
        _mm256_mask3_fmaddsub_pd,
        _mm256_mask3_fmaddsub_ps,
        _mm256_mask3_fmsub_pd,
        _mm256_mask3_fmsub_ps,
        _mm256_mask3_fmsubadd_pd,
        _mm256_mask3_fmsubadd_ps,
        _mm256_mask3_fnmadd_pd,
        _mm256_mask3_fnmadd_ps,
        _mm256_mask3_fnmsub_pd,
        _mm256_mask3_fnmsub_ps,
        _mm256_mask_abs_epi32,
        _mm256_mask_abs_epi64,
        _mm256_mask_add_epi32,
        _mm256_mask_add_epi64,
        _mm256_mask_add_pd,
        _mm256_mask_add_ps,
        _mm256_mask_alignr_epi32,
        _mm256_mask_alignr_epi64,
        _mm256_mask_and_epi32,
        _mm256_mask_and_epi64,
        _mm256_mask_andnot_epi32,
        _mm256_mask_andnot_epi64,
        _mm256_mask_blend_epi32,
        _mm256_mask_blend_epi64,
        _mm256_mask_blend_pd,
        _mm256_mask_blend_ps,
        _mm256_mask_broadcast_f32x4,
        _mm256_mask_broadcast_i32x4,
        _mm256_mask_broadcastd_epi32,
        _mm256_mask_broadcastq_epi64,
        _mm256_mask_broadcastsd_pd,
        _mm256_mask_broadcastss_ps,
        _mm256_mask_cmp_epi32_mask,
        _mm256_mask_cmp_epi64_mask,
        _mm256_mask_cmp_epu32_mask,
        _mm256_mask_cmp_epu64_mask,
        _mm256_mask_cmp_pd_mask,
        _mm256_mask_cmp_ps_mask,
        _mm256_mask_cmpeq_epi32_mask,
        _mm256_mask_cmpeq_epi64_mask,
        _mm256_mask_cmpeq_epu32_mask,
        _mm256_mask_cmpeq_epu64_mask,
        _mm256_mask_cmpge_epi32_mask,
        _mm256_mask_cmpge_epi64_mask,
        _mm256_mask_cmpge_epu32_mask,
        _mm256_mask_cmpge_epu64_mask,
        _mm256_mask_cmpgt_epi32_mask,
        _mm256_mask_cmpgt_epi64_mask,
        _mm256_mask_cmpgt_epu32_mask,
        _mm256_mask_cmpgt_epu64_mask,
        _mm256_mask_cmple_epi32_mask,
        _mm256_mask_cmple_epi64_mask,
        _mm256_mask_cmple_epu32_mask,
        _mm256_mask_cmple_epu64_mask,
        _mm256_mask_cmplt_epi32_mask,
        _mm256_mask_cmplt_epi64_mask,
        _mm256_mask_cmplt_epu32_mask,
        _mm256_mask_cmplt_epu64_mask,
        _mm256_mask_cmpneq_epi32_mask,
        _mm256_mask_cmpneq_epi64_mask,
        _mm256_mask_cmpneq_epu32_mask,
        _mm256_mask_cmpneq_epu64_mask,
        _mm256_mask_compress_epi32,
        _mm256_mask_compress_epi64,
        _mm256_mask_compress_pd,
        _mm256_mask_compress_ps,
        _mm256_mask_compressstoreu_epi32,
        _mm256_mask_compressstoreu_epi64,
        _mm256_mask_compressstoreu_pd,
        _mm256_mask_compressstoreu_ps,
        _mm256_mask_cvt_roundps_ph,
        _mm256_mask_cvtepi16_epi32,
        _mm256_mask_cvtepi16_epi64,
        _mm256_mask_cvtepi32_epi16,
        _mm256_mask_cvtepi32_epi64,
        _mm256_mask_cvtepi32_epi8,
        _mm256_mask_cvtepi32_pd,
        _mm256_mask_cvtepi32_ps,
        _mm256_mask_cvtepi32_storeu_epi16,
        _mm256_mask_cvtepi32_storeu_epi8,
        _mm256_mask_cvtepi64_epi16,
        _mm256_mask_cvtepi64_epi32,
        _mm256_mask_cvtepi64_epi8,
        _mm256_mask_cvtepi64_storeu_epi16,
        _mm256_mask_cvtepi64_storeu_epi32,
        _mm256_mask_cvtepi64_storeu_epi8,
        _mm256_mask_cvtepi8_epi32,
        _mm256_mask_cvtepi8_epi64,
        _mm256_mask_cvtepu16_epi32,
        _mm256_mask_cvtepu16_epi64,
        _mm256_mask_cvtepu32_epi64,
        _mm256_mask_cvtepu32_pd,
        _mm256_mask_cvtepu8_epi32,
        _mm256_mask_cvtepu8_epi64,
        _mm256_mask_cvtpd_epi32,
        _mm256_mask_cvtpd_epu32,
        _mm256_mask_cvtpd_ps,
        _mm256_mask_cvtph_ps,
        _mm256_mask_cvtps_epi32,
        _mm256_mask_cvtps_epu32,
        _mm256_mask_cvtps_ph,
        _mm256_mask_cvtsepi32_epi16,
        _mm256_mask_cvtsepi32_epi8,
        _mm256_mask_cvtsepi32_storeu_epi16,
        _mm256_mask_cvtsepi32_storeu_epi8,
        _mm256_mask_cvtsepi64_epi16,
        _mm256_mask_cvtsepi64_epi32,
        _mm256_mask_cvtsepi64_epi8,
        _mm256_mask_cvtsepi64_storeu_epi16,
        _mm256_mask_cvtsepi64_storeu_epi32,
        _mm256_mask_cvtsepi64_storeu_epi8,
        _mm256_mask_cvttpd_epi32,
        _mm256_mask_cvttpd_epu32,
        _mm256_mask_cvttps_epi32,
        _mm256_mask_cvttps_epu32,
        _mm256_mask_cvtusepi32_epi16,
        _mm256_mask_cvtusepi32_epi8,
        _mm256_mask_cvtusepi32_storeu_epi16,
        _mm256_mask_cvtusepi32_storeu_epi8,
        _mm256_mask_cvtusepi64_epi16,
        _mm256_mask_cvtusepi64_epi32,
        _mm256_mask_cvtusepi64_epi8,
        _mm256_mask_cvtusepi64_storeu_epi16,
        _mm256_mask_cvtusepi64_storeu_epi32,
        _mm256_mask_cvtusepi64_storeu_epi8,
        _mm256_mask_div_pd,
        _mm256_mask_div_ps,
        _mm256_mask_expand_epi32,
        _mm256_mask_expand_epi64,
        _mm256_mask_expand_pd,
        _mm256_mask_expand_ps,
        _mm256_mask_expandloadu_epi32,
        _mm256_mask_expandloadu_epi64,
        _mm256_mask_expandloadu_pd,
        _mm256_mask_expandloadu_ps,
        _mm256_mask_extractf32x4_ps,
        _mm256_mask_extracti32x4_epi32,
        _mm256_mask_fixupimm_pd,
        _mm256_mask_fixupimm_ps,
        _mm256_mask_fmadd_pd,
        _mm256_mask_fmadd_ps,
        _mm256_mask_fmaddsub_pd,
        _mm256_mask_fmaddsub_ps,
        _mm256_mask_fmsub_pd,
        _mm256_mask_fmsub_ps,
        _mm256_mask_fmsubadd_pd,
        _mm256_mask_fmsubadd_ps,
        _mm256_mask_fnmadd_pd,
        _mm256_mask_fnmadd_ps,
        _mm256_mask_fnmsub_pd,
        _mm256_mask_fnmsub_ps,
        _mm256_mask_getexp_pd,
        _mm256_mask_getexp_ps,
        _mm256_mask_getmant_pd,
        _mm256_mask_getmant_ps,
        _mm256_mask_i32scatter_epi32,
        _mm256_mask_i32scatter_epi64,
        _mm256_mask_i32scatter_pd,
        _mm256_mask_i32scatter_ps,
        _mm256_mask_i64scatter_epi32,
        _mm256_mask_i64scatter_epi64,
        _mm256_mask_i64scatter_pd,
        _mm256_mask_i64scatter_ps,
        _mm256_mask_insertf32x4,
        _mm256_mask_inserti32x4,
        _mm256_mask_load_epi32,
        _mm256_mask_load_epi64,
        _mm256_mask_load_pd,
        _mm256_mask_load_ps,
        _mm256_mask_loadu_epi32,
        _mm256_mask_loadu_epi64,
        _mm256_mask_loadu_pd,
        _mm256_mask_loadu_ps,
        _mm256_mask_max_epi32,
        _mm256_mask_max_epi64,
        _mm256_mask_max_epu32,
        _mm256_mask_max_epu64,
        _mm256_mask_max_pd,
        _mm256_mask_max_ps,
        _mm256_mask_min_epi32,
        _mm256_mask_min_epi64,
        _mm256_mask_min_epu32,
        _mm256_mask_min_epu64,
        _mm256_mask_min_pd,
        _mm256_mask_min_ps,
        _mm256_mask_mov_epi32,
        _mm256_mask_mov_epi64,
        _mm256_mask_mov_pd,
        _mm256_mask_mov_ps,
        _mm256_mask_movedup_pd,
        _mm256_mask_movehdup_ps,
        _mm256_mask_moveldup_ps,
        _mm256_mask_mul_epi32,
        _mm256_mask_mul_epu32,
        _mm256_mask_mul_pd,
        _mm256_mask_mul_ps,
        _mm256_mask_mullo_epi32,
        _mm256_mask_or_epi32,
        _mm256_mask_or_epi64,
        _mm256_mask_permute_pd,
        _mm256_mask_permute_ps,
        _mm256_mask_permutevar_pd,
        _mm256_mask_permutevar_ps,
        _mm256_mask_permutex2var_epi32,
        _mm256_mask_permutex2var_epi64,
        _mm256_mask_permutex2var_pd,
        _mm256_mask_permutex2var_ps,
        _mm256_mask_permutex_epi64,
        _mm256_mask_permutex_pd,
        _mm256_mask_permutexvar_epi32,
        _mm256_mask_permutexvar_epi64,
        _mm256_mask_permutexvar_pd,
        _mm256_mask_permutexvar_ps,
        _mm256_mask_rcp14_pd,
        _mm256_mask_rcp14_ps,
        _mm256_mask_rol_epi32,
        _mm256_mask_rol_epi64,
        _mm256_mask_rolv_epi32,
        _mm256_mask_rolv_epi64,
        _mm256_mask_ror_epi32,
        _mm256_mask_ror_epi64,
        _mm256_mask_rorv_epi32,
        _mm256_mask_rorv_epi64,
        _mm256_mask_roundscale_pd,
        _mm256_mask_roundscale_ps,
        _mm256_mask_rsqrt14_pd,
        _mm256_mask_rsqrt14_ps,
        _mm256_mask_scalef_pd,
        _mm256_mask_scalef_ps,
        _mm256_mask_set1_epi32,
        _mm256_mask_set1_epi64,
        _mm256_mask_shuffle_epi32,
        _mm256_mask_shuffle_f32x4,
        _mm256_mask_shuffle_f64x2,
        _mm256_mask_shuffle_i32x4,
        _mm256_mask_shuffle_i64x2,
        _mm256_mask_shuffle_pd,
        _mm256_mask_shuffle_ps,
        _mm256_mask_sll_epi32,
        _mm256_mask_sll_epi64,
        _mm256_mask_slli_epi32,
        _mm256_mask_slli_epi64,
        _mm256_mask_sllv_epi32,
        _mm256_mask_sllv_epi64,
        _mm256_mask_sqrt_pd,
        _mm256_mask_sqrt_ps,
        _mm256_mask_sra_epi32,
        _mm256_mask_sra_epi64,
        _mm256_mask_srai_epi32,
        _mm256_mask_srai_epi64,
        _mm256_mask_srav_epi32,
        _mm256_mask_srav_epi64,
        _mm256_mask_srl_epi32,
        _mm256_mask_srl_epi64,
        _mm256_mask_srli_epi32,
        _mm256_mask_srli_epi64,
        _mm256_mask_srlv_epi32,
        _mm256_mask_srlv_epi64,
        _mm256_mask_store_epi32,
        _mm256_mask_store_epi64,
        _mm256_mask_store_pd,
        _mm256_mask_store_ps,
        _mm256_mask_storeu_epi32,
        _mm256_mask_storeu_epi64,
        _mm256_mask_storeu_pd,
        _mm256_mask_storeu_ps,
        _mm256_mask_sub_epi32,
        _mm256_mask_sub_epi64,
        _mm256_mask_sub_pd,
        _mm256_mask_sub_ps,
        _mm256_mask_ternarylogic_epi32,
        _mm256_mask_ternarylogic_epi64,
        _mm256_mask_test_epi32_mask,
        _mm256_mask_test_epi64_mask,
        _mm256_mask_testn_epi32_mask,
        _mm256_mask_testn_epi64_mask,
        _mm256_mask_unpackhi_epi32,
        _mm256_mask_unpackhi_epi64,
        _mm256_mask_unpackhi_pd,
        _mm256_mask_unpackhi_ps,
        _mm256_mask_unpacklo_epi32,
        _mm256_mask_unpacklo_epi64,
        _mm256_mask_unpacklo_pd,
        _mm256_mask_unpacklo_ps,
        _mm256_mask_xor_epi32,
        _mm256_mask_xor_epi64,
        _mm256_maskz_abs_epi32,
        _mm256_maskz_abs_epi64,
        _mm256_maskz_add_epi32,
        _mm256_maskz_add_epi64,
        _mm256_maskz_add_pd,
        _mm256_maskz_add_ps,
        _mm256_maskz_alignr_epi32,
        _mm256_maskz_alignr_epi64,
        _mm256_maskz_and_epi32,
        _mm256_maskz_and_epi64,
        _mm256_maskz_andnot_epi32,
        _mm256_maskz_andnot_epi64,
        _mm256_maskz_broadcast_f32x4,
        _mm256_maskz_broadcast_i32x4,
        _mm256_maskz_broadcastd_epi32,
        _mm256_maskz_broadcastq_epi64,
        _mm256_maskz_broadcastsd_pd,
        _mm256_maskz_broadcastss_ps,
        _mm256_maskz_compress_epi32,
        _mm256_maskz_compress_epi64,
        _mm256_maskz_compress_pd,
        _mm256_maskz_compress_ps,
        _mm256_maskz_cvt_roundps_ph,
        _mm256_maskz_cvtepi16_epi32,
        _mm256_maskz_cvtepi16_epi64,
        _mm256_maskz_cvtepi32_epi16,
        _mm256_maskz_cvtepi32_epi64,
        _mm256_maskz_cvtepi32_epi8,
        _mm256_maskz_cvtepi32_pd,
        _mm256_maskz_cvtepi32_ps,
        _mm256_maskz_cvtepi64_epi16,
        _mm256_maskz_cvtepi64_epi32,
        _mm256_maskz_cvtepi64_epi8,
        _mm256_maskz_cvtepi8_epi32,
        _mm256_maskz_cvtepi8_epi64,
        _mm256_maskz_cvtepu16_epi32,
        _mm256_maskz_cvtepu16_epi64,
        _mm256_maskz_cvtepu32_epi64,
        _mm256_maskz_cvtepu32_pd,
        _mm256_maskz_cvtepu8_epi32,
        _mm256_maskz_cvtepu8_epi64,
        _mm256_maskz_cvtpd_epi32,
        _mm256_maskz_cvtpd_epu32,
        _mm256_maskz_cvtpd_ps,
        _mm256_maskz_cvtph_ps,
        _mm256_maskz_cvtps_epi32,
        _mm256_maskz_cvtps_epu32,
        _mm256_maskz_cvtps_ph,
        _mm256_maskz_cvtsepi32_epi16,
        _mm256_maskz_cvtsepi32_epi8,
        _mm256_maskz_cvtsepi64_epi16,
        _mm256_maskz_cvtsepi64_epi32,
        _mm256_maskz_cvtsepi64_epi8,
        _mm256_maskz_cvttpd_epi32,
        _mm256_maskz_cvttpd_epu32,
        _mm256_maskz_cvttps_epi32,
        _mm256_maskz_cvttps_epu32,
        _mm256_maskz_cvtusepi32_epi16,
        _mm256_maskz_cvtusepi32_epi8,
        _mm256_maskz_cvtusepi64_epi16,
        _mm256_maskz_cvtusepi64_epi32,
        _mm256_maskz_cvtusepi64_epi8,
        _mm256_maskz_div_pd,
        _mm256_maskz_div_ps,
        _mm256_maskz_expand_epi32,
        _mm256_maskz_expand_epi64,
        _mm256_maskz_expand_pd,
        _mm256_maskz_expand_ps,
        _mm256_maskz_expandloadu_epi32,
        _mm256_maskz_expandloadu_epi64,
        _mm256_maskz_expandloadu_pd,
        _mm256_maskz_expandloadu_ps,
        _mm256_maskz_extractf32x4_ps,
        _mm256_maskz_extracti32x4_epi32,
        _mm256_maskz_fixupimm_pd,
        _mm256_maskz_fixupimm_ps,
        _mm256_maskz_fmadd_pd,
        _mm256_maskz_fmadd_ps,
        _mm256_maskz_fmaddsub_pd,
        _mm256_maskz_fmaddsub_ps,
        _mm256_maskz_fmsub_pd,
        _mm256_maskz_fmsub_ps,
        _mm256_maskz_fmsubadd_pd,
        _mm256_maskz_fmsubadd_ps,
        _mm256_maskz_fnmadd_pd,
        _mm256_maskz_fnmadd_ps,
        _mm256_maskz_fnmsub_pd,
        _mm256_maskz_fnmsub_ps,
        _mm256_maskz_getexp_pd,
        _mm256_maskz_getexp_ps,
        _mm256_maskz_getmant_pd,
        _mm256_maskz_getmant_ps,
        _mm256_maskz_insertf32x4,
        _mm256_maskz_inserti32x4,
        _mm256_maskz_load_epi32,
        _mm256_maskz_load_epi64,
        _mm256_maskz_load_pd,
        _mm256_maskz_load_ps,
        _mm256_maskz_loadu_epi32,
        _mm256_maskz_loadu_epi64,
        _mm256_maskz_loadu_pd,
        _mm256_maskz_loadu_ps,
        _mm256_maskz_max_epi32,
        _mm256_maskz_max_epi64,
        _mm256_maskz_max_epu32,
        _mm256_maskz_max_epu64,
        _mm256_maskz_max_pd,
        _mm256_maskz_max_ps,
        _mm256_maskz_min_epi32,
        _mm256_maskz_min_epi64,
        _mm256_maskz_min_epu32,
        _mm256_maskz_min_epu64,
        _mm256_maskz_min_pd,
        _mm256_maskz_min_ps,
        _mm256_maskz_mov_epi32,
        _mm256_maskz_mov_epi64,
        _mm256_maskz_mov_pd,
        _mm256_maskz_mov_ps,
        _mm256_maskz_movedup_pd,
        _mm256_maskz_movehdup_ps,
        _mm256_maskz_moveldup_ps,
        _mm256_maskz_mul_epi32,
        _mm256_maskz_mul_epu32,
        _mm256_maskz_mul_pd,
        _mm256_maskz_mul_ps,
        _mm256_maskz_mullo_epi32,
        _mm256_maskz_or_epi32,
        _mm256_maskz_or_epi64,
        _mm256_maskz_permute_pd,
        _mm256_maskz_permute_ps,
        _mm256_maskz_permutevar_pd,
        _mm256_maskz_permutevar_ps,
        _mm256_maskz_permutex2var_epi32,
        _mm256_maskz_permutex2var_epi64,
        _mm256_maskz_permutex2var_pd,
        _mm256_maskz_permutex2var_ps,
        _mm256_maskz_permutex_epi64,
        _mm256_maskz_permutex_pd,
        _mm256_maskz_permutexvar_epi32,
        _mm256_maskz_permutexvar_epi64,
        _mm256_maskz_permutexvar_pd,
        _mm256_maskz_permutexvar_ps,
        _mm256_maskz_rcp14_pd,
        _mm256_maskz_rcp14_ps,
        _mm256_maskz_rol_epi32,
        _mm256_maskz_rol_epi64,
        _mm256_maskz_rolv_epi32,
        _mm256_maskz_rolv_epi64,
        _mm256_maskz_ror_epi32,
        _mm256_maskz_ror_epi64,
        _mm256_maskz_rorv_epi32,
        _mm256_maskz_rorv_epi64,
        _mm256_maskz_roundscale_pd,
        _mm256_maskz_roundscale_ps,
        _mm256_maskz_rsqrt14_pd,
        _mm256_maskz_rsqrt14_ps,
        _mm256_maskz_scalef_pd,
        _mm256_maskz_scalef_ps,
        _mm256_maskz_set1_epi32,
        _mm256_maskz_set1_epi64,
        _mm256_maskz_shuffle_epi32,
        _mm256_maskz_shuffle_f32x4,
        _mm256_maskz_shuffle_f64x2,
        _mm256_maskz_shuffle_i32x4,
        _mm256_maskz_shuffle_i64x2,
        _mm256_maskz_shuffle_pd,
        _mm256_maskz_shuffle_ps,
        _mm256_maskz_sll_epi32,
        _mm256_maskz_sll_epi64,
        _mm256_maskz_slli_epi32,
        _mm256_maskz_slli_epi64,
        _mm256_maskz_sllv_epi32,
        _mm256_maskz_sllv_epi64,
        _mm256_maskz_sqrt_pd,
        _mm256_maskz_sqrt_ps,
        _mm256_maskz_sra_epi32,
        _mm256_maskz_sra_epi64,
        _mm256_maskz_srai_epi32,
        _mm256_maskz_srai_epi64,
        _mm256_maskz_srav_epi32,
        _mm256_maskz_srav_epi64,
        _mm256_maskz_srl_epi32,
        _mm256_maskz_srl_epi64,
        _mm256_maskz_srli_epi32,
        _mm256_maskz_srli_epi64,
        _mm256_maskz_srlv_epi32,
        _mm256_maskz_srlv_epi64,
        _mm256_maskz_sub_epi32,
        _mm256_maskz_sub_epi64,
        _mm256_maskz_sub_pd,
        _mm256_maskz_sub_ps,
        _mm256_maskz_ternarylogic_epi32,
        _mm256_maskz_ternarylogic_epi64,
        _mm256_maskz_unpackhi_epi32,
        _mm256_maskz_unpackhi_epi64,
        _mm256_maskz_unpackhi_pd,
        _mm256_maskz_unpackhi_ps,
        _mm256_maskz_unpacklo_epi32,
        _mm256_maskz_unpacklo_epi64,
        _mm256_maskz_unpacklo_pd,
        _mm256_maskz_unpacklo_ps,
        _mm256_maskz_xor_epi32,
        _mm256_maskz_xor_epi64,
        _mm256_max_epi64,
        _mm256_max_epu64,
        _mm256_min_epi64,
        _mm256_min_epu64,
        _mm256_mmask_i32gather_epi32,
        _mm256_mmask_i32gather_epi64,
        _mm256_mmask_i32gather_pd,
        _mm256_mmask_i32gather_ps,
        _mm256_mmask_i64gather_epi32,
        _mm256_mmask_i64gather_epi64,
        _mm256_mmask_i64gather_pd,
        _mm256_mmask_i64gather_ps,
        _mm256_or_epi32,
        _mm256_or_epi64,
        _mm256_permutex2var_epi32,
        _mm256_permutex2var_epi64,
        _mm256_permutex2var_pd,
        _mm256_permutex2var_ps,
        _mm256_permutex_epi64,
        _mm256_permutex_pd,
        _mm256_permutexvar_epi32,
        _mm256_permutexvar_epi64,
        _mm256_permutexvar_pd,
        _mm256_permutexvar_ps,
        _mm256_rcp14_pd,
        _mm256_rcp14_ps,
        _mm256_rol_epi32,
        _mm256_rol_epi64,
        _mm256_rolv_epi32,
        _mm256_rolv_epi64,
        _mm256_ror_epi32,
        _mm256_ror_epi64,
        _mm256_rorv_epi32,
        _mm256_rorv_epi64,
        _mm256_roundscale_pd,
        _mm256_roundscale_ps,
        _mm256_rsqrt14_pd,
        _mm256_rsqrt14_ps,
        _mm256_scalef_pd,
        _mm256_scalef_ps,
        _mm256_shuffle_f32x4,
        _mm256_shuffle_f64x2,
        _mm256_shuffle_i32x4,
        _mm256_shuffle_i64x2,
        _mm256_sra_epi64,
        _mm256_srai_epi64,
        _mm256_srav_epi64,
        _mm256_store_epi32,
        _mm256_store_epi64,
        _mm256_storeu_epi32,
        _mm256_storeu_epi64,
        _mm256_ternarylogic_epi32,
        _mm256_ternarylogic_epi64,
        _mm256_test_epi32_mask,
        _mm256_test_epi64_mask,
        _mm256_testn_epi32_mask,
        _mm256_testn_epi64_mask,
        _mm256_xor_epi32,
        _mm256_xor_epi64,
        _mm512_abs_epi32,
        _mm512_abs_epi64,
        _mm512_abs_pd,
        _mm512_abs_ps,
        _mm512_add_epi32,
        _mm512_add_epi64,
        _mm512_add_pd,
        _mm512_add_ps,
        _mm512_add_round_pd,
        _mm512_add_round_ps,
        _mm512_alignr_epi32,
        _mm512_alignr_epi64,
        _mm512_and_epi32,
        _mm512_and_epi64,
        _mm512_and_si512,
        _mm512_andnot_epi32,
        _mm512_andnot_epi64,
        _mm512_andnot_si512,
        _mm512_broadcast_f32x4,
        _mm512_broadcast_f64x4,
        _mm512_broadcast_i32x4,
        _mm512_broadcast_i64x4,
        _mm512_broadcastd_epi32,
        _mm512_broadcastq_epi64,
        _mm512_broadcastsd_pd,
        _mm512_broadcastss_ps,
        _mm512_castpd128_pd512,
        _mm512_castpd256_pd512,
        _mm512_castpd512_pd128,
        _mm512_castpd512_pd256,
        _mm512_castpd_ps,
        _mm512_castpd_si512,
        _mm512_castps128_ps512,
        _mm512_castps256_ps512,
        _mm512_castps512_ps128,
        _mm512_castps512_ps256,
        _mm512_castps_pd,
        _mm512_castps_si512,
        _mm512_castsi128_si512,
        _mm512_castsi256_si512,
        _mm512_castsi512_pd,
        _mm512_castsi512_ps,
        _mm512_castsi512_si128,
        _mm512_castsi512_si256,
        _mm512_cmp_epi32_mask,
        _mm512_cmp_epi64_mask,
        _mm512_cmp_epu32_mask,
        _mm512_cmp_epu64_mask,
        _mm512_cmp_pd_mask,
        _mm512_cmp_ps_mask,
        _mm512_cmp_round_pd_mask,
        _mm512_cmp_round_ps_mask,
        _mm512_cmpeq_epi32_mask,
        _mm512_cmpeq_epi64_mask,
        _mm512_cmpeq_epu32_mask,
        _mm512_cmpeq_epu64_mask,
        _mm512_cmpeq_pd_mask,
        _mm512_cmpeq_ps_mask,
        _mm512_cmpge_epi32_mask,
        _mm512_cmpge_epi64_mask,
        _mm512_cmpge_epu32_mask,
        _mm512_cmpge_epu64_mask,
        _mm512_cmpgt_epi32_mask,
        _mm512_cmpgt_epi64_mask,
        _mm512_cmpgt_epu32_mask,
        _mm512_cmpgt_epu64_mask,
        _mm512_cmple_epi32_mask,
        _mm512_cmple_epi64_mask,
        _mm512_cmple_epu32_mask,
        _mm512_cmple_epu64_mask,
        _mm512_cmple_pd_mask,
        _mm512_cmple_ps_mask,
        _mm512_cmplt_epi32_mask,
        _mm512_cmplt_epi64_mask,
        _mm512_cmplt_epu32_mask,
        _mm512_cmplt_epu64_mask,
        _mm512_cmplt_pd_mask,
        _mm512_cmplt_ps_mask,
        _mm512_cmpneq_epi32_mask,
        _mm512_cmpneq_epi64_mask,
        _mm512_cmpneq_epu32_mask,
        _mm512_cmpneq_epu64_mask,
        _mm512_cmpneq_pd_mask,
        _mm512_cmpneq_ps_mask,
        _mm512_cmpnle_pd_mask,
        _mm512_cmpnle_ps_mask,
        _mm512_cmpnlt_pd_mask,
        _mm512_cmpnlt_ps_mask,
        _mm512_cmpord_pd_mask,
        _mm512_cmpord_ps_mask,
        _mm512_cmpunord_pd_mask,
        _mm512_cmpunord_ps_mask,
        _mm512_cvt_roundepi32_ps,
        _mm512_cvt_roundepu32_ps,
        _mm512_cvt_roundpd_epi32,
        _mm512_cvt_roundpd_epu32,
        _mm512_cvt_roundpd_ps,
        _mm512_cvt_roundph_ps,
        _mm512_cvt_roundps_epi32,
        _mm512_cvt_roundps_epu32,
        _mm512_cvt_roundps_pd,
        _mm512_cvt_roundps_ph,
        _mm512_cvtepi16_epi32,
        _mm512_cvtepi16_epi64,
        _mm512_cvtepi32_epi16,
        _mm512_cvtepi32_epi64,
        _mm512_cvtepi32_epi8,
        _mm512_cvtepi32_pd,
        _mm512_cvtepi32_ps,
        _mm512_cvtepi32lo_pd,
        _mm512_cvtepi64_epi16,
        _mm512_cvtepi64_epi32,
        _mm512_cvtepi64_epi8,
        _mm512_cvtepi8_epi32,
        _mm512_cvtepi8_epi64,
        _mm512_cvtepu16_epi32,
        _mm512_cvtepu16_epi64,
        _mm512_cvtepu32_epi64,
        _mm512_cvtepu32_pd,
        _mm512_cvtepu32_ps,
        _mm512_cvtepu32lo_pd,
        _mm512_cvtepu8_epi32,
        _mm512_cvtepu8_epi64,
        _mm512_cvtpd_epi32,
        _mm512_cvtpd_epu32,
        _mm512_cvtpd_ps,
        _mm512_cvtpd_pslo,
        _mm512_cvtph_ps,
        _mm512_cvtps_epi32,
        _mm512_cvtps_epu32,
        _mm512_cvtps_pd,
        _mm512_cvtps_ph,
        _mm512_cvtpslo_pd,
        _mm512_cvtsd_f64,
        _mm512_cvtsepi32_epi16,
        _mm512_cvtsepi32_epi8,
        _mm512_cvtsepi64_epi16,
        _mm512_cvtsepi64_epi32,
        _mm512_cvtsepi64_epi8,
        _mm512_cvtsi512_si32,
        _mm512_cvtss_f32,
        _mm512_cvtt_roundpd_epi32,
        _mm512_cvtt_roundpd_epu32,
        _mm512_cvtt_roundps_epi32,
        _mm512_cvtt_roundps_epu32,
        _mm512_cvttpd_epi32,
        _mm512_cvttpd_epu32,
        _mm512_cvttps_epi32,
        _mm512_cvttps_epu32,
        _mm512_cvtusepi32_epi16,
        _mm512_cvtusepi32_epi8,
        _mm512_cvtusepi64_epi16,
        _mm512_cvtusepi64_epi32,
        _mm512_cvtusepi64_epi8,
        _mm512_div_pd,
        _mm512_div_ps,
        _mm512_div_round_pd,
        _mm512_div_round_ps,
        _mm512_extractf32x4_ps,
        _mm512_extractf64x4_pd,
        _mm512_extracti32x4_epi32,
        _mm512_extracti64x4_epi64,
        _mm512_fixupimm_pd,
        _mm512_fixupimm_ps,
        _mm512_fixupimm_round_pd,
        _mm512_fixupimm_round_ps,
        _mm512_fmadd_pd,
        _mm512_fmadd_ps,
        _mm512_fmadd_round_pd,
        _mm512_fmadd_round_ps,
        _mm512_fmaddsub_pd,
        _mm512_fmaddsub_ps,
        _mm512_fmaddsub_round_pd,
        _mm512_fmaddsub_round_ps,
        _mm512_fmsub_pd,
        _mm512_fmsub_ps,
        _mm512_fmsub_round_pd,
        _mm512_fmsub_round_ps,
        _mm512_fmsubadd_pd,
        _mm512_fmsubadd_ps,
        _mm512_fmsubadd_round_pd,
        _mm512_fmsubadd_round_ps,
        _mm512_fnmadd_pd,
        _mm512_fnmadd_ps,
        _mm512_fnmadd_round_pd,
        _mm512_fnmadd_round_ps,
        _mm512_fnmsub_pd,
        _mm512_fnmsub_ps,
        _mm512_fnmsub_round_pd,
        _mm512_fnmsub_round_ps,
        _mm512_getexp_pd,
        _mm512_getexp_ps,
        _mm512_getexp_round_pd,
        _mm512_getexp_round_ps,
        _mm512_getmant_pd,
        _mm512_getmant_ps,
        _mm512_getmant_round_pd,
        _mm512_getmant_round_ps,
        _mm512_i32gather_epi32,
        _mm512_i32gather_epi64,
        _mm512_i32gather_pd,
        _mm512_i32gather_ps,
        _mm512_i32logather_epi64,
        _mm512_i32logather_pd,
        _mm512_i32loscatter_epi64,
        _mm512_i32loscatter_pd,
        _mm512_i32scatter_epi32,
        _mm512_i32scatter_epi64,
        _mm512_i32scatter_pd,
        _mm512_i32scatter_ps,
        _mm512_i64gather_epi32,
        _mm512_i64gather_epi64,
        _mm512_i64gather_pd,
        _mm512_i64gather_ps,
        _mm512_i64scatter_epi32,
        _mm512_i64scatter_epi64,
        _mm512_i64scatter_pd,
        _mm512_i64scatter_ps,
        _mm512_insertf32x4,
        _mm512_insertf64x4,
        _mm512_inserti32x4,
        _mm512_inserti64x4,
        _mm512_int2mask,
        _mm512_kand,
        _mm512_kandn,
        _mm512_kmov,
        _mm512_knot,
        _mm512_kor,
        _mm512_kortestc,
        _mm512_kortestz,
        _mm512_kunpackb,
        _mm512_kxnor,
        _mm512_kxor,
        _mm512_load_epi32,
        _mm512_load_epi64,
        _mm512_load_pd,
        _mm512_load_ps,
        _mm512_load_si512,
        _mm512_loadu_epi32,
        _mm512_loadu_epi64,
        _mm512_loadu_pd,
        _mm512_loadu_ps,
        _mm512_loadu_si512,
        _mm512_mask2_permutex2var_epi32,
        _mm512_mask2_permutex2var_epi64,
        _mm512_mask2_permutex2var_pd,
        _mm512_mask2_permutex2var_ps,
        _mm512_mask2int,
        _mm512_mask3_fmadd_pd,
        _mm512_mask3_fmadd_ps,
        _mm512_mask3_fmadd_round_pd,
        _mm512_mask3_fmadd_round_ps,
        _mm512_mask3_fmaddsub_pd,
        _mm512_mask3_fmaddsub_ps,
        _mm512_mask3_fmaddsub_round_pd,
        _mm512_mask3_fmaddsub_round_ps,
        _mm512_mask3_fmsub_pd,
        _mm512_mask3_fmsub_ps,
        _mm512_mask3_fmsub_round_pd,
        _mm512_mask3_fmsub_round_ps,
        _mm512_mask3_fmsubadd_pd,
        _mm512_mask3_fmsubadd_ps,
        _mm512_mask3_fmsubadd_round_pd,
        _mm512_mask3_fmsubadd_round_ps,
        _mm512_mask3_fnmadd_pd,
        _mm512_mask3_fnmadd_ps,
        _mm512_mask3_fnmadd_round_pd,
        _mm512_mask3_fnmadd_round_ps,
        _mm512_mask3_fnmsub_pd,
        _mm512_mask3_fnmsub_ps,
        _mm512_mask3_fnmsub_round_pd,
        _mm512_mask3_fnmsub_round_ps,
        _mm512_mask_abs_epi32,
        _mm512_mask_abs_epi64,
        _mm512_mask_abs_pd,
        _mm512_mask_abs_ps,
        _mm512_mask_add_epi32,
        _mm512_mask_add_epi64,
        _mm512_mask_add_pd,
        _mm512_mask_add_ps,
        _mm512_mask_add_round_pd,
        _mm512_mask_add_round_ps,
        _mm512_mask_alignr_epi32,
        _mm512_mask_alignr_epi64,
        _mm512_mask_and_epi32,
        _mm512_mask_and_epi64,
        _mm512_mask_andnot_epi32,
        _mm512_mask_andnot_epi64,
        _mm512_mask_blend_epi32,
        _mm512_mask_blend_epi64,
        _mm512_mask_blend_pd,
        _mm512_mask_blend_ps,
        _mm512_mask_broadcast_f32x4,
        _mm512_mask_broadcast_f64x4,
        _mm512_mask_broadcast_i32x4,
        _mm512_mask_broadcast_i64x4,
        _mm512_mask_broadcastd_epi32,
        _mm512_mask_broadcastq_epi64,
        _mm512_mask_broadcastsd_pd,
        _mm512_mask_broadcastss_ps,
        _mm512_mask_cmp_epi32_mask,
        _mm512_mask_cmp_epi64_mask,
        _mm512_mask_cmp_epu32_mask,
        _mm512_mask_cmp_epu64_mask,
        _mm512_mask_cmp_pd_mask,
        _mm512_mask_cmp_ps_mask,
        _mm512_mask_cmp_round_pd_mask,
        _mm512_mask_cmp_round_ps_mask,
        _mm512_mask_cmpeq_epi32_mask,
        _mm512_mask_cmpeq_epi64_mask,
        _mm512_mask_cmpeq_epu32_mask,
        _mm512_mask_cmpeq_epu64_mask,
        _mm512_mask_cmpeq_pd_mask,
        _mm512_mask_cmpeq_ps_mask,
        _mm512_mask_cmpge_epi32_mask,
        _mm512_mask_cmpge_epi64_mask,
        _mm512_mask_cmpge_epu32_mask,
        _mm512_mask_cmpge_epu64_mask,
        _mm512_mask_cmpgt_epi32_mask,
        _mm512_mask_cmpgt_epi64_mask,
        _mm512_mask_cmpgt_epu32_mask,
        _mm512_mask_cmpgt_epu64_mask,
        _mm512_mask_cmple_epi32_mask,
        _mm512_mask_cmple_epi64_mask,
        _mm512_mask_cmple_epu32_mask,
        _mm512_mask_cmple_epu64_mask,
        _mm512_mask_cmple_pd_mask,
        _mm512_mask_cmple_ps_mask,
        _mm512_mask_cmplt_epi32_mask,
        _mm512_mask_cmplt_epi64_mask,
        _mm512_mask_cmplt_epu32_mask,
        _mm512_mask_cmplt_epu64_mask,
        _mm512_mask_cmplt_pd_mask,
        _mm512_mask_cmplt_ps_mask,
        _mm512_mask_cmpneq_epi32_mask,
        _mm512_mask_cmpneq_epi64_mask,
        _mm512_mask_cmpneq_epu32_mask,
        _mm512_mask_cmpneq_epu64_mask,
        _mm512_mask_cmpneq_pd_mask,
        _mm512_mask_cmpneq_ps_mask,
        _mm512_mask_cmpnle_pd_mask,
        _mm512_mask_cmpnle_ps_mask,
        _mm512_mask_cmpnlt_pd_mask,
        _mm512_mask_cmpnlt_ps_mask,
        _mm512_mask_cmpord_pd_mask,
        _mm512_mask_cmpord_ps_mask,
        _mm512_mask_cmpunord_pd_mask,
        _mm512_mask_cmpunord_ps_mask,
        _mm512_mask_compress_epi32,
        _mm512_mask_compress_epi64,
        _mm512_mask_compress_pd,
        _mm512_mask_compress_ps,
        _mm512_mask_compressstoreu_epi32,
        _mm512_mask_compressstoreu_epi64,
        _mm512_mask_compressstoreu_pd,
        _mm512_mask_compressstoreu_ps,
        _mm512_mask_cvt_roundepi32_ps,
        _mm512_mask_cvt_roundepu32_ps,
        _mm512_mask_cvt_roundpd_epi32,
        _mm512_mask_cvt_roundpd_epu32,
        _mm512_mask_cvt_roundpd_ps,
        _mm512_mask_cvt_roundph_ps,
        _mm512_mask_cvt_roundps_epi32,
        _mm512_mask_cvt_roundps_epu32,
        _mm512_mask_cvt_roundps_pd,
        _mm512_mask_cvt_roundps_ph,
        _mm512_mask_cvtepi16_epi32,
        _mm512_mask_cvtepi16_epi64,
        _mm512_mask_cvtepi32_epi16,
        _mm512_mask_cvtepi32_epi64,
        _mm512_mask_cvtepi32_epi8,
        _mm512_mask_cvtepi32_pd,
        _mm512_mask_cvtepi32_ps,
        _mm512_mask_cvtepi32_storeu_epi16,
        _mm512_mask_cvtepi32_storeu_epi8,
        _mm512_mask_cvtepi32lo_pd,
        _mm512_mask_cvtepi64_epi16,
        _mm512_mask_cvtepi64_epi32,
        _mm512_mask_cvtepi64_epi8,
        _mm512_mask_cvtepi64_storeu_epi16,
        _mm512_mask_cvtepi64_storeu_epi32,
        _mm512_mask_cvtepi64_storeu_epi8,
        _mm512_mask_cvtepi8_epi32,
        _mm512_mask_cvtepi8_epi64,
        _mm512_mask_cvtepu16_epi32,
        _mm512_mask_cvtepu16_epi64,
        _mm512_mask_cvtepu32_epi64,
        _mm512_mask_cvtepu32_pd,
        _mm512_mask_cvtepu32_ps,
        _mm512_mask_cvtepu32lo_pd,
        _mm512_mask_cvtepu8_epi32,
        _mm512_mask_cvtepu8_epi64,
        _mm512_mask_cvtpd_epi32,
        _mm512_mask_cvtpd_epu32,
        _mm512_mask_cvtpd_ps,
        _mm512_mask_cvtpd_pslo,
        _mm512_mask_cvtph_ps,
        _mm512_mask_cvtps_epi32,
        _mm512_mask_cvtps_epu32,
        _mm512_mask_cvtps_pd,
        _mm512_mask_cvtps_ph,
        _mm512_mask_cvtpslo_pd,
        _mm512_mask_cvtsepi32_epi16,
        _mm512_mask_cvtsepi32_epi8,
        _mm512_mask_cvtsepi32_storeu_epi16,
        _mm512_mask_cvtsepi32_storeu_epi8,
        _mm512_mask_cvtsepi64_epi16,
        _mm512_mask_cvtsepi64_epi32,
        _mm512_mask_cvtsepi64_epi8,
        _mm512_mask_cvtsepi64_storeu_epi16,
        _mm512_mask_cvtsepi64_storeu_epi32,
        _mm512_mask_cvtsepi64_storeu_epi8,
        _mm512_mask_cvtt_roundpd_epi32,
        _mm512_mask_cvtt_roundpd_epu32,
        _mm512_mask_cvtt_roundps_epi32,
        _mm512_mask_cvtt_roundps_epu32,
        _mm512_mask_cvttpd_epi32,
        _mm512_mask_cvttpd_epu32,
        _mm512_mask_cvttps_epi32,
        _mm512_mask_cvttps_epu32,
        _mm512_mask_cvtusepi32_epi16,
        _mm512_mask_cvtusepi32_epi8,
        _mm512_mask_cvtusepi32_storeu_epi16,
        _mm512_mask_cvtusepi32_storeu_epi8,
        _mm512_mask_cvtusepi64_epi16,
        _mm512_mask_cvtusepi64_epi32,
        _mm512_mask_cvtusepi64_epi8,
        _mm512_mask_cvtusepi64_storeu_epi16,
        _mm512_mask_cvtusepi64_storeu_epi32,
        _mm512_mask_cvtusepi64_storeu_epi8,
        _mm512_mask_div_pd,
        _mm512_mask_div_ps,
        _mm512_mask_div_round_pd,
        _mm512_mask_div_round_ps,
        _mm512_mask_expand_epi32,
        _mm512_mask_expand_epi64,
        _mm512_mask_expand_pd,
        _mm512_mask_expand_ps,
        _mm512_mask_expandloadu_epi32,
        _mm512_mask_expandloadu_epi64,
        _mm512_mask_expandloadu_pd,
        _mm512_mask_expandloadu_ps,
        _mm512_mask_extractf32x4_ps,
        _mm512_mask_extractf64x4_pd,
        _mm512_mask_extracti32x4_epi32,
        _mm512_mask_extracti64x4_epi64,
        _mm512_mask_fixupimm_pd,
        _mm512_mask_fixupimm_ps,
        _mm512_mask_fixupimm_round_pd,
        _mm512_mask_fixupimm_round_ps,
        _mm512_mask_fmadd_pd,
        _mm512_mask_fmadd_ps,
        _mm512_mask_fmadd_round_pd,
        _mm512_mask_fmadd_round_ps,
        _mm512_mask_fmaddsub_pd,
        _mm512_mask_fmaddsub_ps,
        _mm512_mask_fmaddsub_round_pd,
        _mm512_mask_fmaddsub_round_ps,
        _mm512_mask_fmsub_pd,
        _mm512_mask_fmsub_ps,
        _mm512_mask_fmsub_round_pd,
        _mm512_mask_fmsub_round_ps,
        _mm512_mask_fmsubadd_pd,
        _mm512_mask_fmsubadd_ps,
        _mm512_mask_fmsubadd_round_pd,
        _mm512_mask_fmsubadd_round_ps,
        _mm512_mask_fnmadd_pd,
        _mm512_mask_fnmadd_ps,
        _mm512_mask_fnmadd_round_pd,
        _mm512_mask_fnmadd_round_ps,
        _mm512_mask_fnmsub_pd,
        _mm512_mask_fnmsub_ps,
        _mm512_mask_fnmsub_round_pd,
        _mm512_mask_fnmsub_round_ps,
        _mm512_mask_getexp_pd,
        _mm512_mask_getexp_ps,
        _mm512_mask_getexp_round_pd,
        _mm512_mask_getexp_round_ps,
        _mm512_mask_getmant_pd,
        _mm512_mask_getmant_ps,
        _mm512_mask_getmant_round_pd,
        _mm512_mask_getmant_round_ps,
        _mm512_mask_i32gather_epi32,
        _mm512_mask_i32gather_epi64,
        _mm512_mask_i32gather_pd,
        _mm512_mask_i32gather_ps,
        _mm512_mask_i32logather_epi64,
        _mm512_mask_i32logather_pd,
        _mm512_mask_i32loscatter_epi64,
        _mm512_mask_i32loscatter_pd,
        _mm512_mask_i32scatter_epi32,
        _mm512_mask_i32scatter_epi64,
        _mm512_mask_i32scatter_pd,
        _mm512_mask_i32scatter_ps,
        _mm512_mask_i64gather_epi32,
        _mm512_mask_i64gather_epi64,
        _mm512_mask_i64gather_pd,
        _mm512_mask_i64gather_ps,
        _mm512_mask_i64scatter_epi32,
        _mm512_mask_i64scatter_epi64,
        _mm512_mask_i64scatter_pd,
        _mm512_mask_i64scatter_ps,
        _mm512_mask_insertf32x4,
        _mm512_mask_insertf64x4,
        _mm512_mask_inserti32x4,
        _mm512_mask_inserti64x4,
        _mm512_mask_load_epi32,
        _mm512_mask_load_epi64,
        _mm512_mask_load_pd,
        _mm512_mask_load_ps,
        _mm512_mask_loadu_epi32,
        _mm512_mask_loadu_epi64,
        _mm512_mask_loadu_pd,
        _mm512_mask_loadu_ps,
        _mm512_mask_max_epi32,
        _mm512_mask_max_epi64,
        _mm512_mask_max_epu32,
        _mm512_mask_max_epu64,
        _mm512_mask_max_pd,
        _mm512_mask_max_ps,
        _mm512_mask_max_round_pd,
        _mm512_mask_max_round_ps,
        _mm512_mask_min_epi32,
        _mm512_mask_min_epi64,
        _mm512_mask_min_epu32,
        _mm512_mask_min_epu64,
        _mm512_mask_min_pd,
        _mm512_mask_min_ps,
        _mm512_mask_min_round_pd,
        _mm512_mask_min_round_ps,
        _mm512_mask_mov_epi32,
        _mm512_mask_mov_epi64,
        _mm512_mask_mov_pd,
        _mm512_mask_mov_ps,
        _mm512_mask_movedup_pd,
        _mm512_mask_movehdup_ps,
        _mm512_mask_moveldup_ps,
        _mm512_mask_mul_epi32,
        _mm512_mask_mul_epu32,
        _mm512_mask_mul_pd,
        _mm512_mask_mul_ps,
        _mm512_mask_mul_round_pd,
        _mm512_mask_mul_round_ps,
        _mm512_mask_mullo_epi32,
        _mm512_mask_mullox_epi64,
        _mm512_mask_or_epi32,
        _mm512_mask_or_epi64,
        _mm512_mask_permute_pd,
        _mm512_mask_permute_ps,
        _mm512_mask_permutevar_epi32,
        _mm512_mask_permutevar_pd,
        _mm512_mask_permutevar_ps,
        _mm512_mask_permutex2var_epi32,
        _mm512_mask_permutex2var_epi64,
        _mm512_mask_permutex2var_pd,
        _mm512_mask_permutex2var_ps,
        _mm512_mask_permutex_epi64,
        _mm512_mask_permutex_pd,
        _mm512_mask_permutexvar_epi32,
        _mm512_mask_permutexvar_epi64,
        _mm512_mask_permutexvar_pd,
        _mm512_mask_permutexvar_ps,
        _mm512_mask_rcp14_pd,
        _mm512_mask_rcp14_ps,
        _mm512_mask_reduce_add_epi32,
        _mm512_mask_reduce_add_epi64,
        _mm512_mask_reduce_add_pd,
        _mm512_mask_reduce_add_ps,
        _mm512_mask_reduce_and_epi32,
        _mm512_mask_reduce_and_epi64,
        _mm512_mask_reduce_max_epi32,
        _mm512_mask_reduce_max_epi64,
        _mm512_mask_reduce_max_epu32,
        _mm512_mask_reduce_max_epu64,
        _mm512_mask_reduce_max_pd,
        _mm512_mask_reduce_max_ps,
        _mm512_mask_reduce_min_epi32,
        _mm512_mask_reduce_min_epi64,
        _mm512_mask_reduce_min_epu32,
        _mm512_mask_reduce_min_epu64,
        _mm512_mask_reduce_min_pd,
        _mm512_mask_reduce_min_ps,
        _mm512_mask_reduce_mul_epi32,
        _mm512_mask_reduce_mul_epi64,
        _mm512_mask_reduce_mul_pd,
        _mm512_mask_reduce_mul_ps,
        _mm512_mask_reduce_or_epi32,
        _mm512_mask_reduce_or_epi64,
        _mm512_mask_rol_epi32,
        _mm512_mask_rol_epi64,
        _mm512_mask_rolv_epi32,
        _mm512_mask_rolv_epi64,
        _mm512_mask_ror_epi32,
        _mm512_mask_ror_epi64,
        _mm512_mask_rorv_epi32,
        _mm512_mask_rorv_epi64,
        _mm512_mask_roundscale_pd,
        _mm512_mask_roundscale_ps,
        _mm512_mask_roundscale_round_pd,
        _mm512_mask_roundscale_round_ps,
        _mm512_mask_rsqrt14_pd,
        _mm512_mask_rsqrt14_ps,
        _mm512_mask_scalef_pd,
        _mm512_mask_scalef_ps,
        _mm512_mask_scalef_round_pd,
        _mm512_mask_scalef_round_ps,
        _mm512_mask_set1_epi32,
        _mm512_mask_set1_epi64,
        _mm512_mask_shuffle_epi32,
        _mm512_mask_shuffle_f32x4,
        _mm512_mask_shuffle_f64x2,
        _mm512_mask_shuffle_i32x4,
        _mm512_mask_shuffle_i64x2,
        _mm512_mask_shuffle_pd,
        _mm512_mask_shuffle_ps,
        _mm512_mask_sll_epi32,
        _mm512_mask_sll_epi64,
        _mm512_mask_slli_epi32,
        _mm512_mask_slli_epi64,
        _mm512_mask_sllv_epi32,
        _mm512_mask_sllv_epi64,
        _mm512_mask_sqrt_pd,
        _mm512_mask_sqrt_ps,
        _mm512_mask_sqrt_round_pd,
        _mm512_mask_sqrt_round_ps,
        _mm512_mask_sra_epi32,
        _mm512_mask_sra_epi64,
        _mm512_mask_srai_epi32,
        _mm512_mask_srai_epi64,
        _mm512_mask_srav_epi32,
        _mm512_mask_srav_epi64,
        _mm512_mask_srl_epi32,
        _mm512_mask_srl_epi64,
        _mm512_mask_srli_epi32,
        _mm512_mask_srli_epi64,
        _mm512_mask_srlv_epi32,
        _mm512_mask_srlv_epi64,
        _mm512_mask_store_epi32,
        _mm512_mask_store_epi64,
        _mm512_mask_store_pd,
        _mm512_mask_store_ps,
        _mm512_mask_storeu_epi32,
        _mm512_mask_storeu_epi64,
        _mm512_mask_storeu_pd,
        _mm512_mask_storeu_ps,
        _mm512_mask_sub_epi32,
        _mm512_mask_sub_epi64,
        _mm512_mask_sub_pd,
        _mm512_mask_sub_ps,
        _mm512_mask_sub_round_pd,
        _mm512_mask_sub_round_ps,
        _mm512_mask_ternarylogic_epi32,
        _mm512_mask_ternarylogic_epi64,
        _mm512_mask_test_epi32_mask,
        _mm512_mask_test_epi64_mask,
        _mm512_mask_testn_epi32_mask,
        _mm512_mask_testn_epi64_mask,
        _mm512_mask_unpackhi_epi32,
        _mm512_mask_unpackhi_epi64,
        _mm512_mask_unpackhi_pd,
        _mm512_mask_unpackhi_ps,
        _mm512_mask_unpacklo_epi32,
        _mm512_mask_unpacklo_epi64,
        _mm512_mask_unpacklo_pd,
        _mm512_mask_unpacklo_ps,
        _mm512_mask_xor_epi32,
        _mm512_mask_xor_epi64,
        _mm512_maskz_abs_epi32,
        _mm512_maskz_abs_epi64,
        _mm512_maskz_add_epi32,
        _mm512_maskz_add_epi64,
        _mm512_maskz_add_pd,
        _mm512_maskz_add_ps,
        _mm512_maskz_add_round_pd,
        _mm512_maskz_add_round_ps,
        _mm512_maskz_alignr_epi32,
        _mm512_maskz_alignr_epi64,
        _mm512_maskz_and_epi32,
        _mm512_maskz_and_epi64,
        _mm512_maskz_andnot_epi32,
        _mm512_maskz_andnot_epi64,
        _mm512_maskz_broadcast_f32x4,
        _mm512_maskz_broadcast_f64x4,
        _mm512_maskz_broadcast_i32x4,
        _mm512_maskz_broadcast_i64x4,
        _mm512_maskz_broadcastd_epi32,
        _mm512_maskz_broadcastq_epi64,
        _mm512_maskz_broadcastsd_pd,
        _mm512_maskz_broadcastss_ps,
        _mm512_maskz_compress_epi32,
        _mm512_maskz_compress_epi64,
        _mm512_maskz_compress_pd,
        _mm512_maskz_compress_ps,
        _mm512_maskz_cvt_roundepi32_ps,
        _mm512_maskz_cvt_roundepu32_ps,
        _mm512_maskz_cvt_roundpd_epi32,
        _mm512_maskz_cvt_roundpd_epu32,
        _mm512_maskz_cvt_roundpd_ps,
        _mm512_maskz_cvt_roundph_ps,
        _mm512_maskz_cvt_roundps_epi32,
        _mm512_maskz_cvt_roundps_epu32,
        _mm512_maskz_cvt_roundps_pd,
        _mm512_maskz_cvt_roundps_ph,
        _mm512_maskz_cvtepi16_epi32,
        _mm512_maskz_cvtepi16_epi64,
        _mm512_maskz_cvtepi32_epi16,
        _mm512_maskz_cvtepi32_epi64,
        _mm512_maskz_cvtepi32_epi8,
        _mm512_maskz_cvtepi32_pd,
        _mm512_maskz_cvtepi32_ps,
        _mm512_maskz_cvtepi64_epi16,
        _mm512_maskz_cvtepi64_epi32,
        _mm512_maskz_cvtepi64_epi8,
        _mm512_maskz_cvtepi8_epi32,
        _mm512_maskz_cvtepi8_epi64,
        _mm512_maskz_cvtepu16_epi32,
        _mm512_maskz_cvtepu16_epi64,
        _mm512_maskz_cvtepu32_epi64,
        _mm512_maskz_cvtepu32_pd,
        _mm512_maskz_cvtepu32_ps,
        _mm512_maskz_cvtepu8_epi32,
        _mm512_maskz_cvtepu8_epi64,
        _mm512_maskz_cvtpd_epi32,
        _mm512_maskz_cvtpd_epu32,
        _mm512_maskz_cvtpd_ps,
        _mm512_maskz_cvtph_ps,
        _mm512_maskz_cvtps_epi32,
        _mm512_maskz_cvtps_epu32,
        _mm512_maskz_cvtps_pd,
        _mm512_maskz_cvtps_ph,
        _mm512_maskz_cvtsepi32_epi16,
        _mm512_maskz_cvtsepi32_epi8,
        _mm512_maskz_cvtsepi64_epi16,
        _mm512_maskz_cvtsepi64_epi32,
        _mm512_maskz_cvtsepi64_epi8,
        _mm512_maskz_cvtt_roundpd_epi32,
        _mm512_maskz_cvtt_roundpd_epu32,
        _mm512_maskz_cvtt_roundps_epi32,
        _mm512_maskz_cvtt_roundps_epu32,
        _mm512_maskz_cvttpd_epi32,
        _mm512_maskz_cvttpd_epu32,
        _mm512_maskz_cvttps_epi32,
        _mm512_maskz_cvttps_epu32,
        _mm512_maskz_cvtusepi32_epi16,
        _mm512_maskz_cvtusepi32_epi8,
        _mm512_maskz_cvtusepi64_epi16,
        _mm512_maskz_cvtusepi64_epi32,
        _mm512_maskz_cvtusepi64_epi8,
        _mm512_maskz_div_pd,
        _mm512_maskz_div_ps,
        _mm512_maskz_div_round_pd,
        _mm512_maskz_div_round_ps,
        _mm512_maskz_expand_epi32,
        _mm512_maskz_expand_epi64,
        _mm512_maskz_expand_pd,
        _mm512_maskz_expand_ps,
        _mm512_maskz_expandloadu_epi32,
        _mm512_maskz_expandloadu_epi64,
        _mm512_maskz_expandloadu_pd,
        _mm512_maskz_expandloadu_ps,
        _mm512_maskz_extractf32x4_ps,
        _mm512_maskz_extractf64x4_pd,
        _mm512_maskz_extracti32x4_epi32,
        _mm512_maskz_extracti64x4_epi64,
        _mm512_maskz_fixupimm_pd,
        _mm512_maskz_fixupimm_ps,
        _mm512_maskz_fixupimm_round_pd,
        _mm512_maskz_fixupimm_round_ps,
        _mm512_maskz_fmadd_pd,
        _mm512_maskz_fmadd_ps,
        _mm512_maskz_fmadd_round_pd,
        _mm512_maskz_fmadd_round_ps,
        _mm512_maskz_fmaddsub_pd,
        _mm512_maskz_fmaddsub_ps,
        _mm512_maskz_fmaddsub_round_pd,
        _mm512_maskz_fmaddsub_round_ps,
        _mm512_maskz_fmsub_pd,
        _mm512_maskz_fmsub_ps,
        _mm512_maskz_fmsub_round_pd,
        _mm512_maskz_fmsub_round_ps,
        _mm512_maskz_fmsubadd_pd,
        _mm512_maskz_fmsubadd_ps,
        _mm512_maskz_fmsubadd_round_pd,
        _mm512_maskz_fmsubadd_round_ps,
        _mm512_maskz_fnmadd_pd,
        _mm512_maskz_fnmadd_ps,
        _mm512_maskz_fnmadd_round_pd,
        _mm512_maskz_fnmadd_round_ps,
        _mm512_maskz_fnmsub_pd,
        _mm512_maskz_fnmsub_ps,
        _mm512_maskz_fnmsub_round_pd,
        _mm512_maskz_fnmsub_round_ps,
        _mm512_maskz_getexp_pd,
        _mm512_maskz_getexp_ps,
        _mm512_maskz_getexp_round_pd,
        _mm512_maskz_getexp_round_ps,
        _mm512_maskz_getmant_pd,
        _mm512_maskz_getmant_ps,
        _mm512_maskz_getmant_round_pd,
        _mm512_maskz_getmant_round_ps,
        _mm512_maskz_insertf32x4,
        _mm512_maskz_insertf64x4,
        _mm512_maskz_inserti32x4,
        _mm512_maskz_inserti64x4,
        _mm512_maskz_load_epi32,
        _mm512_maskz_load_epi64,
        _mm512_maskz_load_pd,
        _mm512_maskz_load_ps,
        _mm512_maskz_loadu_epi32,
        _mm512_maskz_loadu_epi64,
        _mm512_maskz_loadu_pd,
        _mm512_maskz_loadu_ps,
        _mm512_maskz_max_epi32,
        _mm512_maskz_max_epi64,
        _mm512_maskz_max_epu32,
        _mm512_maskz_max_epu64,
        _mm512_maskz_max_pd,
        _mm512_maskz_max_ps,
        _mm512_maskz_max_round_pd,
        _mm512_maskz_max_round_ps,
        _mm512_maskz_min_epi32,
        _mm512_maskz_min_epi64,
        _mm512_maskz_min_epu32,
        _mm512_maskz_min_epu64,
        _mm512_maskz_min_pd,
        _mm512_maskz_min_ps,
        _mm512_maskz_min_round_pd,
        _mm512_maskz_min_round_ps,
        _mm512_maskz_mov_epi32,
        _mm512_maskz_mov_epi64,
        _mm512_maskz_mov_pd,
        _mm512_maskz_mov_ps,
        _mm512_maskz_movedup_pd,
        _mm512_maskz_movehdup_ps,
        _mm512_maskz_moveldup_ps,
        _mm512_maskz_mul_epi32,
        _mm512_maskz_mul_epu32,
        _mm512_maskz_mul_pd,
        _mm512_maskz_mul_ps,
        _mm512_maskz_mul_round_pd,
        _mm512_maskz_mul_round_ps,
        _mm512_maskz_mullo_epi32,
        _mm512_maskz_or_epi32,
        _mm512_maskz_or_epi64,
        _mm512_maskz_permute_pd,
        _mm512_maskz_permute_ps,
        _mm512_maskz_permutevar_pd,
        _mm512_maskz_permutevar_ps,
        _mm512_maskz_permutex2var_epi32,
        _mm512_maskz_permutex2var_epi64,
        _mm512_maskz_permutex2var_pd,
        _mm512_maskz_permutex2var_ps,
        _mm512_maskz_permutex_epi64,
        _mm512_maskz_permutex_pd,
        _mm512_maskz_permutexvar_epi32,
        _mm512_maskz_permutexvar_epi64,
        _mm512_maskz_permutexvar_pd,
        _mm512_maskz_permutexvar_ps,
        _mm512_maskz_rcp14_pd,
        _mm512_maskz_rcp14_ps,
        _mm512_maskz_rol_epi32,
        _mm512_maskz_rol_epi64,
        _mm512_maskz_rolv_epi32,
        _mm512_maskz_rolv_epi64,
        _mm512_maskz_ror_epi32,
        _mm512_maskz_ror_epi64,
        _mm512_maskz_rorv_epi32,
        _mm512_maskz_rorv_epi64,
        _mm512_maskz_roundscale_pd,
        _mm512_maskz_roundscale_ps,
        _mm512_maskz_roundscale_round_pd,
        _mm512_maskz_roundscale_round_ps,
        _mm512_maskz_rsqrt14_pd,
        _mm512_maskz_rsqrt14_ps,
        _mm512_maskz_scalef_pd,
        _mm512_maskz_scalef_ps,
        _mm512_maskz_scalef_round_pd,
        _mm512_maskz_scalef_round_ps,
        _mm512_maskz_set1_epi32,
        _mm512_maskz_set1_epi64,
        _mm512_maskz_shuffle_epi32,
        _mm512_maskz_shuffle_f32x4,
        _mm512_maskz_shuffle_f64x2,
        _mm512_maskz_shuffle_i32x4,
        _mm512_maskz_shuffle_i64x2,
        _mm512_maskz_shuffle_pd,
        _mm512_maskz_shuffle_ps,
        _mm512_maskz_sll_epi32,
        _mm512_maskz_sll_epi64,
        _mm512_maskz_slli_epi32,
        _mm512_maskz_slli_epi64,
        _mm512_maskz_sllv_epi32,
        _mm512_maskz_sllv_epi64,
        _mm512_maskz_sqrt_pd,
        _mm512_maskz_sqrt_ps,
        _mm512_maskz_sqrt_round_pd,
        _mm512_maskz_sqrt_round_ps,
        _mm512_maskz_sra_epi32,
        _mm512_maskz_sra_epi64,
        _mm512_maskz_srai_epi32,
        _mm512_maskz_srai_epi64,
        _mm512_maskz_srav_epi32,
        _mm512_maskz_srav_epi64,
        _mm512_maskz_srl_epi32,
        _mm512_maskz_srl_epi64,
        _mm512_maskz_srli_epi32,
        _mm512_maskz_srli_epi64,
        _mm512_maskz_srlv_epi32,
        _mm512_maskz_srlv_epi64,
        _mm512_maskz_sub_epi32,
        _mm512_maskz_sub_epi64,
        _mm512_maskz_sub_pd,
        _mm512_maskz_sub_ps,
        _mm512_maskz_sub_round_pd,
        _mm512_maskz_sub_round_ps,
        _mm512_maskz_ternarylogic_epi32,
        _mm512_maskz_ternarylogic_epi64,
        _mm512_maskz_unpackhi_epi32,
        _mm512_maskz_unpackhi_epi64,
        _mm512_maskz_unpackhi_pd,
        _mm512_maskz_unpackhi_ps,
        _mm512_maskz_unpacklo_epi32,
        _mm512_maskz_unpacklo_epi64,
        _mm512_maskz_unpacklo_pd,
        _mm512_maskz_unpacklo_ps,
        _mm512_maskz_xor_epi32,
        _mm512_maskz_xor_epi64,
        _mm512_max_epi32,
        _mm512_max_epi64,
        _mm512_max_epu32,
        _mm512_max_epu64,
        _mm512_max_pd,
        _mm512_max_ps,
        _mm512_max_round_pd,
        _mm512_max_round_ps,
        _mm512_min_epi32,
        _mm512_min_epi64,
        _mm512_min_epu32,
        _mm512_min_epu64,
        _mm512_min_pd,
        _mm512_min_ps,
        _mm512_min_round_pd,
        _mm512_min_round_ps,
        _mm512_movedup_pd,
        _mm512_movehdup_ps,
        _mm512_moveldup_ps,
        _mm512_mul_epi32,
        _mm512_mul_epu32,
        _mm512_mul_pd,
        _mm512_mul_ps,
        _mm512_mul_round_pd,
        _mm512_mul_round_ps,
        _mm512_mullo_epi32,
        _mm512_mullox_epi64,
        _mm512_or_epi32,
        _mm512_or_epi64,
        _mm512_or_si512,
        _mm512_permute_pd,
        _mm512_permute_ps,
        _mm512_permutevar_epi32,
        _mm512_permutevar_pd,
        _mm512_permutevar_ps,
        _mm512_permutex2var_epi32,
        _mm512_permutex2var_epi64,
        _mm512_permutex2var_pd,
        _mm512_permutex2var_ps,
        _mm512_permutex_epi64,
        _mm512_permutex_pd,
        _mm512_permutexvar_epi32,
        _mm512_permutexvar_epi64,
        _mm512_permutexvar_pd,
        _mm512_permutexvar_ps,
        _mm512_rcp14_pd,
        _mm512_rcp14_ps,
        _mm512_reduce_add_epi32,
        _mm512_reduce_add_epi64,
        _mm512_reduce_add_pd,
        _mm512_reduce_add_ps,
        _mm512_reduce_and_epi32,
        _mm512_reduce_and_epi64,
        _mm512_reduce_max_epi32,
        _mm512_reduce_max_epi64,
        _mm512_reduce_max_epu32,
        _mm512_reduce_max_epu64,
        _mm512_reduce_max_pd,
        _mm512_reduce_max_ps,
        _mm512_reduce_min_epi32,
        _mm512_reduce_min_epi64,
        _mm512_reduce_min_epu32,
        _mm512_reduce_min_epu64,
        _mm512_reduce_min_pd,
        _mm512_reduce_min_ps,
        _mm512_reduce_mul_epi32,
        _mm512_reduce_mul_epi64,
        _mm512_reduce_mul_pd,
        _mm512_reduce_mul_ps,
        _mm512_reduce_or_epi32,
        _mm512_reduce_or_epi64,
        _mm512_rol_epi32,
        _mm512_rol_epi64,
        _mm512_rolv_epi32,
        _mm512_rolv_epi64,
        _mm512_ror_epi32,
        _mm512_ror_epi64,
        _mm512_rorv_epi32,
        _mm512_rorv_epi64,
        _mm512_roundscale_pd,
        _mm512_roundscale_ps,
        _mm512_roundscale_round_pd,
        _mm512_roundscale_round_ps,
        _mm512_rsqrt14_pd,
        _mm512_rsqrt14_ps,
        _mm512_scalef_pd,
        _mm512_scalef_ps,
        _mm512_scalef_round_pd,
        _mm512_scalef_round_ps,
        _mm512_set1_epi16,
        _mm512_set1_epi32,
        _mm512_set1_epi64,
        _mm512_set1_epi8,
        _mm512_set1_pd,
        _mm512_set1_ps,
        _mm512_set4_epi32,
        _mm512_set4_epi64,
        _mm512_set4_pd,
        _mm512_set4_ps,
        _mm512_set_epi16,
        _mm512_set_epi32,
        _mm512_set_epi64,
        _mm512_set_epi8,
        _mm512_set_pd,
        _mm512_set_ps,
        _mm512_setr4_epi32,
        _mm512_setr4_epi64,
        _mm512_setr4_pd,
        _mm512_setr4_ps,
        _mm512_setr_epi32,
        _mm512_setr_epi64,
        _mm512_setr_pd,
        _mm512_setr_ps,
        _mm512_setzero,
        _mm512_setzero_epi32,
        _mm512_setzero_pd,
        _mm512_setzero_ps,
        _mm512_setzero_si512,
        _mm512_shuffle_epi32,
        _mm512_shuffle_f32x4,
        _mm512_shuffle_f64x2,
        _mm512_shuffle_i32x4,
        _mm512_shuffle_i64x2,
        _mm512_shuffle_pd,
        _mm512_shuffle_ps,
        _mm512_sll_epi32,
        _mm512_sll_epi64,
        _mm512_slli_epi32,
        _mm512_slli_epi64,
        _mm512_sllv_epi32,
        _mm512_sllv_epi64,
        _mm512_sqrt_pd,
        _mm512_sqrt_ps,
        _mm512_sqrt_round_pd,
        _mm512_sqrt_round_ps,
        _mm512_sra_epi32,
        _mm512_sra_epi64,
        _mm512_srai_epi32,
        _mm512_srai_epi64,
        _mm512_srav_epi32,
        _mm512_srav_epi64,
        _mm512_srl_epi32,
        _mm512_srl_epi64,
        _mm512_srli_epi32,
        _mm512_srli_epi64,
        _mm512_srlv_epi32,
        _mm512_srlv_epi64,
        _mm512_store_epi32,
        _mm512_store_epi64,
        _mm512_store_pd,
        _mm512_store_ps,
        _mm512_store_si512,
        _mm512_storeu_epi32,
        _mm512_storeu_epi64,
        _mm512_storeu_pd,
        _mm512_storeu_ps,
        _mm512_storeu_si512,
        _mm512_stream_load_si512,
        _mm512_stream_pd,
        _mm512_stream_ps,
        _mm512_stream_si512,
        _mm512_sub_epi32,
        _mm512_sub_epi64,
        _mm512_sub_pd,
        _mm512_sub_ps,
        _mm512_sub_round_pd,
        _mm512_sub_round_ps,
        _mm512_ternarylogic_epi32,
        _mm512_ternarylogic_epi64,
        _mm512_test_epi32_mask,
        _mm512_test_epi64_mask,
        _mm512_testn_epi32_mask,
        _mm512_testn_epi64_mask,
        _mm512_undefined,
        _mm512_undefined_epi32,
        _mm512_undefined_pd,
        _mm512_undefined_ps,
        _mm512_unpackhi_epi32,
        _mm512_unpackhi_epi64,
        _mm512_unpackhi_pd,
        _mm512_unpackhi_ps,
        _mm512_unpacklo_epi32,
        _mm512_unpacklo_epi64,
        _mm512_unpacklo_pd,
        _mm512_unpacklo_ps,
        _mm512_xor_epi32,
        _mm512_xor_epi64,
        _mm512_xor_si512,
        _mm512_zextpd128_pd512,
        _mm512_zextpd256_pd512,
        _mm512_zextps128_ps512,
        _mm512_zextps256_ps512,
        _mm512_zextsi128_si512,
        _mm512_zextsi256_si512,
        _mm_abs_epi64,
        _mm_add_round_sd,
        _mm_add_round_ss,
        _mm_alignr_epi32,
        _mm_alignr_epi64,
        _mm_cmp_epi32_mask,
        _mm_cmp_epi64_mask,
        _mm_cmp_epu32_mask,
        _mm_cmp_epu64_mask,
        _mm_cmp_pd_mask,
        _mm_cmp_ps_mask,
        _mm_cmp_round_sd_mask,
        _mm_cmp_round_ss_mask,
        _mm_cmp_sd_mask,
        _mm_cmp_ss_mask,
        _mm_cmpeq_epi32_mask,
        _mm_cmpeq_epi64_mask,
        _mm_cmpeq_epu32_mask,
        _mm_cmpeq_epu64_mask,
        _mm_cmpge_epi32_mask,
        _mm_cmpge_epi64_mask,
        _mm_cmpge_epu32_mask,
        _mm_cmpge_epu64_mask,
        _mm_cmpgt_epi32_mask,
        _mm_cmpgt_epi64_mask,
        _mm_cmpgt_epu32_mask,
        _mm_cmpgt_epu64_mask,
        _mm_cmple_epi32_mask,
        _mm_cmple_epi64_mask,
        _mm_cmple_epu32_mask,
        _mm_cmple_epu64_mask,
        _mm_cmplt_epi32_mask,
        _mm_cmplt_epi64_mask,
        _mm_cmplt_epu32_mask,
        _mm_cmplt_epu64_mask,
        _mm_cmpneq_epi32_mask,
        _mm_cmpneq_epi64_mask,
        _mm_cmpneq_epu32_mask,
        _mm_cmpneq_epu64_mask,
        _mm_comi_round_sd,
        _mm_comi_round_ss,
        _mm_cvt_roundi32_ss,
        _mm_cvt_roundi64_sd,
        _mm_cvt_roundi64_ss,
        _mm_cvt_roundsd_i32,
        _mm_cvt_roundsd_i64,
        _mm_cvt_roundsd_si32,
        _mm_cvt_roundsd_si64,
        _mm_cvt_roundsd_ss,
        _mm_cvt_roundsd_u32,
        _mm_cvt_roundsd_u64,
        _mm_cvt_roundsi32_ss,
        _mm_cvt_roundsi64_sd,
        _mm_cvt_roundsi64_ss,
        _mm_cvt_roundss_i32,
        _mm_cvt_roundss_i64,
        _mm_cvt_roundss_sd,
        _mm_cvt_roundss_si32,
        _mm_cvt_roundss_si64,
        _mm_cvt_roundss_u32,
        _mm_cvt_roundss_u64,
        _mm_cvt_roundu32_ss,
        _mm_cvt_roundu64_sd,
        _mm_cvt_roundu64_ss,
        _mm_cvtepi32_epi16,
        _mm_cvtepi32_epi8,
        _mm_cvtepi64_epi16,
        _mm_cvtepi64_epi32,
        _mm_cvtepi64_epi8,
        _mm_cvtepu32_pd,
        _mm_cvti32_sd,
        _mm_cvti32_ss,
        _mm_cvti64_sd,
        _mm_cvti64_ss,
        _mm_cvtpd_epu32,
        _mm_cvtps_epu32,
        _mm_cvtsd_i32,
        _mm_cvtsd_i64,
        _mm_cvtsd_u32,
        _mm_cvtsd_u64,
        _mm_cvtsepi32_epi16,
        _mm_cvtsepi32_epi8,
        _mm_cvtsepi64_epi16,
        _mm_cvtsepi64_epi32,
        _mm_cvtsepi64_epi8,
        _mm_cvtss_i32,
        _mm_cvtss_i64,
        _mm_cvtss_u32,
        _mm_cvtss_u64,
        _mm_cvtt_roundsd_i32,
        _mm_cvtt_roundsd_i64,
        _mm_cvtt_roundsd_si32,
        _mm_cvtt_roundsd_si64,
        _mm_cvtt_roundsd_u32,
        _mm_cvtt_roundsd_u64,
        _mm_cvtt_roundss_i32,
        _mm_cvtt_roundss_i64,
        _mm_cvtt_roundss_si32,
        _mm_cvtt_roundss_si64,
        _mm_cvtt_roundss_u32,
        _mm_cvtt_roundss_u64,
        _mm_cvttpd_epu32,
        _mm_cvttps_epu32,
        _mm_cvttsd_i32,
        _mm_cvttsd_i64,
        _mm_cvttsd_u32,
        _mm_cvttsd_u64,
        _mm_cvttss_i32,
        _mm_cvttss_i64,
        _mm_cvttss_u32,
        _mm_cvttss_u64,
        _mm_cvtu32_sd,
        _mm_cvtu32_ss,
        _mm_cvtu64_sd,
        _mm_cvtu64_ss,
        _mm_cvtusepi32_epi16,
        _mm_cvtusepi32_epi8,
        _mm_cvtusepi64_epi16,
        _mm_cvtusepi64_epi32,
        _mm_cvtusepi64_epi8,
        _mm_div_round_sd,
        _mm_div_round_ss,
        _mm_fixupimm_pd,
        _mm_fixupimm_ps,
        _mm_fixupimm_round_sd,
        _mm_fixupimm_round_ss,
        _mm_fixupimm_sd,
        _mm_fixupimm_ss,
        _mm_fmadd_round_sd,
        _mm_fmadd_round_ss,
        _mm_fmsub_round_sd,
        _mm_fmsub_round_ss,
        _mm_fnmadd_round_sd,
        _mm_fnmadd_round_ss,
        _mm_fnmsub_round_sd,
        _mm_fnmsub_round_ss,
        _mm_getexp_pd,
        _mm_getexp_ps,
        _mm_getexp_round_sd,
        _mm_getexp_round_ss,
        _mm_getexp_sd,
        _mm_getexp_ss,
        _mm_getmant_pd,
        _mm_getmant_ps,
        _mm_getmant_round_sd,
        _mm_getmant_round_ss,
        _mm_getmant_sd,
        _mm_getmant_ss,
        _mm_i32scatter_epi32,
        _mm_i32scatter_epi64,
        _mm_i32scatter_pd,
        _mm_i32scatter_ps,
        _mm_i64scatter_epi32,
        _mm_i64scatter_epi64,
        _mm_i64scatter_pd,
        _mm_i64scatter_ps,
        _mm_load_epi32,
        _mm_load_epi64,
        _mm_loadu_epi32,
        _mm_loadu_epi64,
        _mm_mask2_permutex2var_epi32,
        _mm_mask2_permutex2var_epi64,
        _mm_mask2_permutex2var_pd,
        _mm_mask2_permutex2var_ps,
        _mm_mask3_fmadd_pd,
        _mm_mask3_fmadd_ps,
        _mm_mask3_fmadd_round_sd,
        _mm_mask3_fmadd_round_ss,
        _mm_mask3_fmadd_sd,
        _mm_mask3_fmadd_ss,
        _mm_mask3_fmaddsub_pd,
        _mm_mask3_fmaddsub_ps,
        _mm_mask3_fmsub_pd,
        _mm_mask3_fmsub_ps,
        _mm_mask3_fmsub_round_sd,
        _mm_mask3_fmsub_round_ss,
        _mm_mask3_fmsub_sd,
        _mm_mask3_fmsub_ss,
        _mm_mask3_fmsubadd_pd,
        _mm_mask3_fmsubadd_ps,
        _mm_mask3_fnmadd_pd,
        _mm_mask3_fnmadd_ps,
        _mm_mask3_fnmadd_round_sd,
        _mm_mask3_fnmadd_round_ss,
        _mm_mask3_fnmadd_sd,
        _mm_mask3_fnmadd_ss,
        _mm_mask3_fnmsub_pd,
        _mm_mask3_fnmsub_ps,
        _mm_mask3_fnmsub_round_sd,
        _mm_mask3_fnmsub_round_ss,
        _mm_mask3_fnmsub_sd,
        _mm_mask3_fnmsub_ss,
        _mm_mask_abs_epi32,
        _mm_mask_abs_epi64,
        _mm_mask_add_epi32,
        _mm_mask_add_epi64,
        _mm_mask_add_pd,
        _mm_mask_add_ps,
        _mm_mask_add_round_sd,
        _mm_mask_add_round_ss,
        _mm_mask_add_sd,
        _mm_mask_add_ss,
        _mm_mask_alignr_epi32,
        _mm_mask_alignr_epi64,
        _mm_mask_and_epi32,
        _mm_mask_and_epi64,
        _mm_mask_andnot_epi32,
        _mm_mask_andnot_epi64,
        _mm_mask_blend_epi32,
        _mm_mask_blend_epi64,
        _mm_mask_blend_pd,
        _mm_mask_blend_ps,
        _mm_mask_broadcastd_epi32,
        _mm_mask_broadcastq_epi64,
        _mm_mask_broadcastss_ps,
        _mm_mask_cmp_epi32_mask,
        _mm_mask_cmp_epi64_mask,
        _mm_mask_cmp_epu32_mask,
        _mm_mask_cmp_epu64_mask,
        _mm_mask_cmp_pd_mask,
        _mm_mask_cmp_ps_mask,
        _mm_mask_cmp_round_sd_mask,
        _mm_mask_cmp_round_ss_mask,
        _mm_mask_cmp_sd_mask,
        _mm_mask_cmp_ss_mask,
        _mm_mask_cmpeq_epi32_mask,
        _mm_mask_cmpeq_epi64_mask,
        _mm_mask_cmpeq_epu32_mask,
        _mm_mask_cmpeq_epu64_mask,
        _mm_mask_cmpge_epi32_mask,
        _mm_mask_cmpge_epi64_mask,
        _mm_mask_cmpge_epu32_mask,
        _mm_mask_cmpge_epu64_mask,
        _mm_mask_cmpgt_epi32_mask,
        _mm_mask_cmpgt_epi64_mask,
        _mm_mask_cmpgt_epu32_mask,
        _mm_mask_cmpgt_epu64_mask,
        _mm_mask_cmple_epi32_mask,
        _mm_mask_cmple_epi64_mask,
        _mm_mask_cmple_epu32_mask,
        _mm_mask_cmple_epu64_mask,
        _mm_mask_cmplt_epi32_mask,
        _mm_mask_cmplt_epi64_mask,
        _mm_mask_cmplt_epu32_mask,
        _mm_mask_cmplt_epu64_mask,
        _mm_mask_cmpneq_epi32_mask,
        _mm_mask_cmpneq_epi64_mask,
        _mm_mask_cmpneq_epu32_mask,
        _mm_mask_cmpneq_epu64_mask,
        _mm_mask_compress_epi32,
        _mm_mask_compress_epi64,
        _mm_mask_compress_pd,
        _mm_mask_compress_ps,
        _mm_mask_compressstoreu_epi32,
        _mm_mask_compressstoreu_epi64,
        _mm_mask_compressstoreu_pd,
        _mm_mask_compressstoreu_ps,
        _mm_mask_cvt_roundps_ph,
        _mm_mask_cvt_roundsd_ss,
        _mm_mask_cvt_roundss_sd,
        _mm_mask_cvtepi16_epi32,
        _mm_mask_cvtepi16_epi64,
        _mm_mask_cvtepi32_epi16,
        _mm_mask_cvtepi32_epi64,
        _mm_mask_cvtepi32_epi8,
        _mm_mask_cvtepi32_pd,
        _mm_mask_cvtepi32_ps,
        _mm_mask_cvtepi32_storeu_epi16,
        _mm_mask_cvtepi32_storeu_epi8,
        _mm_mask_cvtepi64_epi16,
        _mm_mask_cvtepi64_epi32,
        _mm_mask_cvtepi64_epi8,
        _mm_mask_cvtepi64_storeu_epi16,
        _mm_mask_cvtepi64_storeu_epi32,
        _mm_mask_cvtepi64_storeu_epi8,
        _mm_mask_cvtepi8_epi32,
        _mm_mask_cvtepi8_epi64,
        _mm_mask_cvtepu16_epi32,
        _mm_mask_cvtepu16_epi64,
        _mm_mask_cvtepu32_epi64,
        _mm_mask_cvtepu32_pd,
        _mm_mask_cvtepu8_epi32,
        _mm_mask_cvtepu8_epi64,
        _mm_mask_cvtpd_epi32,
        _mm_mask_cvtpd_epu32,
        _mm_mask_cvtpd_ps,
        _mm_mask_cvtph_ps,
        _mm_mask_cvtps_epi32,
        _mm_mask_cvtps_epu32,
        _mm_mask_cvtps_ph,
        _mm_mask_cvtsd_ss,
        _mm_mask_cvtsepi32_epi16,
        _mm_mask_cvtsepi32_epi8,
        _mm_mask_cvtsepi32_storeu_epi16,
        _mm_mask_cvtsepi32_storeu_epi8,
        _mm_mask_cvtsepi64_epi16,
        _mm_mask_cvtsepi64_epi32,
        _mm_mask_cvtsepi64_epi8,
        _mm_mask_cvtsepi64_storeu_epi16,
        _mm_mask_cvtsepi64_storeu_epi32,
        _mm_mask_cvtsepi64_storeu_epi8,
        _mm_mask_cvtss_sd,
        _mm_mask_cvttpd_epi32,
        _mm_mask_cvttpd_epu32,
        _mm_mask_cvttps_epi32,
        _mm_mask_cvttps_epu32,
        _mm_mask_cvtusepi32_epi16,
        _mm_mask_cvtusepi32_epi8,
        _mm_mask_cvtusepi32_storeu_epi16,
        _mm_mask_cvtusepi32_storeu_epi8,
        _mm_mask_cvtusepi64_epi16,
        _mm_mask_cvtusepi64_epi32,
        _mm_mask_cvtusepi64_epi8,
        _mm_mask_cvtusepi64_storeu_epi16,
        _mm_mask_cvtusepi64_storeu_epi32,
        _mm_mask_cvtusepi64_storeu_epi8,
        _mm_mask_div_pd,
        _mm_mask_div_ps,
        _mm_mask_div_round_sd,
        _mm_mask_div_round_ss,
        _mm_mask_div_sd,
        _mm_mask_div_ss,
        _mm_mask_expand_epi32,
        _mm_mask_expand_epi64,
        _mm_mask_expand_pd,
        _mm_mask_expand_ps,
        _mm_mask_expandloadu_epi32,
        _mm_mask_expandloadu_epi64,
        _mm_mask_expandloadu_pd,
        _mm_mask_expandloadu_ps,
        _mm_mask_fixupimm_pd,
        _mm_mask_fixupimm_ps,
        _mm_mask_fixupimm_round_sd,
        _mm_mask_fixupimm_round_ss,
        _mm_mask_fixupimm_sd,
        _mm_mask_fixupimm_ss,
        _mm_mask_fmadd_pd,
        _mm_mask_fmadd_ps,
        _mm_mask_fmadd_round_sd,
        _mm_mask_fmadd_round_ss,
        _mm_mask_fmadd_sd,
        _mm_mask_fmadd_ss,
        _mm_mask_fmaddsub_pd,
        _mm_mask_fmaddsub_ps,
        _mm_mask_fmsub_pd,
        _mm_mask_fmsub_ps,
        _mm_mask_fmsub_round_sd,
        _mm_mask_fmsub_round_ss,
        _mm_mask_fmsub_sd,
        _mm_mask_fmsub_ss,
        _mm_mask_fmsubadd_pd,
        _mm_mask_fmsubadd_ps,
        _mm_mask_fnmadd_pd,
        _mm_mask_fnmadd_ps,
        _mm_mask_fnmadd_round_sd,
        _mm_mask_fnmadd_round_ss,
        _mm_mask_fnmadd_sd,
        _mm_mask_fnmadd_ss,
        _mm_mask_fnmsub_pd,
        _mm_mask_fnmsub_ps,
        _mm_mask_fnmsub_round_sd,
        _mm_mask_fnmsub_round_ss,
        _mm_mask_fnmsub_sd,
        _mm_mask_fnmsub_ss,
        _mm_mask_getexp_pd,
        _mm_mask_getexp_ps,
        _mm_mask_getexp_round_sd,
        _mm_mask_getexp_round_ss,
        _mm_mask_getexp_sd,
        _mm_mask_getexp_ss,
        _mm_mask_getmant_pd,
        _mm_mask_getmant_ps,
        _mm_mask_getmant_round_sd,
        _mm_mask_getmant_round_ss,
        _mm_mask_getmant_sd,
        _mm_mask_getmant_ss,
        _mm_mask_i32scatter_epi32,
        _mm_mask_i32scatter_epi64,
        _mm_mask_i32scatter_pd,
        _mm_mask_i32scatter_ps,
        _mm_mask_i64scatter_epi32,
        _mm_mask_i64scatter_epi64,
        _mm_mask_i64scatter_pd,
        _mm_mask_i64scatter_ps,
        _mm_mask_load_epi32,
        _mm_mask_load_epi64,
        _mm_mask_load_pd,
        _mm_mask_load_ps,
        _mm_mask_load_sd,
        _mm_mask_load_ss,
        _mm_mask_loadu_epi32,
        _mm_mask_loadu_epi64,
        _mm_mask_loadu_pd,
        _mm_mask_loadu_ps,
        _mm_mask_max_epi32,
        _mm_mask_max_epi64,
        _mm_mask_max_epu32,
        _mm_mask_max_epu64,
        _mm_mask_max_pd,
        _mm_mask_max_ps,
        _mm_mask_max_round_sd,
        _mm_mask_max_round_ss,
        _mm_mask_max_sd,
        _mm_mask_max_ss,
        _mm_mask_min_epi32,
        _mm_mask_min_epi64,
        _mm_mask_min_epu32,
        _mm_mask_min_epu64,
        _mm_mask_min_pd,
        _mm_mask_min_ps,
        _mm_mask_min_round_sd,
        _mm_mask_min_round_ss,
        _mm_mask_min_sd,
        _mm_mask_min_ss,
        _mm_mask_mov_epi32,
        _mm_mask_mov_epi64,
        _mm_mask_mov_pd,
        _mm_mask_mov_ps,
        _mm_mask_move_sd,
        _mm_mask_move_ss,
        _mm_mask_movedup_pd,
        _mm_mask_movehdup_ps,
        _mm_mask_moveldup_ps,
        _mm_mask_mul_epi32,
        _mm_mask_mul_epu32,
        _mm_mask_mul_pd,
        _mm_mask_mul_ps,
        _mm_mask_mul_round_sd,
        _mm_mask_mul_round_ss,
        _mm_mask_mul_sd,
        _mm_mask_mul_ss,
        _mm_mask_mullo_epi32,
        _mm_mask_or_epi32,
        _mm_mask_or_epi64,
        _mm_mask_permute_pd,
        _mm_mask_permute_ps,
        _mm_mask_permutevar_pd,
        _mm_mask_permutevar_ps,
        _mm_mask_permutex2var_epi32,
        _mm_mask_permutex2var_epi64,
        _mm_mask_permutex2var_pd,
        _mm_mask_permutex2var_ps,
        _mm_mask_rcp14_pd,
        _mm_mask_rcp14_ps,
        _mm_mask_rcp14_sd,
        _mm_mask_rcp14_ss,
        _mm_mask_rol_epi32,
        _mm_mask_rol_epi64,
        _mm_mask_rolv_epi32,
        _mm_mask_rolv_epi64,
        _mm_mask_ror_epi32,
        _mm_mask_ror_epi64,
        _mm_mask_rorv_epi32,
        _mm_mask_rorv_epi64,
        _mm_mask_roundscale_pd,
        _mm_mask_roundscale_ps,
        _mm_mask_roundscale_round_sd,
        _mm_mask_roundscale_round_ss,
        _mm_mask_roundscale_sd,
        _mm_mask_roundscale_ss,
        _mm_mask_rsqrt14_pd,
        _mm_mask_rsqrt14_ps,
        _mm_mask_rsqrt14_sd,
        _mm_mask_rsqrt14_ss,
        _mm_mask_scalef_pd,
        _mm_mask_scalef_ps,
        _mm_mask_scalef_round_sd,
        _mm_mask_scalef_round_ss,
        _mm_mask_scalef_sd,
        _mm_mask_scalef_ss,
        _mm_mask_set1_epi32,
        _mm_mask_set1_epi64,
        _mm_mask_shuffle_epi32,
        _mm_mask_shuffle_pd,
        _mm_mask_shuffle_ps,
        _mm_mask_sll_epi32,
        _mm_mask_sll_epi64,
        _mm_mask_slli_epi32,
        _mm_mask_slli_epi64,
        _mm_mask_sllv_epi32,
        _mm_mask_sllv_epi64,
        _mm_mask_sqrt_pd,
        _mm_mask_sqrt_ps,
        _mm_mask_sqrt_round_sd,
        _mm_mask_sqrt_round_ss,
        _mm_mask_sqrt_sd,
        _mm_mask_sqrt_ss,
        _mm_mask_sra_epi32,
        _mm_mask_sra_epi64,
        _mm_mask_srai_epi32,
        _mm_mask_srai_epi64,
        _mm_mask_srav_epi32,
        _mm_mask_srav_epi64,
        _mm_mask_srl_epi32,
        _mm_mask_srl_epi64,
        _mm_mask_srli_epi32,
        _mm_mask_srli_epi64,
        _mm_mask_srlv_epi32,
        _mm_mask_srlv_epi64,
        _mm_mask_store_epi32,
        _mm_mask_store_epi64,
        _mm_mask_store_pd,
        _mm_mask_store_ps,
        _mm_mask_store_sd,
        _mm_mask_store_ss,
        _mm_mask_storeu_epi32,
        _mm_mask_storeu_epi64,
        _mm_mask_storeu_pd,
        _mm_mask_storeu_ps,
        _mm_mask_sub_epi32,
        _mm_mask_sub_epi64,
        _mm_mask_sub_pd,
        _mm_mask_sub_ps,
        _mm_mask_sub_round_sd,
        _mm_mask_sub_round_ss,
        _mm_mask_sub_sd,
        _mm_mask_sub_ss,
        _mm_mask_ternarylogic_epi32,
        _mm_mask_ternarylogic_epi64,
        _mm_mask_test_epi32_mask,
        _mm_mask_test_epi64_mask,
        _mm_mask_testn_epi32_mask,
        _mm_mask_testn_epi64_mask,
        _mm_mask_unpackhi_epi32,
        _mm_mask_unpackhi_epi64,
        _mm_mask_unpackhi_pd,
        _mm_mask_unpackhi_ps,
        _mm_mask_unpacklo_epi32,
        _mm_mask_unpacklo_epi64,
        _mm_mask_unpacklo_pd,
        _mm_mask_unpacklo_ps,
        _mm_mask_xor_epi32,
        _mm_mask_xor_epi64,
        _mm_maskz_abs_epi32,
        _mm_maskz_abs_epi64,
        _mm_maskz_add_epi32,
        _mm_maskz_add_epi64,
        _mm_maskz_add_pd,
        _mm_maskz_add_ps,
        _mm_maskz_add_round_sd,
        _mm_maskz_add_round_ss,
        _mm_maskz_add_sd,
        _mm_maskz_add_ss,
        _mm_maskz_alignr_epi32,
        _mm_maskz_alignr_epi64,
        _mm_maskz_and_epi32,
        _mm_maskz_and_epi64,
        _mm_maskz_andnot_epi32,
        _mm_maskz_andnot_epi64,
        _mm_maskz_broadcastd_epi32,
        _mm_maskz_broadcastq_epi64,
        _mm_maskz_broadcastss_ps,
        _mm_maskz_compress_epi32,
        _mm_maskz_compress_epi64,
        _mm_maskz_compress_pd,
        _mm_maskz_compress_ps,
        _mm_maskz_cvt_roundps_ph,
        _mm_maskz_cvt_roundsd_ss,
        _mm_maskz_cvt_roundss_sd,
        _mm_maskz_cvtepi16_epi32,
        _mm_maskz_cvtepi16_epi64,
        _mm_maskz_cvtepi32_epi16,
        _mm_maskz_cvtepi32_epi64,
        _mm_maskz_cvtepi32_epi8,
        _mm_maskz_cvtepi32_pd,
        _mm_maskz_cvtepi32_ps,
        _mm_maskz_cvtepi64_epi16,
        _mm_maskz_cvtepi64_epi32,
        _mm_maskz_cvtepi64_epi8,
        _mm_maskz_cvtepi8_epi32,
        _mm_maskz_cvtepi8_epi64,
        _mm_maskz_cvtepu16_epi32,
        _mm_maskz_cvtepu16_epi64,
        _mm_maskz_cvtepu32_epi64,
        _mm_maskz_cvtepu32_pd,
        _mm_maskz_cvtepu8_epi32,
        _mm_maskz_cvtepu8_epi64,
        _mm_maskz_cvtpd_epi32,
        _mm_maskz_cvtpd_epu32,
        _mm_maskz_cvtpd_ps,
        _mm_maskz_cvtph_ps,
        _mm_maskz_cvtps_epi32,
        _mm_maskz_cvtps_epu32,
        _mm_maskz_cvtps_ph,
        _mm_maskz_cvtsd_ss,
        _mm_maskz_cvtsepi32_epi16,
        _mm_maskz_cvtsepi32_epi8,
        _mm_maskz_cvtsepi64_epi16,
        _mm_maskz_cvtsepi64_epi32,
        _mm_maskz_cvtsepi64_epi8,
        _mm_maskz_cvtss_sd,
        _mm_maskz_cvttpd_epi32,
        _mm_maskz_cvttpd_epu32,
        _mm_maskz_cvttps_epi32,
        _mm_maskz_cvttps_epu32,
        _mm_maskz_cvtusepi32_epi16,
        _mm_maskz_cvtusepi32_epi8,
        _mm_maskz_cvtusepi64_epi16,
        _mm_maskz_cvtusepi64_epi32,
        _mm_maskz_cvtusepi64_epi8,
        _mm_maskz_div_pd,
        _mm_maskz_div_ps,
        _mm_maskz_div_round_sd,
        _mm_maskz_div_round_ss,
        _mm_maskz_div_sd,
        _mm_maskz_div_ss,
        _mm_maskz_expand_epi32,
        _mm_maskz_expand_epi64,
        _mm_maskz_expand_pd,
        _mm_maskz_expand_ps,
        _mm_maskz_expandloadu_epi32,
        _mm_maskz_expandloadu_epi64,
        _mm_maskz_expandloadu_pd,
        _mm_maskz_expandloadu_ps,
        _mm_maskz_fixupimm_pd,
        _mm_maskz_fixupimm_ps,
        _mm_maskz_fixupimm_round_sd,
        _mm_maskz_fixupimm_round_ss,
        _mm_maskz_fixupimm_sd,
        _mm_maskz_fixupimm_ss,
        _mm_maskz_fmadd_pd,
        _mm_maskz_fmadd_ps,
        _mm_maskz_fmadd_round_sd,
        _mm_maskz_fmadd_round_ss,
        _mm_maskz_fmadd_sd,
        _mm_maskz_fmadd_ss,
        _mm_maskz_fmaddsub_pd,
        _mm_maskz_fmaddsub_ps,
        _mm_maskz_fmsub_pd,
        _mm_maskz_fmsub_ps,
        _mm_maskz_fmsub_round_sd,
        _mm_maskz_fmsub_round_ss,
        _mm_maskz_fmsub_sd,
        _mm_maskz_fmsub_ss,
        _mm_maskz_fmsubadd_pd,
        _mm_maskz_fmsubadd_ps,
        _mm_maskz_fnmadd_pd,
        _mm_maskz_fnmadd_ps,
        _mm_maskz_fnmadd_round_sd,
        _mm_maskz_fnmadd_round_ss,
        _mm_maskz_fnmadd_sd,
        _mm_maskz_fnmadd_ss,
        _mm_maskz_fnmsub_pd,
        _mm_maskz_fnmsub_ps,
        _mm_maskz_fnmsub_round_sd,
        _mm_maskz_fnmsub_round_ss,
        _mm_maskz_fnmsub_sd,
        _mm_maskz_fnmsub_ss,
        _mm_maskz_getexp_pd,
        _mm_maskz_getexp_ps,
        _mm_maskz_getexp_round_sd,
        _mm_maskz_getexp_round_ss,
        _mm_maskz_getexp_sd,
        _mm_maskz_getexp_ss,
        _mm_maskz_getmant_pd,
        _mm_maskz_getmant_ps,
        _mm_maskz_getmant_round_sd,
        _mm_maskz_getmant_round_ss,
        _mm_maskz_getmant_sd,
        _mm_maskz_getmant_ss,
        _mm_maskz_load_epi32,
        _mm_maskz_load_epi64,
        _mm_maskz_load_pd,
        _mm_maskz_load_ps,
        _mm_maskz_load_sd,
        _mm_maskz_load_ss,
        _mm_maskz_loadu_epi32,
        _mm_maskz_loadu_epi64,
        _mm_maskz_loadu_pd,
        _mm_maskz_loadu_ps,
        _mm_maskz_max_epi32,
        _mm_maskz_max_epi64,
        _mm_maskz_max_epu32,
        _mm_maskz_max_epu64,
        _mm_maskz_max_pd,
        _mm_maskz_max_ps,
        _mm_maskz_max_round_sd,
        _mm_maskz_max_round_ss,
        _mm_maskz_max_sd,
        _mm_maskz_max_ss,
        _mm_maskz_min_epi32,
        _mm_maskz_min_epi64,
        _mm_maskz_min_epu32,
        _mm_maskz_min_epu64,
        _mm_maskz_min_pd,
        _mm_maskz_min_ps,
        _mm_maskz_min_round_sd,
        _mm_maskz_min_round_ss,
        _mm_maskz_min_sd,
        _mm_maskz_min_ss,
        _mm_maskz_mov_epi32,
        _mm_maskz_mov_epi64,
        _mm_maskz_mov_pd,
        _mm_maskz_mov_ps,
        _mm_maskz_move_sd,
        _mm_maskz_move_ss,
        _mm_maskz_movedup_pd,
        _mm_maskz_movehdup_ps,
        _mm_maskz_moveldup_ps,
        _mm_maskz_mul_epi32,
        _mm_maskz_mul_epu32,
        _mm_maskz_mul_pd,
        _mm_maskz_mul_ps,
        _mm_maskz_mul_round_sd,
        _mm_maskz_mul_round_ss,
        _mm_maskz_mul_sd,
        _mm_maskz_mul_ss,
        _mm_maskz_mullo_epi32,
        _mm_maskz_or_epi32,
        _mm_maskz_or_epi64,
        _mm_maskz_permute_pd,
        _mm_maskz_permute_ps,
        _mm_maskz_permutevar_pd,
        _mm_maskz_permutevar_ps,
        _mm_maskz_permutex2var_epi32,
        _mm_maskz_permutex2var_epi64,
        _mm_maskz_permutex2var_pd,
        _mm_maskz_permutex2var_ps,
        _mm_maskz_rcp14_pd,
        _mm_maskz_rcp14_ps,
        _mm_maskz_rcp14_sd,
        _mm_maskz_rcp14_ss,
        _mm_maskz_rol_epi32,
        _mm_maskz_rol_epi64,
        _mm_maskz_rolv_epi32,
        _mm_maskz_rolv_epi64,
        _mm_maskz_ror_epi32,
        _mm_maskz_ror_epi64,
        _mm_maskz_rorv_epi32,
        _mm_maskz_rorv_epi64,
        _mm_maskz_roundscale_pd,
        _mm_maskz_roundscale_ps,
        _mm_maskz_roundscale_round_sd,
        _mm_maskz_roundscale_round_ss,
        _mm_maskz_roundscale_sd,
        _mm_maskz_roundscale_ss,
        _mm_maskz_rsqrt14_pd,
        _mm_maskz_rsqrt14_ps,
        _mm_maskz_rsqrt14_sd,
        _mm_maskz_rsqrt14_ss,
        _mm_maskz_scalef_pd,
        _mm_maskz_scalef_ps,
        _mm_maskz_scalef_round_sd,
        _mm_maskz_scalef_round_ss,
        _mm_maskz_scalef_sd,
        _mm_maskz_scalef_ss,
        _mm_maskz_set1_epi32,
        _mm_maskz_set1_epi64,
        _mm_maskz_shuffle_epi32,
        _mm_maskz_shuffle_pd,
        _mm_maskz_shuffle_ps,
        _mm_maskz_sll_epi32,
        _mm_maskz_sll_epi64,
        _mm_maskz_slli_epi32,
        _mm_maskz_slli_epi64,
        _mm_maskz_sllv_epi32,
        _mm_maskz_sllv_epi64,
        _mm_maskz_sqrt_pd,
        _mm_maskz_sqrt_ps,
        _mm_maskz_sqrt_round_sd,
        _mm_maskz_sqrt_round_ss,
        _mm_maskz_sqrt_sd,
        _mm_maskz_sqrt_ss,
        _mm_maskz_sra_epi32,
        _mm_maskz_sra_epi64,
        _mm_maskz_srai_epi32,
        _mm_maskz_srai_epi64,
        _mm_maskz_srav_epi32,
        _mm_maskz_srav_epi64,
        _mm_maskz_srl_epi32,
        _mm_maskz_srl_epi64,
        _mm_maskz_srli_epi32,
        _mm_maskz_srli_epi64,
        _mm_maskz_srlv_epi32,
        _mm_maskz_srlv_epi64,
        _mm_maskz_sub_epi32,
        _mm_maskz_sub_epi64,
        _mm_maskz_sub_pd,
        _mm_maskz_sub_ps,
        _mm_maskz_sub_round_sd,
        _mm_maskz_sub_round_ss,
        _mm_maskz_sub_sd,
        _mm_maskz_sub_ss,
        _mm_maskz_ternarylogic_epi32,
        _mm_maskz_ternarylogic_epi64,
        _mm_maskz_unpackhi_epi32,
        _mm_maskz_unpackhi_epi64,
        _mm_maskz_unpackhi_pd,
        _mm_maskz_unpackhi_ps,
        _mm_maskz_unpacklo_epi32,
        _mm_maskz_unpacklo_epi64,
        _mm_maskz_unpacklo_pd,
        _mm_maskz_unpacklo_ps,
        _mm_maskz_xor_epi32,
        _mm_maskz_xor_epi64,
        _mm_max_epi64,
        _mm_max_epu64,
        _mm_max_round_sd,
        _mm_max_round_ss,
        _mm_min_epi64,
        _mm_min_epu64,
        _mm_min_round_sd,
        _mm_min_round_ss,
        _mm_mmask_i32gather_epi32,
        _mm_mmask_i32gather_epi64,
        _mm_mmask_i32gather_pd,
        _mm_mmask_i32gather_ps,
        _mm_mmask_i64gather_epi32,
        _mm_mmask_i64gather_epi64,
        _mm_mmask_i64gather_pd,
        _mm_mmask_i64gather_ps,
        _mm_mul_round_sd,
        _mm_mul_round_ss,
        _mm_or_epi32,
        _mm_or_epi64,
        _mm_permutex2var_epi32,
        _mm_permutex2var_epi64,
        _mm_permutex2var_pd,
        _mm_permutex2var_ps,
        _mm_rcp14_pd,
        _mm_rcp14_ps,
        _mm_rcp14_sd,
        _mm_rcp14_ss,
        _mm_rol_epi32,
        _mm_rol_epi64,
        _mm_rolv_epi32,
        _mm_rolv_epi64,
        _mm_ror_epi32,
        _mm_ror_epi64,
        _mm_rorv_epi32,
        _mm_rorv_epi64,
        _mm_roundscale_pd,
        _mm_roundscale_ps,
        _mm_roundscale_round_sd,
        _mm_roundscale_round_ss,
        _mm_roundscale_sd,
        _mm_roundscale_ss,
        _mm_rsqrt14_pd,
        _mm_rsqrt14_ps,
        _mm_rsqrt14_sd,
        _mm_rsqrt14_ss,
        _mm_scalef_pd,
        _mm_scalef_ps,
        _mm_scalef_round_sd,
        _mm_scalef_round_ss,
        _mm_scalef_sd,
        _mm_scalef_ss,
        _mm_sqrt_round_sd,
        _mm_sqrt_round_ss,
        _mm_sra_epi64,
        _mm_srai_epi64,
        _mm_srav_epi64,
        _mm_store_epi32,
        _mm_store_epi64,
        _mm_storeu_epi32,
        _mm_storeu_epi64,
        _mm_sub_round_sd,
        _mm_sub_round_ss,
        _mm_ternarylogic_epi32,
        _mm_ternarylogic_epi64,
        _mm_test_epi32_mask,
        _mm_test_epi64_mask,
        _mm_testn_epi32_mask,
        _mm_testn_epi64_mask,
        _mm_xor_epi32,
        _mm_xor_epi64,
    }
}