thermite 0.2.1

High-performance, generic, ISA-portable SIMD library with a policy-configurable transcendental math library
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

use generic_array::{
    GenericArray,
    typenum::{self, Unsigned},
};

use crate::{
    isa::InstructionSet,
    register::{
        BitwiseRegister, CastMaskRegister, CoreRegister, FloatRegister, InterleaveRegister, MaskElement, MaskRegister,
        NativeCapability, NumericRegister, PartialOrdRegister, PermuteRegister, Register, ShuffleRegister,
        SignedRegister, Storage, ZeroUpper, empty_reg, reg,
    },
};

use super::arch;

#[cfg_attr(not(feature = "document_registers"), doc(hidden))]
#[derive(Debug, Clone, Copy, Hash)]
pub struct F64x2Neon;

neon_mask_core!(
    F64x2Neon, lanes: 2(typenum::U2), storage: float64x2_t, suffix: f64,
    truthy: f64::from_bits(!0), from_u: vreinterpretq_f64_u64
);

neon_register!(
    F64x2Neon, elem: f64, lanes: 2, suffix: f64, vec: float64x2,
    signed: super::I64x2Neon, unsigned: super::U64x2Neon,
    compress: table, bytes: (vreinterpretq_u8_f64, vreinterpretq_f64_u8)
);

neon_partial_ord!(F64x2Neon, suffix: f64, from_u: vreinterpretq_f64_u64);

neon_shuffle_permute!(F64x2Neon, suffix: f64, from_u: vreinterpretq_f64_u64; 2);

neon_float_register!(
    F64x2Neon, elem: f64, lanes: 2, suffix: f64, from_u: vreinterpretq_f64_u64,
    bits: super::U64x2Neon, signed_bits: super::I64x2Neon,
    extended: Self,
    exp_mask: 0x7FF0_0000_0000_0000, approx: no
);

neon_concat_scalar2!(F64x2Neon, elem: f64, suffix: f64);
neon_extend_scalar!(F64x2Neon, elem: f64);