ternlang-hdl-0.1.0
Platform
Feature flags

docs.rs

Rust

ternlang-hdl 0.1.0

Verilog-2001 codegen for balanced ternary — BET processor primitives, sparse matmul array, FPGA simulation wrapper.

Crate
Source
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src
synth
.cargo_vcs_info.json
Cargo.lock
Cargo.toml
Cargo.toml.orig
LICENSE