systile 0.7.0

A TPU-native tiled tensor data structure: the Systolic Tile Lattice. Padding-aware, sublane/lane laid out, bf16/int8 first, with a CPU reference simulator of systolic dataflow.
Documentation 
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# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 3

[[package]]
name = "systile"
version = "0.7.0"