system_rust 0.2.15

This is a hardware simulation framework inspired by SystemC for Rust. It features multithreading with a sender-receiver architecture, 4-state logic types, and logging functionality.
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@startuml
interface ModuleInterface
ModuleInterface : fn new() -> Self

interface ComputeModule
ComputeModule : fn compute(&self)
ComputeModule : fn sensitivity_list(&self) -> Vec<u128>

interface CompositeModule
CompositeModule : fn build(&self, sim: &SimulationContext)

struct Module
Module : Arc<ComputeModule> value
Module : u128 id
Module : fn new<T: ComputeModule + 'static>(module: T) -> Self
Module : fn id(&self) -> u128
Module : fn compute(&self)
Module : fn sensitivity_list(&self) -> Vec<u128>

ComputeModule <|-- ModuleInterface
CompositeModule <|-- ModuleInterface
Module *-- ComputeModule
@enduml