swm341_pac/i2c0/
clk.rs

1#[doc = "Register `CLK` reader"]
2pub struct R(crate::R<CLK_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLK_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLK_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLK_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLK` writer"]
17pub struct W(crate::W<CLK_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLK_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLK_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLK_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SCLL` reader - SCLL field"]
38pub type SCLL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SCLL` writer - SCLL field"]
40pub type SCLL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u8, u8, 8, O>;
41#[doc = "Field `SCLH` reader - SCLH field"]
42pub type SCLH_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `SCLH` writer - SCLH field"]
44pub type SCLH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u8, u8, 8, O>;
45#[doc = "Field `DIV` reader - DIV field"]
46pub type DIV_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `DIV` writer - DIV field"]
48pub type DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u8, u8, 8, O>;
49#[doc = "Field `SDAH` reader - SDAH field"]
50pub type SDAH_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `SDAH` writer - SDAH field"]
52pub type SDAH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u8, u8, 4, O>;
53impl R {
54    #[doc = "Bits 0:7 - SCLL field"]
55    #[inline(always)]
56    pub fn scll(&self) -> SCLL_R {
57        SCLL_R::new((self.bits & 0xff) as u8)
58    }
59    #[doc = "Bits 8:15 - SCLH field"]
60    #[inline(always)]
61    pub fn sclh(&self) -> SCLH_R {
62        SCLH_R::new(((self.bits >> 8) & 0xff) as u8)
63    }
64    #[doc = "Bits 16:23 - DIV field"]
65    #[inline(always)]
66    pub fn div(&self) -> DIV_R {
67        DIV_R::new(((self.bits >> 16) & 0xff) as u8)
68    }
69    #[doc = "Bits 24:27 - SDAH field"]
70    #[inline(always)]
71    pub fn sdah(&self) -> SDAH_R {
72        SDAH_R::new(((self.bits >> 24) & 0x0f) as u8)
73    }
74}
75impl W {
76    #[doc = "Bits 0:7 - SCLL field"]
77    #[inline(always)]
78    pub fn scll(&mut self) -> SCLL_W<0> {
79        SCLL_W::new(self)
80    }
81    #[doc = "Bits 8:15 - SCLH field"]
82    #[inline(always)]
83    pub fn sclh(&mut self) -> SCLH_W<8> {
84        SCLH_W::new(self)
85    }
86    #[doc = "Bits 16:23 - DIV field"]
87    #[inline(always)]
88    pub fn div(&mut self) -> DIV_W<16> {
89        DIV_W::new(self)
90    }
91    #[doc = "Bits 24:27 - SDAH field"]
92    #[inline(always)]
93    pub fn sdah(&mut self) -> SDAH_W<24> {
94        SDAH_W::new(self)
95    }
96    #[doc = "Writes raw bits to the register."]
97    #[inline(always)]
98    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
99        self.0.bits(bits);
100        self
101    }
102}
103#[doc = "CLK register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk](index.html) module"]
104pub struct CLK_SPEC;
105impl crate::RegisterSpec for CLK_SPEC {
106    type Ux = u32;
107}
108#[doc = "`read()` method returns [clk::R](R) reader structure"]
109impl crate::Readable for CLK_SPEC {
110    type Reader = R;
111}
112#[doc = "`write(|w| ..)` method takes [clk::W](W) writer structure"]
113impl crate::Writable for CLK_SPEC {
114    type Writer = W;
115}
116#[doc = "`reset()` method sets CLK to value 0"]
117impl crate::Resettable for CLK_SPEC {
118    #[inline(always)]
119    fn reset_value() -> Self::Ux {
120        0
121    }
122}
swm341_pac/i2c0/clk.rs

swm341_pac/i2c0/
clk.rs
