use crate::svd::{create_bit_range, create_field, create_register, create_register_properties};
use crate::Result;
/// Creates the Low Power Divisor Latch High Register.
pub fn create() -> Result<svd::RegisterCluster> {
Ok(svd::RegisterCluster::Register(
create_register(
"lpdlh",
"Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.",
0x24,
create_register_properties(32, 0)?,
Some(&[
create_field(
"lpdlh",
"This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data",
create_bit_range("[7:0]")?,
svd::Access::ReadWrite,
None,
)?,
]),
None,
)?
))
}